[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrp.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp.h
new file mode 100644
index 0000000..2133cd2
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cph1xrxbrp_93.h"
+#elif defined(__MD95__)
+#include "cph1xrxbrp_93.h"
+#elif defined(__MD97__)
+#include "cph1xrxbrp_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_93.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_93.h
new file mode 100644
index 0000000..39f21bf
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_93.h
@@ -0,0 +1,444 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXBRP_H_
+#define _CPH_1X_RXBRP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_C_1XRTT_REG_BASE (0xAD040000)
+
+#define RXBRP_C_1XRTT_end (RXBRP_C_1XRTT_REG_BASE + 0x0210 + 1*4)
+
+
+
+#define DBRP_RTT_START ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0000))
+#define DBRP_RTT_DONE ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0004))
+#define DBRP_RTT_DONE_VEC ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0008))
+#define DBRP_RTT_CFG_OK ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x000C))
+#define DBRP_RTT_CH_DET ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0010))
+#define DBRP_RTT_SCAL_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0014))
+#define DBRP_RTT_FCH_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0018))
+#define DBRP_RTT_FCH_ET_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x001C))
+#define DBRP_RTT_SYNC_VIT_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0020))
+#define DBRP_RTT_DBG0 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x00D0))
+#define DBRP_RTT_PWR_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x00F0))
+#define DBRP_RTT_FCH_FULL_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0100))
+#define DBRP_RTT_FCH_FULL_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0104))
+#define DBRP_RTT_FCH_FULL_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0108))
+#define DBRP_RTT_FCH_HALF_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x010C))
+#define DBRP_RTT_FCH_HALF_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0110))
+#define DBRP_RTT_FCH_QUAR_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0114))
+#define DBRP_RTT_FCH_QUAR_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0118))
+#define DBRP_RTT_FCH_EIGH_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x011C))
+#define DBRP_RTT_FCH_EIGH_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0120))
+#define DBRP_RTT_SCH_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0124))
+#define DBRP_RTT_SCH_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0128))
+#define DBRP_RTT_SCH_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x012C))
+#define DBRP_RTT_FCH_ET_PCG_CNT ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0200))
+#define DBRP_RTT_FCH_SCALE_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0204))
+#define DBRP_RTT_FCH_SCALE_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0208))
+#define DBRP_RTT_SCH_SCALE_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x020C))
+#define DBRP_RTT_SCH_SCALE_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0210))
+
+
+#define DBRP_RTT_START_BRP_RTT_START_LSB (15)
+#define DBRP_RTT_START_BRP_RTT_START_WIDTH (1)
+#define DBRP_RTT_START_BRP_RTT_START_MASK (0x00008000)
+#define DBRP_RTT_START_BRP_RTT_START_BIT (0x00008000)
+
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_LSB (16)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_WIDTH (1)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_MASK (0x00010000)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_BIT (0x00010000)
+
+#define DBRP_RTT_DONE_RTT_DONE_LSB (0)
+#define DBRP_RTT_DONE_RTT_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_RTT_DONE_MASK (0x00000001)
+#define DBRP_RTT_DONE_RTT_DONE_BIT (0x00000001)
+
+#define DBRP_RTT_DONE_VEC_TUR_DONE_LSB (3)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_MASK (0x00000008)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_BIT (0x00000008)
+
+#define DBRP_RTT_DONE_VEC_VIT_DONE_LSB (2)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_MASK (0x00000004)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_BIT (0x00000004)
+
+#define DBRP_RTT_DONE_VEC_CORR_DONE_LSB (1)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_MASK (0x00000002)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_BIT (0x00000002)
+
+#define DBRP_RTT_DONE_VEC_DRM_DONE_LSB (0)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_MASK (0x00000001)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_BIT (0x00000001)
+
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_LSB (15)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_WIDTH (1)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_MASK (0x00008000)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_BIT (0x00008000)
+
+#define DBRP_RTT_CFG_OK_CFG_OK_LSB (0)
+#define DBRP_RTT_CFG_OK_CFG_OK_WIDTH (1)
+#define DBRP_RTT_CFG_OK_CFG_OK_MASK (0x00000001)
+#define DBRP_RTT_CFG_OK_CFG_OK_BIT (0x00000001)
+
+#define DBRP_RTT_CH_DET_SCH_ENCODING_LSB (2)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_WIDTH (1)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_MASK (0x00000004)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_BIT (0x00000004)
+
+#define DBRP_RTT_CH_DET_SCH_EN_LSB (1)
+#define DBRP_RTT_CH_DET_SCH_EN_WIDTH (1)
+#define DBRP_RTT_CH_DET_SCH_EN_MASK (0x00000002)
+#define DBRP_RTT_CH_DET_SCH_EN_BIT (0x00000002)
+
+#define DBRP_RTT_CH_DET_FCH_EN_LSB (0)
+#define DBRP_RTT_CH_DET_FCH_EN_WIDTH (1)
+#define DBRP_RTT_CH_DET_FCH_EN_MASK (0x00000001)
+#define DBRP_RTT_CH_DET_FCH_EN_BIT (0x00000001)
+
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_LSB (1)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_WIDTH (1)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_MASK (0x00000002)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_BIT (0x00000002)
+
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_LSB (0)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_WIDTH (1)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_MASK (0x00000001)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_BIT (0x00000001)
+
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_LSB (18)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_MASK (0x00040000)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_BIT (0x00040000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_LSB (17)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_MASK (0x00020000)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_BIT (0x00020000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_LSB (16)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_MASK (0x00010000)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_LSB (12)
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_MASK (0x0000F000)
+
+#define DBRP_RTT_FCH_CFG_CH_SEL_LSB (0)
+#define DBRP_RTT_FCH_CFG_CH_SEL_WIDTH (2)
+#define DBRP_RTT_FCH_CFG_CH_SEL_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_LSB (31)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_WIDTH (1)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_MASK (0x80000000)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_BIT (0x80000000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_LSB (24)
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_MASK (0x0F000000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_LSB (20)
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_MASK (0x00F00000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_LSB (16)
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_MASK (0x000F0000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_LSB (0)
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_WIDTH (16)
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_MASK (0x0000FFFF)
+
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_LSB (0)
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_MASK (0x0000000F)
+
+#define DBRP_RTT_DBG0_DRM_FSM_CS_LSB (24)
+#define DBRP_RTT_DBG0_DRM_FSM_CS_WIDTH (5)
+#define DBRP_RTT_DBG0_DRM_FSM_CS_MASK (0x1F000000)
+
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_LSB (20)
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_WIDTH (3)
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_MASK (0x00700000)
+
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_LSB (12)
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_WIDTH (5)
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_MASK (0x0001F000)
+
+#define DBRP_RTT_DBG0_TOP_FSM_CS_LSB (0)
+#define DBRP_RTT_DBG0_TOP_FSM_CS_WIDTH (9)
+#define DBRP_RTT_DBG0_TOP_FSM_CS_MASK (0x000001FF)
+
+#define DBRP_RTT_PWR_CFG_PWR_MODE_LSB (15)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_WIDTH (1)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_MASK (0x00008000)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_BIT (0x00008000)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_LSB (27)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_WIDTH (1)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_MASK (0x08000000)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_BIT (0x08000000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_LSB (20)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_WIDTH (7)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_MASK (0x07F00000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_LSB (16)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_WIDTH (2)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_MASK (0x00030000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_LSB (27)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_WIDTH (1)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_MASK (0x08000000)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_BIT (0x08000000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_LSB (20)
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_WIDTH (7)
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_MASK (0x07F00000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_LSB (16)
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_WIDTH (2)
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_MASK (0x00030000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_SCH_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_SCH_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_SCH_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_LSB (0)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_MASK (0x0000000F)
+
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (17)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x0001FFFF)
+
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (21)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x001FFFFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+
+#endif //#ifndef _CPH_1X_RXBRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_97.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_97.h
new file mode 100644
index 0000000..aad994f
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrp_97.h
@@ -0,0 +1,444 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXBRP_H_
+#define _CPH_1X_RXBRP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_C_1XRTT_REG_BASE (0xAC840000)
+
+#define RXBRP_C_1XRTT_end (RXBRP_C_1XRTT_REG_BASE + 0x0210 + 1*4)
+
+
+
+#define DBRP_RTT_START ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0000))
+#define DBRP_RTT_DONE ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0004))
+#define DBRP_RTT_DONE_VEC ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0008))
+#define DBRP_RTT_CFG_OK ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x000C))
+#define DBRP_RTT_CH_DET ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0010))
+#define DBRP_RTT_SCAL_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0014))
+#define DBRP_RTT_FCH_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0018))
+#define DBRP_RTT_FCH_ET_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x001C))
+#define DBRP_RTT_SYNC_VIT_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0020))
+#define DBRP_RTT_DBG0 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x00D0))
+#define DBRP_RTT_PWR_CFG ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x00F0))
+#define DBRP_RTT_FCH_FULL_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0100))
+#define DBRP_RTT_FCH_FULL_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0104))
+#define DBRP_RTT_FCH_FULL_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0108))
+#define DBRP_RTT_FCH_HALF_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x010C))
+#define DBRP_RTT_FCH_HALF_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0110))
+#define DBRP_RTT_FCH_QUAR_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0114))
+#define DBRP_RTT_FCH_QUAR_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0118))
+#define DBRP_RTT_FCH_EIGH_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x011C))
+#define DBRP_RTT_FCH_EIGH_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0120))
+#define DBRP_RTT_SCH_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0124))
+#define DBRP_RTT_SCH_PARAM2 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0128))
+#define DBRP_RTT_SCH_PARAM3 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x012C))
+#define DBRP_RTT_FCH_ET_PCG_CNT ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0200))
+#define DBRP_RTT_FCH_SCALE_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0204))
+#define DBRP_RTT_FCH_SCALE_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0208))
+#define DBRP_RTT_SCH_SCALE_PARAM ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x020C))
+#define DBRP_RTT_SCH_SCALE_PARAM1 ((APBADDR32)(RXBRP_C_1XRTT_REG_BASE + 0x0210))
+
+
+#define DBRP_RTT_START_BRP_RTT_START_LSB (15)
+#define DBRP_RTT_START_BRP_RTT_START_WIDTH (1)
+#define DBRP_RTT_START_BRP_RTT_START_MASK (0x00008000)
+#define DBRP_RTT_START_BRP_RTT_START_BIT (0x00008000)
+
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_LSB (16)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_WIDTH (1)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_MASK (0x00010000)
+#define DBRP_RTT_DONE_RTT_SW_IRQ_TRIG_BIT (0x00010000)
+
+#define DBRP_RTT_DONE_RTT_DONE_LSB (0)
+#define DBRP_RTT_DONE_RTT_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_RTT_DONE_MASK (0x00000001)
+#define DBRP_RTT_DONE_RTT_DONE_BIT (0x00000001)
+
+#define DBRP_RTT_DONE_VEC_TUR_DONE_LSB (3)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_MASK (0x00000008)
+#define DBRP_RTT_DONE_VEC_TUR_DONE_BIT (0x00000008)
+
+#define DBRP_RTT_DONE_VEC_VIT_DONE_LSB (2)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_MASK (0x00000004)
+#define DBRP_RTT_DONE_VEC_VIT_DONE_BIT (0x00000004)
+
+#define DBRP_RTT_DONE_VEC_CORR_DONE_LSB (1)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_MASK (0x00000002)
+#define DBRP_RTT_DONE_VEC_CORR_DONE_BIT (0x00000002)
+
+#define DBRP_RTT_DONE_VEC_DRM_DONE_LSB (0)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_WIDTH (1)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_MASK (0x00000001)
+#define DBRP_RTT_DONE_VEC_DRM_DONE_BIT (0x00000001)
+
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_LSB (15)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_WIDTH (1)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_MASK (0x00008000)
+#define DBRP_RTT_CFG_OK_CFG_ASSERT_BIT (0x00008000)
+
+#define DBRP_RTT_CFG_OK_CFG_OK_LSB (0)
+#define DBRP_RTT_CFG_OK_CFG_OK_WIDTH (1)
+#define DBRP_RTT_CFG_OK_CFG_OK_MASK (0x00000001)
+#define DBRP_RTT_CFG_OK_CFG_OK_BIT (0x00000001)
+
+#define DBRP_RTT_CH_DET_SCH_ENCODING_LSB (2)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_WIDTH (1)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_MASK (0x00000004)
+#define DBRP_RTT_CH_DET_SCH_ENCODING_BIT (0x00000004)
+
+#define DBRP_RTT_CH_DET_SCH_EN_LSB (1)
+#define DBRP_RTT_CH_DET_SCH_EN_WIDTH (1)
+#define DBRP_RTT_CH_DET_SCH_EN_MASK (0x00000002)
+#define DBRP_RTT_CH_DET_SCH_EN_BIT (0x00000002)
+
+#define DBRP_RTT_CH_DET_FCH_EN_LSB (0)
+#define DBRP_RTT_CH_DET_FCH_EN_WIDTH (1)
+#define DBRP_RTT_CH_DET_FCH_EN_MASK (0x00000001)
+#define DBRP_RTT_CH_DET_FCH_EN_BIT (0x00000001)
+
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_LSB (1)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_WIDTH (1)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_MASK (0x00000002)
+#define DBRP_RTT_SCAL_CFG_DEREAP_SCAL_MODE_BIT (0x00000002)
+
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_LSB (0)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_WIDTH (1)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_MASK (0x00000001)
+#define DBRP_RTT_SCAL_CFG_SCAL_MODE_BIT (0x00000001)
+
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_LSB (18)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_MASK (0x00040000)
+#define DBRP_RTT_FCH_CFG_SYNC_VIT_EN_BIT (0x00040000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_LSB (17)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_MASK (0x00020000)
+#define DBRP_RTT_FCH_CFG_SYNC_CORR_EN_BIT (0x00020000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_LSB (16)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_WIDTH (1)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_MASK (0x00010000)
+#define DBRP_RTT_FCH_CFG_SYNC_DRM_EN_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_LSB (12)
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_FCH_CFG_SYNC_BUF_IDX_MASK (0x0000F000)
+
+#define DBRP_RTT_FCH_CFG_CH_SEL_LSB (0)
+#define DBRP_RTT_FCH_CFG_CH_SEL_WIDTH (2)
+#define DBRP_RTT_FCH_CFG_CH_SEL_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_LSB (31)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_WIDTH (1)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_MASK (0x80000000)
+#define DBRP_RTT_FCH_ET_PARAM_ET_EN_BIT (0x80000000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_LSB (24)
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_FULL_PCG_MASK (0x0F000000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_LSB (20)
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_HALF_PCG_MASK (0x00F00000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_LSB (16)
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PARAM_ET_QUAR_PCG_MASK (0x000F0000)
+
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_LSB (0)
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_WIDTH (16)
+#define DBRP_RTT_FCH_ET_PARAM_ET_PCG_MAP_MASK (0x0000FFFF)
+
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_LSB (0)
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_SYNC_VIT_PARAM_SYNC_START_BUF_IDX_MASK (0x0000000F)
+
+#define DBRP_RTT_DBG0_DRM_FSM_CS_LSB (24)
+#define DBRP_RTT_DBG0_DRM_FSM_CS_WIDTH (5)
+#define DBRP_RTT_DBG0_DRM_FSM_CS_MASK (0x1F000000)
+
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_LSB (20)
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_WIDTH (3)
+#define DBRP_RTT_DBG0_DET_CHNL_ITER_MASK (0x00700000)
+
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_LSB (12)
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_WIDTH (5)
+#define DBRP_RTT_DBG0_MAIN_FSM_CS_MASK (0x0001F000)
+
+#define DBRP_RTT_DBG0_TOP_FSM_CS_LSB (0)
+#define DBRP_RTT_DBG0_TOP_FSM_CS_WIDTH (9)
+#define DBRP_RTT_DBG0_TOP_FSM_CS_MASK (0x000001FF)
+
+#define DBRP_RTT_PWR_CFG_PWR_MODE_LSB (15)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_WIDTH (1)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_MASK (0x00008000)
+#define DBRP_RTT_PWR_CFG_PWR_MODE_BIT (0x00008000)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_LSB (27)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_WIDTH (1)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_MASK (0x08000000)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_FB_EN_BIT (0x08000000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_LSB (20)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_WIDTH (7)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_J_M1_MASK (0x07F00000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_LSB (16)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_WIDTH (2)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_M_MASK (0x00030000)
+
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_RTT_FCH_FULL_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_FULL_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_FULL_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_FULL_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_FULL_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_FULL_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_FULL_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_HALF_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_HALF_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_HALF_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_HALF_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_HALF_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_HALF_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_QUAR_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_QUAR_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_QUAR_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_QUAR_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_QUAR_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_FCH_EIGH_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_FCH_EIGH_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_FCH_EIGH_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_FCH_EIGH_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_FCH_EIGH_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_LSB (27)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_WIDTH (1)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_MASK (0x08000000)
+#define DBRP_RTT_SCH_PARAM1_INTLV_FB_EN_BIT (0x08000000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_LSB (20)
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_WIDTH (7)
+#define DBRP_RTT_SCH_PARAM1_INTLV_J_M1_MASK (0x07F00000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_LSB (16)
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_WIDTH (2)
+#define DBRP_RTT_SCH_PARAM1_INTLV_M_MASK (0x00030000)
+
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_RTT_SCH_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_LSB (17)
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_WIDTH (15)
+#define DBRP_RTT_SCH_PARAM2_ENCODED_BITS_MASK (0xFFFE0000)
+
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_LSB (5)
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_WIDTH (12)
+#define DBRP_RTT_SCH_PARAM2_PUNC_PATTERN_MASK (0x0001FFE0)
+
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_LSB (2)
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_WIDTH (3)
+#define DBRP_RTT_SCH_PARAM2_PUNC_CFG_MASK (0x0000001C)
+
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_WIDTH (2)
+#define DBRP_RTT_SCH_PARAM2_REPEAT_RATE_MASK (0x00000003)
+
+#define DBRP_RTT_SCH_PARAM3_SETPT_LSB (17)
+#define DBRP_RTT_SCH_PARAM3_SETPT_WIDTH (7)
+#define DBRP_RTT_SCH_PARAM3_SETPT_MASK (0x00FE0000)
+
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_LSB (16)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_WIDTH (1)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_MASK (0x00010000)
+#define DBRP_RTT_SCH_PARAM3_CODE_RATE_BIT (0x00010000)
+
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_LSB (13)
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_WIDTH (3)
+#define DBRP_RTT_SCH_PARAM3_CRC_SIZE_MASK (0x0000E000)
+
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_LSB (0)
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_WIDTH (13)
+#define DBRP_RTT_SCH_PARAM3_CODE_BLOCK_SIZE_MASK (0x00001FFF)
+
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_LSB (0)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_MASK (0x0000000F)
+
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (17)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x0001FFFF)
+
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (21)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x001FFFFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+
+#endif //#ifndef _CPH_1X_RXBRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser.h
new file mode 100644
index 0000000..b8fa30c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser.h
@@ -0,0 +1,45 @@
+
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cph1xrxbrpcorrser_93.h"
+#elif defined(__MD95__)
+#include "cph1xrxbrpcorrser_93.h"
+#elif defined(__MD97__)
+#include "cph1xrxbrpcorrser_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_93.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_93.h
new file mode 100644
index 0000000..9c2cccf
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_93.h
@@ -0,0 +1,224 @@
+
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXBRP_CORRSER_H_
+#define _CPH_1X_RXBRP_CORRSER_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_C_CORR_SER_REG_BASE (0xAD050000)
+
+#define RXBRP_C_CORR_SER_end (RXBRP_C_CORR_SER_REG_BASE + 0x007C + 1*4)
+
+
+
+#define DBRP_RTT_CORR_BUF_IDX ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0000))
+#define DBRP_RTT_CORR_ENERGY ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0004))
+#define DBRP_RTT_CORR_RSLT0 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0008))
+#define DBRP_RTT_CORR_RSLT1 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x000C))
+#define DBRP_RTT_CORR_RSLT2 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0010))
+#define DBRP_RTT_CORR_RSLT3 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0014))
+#define DBRP_RTT_CORR_RSLT4 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0018))
+#define DBRP_RTT_CORR_RSLT5 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x001C))
+#define DBRP_RTT_CORR_RSLT6 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0020))
+#define DBRP_RTT_CORR_RSLT7 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0024))
+#define DBRP_RTT_CORR_RSLT8 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0028))
+#define DBRP_RTT_CORR_RSLT9 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x002C))
+#define DBRP_RTT_CORR_RSLT10 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0030))
+#define DBRP_RTT_CORR_RSLT11 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0034))
+#define DBRP_RTT_CORR_RSLT12 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0038))
+#define DBRP_RTT_CORR_RSLT13 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x003C))
+#define DBRP_RTT_CORR_RSLT14 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0040))
+#define DBRP_RTT_CORR_RSLT15 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0044))
+#define DBRP_RTT_CORR_RSLT_EXTRA ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0048))
+#define DBRP_RTT_CORR_FULL_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x004C))
+#define DBRP_RTT_CORR_HALF_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0050))
+#define DBRP_RTT_CORR_QUAR_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0054))
+#define DBRP_RTT_CORR_EIGH_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0058))
+#define DBRP_RTT_CORR_FULL_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x005C))
+#define DBRP_RTT_CORR_HALF_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0060))
+#define DBRP_RTT_CORR_QUAR_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0064))
+#define DBRP_RTT_CORR_EIGH_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0068))
+#define DBRP_RTT_CORR_PATTERN_EXTRA ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x006C))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0070))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0074))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0078))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x007C))
+
+
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_LSB (0)
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_MASK (0x0000000F)
+
+#define DBRP_RTT_CORR_ENERGY_ENERGY_LSB (0)
+#define DBRP_RTT_CORR_ENERGY_ENERGY_WIDTH (9)
+#define DBRP_RTT_CORR_ENERGY_ENERGY_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_LSB (6)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_WIDTH (1)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_MASK (0x00000040)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_BIT (0x00000040)
+
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_LSB (0)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_WIDTH (6)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_MASK (0x0000003F)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+
+#endif //#ifndef _CPH_1X_RXBRP_CORRSER_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_97.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_97.h
new file mode 100644
index 0000000..70ae320
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpcorrser_97.h
@@ -0,0 +1,229 @@
+
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXBRP_CORRSER_H_
+#define _CPH_1X_RXBRP_CORRSER_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_C_CORR_SER_REG_BASE (0xAC850000)
+
+#define RXBRP_C_CORR_SER_end (RXBRP_C_CORR_SER_REG_BASE + 0x007C + 1*4)
+
+
+
+#define DBRP_RTT_CORR_BUF_IDX ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0000))
+#define DBRP_RTT_CORR_ENERGY ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0004))
+#define DBRP_RTT_CORR_RSLT0 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0008))
+#define DBRP_RTT_CORR_RSLT1 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x000C))
+#define DBRP_RTT_CORR_RSLT2 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0010))
+#define DBRP_RTT_CORR_RSLT3 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0014))
+#define DBRP_RTT_CORR_RSLT4 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0018))
+#define DBRP_RTT_CORR_RSLT5 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x001C))
+#define DBRP_RTT_CORR_RSLT6 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0020))
+#define DBRP_RTT_CORR_RSLT7 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0024))
+#define DBRP_RTT_CORR_RSLT8 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0028))
+#define DBRP_RTT_CORR_RSLT9 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x002C))
+#define DBRP_RTT_CORR_RSLT10 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0030))
+#define DBRP_RTT_CORR_RSLT11 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0034))
+#define DBRP_RTT_CORR_RSLT12 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0038))
+#define DBRP_RTT_CORR_RSLT13 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x003C))
+#define DBRP_RTT_CORR_RSLT14 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0040))
+#define DBRP_RTT_CORR_RSLT15 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0044))
+#define DBRP_RTT_CORR_RSLT16 ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0048))
+#define DBRP_RTT_CORR_RSLT_EXTRA ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x004C))
+#define DBRP_RTT_CORR_FULL_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0050))
+#define DBRP_RTT_CORR_HALF_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0054))
+#define DBRP_RTT_CORR_QUAR_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0058))
+#define DBRP_RTT_CORR_EIGH_SER ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x005C))
+#define DBRP_RTT_CORR_FULL_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0060))
+#define DBRP_RTT_CORR_HALF_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0064))
+#define DBRP_RTT_CORR_QUAR_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0068))
+#define DBRP_RTT_CORR_EIGH_BEST_PM ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x006C))
+#define DBRP_RTT_CORR_PATTERN_EXTRA ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0070))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0074))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0078))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x007C))
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH ((APBADDR32)(RXBRP_C_CORR_SER_REG_BASE + 0x0080))
+
+
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_LSB (0)
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_WIDTH (4)
+#define DBRP_RTT_CORR_BUF_IDX_SYN_BUF_IDX_MASK (0x0000000F)
+
+#define DBRP_RTT_CORR_ENERGY_ENERGY_LSB (0)
+#define DBRP_RTT_CORR_ENERGY_ENERGY_WIDTH (9)
+#define DBRP_RTT_CORR_ENERGY_ENERGY_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT0_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT1_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT2_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT3_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT4_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT5_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT6_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT7_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT8_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT9_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT10_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT11_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT12_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT13_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT14_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT15_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT16_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT16_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT16_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_LSB (0)
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_WIDTH (9)
+#define DBRP_RTT_CORR_RSLT_EXTRA_CORR_RSLT_MASK (0x000001FF)
+
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_FULL_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_HALF_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_QUAR_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_LSB (0)
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_WIDTH (11)
+#define DBRP_RTT_CORR_EIGH_SER_SER_RSLT_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_FULL_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_HALF_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_QUAR_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_LSB (0)
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_WIDTH (15)
+#define DBRP_RTT_CORR_EIGH_BEST_PM_BEST_PM_MASK (0x00007FFF)
+
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_LSB (6)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_WIDTH (1)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_MASK (0x00000040)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_CORR_EXTRA_ENABLE_BIT (0x00000040)
+
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_LSB (0)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_WIDTH (6)
+#define DBRP_RTT_CORR_PATTERN_EXTRA_MSG_LENGTH_MASK (0x0000003F)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_FULL_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_HALF_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_QUAR_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_LSB (0)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_WIDTH (11)
+#define DBRP_RTT_CORR_VALID_SYMBOL_NUM_EIGH_VALID_SYMBOL_NUM_MASK (0x000007FF)
+
+
+#endif //#ifndef _CPH_1X_RXBRP_CORRSER_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpdma.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpdma.h
new file mode 100644
index 0000000..7ef6a48
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpdma.h
@@ -0,0 +1,84 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXBRP_DMA_H_
+#define _CPH_1X_RXBRP_DMA_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_C_1XRTT_DMA_REG_BASE (0x00000000)
+
+#define RXBRP_C_1XRTT_DMA_end (RXBRP_C_1XRTT_DMA_REG_BASE + 0x0010 + 1*4)
+
+
+
+#define DBRP_RTT_FCH_ET_PCG_CNT_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0000))
+#define DBRP_RTT_FCH_SCALE_PARAM_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0004))
+#define DBRP_RTT_FCH_SCALE_PARAM1_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0008))
+#define DBRP_RTT_SCH_SCALE_PARAM_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x000C))
+#define DBRP_RTT_SCH_SCALE_PARAM1_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0010))
+
+
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_LSB (0)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_WIDTH (4)
+#define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_MASK (0x0000000F)
+
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (17)
+#define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x0001FFFF)
+
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (21)
+#define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x001FFFFF)
+
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15)
+#define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF)
+
+
+#endif //#ifndef _CPH_1X_RXBRP_DMA_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma.h
new file mode 100644
index 0000000..7e377b3
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cph1xrxbrpwctdma_93.h"
+#elif defined(__MD95__)
+#include "cph1xrxbrpwctdma_93.h"
+#elif defined(__MD97__)
+#include "cph1xrxbrpwctdma_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_93.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_93.h
new file mode 100644
index 0000000..bbc358c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_93.h
@@ -0,0 +1,510 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RX_BRP_WCT_DMA_H_
+#define _CPH_1X_RX_BRP_WCT_DMA_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCT_DMA_REG_BASE (0xAD150000)
+
+#define RXBRP_WCT_DMA_end (RXBRP_WCT_DMA_REG_BASE + 0x00B4 + 1*4)
+
+
+
+#define DBRP_DMA_RESET ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0000))
+#define DBRP_DMA_CH0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0004))
+#define DBRP_DMA_CH0_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0008))
+#define DBRP_DMA_CH0_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x000C))
+#define DBRP_DMA_CH0_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0010))
+#define DBRP_DMA_CH0_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0014))
+#define DBRP_DMA_CH0_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0018))
+#define DBRP_DMA_CH1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x001C))
+#define DBRP_DMA_CH1_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0020))
+#define DBRP_DMA_CH1_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0024))
+#define DBRP_DMA_CH1_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0028))
+#define DBRP_DMA_CH1_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x002C))
+#define DBRP_DMA_CH1_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0030))
+#define DBRP_DMA_CH2 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0034))
+#define DBRP_DMA_CH2_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0038))
+#define DBRP_DMA_CH2_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x003C))
+#define DBRP_DMA_CH2_CTRL_CNFG_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0040))
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0044))
+#define DBRP_DMA_CH2_CTRL_CNFG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0048))
+#define DBRP_DMA_CH2_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x004C))
+#define DBRP_DMA_CH2_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0050))
+#define DBRP_DMA_CH2_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0054))
+#define DBRP_DMA_CH3 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0058))
+#define DBRP_DMA_CH3_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x005C))
+#define DBRP_DMA_CH3_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0060))
+#define DBRP_DMA_CH3_CTRL_CNFG_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0064))
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0068))
+#define DBRP_DMA_CH3_CTRL_CNFG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x006C))
+#define DBRP_DMA_CH3_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0070))
+#define DBRP_DMA_CH3_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0074))
+#define DBRP_DMA_CH3_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0078))
+#define DBRP_DMA_CH4 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x007C))
+#define DBRP_DMA_CH4_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0080))
+#define DBRP_DMA_CH4_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0084))
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0088))
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x008C))
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0090))
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0094))
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0098))
+#define DBRP_DMA_CH4_CTRL_DATA_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x009C))
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A0))
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A4))
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A8))
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00AC))
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00B0))
+#define DBRP_DMA_CH4_CTRL_DATA_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00B4))
+
+#define DBRP_DMA_DEBUG_START ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00E0))
+
+
+#define DBRP_DMA_RESET_SW_RESET_LSB (0)
+#define DBRP_DMA_RESET_SW_RESET_WIDTH (1)
+#define DBRP_DMA_RESET_SW_RESET_MASK (0x00000001)
+#define DBRP_DMA_RESET_SW_RESET_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_TRIG_LSB (0)
+#define DBRP_DMA_CH0_TRIG_WIDTH (1)
+#define DBRP_DMA_CH0_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH0_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH0_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH0_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH0_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH0_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH0_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH0_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH0_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH0_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH0_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH0_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_TRIG_LSB (0)
+#define DBRP_DMA_CH1_TRIG_WIDTH (1)
+#define DBRP_DMA_CH1_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH1_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH1_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH1_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH1_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH1_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH1_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH1_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH1_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH1_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH1_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH1_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_TRIG_LSB (0)
+#define DBRP_DMA_CH2_TRIG_WIDTH (1)
+#define DBRP_DMA_CH2_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH2_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH2_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH2_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH2_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH2_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH2_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH2_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH2_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH2_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH2_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_TRIG_LSB (0)
+#define DBRP_DMA_CH3_TRIG_WIDTH (1)
+#define DBRP_DMA_CH3_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH3_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH3_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH3_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH3_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH3_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH3_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH3_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH3_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH3_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH3_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_TRIG_LSB (0)
+#define DBRP_DMA_CH4_TRIG_WIDTH (1)
+#define DBRP_DMA_CH4_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH4_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_LSB (3)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_MASK (0x00000008)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_BIT (0x00000008)
+
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_LSB (2)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_MASK (0x00000004)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_BIT (0x00000004)
+
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_LSB (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_LSB (0)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_LSB (20)
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_MASK (0x00F00000)
+
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_MASK (0x000F0000)
+
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_LSB (9)
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_MASK (0x0000FE00)
+
+#define DBRP_DMA_CH4_CTRL_CC_EN_LSB (7)
+#define DBRP_DMA_CH4_CTRL_CC_EN_WIDTH (2)
+#define DBRP_DMA_CH4_CTRL_CC_EN_MASK (0x00000180)
+
+#define DBRP_DMA_CH4_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH4_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH4_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH4_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH4_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH4_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH4_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH4_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH4_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_MASK (0x0000FFFF)
+
+
+#endif //#ifndef _CPH_1X_RX_BRP_WCT_DMA_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_97.h b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_97.h
new file mode 100644
index 0000000..b6e8774
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxbrpwctdma_97.h
@@ -0,0 +1,510 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RX_BRP_WCT_DMA_H_
+#define _CPH_1X_RX_BRP_WCT_DMA_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCT_DMA_REG_BASE (0xAC950000)
+
+#define RXBRP_WCT_DMA_end (RXBRP_WCT_DMA_REG_BASE + 0x00B4 + 1*4)
+
+
+
+#define DBRP_DMA_RESET ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0000))
+#define DBRP_DMA_CH0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0004))
+#define DBRP_DMA_CH0_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0008))
+#define DBRP_DMA_CH0_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x000C))
+#define DBRP_DMA_CH0_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0010))
+#define DBRP_DMA_CH0_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0014))
+#define DBRP_DMA_CH0_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0018))
+#define DBRP_DMA_CH1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x001C))
+#define DBRP_DMA_CH1_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0020))
+#define DBRP_DMA_CH1_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0024))
+#define DBRP_DMA_CH1_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0028))
+#define DBRP_DMA_CH1_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x002C))
+#define DBRP_DMA_CH1_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0030))
+#define DBRP_DMA_CH2 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0034))
+#define DBRP_DMA_CH2_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0038))
+#define DBRP_DMA_CH2_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x003C))
+#define DBRP_DMA_CH2_CTRL_CNFG_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0040))
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0044))
+#define DBRP_DMA_CH2_CTRL_CNFG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0048))
+#define DBRP_DMA_CH2_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x004C))
+#define DBRP_DMA_CH2_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0050))
+#define DBRP_DMA_CH2_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0054))
+#define DBRP_DMA_CH3 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0058))
+#define DBRP_DMA_CH3_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x005C))
+#define DBRP_DMA_CH3_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0060))
+#define DBRP_DMA_CH3_CTRL_CNFG_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0064))
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0068))
+#define DBRP_DMA_CH3_CTRL_CNFG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x006C))
+#define DBRP_DMA_CH3_CTRL_DATA_PING ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0070))
+#define DBRP_DMA_CH3_CTRL_DATA_PONG ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0074))
+#define DBRP_DMA_CH3_CTRL_DATA ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0078))
+#define DBRP_DMA_CH4 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x007C))
+#define DBRP_DMA_CH4_REQ ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0080))
+#define DBRP_DMA_CH4_CTRL ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0084))
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0088))
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x008C))
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0090))
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0094))
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x0098))
+#define DBRP_DMA_CH4_CTRL_DATA_CC0 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x009C))
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A0))
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A4))
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00A8))
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00AC))
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00B0))
+#define DBRP_DMA_CH4_CTRL_DATA_CC1 ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00B4))
+
+#define DBRP_DMA_DEBUG_START ((APBADDR32)(RXBRP_WCT_DMA_REG_BASE + 0x00E0))
+
+
+#define DBRP_DMA_RESET_SW_RESET_LSB (0)
+#define DBRP_DMA_RESET_SW_RESET_WIDTH (1)
+#define DBRP_DMA_RESET_SW_RESET_MASK (0x00000001)
+#define DBRP_DMA_RESET_SW_RESET_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_TRIG_LSB (0)
+#define DBRP_DMA_CH0_TRIG_WIDTH (1)
+#define DBRP_DMA_CH0_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH0_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH0_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH0_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH0_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH0_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH0_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH0_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH0_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH0_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH0_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH0_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH0_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH0_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH0_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH0_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH0_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_TRIG_LSB (0)
+#define DBRP_DMA_CH1_TRIG_WIDTH (1)
+#define DBRP_DMA_CH1_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH1_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH1_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH1_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH1_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH1_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH1_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH1_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH1_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH1_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH1_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH1_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH1_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH1_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH1_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH1_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH1_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_TRIG_LSB (0)
+#define DBRP_DMA_CH2_TRIG_WIDTH (1)
+#define DBRP_DMA_CH2_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH2_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH2_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH2_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH2_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH2_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH2_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH2_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH2_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH2_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH2_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH2_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH2_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH2_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH2_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_LSB (0)
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_CNFG_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH2_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_TRIG_LSB (0)
+#define DBRP_DMA_CH3_TRIG_WIDTH (1)
+#define DBRP_DMA_CH3_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH3_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_LSB (1)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH3_REQ_DATA_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_LSB (0)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH3_REQ_CNFG_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_LSB (14)
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH3_CTRL_BUF_IDX_MASK (0x0003C000)
+
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_LSB (7)
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH3_CTRL_ACC_IDX_MASK (0x00003F80)
+
+#define DBRP_DMA_CH3_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH3_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH3_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH3_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH3_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH3_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH3_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH3_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH3_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_LSB (0)
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_CNFG_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PING_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_PONG_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_LSB (0)
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH3_CTRL_DATA_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_TRIG_LSB (0)
+#define DBRP_DMA_CH4_TRIG_WIDTH (1)
+#define DBRP_DMA_CH4_TRIG_MASK (0x00000001)
+#define DBRP_DMA_CH4_TRIG_BIT (0x00000001)
+
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_LSB (3)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_MASK (0x00000008)
+#define DBRP_DMA_CH4_REQ_DATA_CC1_PING_SEL_BIT (0x00000008)
+
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_LSB (2)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_MASK (0x00000004)
+#define DBRP_DMA_CH4_REQ_CNFG_CC1_PING_SEL_BIT (0x00000004)
+
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_LSB (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_MASK (0x00000002)
+#define DBRP_DMA_CH4_REQ_DATA_CC0_PING_SEL_BIT (0x00000002)
+
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_LSB (0)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_WIDTH (1)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_MASK (0x00000001)
+#define DBRP_DMA_CH4_REQ_CNFG_CC0_PING_SEL_BIT (0x00000001)
+
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_LSB (20)
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH4_CTRL_CC1_BUF_IDX_MASK (0x00F00000)
+
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_WIDTH (4)
+#define DBRP_DMA_CH4_CTRL_CC0_BUF_IDX_MASK (0x000F0000)
+
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_LSB (9)
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_WIDTH (7)
+#define DBRP_DMA_CH4_CTRL_ACC_IDX_MASK (0x0000FE00)
+
+#define DBRP_DMA_CH4_CTRL_CC_EN_LSB (7)
+#define DBRP_DMA_CH4_CTRL_CC_EN_WIDTH (2)
+#define DBRP_DMA_CH4_CTRL_CC_EN_MASK (0x00000180)
+
+#define DBRP_DMA_CH4_CTRL_PRIORITY_LSB (4)
+#define DBRP_DMA_CH4_CTRL_PRIORITY_WIDTH (3)
+#define DBRP_DMA_CH4_CTRL_PRIORITY_MASK (0x00000070)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_LSB (3)
+#define DBRP_DMA_CH4_CTRL_CNFG_WIDTH (1)
+#define DBRP_DMA_CH4_CTRL_CNFG_MASK (0x00000008)
+#define DBRP_DMA_CH4_CTRL_CNFG_BIT (0x00000008)
+
+#define DBRP_DMA_CH4_CTRL_MODE_LSB (0)
+#define DBRP_DMA_CH4_CTRL_MODE_WIDTH (3)
+#define DBRP_DMA_CH4_CTRL_MODE_MASK (0x00000007)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC0_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC0_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_CC0_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PING_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_PONG_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_CNFG_CC1_LENGTH_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PING_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_LSB (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_START_SAMPLE_IDX_MASK (0xFFFF0000)
+
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_PONG_CC1_BASE_ADDR_IDX_MASK (0x0000FFFF)
+
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_LSB (0)
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_WIDTH (16)
+#define DBRP_DMA_CH4_CTRL_DATA_CC1_LENGTH_MASK (0x0000FFFF)
+
+
+#endif //#ifndef _CPH_1X_RX_BRP_WCT_DMA_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen.h b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen.h
new file mode 100644
index 0000000..e25af1d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cph1xrxeventgen_g93.h"
+#elif defined(__MD95__)
+#include "cph1xrxeventgen_g95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cph1xrxeventgen_g97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g93.h b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g93.h
new file mode 100644
index 0000000..4e90e88
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g93.h
@@ -0,0 +1,586 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RX_EVENTGEN_H_
+#define _CPH_1X_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define ST1X_RX_EVENTGEN_REG_BASE (0xA7060000)
+
+#define ST1X_RX_EVENTGEN_end (ST1X_RX_EVENTGEN_REG_BASE + 0x3000 + 38*4)
+
+
+#define ST1X_RXBRP_EVENT_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0000))
+#define ST1X_RXBRP_EVENT_MASK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0004))
+#define ST1X_uSIP_IRQ_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0008))
+#define ST1X_uSIP_IRQ_MASK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x000C))
+#define ST1X_uSIP_IRQ_CLR ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0010))
+#define ST1X_uSIP_IRQ_SRC ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0014))
+#define ST1X_uSIP_IRQ_ISR ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0018))
+#define ST1X_RXDFE_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x001C))
+#define ST1X_RXDFE_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0020))
+#define ST1X_DBG_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0024))
+#define ST1X_DBG_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0028))
+#define ST1X_TTR_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x002C))
+#define ST1X_TTR_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0030))
+#define ST1X_DVFS_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0034))
+#define ST1X_RX_BSIRD_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0F30 + (n)*4)) //n is from 0 to 2
+#define ST1X_RX_BSI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x1030 + (n)*4)) //n is from 0 to 49
+#define ST1X_RX_MIPI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x2000 + (n)*4)) //n is from 0 to 81
+#define ST1X_RX_BPI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x3000 + (n)*4)) //n is from 0 to 37
+
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define ST1X_uSIP_IRQ_MASK_MSK15_LSB (15)
+#define ST1X_uSIP_IRQ_MASK_MSK15_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_MASK_MSK15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK14_LSB (14)
+#define ST1X_uSIP_IRQ_MASK_MSK14_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_MASK_MSK14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK13_LSB (13)
+#define ST1X_uSIP_IRQ_MASK_MSK13_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_MASK_MSK13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK12_LSB (12)
+#define ST1X_uSIP_IRQ_MASK_MSK12_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_MASK_MSK12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK11_LSB (11)
+#define ST1X_uSIP_IRQ_MASK_MSK11_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_MASK_MSK11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_MASK_MSK10_LSB (10)
+#define ST1X_uSIP_IRQ_MASK_MSK10_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_MASK_MSK10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_MASK_MSK9_LSB (9)
+#define ST1X_uSIP_IRQ_MASK_MSK9_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_MASK_MSK9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_MASK_MSK8_LSB (8)
+#define ST1X_uSIP_IRQ_MASK_MSK8_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_MASK_MSK8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_MASK_MSK7_LSB (7)
+#define ST1X_uSIP_IRQ_MASK_MSK7_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_MASK_MSK7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_MASK_MSK6_LSB (6)
+#define ST1X_uSIP_IRQ_MASK_MSK6_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_MASK_MSK6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_MASK_MSK5_LSB (5)
+#define ST1X_uSIP_IRQ_MASK_MSK5_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_MASK_MSK5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_MASK_MSK4_LSB (4)
+#define ST1X_uSIP_IRQ_MASK_MSK4_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_MASK_MSK4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_MASK_MSK3_LSB (3)
+#define ST1X_uSIP_IRQ_MASK_MSK3_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_MASK_MSK3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_MASK_MSK2_LSB (2)
+#define ST1X_uSIP_IRQ_MASK_MSK2_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_MASK_MSK2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_MASK_MSK1_LSB (1)
+#define ST1X_uSIP_IRQ_MASK_MSK1_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_MASK_MSK1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_MASK_MSK0_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_MSK0_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_MASK_MSK0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_CLR_CLR15_LSB (15)
+#define ST1X_uSIP_IRQ_CLR_CLR15_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_CLR_CLR15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR14_LSB (14)
+#define ST1X_uSIP_IRQ_CLR_CLR14_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_CLR_CLR14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR13_LSB (13)
+#define ST1X_uSIP_IRQ_CLR_CLR13_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_CLR_CLR13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR12_LSB (12)
+#define ST1X_uSIP_IRQ_CLR_CLR12_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_CLR_CLR12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR11_LSB (11)
+#define ST1X_uSIP_IRQ_CLR_CLR11_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_CLR_CLR11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_CLR_CLR10_LSB (10)
+#define ST1X_uSIP_IRQ_CLR_CLR10_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_CLR_CLR10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_CLR_CLR9_LSB (9)
+#define ST1X_uSIP_IRQ_CLR_CLR9_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_CLR_CLR9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_CLR_CLR8_LSB (8)
+#define ST1X_uSIP_IRQ_CLR_CLR8_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_CLR_CLR8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_CLR_CLR7_LSB (7)
+#define ST1X_uSIP_IRQ_CLR_CLR7_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_CLR_CLR7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_CLR_CLR6_LSB (6)
+#define ST1X_uSIP_IRQ_CLR_CLR6_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_CLR_CLR6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_CLR_CLR5_LSB (5)
+#define ST1X_uSIP_IRQ_CLR_CLR5_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_CLR_CLR5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_CLR_CLR4_LSB (4)
+#define ST1X_uSIP_IRQ_CLR_CLR4_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_CLR_CLR4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_CLR_CLR3_LSB (3)
+#define ST1X_uSIP_IRQ_CLR_CLR3_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_CLR_CLR3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_CLR_CLR2_LSB (2)
+#define ST1X_uSIP_IRQ_CLR_CLR2_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_CLR_CLR2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_CLR_CLR1_LSB (1)
+#define ST1X_uSIP_IRQ_CLR_CLR1_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_CLR_CLR1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_CLR_CLR0_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_CLR0_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_CLR_CLR0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_SRC_SRC15_LSB (15)
+#define ST1X_uSIP_IRQ_SRC_SRC15_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_SRC_SRC15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC14_LSB (14)
+#define ST1X_uSIP_IRQ_SRC_SRC14_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_SRC_SRC14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC13_LSB (13)
+#define ST1X_uSIP_IRQ_SRC_SRC13_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_SRC_SRC13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC12_LSB (12)
+#define ST1X_uSIP_IRQ_SRC_SRC12_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_SRC_SRC12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC11_LSB (11)
+#define ST1X_uSIP_IRQ_SRC_SRC11_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_SRC_SRC11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_SRC_SRC10_LSB (10)
+#define ST1X_uSIP_IRQ_SRC_SRC10_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_SRC_SRC10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_SRC_SRC9_LSB (9)
+#define ST1X_uSIP_IRQ_SRC_SRC9_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_SRC_SRC9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_SRC_SRC8_LSB (8)
+#define ST1X_uSIP_IRQ_SRC_SRC8_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_SRC_SRC8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_SRC_SRC7_LSB (7)
+#define ST1X_uSIP_IRQ_SRC_SRC7_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_SRC_SRC7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_SRC_SRC6_LSB (6)
+#define ST1X_uSIP_IRQ_SRC_SRC6_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_SRC_SRC6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_SRC_SRC5_LSB (5)
+#define ST1X_uSIP_IRQ_SRC_SRC5_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_SRC_SRC5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_SRC_SRC4_LSB (4)
+#define ST1X_uSIP_IRQ_SRC_SRC4_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_SRC_SRC4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_SRC_SRC3_LSB (3)
+#define ST1X_uSIP_IRQ_SRC_SRC3_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_SRC_SRC3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_SRC_SRC2_LSB (2)
+#define ST1X_uSIP_IRQ_SRC_SRC2_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_SRC_SRC2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_SRC_SRC1_LSB (1)
+#define ST1X_uSIP_IRQ_SRC_SRC1_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_SRC_SRC1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_SRC_SRC0_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_SRC0_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_SRC_SRC0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_ISR_ISR15_LSB (15)
+#define ST1X_uSIP_IRQ_ISR_ISR15_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_ISR_ISR15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR14_LSB (14)
+#define ST1X_uSIP_IRQ_ISR_ISR14_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_ISR_ISR14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR13_LSB (13)
+#define ST1X_uSIP_IRQ_ISR_ISR13_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_ISR_ISR13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR12_LSB (12)
+#define ST1X_uSIP_IRQ_ISR_ISR12_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_ISR_ISR12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR11_LSB (11)
+#define ST1X_uSIP_IRQ_ISR_ISR11_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_ISR_ISR11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_ISR_ISR10_LSB (10)
+#define ST1X_uSIP_IRQ_ISR_ISR10_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_ISR_ISR10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_ISR_ISR9_LSB (9)
+#define ST1X_uSIP_IRQ_ISR_ISR9_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_ISR_ISR9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_ISR_ISR8_LSB (8)
+#define ST1X_uSIP_IRQ_ISR_ISR8_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_ISR_ISR8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_ISR_ISR7_LSB (7)
+#define ST1X_uSIP_IRQ_ISR_ISR7_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_ISR_ISR7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_ISR_ISR6_LSB (6)
+#define ST1X_uSIP_IRQ_ISR_ISR6_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_ISR_ISR6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_ISR_ISR5_LSB (5)
+#define ST1X_uSIP_IRQ_ISR_ISR5_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_ISR_ISR5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_ISR_ISR4_LSB (4)
+#define ST1X_uSIP_IRQ_ISR_ISR4_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_ISR_ISR4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_ISR_ISR3_LSB (3)
+#define ST1X_uSIP_IRQ_ISR_ISR3_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_ISR_ISR3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_ISR_ISR2_LSB (2)
+#define ST1X_uSIP_IRQ_ISR_ISR2_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_ISR_ISR2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_ISR_ISR1_LSB (1)
+#define ST1X_uSIP_IRQ_ISR_ISR1_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_ISR_ISR1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_ISR_ISR0_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_ISR0_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_ISR_ISR0_BIT (0x00000001)
+
+#define ST1X_RXDFE_ON_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RXDFE_OFF_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DBG_ON_EVENT_EN_LSB (31)
+#define ST1X_DBG_ON_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_DBG_OFF_EVENT_EN_LSB (31)
+#define ST1X_DBG_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_TTR_ON_EVENT_EN_LSB (31)
+#define ST1X_TTR_ON_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_TTR_OFF_EVENT_EN_LSB (31)
+#define ST1X_TTR_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DVFS_EVENT_EN_LSB (31)
+#define ST1X_DVFS_EVENT_EN_WIDTH (1)
+#define ST1X_DVFS_EVENT_EN_MASK (0x80000000)
+#define ST1X_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DVFS_EVENT_MODE_LSB (30)
+#define ST1X_DVFS_EVENT_MODE_WIDTH (1)
+#define ST1X_DVFS_EVENT_MODE_MASK (0x40000000)
+#define ST1X_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BSIRD_EVENT_EN_LSB (31)
+#define ST1X_RX_BSIRD_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BSIRD_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BSIRD_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_LSB (2)
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BSI_EVENT_EN_LSB (31)
+#define ST1X_RX_BSI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BSI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BSI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_LSB (2)
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_MIPI_EVENT_EN_LSB (31)
+#define ST1X_RX_MIPI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_MIPI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_MIPI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_LSB (2)
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BPI_EVENT_EN_LSB (31)
+#define ST1X_RX_BPI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BPI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BPI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_LSB (2)
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_WIDTH (18)
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_MASK (0x000FFFFC)
+
+#endif //#ifndef _CPH_1X_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g95.h b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g95.h
new file mode 100644
index 0000000..4356073
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g95.h
@@ -0,0 +1,586 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RX_EVENTGEN_H_
+#define _CPH_1X_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define ST1X_RX_EVENTGEN_REG_BASE (0xA6210000)
+
+#define ST1X_RX_EVENTGEN_end (ST1X_RX_EVENTGEN_REG_BASE + 0x3000 + 38*4)
+
+
+#define ST1X_RXBRP_EVENT_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0000))
+#define ST1X_RXBRP_EVENT_MASK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0004))
+#define ST1X_uSIP_IRQ_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0008))
+#define ST1X_uSIP_IRQ_MASK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x000C))
+#define ST1X_uSIP_IRQ_CLR ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0010))
+#define ST1X_uSIP_IRQ_SRC ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0014))
+#define ST1X_uSIP_IRQ_ISR ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0018))
+#define ST1X_RXDFE_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x001C))
+#define ST1X_RXDFE_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0020))
+#define ST1X_DBG_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0024))
+#define ST1X_DBG_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0028))
+#define ST1X_TTR_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x002C))
+#define ST1X_TTR_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0030))
+#define ST1X_DVFS_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0034))
+#define ST1X_RX_BSIRD_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0F30 + (n)*4)) //n is from 0 to 2
+#define ST1X_RX_BSI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x1030 + (n)*4)) //n is from 0 to 49
+#define ST1X_RX_MIPI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x2000 + (n)*4)) //n is from 0 to 81
+#define ST1X_RX_BPI_EVENT(n) ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x3000 + (n)*4)) //n is from 0 to 37
+
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define ST1X_uSIP_IRQ_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define ST1X_uSIP_IRQ_MASK_MSK15_LSB (15)
+#define ST1X_uSIP_IRQ_MASK_MSK15_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_MASK_MSK15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK14_LSB (14)
+#define ST1X_uSIP_IRQ_MASK_MSK14_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_MASK_MSK14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK13_LSB (13)
+#define ST1X_uSIP_IRQ_MASK_MSK13_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_MASK_MSK13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK12_LSB (12)
+#define ST1X_uSIP_IRQ_MASK_MSK12_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_MASK_MSK12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_MASK_MSK11_LSB (11)
+#define ST1X_uSIP_IRQ_MASK_MSK11_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_MASK_MSK11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_MASK_MSK10_LSB (10)
+#define ST1X_uSIP_IRQ_MASK_MSK10_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_MASK_MSK10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_MASK_MSK9_LSB (9)
+#define ST1X_uSIP_IRQ_MASK_MSK9_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_MASK_MSK9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_MASK_MSK8_LSB (8)
+#define ST1X_uSIP_IRQ_MASK_MSK8_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_MASK_MSK8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_MASK_MSK7_LSB (7)
+#define ST1X_uSIP_IRQ_MASK_MSK7_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_MASK_MSK7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_MASK_MSK6_LSB (6)
+#define ST1X_uSIP_IRQ_MASK_MSK6_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_MASK_MSK6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_MASK_MSK5_LSB (5)
+#define ST1X_uSIP_IRQ_MASK_MSK5_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_MASK_MSK5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_MASK_MSK4_LSB (4)
+#define ST1X_uSIP_IRQ_MASK_MSK4_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_MASK_MSK4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_MASK_MSK3_LSB (3)
+#define ST1X_uSIP_IRQ_MASK_MSK3_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_MASK_MSK3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_MASK_MSK2_LSB (2)
+#define ST1X_uSIP_IRQ_MASK_MSK2_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_MASK_MSK2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_MASK_MSK1_LSB (1)
+#define ST1X_uSIP_IRQ_MASK_MSK1_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_MASK_MSK1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_MASK_MSK0_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_MSK0_WIDTH (1)
+#define ST1X_uSIP_IRQ_MASK_MSK0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_MASK_MSK0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_CLR_CLR15_LSB (15)
+#define ST1X_uSIP_IRQ_CLR_CLR15_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_CLR_CLR15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR14_LSB (14)
+#define ST1X_uSIP_IRQ_CLR_CLR14_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_CLR_CLR14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR13_LSB (13)
+#define ST1X_uSIP_IRQ_CLR_CLR13_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_CLR_CLR13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR12_LSB (12)
+#define ST1X_uSIP_IRQ_CLR_CLR12_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_CLR_CLR12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_CLR_CLR11_LSB (11)
+#define ST1X_uSIP_IRQ_CLR_CLR11_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_CLR_CLR11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_CLR_CLR10_LSB (10)
+#define ST1X_uSIP_IRQ_CLR_CLR10_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_CLR_CLR10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_CLR_CLR9_LSB (9)
+#define ST1X_uSIP_IRQ_CLR_CLR9_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_CLR_CLR9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_CLR_CLR8_LSB (8)
+#define ST1X_uSIP_IRQ_CLR_CLR8_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_CLR_CLR8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_CLR_CLR7_LSB (7)
+#define ST1X_uSIP_IRQ_CLR_CLR7_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_CLR_CLR7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_CLR_CLR6_LSB (6)
+#define ST1X_uSIP_IRQ_CLR_CLR6_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_CLR_CLR6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_CLR_CLR5_LSB (5)
+#define ST1X_uSIP_IRQ_CLR_CLR5_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_CLR_CLR5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_CLR_CLR4_LSB (4)
+#define ST1X_uSIP_IRQ_CLR_CLR4_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_CLR_CLR4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_CLR_CLR3_LSB (3)
+#define ST1X_uSIP_IRQ_CLR_CLR3_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_CLR_CLR3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_CLR_CLR2_LSB (2)
+#define ST1X_uSIP_IRQ_CLR_CLR2_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_CLR_CLR2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_CLR_CLR1_LSB (1)
+#define ST1X_uSIP_IRQ_CLR_CLR1_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_CLR_CLR1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_CLR_CLR0_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_CLR0_WIDTH (1)
+#define ST1X_uSIP_IRQ_CLR_CLR0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_CLR_CLR0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_SRC_SRC15_LSB (15)
+#define ST1X_uSIP_IRQ_SRC_SRC15_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_SRC_SRC15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC14_LSB (14)
+#define ST1X_uSIP_IRQ_SRC_SRC14_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_SRC_SRC14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC13_LSB (13)
+#define ST1X_uSIP_IRQ_SRC_SRC13_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_SRC_SRC13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC12_LSB (12)
+#define ST1X_uSIP_IRQ_SRC_SRC12_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_SRC_SRC12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_SRC_SRC11_LSB (11)
+#define ST1X_uSIP_IRQ_SRC_SRC11_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_SRC_SRC11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_SRC_SRC10_LSB (10)
+#define ST1X_uSIP_IRQ_SRC_SRC10_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_SRC_SRC10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_SRC_SRC9_LSB (9)
+#define ST1X_uSIP_IRQ_SRC_SRC9_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_SRC_SRC9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_SRC_SRC8_LSB (8)
+#define ST1X_uSIP_IRQ_SRC_SRC8_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_SRC_SRC8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_SRC_SRC7_LSB (7)
+#define ST1X_uSIP_IRQ_SRC_SRC7_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_SRC_SRC7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_SRC_SRC6_LSB (6)
+#define ST1X_uSIP_IRQ_SRC_SRC6_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_SRC_SRC6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_SRC_SRC5_LSB (5)
+#define ST1X_uSIP_IRQ_SRC_SRC5_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_SRC_SRC5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_SRC_SRC4_LSB (4)
+#define ST1X_uSIP_IRQ_SRC_SRC4_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_SRC_SRC4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_SRC_SRC3_LSB (3)
+#define ST1X_uSIP_IRQ_SRC_SRC3_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_SRC_SRC3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_SRC_SRC2_LSB (2)
+#define ST1X_uSIP_IRQ_SRC_SRC2_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_SRC_SRC2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_SRC_SRC1_LSB (1)
+#define ST1X_uSIP_IRQ_SRC_SRC1_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_SRC_SRC1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_SRC_SRC0_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_SRC0_WIDTH (1)
+#define ST1X_uSIP_IRQ_SRC_SRC0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_SRC_SRC0_BIT (0x00000001)
+
+#define ST1X_uSIP_IRQ_ISR_ISR15_LSB (15)
+#define ST1X_uSIP_IRQ_ISR_ISR15_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR15_MASK (0x00008000)
+#define ST1X_uSIP_IRQ_ISR_ISR15_BIT (0x00008000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR14_LSB (14)
+#define ST1X_uSIP_IRQ_ISR_ISR14_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR14_MASK (0x00004000)
+#define ST1X_uSIP_IRQ_ISR_ISR14_BIT (0x00004000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR13_LSB (13)
+#define ST1X_uSIP_IRQ_ISR_ISR13_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR13_MASK (0x00002000)
+#define ST1X_uSIP_IRQ_ISR_ISR13_BIT (0x00002000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR12_LSB (12)
+#define ST1X_uSIP_IRQ_ISR_ISR12_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR12_MASK (0x00001000)
+#define ST1X_uSIP_IRQ_ISR_ISR12_BIT (0x00001000)
+
+#define ST1X_uSIP_IRQ_ISR_ISR11_LSB (11)
+#define ST1X_uSIP_IRQ_ISR_ISR11_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR11_MASK (0x00000800)
+#define ST1X_uSIP_IRQ_ISR_ISR11_BIT (0x00000800)
+
+#define ST1X_uSIP_IRQ_ISR_ISR10_LSB (10)
+#define ST1X_uSIP_IRQ_ISR_ISR10_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR10_MASK (0x00000400)
+#define ST1X_uSIP_IRQ_ISR_ISR10_BIT (0x00000400)
+
+#define ST1X_uSIP_IRQ_ISR_ISR9_LSB (9)
+#define ST1X_uSIP_IRQ_ISR_ISR9_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR9_MASK (0x00000200)
+#define ST1X_uSIP_IRQ_ISR_ISR9_BIT (0x00000200)
+
+#define ST1X_uSIP_IRQ_ISR_ISR8_LSB (8)
+#define ST1X_uSIP_IRQ_ISR_ISR8_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR8_MASK (0x00000100)
+#define ST1X_uSIP_IRQ_ISR_ISR8_BIT (0x00000100)
+
+#define ST1X_uSIP_IRQ_ISR_ISR7_LSB (7)
+#define ST1X_uSIP_IRQ_ISR_ISR7_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR7_MASK (0x00000080)
+#define ST1X_uSIP_IRQ_ISR_ISR7_BIT (0x00000080)
+
+#define ST1X_uSIP_IRQ_ISR_ISR6_LSB (6)
+#define ST1X_uSIP_IRQ_ISR_ISR6_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR6_MASK (0x00000040)
+#define ST1X_uSIP_IRQ_ISR_ISR6_BIT (0x00000040)
+
+#define ST1X_uSIP_IRQ_ISR_ISR5_LSB (5)
+#define ST1X_uSIP_IRQ_ISR_ISR5_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR5_MASK (0x00000020)
+#define ST1X_uSIP_IRQ_ISR_ISR5_BIT (0x00000020)
+
+#define ST1X_uSIP_IRQ_ISR_ISR4_LSB (4)
+#define ST1X_uSIP_IRQ_ISR_ISR4_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR4_MASK (0x00000010)
+#define ST1X_uSIP_IRQ_ISR_ISR4_BIT (0x00000010)
+
+#define ST1X_uSIP_IRQ_ISR_ISR3_LSB (3)
+#define ST1X_uSIP_IRQ_ISR_ISR3_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR3_MASK (0x00000008)
+#define ST1X_uSIP_IRQ_ISR_ISR3_BIT (0x00000008)
+
+#define ST1X_uSIP_IRQ_ISR_ISR2_LSB (2)
+#define ST1X_uSIP_IRQ_ISR_ISR2_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR2_MASK (0x00000004)
+#define ST1X_uSIP_IRQ_ISR_ISR2_BIT (0x00000004)
+
+#define ST1X_uSIP_IRQ_ISR_ISR1_LSB (1)
+#define ST1X_uSIP_IRQ_ISR_ISR1_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR1_MASK (0x00000002)
+#define ST1X_uSIP_IRQ_ISR_ISR1_BIT (0x00000002)
+
+#define ST1X_uSIP_IRQ_ISR_ISR0_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_ISR0_WIDTH (1)
+#define ST1X_uSIP_IRQ_ISR_ISR0_MASK (0x00000001)
+#define ST1X_uSIP_IRQ_ISR_ISR0_BIT (0x00000001)
+
+#define ST1X_RXDFE_ON_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RXDFE_OFF_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DBG_ON_EVENT_EN_LSB (31)
+#define ST1X_DBG_ON_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_DBG_OFF_EVENT_EN_LSB (31)
+#define ST1X_DBG_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_TTR_ON_EVENT_EN_LSB (31)
+#define ST1X_TTR_ON_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_TTR_OFF_EVENT_EN_LSB (31)
+#define ST1X_TTR_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DVFS_EVENT_EN_LSB (31)
+#define ST1X_DVFS_EVENT_EN_WIDTH (1)
+#define ST1X_DVFS_EVENT_EN_MASK (0x80000000)
+#define ST1X_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DVFS_EVENT_MODE_LSB (30)
+#define ST1X_DVFS_EVENT_MODE_WIDTH (1)
+#define ST1X_DVFS_EVENT_MODE_MASK (0x40000000)
+#define ST1X_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BSIRD_EVENT_EN_LSB (31)
+#define ST1X_RX_BSIRD_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BSIRD_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BSIRD_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_LSB (2)
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BSI_EVENT_EN_LSB (31)
+#define ST1X_RX_BSI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BSI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BSI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_LSB (2)
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_BSI_EVENT_RX_BSI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_MIPI_EVENT_EN_LSB (31)
+#define ST1X_RX_MIPI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_MIPI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_MIPI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_LSB (2)
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_WIDTH (18)
+#define ST1X_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RX_BPI_EVENT_EN_LSB (31)
+#define ST1X_RX_BPI_EVENT_EN_WIDTH (1)
+#define ST1X_RX_BPI_EVENT_EN_MASK (0x80000000)
+#define ST1X_RX_BPI_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_LSB (2)
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_WIDTH (18)
+#define ST1X_RX_BPI_EVENT_RX_BPI_EVENT_TIME_MASK (0x000FFFFC)
+
+#endif //#ifndef _CPH_1X_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g97.h b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g97.h
new file mode 100644
index 0000000..1fa948f
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxeventgen_g97.h
@@ -0,0 +1,421 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RX_EVENTGEN_H_
+#define _CPH_1X_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define ST1X_RX_EVENTGEN_REG_BASE (0xA8200000)
+
+#define ST1X_RX_EVENTGEN_end (ST1X_RX_EVENTGEN_REG_BASE + 0x3000 + 38*4)
+
+
+#define ST1X_RXBRP_EVENT_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0000))
+#define ST1X_RXBRP_EVENT_MASK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0004))
+
+#define ST1X_RXDFE_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x001C))
+#define ST1X_RXDFE_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0020))
+#define ST1X_DBG_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0024))
+#define ST1X_DBG_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0028))
+#define ST1X_TTR_ON_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x002C))
+#define ST1X_TTR_OFF_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0030))
+#define ST1X_DVFS_EVENT ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0034))
+
+#define ST1X_WDG_EN ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0040))
+#define ST1X_WDG_BOUND_OFFSET ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0044))
+#define ST1X_WDG_CHKPT_UNCHK ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0048))
+#define ST1X_WDG_CHKPT_TIME_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x004C))
+#define ST1X_WDG_URGENT_SW_CLR ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0060))
+#define ST1X_WDG_DBG ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0064))
+
+#define ST1X_uSIP_IRQ_OFFSET_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0080))
+#define ST1X_uSIP_IRQ_MASK_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0084))
+#define ST1X_uSIP_IRQ_CLR_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0088))
+#define ST1X_uSIP_IRQ_SRC_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x008C))
+#define ST1X_uSIP_IRQ_ISR_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0090))
+#define ST1X_uSIP_IRQ_LATCH_TIME_0 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0094))
+
+#define ST1X_uSIP_IRQ_OFFSET_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00A0))
+#define ST1X_uSIP_IRQ_MASK_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00A4))
+#define ST1X_uSIP_IRQ_CLR_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00A8))
+#define ST1X_uSIP_IRQ_SRC_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00AC))
+#define ST1X_uSIP_IRQ_ISR_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00B0))
+#define ST1X_uSIP_IRQ_LATCH_TIME_1 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00B4))
+
+#define ST1X_uSIP_IRQ_OFFSET_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00C0))
+#define ST1X_uSIP_IRQ_MASK_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00C4))
+#define ST1X_uSIP_IRQ_CLR_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00C8))
+#define ST1X_uSIP_IRQ_SRC_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00CC))
+#define ST1X_uSIP_IRQ_ISR_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00D0))
+#define ST1X_uSIP_IRQ_LATCH_TIME_2 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00D4))
+
+#define ST1X_uSIP_IRQ_OFFSET_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00E0))
+#define ST1X_uSIP_IRQ_MASK_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00E4))
+#define ST1X_uSIP_IRQ_CLR_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00E8))
+#define ST1X_uSIP_IRQ_SRC_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00EC))
+#define ST1X_uSIP_IRQ_ISR_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00F0))
+#define ST1X_uSIP_IRQ_LATCH_TIME_3 ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x00F4))
+
+#define ST1X_uSIP_IRQ_STATUS ((APBADDR32)(ST1X_RX_EVENTGEN_REG_BASE + 0x0100))
+
+
+
+
+
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define ST1X_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define ST1X_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define ST1X_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define ST1X_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define ST1X_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define ST1X_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define ST1X_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define ST1X_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define ST1X_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define ST1X_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define ST1X_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define ST1X_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define ST1X_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define ST1X_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define ST1X_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define ST1X_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define ST1X_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define ST1X_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+
+#define ST1X_RXDFE_ON_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_RXDFE_OFF_EVENT_EN_LSB (31)
+#define ST1X_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DBG_ON_EVENT_EN_LSB (31)
+#define ST1X_DBG_ON_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_DBG_OFF_EVENT_EN_LSB (31)
+#define ST1X_DBG_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define ST1X_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define ST1X_TTR_ON_EVENT_EN_LSB (31)
+#define ST1X_TTR_ON_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_TTR_OFF_EVENT_EN_LSB (31)
+#define ST1X_TTR_OFF_EVENT_EN_WIDTH (1)
+#define ST1X_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define ST1X_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define ST1X_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_DVFS_EVENT_EN_LSB (31)
+#define ST1X_DVFS_EVENT_EN_WIDTH (1)
+#define ST1X_DVFS_EVENT_EN_MASK (0x80000000)
+#define ST1X_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define ST1X_DVFS_EVENT_MODE_LSB (30)
+#define ST1X_DVFS_EVENT_MODE_WIDTH (1)
+#define ST1X_DVFS_EVENT_MODE_MASK (0x40000000)
+#define ST1X_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define ST1X_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define ST1X_WDG_EN_WDG_EN_LSB (0)
+#define ST1X_WDG_EN_WDG_EN_WIDTH (1)
+#define ST1X_WDG_EN_WDG_EN_MASK (0x00000001)
+
+#define ST1X_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_LSB (3)
+#define ST1X_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_WIDTH (11)
+#define ST1X_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_MASK (0x00003FF8)
+
+#define ST1X_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_LSB (0)
+#define ST1X_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_WIDTH (1)
+#define ST1X_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_MASK (0x00000001)
+
+
+#define ST1X_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_LSB (3)
+#define ST1X_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_WIDTH (17)
+#define ST1X_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_MASK (0x0000FFF8)
+
+#define ST1X_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_LSB (3)
+#define ST1X_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_WIDTH (6)
+#define ST1X_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_MASK (0x000001F8)
+
+#define ST1X_uSIP_IRQ_MASK_0_MSK0_23_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_0_MSK0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_MASK_0_MSK0_23__MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_CLR_0_CLR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_0_CLR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_CLR_0_CLR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_SRC_0_SRC0_23_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_0_SRC0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_SRC_0_SRC0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_ISR_0_ISR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_0_ISR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_ISR_0_ISR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_ERROR_FLAG_LSB (31)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_ERROR_FLAG_MASK (0x80000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_CLEAR_ERROR_FLAG_LSB (30)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_CLEAR_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_CLEAR_ERROR_FLAG_MASK (0x40000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_S_TIME_LSB (9)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_S_TIME_WIDTH (11)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_S_TIME_MASK (0x00FFFFE0)
+
+#define ST1X_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_LSB (3)
+#define ST1X_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_WIDTH (6)
+#define ST1X_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_MASK (0x000001F8)
+
+#define ST1X_uSIP_IRQ_MASK_1_MSK0_23_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_1_MSK0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_MASK_1_MSK0_23__MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_CLR_1_CLR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_1_CLR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_CLR_1_CLR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_SRC_1_SRC0_23_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_1_SRC0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_SRC_0_SRC0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_ISR_1_ISR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_1_ISR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_ISR_1_ISR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_ERROR_FLAG_LSB (31)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_ERROR_FLAG_MASK (0x80000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_CLEAR_ERROR_FLAG_LSB (30)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_CLEAR_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_CLEAR_ERROR_FLAG_MASK (0x40000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_S_TIME_LSB (9)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_S_TIME_WIDTH (11)
+#define ST1X_uSIP_IRQ_LATCH_TIME_1_S_TIME_MASK (0x00FFFFE0)
+
+#define ST1X_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_LSB (3)
+#define ST1X_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_WIDTH (6)
+#define ST1X_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_MASK (0x000001F8)
+
+#define ST1X_uSIP_IRQ_MASK_2_MSK0_23_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_2_MSK0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_MASK_2_MSK0_23__MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_CLR_2_CLR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_2_CLR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_CLR_2_CLR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_SRC_2_SRC0_23_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_2_SRC0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_SRC_2_SRC0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_ISR_2_ISR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_2_ISR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_ISR_2_ISR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_ERROR_FLAG_LSB (31)
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_ERROR_FLAG_MASK (0x80000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_CLEAR_ERROR_FLAG_LSB (30)
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_CLEAR_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_0_CLEAR_ERROR_FLAG_MASK (0x40000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_S_TIME_LSB (9)
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_S_TIME_WIDTH (11)
+#define ST1X_uSIP_IRQ_LATCH_TIME_2_S_TIME_MASK (0x00FFFFE0)
+
+#define ST1X_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_LSB (3)
+#define ST1X_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_WIDTH (6)
+#define ST1X_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_MASK (0x000001F8)
+
+#define ST1X_uSIP_IRQ_MASK_3_MSK0_23_LSB (0)
+#define ST1X_uSIP_IRQ_MASK_3_MSK0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_MASK_3_MSK0_23__MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_CLR_3_CLR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_CLR_3_CLR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_CLR_3_CLR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_SRC_3_SRC0_23_LSB (0)
+#define ST1X_uSIP_IRQ_SRC_3_SRC0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_SRC_3_SRC0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_ISR_3_ISR0_23_LSB (0)
+#define ST1X_uSIP_IRQ_ISR_3_ISR0_23_WIDTH (24)
+#define ST1X_uSIP_IRQ_ISR_3_ISR0_23_MASK (0x00FFFFFF)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_ERROR_FLAG_LSB (31)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_ERROR_FLAG_MASK (0x80000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_CLEAR_ERROR_FLAG_LSB (30)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_CLEAR_ERROR_FLAG_WIDTH (1)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_CLEAR_ERROR_FLAG_MASK (0x40000000)
+
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_S_TIME_LSB (9)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_S_TIME_WIDTH (11)
+#define ST1X_uSIP_IRQ_LATCH_TIME_3_S_TIME_MASK (0x00FFFFE0)
+
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_0_LSB (0)
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_0_WIDTH (1)
+#define ST1X_uSIP_STATUS_STATUS_IRQ_0_MASK (0x00000001)
+
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_1_LSB (1)
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_1_WIDTH (1)
+#define ST1X_uSIP_STATUS_STATUS_IRQ_1_MASK (0x00000002)
+
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_2_LSB (2)
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_2_WIDTH (1)
+#define ST1X_uSIP_STATUS_STATUS_IRQ_2_MASK (0x00000004)
+
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_3_LSB (1)
+#define ST1X_uSIP_IRQ_STATUS_STATUS_IRQ_3_WIDTH (1)
+#define ST1X_uSIP_STATUS_STATUS_IRQ_3_MASK (0x00000008)
+
+#endif //#ifndef _CPH_1X_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xrxslp.h b/mcu/interface/l1/cl1/common/HW/cph1xrxslp.h
new file mode 100644
index 0000000..ec12e35
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xrxslp.h
@@ -0,0 +1,212 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_RXSLP_H_
+#define _CPH_1X_RXSLP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define ST1X_RX_SLP_REG_BASE (0x00000000)
+
+#define ST1X_RX_SLP_end (ST1X_RX_SLP_REG_BASE + 0xA60D0060 + 1*4)
+
+
+
+#define ST1X_SM_CON ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0000))
+#define ST1X_SM_PAUSE_TIME ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0004))
+#define ST1X_SM_STA ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0008))
+#define ST1X_SM_CFG ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D000C))
+#define ST1X_SM_START_TIME ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0010))
+#define ST1X_SM_SW_WAKE_CON ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0014))
+#define ST1X_SM_STEP_FRAC ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0018))
+#define ST1X_SM_SYSCNT_F32K_INT ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D001C))
+#define ST1X_SM_SYSCNT_F32K_FRAC ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0020))
+#define ST1X_SM_SUPFRM_F32K_L ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0024))
+#define ST1X_SM_SUPFRM_F32K_H ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0028))
+#define ST1X_SM_SLEEP_OFFSET ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D002C))
+#define ST1X_SM_TIME_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0030))
+#define ST1X_SM_SUPFRM_TIME_L_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0034))
+#define ST1X_SM_SUPFRM_TIME_H_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0038))
+#define ST1X_SM_TIME_SLTBD ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D003C))
+#define ST1X_SM_SUPFRM_TIME_L_SLTBD ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0040))
+#define ST1X_SM_SUPFRM_TIME_H_SLTBD ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0044))
+#define ST1X_SM_TIME_WAKEUP_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0048))
+#define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D004C))
+#define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0050))
+#define ST1X_SM_FINAL_PAUSE_DURATION ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0054))
+#define ST1X_SM_PRESLP_CNT ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0058))
+#define ST1X_SM_SLT_START_F32K ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D005C))
+#define ST1X_SM_WAKEUP_START_F32K ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0060))
+
+
+#define ST1X_SM_CON_CLR_CNT_LSB (15)
+#define ST1X_SM_CON_CLR_CNT_WIDTH (1)
+#define ST1X_SM_CON_CLR_CNT_MASK (0x00008000)
+#define ST1X_SM_CON_CLR_CNT_BIT (0x00008000)
+
+#define ST1X_SM_CON_PAUSE_START_LSB (1)
+#define ST1X_SM_CON_PAUSE_START_WIDTH (1)
+#define ST1X_SM_CON_PAUSE_START_MASK (0x00000002)
+#define ST1X_SM_CON_PAUSE_START_BIT (0x00000002)
+
+#define ST1X_SM_CON_PAUSE_MODE_LSB (0)
+#define ST1X_SM_CON_PAUSE_MODE_WIDTH (1)
+#define ST1X_SM_CON_PAUSE_MODE_MASK (0x00000001)
+#define ST1X_SM_CON_PAUSE_MODE_BIT (0x00000001)
+
+#define ST1X_SM_PAUSE_TIME_PAUSE_TIME_LSB (0)
+#define ST1X_SM_PAUSE_TIME_PAUSE_TIME_WIDTH (32)
+#define ST1X_SM_PAUSE_TIME_PAUSE_TIME_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_STA_SLP_EXIT_CPL_LSB (7)
+#define ST1X_SM_STA_SLP_EXIT_CPL_WIDTH (1)
+#define ST1X_SM_STA_SLP_EXIT_CPL_MASK (0x00000080)
+#define ST1X_SM_STA_SLP_EXIT_CPL_BIT (0x00000080)
+
+#define ST1X_SM_STA_PAUSE_CPL_LSB (6)
+#define ST1X_SM_STA_PAUSE_CPL_WIDTH (1)
+#define ST1X_SM_STA_PAUSE_CPL_MASK (0x00000040)
+#define ST1X_SM_STA_PAUSE_CPL_BIT (0x00000040)
+
+#define ST1X_SM_CFG_SW_WAKE_EN_LSB (8)
+#define ST1X_SM_CFG_SW_WAKE_EN_WIDTH (1)
+#define ST1X_SM_CFG_SW_WAKE_EN_MASK (0x00000100)
+#define ST1X_SM_CFG_SW_WAKE_EN_BIT (0x00000100)
+
+#define ST1X_SM_CFG_IRQ_EN_LSB (1)
+#define ST1X_SM_CFG_IRQ_EN_WIDTH (1)
+#define ST1X_SM_CFG_IRQ_EN_MASK (0x00000002)
+#define ST1X_SM_CFG_IRQ_EN_BIT (0x00000002)
+
+#define ST1X_SM_START_TIME_SYSTEM_TIME_CNT_LSB (2)
+#define ST1X_SM_START_TIME_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST1X_SM_START_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST1X_SM_SW_WAKE_CON_SW_EVENT_LSB (0)
+#define ST1X_SM_SW_WAKE_CON_SW_EVENT_WIDTH (1)
+#define ST1X_SM_SW_WAKE_CON_SW_EVENT_MASK (0x00000001)
+#define ST1X_SM_SW_WAKE_CON_SW_EVENT_BIT (0x00000001)
+
+#define ST1X_SM_STEP_FRAC_STEP_INT_LSB (18)
+#define ST1X_SM_STEP_FRAC_STEP_INT_WIDTH (9)
+#define ST1X_SM_STEP_FRAC_STEP_INT_MASK (0x07FC0000)
+
+#define ST1X_SM_STEP_FRAC_STEP_FRAC_LSB (0)
+#define ST1X_SM_STEP_FRAC_STEP_FRAC_WIDTH (18)
+#define ST1X_SM_STEP_FRAC_STEP_FRAC_MASK (0x0003FFFF)
+
+#define ST1X_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_LSB (0)
+#define ST1X_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_WIDTH (20)
+#define ST1X_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_MASK (0x000FFFFF)
+
+#define ST1X_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_LSB (0)
+#define ST1X_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_WIDTH (18)
+#define ST1X_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_MASK (0x0003FFFF)
+
+#define ST1X_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_LSB (0)
+#define ST1X_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_WIDTH (32)
+#define ST1X_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_LSB (0)
+#define ST1X_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_WIDTH (4)
+#define ST1X_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_MASK (0x0000000F)
+
+#define ST1X_SM_SLEEP_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST1X_SM_SLEEP_OFFSET_CHIP_OFFSET_WIDTH (14)
+#define ST1X_SM_SLEEP_OFFSET_CHIP_OFFSET_MASK (0x0000FFFC)
+
+#define ST1X_SM_TIME_START_SM_TIME_START_LSB (0)
+#define ST1X_SM_TIME_START_SM_TIME_START_WIDTH (20)
+#define ST1X_SM_TIME_START_SM_TIME_START_MASK (0x000FFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_WIDTH (32)
+#define ST1X_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_WIDTH (4)
+#define ST1X_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_MASK (0x0000000F)
+
+#define ST1X_SM_TIME_SLTBD_SM_TIME_SLTBD_LSB (0)
+#define ST1X_SM_TIME_SLTBD_SM_TIME_SLTBD_WIDTH (20)
+#define ST1X_SM_TIME_SLTBD_SM_TIME_SLTBD_MASK (0x000FFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (32)
+#define ST1X_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (4)
+#define ST1X_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0x0000000F)
+
+#define ST1X_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_LSB (0)
+#define ST1X_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_WIDTH (20)
+#define ST1X_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_MASK (0x000FFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (32)
+#define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (4)
+#define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0x0000000F)
+
+#define ST1X_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_LSB (0)
+#define ST1X_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_WIDTH (32)
+#define ST1X_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_MASK (0xFFFFFFFF)
+
+#define ST1X_SM_PRESLP_CNT_SM_PRESLP_CNT_LSB (0)
+#define ST1X_SM_PRESLP_CNT_SM_PRESLP_CNT_WIDTH (6)
+#define ST1X_SM_PRESLP_CNT_SM_PRESLP_CNT_MASK (0x0000003F)
+
+#define ST1X_SM_SLT_START_F32K_SM_SLT_START_F32K_LSB (0)
+#define ST1X_SM_SLT_START_F32K_SM_SLT_START_F32K_WIDTH (6)
+#define ST1X_SM_SLT_START_F32K_SM_SLT_START_F32K_MASK (0x0000003F)
+
+#define ST1X_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_LSB (0)
+#define ST1X_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_WIDTH (32)
+#define ST1X_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _CPH_1X_RXSLP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xschreg.h b/mcu/interface/l1/cl1/common/HW/cph1xschreg.h
new file mode 100644
index 0000000..a8c8648
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xschreg.h
@@ -0,0 +1,46 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cph1xschreg_93.h"
+#elif defined(__MD95__)
+#include "cph1xschreg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cph1xschreg_97.h"
+
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
+
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xschreg_93.h b/mcu/interface/l1/cl1/common/HW/cph1xschreg_93.h
new file mode 100644
index 0000000..cf3d2f3
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xschreg_93.h
@@ -0,0 +1,529 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_SCH_H_
+#define _CPH_1X_SCH_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define SEARCHER_REG_BASE (0xA7880000)
+
+#define SEARCHER_end (SEARCHER_REG_BASE + 0x0b60 + 1*4)
+
+
+
+#define SR_CTL1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0000))
+#define SR_CORR_LEN ((APBADDR32)(SEARCHER_REG_BASE + 0x0004))
+#define SR_NONCO_PASS ((APBADDR32)(SEARCHER_REG_BASE + 0x0008))
+#define SR_AUX_PLT_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x000C))
+#define SR_WIND ((APBADDR32)(SEARCHER_REG_BASE + 0x0010))
+#define SR_D1_THRES ((APBADDR32)(SEARCHER_REG_BASE + 0x0014))
+#define SR_AUX_OFF_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x0018))
+#define SR_OUTPUT ((APBADDR32)(SEARCHER_REG_BASE + 0x001C))
+#define SR_TST_CTL ((APBADDR32)(SEARCHER_REG_BASE + 0x0020))
+#define SR_TST_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0024))
+#define SR_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0028))
+#define SR_STAT ((APBADDR32)(SEARCHER_REG_BASE + 0x002c))
+#define SR_SMPL_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0030))
+#define SR_THRESH ((APBADDR32)(SEARCHER_REG_BASE + 0x0034))
+#define SR_WIN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0038))
+#define SR_INBUF_TSTCTL ((APBADDR32)(SEARCHER_REG_BASE + 0x003C))
+#define SR_INBUF_TSTDAT ((APBADDR32)(SEARCHER_REG_BASE + 0x0040))
+#define SR_PEAK1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0044))
+#define SR_PEAK2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0048))
+#define SR_PEAK3 ((APBADDR32)(SEARCHER_REG_BASE + 0x004C))
+#define SR_PEAK4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0050))
+#define SR_START_DLY ((APBADDR32)(SEARCHER_REG_BASE + 0x0054))
+#define SR_PN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0058))
+#define SR_PAGE_NUM ((APBADDR32)(SEARCHER_REG_BASE + 0x005C))
+#define SR_DATA_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0060))
+#define SR_IC_DLY_CFG ((APBADDR32)(SEARCHER_REG_BASE + 0x0064))
+#define SR_IC_DLY_CFG1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0068))
+#define SR_WIND_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0110))
+#define SR_PN_OFFSET_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0158))
+#define SR_DATA_CNT_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0160))
+#define SR_WIND_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0210))
+#define SR_PN_OFFSET_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0258))
+#define SR_DATA_CNT_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0260))
+#define SR_WIND_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0310))
+#define SR_PN_OFFSET_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0358))
+#define SR_DATA_CNT_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0360))
+#define SR_WIND_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0410))
+#define SR_PN_OFFSET_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0458))
+#define SR_DATA_CNT_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0460))
+#define SR_WIND_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0510))
+#define SR_PN_OFFSET_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0558))
+#define SR_DATA_CNT_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0560))
+#define SR_WIND_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0610))
+#define SR_PN_OFFSET_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0658))
+#define SR_DATA_CNT_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0660))
+#define SR_WIND_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0710))
+#define SR_PN_OFFSET_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0758))
+#define SR_DATA_CNT_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0760))
+#define SR_WIND_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0810))
+#define SR_PN_OFFSET_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0858))
+#define SR_DATA_CNT_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0860))
+#define SR_WIND_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0910))
+#define SR_PN_OFFSET_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0958))
+#define SR_DATA_CNT_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0960))
+#define SR_WIND_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a10))
+#define SR_PN_OFFSET_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a58))
+#define SR_DATA_CNT_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a60))
+#define SR_WIND_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b10))
+#define SR_PN_OFFSET_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b58))
+#define SR_DATA_CNT_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b60))
+
+
+#define SR_CTL1_OUT_SEL_LSB (16)
+#define SR_CTL1_OUT_SEL_WIDTH (2)
+#define SR_CTL1_OUT_SEL_MASK (0x00030000)
+
+#define SR_CTL1_THRESH_EN_LSB (14)
+#define SR_CTL1_THRESH_EN_WIDTH (1)
+#define SR_CTL1_THRESH_EN_MASK (0x00004000)
+#define SR_CTL1_THRESH_EN_BIT (0x00004000)
+
+#define SR_CTL1_CLR_BUF_CNTRS_LSB (12)
+#define SR_CTL1_CLR_BUF_CNTRS_WIDTH (1)
+#define SR_CTL1_CLR_BUF_CNTRS_MASK (0x00001000)
+#define SR_CTL1_CLR_BUF_CNTRS_BIT (0x00001000)
+
+#define SR_CTL1_TONE_LSB (11)
+#define SR_CTL1_TONE_WIDTH (1)
+#define SR_CTL1_TONE_MASK (0x00000800)
+#define SR_CTL1_TONE_BIT (0x00000800)
+
+#define SR_CTL1_TC_LSB (9)
+#define SR_CTL1_TC_WIDTH (2)
+#define SR_CTL1_TC_MASK (0x00000600)
+
+#define SR_CTL1_AUX_PILOT_EN_LSB (7)
+#define SR_CTL1_AUX_PILOT_EN_WIDTH (1)
+#define SR_CTL1_AUX_PILOT_EN_MASK (0x00000080)
+#define SR_CTL1_AUX_PILOT_EN_BIT (0x00000080)
+
+#define SR_CTL1_COHERENT_LSB (6)
+#define SR_CTL1_COHERENT_WIDTH (1)
+#define SR_CTL1_COHERENT_MASK (0x00000040)
+#define SR_CTL1_COHERENT_BIT (0x00000040)
+
+#define SR_CTL1_FREQ_DOMAIN_LSB (5)
+#define SR_CTL1_FREQ_DOMAIN_WIDTH (1)
+#define SR_CTL1_FREQ_DOMAIN_MASK (0x00000020)
+#define SR_CTL1_FREQ_DOMAIN_BIT (0x00000020)
+
+#define SR_CTL1_LOAD_TWO_BUF_LSB (3)
+#define SR_CTL1_LOAD_TWO_BUF_WIDTH (1)
+#define SR_CTL1_LOAD_TWO_BUF_MASK (0x00000008)
+#define SR_CTL1_LOAD_TWO_BUF_BIT (0x00000008)
+
+#define SR_CTL1_INPUT_BUF_EN_LSB (2)
+#define SR_CTL1_INPUT_BUF_EN_WIDTH (1)
+#define SR_CTL1_INPUT_BUF_EN_MASK (0x00000004)
+#define SR_CTL1_INPUT_BUF_EN_BIT (0x00000004)
+
+#define SR_CTL1_ACQ_MODE_EN_LSB (1)
+#define SR_CTL1_ACQ_MODE_EN_WIDTH (1)
+#define SR_CTL1_ACQ_MODE_EN_MASK (0x00000002)
+#define SR_CTL1_ACQ_MODE_EN_BIT (0x00000002)
+
+#define SR_CTL1_INIT_LSB (0)
+#define SR_CTL1_INIT_WIDTH (1)
+#define SR_CTL1_INIT_MASK (0x00000001)
+#define SR_CTL1_INIT_BIT (0x00000001)
+
+#define SR_CORR_LEN_D2_LSB (6)
+#define SR_CORR_LEN_D2_WIDTH (6)
+#define SR_CORR_LEN_D2_MASK (0x00000FC0)
+
+#define SR_CORR_LEN_D1_LSB (0)
+#define SR_CORR_LEN_D1_WIDTH (6)
+#define SR_CORR_LEN_D1_MASK (0x0000003F)
+
+#define SR_NONCO_PASS_D2MSB_LSB (7)
+#define SR_NONCO_PASS_D2MSB_WIDTH (6)
+#define SR_NONCO_PASS_D2MSB_MASK (0x00001F80)
+
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_LSB (6)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_WIDTH (1)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_MASK (0x00000040)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_BIT (0x00000040)
+
+#define SR_NONCO_PASS_D1LSB_LSB (0)
+#define SR_NONCO_PASS_D1LSB_WIDTH (6)
+#define SR_NONCO_PASS_D1LSB_MASK (0x0000003F)
+
+#define SR_AUX_PLT_WALSH_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_WIND_SIZE_LSB (0)
+#define SR_WIND_SIZE_WIDTH (15)
+#define SR_WIND_SIZE_MASK (0x00007FFF)
+
+#define SR_D1_THRES_CFG_LSB (0)
+#define SR_D1_THRES_CFG_WIDTH (16)
+#define SR_D1_THRES_CFG_MASK (0x0000FFFF)
+
+#define SR_AUX_OFF_WALSH_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_CODE_MASK (0x000001FF)
+
+#define SR_OUTPUT_WIN_OFFSET_LSB (17)
+#define SR_OUTPUT_WIN_OFFSET_WIDTH (9)
+#define SR_OUTPUT_WIN_OFFSET_MASK (0x03FE0000)
+
+#define SR_OUTPUT_E_L_IND_LSB (16)
+#define SR_OUTPUT_E_L_IND_WIDTH (1)
+#define SR_OUTPUT_E_L_IND_MASK (0x00010000)
+#define SR_OUTPUT_E_L_IND_BIT (0x00010000)
+
+#define SR_OUTPUT_METRIC_LSB (0)
+#define SR_OUTPUT_METRIC_WIDTH (16)
+#define SR_OUTPUT_METRIC_MASK (0x0000FFFF)
+
+#define SR_TST_CTL_TST_GO_LSB (4)
+#define SR_TST_CTL_TST_GO_WIDTH (1)
+#define SR_TST_CTL_TST_GO_MASK (0x00000010)
+#define SR_TST_CTL_TST_GO_BIT (0x00000010)
+
+#define SR_TST_CTL_TEST3_LSB (2)
+#define SR_TST_CTL_TEST3_WIDTH (1)
+#define SR_TST_CTL_TEST3_MASK (0x00000004)
+#define SR_TST_CTL_TEST3_BIT (0x00000004)
+
+#define SR_TST_CTL2_OBUF_ADDR_LSB (3)
+#define SR_TST_CTL2_OBUF_ADDR_WIDTH (9)
+#define SR_TST_CTL2_OBUF_ADDR_MASK (0x00000FF8)
+
+#define SR_TST_CTL2_OBF_RPTR_RST_LSB (2)
+#define SR_TST_CTL2_OBF_RPTR_RST_WIDTH (1)
+#define SR_TST_CTL2_OBF_RPTR_RST_MASK (0x00000004)
+#define SR_TST_CTL2_OBF_RPTR_RST_BIT (0x00000004)
+
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_LSB (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_WIDTH (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_MASK (0x00000002)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_BIT (0x00000002)
+
+#define SR_TST_CTL2_TEST_MODE_LSB (0)
+#define SR_TST_CTL2_TEST_MODE_WIDTH (1)
+#define SR_TST_CTL2_TEST_MODE_MASK (0x00000001)
+#define SR_TST_CTL2_TEST_MODE_BIT (0x00000001)
+
+#define SR_CTL2_CLK_ENB_LSB (0)
+#define SR_CTL2_CLK_ENB_WIDTH (1)
+#define SR_CTL2_CLK_ENB_MASK (0x00000001)
+#define SR_CTL2_CLK_ENB_BIT (0x00000001)
+
+#define SR_STAT_DONE_STAT_LSB (2)
+#define SR_STAT_DONE_STAT_WIDTH (1)
+#define SR_STAT_DONE_STAT_MASK (0x00000004)
+#define SR_STAT_DONE_STAT_BIT (0x00000004)
+
+#define SR_STAT_OBF_STAT_LSB (0)
+#define SR_STAT_OBF_STAT_WIDTH (1)
+#define SR_STAT_OBF_STAT_MASK (0x00000001)
+#define SR_STAT_OBF_STAT_BIT (0x00000001)
+
+#define SR_SMPL_CNT_SMPL_CNT_LSB (0)
+#define SR_SMPL_CNT_SMPL_CNT_WIDTH (10)
+#define SR_SMPL_CNT_SMPL_CNT_MASK (0x000003FF)
+
+#define SR_THRESH_OUTPUT_LSB (0)
+#define SR_THRESH_OUTPUT_WIDTH (16)
+#define SR_THRESH_OUTPUT_MASK (0x0000FFFF)
+
+#define SR_WIN_OFFSET_CFG_LSB (1)
+#define SR_WIN_OFFSET_CFG_WIDTH (9)
+#define SR_WIN_OFFSET_CFG_MASK (0x000003FE)
+
+#define SR_WIN_OFFSET_E_L_IND_LSB (0)
+#define SR_WIN_OFFSET_E_L_IND_WIDTH (1)
+#define SR_WIN_OFFSET_E_L_IND_MASK (0x00000001)
+#define SR_WIN_OFFSET_E_L_IND_BIT (0x00000001)
+
+#define SR_INBUF_TSTCTL_TST_EN_LSB (11)
+#define SR_INBUF_TSTCTL_TST_EN_WIDTH (1)
+#define SR_INBUF_TSTCTL_TST_EN_MASK (0x00000800)
+#define SR_INBUF_TSTCTL_TST_EN_BIT (0x00000800)
+
+#define SR_INBUF_TSTCTL_TST_ADDR_LSB (0)
+#define SR_INBUF_TSTCTL_TST_ADDR_WIDTH (11)
+#define SR_INBUF_TSTCTL_TST_ADDR_MASK (0x000007FF)
+
+#define SR_INBUF_TSTDAT_TSTDAT_LSB (0)
+#define SR_INBUF_TSTDAT_TSTDAT_WIDTH (16)
+#define SR_INBUF_TSTDAT_TSTDAT_MASK (0x0000FFFF)
+
+#define SR_PEAK1_WIN_OFFSET_LSB (17)
+#define SR_PEAK1_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK1_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK1_E_L_IND_LSB (16)
+#define SR_PEAK1_E_L_IND_WIDTH (1)
+#define SR_PEAK1_E_L_IND_MASK (0x00010000)
+#define SR_PEAK1_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK1_METRIC_LSB (0)
+#define SR_PEAK1_METRIC_WIDTH (16)
+#define SR_PEAK1_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK2_WIN_OFFSET_LSB (17)
+#define SR_PEAK2_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK2_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK2_E_L_IND_LSB (16)
+#define SR_PEAK2_E_L_IND_WIDTH (1)
+#define SR_PEAK2_E_L_IND_MASK (0x00010000)
+#define SR_PEAK2_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK2_METRIC_LSB (0)
+#define SR_PEAK2_METRIC_WIDTH (16)
+#define SR_PEAK2_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK3_WIN_OFFSET_LSB (17)
+#define SR_PEAK3_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK3_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK3_E_L_IND_LSB (16)
+#define SR_PEAK3_E_L_IND_WIDTH (1)
+#define SR_PEAK3_E_L_IND_MASK (0x00010000)
+#define SR_PEAK3_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK3_METRIC_LSB (0)
+#define SR_PEAK3_METRIC_WIDTH (16)
+#define SR_PEAK3_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK4_WIN_OFFSET_LSB (17)
+#define SR_PEAK4_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK4_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK4_E_L_IND_LSB (16)
+#define SR_PEAK4_E_L_IND_WIDTH (1)
+#define SR_PEAK4_E_L_IND_MASK (0x00010000)
+#define SR_PEAK4_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK4_METRIC_LSB (0)
+#define SR_PEAK4_METRIC_WIDTH (16)
+#define SR_PEAK4_METRIC_MASK (0x0000FFFF)
+
+#define SR_START_DLY_EN_LSB (20)
+#define SR_START_DLY_EN_WIDTH (1)
+#define SR_START_DLY_EN_MASK (0x00100000)
+#define SR_START_DLY_EN_BIT (0x00100000)
+
+#define SR_PN_OFFSET_CFG_LSB (0)
+#define SR_PN_OFFSET_CFG_WIDTH (15)
+#define SR_PN_OFFSET_CFG_MASK (0x00007FFF)
+
+#define SR_PAGE_NUM_CFG_LSB (0)
+#define SR_PAGE_NUM_CFG_WIDTH (4)
+#define SR_PAGE_NUM_CFG_MASK (0x0000000F)
+
+#define SR_DATA_CNT_READ_LSB (0)
+#define SR_DATA_CNT_READ_WIDTH (9)
+#define SR_DATA_CNT_READ_MASK (0x000001FF)
+
+#define SR_IC_DLY_CFG_DLY_MODE_LSB (6)
+#define SR_IC_DLY_CFG_DLY_MODE_WIDTH (2)
+#define SR_IC_DLY_CFG_DLY_MODE_MASK (0x000000C0)
+
+#define SR_IC_DLY_CFG_SR_SFT_RST_LSB (2)
+#define SR_IC_DLY_CFG_SR_SFT_RST_WIDTH (1)
+#define SR_IC_DLY_CFG_SR_SFT_RST_MASK (0x00000004)
+#define SR_IC_DLY_CFG_SR_SFT_RST_BIT (0x00000004)
+
+#define SR_IC_DLY_CFG_IC_EN_LSB (1)
+#define SR_IC_DLY_CFG_IC_EN_WIDTH (1)
+#define SR_IC_DLY_CFG_IC_EN_MASK (0x00000002)
+#define SR_IC_DLY_CFG_IC_EN_BIT (0x00000002)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_LSB (0)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_WIDTH (1)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_MASK (0x00000001)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_BIT (0x00000001)
+
+#define SR_WIND_1_SIZE_LSB (0)
+#define SR_WIND_1_SIZE_WIDTH (15)
+#define SR_WIND_1_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_1_CFG_LSB (0)
+#define SR_PN_OFFSET_1_CFG_WIDTH (15)
+#define SR_PN_OFFSET_1_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_1_READ_LSB (0)
+#define SR_DATA_CNT_1_READ_WIDTH (9)
+#define SR_DATA_CNT_1_READ_MASK (0x000001FF)
+
+#define SR_WIND_2_SIZE_LSB (0)
+#define SR_WIND_2_SIZE_WIDTH (15)
+#define SR_WIND_2_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_2_CFG_LSB (0)
+#define SR_PN_OFFSET_2_CFG_WIDTH (15)
+#define SR_PN_OFFSET_2_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_2_READ_LSB (0)
+#define SR_DATA_CNT_2_READ_WIDTH (9)
+#define SR_DATA_CNT_2_READ_MASK (0x000001FF)
+
+#define SR_WIND_3_SIZE_LSB (0)
+#define SR_WIND_3_SIZE_WIDTH (15)
+#define SR_WIND_3_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_3_CFG_LSB (0)
+#define SR_PN_OFFSET_3_CFG_WIDTH (15)
+#define SR_PN_OFFSET_3_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_3_READ_LSB (0)
+#define SR_DATA_CNT_3_READ_WIDTH (9)
+#define SR_DATA_CNT_3_READ_MASK (0x000001FF)
+
+#define SR_WIND_4_SIZE_LSB (0)
+#define SR_WIND_4_SIZE_WIDTH (15)
+#define SR_WIND_4_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_4_CFG_LSB (0)
+#define SR_PN_OFFSET_4_CFG_WIDTH (15)
+#define SR_PN_OFFSET_4_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_4_READ_LSB (0)
+#define SR_DATA_CNT_4_READ_WIDTH (9)
+#define SR_DATA_CNT_4_READ_MASK (0x000001FF)
+
+#define SR_WIND_5_SIZE_LSB (0)
+#define SR_WIND_5_SIZE_WIDTH (15)
+#define SR_WIND_5_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_5_CFG_LSB (0)
+#define SR_PN_OFFSET_5_CFG_WIDTH (15)
+#define SR_PN_OFFSET_5_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_5_READ_LSB (0)
+#define SR_DATA_CNT_5_READ_WIDTH (9)
+#define SR_DATA_CNT_5_READ_MASK (0x000001FF)
+
+#define SR_WIND_6_SIZE_LSB (0)
+#define SR_WIND_6_SIZE_WIDTH (15)
+#define SR_WIND_6_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_6_CFG_LSB (0)
+#define SR_PN_OFFSET_6_CFG_WIDTH (15)
+#define SR_PN_OFFSET_6_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_6_READ_LSB (0)
+#define SR_DATA_CNT_6_READ_WIDTH (9)
+#define SR_DATA_CNT_6_READ_MASK (0x000001FF)
+
+#define SR_WIND_7_SIZE_LSB (0)
+#define SR_WIND_7_SIZE_WIDTH (15)
+#define SR_WIND_7_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_7_CFG_LSB (0)
+#define SR_PN_OFFSET_7_CFG_WIDTH (15)
+#define SR_PN_OFFSET_7_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_7_READ_LSB (0)
+#define SR_DATA_CNT_7_READ_WIDTH (9)
+#define SR_DATA_CNT_7_READ_MASK (0x000001FF)
+
+#define SR_WIND_8_SIZE_LSB (0)
+#define SR_WIND_8_SIZE_WIDTH (15)
+#define SR_WIND_8_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_8_CFG_LSB (0)
+#define SR_PN_OFFSET_8_CFG_WIDTH (15)
+#define SR_PN_OFFSET_8_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_8_READ_LSB (0)
+#define SR_DATA_CNT_8_READ_WIDTH (9)
+#define SR_DATA_CNT_8_READ_MASK (0x000001FF)
+
+#define SR_WIND_9_SIZE_LSB (0)
+#define SR_WIND_9_SIZE_WIDTH (15)
+#define SR_WIND_9_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_9_CFG_LSB (0)
+#define SR_PN_OFFSET_9_CFG_WIDTH (15)
+#define SR_PN_OFFSET_9_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_9_READ_LSB (0)
+#define SR_DATA_CNT_9_READ_WIDTH (9)
+#define SR_DATA_CNT_9_READ_MASK (0x000001FF)
+
+#define SR_WIND_10_SIZE_LSB (0)
+#define SR_WIND_10_SIZE_WIDTH (15)
+#define SR_WIND_10_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_10_CFG_LSB (0)
+#define SR_PN_OFFSET_10_CFG_WIDTH (15)
+#define SR_PN_OFFSET_10_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_10_READ_LSB (0)
+#define SR_DATA_CNT_10_READ_WIDTH (9)
+#define SR_DATA_CNT_10_READ_MASK (0x000001FF)
+
+#define SR_WIND_11_SIZE_LSB (0)
+#define SR_WIND_11_SIZE_WIDTH (15)
+#define SR_WIND_11_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_11_CFG_LSB (0)
+#define SR_PN_OFFSET_11_CFG_WIDTH (15)
+#define SR_PN_OFFSET_11_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_11_READ_LSB (0)
+#define SR_DATA_CNT_11_READ_WIDTH (9)
+#define SR_DATA_CNT_11_READ_MASK (0x000001FF)
+
+
+#endif //#ifndef _CPH_1X_SCH_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xschreg_95.h b/mcu/interface/l1/cl1/common/HW/cph1xschreg_95.h
new file mode 100644
index 0000000..d159749
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xschreg_95.h
@@ -0,0 +1,775 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_SCH_H_
+#define _CPH_1X_SCH_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define SEARCHER_REG_BASE (0xA7850000)
+
+#define SEARCHER_end (SEARCHER_REG_BASE + 0x0b60 + 1*4)
+
+
+
+#define SR_CTL1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0000))
+#define SR_CORR_LEN ((APBADDR32)(SEARCHER_REG_BASE + 0x0004))
+#define SR_NONCO_PASS ((APBADDR32)(SEARCHER_REG_BASE + 0x0008))
+#define SR_AUX_PLT_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x000C))
+#define SR_WIND ((APBADDR32)(SEARCHER_REG_BASE + 0x0010))
+#define SR_D1_THRES ((APBADDR32)(SEARCHER_REG_BASE + 0x0014))
+#define SR_AUX_OFF_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x0018))
+#define SR_OUTPUT ((APBADDR32)(SEARCHER_REG_BASE + 0x001C))
+#define SR_TST_CTL ((APBADDR32)(SEARCHER_REG_BASE + 0x0020))
+#define SR_TST_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0024))
+#define SR_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0028))
+#define SR_STAT ((APBADDR32)(SEARCHER_REG_BASE + 0x002c))
+#define SR_SMPL_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0030))
+#define SR_THRESH ((APBADDR32)(SEARCHER_REG_BASE + 0x0034))
+#define SR_WIN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0038))
+#define SR_INBUF_TSTCTL ((APBADDR32)(SEARCHER_REG_BASE + 0x003C))
+#define SR_INBUF_TSTDAT ((APBADDR32)(SEARCHER_REG_BASE + 0x0040))
+#define SR_PEAK1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0044))
+#define SR_PEAK2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0048))
+#define SR_PEAK3 ((APBADDR32)(SEARCHER_REG_BASE + 0x004C))
+#define SR_PEAK4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0050))
+#define SR_START_DLY ((APBADDR32)(SEARCHER_REG_BASE + 0x0054))
+#define SR_PN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0058))
+#define SR_PAGE_NUM ((APBADDR32)(SEARCHER_REG_BASE + 0x005C))
+#define SR_DATA_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0060))
+#define SR_IC_DLY_CFG ((APBADDR32)(SEARCHER_REG_BASE + 0x0064))
+#define SR_IC_DLY_CFG1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0068))
+#define SR_IC_DLY_CFG2 ((APBADDR32)(SEARCHER_REG_BASE + 0x006c))
+#define SR_AUX_PLT_WALSH_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x010C))
+#define SR_AUX_PLT_WALSH_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x020C))
+#define SR_AUX_PLT_WALSH_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x030C))
+#define SR_AUX_PLT_WALSH_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x040C))
+#define SR_AUX_PLT_WALSH_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x050C))
+#define SR_AUX_PLT_WALSH_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x060C))
+#define SR_AUX_PLT_WALSH_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x070C))
+#define SR_AUX_PLT_WALSH_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x080C))
+#define SR_AUX_PLT_WALSH_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x090C))
+#define SR_AUX_PLT_WALSH_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0A0C))
+#define SR_AUX_PLT_WALSH_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0B0C))
+#define SR_AUX_OFF_WALSH_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0118))
+#define SR_AUX_OFF_WALSH_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0218))
+#define SR_AUX_OFF_WALSH_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0318))
+#define SR_AUX_OFF_WALSH_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0418))
+#define SR_AUX_OFF_WALSH_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0518))
+#define SR_AUX_OFF_WALSH_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0618))
+#define SR_AUX_OFF_WALSH_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0718))
+#define SR_AUX_OFF_WALSH_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0818))
+#define SR_AUX_OFF_WALSH_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0918))
+#define SR_AUX_OFF_WALSH_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0A18))
+#define SR_AUX_OFF_WALSH_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0B18))
+#define SR_WIND_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0110))
+#define SR_PN_OFFSET_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0158))
+#define SR_DATA_CNT_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0160))
+#define SR_WIND_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0210))
+#define SR_PN_OFFSET_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0258))
+#define SR_DATA_CNT_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0260))
+#define SR_WIND_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0310))
+#define SR_PN_OFFSET_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0358))
+#define SR_DATA_CNT_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0360))
+#define SR_WIND_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0410))
+#define SR_PN_OFFSET_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0458))
+#define SR_DATA_CNT_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0460))
+#define SR_WIND_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0510))
+#define SR_PN_OFFSET_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0558))
+#define SR_DATA_CNT_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0560))
+#define SR_WIND_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0610))
+#define SR_PN_OFFSET_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0658))
+#define SR_DATA_CNT_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0660))
+#define SR_WIND_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0710))
+#define SR_PN_OFFSET_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0758))
+#define SR_DATA_CNT_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0760))
+#define SR_WIND_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0810))
+#define SR_PN_OFFSET_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0858))
+#define SR_DATA_CNT_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0860))
+#define SR_WIND_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0910))
+#define SR_PN_OFFSET_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0958))
+#define SR_DATA_CNT_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0960))
+#define SR_WIND_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a10))
+#define SR_PN_OFFSET_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a58))
+#define SR_DATA_CNT_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a60))
+#define SR_WIND_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b10))
+#define SR_PN_OFFSET_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b58))
+#define SR_DATA_CNT_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b60))
+
+
+#define SR_CTL1_OUT_SEL_LSB (16)
+#define SR_CTL1_OUT_SEL_WIDTH (2)
+#define SR_CTL1_OUT_SEL_MASK (0x00030000)
+
+#define SR_CTL1_THRESH_EN_LSB (14)
+#define SR_CTL1_THRESH_EN_WIDTH (1)
+#define SR_CTL1_THRESH_EN_MASK (0x00004000)
+#define SR_CTL1_THRESH_EN_BIT (0x00004000)
+
+#define SR_CTL1_CLR_BUF_CNTRS_LSB (12)
+#define SR_CTL1_CLR_BUF_CNTRS_WIDTH (1)
+#define SR_CTL1_CLR_BUF_CNTRS_MASK (0x00001000)
+#define SR_CTL1_CLR_BUF_CNTRS_BIT (0x00001000)
+
+#define SR_CTL1_TONE_LSB (11)
+#define SR_CTL1_TONE_WIDTH (1)
+#define SR_CTL1_TONE_MASK (0x00000800)
+#define SR_CTL1_TONE_BIT (0x00000800)
+
+#define SR_CTL1_TC_LSB (9)
+#define SR_CTL1_TC_WIDTH (2)
+#define SR_CTL1_TC_MASK (0x00000600)
+
+#define SR_CTL1_AUX_PILOT_EN_LSB (7)
+#define SR_CTL1_AUX_PILOT_EN_WIDTH (1)
+#define SR_CTL1_AUX_PILOT_EN_MASK (0x00000080)
+#define SR_CTL1_AUX_PILOT_EN_BIT (0x00000080)
+
+#define SR_CTL1_COHERENT_LSB (6)
+#define SR_CTL1_COHERENT_WIDTH (1)
+#define SR_CTL1_COHERENT_MASK (0x00000040)
+#define SR_CTL1_COHERENT_BIT (0x00000040)
+
+#define SR_CTL1_FREQ_DOMAIN_LSB (5)
+#define SR_CTL1_FREQ_DOMAIN_WIDTH (1)
+#define SR_CTL1_FREQ_DOMAIN_MASK (0x00000020)
+#define SR_CTL1_FREQ_DOMAIN_BIT (0x00000020)
+
+#define SR_CTL1_LOAD_TWO_BUF_LSB (3)
+#define SR_CTL1_LOAD_TWO_BUF_WIDTH (1)
+#define SR_CTL1_LOAD_TWO_BUF_MASK (0x00000008)
+#define SR_CTL1_LOAD_TWO_BUF_BIT (0x00000008)
+
+#define SR_CTL1_INPUT_BUF_EN_LSB (2)
+#define SR_CTL1_INPUT_BUF_EN_WIDTH (1)
+#define SR_CTL1_INPUT_BUF_EN_MASK (0x00000004)
+#define SR_CTL1_INPUT_BUF_EN_BIT (0x00000004)
+
+#define SR_CTL1_ACQ_MODE_EN_LSB (1)
+#define SR_CTL1_ACQ_MODE_EN_WIDTH (1)
+#define SR_CTL1_ACQ_MODE_EN_MASK (0x00000002)
+#define SR_CTL1_ACQ_MODE_EN_BIT (0x00000002)
+
+#define SR_CTL1_INIT_LSB (0)
+#define SR_CTL1_INIT_WIDTH (1)
+#define SR_CTL1_INIT_MASK (0x00000001)
+#define SR_CTL1_INIT_BIT (0x00000001)
+
+#define SR_CORR_LEN_D2_LSB (6)
+#define SR_CORR_LEN_D2_WIDTH (6)
+#define SR_CORR_LEN_D2_MASK (0x00000FC0)
+
+#define SR_CORR_LEN_D1_LSB (0)
+#define SR_CORR_LEN_D1_WIDTH (6)
+#define SR_CORR_LEN_D1_MASK (0x0000003F)
+
+#define SR_NONCO_PASS_D2MSB_LSB (7)
+#define SR_NONCO_PASS_D2MSB_WIDTH (6)
+#define SR_NONCO_PASS_D2MSB_MASK (0x00001F80)
+
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_LSB (6)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_WIDTH (1)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_MASK (0x00000040)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_BIT (0x00000040)
+
+#define SR_NONCO_PASS_D1LSB_LSB (0)
+#define SR_NONCO_PASS_D1LSB_WIDTH (6)
+#define SR_NONCO_PASS_D1LSB_MASK (0x0000003F)
+
+#define SR_AUX_PLT_WALSH_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_WIND_SIZE_LSB (0)
+#define SR_WIND_SIZE_WIDTH (15)
+#define SR_WIND_SIZE_MASK (0x00007FFF)
+
+#define SR_D1_THRES_CFG_LSB (0)
+#define SR_D1_THRES_CFG_WIDTH (16)
+#define SR_D1_THRES_CFG_MASK (0x0000FFFF)
+
+#define SR_AUX_OFF_WALSH_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_CODE_MASK (0x000001FF)
+
+#define SR_OUTPUT_WIN_OFFSET_LSB (17)
+#define SR_OUTPUT_WIN_OFFSET_WIDTH (9)
+#define SR_OUTPUT_WIN_OFFSET_MASK (0x03FE0000)
+
+#define SR_OUTPUT_E_L_IND_LSB (16)
+#define SR_OUTPUT_E_L_IND_WIDTH (1)
+#define SR_OUTPUT_E_L_IND_MASK (0x00010000)
+#define SR_OUTPUT_E_L_IND_BIT (0x00010000)
+
+#define SR_OUTPUT_METRIC_LSB (0)
+#define SR_OUTPUT_METRIC_WIDTH (16)
+#define SR_OUTPUT_METRIC_MASK (0x0000FFFF)
+
+#define SR_TST_CTL_TST_GO_LSB (4)
+#define SR_TST_CTL_TST_GO_WIDTH (1)
+#define SR_TST_CTL_TST_GO_MASK (0x00000010)
+#define SR_TST_CTL_TST_GO_BIT (0x00000010)
+
+#define SR_TST_CTL_TEST3_LSB (2)
+#define SR_TST_CTL_TEST3_WIDTH (1)
+#define SR_TST_CTL_TEST3_MASK (0x00000004)
+#define SR_TST_CTL_TEST3_BIT (0x00000004)
+
+#define SR_TST_CTL_NOT_STOP_MODE_LSB (0)
+#define SR_TST_CTL_NOT_STOP_MODE_WIDTH (1)
+#define SR_TST_CTL_NOT_STOP_MODE_MASK (0x00000001)
+#define SR_TST_CTL_NOT_STOP_MODE_BIT (0x00000001)
+#define SR_TST_CTL2_OBUF_ADDR_LSB (3)
+#define SR_TST_CTL2_OBUF_ADDR_WIDTH (9)
+#define SR_TST_CTL2_OBUF_ADDR_MASK (0x00000FF8)
+
+#define SR_TST_CTL2_OBF_RPTR_RST_LSB (2)
+#define SR_TST_CTL2_OBF_RPTR_RST_WIDTH (1)
+#define SR_TST_CTL2_OBF_RPTR_RST_MASK (0x00000004)
+#define SR_TST_CTL2_OBF_RPTR_RST_BIT (0x00000004)
+
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_LSB (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_WIDTH (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_MASK (0x00000002)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_BIT (0x00000002)
+
+#define SR_TST_CTL2_TEST_MODE_LSB (0)
+#define SR_TST_CTL2_TEST_MODE_WIDTH (1)
+#define SR_TST_CTL2_TEST_MODE_MASK (0x00000001)
+#define SR_TST_CTL2_TEST_MODE_BIT (0x00000001)
+
+#define SR_CTL2_CLK_ENB_LSB (0)
+#define SR_CTL2_CLK_ENB_WIDTH (1)
+#define SR_CTL2_CLK_ENB_MASK (0x00000001)
+#define SR_CTL2_CLK_ENB_BIT (0x00000001)
+
+#define SR_STAT_DONE_STAT_LSB (2)
+#define SR_STAT_DONE_STAT_WIDTH (1)
+#define SR_STAT_DONE_STAT_MASK (0x00000004)
+#define SR_STAT_DONE_STAT_BIT (0x00000004)
+
+#define SR_STAT_OBF_STAT_LSB (0)
+#define SR_STAT_OBF_STAT_WIDTH (1)
+#define SR_STAT_OBF_STAT_MASK (0x00000001)
+#define SR_STAT_OBF_STAT_BIT (0x00000001)
+
+#define SR_SMPL_CNT_SMPL_CNT_LSB (0)
+#define SR_SMPL_CNT_SMPL_CNT_WIDTH (10)
+#define SR_SMPL_CNT_SMPL_CNT_MASK (0x000003FF)
+
+#define SR_THRESH_OUTPUT_LSB (0)
+#define SR_THRESH_OUTPUT_WIDTH (16)
+#define SR_THRESH_OUTPUT_MASK (0x0000FFFF)
+
+#define SR_WIN_OFFSET_CFG_LSB (1)
+#define SR_WIN_OFFSET_CFG_WIDTH (9)
+#define SR_WIN_OFFSET_CFG_MASK (0x000003FE)
+
+#define SR_WIN_OFFSET_E_L_IND_LSB (0)
+#define SR_WIN_OFFSET_E_L_IND_WIDTH (1)
+#define SR_WIN_OFFSET_E_L_IND_MASK (0x00000001)
+#define SR_WIN_OFFSET_E_L_IND_BIT (0x00000001)
+
+#define SR_INBUF_TSTCTL_TST_EN_LSB (11)
+#define SR_INBUF_TSTCTL_TST_EN_WIDTH (1)
+#define SR_INBUF_TSTCTL_TST_EN_MASK (0x00000800)
+#define SR_INBUF_TSTCTL_TST_EN_BIT (0x00000800)
+
+#define SR_INBUF_TSTCTL_TST_ADDR_LSB (0)
+#define SR_INBUF_TSTCTL_TST_ADDR_WIDTH (11)
+#define SR_INBUF_TSTCTL_TST_ADDR_MASK (0x000007FF)
+
+#define SR_INBUF_TSTDAT_TSTDAT_LSB (0)
+#define SR_INBUF_TSTDAT_TSTDAT_WIDTH (16)
+#define SR_INBUF_TSTDAT_TSTDAT_MASK (0x0000FFFF)
+
+#define SR_PEAK1_WIN_OFFSET_LSB (17)
+#define SR_PEAK1_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK1_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK1_E_L_IND_LSB (16)
+#define SR_PEAK1_E_L_IND_WIDTH (1)
+#define SR_PEAK1_E_L_IND_MASK (0x00010000)
+#define SR_PEAK1_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK1_METRIC_LSB (0)
+#define SR_PEAK1_METRIC_WIDTH (16)
+#define SR_PEAK1_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK2_WIN_OFFSET_LSB (17)
+#define SR_PEAK2_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK2_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK2_E_L_IND_LSB (16)
+#define SR_PEAK2_E_L_IND_WIDTH (1)
+#define SR_PEAK2_E_L_IND_MASK (0x00010000)
+#define SR_PEAK2_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK2_METRIC_LSB (0)
+#define SR_PEAK2_METRIC_WIDTH (16)
+#define SR_PEAK2_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK3_WIN_OFFSET_LSB (17)
+#define SR_PEAK3_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK3_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK3_E_L_IND_LSB (16)
+#define SR_PEAK3_E_L_IND_WIDTH (1)
+#define SR_PEAK3_E_L_IND_MASK (0x00010000)
+#define SR_PEAK3_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK3_METRIC_LSB (0)
+#define SR_PEAK3_METRIC_WIDTH (16)
+#define SR_PEAK3_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK4_WIN_OFFSET_LSB (17)
+#define SR_PEAK4_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK4_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK4_E_L_IND_LSB (16)
+#define SR_PEAK4_E_L_IND_WIDTH (1)
+#define SR_PEAK4_E_L_IND_MASK (0x00010000)
+#define SR_PEAK4_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK4_METRIC_LSB (0)
+#define SR_PEAK4_METRIC_WIDTH (16)
+#define SR_PEAK4_METRIC_MASK (0x0000FFFF)
+
+#define SR_START_DLY_EN_LSB (20)
+#define SR_START_DLY_EN_WIDTH (1)
+#define SR_START_DLY_EN_MASK (0x00100000)
+#define SR_START_DLY_EN_BIT (0x00100000)
+
+#define SR_PN_OFFSET_CFG_LSB (0)
+#define SR_PN_OFFSET_CFG_WIDTH (15)
+#define SR_PN_OFFSET_CFG_MASK (0x00007FFF)
+
+#define SR_PAGE_NUM_CFG_LSB (0)
+#define SR_PAGE_NUM_CFG_WIDTH (4)
+#define SR_PAGE_NUM_CFG_MASK (0x0000000F)
+
+#define SR_DATA_CNT_READ_LSB (0)
+#define SR_DATA_CNT_READ_WIDTH (9)
+#define SR_DATA_CNT_READ_MASK (0x000001FF)
+
+#define SR_IC_DLY_CFG_SR_SFT_RST_LSB (2)
+#define SR_IC_DLY_CFG_SR_SFT_RST_WIDTH (1)
+#define SR_IC_DLY_CFG_SR_SFT_RST_MASK (0x00000004)
+#define SR_IC_DLY_CFG_SR_SFT_RST_BIT (0x00000004)
+
+#define SR_IC_DLY_CFG_IC_EN_LSB (1)
+#define SR_IC_DLY_CFG_IC_EN_WIDTH (1)
+#define SR_IC_DLY_CFG_IC_EN_MASK (0x00000002)
+#define SR_IC_DLY_CFG_IC_EN_BIT (0x00000002)
+
+#define SR_IC_DLY_CFG_DLY_MODE_LSB (0)
+#define SR_IC_DLY_CFG_DLY_MODE_WIDTH (1)
+#define SR_IC_DLY_CFG_DLY_MODE_MASK (0x00000001)
+#define SR_IC_DLY_CFG_DLY_MODE_BIT (0x00000001)
+
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_LSB (16)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_WIDTH (9)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_MASK (0x01FF0000)
+
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_LSB (7)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_WIDTH (9)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_MASK (0x0000FF80)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_LSB (5)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_MASK (0x00000060)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_LSB (3)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_MASK (0x00000018)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_LSB (1)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_MASK (0x00000006)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_LSB (0)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_WIDTH (1)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_MASK (0x00000001)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_BIT (0x00000001)
+
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_LSB (10)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_WIDTH (1)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_MASK (0x00000400)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_BIT (0x00000400)
+
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_LSB (5)
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_WIDTH (5)
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_MASK (0x000003E0)
+
+#define SR_IC_DLY_CFG2_IC_PLUS_LSB (4)
+#define SR_IC_DLY_CFG2_IC_PLUS_WIDTH (1)
+#define SR_IC_DLY_CFG2_IC_PLUS_MASK (0x00000010)
+#define SR_IC_DLY_CFG2_IC_PLUS_BIT (0x00000010)
+
+#define SR_IC_DLY_CFG2_SMPL_RPH_LSB (2)
+#define SR_IC_DLY_CFG2_SMPL_RPH_WIDTH (2)
+#define SR_IC_DLY_CFG2_SMPL_RPH_MASK (0x0000000C)
+
+#define SR_IC_DLY_CFG2_SMPL_WPH_LSB (0)
+#define SR_IC_DLY_CFG2_SMPL_WPH_WIDTH (2)
+#define SR_IC_DLY_CFG2_SMPL_WPH_MASK (0x00000003)
+
+#define SR_AUX_PLT_WALSH_1_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_1_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_1_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_1_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_1_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_1_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_2_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_2_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_2_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_2_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_2_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_2_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_3_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_3_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_3_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_3_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_3_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_3_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_4_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_4_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_4_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_4_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_4_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_4_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_5_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_5_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_5_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_5_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_5_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_5_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_6_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_6_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_6_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_6_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_6_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_6_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_7_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_7_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_7_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_7_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_7_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_7_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_8_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_8_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_8_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_8_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_8_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_8_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_9_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_9_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_9_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_9_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_9_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_9_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_10_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_10_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_10_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_10_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_10_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_10_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_11_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_11_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_11_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_11_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_11_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_11_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_OFF_WALSH_1_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_1_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_1_CODE_MASK (0x000001FF)
+
+
+#define SR_AUX_OFF_WALSH_2_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_2_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_2_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_3_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_3_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_3_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_4_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_4_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_4_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_5_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_5_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_5_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_6_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_6_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_6_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_7_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_7_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_7_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_8_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_8_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_8_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_9_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_9_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_9_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_10_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_10_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_10_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_11_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_11_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_11_CODE_MASK (0x000001FF)
+
+#define SR_WIND_1_SIZE_LSB (0)
+#define SR_WIND_1_SIZE_WIDTH (15)
+#define SR_WIND_1_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_1_CFG_LSB (0)
+#define SR_PN_OFFSET_1_CFG_WIDTH (15)
+#define SR_PN_OFFSET_1_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_1_READ_LSB (0)
+#define SR_DATA_CNT_1_READ_WIDTH (9)
+#define SR_DATA_CNT_1_READ_MASK (0x000001FF)
+
+#define SR_WIND_2_SIZE_LSB (0)
+#define SR_WIND_2_SIZE_WIDTH (15)
+#define SR_WIND_2_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_2_CFG_LSB (0)
+#define SR_PN_OFFSET_2_CFG_WIDTH (15)
+#define SR_PN_OFFSET_2_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_2_READ_LSB (0)
+#define SR_DATA_CNT_2_READ_WIDTH (9)
+#define SR_DATA_CNT_2_READ_MASK (0x000001FF)
+
+#define SR_WIND_3_SIZE_LSB (0)
+#define SR_WIND_3_SIZE_WIDTH (15)
+#define SR_WIND_3_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_3_CFG_LSB (0)
+#define SR_PN_OFFSET_3_CFG_WIDTH (15)
+#define SR_PN_OFFSET_3_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_3_READ_LSB (0)
+#define SR_DATA_CNT_3_READ_WIDTH (9)
+#define SR_DATA_CNT_3_READ_MASK (0x000001FF)
+
+#define SR_WIND_4_SIZE_LSB (0)
+#define SR_WIND_4_SIZE_WIDTH (15)
+#define SR_WIND_4_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_4_CFG_LSB (0)
+#define SR_PN_OFFSET_4_CFG_WIDTH (15)
+#define SR_PN_OFFSET_4_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_4_READ_LSB (0)
+#define SR_DATA_CNT_4_READ_WIDTH (9)
+#define SR_DATA_CNT_4_READ_MASK (0x000001FF)
+
+#define SR_WIND_5_SIZE_LSB (0)
+#define SR_WIND_5_SIZE_WIDTH (15)
+#define SR_WIND_5_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_5_CFG_LSB (0)
+#define SR_PN_OFFSET_5_CFG_WIDTH (15)
+#define SR_PN_OFFSET_5_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_5_READ_LSB (0)
+#define SR_DATA_CNT_5_READ_WIDTH (9)
+#define SR_DATA_CNT_5_READ_MASK (0x000001FF)
+
+#define SR_WIND_6_SIZE_LSB (0)
+#define SR_WIND_6_SIZE_WIDTH (15)
+#define SR_WIND_6_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_6_CFG_LSB (0)
+#define SR_PN_OFFSET_6_CFG_WIDTH (15)
+#define SR_PN_OFFSET_6_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_6_READ_LSB (0)
+#define SR_DATA_CNT_6_READ_WIDTH (9)
+#define SR_DATA_CNT_6_READ_MASK (0x000001FF)
+
+#define SR_WIND_7_SIZE_LSB (0)
+#define SR_WIND_7_SIZE_WIDTH (15)
+#define SR_WIND_7_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_7_CFG_LSB (0)
+#define SR_PN_OFFSET_7_CFG_WIDTH (15)
+#define SR_PN_OFFSET_7_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_7_READ_LSB (0)
+#define SR_DATA_CNT_7_READ_WIDTH (9)
+#define SR_DATA_CNT_7_READ_MASK (0x000001FF)
+
+#define SR_WIND_8_SIZE_LSB (0)
+#define SR_WIND_8_SIZE_WIDTH (15)
+#define SR_WIND_8_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_8_CFG_LSB (0)
+#define SR_PN_OFFSET_8_CFG_WIDTH (15)
+#define SR_PN_OFFSET_8_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_8_READ_LSB (0)
+#define SR_DATA_CNT_8_READ_WIDTH (9)
+#define SR_DATA_CNT_8_READ_MASK (0x000001FF)
+
+#define SR_WIND_9_SIZE_LSB (0)
+#define SR_WIND_9_SIZE_WIDTH (15)
+#define SR_WIND_9_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_9_CFG_LSB (0)
+#define SR_PN_OFFSET_9_CFG_WIDTH (15)
+#define SR_PN_OFFSET_9_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_9_READ_LSB (0)
+#define SR_DATA_CNT_9_READ_WIDTH (9)
+#define SR_DATA_CNT_9_READ_MASK (0x000001FF)
+
+#define SR_WIND_10_SIZE_LSB (0)
+#define SR_WIND_10_SIZE_WIDTH (15)
+#define SR_WIND_10_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_10_CFG_LSB (0)
+#define SR_PN_OFFSET_10_CFG_WIDTH (15)
+#define SR_PN_OFFSET_10_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_10_READ_LSB (0)
+#define SR_DATA_CNT_10_READ_WIDTH (9)
+#define SR_DATA_CNT_10_READ_MASK (0x000001FF)
+
+#define SR_WIND_11_SIZE_LSB (0)
+#define SR_WIND_11_SIZE_WIDTH (15)
+#define SR_WIND_11_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_11_CFG_LSB (0)
+#define SR_PN_OFFSET_11_CFG_WIDTH (15)
+#define SR_PN_OFFSET_11_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_11_READ_LSB (0)
+#define SR_DATA_CNT_11_READ_WIDTH (9)
+#define SR_DATA_CNT_11_READ_MASK (0x000001FF)
+
+
+#endif //#ifndef _CPH_1X_SCH_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xschreg_97.h b/mcu/interface/l1/cl1/common/HW/cph1xschreg_97.h
new file mode 100644
index 0000000..ff47ae7
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xschreg_97.h
@@ -0,0 +1,781 @@
+/*
+ 97 1xschreg
+ author: aubrey wang
+ data:2018.4.25
+*/
+ /*****************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2016
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ *****************************************************************************/
+#ifndef _CPH_1X_SCH_H_
+#define _CPH_1X_SCH_H_
+
+
+ typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+ typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+ typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+ typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+ typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+ typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+ typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+ typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+ typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define SEARCHER_REG_BASE (0xA9850000)
+
+#define SEARCHER_end (SEARCHER_REG_BASE + 0x0b60 + 1*4)
+
+
+
+#define SR_CTL1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0000))
+#define SR_CORR_LEN ((APBADDR32)(SEARCHER_REG_BASE + 0x0004))
+#define SR_NONCO_PASS ((APBADDR32)(SEARCHER_REG_BASE + 0x0008))
+#define SR_AUX_PLT_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x000C))
+#define SR_WIND ((APBADDR32)(SEARCHER_REG_BASE + 0x0010))
+#define SR_D1_THRES ((APBADDR32)(SEARCHER_REG_BASE + 0x0014))
+#define SR_AUX_OFF_WALSH ((APBADDR32)(SEARCHER_REG_BASE + 0x0018))
+#define SR_OUTPUT ((APBADDR32)(SEARCHER_REG_BASE + 0x001C))
+#define SR_TST_CTL ((APBADDR32)(SEARCHER_REG_BASE + 0x0020))
+#define SR_TST_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0024))
+#define SR_CTL2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0028))
+#define SR_STAT ((APBADDR32)(SEARCHER_REG_BASE + 0x002c))
+#define SR_SMPL_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0030))
+#define SR_THRESH ((APBADDR32)(SEARCHER_REG_BASE + 0x0034))
+#define SR_WIN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0038))
+#define SR_INBUF_TSTCTL ((APBADDR32)(SEARCHER_REG_BASE + 0x003C))
+#define SR_INBUF_TSTDAT ((APBADDR32)(SEARCHER_REG_BASE + 0x0040))
+#define SR_PEAK1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0044))
+#define SR_PEAK2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0048))
+#define SR_PEAK3 ((APBADDR32)(SEARCHER_REG_BASE + 0x004C))
+#define SR_PEAK4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0050))
+#define SR_START_DLY ((APBADDR32)(SEARCHER_REG_BASE + 0x0054))
+#define SR_PN_OFFSET ((APBADDR32)(SEARCHER_REG_BASE + 0x0058))
+#define SR_PAGE_NUM ((APBADDR32)(SEARCHER_REG_BASE + 0x005C))
+#define SR_DATA_CNT ((APBADDR32)(SEARCHER_REG_BASE + 0x0060))
+#define SR_IC_DLY_CFG ((APBADDR32)(SEARCHER_REG_BASE + 0x0064))
+#define SR_IC_DLY_CFG1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0068))
+#define SR_IC_DLY_CFG2 ((APBADDR32)(SEARCHER_REG_BASE + 0x006c))
+#define SR_AUX_PLT_WALSH_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x010C))
+#define SR_AUX_PLT_WALSH_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x020C))
+#define SR_AUX_PLT_WALSH_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x030C))
+#define SR_AUX_PLT_WALSH_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x040C))
+#define SR_AUX_PLT_WALSH_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x050C))
+#define SR_AUX_PLT_WALSH_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x060C))
+#define SR_AUX_PLT_WALSH_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x070C))
+#define SR_AUX_PLT_WALSH_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x080C))
+#define SR_AUX_PLT_WALSH_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x090C))
+#define SR_AUX_PLT_WALSH_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0A0C))
+#define SR_AUX_PLT_WALSH_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0B0C))
+#define SR_AUX_OFF_WALSH_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0118))
+#define SR_AUX_OFF_WALSH_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0218))
+#define SR_AUX_OFF_WALSH_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0318))
+#define SR_AUX_OFF_WALSH_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0418))
+#define SR_AUX_OFF_WALSH_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0518))
+#define SR_AUX_OFF_WALSH_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0618))
+#define SR_AUX_OFF_WALSH_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0718))
+#define SR_AUX_OFF_WALSH_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0818))
+#define SR_AUX_OFF_WALSH_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0918))
+#define SR_AUX_OFF_WALSH_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0A18))
+#define SR_AUX_OFF_WALSH_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0B18))
+#define SR_WIND_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0110))
+#define SR_PN_OFFSET_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0158))
+#define SR_DATA_CNT_1 ((APBADDR32)(SEARCHER_REG_BASE + 0x0160))
+#define SR_WIND_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0210))
+#define SR_PN_OFFSET_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0258))
+#define SR_DATA_CNT_2 ((APBADDR32)(SEARCHER_REG_BASE + 0x0260))
+#define SR_WIND_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0310))
+#define SR_PN_OFFSET_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0358))
+#define SR_DATA_CNT_3 ((APBADDR32)(SEARCHER_REG_BASE + 0x0360))
+#define SR_WIND_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0410))
+#define SR_PN_OFFSET_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0458))
+#define SR_DATA_CNT_4 ((APBADDR32)(SEARCHER_REG_BASE + 0x0460))
+#define SR_WIND_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0510))
+#define SR_PN_OFFSET_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0558))
+#define SR_DATA_CNT_5 ((APBADDR32)(SEARCHER_REG_BASE + 0x0560))
+#define SR_WIND_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0610))
+#define SR_PN_OFFSET_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0658))
+#define SR_DATA_CNT_6 ((APBADDR32)(SEARCHER_REG_BASE + 0x0660))
+#define SR_WIND_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0710))
+#define SR_PN_OFFSET_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0758))
+#define SR_DATA_CNT_7 ((APBADDR32)(SEARCHER_REG_BASE + 0x0760))
+#define SR_WIND_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0810))
+#define SR_PN_OFFSET_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0858))
+#define SR_DATA_CNT_8 ((APBADDR32)(SEARCHER_REG_BASE + 0x0860))
+#define SR_WIND_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0910))
+#define SR_PN_OFFSET_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0958))
+#define SR_DATA_CNT_9 ((APBADDR32)(SEARCHER_REG_BASE + 0x0960))
+#define SR_WIND_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a10))
+#define SR_PN_OFFSET_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a58))
+#define SR_DATA_CNT_10 ((APBADDR32)(SEARCHER_REG_BASE + 0x0a60))
+#define SR_WIND_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b10))
+#define SR_PN_OFFSET_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b58))
+#define SR_DATA_CNT_11 ((APBADDR32)(SEARCHER_REG_BASE + 0x0b60))
+
+
+#define SR_CTL1_OUT_SEL_LSB (16)
+#define SR_CTL1_OUT_SEL_WIDTH (2)
+#define SR_CTL1_OUT_SEL_MASK (0x00030000)
+
+#define SR_CTL1_THRESH_EN_LSB (14)
+#define SR_CTL1_THRESH_EN_WIDTH (1)
+#define SR_CTL1_THRESH_EN_MASK (0x00004000)
+#define SR_CTL1_THRESH_EN_BIT (0x00004000)
+
+#define SR_CTL1_CLR_BUF_CNTRS_LSB (12)
+#define SR_CTL1_CLR_BUF_CNTRS_WIDTH (1)
+#define SR_CTL1_CLR_BUF_CNTRS_MASK (0x00001000)
+#define SR_CTL1_CLR_BUF_CNTRS_BIT (0x00001000)
+
+#define SR_CTL1_TONE_LSB (11)
+#define SR_CTL1_TONE_WIDTH (1)
+#define SR_CTL1_TONE_MASK (0x00000800)
+#define SR_CTL1_TONE_BIT (0x00000800)
+
+#define SR_CTL1_TC_LSB (9)
+#define SR_CTL1_TC_WIDTH (2)
+#define SR_CTL1_TC_MASK (0x00000600)
+
+#define SR_CTL1_AUX_PILOT_EN_LSB (7)
+#define SR_CTL1_AUX_PILOT_EN_WIDTH (1)
+#define SR_CTL1_AUX_PILOT_EN_MASK (0x00000080)
+#define SR_CTL1_AUX_PILOT_EN_BIT (0x00000080)
+
+#define SR_CTL1_COHERENT_LSB (6)
+#define SR_CTL1_COHERENT_WIDTH (1)
+#define SR_CTL1_COHERENT_MASK (0x00000040)
+#define SR_CTL1_COHERENT_BIT (0x00000040)
+
+#define SR_CTL1_FREQ_DOMAIN_LSB (5)
+#define SR_CTL1_FREQ_DOMAIN_WIDTH (1)
+#define SR_CTL1_FREQ_DOMAIN_MASK (0x00000020)
+#define SR_CTL1_FREQ_DOMAIN_BIT (0x00000020)
+
+#define SR_CTL1_LOAD_TWO_BUF_LSB (3)
+#define SR_CTL1_LOAD_TWO_BUF_WIDTH (1)
+#define SR_CTL1_LOAD_TWO_BUF_MASK (0x00000008)
+#define SR_CTL1_LOAD_TWO_BUF_BIT (0x00000008)
+
+#define SR_CTL1_INPUT_BUF_EN_LSB (2)
+#define SR_CTL1_INPUT_BUF_EN_WIDTH (1)
+#define SR_CTL1_INPUT_BUF_EN_MASK (0x00000004)
+#define SR_CTL1_INPUT_BUF_EN_BIT (0x00000004)
+
+#define SR_CTL1_ACQ_MODE_EN_LSB (1)
+#define SR_CTL1_ACQ_MODE_EN_WIDTH (1)
+#define SR_CTL1_ACQ_MODE_EN_MASK (0x00000002)
+#define SR_CTL1_ACQ_MODE_EN_BIT (0x00000002)
+
+#define SR_CTL1_INIT_LSB (0)
+#define SR_CTL1_INIT_WIDTH (1)
+#define SR_CTL1_INIT_MASK (0x00000001)
+#define SR_CTL1_INIT_BIT (0x00000001)
+
+#define SR_CORR_LEN_D2_LSB (6)
+#define SR_CORR_LEN_D2_WIDTH (6)
+#define SR_CORR_LEN_D2_MASK (0x00000FC0)
+
+#define SR_CORR_LEN_D1_LSB (0)
+#define SR_CORR_LEN_D1_WIDTH (6)
+#define SR_CORR_LEN_D1_MASK (0x0000003F)
+
+#define SR_NONCO_PASS_D2MSB_LSB (7)
+#define SR_NONCO_PASS_D2MSB_WIDTH (6)
+#define SR_NONCO_PASS_D2MSB_MASK (0x00001F80)
+
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_LSB (6)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_WIDTH (1)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_MASK (0x00000040)
+#define SR_NONCO_PASS_D2LSB_OR_D1MSB_BIT (0x00000040)
+
+#define SR_NONCO_PASS_D1LSB_LSB (0)
+#define SR_NONCO_PASS_D1LSB_WIDTH (6)
+#define SR_NONCO_PASS_D1LSB_MASK (0x0000003F)
+
+#define SR_AUX_PLT_WALSH_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_WIND_SIZE_LSB (0)
+#define SR_WIND_SIZE_WIDTH (15)
+#define SR_WIND_SIZE_MASK (0x00007FFF)
+
+#define SR_D1_THRES_CFG_LSB (0)
+#define SR_D1_THRES_CFG_WIDTH (16)
+#define SR_D1_THRES_CFG_MASK (0x0000FFFF)
+
+#define SR_AUX_OFF_WALSH_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_CODE_MASK (0x000001FF)
+
+#define SR_OUTPUT_WIN_OFFSET_LSB (17)
+#define SR_OUTPUT_WIN_OFFSET_WIDTH (9)
+#define SR_OUTPUT_WIN_OFFSET_MASK (0x03FE0000)
+
+#define SR_OUTPUT_E_L_IND_LSB (16)
+#define SR_OUTPUT_E_L_IND_WIDTH (1)
+#define SR_OUTPUT_E_L_IND_MASK (0x00010000)
+#define SR_OUTPUT_E_L_IND_BIT (0x00010000)
+
+#define SR_OUTPUT_METRIC_LSB (0)
+#define SR_OUTPUT_METRIC_WIDTH (16)
+#define SR_OUTPUT_METRIC_MASK (0x0000FFFF)
+
+#define SR_TST_CTL_TST_GO_LSB (4)
+#define SR_TST_CTL_TST_GO_WIDTH (1)
+#define SR_TST_CTL_TST_GO_MASK (0x00000010)
+#define SR_TST_CTL_TST_GO_BIT (0x00000010)
+
+#define SR_TST_CTL_TEST3_LSB (2)
+#define SR_TST_CTL_TEST3_WIDTH (1)
+#define SR_TST_CTL_TEST3_MASK (0x00000004)
+#define SR_TST_CTL_TEST3_BIT (0x00000004)
+
+#define SR_TST_CTL_NOT_STOP_MODE_LSB (0)
+#define SR_TST_CTL_NOT_STOP_MODE_WIDTH (1)
+#define SR_TST_CTL_NOT_STOP_MODE_MASK (0x00000001)
+#define SR_TST_CTL_NOT_STOP_MODE_BIT (0x00000001)
+#define SR_TST_CTL2_OBUF_ADDR_LSB (3)
+#define SR_TST_CTL2_OBUF_ADDR_WIDTH (9)
+#define SR_TST_CTL2_OBUF_ADDR_MASK (0x00000FF8)
+
+#define SR_TST_CTL2_OBF_RPTR_RST_LSB (2)
+#define SR_TST_CTL2_OBF_RPTR_RST_WIDTH (1)
+#define SR_TST_CTL2_OBF_RPTR_RST_MASK (0x00000004)
+#define SR_TST_CTL2_OBF_RPTR_RST_BIT (0x00000004)
+
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_LSB (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_WIDTH (1)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_MASK (0x00000002)
+#define SR_TST_CTL2_BUF_ERR_OBF_GEN_BIT (0x00000002)
+
+#define SR_TST_CTL2_TEST_MODE_LSB (0)
+#define SR_TST_CTL2_TEST_MODE_WIDTH (1)
+#define SR_TST_CTL2_TEST_MODE_MASK (0x00000001)
+#define SR_TST_CTL2_TEST_MODE_BIT (0x00000001)
+
+#define SR_CTL2_CLK_ENB_LSB (0)
+#define SR_CTL2_CLK_ENB_WIDTH (1)
+#define SR_CTL2_CLK_ENB_MASK (0x00000001)
+#define SR_CTL2_CLK_ENB_BIT (0x00000001)
+
+#define SR_STAT_DONE_STAT_LSB (2)
+#define SR_STAT_DONE_STAT_WIDTH (1)
+#define SR_STAT_DONE_STAT_MASK (0x00000004)
+#define SR_STAT_DONE_STAT_BIT (0x00000004)
+
+#define SR_STAT_OBF_STAT_LSB (0)
+#define SR_STAT_OBF_STAT_WIDTH (1)
+#define SR_STAT_OBF_STAT_MASK (0x00000001)
+#define SR_STAT_OBF_STAT_BIT (0x00000001)
+
+#define SR_SMPL_CNT_SMPL_CNT_LSB (0)
+#define SR_SMPL_CNT_SMPL_CNT_WIDTH (10)
+#define SR_SMPL_CNT_SMPL_CNT_MASK (0x000003FF)
+
+#define SR_THRESH_OUTPUT_LSB (0)
+#define SR_THRESH_OUTPUT_WIDTH (16)
+#define SR_THRESH_OUTPUT_MASK (0x0000FFFF)
+
+#define SR_WIN_OFFSET_CFG_LSB (1)
+#define SR_WIN_OFFSET_CFG_WIDTH (9)
+#define SR_WIN_OFFSET_CFG_MASK (0x000003FE)
+
+#define SR_WIN_OFFSET_E_L_IND_LSB (0)
+#define SR_WIN_OFFSET_E_L_IND_WIDTH (1)
+#define SR_WIN_OFFSET_E_L_IND_MASK (0x00000001)
+#define SR_WIN_OFFSET_E_L_IND_BIT (0x00000001)
+
+#define SR_INBUF_TSTCTL_TST_EN_LSB (11)
+#define SR_INBUF_TSTCTL_TST_EN_WIDTH (1)
+#define SR_INBUF_TSTCTL_TST_EN_MASK (0x00000800)
+#define SR_INBUF_TSTCTL_TST_EN_BIT (0x00000800)
+
+#define SR_INBUF_TSTCTL_TST_ADDR_LSB (0)
+#define SR_INBUF_TSTCTL_TST_ADDR_WIDTH (11)
+#define SR_INBUF_TSTCTL_TST_ADDR_MASK (0x000007FF)
+
+#define SR_INBUF_TSTDAT_TSTDAT_LSB (0)
+#define SR_INBUF_TSTDAT_TSTDAT_WIDTH (16)
+#define SR_INBUF_TSTDAT_TSTDAT_MASK (0x0000FFFF)
+
+#define SR_PEAK1_WIN_OFFSET_LSB (17)
+#define SR_PEAK1_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK1_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK1_E_L_IND_LSB (16)
+#define SR_PEAK1_E_L_IND_WIDTH (1)
+#define SR_PEAK1_E_L_IND_MASK (0x00010000)
+#define SR_PEAK1_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK1_METRIC_LSB (0)
+#define SR_PEAK1_METRIC_WIDTH (16)
+#define SR_PEAK1_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK2_WIN_OFFSET_LSB (17)
+#define SR_PEAK2_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK2_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK2_E_L_IND_LSB (16)
+#define SR_PEAK2_E_L_IND_WIDTH (1)
+#define SR_PEAK2_E_L_IND_MASK (0x00010000)
+#define SR_PEAK2_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK2_METRIC_LSB (0)
+#define SR_PEAK2_METRIC_WIDTH (16)
+#define SR_PEAK2_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK3_WIN_OFFSET_LSB (17)
+#define SR_PEAK3_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK3_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK3_E_L_IND_LSB (16)
+#define SR_PEAK3_E_L_IND_WIDTH (1)
+#define SR_PEAK3_E_L_IND_MASK (0x00010000)
+#define SR_PEAK3_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK3_METRIC_LSB (0)
+#define SR_PEAK3_METRIC_WIDTH (16)
+#define SR_PEAK3_METRIC_MASK (0x0000FFFF)
+
+#define SR_PEAK4_WIN_OFFSET_LSB (17)
+#define SR_PEAK4_WIN_OFFSET_WIDTH (15)
+#define SR_PEAK4_WIN_OFFSET_MASK (0xFFFE0000)
+
+#define SR_PEAK4_E_L_IND_LSB (16)
+#define SR_PEAK4_E_L_IND_WIDTH (1)
+#define SR_PEAK4_E_L_IND_MASK (0x00010000)
+#define SR_PEAK4_E_L_IND_BIT (0x00010000)
+
+#define SR_PEAK4_METRIC_LSB (0)
+#define SR_PEAK4_METRIC_WIDTH (16)
+#define SR_PEAK4_METRIC_MASK (0x0000FFFF)
+
+#define SR_START_DLY_EN_LSB (20)
+#define SR_START_DLY_EN_WIDTH (1)
+#define SR_START_DLY_EN_MASK (0x00100000)
+#define SR_START_DLY_EN_BIT (0x00100000)
+
+#define SR_PN_OFFSET_CFG_LSB (0)
+#define SR_PN_OFFSET_CFG_WIDTH (15)
+#define SR_PN_OFFSET_CFG_MASK (0x00007FFF)
+
+#define SR_PAGE_NUM_CFG_LSB (0)
+#define SR_PAGE_NUM_CFG_WIDTH (4)
+#define SR_PAGE_NUM_CFG_MASK (0x0000000F)
+
+#define SR_DATA_CNT_READ_LSB (0)
+#define SR_DATA_CNT_READ_WIDTH (9)
+#define SR_DATA_CNT_READ_MASK (0x000001FF)
+
+#define SR_IC_DLY_CFG_SR_SFT_RST_LSB (2)
+#define SR_IC_DLY_CFG_SR_SFT_RST_WIDTH (1)
+#define SR_IC_DLY_CFG_SR_SFT_RST_MASK (0x00000004)
+#define SR_IC_DLY_CFG_SR_SFT_RST_BIT (0x00000004)
+
+#define SR_IC_DLY_CFG_IC_EN_LSB (1)
+#define SR_IC_DLY_CFG_IC_EN_WIDTH (1)
+#define SR_IC_DLY_CFG_IC_EN_MASK (0x00000002)
+#define SR_IC_DLY_CFG_IC_EN_BIT (0x00000002)
+
+#define SR_IC_DLY_CFG_DLY_MODE_LSB (0)
+#define SR_IC_DLY_CFG_DLY_MODE_WIDTH (1)
+#define SR_IC_DLY_CFG_DLY_MODE_MASK (0x00000001)
+#define SR_IC_DLY_CFG_DLY_MODE_BIT (0x00000001)
+
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_LSB (16)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_WIDTH (9)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI1_MASK (0x01FF0000)
+
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_LSB (7)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_WIDTH (9)
+#define SR_IC_DLY_CFG1_SR_BUFF_RADDR_INI0_MASK (0x0000FF80)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_LSB (5)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI3_MASK (0x00000060)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_LSB (3)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI2_MASK (0x00000018)
+
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_LSB (1)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_WIDTH (2)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_INI1_MASK (0x00000006)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_LSB (0)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_WIDTH (1)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_MASK (0x00000001)
+#define SR_IC_DLY_CFG1_SHIFT_CNT_SEL_BIT (0x00000001)
+
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_LSB (10)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_WIDTH (1)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_MASK (0x00000400)
+#define SR_IC_DLY_CFG2_SHIFT_CNT_INI_LD_BIT (0x00000400)
+
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_LSB (5)
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_WIDTH (5)
+#define SR_IC_DLY_CFG2_MUX_SREN_SEL_MASK (0x000003E0)
+
+#define SR_IC_DLY_CFG2_IC_PLUS_LSB (4)
+#define SR_IC_DLY_CFG2_IC_PLUS_WIDTH (1)
+#define SR_IC_DLY_CFG2_IC_PLUS_MASK (0x00000010)
+#define SR_IC_DLY_CFG2_IC_PLUS_BIT (0x00000010)
+
+#define SR_IC_DLY_CFG2_SMPL_RPH_LSB (2)
+#define SR_IC_DLY_CFG2_SMPL_RPH_WIDTH (2)
+#define SR_IC_DLY_CFG2_SMPL_RPH_MASK (0x0000000C)
+
+#define SR_IC_DLY_CFG2_SMPL_WPH_LSB (0)
+#define SR_IC_DLY_CFG2_SMPL_WPH_WIDTH (2)
+#define SR_IC_DLY_CFG2_SMPL_WPH_MASK (0x00000003)
+
+#define SR_AUX_PLT_WALSH_1_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_1_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_1_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_1_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_1_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_1_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_1_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_2_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_2_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_2_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_2_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_2_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_2_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_2_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_3_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_3_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_3_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_3_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_3_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_3_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_3_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_4_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_4_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_4_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_4_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_4_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_4_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_4_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_5_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_5_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_5_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_5_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_5_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_5_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_5_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_6_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_6_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_6_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_6_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_6_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_6_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_6_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_7_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_7_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_7_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_7_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_7_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_7_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_7_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_8_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_8_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_8_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_8_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_8_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_8_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_8_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_9_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_9_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_9_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_9_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_9_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_9_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_9_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_10_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_10_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_10_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_10_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_10_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_10_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_10_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_PLT_WALSH_11_QOF_LSB (9)
+#define SR_AUX_PLT_WALSH_11_QOF_WIDTH (2)
+#define SR_AUX_PLT_WALSH_11_QOF_MASK (0x00000600)
+
+#define SR_AUX_PLT_WALSH_11_N_PARM_LSB (7)
+#define SR_AUX_PLT_WALSH_11_N_PARM_WIDTH (2)
+#define SR_AUX_PLT_WALSH_11_N_PARM_MASK (0x00000180)
+
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_LSB (0)
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_WIDTH (7)
+#define SR_AUX_PLT_WALSH_11_FUNC_NUM_MASK (0x0000007F)
+
+#define SR_AUX_OFF_WALSH_1_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_1_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_1_CODE_MASK (0x000001FF)
+
+
+#define SR_AUX_OFF_WALSH_2_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_2_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_2_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_3_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_3_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_3_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_4_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_4_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_4_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_5_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_5_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_5_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_6_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_6_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_6_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_7_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_7_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_7_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_8_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_8_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_8_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_9_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_9_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_9_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_10_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_10_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_10_CODE_MASK (0x000001FF)
+
+#define SR_AUX_OFF_WALSH_11_CODE_LSB (0)
+#define SR_AUX_OFF_WALSH_11_CODE_WIDTH (9)
+#define SR_AUX_OFF_WALSH_11_CODE_MASK (0x000001FF)
+
+#define SR_WIND_1_SIZE_LSB (0)
+#define SR_WIND_1_SIZE_WIDTH (15)
+#define SR_WIND_1_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_1_CFG_LSB (0)
+#define SR_PN_OFFSET_1_CFG_WIDTH (15)
+#define SR_PN_OFFSET_1_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_1_READ_LSB (0)
+#define SR_DATA_CNT_1_READ_WIDTH (9)
+#define SR_DATA_CNT_1_READ_MASK (0x000001FF)
+
+#define SR_WIND_2_SIZE_LSB (0)
+#define SR_WIND_2_SIZE_WIDTH (15)
+#define SR_WIND_2_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_2_CFG_LSB (0)
+#define SR_PN_OFFSET_2_CFG_WIDTH (15)
+#define SR_PN_OFFSET_2_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_2_READ_LSB (0)
+#define SR_DATA_CNT_2_READ_WIDTH (9)
+#define SR_DATA_CNT_2_READ_MASK (0x000001FF)
+
+#define SR_WIND_3_SIZE_LSB (0)
+#define SR_WIND_3_SIZE_WIDTH (15)
+#define SR_WIND_3_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_3_CFG_LSB (0)
+#define SR_PN_OFFSET_3_CFG_WIDTH (15)
+#define SR_PN_OFFSET_3_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_3_READ_LSB (0)
+#define SR_DATA_CNT_3_READ_WIDTH (9)
+#define SR_DATA_CNT_3_READ_MASK (0x000001FF)
+
+#define SR_WIND_4_SIZE_LSB (0)
+#define SR_WIND_4_SIZE_WIDTH (15)
+#define SR_WIND_4_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_4_CFG_LSB (0)
+#define SR_PN_OFFSET_4_CFG_WIDTH (15)
+#define SR_PN_OFFSET_4_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_4_READ_LSB (0)
+#define SR_DATA_CNT_4_READ_WIDTH (9)
+#define SR_DATA_CNT_4_READ_MASK (0x000001FF)
+
+#define SR_WIND_5_SIZE_LSB (0)
+#define SR_WIND_5_SIZE_WIDTH (15)
+#define SR_WIND_5_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_5_CFG_LSB (0)
+#define SR_PN_OFFSET_5_CFG_WIDTH (15)
+#define SR_PN_OFFSET_5_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_5_READ_LSB (0)
+#define SR_DATA_CNT_5_READ_WIDTH (9)
+#define SR_DATA_CNT_5_READ_MASK (0x000001FF)
+
+#define SR_WIND_6_SIZE_LSB (0)
+#define SR_WIND_6_SIZE_WIDTH (15)
+#define SR_WIND_6_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_6_CFG_LSB (0)
+#define SR_PN_OFFSET_6_CFG_WIDTH (15)
+#define SR_PN_OFFSET_6_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_6_READ_LSB (0)
+#define SR_DATA_CNT_6_READ_WIDTH (9)
+#define SR_DATA_CNT_6_READ_MASK (0x000001FF)
+
+#define SR_WIND_7_SIZE_LSB (0)
+#define SR_WIND_7_SIZE_WIDTH (15)
+#define SR_WIND_7_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_7_CFG_LSB (0)
+#define SR_PN_OFFSET_7_CFG_WIDTH (15)
+#define SR_PN_OFFSET_7_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_7_READ_LSB (0)
+#define SR_DATA_CNT_7_READ_WIDTH (9)
+#define SR_DATA_CNT_7_READ_MASK (0x000001FF)
+
+#define SR_WIND_8_SIZE_LSB (0)
+#define SR_WIND_8_SIZE_WIDTH (15)
+#define SR_WIND_8_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_8_CFG_LSB (0)
+#define SR_PN_OFFSET_8_CFG_WIDTH (15)
+#define SR_PN_OFFSET_8_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_8_READ_LSB (0)
+#define SR_DATA_CNT_8_READ_WIDTH (9)
+#define SR_DATA_CNT_8_READ_MASK (0x000001FF)
+
+#define SR_WIND_9_SIZE_LSB (0)
+#define SR_WIND_9_SIZE_WIDTH (15)
+#define SR_WIND_9_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_9_CFG_LSB (0)
+#define SR_PN_OFFSET_9_CFG_WIDTH (15)
+#define SR_PN_OFFSET_9_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_9_READ_LSB (0)
+#define SR_DATA_CNT_9_READ_WIDTH (9)
+#define SR_DATA_CNT_9_READ_MASK (0x000001FF)
+
+#define SR_WIND_10_SIZE_LSB (0)
+#define SR_WIND_10_SIZE_WIDTH (15)
+#define SR_WIND_10_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_10_CFG_LSB (0)
+#define SR_PN_OFFSET_10_CFG_WIDTH (15)
+#define SR_PN_OFFSET_10_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_10_READ_LSB (0)
+#define SR_DATA_CNT_10_READ_WIDTH (9)
+#define SR_DATA_CNT_10_READ_MASK (0x000001FF)
+
+#define SR_WIND_11_SIZE_LSB (0)
+#define SR_WIND_11_SIZE_WIDTH (15)
+#define SR_WIND_11_SIZE_MASK (0x00007FFF)
+
+#define SR_PN_OFFSET_11_CFG_LSB (0)
+#define SR_PN_OFFSET_11_CFG_WIDTH (15)
+#define SR_PN_OFFSET_11_CFG_MASK (0x00007FFF)
+
+#define SR_DATA_CNT_11_READ_LSB (0)
+#define SR_DATA_CNT_11_READ_WIDTH (9)
+#define SR_DATA_CNT_11_READ_MASK (0x000001FF)
+
+
+#endif //#ifndef _CPH_1X_SCH_H_
+
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xtxbrp.h b/mcu/interface/l1/cl1/common/HW/cph1xtxbrp.h
new file mode 100644
index 0000000..17248b2
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xtxbrp.h
@@ -0,0 +1,879 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_TXBRP_H_
+#define _CPH_1X_TXBRP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#if defined(__MD93__)||defined(__MD95__)
+#define BRP_C2K_1XRTT_REG_BASE (0xa8020000)
+#else
+#define BRP_C2K_1XRTT_REG_BASE (0xa8820000)
+#endif
+#define BRP_C2K_1XRTT_end (BRP_C2K_1XRTT_REG_BASE + 0x03c8 + 1*4)
+
+
+#define WORK_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0000))
+#define GLOBAL_IRQ ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0008))
+#define GLOBAL_IRQ_MASK ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x000c))
+#define GLOBAL_IRQ_CLR ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0010))
+#define RTT_IRQ ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0044))
+#define RTT_IRQ_MASK ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0048))
+#define RTT_IRQ_CLR ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x004c))
+#define TXBRP_SW_CKEN_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0050))
+#define TXBRP_CLK_CTRLSEL_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0054))
+#define DEBUG_REG_BANK_SEL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0058))
+#define MEM_TEST_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x005c))
+#define TRIGGER_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0060))
+#define DI_SWAP_EN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0064))
+#define DI_TEST_CFG ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0068))
+#define I_REG_ULTRA_PRE_EN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x006c))
+#define I_REG_BEGIN_ULTRA_CNT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0070))
+#define I_REG_ULTRA_WATER_MARK ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0074))
+#define DI_DEBUG ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0078))
+#define DEBUG_TRIG_SEL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x007c))
+#define ENC_FSM_STATE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0090))
+#define CRC_DBG_FLAG ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0094))
+#define INTLV_B_LWT_ST_0 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0098))
+#define INTLV_B_LWT_ST_1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x009c))
+#define UTXBRP_CTRL_FSM_STATE1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00a0))
+#define UTXBRP_CTRL_FSM_STATE2 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00a4))
+#define RM_FSM_STATE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00a8))
+#define RUMAP_FSM_STATE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00ac))
+#define UTXBRP_TEST_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00c4))
+#define CRP_SW_READ_CTRL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00c8))
+#define C2K_READ_RST ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00cc))
+#define RTT_START ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00f0))
+#define TXA_INPUT_LEN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0110))
+#define TXA_PUNC ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0118))
+#define TXA_HA_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x011c))
+#define TXA_INTRLV_PARM ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0120))
+#define TXA_FREP_L ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0124))
+#define CHL_TYPE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0128))
+#define TXA_CRC ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x012c))
+#define TXA_FREP_LPML ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0130))
+#define TXA_FREP_MM1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0134))
+#define TXA_FREP_ACC0 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0138))
+#define TXA_PUNC_PAT0 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x013c))
+#define TXA_PUNC_PAT1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0140))
+#define TXA_FREP_LP ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0144))
+#define TXA_TST_CTRL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0148))
+#define RTT_CHNL_BASE_ADDR ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x014c))
+#define TXBRP_DBG_CRC32_EN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03bc))
+#define TXBRP_DBG_CRC32_RSLT_I_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03c0))
+#define TXBRP_DBG_CRC32_RSLT_Q_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03c4))
+#define DEBUG_CRC_SEL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03c8))
+
+
+#define WORK_MODE_LSB (0)
+#define WORK_MODE_WIDTH (5)
+#define WORK_MODE_MASK (0x0000001F)
+
+#define GLOBAL_IRQ_DI_ERR_IRQ_LSB (3)
+#define GLOBAL_IRQ_DI_ERR_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_DI_ERR_IRQ_MASK (0x00000008)
+#define GLOBAL_IRQ_DI_ERR_IRQ_BIT (0x00000008)
+
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_LSB (2)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_MASK (0x00000004)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_BIT (0x00000004)
+
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_LSB (1)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_MASK (0x00000002)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_BIT (0x00000002)
+
+#define GLOBAL_IRQ_MODE_IRQ_LSB (0)
+#define GLOBAL_IRQ_MODE_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_IRQ_MASK (0x00000001)
+#define GLOBAL_IRQ_MODE_IRQ_BIT (0x00000001)
+
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_LSB (3)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_MASK (0x00000008)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_BIT (0x00000008)
+
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_LSB (2)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_MASK (0x00000004)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_BIT (0x00000004)
+
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_LSB (1)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_MASK (0x00000002)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_BIT (0x00000002)
+
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_LSB (0)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_MASK (0x00000001)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_BIT (0x00000001)
+
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_LSB (3)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_MASK (0x00000008)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_BIT (0x00000008)
+
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_LSB (2)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_MASK (0x00000004)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_BIT (0x00000004)
+
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_LSB (1)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_MASK (0x00000002)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_BIT (0x00000002)
+
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_LSB (0)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_MASK (0x00000001)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_BIT (0x00000001)
+
+#define RTT_IRQ_RTT_TRIG_ERR_LSB (3)
+#define RTT_IRQ_RTT_TRIG_ERR_WIDTH (1)
+#define RTT_IRQ_RTT_TRIG_ERR_MASK (0x00000008)
+#define RTT_IRQ_RTT_TRIG_ERR_BIT (0x00000008)
+
+#define RTT_IRQ_RTT_CHNL1_RD_ERR_LSB (2)
+#define RTT_IRQ_RTT_CHNL1_RD_ERR_WIDTH (1)
+#define RTT_IRQ_RTT_CHNL1_RD_ERR_MASK (0x00000004)
+#define RTT_IRQ_RTT_CHNL1_RD_ERR_BIT (0x00000004)
+
+#define RTT_IRQ_RTT_CHNL0_RD_ERR_LSB (1)
+#define RTT_IRQ_RTT_CHNL0_RD_ERR_WIDTH (1)
+#define RTT_IRQ_RTT_CHNL0_RD_ERR_MASK (0x00000002)
+#define RTT_IRQ_RTT_CHNL0_RD_ERR_BIT (0x00000002)
+
+#define RTT_IRQ_RTT_DONE_LSB (0)
+#define RTT_IRQ_RTT_DONE_WIDTH (1)
+#define RTT_IRQ_RTT_DONE_MASK (0x00000001)
+#define RTT_IRQ_RTT_DONE_BIT (0x00000001)
+
+#define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_LSB (3)
+#define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_WIDTH (1)
+#define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_MASK (0x00000008)
+#define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_BIT (0x00000008)
+
+#define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_LSB (2)
+#define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_WIDTH (1)
+#define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_MASK (0x00000004)
+#define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_BIT (0x00000004)
+
+#define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_LSB (1)
+#define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_WIDTH (1)
+#define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_MASK (0x00000002)
+#define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_BIT (0x00000002)
+
+#define RTT_IRQ_MASK_RTT_DONE_MASK_LSB (0)
+#define RTT_IRQ_MASK_RTT_DONE_MASK_WIDTH (1)
+#define RTT_IRQ_MASK_RTT_DONE_MASK_MASK (0x00000001)
+#define RTT_IRQ_MASK_RTT_DONE_MASK_BIT (0x00000001)
+
+#define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_LSB (3)
+#define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_WIDTH (1)
+#define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_MASK (0x00000008)
+#define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_BIT (0x00000008)
+
+#define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_LSB (2)
+#define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_WIDTH (1)
+#define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_MASK (0x00000004)
+#define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_BIT (0x00000004)
+
+#define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_LSB (1)
+#define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_WIDTH (1)
+#define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_MASK (0x00000002)
+#define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_BIT (0x00000002)
+
+#define RTT_IRQ_CLR_RTT_DONE_CLR_LSB (0)
+#define RTT_IRQ_CLR_RTT_DONE_CLR_WIDTH (1)
+#define RTT_IRQ_CLR_RTT_DONE_CLR_MASK (0x00000001)
+#define RTT_IRQ_CLR_RTT_DONE_CLR_BIT (0x00000001)
+
+#define TXBRP_SW_CKEN_TX3G_SW_CKEN_LSB (12)
+#define TXBRP_SW_CKEN_TX3G_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_TX3G_SW_CKEN_MASK (0x00001000)
+#define TXBRP_SW_CKEN_TX3G_SW_CKEN_BIT (0x00001000)
+
+#define TXBRP_SW_CKEN_TXSRP_SW_CKEN_LSB (11)
+#define TXBRP_SW_CKEN_TXSRP_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_TXSRP_SW_CKEN_MASK (0x00000800)
+#define TXBRP_SW_CKEN_TXSRP_SW_CKEN_BIT (0x00000800)
+
+#define TXBRP_SW_CKEN_APB_SW_CKEN_LSB (10)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_MASK (0x00000400)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_BIT (0x00000400)
+
+#define TXBRP_SW_CKEN_OB_SW_CKEN_LSB (9)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_MASK (0x00000200)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_BIT (0x00000200)
+
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_LSB (8)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_MASK (0x00000100)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_BIT (0x00000100)
+
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_LSB (7)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_MASK (0x00000080)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_BIT (0x00000080)
+
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_LSB (6)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_MASK (0x00000040)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_BIT (0x00000040)
+
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_LSB (5)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_MASK (0x00000020)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_BIT (0x00000020)
+
+#define TXBRP_SW_CKEN_RM_SW_CKEN_LSB (4)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_MASK (0x00000010)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_BIT (0x00000010)
+
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_LSB (3)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_MASK (0x00000008)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_BIT (0x00000008)
+
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_LSB (2)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_MASK (0x00000004)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_BIT (0x00000004)
+
+#define TXBRP_SW_CKEN_DI_SW_CKEN_LSB (1)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_MASK (0x00000002)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_BIT (0x00000002)
+
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_LSB (0)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_MASK (0x00000001)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_LSB (12)
+#define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_MASK (0x00001000)
+#define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_BIT (0x00001000)
+
+#define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_LSB (11)
+#define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_MASK (0x00000800)
+#define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_BIT (0x00000800)
+
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_LSB (10)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_MASK (0x00000400)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_BIT (0x00000400)
+
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_LSB (9)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_MASK (0x00000200)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_BIT (0x00000200)
+
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_LSB (8)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_MASK (0x00000100)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_BIT (0x00000100)
+
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_LSB (7)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_MASK (0x00000080)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_BIT (0x00000080)
+
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_LSB (6)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_MASK (0x00000040)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_BIT (0x00000040)
+
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_LSB (5)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_MASK (0x00000020)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_BIT (0x00000020)
+
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_LSB (4)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_MASK (0x00000010)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_BIT (0x00000010)
+
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_LSB (3)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_MASK (0x00000008)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_BIT (0x00000008)
+
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_LSB (2)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_MASK (0x00000004)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_BIT (0x00000004)
+
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_LSB (1)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_MASK (0x00000002)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_BIT (0x00000002)
+
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_LSB (0)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_MASK (0x00000001)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_BIT (0x00000001)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_LSB (24)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_MASK (0xFF000000)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_LSB (16)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_MASK (0x00FF0000)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_LSB (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_MASK (0x0000FF00)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_LSB (0)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_MASK (0x000000FF)
+
+#define MEM_TEST_MODE_CRP_WR_MEM_EN_LSB (1)
+#define MEM_TEST_MODE_CRP_WR_MEM_EN_WIDTH (1)
+#define MEM_TEST_MODE_CRP_WR_MEM_EN_MASK (0x00000002)
+#define MEM_TEST_MODE_CRP_WR_MEM_EN_BIT (0x00000002)
+
+#define MEM_TEST_MODE_MEM_TEST_MODE_LSB (0)
+#define MEM_TEST_MODE_MEM_TEST_MODE_WIDTH (1)
+#define MEM_TEST_MODE_MEM_TEST_MODE_MASK (0x00000001)
+#define MEM_TEST_MODE_MEM_TEST_MODE_BIT (0x00000001)
+
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_LSB (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_WIDTH (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_MASK (0x00000002)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_BIT (0x00000002)
+
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_LSB (0)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_WIDTH (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_MASK (0x00000001)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_BIT (0x00000001)
+
+#define DI_SWAP_EN_LSB (0)
+#define DI_SWAP_EN_WIDTH (3)
+#define DI_SWAP_EN_MASK (0x00000007)
+
+#define DI_TEST_CFG_DI_TEST_MODE_EN_LSB (10)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_WIDTH (1)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_MASK (0x00000400)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_BIT (0x00000400)
+
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_LSB (8)
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_WIDTH (2)
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_MASK (0x00000300)
+
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_LSB (0)
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_WIDTH (8)
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_MASK (0x000000FF)
+
+#define I_REG_ULTRA_PRE_EN_LSB (0)
+#define I_REG_ULTRA_PRE_EN_WIDTH (1)
+#define I_REG_ULTRA_PRE_EN_MASK (0x00000001)
+#define I_REG_ULTRA_PRE_EN_BIT (0x00000001)
+
+#define I_REG_BEGIN_ULTRA_CNT_LSB (0)
+#define I_REG_BEGIN_ULTRA_CNT_WIDTH (3)
+#define I_REG_BEGIN_ULTRA_CNT_MASK (0x00000007)
+
+#define I_REG_ULTRA_WATER_MARK_LSB (0)
+#define I_REG_ULTRA_WATER_MARK_WIDTH (3)
+#define I_REG_ULTRA_WATER_MARK_MASK (0x00000007)
+
+#define DI_DEBUG_DMA0_STATE_LSB (20)
+#define DI_DEBUG_DMA0_STATE_WIDTH (2)
+#define DI_DEBUG_DMA0_STATE_MASK (0x00300000)
+
+#define DI_DEBUG_RAM_RD_STATE_LSB (16)
+#define DI_DEBUG_RAM_RD_STATE_WIDTH (2)
+#define DI_DEBUG_RAM_RD_STATE_MASK (0x00030000)
+
+#define DI_DEBUG_O_DMA0_UTR_LSB (13)
+#define DI_DEBUG_O_DMA0_UTR_WIDTH (1)
+#define DI_DEBUG_O_DMA0_UTR_MASK (0x00002000)
+#define DI_DEBUG_O_DMA0_UTR_BIT (0x00002000)
+
+#define DI_DEBUG_O_DMA0_PTR_UTR_LSB (12)
+#define DI_DEBUG_O_DMA0_PTR_UTR_WIDTH (1)
+#define DI_DEBUG_O_DMA0_PTR_UTR_MASK (0x00001000)
+#define DI_DEBUG_O_DMA0_PTR_UTR_BIT (0x00001000)
+
+#define DI_DEBUG_O_DMA0_RD_REQ_LSB (10)
+#define DI_DEBUG_O_DMA0_RD_REQ_WIDTH (1)
+#define DI_DEBUG_O_DMA0_RD_REQ_MASK (0x00000400)
+#define DI_DEBUG_O_DMA0_RD_REQ_BIT (0x00000400)
+
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_LSB (9)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_WIDTH (1)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_MASK (0x00000200)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_BIT (0x00000200)
+
+#define DI_DEBUG_RAM_FULL_LSB (8)
+#define DI_DEBUG_RAM_FULL_WIDTH (1)
+#define DI_DEBUG_RAM_FULL_MASK (0x00000100)
+#define DI_DEBUG_RAM_FULL_BIT (0x00000100)
+
+#define DI_DEBUG_CHECK_DONE_LSB (7)
+#define DI_DEBUG_CHECK_DONE_WIDTH (1)
+#define DI_DEBUG_CHECK_DONE_MASK (0x00000080)
+#define DI_DEBUG_CHECK_DONE_BIT (0x00000080)
+
+#define DI_DEBUG_DI_OUT_BIT_FINISH_LSB (6)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_WIDTH (1)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_MASK (0x00000040)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_BIT (0x00000040)
+
+#define DI_DEBUG_RAM_ALL_RDATA_READ_LSB (5)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_WIDTH (1)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_MASK (0x00000020)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_BIT (0x00000020)
+
+#define DI_DEBUG_DI_BUSY_LSB (4)
+#define DI_DEBUG_DI_BUSY_WIDTH (1)
+#define DI_DEBUG_DI_BUSY_MASK (0x00000010)
+#define DI_DEBUG_DI_BUSY_BIT (0x00000010)
+
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_LSB (3)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_MASK (0x00000008)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_BIT (0x00000008)
+
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_LSB (2)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_WIDTH (1)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_MASK (0x00000004)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_BIT (0x00000004)
+
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_LSB (1)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_MASK (0x00000002)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_BIT (0x00000002)
+
+#define DI_DEBUG_CRC_BUF_OUT_SEL_LSB (0)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_MASK (0x00000001)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_BIT (0x00000001)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_LSB (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_WIDTH (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_MASK (0x0000FF00)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_WIDTH (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_MASK (0x000000FF)
+
+#define ENC_FSM_STATE_WT_CONV_STATE_LSB (17)
+#define ENC_FSM_STATE_WT_CONV_STATE_WIDTH (3)
+#define ENC_FSM_STATE_WT_CONV_STATE_MASK (0x000E0000)
+
+#define ENC_FSM_STATE_LTE_STATE_LSB (13)
+#define ENC_FSM_STATE_LTE_STATE_WIDTH (4)
+#define ENC_FSM_STATE_LTE_STATE_MASK (0x0001E000)
+
+#define ENC_FSM_STATE_CODEC_DIS_STATE_LSB (10)
+#define ENC_FSM_STATE_CODEC_DIS_STATE_WIDTH (3)
+#define ENC_FSM_STATE_CODEC_DIS_STATE_MASK (0x00001C00)
+
+#define ENC_FSM_STATE_CODEC_EN_STATE_LSB (6)
+#define ENC_FSM_STATE_CODEC_EN_STATE_WIDTH (4)
+#define ENC_FSM_STATE_CODEC_EN_STATE_MASK (0x000003C0)
+
+#define ENC_FSM_STATE_CODEC_W_STATE_LSB (3)
+#define ENC_FSM_STATE_CODEC_W_STATE_WIDTH (3)
+#define ENC_FSM_STATE_CODEC_W_STATE_MASK (0x00000038)
+
+#define ENC_FSM_STATE_CODEC_STATE_LSB (0)
+#define ENC_FSM_STATE_CODEC_STATE_WIDTH (3)
+#define ENC_FSM_STATE_CODEC_STATE_MASK (0x00000007)
+
+#define CRC_DBG_FLAG_CRC_LEN_DBG_LSB (26)
+#define CRC_DBG_FLAG_CRC_LEN_DBG_WIDTH (5)
+#define CRC_DBG_FLAG_CRC_LEN_DBG_MASK (0x7C000000)
+
+#define CRC_DBG_FLAG_RTT_RC_IDX_DBG_LSB (25)
+#define CRC_DBG_FLAG_RTT_RC_IDX_DBG_WIDTH (1)
+#define CRC_DBG_FLAG_RTT_RC_IDX_DBG_MASK (0x02000000)
+#define CRC_DBG_FLAG_RTT_RC_IDX_DBG_BIT (0x02000000)
+
+#define CRC_DBG_FLAG_CQI_OR_DATA_DBG_LSB (24)
+#define CRC_DBG_FLAG_CQI_OR_DATA_DBG_WIDTH (1)
+#define CRC_DBG_FLAG_CQI_OR_DATA_DBG_MASK (0x01000000)
+#define CRC_DBG_FLAG_CQI_OR_DATA_DBG_BIT (0x01000000)
+
+#define CRC_DBG_FLAG_CRC_STATE_DBG_LSB (16)
+#define CRC_DBG_FLAG_CRC_STATE_DBG_WIDTH (6)
+#define CRC_DBG_FLAG_CRC_STATE_DBG_MASK (0x003F0000)
+
+#define CRC_DBG_FLAG_BIT_CNT_DBG_LSB (0)
+#define CRC_DBG_FLAG_BIT_CNT_DBG_WIDTH (15)
+#define CRC_DBG_FLAG_BIT_CNT_DBG_MASK (0x00007FFF)
+
+#define INTLV_B_LWT_ST_0_LTE_WEN_ST_LSB (15)
+#define INTLV_B_LWT_ST_0_LTE_WEN_ST_WIDTH (3)
+#define INTLV_B_LWT_ST_0_LTE_WEN_ST_MASK (0x00038000)
+
+#define INTLV_B_LWT_ST_0_TS_W_STATE_LSB (12)
+#define INTLV_B_LWT_ST_0_TS_W_STATE_WIDTH (3)
+#define INTLV_B_LWT_ST_0_TS_W_STATE_MASK (0x00007000)
+
+#define INTLV_B_LWT_ST_0_TS_R_STATE_LSB (9)
+#define INTLV_B_LWT_ST_0_TS_R_STATE_WIDTH (3)
+#define INTLV_B_LWT_ST_0_TS_R_STATE_MASK (0x00000E00)
+
+#define INTLV_B_LWT_ST_0_PP_W_STATE_UPA_LSB (6)
+#define INTLV_B_LWT_ST_0_PP_W_STATE_UPA_WIDTH (3)
+#define INTLV_B_LWT_ST_0_PP_W_STATE_UPA_MASK (0x000001C0)
+
+#define INTLV_B_LWT_ST_0_PP_W_STATE_DCH_LSB (3)
+#define INTLV_B_LWT_ST_0_PP_W_STATE_DCH_WIDTH (3)
+#define INTLV_B_LWT_ST_0_PP_W_STATE_DCH_MASK (0x00000038)
+
+#define INTLV_B_LWT_ST_0_SEC_INTLV_STATE_LSB (0)
+#define INTLV_B_LWT_ST_0_SEC_INTLV_STATE_WIDTH (3)
+#define INTLV_B_LWT_ST_0_SEC_INTLV_STATE_MASK (0x00000007)
+
+#define INTLV_B_LWT_ST_1_CLM_CNT_LSB (25)
+#define INTLV_B_LWT_ST_1_CLM_CNT_WIDTH (5)
+#define INTLV_B_LWT_ST_1_CLM_CNT_MASK (0x3E000000)
+
+#define INTLV_B_LWT_ST_1_ROW_CNT_LSB (22)
+#define INTLV_B_LWT_ST_1_ROW_CNT_WIDTH (3)
+#define INTLV_B_LWT_ST_1_ROW_CNT_MASK (0x01C00000)
+
+#define INTLV_B_LWT_ST_1_BLK_CNT_LSB (14)
+#define INTLV_B_LWT_ST_1_BLK_CNT_WIDTH (8)
+#define INTLV_B_LWT_ST_1_BLK_CNT_MASK (0x003FC000)
+
+#define INTLV_B_LWT_ST_1_SEC_REQO_LSB (13)
+#define INTLV_B_LWT_ST_1_SEC_REQO_WIDTH (1)
+#define INTLV_B_LWT_ST_1_SEC_REQO_MASK (0x00002000)
+#define INTLV_B_LWT_ST_1_SEC_REQO_BIT (0x00002000)
+
+#define INTLV_B_LWT_ST_1_PPR_REQ_UPA_LSB (9)
+#define INTLV_B_LWT_ST_1_PPR_REQ_UPA_WIDTH (4)
+#define INTLV_B_LWT_ST_1_PPR_REQ_UPA__MASK (0x00001E00)
+
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_UPA_LSB (5)
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_UPA_WIDTH (4)
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_UPA_MASK (0x000001E0)
+
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_LSB (4)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_WIDTH (1)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_MASK (0x00000010)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_BIT (0x00000010)
+
+#define INTLV_B_LWT_ST_1_PPR_REQ_DCH_LSB (3)
+#define INTLV_B_LWT_ST_1_PPR_REQ_DCH_WIDTH (1)
+#define INTLV_B_LWT_ST_1_PPR_REQ_DCH_MASK (0x00000008)
+#define INTLV_B_LWT_ST_1_PPR_REQ_DCH_BIT (0x00000008)
+
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_LSB (2)
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_WIDTH (1)
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_MASK (0x00000004)
+#define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_BIT (0x00000004)
+
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_LSB (1)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_WIDTH (1)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_MASK (0x00000002)
+#define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_BIT (0x00000002)
+
+#define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_LSB (0)
+#define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_WIDTH (1)
+#define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_MASK (0x00000001)
+#define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_BIT (0x00000001)
+
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_LSB (20)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_WIDTH (6)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_MASK (0x03F00000)
+
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_LSB (0)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_WIDTH (20)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_MASK (0x000FFFFF)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_LSB (16)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_WIDTH (4)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_MASK (0x000F0000)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_LSB (7)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_WIDTH (9)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_MASK (0x0000FF80)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_LSB (0)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_WIDTH (7)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_MASK (0x0000007F)
+
+#define RM_FSM_STATE_BIT_SEP_STATE_LSB (16)
+#define RM_FSM_STATE_BIT_SEP_STATE_WIDTH (3)
+#define RM_FSM_STATE_BIT_SEP_STATE_MASK (0x00070000)
+
+#define RM_FSM_STATE_BC_STATE_LSB (0)
+#define RM_FSM_STATE_BC_STATE_WIDTH (16)
+#define RM_FSM_STATE_BC_STATE_MASK (0x0000FFFF)
+
+#define RUMAP_FSM_STATE_BUF_STATE_LSB (5)
+#define RUMAP_FSM_STATE_BUF_STATE_WIDTH (1)
+#define RUMAP_FSM_STATE_BUF_STATE_MASK (0x00000020)
+#define RUMAP_FSM_STATE_BUF_STATE_BIT (0x00000020)
+
+#define RUMAP_FSM_STATE_RU_MAP_STATE_LSB (0)
+#define RUMAP_FSM_STATE_RU_MAP_STATE_WIDTH (5)
+#define RUMAP_FSM_STATE_RU_MAP_STATE_MASK (0x0000001F)
+
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_LSB (1)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_WIDTH (1)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_MASK (0x00000002)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_BIT (0x00000002)
+
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_LSB (0)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_WIDTH (1)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_MASK (0x00000001)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_BIT (0x00000001)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_LSB (13)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_MASK (0x00006000)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_LSB (11)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_MASK (0x00001800)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_LSB (9)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_MASK (0x00000600)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_LSB (7)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_MASK (0x00000180)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_LSB (5)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_MASK (0x00000060)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_LSB (4)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_MASK (0x00000010)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_BIT (0x00000010)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_LSB (3)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_MASK (0x00000008)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_BIT (0x00000008)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_LSB (2)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_MASK (0x00000004)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_BIT (0x00000004)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_LSB (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_MASK (0x00000002)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_BIT (0x00000002)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_LSB (0)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_MASK (0x00000001)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_BIT (0x00000001)
+
+#define C2K_READ_RST_LSB (0)
+#define C2K_READ_RST_WIDTH (1)
+#define C2K_READ_RST_MASK (0x00000001)
+#define C2K_READ_RST_BIT (0x00000001)
+
+#define RTT_START_LSB (0)
+#define RTT_START_WIDTH (1)
+#define RTT_START_MASK (0x00000001)
+#define RTT_START_BIT (0x00000001)
+
+#define TXA_INPUT_LEN_LSB (0)
+#define TXA_INPUT_LEN_WIDTH (13)
+#define TXA_INPUT_LEN_MASK (0x00001FFF)
+
+#define TXA_PUNC_LSB (0)
+#define TXA_PUNC_WIDTH (5)
+#define TXA_PUNC_MASK (0x0000001F)
+
+#define TXA_HA_MODE_TX_SUP_CH_REP_LSB (10)
+#define TXA_HA_MODE_TX_SUP_CH_REP_WIDTH (3)
+#define TXA_HA_MODE_TX_SUP_CH_REP_MASK (0x00001C00)
+
+#define TXA_HA_MODE_TX_CLK_EN_LSB (9)
+#define TXA_HA_MODE_TX_CLK_EN_WIDTH (1)
+#define TXA_HA_MODE_TX_CLK_EN_MASK (0x00000200)
+#define TXA_HA_MODE_TX_CLK_EN_BIT (0x00000200)
+
+#define TXA_HA_MODE_TURBO_TEST_LSB (8)
+#define TXA_HA_MODE_TURBO_TEST_WIDTH (1)
+#define TXA_HA_MODE_TURBO_TEST_MASK (0x00000100)
+#define TXA_HA_MODE_TURBO_TEST_BIT (0x00000100)
+
+#define TXA_HA_MODE_INTRLV_RATE_LSB (6)
+#define TXA_HA_MODE_INTRLV_RATE_WIDTH (2)
+#define TXA_HA_MODE_INTRLV_RATE_MASK (0x000000C0)
+
+#define TXA_HA_MODE_INTRLV_TYPE_LSB (4)
+#define TXA_HA_MODE_INTRLV_TYPE_WIDTH (2)
+#define TXA_HA_MODE_INTRLV_TYPE_MASK (0x00000030)
+
+#define TXA_HA_MODE_ENC_RATE_LSB (2)
+#define TXA_HA_MODE_ENC_RATE_WIDTH (2)
+#define TXA_HA_MODE_ENC_RATE_MASK (0x0000000C)
+
+#define TXA_HA_MODE_ENC_TYPE_LSB (1)
+#define TXA_HA_MODE_ENC_TYPE_WIDTH (1)
+#define TXA_HA_MODE_ENC_TYPE_MASK (0x00000002)
+#define TXA_HA_MODE_ENC_TYPE_BIT (0x00000002)
+
+#define TXA_HA_MODE_TX_HA_MEM_RST_LSB (0)
+#define TXA_HA_MODE_TX_HA_MEM_RST_WIDTH (1)
+#define TXA_HA_MODE_TX_HA_MEM_RST_MASK (0x00000001)
+#define TXA_HA_MODE_TX_HA_MEM_RST_BIT (0x00000001)
+
+#define TXA_INTRLV_PARM_BLK_J1_LSB (9)
+#define TXA_INTRLV_PARM_BLK_J1_WIDTH (3)
+#define TXA_INTRLV_PARM_BLK_J1_MASK (0x00000E00)
+
+#define TXA_INTRLV_PARM_BLK_J0_LSB (6)
+#define TXA_INTRLV_PARM_BLK_J0_WIDTH (3)
+#define TXA_INTRLV_PARM_BLK_J0_MASK (0x000001C0)
+
+#define TXA_INTRLV_PARM_BLK_M_LSB (4)
+#define TXA_INTRLV_PARM_BLK_M_WIDTH (2)
+#define TXA_INTRLV_PARM_BLK_M_MASK (0x00000030)
+
+#define TXA_INTRLV_PARM_TURBO_N_LSB (0)
+#define TXA_INTRLV_PARM_TURBO_N_WIDTH (3)
+#define TXA_INTRLV_PARM_TURBO_N_MASK (0x00000007)
+
+#define TXA_FREP_L_LSB (0)
+#define TXA_FREP_L_WIDTH (14)
+#define TXA_FREP_L_MASK (0x00003FFF)
+
+#define CHL_TYPE_LSB (0)
+#define CHL_TYPE_WIDTH (2)
+#define CHL_TYPE_MASK (0x00000003)
+
+#define TXA_CRC_RTT_RC_IDX_LSB (5)
+#define TXA_CRC_RTT_RC_IDX_WIDTH (1)
+#define TXA_CRC_RTT_RC_IDX_MASK (0x00000020)
+#define TXA_CRC_RTT_RC_IDX_BIT (0x00000020)
+
+#define TXA_CRC_TXA_CRC_LEN_LSB (0)
+#define TXA_CRC_TXA_CRC_LEN_WIDTH (5)
+#define TXA_CRC_TXA_CRC_LEN_MASK (0x0000001F)
+
+#define TXA_FREP_LPML_LSB (0)
+#define TXA_FREP_LPML_WIDTH (15)
+#define TXA_FREP_LPML_MASK (0x00007FFF)
+
+#define TXA_FREP_MM1_LSB (0)
+#define TXA_FREP_MM1_WIDTH (15)
+#define TXA_FREP_MM1_MASK (0x00007FFF)
+
+#define TXA_FREP_ACC0_LSB (0)
+#define TXA_FREP_ACC0_WIDTH (15)
+#define TXA_FREP_ACC0_MASK (0x00007FFF)
+
+#define TXA_PUNC_PAT0_LSB (0)
+#define TXA_PUNC_PAT0_WIDTH (16)
+#define TXA_PUNC_PAT0_MASK (0x0000FFFF)
+
+#define TXA_PUNC_PAT1_LSB (0)
+#define TXA_PUNC_PAT1_WIDTH (16)
+#define TXA_PUNC_PAT1_MASK (0x0000FFFF)
+
+#define TXA_FREP_LP_LSB (0)
+#define TXA_FREP_LP_WIDTH (15)
+#define TXA_FREP_LP_MASK (0x00007FFF)
+
+#define TXA_TST_CTRL_TXA_ADD_LSB (2)
+#define TXA_TST_CTRL_TXA_ADD_WIDTH (11)
+#define TXA_TST_CTRL_TXA_ADD_MASK (0x00001FFC)
+
+#define TXA_TST_CTRL_TXA_ADD_MD_LSB (1)
+#define TXA_TST_CTRL_TXA_ADD_MD_WIDTH (1)
+#define TXA_TST_CTRL_TXA_ADD_MD_MASK (0x00000002)
+#define TXA_TST_CTRL_TXA_ADD_MD_BIT (0x00000002)
+
+#define TXA_TST_CTRL_TXA_TST_MD_LSB (0)
+#define TXA_TST_CTRL_TXA_TST_MD_WIDTH (1)
+#define TXA_TST_CTRL_TXA_TST_MD_MASK (0x00000001)
+#define TXA_TST_CTRL_TXA_TST_MD_BIT (0x00000001)
+
+#define RTT_CHNL_BASE_ADDR_LSB (0)
+#define RTT_CHNL_BASE_ADDR_WIDTH (32)
+#define RTT_CHNL_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_LSB (2)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_WIDTH (1)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_MASK (0x00000004)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_BIT (0x00000004)
+
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_LSB (1)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_WIDTH (1)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_MASK (0x00000002)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_BIT (0x00000002)
+
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_LSB (0)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_WIDTH (1)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_MASK (0x00000001)
+#define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_BIT (0x00000001)
+
+#define TXBRP_DBG_CRC32_RSLT_I_LSB (0)
+#define TXBRP_DBG_CRC32_RSLT_I_WIDTH (24)
+#define TXBRP_DBG_CRC32_RSLT_I_MASK (0x00FFFFFF)
+
+#define TXBRP_DBG_CRC32_RSLT_Q_LSB (0)
+#define TXBRP_DBG_CRC32_RSLT_Q_WIDTH (24)
+#define TXBRP_DBG_CRC32_RSLT_Q_MASK (0x00FFFFFF)
+
+#define DEBUG_CRC_SEL_LSB (0)
+#define DEBUG_CRC_SEL_WIDTH (4)
+#define DEBUG_CRC_SEL_MASK (0x0000000F)
+
+#endif //#ifndef _CPH_1X_TXBRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xtxcrp.h b/mcu/interface/l1/cl1/common/HW/cph1xtxcrp.h
new file mode 100644
index 0000000..cfe1355
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xtxcrp.h
@@ -0,0 +1,271 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_TXCRP_H_
+#define _CPH_1X_TXCRP_H_
+
+/** TBD: Common register read and write function, maybe replaced later */
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXCRP_C_1XRTT_REG_BASE (0xa8160000)
+#else
+#define TXCRP_C_1XRTT_REG_BASE (0xa8960000)
+#endif
+#define TXCRP_C_1XRTT_end (TXCRP_C_1XRTT_REG_BASE + 0x0064 + 1*4)
+
+#define C1XTXCRP_ACK1_BIT ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0000))
+#define C1XTXCRP_CTRL ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0004))
+#define C1XTXCRP_PC_BIT_EPM ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0008))
+#define C1XTXCRP_FCH_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x000C))
+#define C1XTXCRP_SCH_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0010))
+#define C1XTXCRP_PILOT_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0014))
+#define C1XTXCRP_ACKCH1_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0018))
+#define C1XTXCRP_TEST_CTRL ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x001C))
+#define C1XTXCRP_LC_INIT_0 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0020))
+#define C1XTXCRP_LC_INIT_1 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0024))
+#define C1XTXCRP_LC_INIT_2 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0028))
+#define C1XTXCRP_LC_MASK_0 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x002C))
+#define C1XTXCRP_LC_MASK_1 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0030))
+#define C1XTXCRP_LC_MASK_2 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0034))
+#define C1XTXCRP_LC_SCRAMBLE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0038))
+#define C1XTXCRP_ACTIVE_STOP ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x003C))
+#define C1XTXCRP_SC_INIT_PCG ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0040))
+#define C1XTXCRP_FCH_STATUS ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0044))
+#define C1XTXCRP_KS_START ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0048))
+#define C1XTXCRP_KS_SQUARE_DB_RESULT ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x004C))
+#define C1XTXCRP_PCG_INDEX_EPM ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0054))
+#define C1XTXCRP_TXBRP_MEM_END_EPM ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0058))
+#define C1XTXCRP_DEBUG_OB_0 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x005C))
+#define C1XTXCRP_DEBUG_OB_1 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0060))
+#define C1XTXCRP_LATCH_SWITCH ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0064))
+//#define C1XTXCRP_SW_RESET ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0068))
+
+/** Register filed definition */
+#define ACKCH1_RESULT_LSB (0)
+#define ACKCH1_RESULT_WIDTH (1)
+#define ACKCH1_RESULT_MASK (0x00000001)
+#define ACKCH1_RESULT_BIT (0x00000001)
+
+#define ACKCH1_EN_LSB (8)
+#define ACKCH1_EN_WIDTH (1)
+#define ACKCH1_EN_MASK (0x00000100)
+#define ACKCH1_EN_BIT (0x00000100)
+
+#define SCH_WALSH_COVER_LSB (6)
+#define SCH_WALSH_COVER_WIDTH (2)
+#define SCH_WALSH_COVER_MASK (0x000000C0)
+
+#define PILOT_EN_LSB (5)
+#define PILOT_EN_WIDTH (1)
+#define PILOT_EN_MASK (0x00000020)
+#define PILOT_EN_BIT (0x00000020)
+
+#define SCH_EN_LSB (4)
+#define SCH_EN_WIDTH (1)
+#define SCH_EN_MASK (0x00000010)
+#define SCH_EN_BIT (0x00000010)
+
+#define FCH_EN_LSB (2)
+#define FCH_EN_WIDTH (1)
+#define FCH_EN_MASK (0x00000004)
+#define FCH_EN_BIT (0x00000004)
+
+#define IS95_EN_LSB (0)
+#define IS95_EN_WIDTH (1)
+#define IS95_EN_MASK (0x00000001)
+#define IS95_EN_BIT (0x00000001)
+
+#define PC_BIT_MANUAL_LSB (1)
+#define PC_BIT_MANUAL_WIDTH (1)
+#define PC_BIT_MANUAL_MASK (0x00000002)
+#define PC_BIT_MANUAL_BIT (0x00000002)
+
+#define PC_BIT_MANUAL_EN_LSB (0)
+#define PC_BIT_MANUAL_EN_WIDTH (1)
+#define PC_BIT_MANUAL_EN_MASK (0x00000001)
+#define PC_BIT_MANUAL_EN_BIT (0x00000001)
+
+#define FCH_SCALE_LSB (0)
+#define FCH_SCALE_WIDTH (9)
+#define FCH_SCALE_MASK (0x000001FF)
+
+#define SCH_SCALE_LSB (0)
+#define SCH_SCALE_WIDTH (9)
+#define SCH_SCALE_MASK (0x000001FF)
+
+#define PILOT_SCALE_LSB (0)
+#define PILOT_SCALE_WIDTH (9)
+#define PILOT_SCALE_MASK (0x000001FF)
+
+#define ACKCH1_SCALE_LSB (0)
+#define ACKCH1_SCALE_WIDTH (9)
+#define ACKCH1_SCALE_MASK (0x000001FF)
+
+#define TESTCTRL_HW_CLKEN_BYP_LSB (1)
+#define TESTCTRL_HW_CLKEN_BYP_WIDTH (1)
+#define TESTCTRL_HW_CLKEN_BYP_MASK (0x00000002)
+#define TESTCTRL_HW_CLKEN_BYP_BIT (0x00000002)
+
+#define TESTCTRL_CONJUGATE_LSB (0)
+#define TESTCTRL_CONJUGATE_WIDTH (1)
+#define TESTCTRL_CONJUGATE_MASK (0x00000001)
+#define TESTCTRL_CONJUGATE_BIT (0x00000001)
+
+#define LC_INIT_VALUE_15_0_LSB (0)
+#define LC_INIT_VALUE_15_0_WIDTH (16)
+#define LC_INIT_VALUE_15_0_MASK (0x0000FFFF)
+
+#define LC_INIT_VALUE_31_16_LSB (0)
+#define LC_INIT_VALUE_31_16_WIDTH (16)
+#define LC_INIT_VALUE_31_16_MASK (0x0000FFFF)
+
+#define LC_INIT_VALUE_41_32_LSB (0)
+#define LC_INIT_VALUE_41_32_WIDTH (10)
+#define LC_INIT_VALUE_41_32_MASK (0x000003FF)
+
+#define LC_MASK_15_0_LSB (0)
+#define LC_MASK_15_0_WIDTH (16)
+#define LC_MASK_15_0_MASK (0x0000FFFF)
+
+#define LC_MASK_31_16_LSB (0)
+#define LC_MASK_31_16_WIDTH (16)
+#define LC_MASK_31_16_MASK (0x0000FFFF)
+
+#define LC_MASK_41_32_LSB (0)
+#define LC_MASK_41_32_WIDTH (10)
+#define LC_MASK_41_32_MASK (0x000003FF)
+
+#define LC_SCRAMBLE_LSB (0)
+#define LC_SCRAMBLE_WIDTH (14)
+#define LC_SCRAMBLE_MASK (0x00003FFF)
+
+#define ACTIVE_EN_LSB (1)
+#define ACTIVE_EN_WIDTH (1)
+#define ACTIVE_EN_MASK (0x00000002)
+#define ACTIVE_EN_BIT (0x00000002)
+
+#define STOP_BY_PCG_LSB (0)
+#define STOP_BY_PCG_WIDTH (1)
+#define STOP_BY_PCG_MASK (0x00000001)
+#define STOP_BY_PCG_BIT (0x00000001)
+
+#define SC_INIT_PCG_LSB (1)
+#define SC_INIT_PCG_WIDTH (6)
+#define SC_INIT_PCG_MASK (0x0000007E)
+
+#define SC_INIT_PCG_START_LSB (0)
+#define SC_INIT_PCG_START_WIDTH (1)
+#define SC_INIT_PCG_START_MASK (0x00000001)
+#define SC_INIT_PCG_START_BIT (0x00000001)
+
+#define FCH_PREAMBLE_EN_LSB (1)
+#define FCH_PREAMBLE_EN_WIDTH (1)
+#define FCH_PREAMBLE_EN_MASK (0x00000002)
+#define FCH_PREAMBLE_EN_BIT (0x00000002)
+
+#define FCH_GATING_EN_LSB (0)
+#define FCH_GATING_EN_WIDTH (1)
+#define FCH_GATING_EN_MASK (0x00000001)
+#define FCH_GATING_EN_BIT (0x00000001)
+
+#define KS_CALC_START_LSB (1)
+#define KS_CALC_START_WIDTH (1)
+#define KS_CALC_START_MASK (0x00000002)
+#define KS_CALC_START_BIT (0x00000002)
+
+#define KS_CALC_MANUAL_LSB (0)
+#define KS_CALC_MANUAL_WIDTH (1)
+#define KS_CALC_MANUAL_MASK (0x00000001)
+#define KS_CALC_MANUAL_BIT (0x00000001)
+
+#define KS_CALC_RESULT_LSB (1)
+#define KS_CALC_RESULT_WIDTH (13)
+#define KS_CALC_RESULT_MASK (0x00003FFE)
+
+#define KS_CALC_FINISH_LSB (0)
+#define KS_CALC_FINISH_WIDTH (1)
+#define KS_CALC_FINISH_MASK (0x00000001)
+#define KS_CALC_FINISH_BIT (0x00000001)
+
+#define PCG_INDEX_MANUAL_LSB (1)
+#define PCG_INDEX_MANUAL_WIDTH (4)
+#define PCG_INDEX_MANUAL_MASK (0x0000001E)
+
+#define PCG_INDEX_MANUAL_EN_LSB (0)
+#define PCG_INDEX_MANUAL_EN_WIDTH (1)
+#define PCG_INDEX_MANUAL_EN_MASK (0x00000001)
+#define PCG_INDEX_MANUAL_EN_BIT (0x00000001)
+
+#define TXBRP_ADDR_2_MANUAL_EN_LSB (10)
+#define TXBRP_ADDR_2_MANUAL_EN_WIDTH (10)
+#define TXBRP_ADDR_2_MANUAL_EN_MASK (0x000FFC00)
+
+#define TXBRP_ADDR_1_MANUAL_EN_LSB (1)
+#define TXBRP_ADDR_1_MANUAL_EN_WIDTH (9)
+#define TXBRP_ADDR_1_MANUAL_EN_MASK (0x000003FE)
+
+#define TXBRP_ADDR_MANUAL_EN_LSB (0)
+#define TXBRP_ADDR_MANUAL_EN_WIDTH (1)
+#define TXBRP_ADDR_MANUAL_EN_MASK (0x00000001)
+#define TXBRP_ADDR_MANUAL_EN_BIT (0x00000001)
+
+#define HW_DEBUG_OB_31_0_LSB (0)
+#define HW_DEBUG_OB_31_0_WIDTH (32)
+#define HW_DEBUG_OB_31_0_MASK (0xFFFFFFFF)
+
+#define HW_DEBUG_OB_63_32_LSB (0)
+#define HW_DEBUG_OB_63_32_WIDTH (32)
+#define HW_DEBUG_OB_63_32_MASK (0xFFFFFFFF)
+
+#define LATCH_SWITCH_LSB (0)
+#define LATCH_SWITCH_WIDTH (1)
+#define LATCH_SWITCH_MASK (0x00000001)
+#define LATCH_SWITCH_BIT (0x00000001)
+
+#define SW_RST_LSB (0)
+#define SW_RST_WIDTH (1)
+#define SW_RST_MASK (0x00000001)
+#define SW_RST_BIT (0x00000001)
+
+
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xtxtmr.h b/mcu/interface/l1/cl1/common/HW/cph1xtxtmr.h
new file mode 100644
index 0000000..5e2849a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xtxtmr.h
@@ -0,0 +1,65 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_TXTRM_H_
+#define _CPH_1X_TX_TRM_H_
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define TXTMR_C_1XRTT_REG_BASE (0) /**TBD*/
+
+#define C1XTXTMR_ENABLE ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0000))
+#define C1XTXTMR_FRAME_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0004))
+#define C1XTXTMR_TRX_DLY ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0008))
+#define C1XTXTMR_RA_DLY ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x000C))
+#define C1XTXTMR_TXDFE_WIN_ON_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0010))
+#define C1XTXTMR_TXDFE_WIN_OFF_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0014))
+#define C1XTXTMR_TXDFE_FIFO_WIN_ON_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0018))
+#define C1XTXTMR_TXDFE_FIFO_WIN_OFF_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x001C))
+#define C1XTXTMR_TXDAC_WIN_ON_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0020))
+#define C1XTXTMR_TXDAC_WIN_OFF_OFFSET ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0024))
+#define C1XTXTMR_TXBRP_STR ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0028))
+#define C1XTXTMR_TXCRP_STR ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x002C))
+#define C1XTXTMR_KS_STR ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0030))
+#define C1XTXTMR_SYSTMR_CNT ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0034))
+
+
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphb2rif.h b/mcu/interface/l1/cl1/common/HW/cphb2rif.h
new file mode 100644
index 0000000..b6e5d9a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphb2rif.h
@@ -0,0 +1,39 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__) || defined(__MD95__)
+#include "cphb2rif_93_95.h"
+#else
+#include "cphb2rif_97.h"
+#endif
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphb2rif_93_95.h b/mcu/interface/l1/cl1/common/HW/cphb2rif_93_95.h
new file mode 100644
index 0000000..97293d6
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphb2rif_93_95.h
@@ -0,0 +1,228 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _EL1D_REG_ELBRUS_H_
+#define _EL1D_REG_ELBRUS_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define B2RIF_REG_BASE (0xAC100000)
+
+#define B2RIF_end (B2RIF_REG_BASE + 0x003C + 1*4)
+
+
+
+#define B2RIF_CON ((APBADDR32)(B2RIF_REG_BASE + 0x0000))
+#define B2RIF_SW_RST ((APBADDR32)(B2RIF_REG_BASE + 0x0004))
+#define B2RIF_2SLOT_IND ((APBADDR32)(B2RIF_REG_BASE + 0x0008))
+#define B2RIF_DIS ((APBADDR32)(B2RIF_REG_BASE + 0x000C))
+#define B2RIF_DBG_CON ((APBADDR32)(B2RIF_REG_BASE + 0x0010))
+#define B2RIF_RREQ_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x0014))
+#define B2RIF_RRDY_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x0018))
+#define B2RIF_LREQ_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x001C))
+#define B2RIF_R_CON_A0C0_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0020))
+#define B2RIF_R_CON_A1C0_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0024))
+#define B2RIF_R_CON_A0C1_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0028))
+#define B2RIF_R_CON_A1C1_0 ((APBADDR32)(B2RIF_REG_BASE + 0x002C))
+#define B2RIF_R_CON_A0C0_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0030))
+#define B2RIF_R_CON_A1C0_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0034))
+#define B2RIF_R_CON_A0C1_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0038))
+#define B2RIF_R_CON_A1C1_1 ((APBADDR32)(B2RIF_REG_BASE + 0x003C))
+#define B2RIF_R_CON_QLIC_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0040))
+#define B2RIF_R_CON_QLIC_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0044))
+#define B2RIF_HOLD_STA ((APBADDR32)(B2RIF_REG_BASE + 0x0048))
+
+
+#define B2RIF_CON_B2RIF_MODE_LSB (2)
+#define B2RIF_CON_B2RIF_MODE_WIDTH (2)
+#define B2RIF_CON_B2RIF_MODE_MASK (0x0000000C)
+
+#define B2RIF_CON_B2RIF_QLIC_EN_LSB (1)
+#define B2RIF_CON_B2RIF_QLIC_EN_WIDTH (1)
+#define B2RIF_CON_B2RIF_QLIC_EN_MASK (0x00000002)
+#define B2RIF_CON_B2RIF_QLIC_EN_BIT (0x00000002)
+
+#define B2RIF_CON_B2RIF_EN_LSB (0)
+#define B2RIF_CON_B2RIF_EN_WIDTH (1)
+#define B2RIF_CON_B2RIF_EN_MASK (0x00000001)
+#define B2RIF_CON_B2RIF_EN_BIT (0x00000001)
+
+#define B2RIF_SW_RST_B2RIF_SW_RST_LSB (0)
+#define B2RIF_SW_RST_B2RIF_SW_RST_WIDTH (1)
+#define B2RIF_SW_RST_B2RIF_SW_RST_MASK (0x00000001)
+#define B2RIF_SW_RST_B2RIF_SW_RST_BIT (0x00000001)
+
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_LSB (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_WIDTH (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_MASK (0x00000002)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_BIT (0x00000002)
+
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_LSB (0)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_WIDTH (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_MASK (0x00000001)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_BIT (0x00000001)
+
+#define B2RIF_DIS_LDR_REQ_DIS_LSB (3)
+#define B2RIF_DIS_LDR_REQ_DIS_WIDTH (1)
+#define B2RIF_DIS_LDR_REQ_DIS_MASK (0x00000008)
+#define B2RIF_DIS_LDR_REQ_DIS_BIT (0x00000008)
+
+#define B2RIF_DIS_BRAM_READ0_DIS_LSB (2)
+#define B2RIF_DIS_BRAM_READ0_DIS_WIDTH (1)
+#define B2RIF_DIS_BRAM_READ0_DIS_MASK (0x00000004)
+#define B2RIF_DIS_BRAM_READ0_DIS_BIT (0x00000004)
+
+#define B2RIF_DIS_BRAM_READ1_DIS_LSB (1)
+#define B2RIF_DIS_BRAM_READ1_DIS_WIDTH (1)
+#define B2RIF_DIS_BRAM_READ1_DIS_MASK (0x00000002)
+#define B2RIF_DIS_BRAM_READ1_DIS_BIT (0x00000002)
+
+#define B2RIF_DIS_LDR_LPWR_DIS_LSB (0)
+#define B2RIF_DIS_LDR_LPWR_DIS_WIDTH (1)
+#define B2RIF_DIS_LDR_LPWR_DIS_MASK (0x00000001)
+#define B2RIF_DIS_LDR_LPWR_DIS_BIT (0x00000001)
+
+#define B2RIF_DBG_CON_DBG_CLR_LSB (4)
+#define B2RIF_DBG_CON_DBG_CLR_WIDTH (1)
+#define B2RIF_DBG_CON_DBG_CLR_MASK (0x00000010)
+#define B2RIF_DBG_CON_DBG_CLR_BIT (0x00000010)
+
+#define B2RIF_DBG_CON_DBG_EN_LSB (0)
+#define B2RIF_DBG_CON_DBG_EN_WIDTH (1)
+#define B2RIF_DBG_CON_DBG_EN_MASK (0x00000001)
+#define B2RIF_DBG_CON_DBG_EN_BIT (0x00000001)
+
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_LSB (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_WIDTH (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_MASK (0x0000FF00)
+
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_LSB (0)
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_WIDTH (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_MASK (0x000000FF)
+
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_LSB (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_WIDTH (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_MASK (0x0000FF00)
+
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_LSB (0)
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_WIDTH (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_MASK (0x000000FF)
+
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_LSB (0)
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_WIDTH (8)
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_MASK (0x000000FF)
+
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_LSB (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_LSB (0)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_LSB (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_LSB (0)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_LSB (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_LSB (0)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_LSB (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_LSB (0)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_LSB (0)
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_LSB (0)
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_LSB (0)
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_LSB (0)
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_LSB (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_MASH (0xFFFF0000)
+
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_LSB (0)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_MASH (0x0000FFFF)
+
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_LSB (0)
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_MASH (0x0000FFFF)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_REAL_LSB (16)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_REAL_WIDTH (16)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_REAL_MASH (0xFFFF0000)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_LSB (8)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_WIDTH (1)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_MASH (0x00000100)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_MAX_LSB (0)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_MAX_WIDTH (8)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_MAX_MASH (0x000000FF)
+
+#endif //#ifndef _EL1D_REG_ELBRUS_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphb2rif_97.h b/mcu/interface/l1/cl1/common/HW/cphb2rif_97.h
new file mode 100644
index 0000000..f8b3b6d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphb2rif_97.h
@@ -0,0 +1,261 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_B2RIF_97_H_
+#define _CPH_B2RIF_97_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define B2RIF_REG_BASE (0xACD00000)
+
+#define B2RIF_end (B2RIF_REG_BASE + 0x0108 + 1*4)
+
+
+
+#define B2RIF_CON ((APBADDR32)(B2RIF_REG_BASE + 0x0000))
+#define B2RIF_SW_RST ((APBADDR32)(B2RIF_REG_BASE + 0x0004))
+#define B2RIF_2SLOT_IND ((APBADDR32)(B2RIF_REG_BASE + 0x0008))
+#define B2RIF_DIS ((APBADDR32)(B2RIF_REG_BASE + 0x000C))
+#define B2RIF_DBG_CON ((APBADDR32)(B2RIF_REG_BASE + 0x0010))
+#define B2RIF_RREQ_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x0014))
+#define B2RIF_RRDY_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x0018))
+#define B2RIF_LREQ_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x001C))
+#define B2RIF_R_CON_A0C0_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0020))
+#define B2RIF_R_CON_A1C0_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0024))
+#define B2RIF_R_CON_A0C1_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0028))
+#define B2RIF_R_CON_A1C1_0 ((APBADDR32)(B2RIF_REG_BASE + 0x002C))
+#define B2RIF_R_CON_A0C0_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0030))
+#define B2RIF_R_CON_A1C0_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0034))
+#define B2RIF_R_CON_A0C1_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0038))
+#define B2RIF_R_CON_A1C1_1 ((APBADDR32)(B2RIF_REG_BASE + 0x003C))
+#define B2RIF_R_CON_QLIC_0 ((APBADDR32)(B2RIF_REG_BASE + 0x0040))
+#define B2RIF_R_CON_QLIC_1 ((APBADDR32)(B2RIF_REG_BASE + 0x0044))
+#define B2RIF_HOLD_STA ((APBADDR32)(B2RIF_REG_BASE + 0x0048))
+#define B2RIF_RESERVED0 ((APBADDR32)(B2RIF_REG_BASE + 0x004c))
+#define B2RIF_RESERVED1 ((APBADDR32)(B2RIF_REG_BASE + 0x0050))
+#define IC_SYNC ((APBADDR32)(B2RIF_REG_BASE + 0x0100))
+#define IC_SYNC_SYS_CNT ((APBADDR32)(B2RIF_REG_BASE + 0x0104))
+#define IC_SYNC_IC_ADDR ((APBADDR32)(B2RIF_REG_BASE + 0x0108))
+
+
+
+
+#define B2RIF_CON_B2RIF_MODE_LSB (2)
+#define B2RIF_CON_B2RIF_MODE_WIDTH (2)
+#define B2RIF_CON_B2RIF_MODE_MASK (0x0000000C)
+
+#define B2RIF_CON_B2RIF_EN_LSB (0)
+#define B2RIF_CON_B2RIF_EN_WIDTH (1)
+#define B2RIF_CON_B2RIF_EN_MASK (0x00000001)
+#define B2RIF_CON_B2RIF_EN_BIT (0x00000001)
+
+#define B2RIF_SW_RST_B2RIF_SW_RST_LSB (0)
+#define B2RIF_SW_RST_B2RIF_SW_RST_WIDTH (1)
+#define B2RIF_SW_RST_B2RIF_SW_RST_MASK (0x00000001)
+#define B2RIF_SW_RST_B2RIF_SW_RST_BIT (0x00000001)
+
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_LSB (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_WIDTH (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_MASK (0x00000002)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_1_BIT (0x00000002)
+
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_LSB (0)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_WIDTH (1)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_MASK (0x00000001)
+#define B2RIF_2SLOT_IND_B2RIF_2SLOT_IND_0_BIT (0x00000001)
+
+#define B2RIF_DIS_LDR_REQ_DIS_LSB (3)
+#define B2RIF_DIS_LDR_REQ_DIS_WIDTH (1)
+#define B2RIF_DIS_LDR_REQ_DIS_MASK (0x00000008)
+#define B2RIF_DIS_LDR_REQ_DIS_BIT (0x00000008)
+
+#define B2RIF_DIS_BRAM_READ0_DIS_LSB (2)
+#define B2RIF_DIS_BRAM_READ0_DIS_WIDTH (1)
+#define B2RIF_DIS_BRAM_READ0_DIS_MASK (0x00000004)
+#define B2RIF_DIS_BRAM_READ0_DIS_BIT (0x00000004)
+
+#define B2RIF_DIS_BRAM_READ1_DIS_LSB (1)
+#define B2RIF_DIS_BRAM_READ1_DIS_WIDTH (1)
+#define B2RIF_DIS_BRAM_READ1_DIS_MASK (0x00000002)
+#define B2RIF_DIS_BRAM_READ1_DIS_BIT (0x00000002)
+
+#define B2RIF_DIS_LDR_LPWR_DIS_LSB (0)
+#define B2RIF_DIS_LDR_LPWR_DIS_WIDTH (1)
+#define B2RIF_DIS_LDR_LPWR_DIS_MASK (0x00000001)
+#define B2RIF_DIS_LDR_LPWR_DIS_BIT (0x00000001)
+
+#define B2RIF_DBG_CON_DBG_CLR_LSB (4)
+#define B2RIF_DBG_CON_DBG_CLR_WIDTH (1)
+#define B2RIF_DBG_CON_DBG_CLR_MASK (0x00000010)
+#define B2RIF_DBG_CON_DBG_CLR_BIT (0x00000010)
+
+#define B2RIF_DBG_CON_DBG_EN_LSB (0)
+#define B2RIF_DBG_CON_DBG_EN_WIDTH (1)
+#define B2RIF_DBG_CON_DBG_EN_MASK (0x00000001)
+#define B2RIF_DBG_CON_DBG_EN_BIT (0x00000001)
+
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_LSB (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_WIDTH (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_1_MASK (0x0000FF00)
+
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_LSB (0)
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_WIDTH (8)
+#define B2RIF_RREQ_CNT_RREQ_CNT_0_MASK (0x000000FF)
+
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_LSB (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_WIDTH (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_1_MASK (0x0000FF00)
+
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_LSB (0)
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_WIDTH (8)
+#define B2RIF_RRDY_CNT_RRDY_CNT_0_MASK (0x000000FF)
+
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_LSB (0)
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_WIDTH (8)
+#define B2RIF_LREQ_CNT_LOADER_REQ_CNT_MASK (0x000000FF)
+
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_LSB (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_ST_SAM_IDX_0_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_LSB (0)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_0_B2RIF_R_BASE_ADDR_0_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_LSB (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_ST_SAM_IDX_1_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_LSB (0)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_0_B2RIF_R_BASE_ADDR_1_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_LSB (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_ST_SAM_IDX_2_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_LSB (0)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_0_B2RIF_R_BASE_ADDR_2_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_LSB (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_ST_SAM_IDX_3_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_LSB (0)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_0_B2RIF_R_BASE_ADDR_3_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_LSB (0)
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_WIDTH (16)
+#define B2RIF_R_CON_A0C0_1_B2RIF_R_BUF_SIZE_0_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_LSB (0)
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_WIDTH (16)
+#define B2RIF_R_CON_A1C0_1_B2RIF_R_BUF_SIZE_1_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_LSB (0)
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_WIDTH (16)
+#define B2RIF_R_CON_A0C1_1_B2RIF_R_BUF_SIZE_2_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_LSB (0)
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_WIDTH (16)
+#define B2RIF_R_CON_A1C1_1_B2RIF_R_BUF_SIZE_3_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_LSB (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_ST_SAM_IDX_Q_MASK (0xFFFF0000)
+
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_LSB (0)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_0_B2RIF_R_BASE_ADDR_Q_MASK (0x0000FFFF)
+
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_LSB (0)
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_WIDTH (16)
+#define B2RIF_R_CON_QLIC_1_B2RIF_R_BUF_SIZE_Q_MASK (0x0000FFFF)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_LSB (16)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_WIDTH (16)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_MASK (0xFFFF0000)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_LSB (8)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_WIDTH (1)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_MASK (0x00000100)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_CNT_OVER_STA_BIT (0x00000100)
+
+#define B2RIF_HOLD_STA_B2RIF_HOLD_MAX_CNT_LSB (0)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_MAX_CNT_WIDTH (8)
+#define B2RIF_HOLD_STA_B2RIF_HOLD_MAX_CNT_MASK (0x000000FF)
+
+#define B2RIF_RESERVED0_B2RIF_RESERVED0_LSB (0)
+#define B2RIF_RESERVED0_B2RIF_RESERVED0_WIDTH (32)
+#define B2RIF_RESERVED0_B2RIF_RESERVED0_MASK (0xFFFFFFFF)
+
+#define B2RIF_RESERVED1_B2RIF_RESERVED1_LSB (0)
+#define B2RIF_RESERVED1_B2RIF_RESERVED1_WIDTH (32)
+#define B2RIF_RESERVED1_B2RIF_RESERVED1_MASK (0xFFFFFFFF)
+
+#define IC_SYNC_B2RIF_IC_RD_STATE_ENABLE_LSB (0)
+#define IC_SYNC_B2RIF_IC_RD_STATE_ENABLE_WIDTH (1)
+#define IC_SYNC_B2RIF_IC_RD_STATE_ENABLE_MASK (0x00000001)
+#define IC_SYNC_B2RIF_IC_RD_STATE_ENABLE_BIT (0x00000001)
+
+#define IC_SYNC_SYS_CNT_B2RIF_IC_SYNC_SYS_DONE_LSB (31)
+#define IC_SYNC_SYS_CNT_B2RIF_IC_SYNC_SYS_DONE_WIDTH (1)
+#define IC_SYNC_SYS_CNT_B2RIF_IC_SYNC_SYS_DONE_MASK (0x80000000)
+#define IC_SYNC_SYS_CNT_B2RIF_IC_SYNC_SYS_DONE_BIT (0x80000000)
+
+#define IC_SYNC_SYS_CNT_B2RIF_IC_RD_SYS_CNT_LSB (0)
+#define IC_SYNC_SYS_CNT_B2RIF_IC_RD_SYS_CNT_WIDTH (20)
+#define IC_SYNC_SYS_CNT_B2RIF_IC_RD_SYS_CNT_MASK (0x000FFFFF)
+
+#define IC_SYNC_IC_ADDR_B2RIF_IC_SYNC_ADDR_DONE_LSB (31)
+#define IC_SYNC_IC_ADDR_B2RIF_IC_SYNC_ADDR_DONE_WIDTH (1)
+#define IC_SYNC_IC_ADDR_B2RIF_IC_SYNC_ADDR_DONE_MASK (0x80000000)
+#define IC_SYNC_IC_ADDR_B2RIF_IC_SYNC_ADDR_DONE_BIT (0x80000000)
+
+#define IC_SYNC_IC_ADDR_B2RIF_IC_RD_ADDR_LSB (0)
+#define IC_SYNC_IC_ADDR_B2RIF_IC_RD_ADDR_WIDTH (20)
+#define IC_SYNC_IC_ADDR_B2RIF_IC_RD_ADDR_MASK (0x000FFFFF)
+#endif //#ifndef _CPH_B2RIF_97_H_
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg.h b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg.h
new file mode 100644
index 0000000..6f6c5a9
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphbigramglbconreg_93.h"
+#elif defined(__MD95__)
+#include "cphbigramglbconreg_95.h"
+#else
+#include "cphbigramglbconreg_95.h"/*#error "[ERROR] Invalid MD generation" For build error*/
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_93.h b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_93.h
new file mode 100644
index 0000000..174950d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_93.h
@@ -0,0 +1,1282 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_BIGRAM_GLB_CON_REG_H_
+#define _CPH_BIGRAM_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define BIGRAM_GLOBAL_CON_REG_BASE (0xAB810000)
+
+#define BIGRAM_GLOBAL_CON_end (BIGRAM_GLOBAL_CON_REG_BASE + 0x0118 + 1*4)
+
+
+
+#define BIGRAM_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0000))
+#define BIGRAM_PWR_AWARE_CTRL ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0004))
+#define BIGRAM_LTE_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0008))
+#define BIGRAM_LTE_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x000C))
+#define BIGRAM_LTE_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0010))
+#define BIGRAM_FDD_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0018))
+#define BIGRAM_FDD_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x001C))
+#define BIGRAM_FDD_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0020))
+#define BIGRAM_TDD_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0028))
+#define BIGRAM_TDD_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x002C))
+#define BIGRAM_TDD_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0030))
+#define BIGRAM_C2K_1XRTT_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0038))
+#define BIGRAM_C2K_1XRTT_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x003C))
+#define BIGRAM_C2K_1XRTT_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0040))
+#define BIGRAM_C2K_EVDO_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0048))
+#define BIGRAM_C2K_EVDO_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x004C))
+#define BIGRAM_C2K_EVDO_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0050))
+#define BIGRAM_LTE_EL1D_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0058))
+#define BIGRAM_LTE_EL1D_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x005C))
+#define BIGRAM_LTE_EL1D_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0060))
+#define BIGRAM_CK_IDLE_DIV ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0068))
+#define BIGRAM_CK_IDLE_MASK ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x006C))
+#define BIGRAM_BUS_CONFIG0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0100))
+#define BIGRAM_BUS_STATUS0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0104))
+#define BIGRAM_SLV_BUS_CONFIG0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0108))
+#define BIGRAM_SLV_BUS_STATUS0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x010C))
+#define BIGRAM_SLV_BUS_STATUS1 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0110))
+#define BIGRAM_BUS_DBGOUT ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0114))
+#define BIGRAM_CLK_DIV2_DIS ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0118))
+
+
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_LSB (10)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_MASK (0x00000400)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_BIT (0x00000400)
+
+#define BIGRAM_CG_CON_DSTDB_CK_CG_LSB (9)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_MASK (0x00000200)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_BIT (0x00000200)
+
+#define BIGRAM_CG_CON_D2BIF_CK_CG_LSB (8)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_MASK (0x00000100)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_BIT (0x00000100)
+
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_LSB (7)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_MASK (0x00000080)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_BIT (0x00000080)
+
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_LSB (6)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_MASK (0x00000040)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_BIT (0x00000040)
+
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_LSB (5)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_MASK (0x00000020)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_BIT (0x00000020)
+
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_LSB (4)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_MASK (0x00000010)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_BIT (0x00000010)
+
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_LSB (3)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_MASK (0x00000008)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_BIT (0x00000008)
+
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_LSB (2)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_MASK (0x00000004)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_BIT (0x00000004)
+
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_LSB (1)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_MASK (0x00000002)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_BIT (0x00000002)
+
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_LSB (0)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_MASK (0x00000001)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_BIT (0x00000001)
+
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_LSB (0)
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_WIDTH (32)
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_MASK (0xFFFFFFFF)
+
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_LSB (10)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_LSB (9)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_LSB (8)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_LSB (6)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_LSB (5)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_LSB (10)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_LSB (9)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_LSB (8)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_LSB (6)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_LSB (5)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_LSB (0)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_MASK (0x00000001)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_LSB (10)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_LSB (9)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_LSB (8)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_LSB (6)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_LSB (5)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_LSB (9)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_LSB (8)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_LSB (7)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_LSB (6)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_LSB (5)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_LSB (4)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_LSB (3)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_LSB (2)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_LSB (1)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_LSB (0)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_LSB (9)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_LSB (9)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_LSB (8)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_LSB (8)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_LSB (7)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_LSB (7)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_LSB (6)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_LSB (6)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_LSB (5)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_LSB (5)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_LSB (4)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_LSB (4)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_LSB (3)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_LSB (3)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_LSB (2)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_LSB (2)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_LSB (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_LSB (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_LSB (0)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_LSB (0)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_BIT (0x00000001)
+
+#define BIGRAM_BUS_CONFIG0_debug_sel_LSB (31)
+#define BIGRAM_BUS_CONFIG0_debug_sel_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_debug_sel_MASK (0x80000000)
+#define BIGRAM_BUS_CONFIG0_debug_sel_BIT (0x80000000)
+
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_LSB (9)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_MASK (0x00000600)
+
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_LSB (7)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_MASK (0x00000180)
+
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_LSB (5)
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_MASK (0x00000060)
+
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_LSB (3)
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_MASK (0x00000018)
+
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_LSB (2)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_MASK (0x00000004)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_BIT (0x00000004)
+
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_LSB (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_MASK (0x00000002)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_BIT (0x00000002)
+
+#define BIGRAM_BUS_CONFIG0_cg_disable_LSB (0)
+#define BIGRAM_BUS_CONFIG0_cg_disable_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_cg_disable_MASK (0x00000001)
+#define BIGRAM_BUS_CONFIG0_cg_disable_BIT (0x00000001)
+
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_LSB (3)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_MASK (0x00000008)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_BIT (0x00000008)
+
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_LSB (2)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_MASK (0x00000004)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_BIT (0x00000004)
+
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_LSB (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_MASK (0x00000002)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_BIT (0x00000002)
+
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_LSB (0)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_MASK (0x00000001)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_LSB (5)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_WIDTH (2)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_MASK (0x00000060)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_LSB (4)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_MASK (0x00000010)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_BIT (0x00000010)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_LSB (3)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_MASK (0x00000008)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_BIT (0x00000008)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_LSB (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_WIDTH (2)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_MASK (0x00000006)
+
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_LSB (0)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_MASK (0x00000001)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_LSB (21)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_MASK (0x00200000)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_BIT (0x00200000)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_LSB (18)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_WIDTH (3)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_MASK (0x001C0000)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_LSB (5)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_WIDTH (13)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_MASK (0x0003FFE0)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_LSB (4)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_MASK (0x00000010)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_BIT (0x00000010)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_LSB (3)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_MASK (0x00000008)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_BIT (0x00000008)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_LSB (2)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_MASK (0x00000004)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_BIT (0x00000004)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_LSB (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_MASK (0x00000002)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_BIT (0x00000002)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_LSB (0)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_MASK (0x00000001)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_LSB (0)
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_WIDTH (32)
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_MASK (0xFFFFFFFF)
+
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_LSB (0)
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_WIDTH (32)
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_MASK (0xFFFFFFFF)
+
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_LSB (0)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_WIDTH (1)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_MASK (0x00000001)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_BIT (0x00000001)
+
+
+#endif /*#ifndef _CPH_BIGRAM_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_95.h b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_95.h
new file mode 100644
index 0000000..174950d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphbigramglbconreg_95.h
@@ -0,0 +1,1282 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_BIGRAM_GLB_CON_REG_H_
+#define _CPH_BIGRAM_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define BIGRAM_GLOBAL_CON_REG_BASE (0xAB810000)
+
+#define BIGRAM_GLOBAL_CON_end (BIGRAM_GLOBAL_CON_REG_BASE + 0x0118 + 1*4)
+
+
+
+#define BIGRAM_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0000))
+#define BIGRAM_PWR_AWARE_CTRL ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0004))
+#define BIGRAM_LTE_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0008))
+#define BIGRAM_LTE_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x000C))
+#define BIGRAM_LTE_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0010))
+#define BIGRAM_FDD_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0018))
+#define BIGRAM_FDD_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x001C))
+#define BIGRAM_FDD_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0020))
+#define BIGRAM_TDD_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0028))
+#define BIGRAM_TDD_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x002C))
+#define BIGRAM_TDD_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0030))
+#define BIGRAM_C2K_1XRTT_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0038))
+#define BIGRAM_C2K_1XRTT_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x003C))
+#define BIGRAM_C2K_1XRTT_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0040))
+#define BIGRAM_C2K_EVDO_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0048))
+#define BIGRAM_C2K_EVDO_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x004C))
+#define BIGRAM_C2K_EVDO_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0050))
+#define BIGRAM_LTE_EL1D_CG_CLR ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0058))
+#define BIGRAM_LTE_EL1D_CG_SET ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x005C))
+#define BIGRAM_LTE_EL1D_CG_CON ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0060))
+#define BIGRAM_CK_IDLE_DIV ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0068))
+#define BIGRAM_CK_IDLE_MASK ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x006C))
+#define BIGRAM_BUS_CONFIG0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0100))
+#define BIGRAM_BUS_STATUS0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0104))
+#define BIGRAM_SLV_BUS_CONFIG0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0108))
+#define BIGRAM_SLV_BUS_STATUS0 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x010C))
+#define BIGRAM_SLV_BUS_STATUS1 ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0110))
+#define BIGRAM_BUS_DBGOUT ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0114))
+#define BIGRAM_CLK_DIV2_DIS ((APBADDR32)(BIGRAM_GLOBAL_CON_REG_BASE + 0x0118))
+
+
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_LSB (10)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_MASK (0x00000400)
+#define BIGRAM_CG_CON_RAKE_32X_CK_CG_BIT (0x00000400)
+
+#define BIGRAM_CG_CON_DSTDB_CK_CG_LSB (9)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_MASK (0x00000200)
+#define BIGRAM_CG_CON_DSTDB_CK_CG_BIT (0x00000200)
+
+#define BIGRAM_CG_CON_D2BIF_CK_CG_LSB (8)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_MASK (0x00000100)
+#define BIGRAM_CG_CON_D2BIF_CK_CG_BIT (0x00000100)
+
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_LSB (7)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_MASK (0x00000080)
+#define BIGRAM_CG_CON_DFE_DUMP_CK_CG_BIT (0x00000080)
+
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_LSB (6)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_MASK (0x00000040)
+#define BIGRAM_CG_CON_BR_DMA_CK_CG_BIT (0x00000040)
+
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_LSB (5)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_MASK (0x00000020)
+#define BIGRAM_CG_CON_BIGRAM_CK_CG_BIT (0x00000020)
+
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_LSB (4)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_MASK (0x00000010)
+#define BIGRAM_CG_CON_DFE_DUMP_VDSP_CK_CG_BIT (0x00000010)
+
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_LSB (3)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_MASK (0x00000008)
+#define BIGRAM_CG_CON_D2BIF_VDSP_CK_CG_BIT (0x00000008)
+
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_LSB (2)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_MASK (0x00000004)
+#define BIGRAM_CG_CON_RXT2F_VDSP_CK_CG_BIT (0x00000004)
+
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_LSB (1)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_MASK (0x00000002)
+#define BIGRAM_CG_CON_BIGRAM_BRP_CK_CG_BIT (0x00000002)
+
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_LSB (0)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_WIDTH (1)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_MASK (0x00000001)
+#define BIGRAM_CG_CON_BIGRAM_RAKE_CK_CG_BIT (0x00000001)
+
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_LSB (0)
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_WIDTH (32)
+#define BIGRAM_PWR_AWARE_CTRL_BIGRAM_PWR_AWARE_MASK (0xFFFFFFFF)
+
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_LTE_CG_CLR_L_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_LTE_CG_CLR_L_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_LTE_CG_CLR_L_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_LTE_CG_CLR_L_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_LTE_CG_CLR_L_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_LTE_CG_CLR_L_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_LTE_CG_CLR_L_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_LTE_CG_SET_L_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_LTE_CG_SET_L_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_LTE_CG_SET_L_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_LTE_CG_SET_L_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_LTE_CG_SET_L_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_LTE_CG_SET_L_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_LTE_CG_SET_L_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_LSB (10)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_LTE_CG_CON_L_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_LSB (9)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_LTE_CG_CON_L_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_LSB (8)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_LSB (6)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_LTE_CG_CON_L_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_LSB (5)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_LTE_CG_CON_L_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_LTE_CG_CON_L_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_LTE_CG_CON_L_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_LTE_CG_CON_L_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_FDD_CG_CLR_W_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_FDD_CG_CLR_W_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_FDD_CG_CLR_W_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_FDD_CG_CLR_W_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_FDD_CG_CLR_W_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_FDD_CG_CLR_W_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_FDD_CG_CLR_W_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_FDD_CG_SET_W_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_FDD_CG_SET_W_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_FDD_CG_SET_W_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_FDD_CG_SET_W_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_FDD_CG_SET_W_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_FDD_CG_SET_W_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_FDD_CG_SET_W_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_LSB (10)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_FDD_CG_CON_W_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_LSB (9)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_FDD_CG_CON_W_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_LSB (8)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_LSB (6)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_FDD_CG_CON_W_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_LSB (5)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_FDD_CG_CON_W_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_FDD_CG_CON_W_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_FDD_CG_CON_W_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_FDD_CG_CON_W_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_TDD_CG_CLR_T_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_TDD_CG_CLR_T_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_TDD_CG_CLR_T_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_TDD_CG_CLR_T_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_TDD_CG_CLR_T_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_TDD_CG_CLR_T_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_LSB (0)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_WIDTH (1)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_MASK (0x00000001)
+#define BIGRAM_TDD_CG_CLR_T_BIGRAM_RAKE_CK_CLR_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_TDD_CG_SET_T_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_TDD_CG_SET_T_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_TDD_CG_SET_T_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_TDD_CG_SET_T_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_TDD_CG_SET_T_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_TDD_CG_SET_T_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_TDD_CG_SET_T_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_LSB (10)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_TDD_CG_CON_T_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_LSB (9)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_TDD_CG_CON_T_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_LSB (8)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_LSB (6)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_TDD_CG_CON_T_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_LSB (5)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_TDD_CG_CON_T_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_TDD_CG_CON_T_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_TDD_CG_CON_T_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_TDD_CG_CON_T_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_CLR_C1_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_SET_C1_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_LSB (10)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_LSB (9)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_LSB (8)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_LSB (6)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_LSB (5)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_C2K_1XRTT_CG_CON_C1_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RAKE_32X_CG_CLR_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DSTDB_CG_CLR_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_CG_CLR_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_CG_CLR_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BR_DMA_CG_CLR_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_CG_CLR_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_DFE_DUMP_VDSP_CG_CLR_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_D2BIF_VDSP_CG_CLR_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_RXT2F_VDSP_CG_CLR_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_BRP_CG_CLR_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_CLR_CE_BIGRAM_RAKE_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RAKE_32X_CG_SET_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DSTDB_CG_SET_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_CG_SET_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_CG_SET_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BR_DMA_CG_SET_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_CG_SET_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_DFE_DUMP_VDSP_CG_SET_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_D2BIF_VDSP_CG_SET_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_RXT2F_VDSP_CG_SET_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_BRP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_SET_CE_BIGRAM_RAKE_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_LSB (10)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_MASK (0x00000400)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RAKE_32X_CG_BIT (0x00000400)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_LSB (9)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_MASK (0x00000200)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DSTDB_CG_BIT (0x00000200)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_LSB (8)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_MASK (0x00000100)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_CG_BIT (0x00000100)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_LSB (7)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_MASK (0x00000080)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_CG_BIT (0x00000080)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_LSB (6)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_MASK (0x00000040)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BR_DMA_CG_BIT (0x00000040)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_LSB (5)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_MASK (0x00000020)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_CG_BIT (0x00000020)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_LSB (4)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_MASK (0x00000010)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_DFE_DUMP_VDSP_CG_BIT (0x00000010)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_LSB (3)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_MASK (0x00000008)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_D2BIF_VDSP_CG_BIT (0x00000008)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_LSB (2)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_MASK (0x00000004)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_RXT2F_VDSP_CG_BIT (0x00000004)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_LSB (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_MASK (0x00000002)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_BRP_CG_BIT (0x00000002)
+
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_LSB (0)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_WIDTH (1)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_MASK (0x00000001)
+#define BIGRAM_C2K_EVDO_CG_CON_CE_BIGRAM_RAKE_CG_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_SWAP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_CLR_L_D2BIF_VDSP_SWAP_CG_CLR_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_SWAP_CG_SET_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_SET_L_D2BIF_VDSP_SWAP_CG_SET_BIT (0x00000001)
+
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_LSB (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_MASK (0x00000002)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_SWAP_CG_BIT (0x00000002)
+
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_LSB (0)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_WIDTH (1)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_MASK (0x00000001)
+#define BIGRAM_LTE_EL1D_CG_CON_L_D2BIF_VDSP_SWAP_CG_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_LSB (9)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_DIV_DSTDB_CK_IDLE_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_LSB (8)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_CK_IDLE_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_LSB (7)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_CK_IDLE_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_LSB (6)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_DIV_BR_DMA_CK_IDLE_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_LSB (5)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_DIV_BIGRAM_CK_IDLE_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_LSB (4)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_DIV_DFE_DUMP_VDSP_CK_IDLE_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_LSB (3)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_DIV_D2BIF_VDSP_CK_IDLE_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_LSB (2)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_DIV_RXT2F_VDSP_CK_IDLE_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_LSB (1)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_DIV_BRP_CK_IDLE_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_LSB (0)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_WIDTH (1)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_DIV_RAKE_CK_IDLE_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_LSB (9)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_dbg_mask_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_LSB (9)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_MASK (0x00000200)
+#define BIGRAM_CK_IDLE_MASK_DSTDB_CK_IDLE_mask_BIT (0x00000200)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_LSB (8)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_dbg_mask_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_LSB (8)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_MASK (0x00000100)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_CK_IDLE_mask_BIT (0x00000100)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_LSB (7)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_dbg_mask_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_LSB (7)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_MASK (0x00000080)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_CK_IDLE_mask_BIT (0x00000080)
+
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_LSB (6)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_dbg_mask_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_LSB (6)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_MASK (0x00000040)
+#define BIGRAM_CK_IDLE_MASK_BR_DMA_CK_IDLE_mask_BIT (0x00000040)
+
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_LSB (5)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_dbg_mask_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_LSB (5)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_MASK (0x00000020)
+#define BIGRAM_CK_IDLE_MASK_BIGRAM_CK_IDLE_mask_BIT (0x00000020)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_LSB (4)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_dbg_mask_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_LSB (4)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_MASK (0x00000010)
+#define BIGRAM_CK_IDLE_MASK_DFE_DUMP_VDSP_CK_IDLE_mask_BIT (0x00000010)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_LSB (3)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_dbg_mask_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_LSB (3)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_MASK (0x00000008)
+#define BIGRAM_CK_IDLE_MASK_D2BIF_VDSP_CK_IDLE_mask_BIT (0x00000008)
+
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_LSB (2)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_dbg_mask_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_LSB (2)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_MASK (0x00000004)
+#define BIGRAM_CK_IDLE_MASK_RXT2F_VDSP_CK_IDLE_mask_BIT (0x00000004)
+
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_LSB (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_dbg_mask_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_LSB (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_MASK (0x00000002)
+#define BIGRAM_CK_IDLE_MASK_BRP_CK_IDLE_mask_BIT (0x00000002)
+
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_LSB (0)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_dbg_mask_BIT (0x00000001)
+
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_LSB (0)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_WIDTH (1)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_MASK (0x00000001)
+#define BIGRAM_CK_IDLE_MASK_RAKE_CK_IDLE_mask_BIT (0x00000001)
+
+#define BIGRAM_BUS_CONFIG0_debug_sel_LSB (31)
+#define BIGRAM_BUS_CONFIG0_debug_sel_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_debug_sel_MASK (0x80000000)
+#define BIGRAM_BUS_CONFIG0_debug_sel_BIT (0x80000000)
+
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_LSB (9)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_arflush_thre_MASK (0x00000600)
+
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_LSB (7)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_bigram_slv_awflush_thre_MASK (0x00000180)
+
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_LSB (5)
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_slv_sync_sel_MASK (0x00000060)
+
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_LSB (3)
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_WIDTH (2)
+#define BIGRAM_BUS_CONFIG0_mst_sync_sel_MASK (0x00000018)
+
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_LSB (2)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_MASK (0x00000004)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_ostd_ext_en_BIT (0x00000004)
+
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_LSB (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_MASK (0x00000002)
+#define BIGRAM_BUS_CONFIG0_bigram_mas_mi_qos_on_BIT (0x00000002)
+
+#define BIGRAM_BUS_CONFIG0_cg_disable_LSB (0)
+#define BIGRAM_BUS_CONFIG0_cg_disable_WIDTH (1)
+#define BIGRAM_BUS_CONFIG0_cg_disable_MASK (0x00000001)
+#define BIGRAM_BUS_CONFIG0_cg_disable_BIT (0x00000001)
+
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_LSB (3)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_MASK (0x00000008)
+#define BIGRAM_BUS_STATUS0_bigram_mas_gals_tx_idle_BIT (0x00000008)
+
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_LSB (2)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_MASK (0x00000004)
+#define BIGRAM_BUS_STATUS0_bigram_gals_idle_BIT (0x00000004)
+
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_LSB (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_MASK (0x00000002)
+#define BIGRAM_BUS_STATUS0_bigram_mi_r_busy_BIT (0x00000002)
+
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_LSB (0)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_WIDTH (1)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_MASK (0x00000001)
+#define BIGRAM_BUS_STATUS0_bigram_mi_w_busy_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_LSB (5)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_WIDTH (2)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_interleave_en_MASK (0x00000060)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_LSB (4)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_MASK (0x00000010)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_OSTD_disable_BIT (0x00000010)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_LSB (3)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_MASK (0x00000008)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_ctrl_bypass_BIT (0x00000008)
+
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_LSB (1)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_WIDTH (2)
+#define BIGRAM_SLV_BUS_CONFIG0_bigram_slv_si_way_en_MASK (0x00000006)
+
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_LSB (0)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_WIDTH (1)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_MASK (0x00000001)
+#define BIGRAM_SLV_BUS_CONFIG0_cg_disable_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_LSB (21)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_MASK (0x00200000)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_axi2sram_idle_BIT (0x00200000)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_LSB (18)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_WIDTH (3)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_domain_MASK (0x001C0000)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_LSB (5)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_WIDTH (13)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_id_MASK (0x0003FFE0)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_LSB (4)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_MASK (0x00000010)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_w_BIT (0x00000010)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_LSB (3)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_MASK (0x00000008)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_dec_err_r_BIT (0x00000008)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_LSB (2)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_MASK (0x00000004)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_rd_ot_busy_BIT (0x00000004)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_LSB (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_MASK (0x00000002)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_wr_ot_busy_BIT (0x00000002)
+
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_LSB (0)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_WIDTH (1)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_MASK (0x00000001)
+#define BIGRAM_SLV_BUS_STATUS0_bigram_slv_si_ctrl_updated_BIT (0x00000001)
+
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_LSB (0)
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_WIDTH (32)
+#define BIGRAM_SLV_BUS_STATUS1_bigram_slv_si_dec_err_addr_MASK (0xFFFFFFFF)
+
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_LSB (0)
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_WIDTH (32)
+#define BIGRAM_BUS_DBGOUT_bigram_bus_dbgout_MASK (0xFFFFFFFF)
+
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_LSB (0)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_WIDTH (1)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_MASK (0x00000001)
+#define BIGRAM_CLK_DIV2_DIS_bigram_div2_disable_BIT (0x00000001)
+
+
+#endif /*#ifndef _CPH_BIGRAM_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg.h b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg.h
new file mode 100644
index 0000000..d921103
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphc2kl1aocfg_93.h"
+#elif defined(__MD95__)
+#include "cphc2kl1aocfg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphc2kl1aocfg_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_93.h b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_93.h
new file mode 100644
index 0000000..267f31e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_93.h
@@ -0,0 +1,563 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_L1_A0CFG_H_
+#define _CPH_C2K_L1_A0CFG_H_
+#include "drvpdn.h"
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MODEML1_AO_CONFIG_REG_BASE (0xA6020000)
+
+#define MODEML1_AO_CONFIG_end (MODEML1_AO_CONFIG_REG_BASE + 0x350 + 1*4)
+
+
+
+#define MDL1AO_CON0 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x00))
+#define MDL1AO_CON1 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x04))
+#define MDL1AO_CON2 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x08))
+#define MDL1AO_CON4 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x10))
+#define MDL1AO_CON5 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x14))
+#define MDL1AO_CON6 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x18))
+#define MDL1AO_CON7 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x1c))
+#define MDL1AO_CON8 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x20))
+#define MDL1AO_CON9 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x24))
+#define MDL1AO_CON10 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x28))
+#define MDL1AO_CON11 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x2c))
+#define MDL1AO_CON12 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x30))
+#define MDL1AO_CON14 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x38))
+#define MDL1AO_CON15 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x3C))
+#define MDL1AO_CON16 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x40))
+#define MDL1AO_CON17 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x44))
+#define MDL1AO_CON18 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x48))
+#define MDL1AO_CON19 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x4C))
+#if 0 /* defined in drvpdn.h */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#define MDL1AO_CON212 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x350))
+
+
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_LSB (0)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_WIDTH (1)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_MASK (0x00000001)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_LSB (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_MASK (0x00000002)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_BIT (0x00000002)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_LSB (0)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_MASK (0x00000001)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_BIT (0x00000001)
+
+#define MDL1AO_CON2_BUS2X_DCM_CON_LSB (0)
+#define MDL1AO_CON2_BUS2X_DCM_CON_WIDTH (32)
+#define MDL1AO_CON2_BUS2X_DCM_CON_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_LSB (0)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_WIDTH (8)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_MASK (0x000000FF)
+
+#define MDL1AO_CON5_GLBCON_DBG_SEL_LSB (0)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_WIDTH (2)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_MASK (0x00000003)
+
+#define MDL1AO_CON6_BUS_PWR_AWARE_LSB (0)
+#define MDL1AO_CON6_BUS_PWR_AWARE_WIDTH (32)
+#define MDL1AO_CON6_BUS_PWR_AWARE_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON7_MBIST_OUT_SEL_LSB (0)
+#define MDL1AO_CON7_MBIST_OUT_SEL_WIDTH (4)
+#define MDL1AO_CON7_MBIST_OUT_SEL_MASK (0x0000000F)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_LSB (3)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_MASK (0x00000008)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_BIT (0x00000008)
+
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_LSB (2)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_MASK (0x00000004)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_BIT (0x00000004)
+
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_LSB (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_MASK (0x00000002)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_BIT (0x00000002)
+
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_LSB (0)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_MASK (0x00000001)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_LSB (0)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_WIDTH (1)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_MASK (0x00000001)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_BIT (0x00000001)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_LSB (2)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_MASK (0x00000004)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_BIT (0x00000004)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_LSB (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_MASK (0x00000002)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_BIT (0x00000002)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_LSB (0)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_MASK (0x00000001)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_BIT (0x00000001)
+
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_LSB (0)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_WIDTH (5)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_MASK (0x0000001F)
+
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_LSB (0)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_WIDTH (5)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_MASK (0x0000001F)
+
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_LSB (0)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_WIDTH (5)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_MASK (0x0000001F)
+
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_LSB (0)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_WIDTH (5)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_MASK (0x0000001F)
+
+#define MDL1AO_CON18_RG_DBG_SUB_EN_LSB (0)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_WIDTH (4)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_MASK (0x0000000F)
+
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_LSB (0)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_WIDTH (6)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_MASK (0x0000003F)
+
+#define MDL1AO_CON20_PDN_CDO_TTR_LSB (18)
+#define MDL1AO_CON20_PDN_CDO_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_CDO_TTR_MASK (0x00040000)
+#define MDL1AO_CON20_PDN_CDO_TTR_BIT (0x00040000)
+
+#define MDL1AO_CON20_PDN_C1X_TTR_LSB (17)
+#define MDL1AO_CON20_PDN_C1X_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C1X_TTR_MASK (0x00020000)
+#define MDL1AO_CON20_PDN_C1X_TTR_BIT (0x00020000)
+
+#define MDL1AO_CON20_PDN_FREQM_LSB (16)
+#define MDL1AO_CON20_PDN_FREQM_WIDTH (1)
+#define MDL1AO_CON20_PDN_FREQM_MASK (0x00010000)
+#define MDL1AO_CON20_PDN_FREQM_BIT (0x00010000)
+
+#define MDL1AO_CON20_PDN_DVFS_CTRL_LSB (15)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_MASK (0x00008000)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_BIT (0x00008000)
+
+#define MDL1AO_CON20_PDN_IDC_UART_LSB (14)
+#define MDL1AO_CON20_PDN_IDC_UART_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_UART_MASK (0x00004000)
+#define MDL1AO_CON20_PDN_IDC_UART_BIT (0x00004000)
+
+#define MDL1AO_CON20_PDN_BSI_LSB (13)
+#define MDL1AO_CON20_PDN_BSI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BSI_MASK (0x00002000)
+#define MDL1AO_CON20_PDN_BSI_BIT (0x00002000)
+
+#define MDL1AO_CON20_PDN_BPI_LSB (12)
+#define MDL1AO_CON20_PDN_BPI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BPI_MASK (0x00001000)
+#define MDL1AO_CON20_PDN_BPI_BIT (0x00001000)
+
+#define MDL1AO_CON20_PDN_IDC_CTRL_LSB (11)
+#define MDL1AO_CON20_PDN_IDC_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_CTRL_MASK (0x00000800)
+#define MDL1AO_CON20_PDN_IDC_CTRL_BIT (0x00000800)
+
+#define MDL1AO_CON20_PDN_LTE_SLP_LSB (10)
+#define MDL1AO_CON20_PDN_LTE_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_SLP_MASK (0x00000400)
+#define MDL1AO_CON20_PDN_LTE_SLP_BIT (0x00000400)
+
+#define MDL1AO_CON20_PDN_LTE_TMR_LSB (9)
+#define MDL1AO_CON20_PDN_LTE_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_TMR_MASK (0x00000200)
+#define MDL1AO_CON20_PDN_LTE_TMR_BIT (0x00000200)
+
+#define MDL1AO_CON20_PDN_FDD_SLP_LSB (8)
+#define MDL1AO_CON20_PDN_FDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_SLP_MASK (0x00000100)
+#define MDL1AO_CON20_PDN_FDD_SLP_BIT (0x00000100)
+
+#define MDL1AO_CON20_PDN_FDD_TMR_LSB (7)
+#define MDL1AO_CON20_PDN_FDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_TMR_MASK (0x00000080)
+#define MDL1AO_CON20_PDN_FDD_TMR_BIT (0x00000080)
+
+#define MDL1AO_CON20_PDN_TDD_SLP_LSB (6)
+#define MDL1AO_CON20_PDN_TDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_SLP_MASK (0x00000040)
+#define MDL1AO_CON20_PDN_TDD_SLP_BIT (0x00000040)
+
+#define MDL1AO_CON20_PDN_TDD_TMR_LSB (5)
+#define MDL1AO_CON20_PDN_TDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_TMR_MASK (0x00000020)
+#define MDL1AO_CON20_PDN_TDD_TMR_BIT (0x00000020)
+
+#define MDL1AO_CON20_PDN_TDMA_SLP_LSB (4)
+#define MDL1AO_CON20_PDN_TDMA_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDMA_SLP_MASK (0x00000010)
+#define MDL1AO_CON20_PDN_TDMA_SLP_BIT (0x00000010)
+
+#define MDL1AO_CON20_PDN_C2K1X_SLP_LSB (3)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_MASK (0x00000008)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_BIT (0x00000008)
+
+#define MDL1AO_CON20_PDN_C2K1X_TMR_LSB (2)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_MASK (0x00000004)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_BIT (0x00000004)
+
+#define MDL1AO_CON20_PDN_C2KDO_SLP_LSB (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_MASK (0x00000002)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_BIT (0x00000002)
+
+#define MDL1AO_CON20_PDN_C2KDO_TMR_LSB (0)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_MASK (0x00000001)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_BIT (0x00000001)
+
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_LSB (20)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_MASK (0x00100000)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_BIT (0x00100000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_LSB (21)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_MASK (0x00200000)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_BIT (0x00200000)
+
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_LSB (18)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_MASK (0x00040000)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_BIT (0x00040000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_LSB (17)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_MASK (0x00020000)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_BIT (0x00020000)
+
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_LSB (16)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_MASK (0x00010000)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_BIT (0x00010000)
+
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_LSB (15)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_MASK (0x00008000)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_BIT (0x00008000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_LSB (14)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_MASK (0x00004000)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_BIT (0x00004000)
+
+#define MDL1AO_PDN_SET_PDN_BSI_SET_LSB (13)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_MASK (0x00002000)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_BIT (0x00002000)
+
+#define MDL1AO_PDN_SET_PDN_BPI_SET_LSB (12)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_MASK (0x00001000)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_BIT (0x00001000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_LSB (11)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_MASK (0x00000800)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_BIT (0x00000800)
+
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_LSB (10)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_MASK (0x00000400)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_BIT (0x00000400)
+
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_LSB (9)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_MASK (0x00000200)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_BIT (0x00000200)
+
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_LSB (8)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_MASK (0x00000100)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_BIT (0x00000100)
+
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_LSB (7)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_MASK (0x00000080)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_BIT (0x00000080)
+
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_LSB (6)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_MASK (0x00000040)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_BIT (0x00000040)
+
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_LSB (5)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_MASK (0x00000020)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_BIT (0x00000020)
+
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_LSB (4)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_MASK (0x00000010)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_BIT (0x00000010)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_LSB (3)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_MASK (0x00000008)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_BIT (0x00000008)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_LSB (2)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_MASK (0x00000004)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_BIT (0x00000004)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_LSB (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_MASK (0x00000002)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_BIT (0x00000002)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_LSB (0)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_MASK (0x00000001)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_BIT (0x00000001)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_LSB (20)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_MASK (0x00100000)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_BIT (0x00100000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_LSB (21)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_MASK (0x00200000)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_BIT (0x00200000)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_LSB (18)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_MASK (0x00040000)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_BIT (0x00040000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_LSB (17)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_MASK (0x00020000)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_BIT (0x00020000)
+
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_LSB (16)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_MASK (0x00010000)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_BIT (0x00010000)
+
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_LSB (15)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_MASK (0x00008000)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_BIT (0x00008000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_LSB (14)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_MASK (0x00004000)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_BIT (0x00004000)
+
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_LSB (13)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_MASK (0x00002000)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_BIT (0x00002000)
+
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_LSB (12)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_MASK (0x00001000)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_BIT (0x00001000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_LSB (11)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_MASK (0x00000800)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_BIT (0x00000800)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_LSB (10)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_MASK (0x00000400)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_BIT (0x00000400)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_LSB (9)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_MASK (0x00000200)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_BIT (0x00000200)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_LSB (8)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_MASK (0x00000100)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_BIT (0x00000100)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_LSB (7)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_MASK (0x00000080)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_BIT (0x00000080)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_LSB (6)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_MASK (0x00000040)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_BIT (0x00000040)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_LSB (5)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_MASK (0x00000020)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_BIT (0x00000020)
+
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_LSB (4)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_MASK (0x00000010)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_BIT (0x00000010)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_LSB (3)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_MASK (0x00000008)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_BIT (0x00000008)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_LSB (2)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_MASK (0x00000004)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_BIT (0x00000004)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_LSB (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_MASK (0x00000002)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_BIT (0x00000002)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_LSB (0)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_MASK (0x00000001)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_BIT (0x00000001)
+
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_LSB (9)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_MASK (0x00000200)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_BIT (0x00000200)
+
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_LSB (8)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_MASK (0x00000100)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_BIT (0x00000100)
+
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_LSB (7)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_MASK (0x00000080)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_BIT (0x00000080)
+
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_LSB (6)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_MASK (0x00000040)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_BIT (0x00000040)
+
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_LSB (5)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_MASK (0x00000020)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_BIT (0x00000020)
+
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_LSB (4)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_MASK (0x00000010)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_BIT (0x00000010)
+
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_LSB (3)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_MASK (0x00000008)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_BIT (0x00000008)
+
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_LSB (2)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_MASK (0x00000004)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_BIT (0x00000004)
+
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_LSB (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_MASK (0x00000002)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_BIT (0x00000002)
+
+#define MDL1AO_CON212_EFUSE_VALID_LSB (0)
+#define MDL1AO_CON212_EFUSE_VALID_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_VALID_MASK (0x00000001)
+#define MDL1AO_CON212_EFUSE_VALID_BIT (0x00000001)
+#endif //#ifndef _CPH_C2K_L1_A0CFG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_95.h b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_95.h
new file mode 100644
index 0000000..267f31e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_95.h
@@ -0,0 +1,563 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_L1_A0CFG_H_
+#define _CPH_C2K_L1_A0CFG_H_
+#include "drvpdn.h"
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MODEML1_AO_CONFIG_REG_BASE (0xA6020000)
+
+#define MODEML1_AO_CONFIG_end (MODEML1_AO_CONFIG_REG_BASE + 0x350 + 1*4)
+
+
+
+#define MDL1AO_CON0 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x00))
+#define MDL1AO_CON1 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x04))
+#define MDL1AO_CON2 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x08))
+#define MDL1AO_CON4 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x10))
+#define MDL1AO_CON5 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x14))
+#define MDL1AO_CON6 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x18))
+#define MDL1AO_CON7 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x1c))
+#define MDL1AO_CON8 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x20))
+#define MDL1AO_CON9 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x24))
+#define MDL1AO_CON10 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x28))
+#define MDL1AO_CON11 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x2c))
+#define MDL1AO_CON12 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x30))
+#define MDL1AO_CON14 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x38))
+#define MDL1AO_CON15 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x3C))
+#define MDL1AO_CON16 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x40))
+#define MDL1AO_CON17 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x44))
+#define MDL1AO_CON18 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x48))
+#define MDL1AO_CON19 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x4C))
+#if 0 /* defined in drvpdn.h */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#define MDL1AO_CON212 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x350))
+
+
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_LSB (0)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_WIDTH (1)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_MASK (0x00000001)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_LSB (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_MASK (0x00000002)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_BIT (0x00000002)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_LSB (0)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_MASK (0x00000001)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_BIT (0x00000001)
+
+#define MDL1AO_CON2_BUS2X_DCM_CON_LSB (0)
+#define MDL1AO_CON2_BUS2X_DCM_CON_WIDTH (32)
+#define MDL1AO_CON2_BUS2X_DCM_CON_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_LSB (0)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_WIDTH (8)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_MASK (0x000000FF)
+
+#define MDL1AO_CON5_GLBCON_DBG_SEL_LSB (0)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_WIDTH (2)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_MASK (0x00000003)
+
+#define MDL1AO_CON6_BUS_PWR_AWARE_LSB (0)
+#define MDL1AO_CON6_BUS_PWR_AWARE_WIDTH (32)
+#define MDL1AO_CON6_BUS_PWR_AWARE_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON7_MBIST_OUT_SEL_LSB (0)
+#define MDL1AO_CON7_MBIST_OUT_SEL_WIDTH (4)
+#define MDL1AO_CON7_MBIST_OUT_SEL_MASK (0x0000000F)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_LSB (3)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_MASK (0x00000008)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_BIT (0x00000008)
+
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_LSB (2)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_MASK (0x00000004)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_BIT (0x00000004)
+
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_LSB (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_MASK (0x00000002)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_BIT (0x00000002)
+
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_LSB (0)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_MASK (0x00000001)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_LSB (0)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_WIDTH (1)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_MASK (0x00000001)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_BIT (0x00000001)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_LSB (2)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_MASK (0x00000004)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_BIT (0x00000004)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_LSB (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_MASK (0x00000002)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_BIT (0x00000002)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_LSB (0)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_MASK (0x00000001)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_BIT (0x00000001)
+
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_LSB (0)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_WIDTH (5)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_MASK (0x0000001F)
+
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_LSB (0)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_WIDTH (5)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_MASK (0x0000001F)
+
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_LSB (0)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_WIDTH (5)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_MASK (0x0000001F)
+
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_LSB (0)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_WIDTH (5)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_MASK (0x0000001F)
+
+#define MDL1AO_CON18_RG_DBG_SUB_EN_LSB (0)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_WIDTH (4)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_MASK (0x0000000F)
+
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_LSB (0)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_WIDTH (6)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_MASK (0x0000003F)
+
+#define MDL1AO_CON20_PDN_CDO_TTR_LSB (18)
+#define MDL1AO_CON20_PDN_CDO_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_CDO_TTR_MASK (0x00040000)
+#define MDL1AO_CON20_PDN_CDO_TTR_BIT (0x00040000)
+
+#define MDL1AO_CON20_PDN_C1X_TTR_LSB (17)
+#define MDL1AO_CON20_PDN_C1X_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C1X_TTR_MASK (0x00020000)
+#define MDL1AO_CON20_PDN_C1X_TTR_BIT (0x00020000)
+
+#define MDL1AO_CON20_PDN_FREQM_LSB (16)
+#define MDL1AO_CON20_PDN_FREQM_WIDTH (1)
+#define MDL1AO_CON20_PDN_FREQM_MASK (0x00010000)
+#define MDL1AO_CON20_PDN_FREQM_BIT (0x00010000)
+
+#define MDL1AO_CON20_PDN_DVFS_CTRL_LSB (15)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_MASK (0x00008000)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_BIT (0x00008000)
+
+#define MDL1AO_CON20_PDN_IDC_UART_LSB (14)
+#define MDL1AO_CON20_PDN_IDC_UART_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_UART_MASK (0x00004000)
+#define MDL1AO_CON20_PDN_IDC_UART_BIT (0x00004000)
+
+#define MDL1AO_CON20_PDN_BSI_LSB (13)
+#define MDL1AO_CON20_PDN_BSI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BSI_MASK (0x00002000)
+#define MDL1AO_CON20_PDN_BSI_BIT (0x00002000)
+
+#define MDL1AO_CON20_PDN_BPI_LSB (12)
+#define MDL1AO_CON20_PDN_BPI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BPI_MASK (0x00001000)
+#define MDL1AO_CON20_PDN_BPI_BIT (0x00001000)
+
+#define MDL1AO_CON20_PDN_IDC_CTRL_LSB (11)
+#define MDL1AO_CON20_PDN_IDC_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_CTRL_MASK (0x00000800)
+#define MDL1AO_CON20_PDN_IDC_CTRL_BIT (0x00000800)
+
+#define MDL1AO_CON20_PDN_LTE_SLP_LSB (10)
+#define MDL1AO_CON20_PDN_LTE_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_SLP_MASK (0x00000400)
+#define MDL1AO_CON20_PDN_LTE_SLP_BIT (0x00000400)
+
+#define MDL1AO_CON20_PDN_LTE_TMR_LSB (9)
+#define MDL1AO_CON20_PDN_LTE_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_TMR_MASK (0x00000200)
+#define MDL1AO_CON20_PDN_LTE_TMR_BIT (0x00000200)
+
+#define MDL1AO_CON20_PDN_FDD_SLP_LSB (8)
+#define MDL1AO_CON20_PDN_FDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_SLP_MASK (0x00000100)
+#define MDL1AO_CON20_PDN_FDD_SLP_BIT (0x00000100)
+
+#define MDL1AO_CON20_PDN_FDD_TMR_LSB (7)
+#define MDL1AO_CON20_PDN_FDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_TMR_MASK (0x00000080)
+#define MDL1AO_CON20_PDN_FDD_TMR_BIT (0x00000080)
+
+#define MDL1AO_CON20_PDN_TDD_SLP_LSB (6)
+#define MDL1AO_CON20_PDN_TDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_SLP_MASK (0x00000040)
+#define MDL1AO_CON20_PDN_TDD_SLP_BIT (0x00000040)
+
+#define MDL1AO_CON20_PDN_TDD_TMR_LSB (5)
+#define MDL1AO_CON20_PDN_TDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_TMR_MASK (0x00000020)
+#define MDL1AO_CON20_PDN_TDD_TMR_BIT (0x00000020)
+
+#define MDL1AO_CON20_PDN_TDMA_SLP_LSB (4)
+#define MDL1AO_CON20_PDN_TDMA_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDMA_SLP_MASK (0x00000010)
+#define MDL1AO_CON20_PDN_TDMA_SLP_BIT (0x00000010)
+
+#define MDL1AO_CON20_PDN_C2K1X_SLP_LSB (3)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_MASK (0x00000008)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_BIT (0x00000008)
+
+#define MDL1AO_CON20_PDN_C2K1X_TMR_LSB (2)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_MASK (0x00000004)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_BIT (0x00000004)
+
+#define MDL1AO_CON20_PDN_C2KDO_SLP_LSB (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_MASK (0x00000002)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_BIT (0x00000002)
+
+#define MDL1AO_CON20_PDN_C2KDO_TMR_LSB (0)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_MASK (0x00000001)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_BIT (0x00000001)
+
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_LSB (20)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_MASK (0x00100000)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_BIT (0x00100000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_LSB (21)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_MASK (0x00200000)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_BIT (0x00200000)
+
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_LSB (18)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_MASK (0x00040000)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_BIT (0x00040000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_LSB (17)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_MASK (0x00020000)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_BIT (0x00020000)
+
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_LSB (16)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_MASK (0x00010000)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_BIT (0x00010000)
+
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_LSB (15)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_MASK (0x00008000)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_BIT (0x00008000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_LSB (14)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_MASK (0x00004000)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_BIT (0x00004000)
+
+#define MDL1AO_PDN_SET_PDN_BSI_SET_LSB (13)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_MASK (0x00002000)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_BIT (0x00002000)
+
+#define MDL1AO_PDN_SET_PDN_BPI_SET_LSB (12)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_MASK (0x00001000)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_BIT (0x00001000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_LSB (11)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_MASK (0x00000800)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_BIT (0x00000800)
+
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_LSB (10)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_MASK (0x00000400)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_BIT (0x00000400)
+
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_LSB (9)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_MASK (0x00000200)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_BIT (0x00000200)
+
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_LSB (8)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_MASK (0x00000100)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_BIT (0x00000100)
+
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_LSB (7)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_MASK (0x00000080)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_BIT (0x00000080)
+
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_LSB (6)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_MASK (0x00000040)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_BIT (0x00000040)
+
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_LSB (5)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_MASK (0x00000020)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_BIT (0x00000020)
+
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_LSB (4)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_MASK (0x00000010)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_BIT (0x00000010)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_LSB (3)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_MASK (0x00000008)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_BIT (0x00000008)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_LSB (2)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_MASK (0x00000004)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_BIT (0x00000004)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_LSB (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_MASK (0x00000002)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_BIT (0x00000002)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_LSB (0)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_MASK (0x00000001)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_BIT (0x00000001)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_LSB (20)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_MASK (0x00100000)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_BIT (0x00100000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_LSB (21)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_MASK (0x00200000)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_BIT (0x00200000)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_LSB (18)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_MASK (0x00040000)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_BIT (0x00040000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_LSB (17)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_MASK (0x00020000)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_BIT (0x00020000)
+
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_LSB (16)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_MASK (0x00010000)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_BIT (0x00010000)
+
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_LSB (15)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_MASK (0x00008000)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_BIT (0x00008000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_LSB (14)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_MASK (0x00004000)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_BIT (0x00004000)
+
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_LSB (13)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_MASK (0x00002000)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_BIT (0x00002000)
+
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_LSB (12)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_MASK (0x00001000)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_BIT (0x00001000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_LSB (11)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_MASK (0x00000800)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_BIT (0x00000800)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_LSB (10)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_MASK (0x00000400)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_BIT (0x00000400)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_LSB (9)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_MASK (0x00000200)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_BIT (0x00000200)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_LSB (8)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_MASK (0x00000100)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_BIT (0x00000100)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_LSB (7)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_MASK (0x00000080)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_BIT (0x00000080)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_LSB (6)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_MASK (0x00000040)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_BIT (0x00000040)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_LSB (5)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_MASK (0x00000020)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_BIT (0x00000020)
+
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_LSB (4)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_MASK (0x00000010)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_BIT (0x00000010)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_LSB (3)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_MASK (0x00000008)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_BIT (0x00000008)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_LSB (2)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_MASK (0x00000004)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_BIT (0x00000004)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_LSB (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_MASK (0x00000002)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_BIT (0x00000002)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_LSB (0)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_MASK (0x00000001)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_BIT (0x00000001)
+
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_LSB (9)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_MASK (0x00000200)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_BIT (0x00000200)
+
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_LSB (8)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_MASK (0x00000100)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_BIT (0x00000100)
+
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_LSB (7)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_MASK (0x00000080)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_BIT (0x00000080)
+
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_LSB (6)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_MASK (0x00000040)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_BIT (0x00000040)
+
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_LSB (5)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_MASK (0x00000020)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_BIT (0x00000020)
+
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_LSB (4)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_MASK (0x00000010)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_BIT (0x00000010)
+
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_LSB (3)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_MASK (0x00000008)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_BIT (0x00000008)
+
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_LSB (2)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_MASK (0x00000004)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_BIT (0x00000004)
+
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_LSB (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_MASK (0x00000002)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_BIT (0x00000002)
+
+#define MDL1AO_CON212_EFUSE_VALID_LSB (0)
+#define MDL1AO_CON212_EFUSE_VALID_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_VALID_MASK (0x00000001)
+#define MDL1AO_CON212_EFUSE_VALID_BIT (0x00000001)
+#endif //#ifndef _CPH_C2K_L1_A0CFG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_97.h b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_97.h
new file mode 100644
index 0000000..bccc5c1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2kl1aocfg_97.h
@@ -0,0 +1,577 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_L1_A0CFG_H_
+#define _CPH_C2K_L1_A0CFG_H_
+#include "drvpdn.h"
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD97__) || defined(__MD97P__)
+#define MODEML1_AO_CONFIG_REG_BASE (0xA8020000)/*97*/
+#else
+#define MODEML1_AO_CONFIG_REG_BASE (0xA6020000)/*93 95*/
+#endif
+#define MODEML1_AO_CONFIG_end (MODEML1_AO_CONFIG_REG_BASE + 0x350 + 1*4)
+
+
+#define MDL1AO_CON0 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x00))
+#define MDL1AO_CON1 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x04))
+#define MDL1AO_CON2 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x08))
+#define MDL1AO_CON4 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x10))
+#define MDL1AO_CON5 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x14))
+#define MDL1AO_CON6 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x18))
+#define MDL1AO_CON7 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x1c))
+#define MDL1AO_CON8 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x20))
+#define MDL1AO_CON9 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x24))
+#define MDL1AO_CON10 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x28))
+#define MDL1AO_CON11 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x2c))
+#define MDL1AO_CON12 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x30))
+#define MDL1AO_CON14 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x38))
+#define MDL1AO_CON15 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x3C))
+#define MDL1AO_CON16 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x40))
+#define MDL1AO_CON17 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x44))
+#define MDL1AO_CON18 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x48))
+#define MDL1AO_CON19 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x4C))
+#if 0 /* defined in drvpdn.h */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#define MDL1AO_CON212 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x350))
+#if defined(__MD97__) || defined(__MD97P__)
+#define MDL1AO_CON13 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x5c))
+#define MDL1AO_CON21 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x60))
+#define MDL1AO_CON22 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x64))
+#define MDL1AO_CON23 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x68))
+#define MDL1AO_CON24 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x6c))
+
+#define MDL1AO_DVFS_DBG_SEL ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x70))
+#define MDL1AO_DVFS_DBG_EN ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x74))
+#define MDL1AO_DIGRF_P2P_CON_0 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x78))
+#define MDL1AO_DIGRF_P2P_CON_1 ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x7C))
+#define MDL1AO_BW_LMT_CON ((APBADDR32)(MODEML1_AO_CONFIG_REG_BASE + 0x80))
+#endif
+
+
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_LSB (0)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_WIDTH (1)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_MASK (0x00000001)
+#define MDL1AO_CON0_MDL1AO_MAS_BUS_IDLE_DIV_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_LSB (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_MASK (0x00000002)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SW_DIV2_BIT (0x00000002)
+
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_LSB (0)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_WIDTH (1)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_MASK (0x00000001)
+#define MDL1AO_CON1_FESYS_BUS2X_CK_SEL_BIT (0x00000001)
+
+#define MDL1AO_CON2_BUS2X_DCM_CON_LSB (0)
+#define MDL1AO_CON2_BUS2X_DCM_CON_WIDTH (32)
+#define MDL1AO_CON2_BUS2X_DCM_CON_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_LSB (0)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_WIDTH (8)
+#define MDL1AO_CON4_IDC_UART_DBG_SEL_MASK (0x000000FF)
+
+#define MDL1AO_CON5_GLBCON_DBG_SEL_LSB (0)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_WIDTH (2)
+#define MDL1AO_CON5_GLBCON_DBG_SEL_MASK (0x00000003)
+
+#define MDL1AO_CON6_BUS_PWR_AWARE_LSB (0)
+#define MDL1AO_CON6_BUS_PWR_AWARE_WIDTH (32)
+#define MDL1AO_CON6_BUS_PWR_AWARE_MASK (0xFFFFFFFF)
+
+#define MDL1AO_CON7_MBIST_OUT_SEL_LSB (0)
+#define MDL1AO_CON7_MBIST_OUT_SEL_WIDTH (4)
+#define MDL1AO_CON7_MBIST_OUT_SEL_MASK (0x0000000F)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON8_BSI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON8_BSI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_LSB (2)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_WIDTH (30)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_ADDR_MASK (0xFFFFFFFC)
+
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_LSB (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_MASK (0x00000002)
+#define MDL1AO_CON9_BPI_MM_P2P_RX_CLOCK_EN_BIT (0x00000002)
+
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_LSB (0)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_WIDTH (1)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_MASK (0x00000001)
+#define MDL1AO_CON9_BPI_MM_P2P_ERR_TIMEOUT_BIT (0x00000001)
+
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_LSB (3)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_MASK (0x00000008)
+#define MDL1AO_CON10_RAKE_MODEMCTI_WAKEUP_MASK_BIT (0x00000008)
+
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_LSB (2)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_MASK (0x00000004)
+#define MDL1AO_CON10_RAKE_CSYS_WAKEUP_MASK_BIT (0x00000004)
+
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_LSB (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_MASK (0x00000002)
+#define MDL1AO_CON10_SCQ_MODEMCTI_WAKEUP_MASK_BIT (0x00000002)
+
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_LSB (0)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_WIDTH (1)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_MASK (0x00000001)
+#define MDL1AO_CON10_SCQ_CSYS_WAKEUP_MASK_BIT (0x00000001)
+
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_LSB (0)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_WIDTH (1)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_MASK (0x00000001)
+#define MDL1AO_CON11_FESYS_BUS2X_CK_DFS_EN_BIT (0x00000001)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_LSB (2)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_MASK (0x00000004)
+#define MDL1AO_CON12_GPS_SYNC_MASK_EVDO_BIT (0x00000004)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_LSB (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_MASK (0x00000002)
+#define MDL1AO_CON12_GPS_SYNC_MASK_1XRTT_BIT (0x00000002)
+
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_LSB (0)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_WIDTH (1)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_MASK (0x00000001)
+#define MDL1AO_CON12_GPS_SYNC_MASK_LWTG_BIT (0x00000001)
+
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_LSB (0)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_WIDTH (5)
+#define MDL1AO_CON14_RG_DBG_MOD_SEL0_MASK (0x0000001F)
+
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_LSB (0)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_WIDTH (5)
+#define MDL1AO_CON15_RG_DBG_MOD_SEL1_MASK (0x0000001F)
+
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_LSB (0)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_WIDTH (5)
+#define MDL1AO_CON16_RG_DBG_MOD_SEL2_MASK (0x0000001F)
+
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_LSB (0)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_WIDTH (5)
+#define MDL1AO_CON17_RG_DBG_MOD_SEL3_MASK (0x0000001F)
+
+#define MDL1AO_CON18_RG_DBG_SUB_EN_LSB (0)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_WIDTH (4)
+#define MDL1AO_CON18_RG_DBG_SUB_EN_MASK (0x0000000F)
+
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_LSB (0)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_WIDTH (6)
+#define MDL1AO_CON19_MDL1AO_DDR_CLK_EN_MASK (0x0000003F)
+
+#define MDL1AO_CON20_PDN_CDO_TTR_LSB (18)
+#define MDL1AO_CON20_PDN_CDO_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_CDO_TTR_MASK (0x00040000)
+#define MDL1AO_CON20_PDN_CDO_TTR_BIT (0x00040000)
+
+#define MDL1AO_CON20_PDN_C1X_TTR_LSB (17)
+#define MDL1AO_CON20_PDN_C1X_TTR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C1X_TTR_MASK (0x00020000)
+#define MDL1AO_CON20_PDN_C1X_TTR_BIT (0x00020000)
+
+#define MDL1AO_CON20_PDN_FREQM_LSB (16)
+#define MDL1AO_CON20_PDN_FREQM_WIDTH (1)
+#define MDL1AO_CON20_PDN_FREQM_MASK (0x00010000)
+#define MDL1AO_CON20_PDN_FREQM_BIT (0x00010000)
+
+#define MDL1AO_CON20_PDN_DVFS_CTRL_LSB (15)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_MASK (0x00008000)
+#define MDL1AO_CON20_PDN_DVFS_CTRL_BIT (0x00008000)
+
+#define MDL1AO_CON20_PDN_IDC_UART_LSB (14)
+#define MDL1AO_CON20_PDN_IDC_UART_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_UART_MASK (0x00004000)
+#define MDL1AO_CON20_PDN_IDC_UART_BIT (0x00004000)
+
+#define MDL1AO_CON20_PDN_BSI_LSB (13)
+#define MDL1AO_CON20_PDN_BSI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BSI_MASK (0x00002000)
+#define MDL1AO_CON20_PDN_BSI_BIT (0x00002000)
+
+#define MDL1AO_CON20_PDN_BPI_LSB (12)
+#define MDL1AO_CON20_PDN_BPI_WIDTH (1)
+#define MDL1AO_CON20_PDN_BPI_MASK (0x00001000)
+#define MDL1AO_CON20_PDN_BPI_BIT (0x00001000)
+
+#define MDL1AO_CON20_PDN_IDC_CTRL_LSB (11)
+#define MDL1AO_CON20_PDN_IDC_CTRL_WIDTH (1)
+#define MDL1AO_CON20_PDN_IDC_CTRL_MASK (0x00000800)
+#define MDL1AO_CON20_PDN_IDC_CTRL_BIT (0x00000800)
+
+#define MDL1AO_CON20_PDN_LTE_SLP_LSB (10)
+#define MDL1AO_CON20_PDN_LTE_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_SLP_MASK (0x00000400)
+#define MDL1AO_CON20_PDN_LTE_SLP_BIT (0x00000400)
+
+#define MDL1AO_CON20_PDN_LTE_TMR_LSB (9)
+#define MDL1AO_CON20_PDN_LTE_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_LTE_TMR_MASK (0x00000200)
+#define MDL1AO_CON20_PDN_LTE_TMR_BIT (0x00000200)
+
+#define MDL1AO_CON20_PDN_FDD_SLP_LSB (8)
+#define MDL1AO_CON20_PDN_FDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_SLP_MASK (0x00000100)
+#define MDL1AO_CON20_PDN_FDD_SLP_BIT (0x00000100)
+
+#define MDL1AO_CON20_PDN_FDD_TMR_LSB (7)
+#define MDL1AO_CON20_PDN_FDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_FDD_TMR_MASK (0x00000080)
+#define MDL1AO_CON20_PDN_FDD_TMR_BIT (0x00000080)
+
+#define MDL1AO_CON20_PDN_TDD_SLP_LSB (6)
+#define MDL1AO_CON20_PDN_TDD_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_SLP_MASK (0x00000040)
+#define MDL1AO_CON20_PDN_TDD_SLP_BIT (0x00000040)
+
+#define MDL1AO_CON20_PDN_TDD_TMR_LSB (5)
+#define MDL1AO_CON20_PDN_TDD_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDD_TMR_MASK (0x00000020)
+#define MDL1AO_CON20_PDN_TDD_TMR_BIT (0x00000020)
+
+#define MDL1AO_CON20_PDN_TDMA_SLP_LSB (4)
+#define MDL1AO_CON20_PDN_TDMA_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_TDMA_SLP_MASK (0x00000010)
+#define MDL1AO_CON20_PDN_TDMA_SLP_BIT (0x00000010)
+
+#define MDL1AO_CON20_PDN_C2K1X_SLP_LSB (3)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_MASK (0x00000008)
+#define MDL1AO_CON20_PDN_C2K1X_SLP_BIT (0x00000008)
+
+#define MDL1AO_CON20_PDN_C2K1X_TMR_LSB (2)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_MASK (0x00000004)
+#define MDL1AO_CON20_PDN_C2K1X_TMR_BIT (0x00000004)
+
+#define MDL1AO_CON20_PDN_C2KDO_SLP_LSB (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_MASK (0x00000002)
+#define MDL1AO_CON20_PDN_C2KDO_SLP_BIT (0x00000002)
+
+#define MDL1AO_CON20_PDN_C2KDO_TMR_LSB (0)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_WIDTH (1)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_MASK (0x00000001)
+#define MDL1AO_CON20_PDN_C2KDO_TMR_BIT (0x00000001)
+
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_LSB (20)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_MASK (0x00100000)
+#define MDL1AO_PDN_SET_PDN_CDO_EVENTGEN_SET_BIT (0x00100000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_LSB (21)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_MASK (0x00200000)
+#define MDL1AO_PDN_SET_PDN_C1X_EVENTGEN_SET_BIT (0x00200000)
+
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_LSB (18)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_MASK (0x00040000)
+#define MDL1AO_PDN_SET_PDN_CDO_TTR_SET_BIT (0x00040000)
+
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_LSB (17)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_MASK (0x00020000)
+#define MDL1AO_PDN_SET_PDN_C1X_TTR_SET_BIT (0x00020000)
+
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_LSB (16)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_MASK (0x00010000)
+#define MDL1AO_PDN_SET_PDN_FREQM_SET_BIT (0x00010000)
+
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_LSB (15)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_MASK (0x00008000)
+#define MDL1AO_PDN_SET_PDN_DVFS_CTRL_SET_BIT (0x00008000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_LSB (14)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_MASK (0x00004000)
+#define MDL1AO_PDN_SET_PDN_IDC_UART_SET_BIT (0x00004000)
+
+#define MDL1AO_PDN_SET_PDN_BSI_SET_LSB (13)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_MASK (0x00002000)
+#define MDL1AO_PDN_SET_PDN_BSI_SET_BIT (0x00002000)
+
+#define MDL1AO_PDN_SET_PDN_BPI_SET_LSB (12)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_MASK (0x00001000)
+#define MDL1AO_PDN_SET_PDN_BPI_SET_BIT (0x00001000)
+
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_LSB (11)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_MASK (0x00000800)
+#define MDL1AO_PDN_SET_PDN_IDC_CTRL_SET_BIT (0x00000800)
+
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_LSB (10)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_MASK (0x00000400)
+#define MDL1AO_PDN_SET_PDN_LTE_SLP_SET_BIT (0x00000400)
+
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_LSB (9)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_MASK (0x00000200)
+#define MDL1AO_PDN_SET_PDN_LTE_TMR_SET_BIT (0x00000200)
+
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_LSB (8)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_MASK (0x00000100)
+#define MDL1AO_PDN_SET_PDN_FDD_SLP_SET_BIT (0x00000100)
+
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_LSB (7)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_MASK (0x00000080)
+#define MDL1AO_PDN_SET_PDN_FDD_TMR_SET_BIT (0x00000080)
+
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_LSB (6)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_MASK (0x00000040)
+#define MDL1AO_PDN_SET_PDN_TDD_SLP_SET_BIT (0x00000040)
+
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_LSB (5)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_MASK (0x00000020)
+#define MDL1AO_PDN_SET_PDN_TDD_TMR_SET_BIT (0x00000020)
+
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_LSB (4)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_MASK (0x00000010)
+#define MDL1AO_PDN_SET_PDN_TDMA_SLP_SET_BIT (0x00000010)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_LSB (3)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_MASK (0x00000008)
+#define MDL1AO_PDN_SET_PDN_C2K1X_SLP_SET_BIT (0x00000008)
+
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_LSB (2)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_MASK (0x00000004)
+#define MDL1AO_PDN_SET_PDN_C2K1X_TMR_SET_BIT (0x00000004)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_LSB (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_MASK (0x00000002)
+#define MDL1AO_PDN_SET_PDN_C2KDO_SLP_SET_BIT (0x00000002)
+
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_LSB (0)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_WIDTH (1)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_MASK (0x00000001)
+#define MDL1AO_PDN_SET_PDN_C2KDO_TMR_SET_BIT (0x00000001)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_LSB (20)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_MASK (0x00100000)
+#define MDL1AO_PDN_CLR_PDN_CDO_EVENTGEN_CLR_BIT (0x00100000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_LSB (21)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_MASK (0x00200000)
+#define MDL1AO_PDN_CLR_PDN_C1X_EVENTGEN_CLR_BIT (0x00200000)
+
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_LSB (18)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_MASK (0x00040000)
+#define MDL1AO_PDN_CLR_PDN_CDO_TTR_CLR_BIT (0x00040000)
+
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_LSB (17)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_MASK (0x00020000)
+#define MDL1AO_PDN_CLR_PDN_C1X_TTR_CLR_BIT (0x00020000)
+
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_LSB (16)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_MASK (0x00010000)
+#define MDL1AO_PDN_CLR_PDN_FREQM_CLR_BIT (0x00010000)
+
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_LSB (15)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_MASK (0x00008000)
+#define MDL1AO_PDN_CLR_PDN_DVFS_CTRL_CLR_BIT (0x00008000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_LSB (14)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_MASK (0x00004000)
+#define MDL1AO_PDN_CLR_PDN_IDC_UART_CLR_BIT (0x00004000)
+
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_LSB (13)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_MASK (0x00002000)
+#define MDL1AO_PDN_CLR_PDN_BSI_CLR_BIT (0x00002000)
+
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_LSB (12)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_MASK (0x00001000)
+#define MDL1AO_PDN_CLR_PDN_BPI_CLR_BIT (0x00001000)
+
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_LSB (11)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_MASK (0x00000800)
+#define MDL1AO_PDN_CLR_PDN_IDC_CTRL_CLR_BIT (0x00000800)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_LSB (10)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_MASK (0x00000400)
+#define MDL1AO_PDN_CLR_PDN_LTE_SLP_CLR_BIT (0x00000400)
+
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_LSB (9)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_MASK (0x00000200)
+#define MDL1AO_PDN_CLR_PDN_LTE_TMR_CLR_BIT (0x00000200)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_LSB (8)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_MASK (0x00000100)
+#define MDL1AO_PDN_CLR_PDN_FDD_SLP_CLR_BIT (0x00000100)
+
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_LSB (7)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_MASK (0x00000080)
+#define MDL1AO_PDN_CLR_PDN_FDD_TMR_CLR_BIT (0x00000080)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_LSB (6)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_MASK (0x00000040)
+#define MDL1AO_PDN_CLR_PDN_TDD_SLP_CLR_BIT (0x00000040)
+
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_LSB (5)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_MASK (0x00000020)
+#define MDL1AO_PDN_CLR_PDN_TDD_TMR_CLR_BIT (0x00000020)
+
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_LSB (4)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_MASK (0x00000010)
+#define MDL1AO_PDN_CLR_PDN_TDMA_SLP_CLR_BIT (0x00000010)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_LSB (3)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_MASK (0x00000008)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_SLP_CLR_BIT (0x00000008)
+
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_LSB (2)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_MASK (0x00000004)
+#define MDL1AO_PDN_CLR_PDN_C2K1X_TMR_CLR_BIT (0x00000004)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_LSB (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_MASK (0x00000002)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_SLP_CLR_BIT (0x00000002)
+
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_LSB (0)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_WIDTH (1)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_MASK (0x00000001)
+#define MDL1AO_PDN_CLR_PDN_C2KDO_TMR_CLR_BIT (0x00000001)
+
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_LSB (9)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_MASK (0x00000200)
+#define MDL1AO_CON212_EFUSE_LTE_CA_DISABLE_BIT (0x00000200)
+
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_LSB (8)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_MASK (0x00000100)
+#define MDL1AO_CON212_EFUSE_C2K_DISABLE_BIT (0x00000100)
+
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_LSB (7)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_MASK (0x00000080)
+#define MDL1AO_CON212_EFUSE_LTE_FDD_DISABLE_BIT (0x00000080)
+
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_LSB (6)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_MASK (0x00000040)
+#define MDL1AO_CON212_EFUSE_LTE_TDD_DISABLE_BIT (0x00000040)
+
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_LSB (5)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_MASK (0x00000020)
+#define MDL1AO_CON212_EFUSE_MD1_DISABLE_BIT (0x00000020)
+
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_LSB (4)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_MASK (0x00000010)
+#define MDL1AO_CON212_EFUSE_JTAG_DIS_BIT (0x00000010)
+
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_LSB (3)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_MASK (0x00000008)
+#define MDL1AO_CON212_EFUSE_MD2G_LOCK_2G_BIT (0x00000008)
+
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_LSB (2)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_MASK (0x00000004)
+#define MDL1AO_CON212_EFUSE_MD2G_PROTECT_B_BIT (0x00000004)
+
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_LSB (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_MASK (0x00000002)
+#define MDL1AO_CON212_EFUSE_SW_JTAG_CON_BIT (0x00000002)
+
+#define MDL1AO_CON212_EFUSE_VALID_LSB (0)
+#define MDL1AO_CON212_EFUSE_VALID_WIDTH (1)
+#define MDL1AO_CON212_EFUSE_VALID_MASK (0x00000001)
+#define MDL1AO_CON212_EFUSE_VALID_BIT (0x00000001)
+#endif //#ifndef _CPH_C2K_L1_A0CFG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit.h
new file mode 100644
index 0000000..8b951e2
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphc2krxbrpdvit_93.h"
+#elif defined(__MD95__)
+#include "cphc2krxbrpdvit_93.h"
+#elif defined(__MD97__)
+#include "cphc2krxbrpdvit_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_93.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_93.h
new file mode 100644
index 0000000..cafe5a5
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_93.h
@@ -0,0 +1,1862 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RX_BRP_DVIT_H_
+#define _CPH_C2K_RX_BRP_DVIT_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCT_DVIT_REG_BASE (0xAD070000)
+
+#define RXBRP_WCT_DVIT_end (RXBRP_WCT_DVIT_REG_BASE + 0x4038 + 1*4)
+
+
+
+#define DBRP_VITW_WT_CTRL ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0000))
+#define DBRP_VITW_WT_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0004))
+#define DBRP_VITW_WT_DONE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0008))
+#define DBRP_VITW_WT_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x000c))
+#define DBRP_VITW_WT_DONE_VEC ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0010))
+#define DBRP_VITW_WT_CHEN ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0018))
+#define DBRP_VITW_WT_BCH_DMACFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0100))
+#define DBRP_VITW_WT_BCH_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0104))
+#define DBRP_VITW_WT_BCH_SFN ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0108))
+#define DBRP_VITW_WT_BCH_SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x010c))
+#define DBRP_VITW_WT_BCH_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0110))
+#define DBRP_VITW_WT_BCH_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0114))
+#define DBRP_VITW_WT_TRCH0_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1000))
+#define DBRP_VITW_WT_TRCH0_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1004))
+#define DBRP_VITW_WT_TRCH0_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1008))
+#define DBRP_VITW_WT_TRCH0_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x100c))
+#define DBRP_VITW_WT_TRCH0_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1010))
+#define DBRP_VITW_WT_TRCH0_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1014))
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1018))
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x101c))
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1020))
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1024))
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1028))
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x102C))
+#define DBRP_VITW_WT_TRCH0_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1030))
+#define DBRP_VITW_WT_TRCH0_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1034))
+#define DBRP_VITW_WT_TRCH1_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1100))
+#define DBRP_VITW_WT_TRCH1_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1104))
+#define DBRP_VITW_WT_TRCH1_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1108))
+#define DBRP_VITW_WT_TRCH1_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x110c))
+#define DBRP_VITW_WT_TRCH1_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1110))
+#define DBRP_VITW_WT_TRCH1_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1114))
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1118))
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x111c))
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1120))
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1124))
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1128))
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x112C))
+#define DBRP_VITW_WT_TRCH1_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1130))
+#define DBRP_VITW_WT_TRCH1_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1134))
+#define DBRP_VITW_WT_TRCH2_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1200))
+#define DBRP_VITW_WT_TRCH2_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1204))
+#define DBRP_VITW_WT_TRCH2_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1208))
+#define DBRP_VITW_WT_TRCH2_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x120c))
+#define DBRP_VITW_WT_TRCH2_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1210))
+#define DBRP_VITW_WT_TRCH2_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1214))
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1218))
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x121c))
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1220))
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1224))
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1228))
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x122C))
+#define DBRP_VITW_WT_TRCH2_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1230))
+#define DBRP_VITW_WT_TRCH2_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1234))
+#define DBRP_VITW_WT_TRCH3_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1300))
+#define DBRP_VITW_WT_TRCH3_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1304))
+#define DBRP_VITW_WT_TRCH3_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1308))
+#define DBRP_VITW_WT_TRCH3_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x130c))
+#define DBRP_VITW_WT_TRCH3_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1310))
+#define DBRP_VITW_WT_TRCH3_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1314))
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1318))
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x131c))
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1320))
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1324))
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1328))
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x132C))
+#define DBRP_VITW_WT_TRCH3_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1330))
+#define DBRP_VITW_WT_TRCH3_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1334))
+#define DBRP_VITW_WT_TRCH4_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1400))
+#define DBRP_VITW_WT_TRCH4_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1404))
+#define DBRP_VITW_WT_TRCH4_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1408))
+#define DBRP_VITW_WT_TRCH4_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x140c))
+#define DBRP_VITW_WT_TRCH4_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1410))
+#define DBRP_VITW_WT_TRCH4_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1414))
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1418))
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x141c))
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1420))
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1424))
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1428))
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x142C))
+#define DBRP_VITW_WT_TRCH4_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1430))
+#define DBRP_VITW_WT_TRCH4_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1434))
+#define DBRP_VITW_WT_TRCH5_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1500))
+#define DBRP_VITW_WT_TRCH5_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1504))
+#define DBRP_VITW_WT_TRCH5_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1508))
+#define DBRP_VITW_WT_TRCH5_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x150c))
+#define DBRP_VITW_WT_TRCH5_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1510))
+#define DBRP_VITW_WT_TRCH5_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1514))
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1518))
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x151c))
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1520))
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1524))
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1528))
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x152C))
+#define DBRP_VITW_WT_TRCH5_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1530))
+#define DBRP_VITW_WT_TRCH5_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1534))
+#define DBRP_VITW_WT_TRCH6_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1600))
+#define DBRP_VITW_WT_TRCH6_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1604))
+#define DBRP_VITW_WT_TRCH6_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1608))
+#define DBRP_VITW_WT_TRCH6_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x160c))
+#define DBRP_VITW_WT_TRCH6_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1610))
+#define DBRP_VITW_WT_TRCH6_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1614))
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1618))
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x161c))
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1620))
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1624))
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1628))
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x162C))
+#define DBRP_VITW_WT_TRCH6_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1630))
+#define DBRP_VITW_WT_TRCH6_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1634))
+#define DBRP_VITW_WT_TRCH7_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1700))
+#define DBRP_VITW_WT_TRCH7_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1704))
+#define DBRP_VITW_WT_TRCH7_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1708))
+#define DBRP_VITW_WT_TRCH7_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x170c))
+#define DBRP_VITW_WT_TRCH7_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1710))
+#define DBRP_VITW_WT_TRCH7_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1714))
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1718))
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x171c))
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1720))
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1724))
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1728))
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x172C))
+#define DBRP_VITW_WT_TRCH7_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1730))
+#define DBRP_VITW_WT_TRCH7_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1734))
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2000))
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2004))
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2008))
+#define DBRP_VITW_WT_BTFD1_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2010))
+#define DBRP_VITW_WT_BTFD1_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2014))
+#define DBRP_VITW_WT_BTFD2_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2020))
+#define DBRP_VITW_WT_BTFD2_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2024))
+#define DBRP_VITW_WT_BTFD3_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2030))
+#define DBRP_VITW_WT_BTFD3_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2034))
+#define DBRP_VITW_WT_BTFD_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2080))
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2100))
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2104))
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2108))
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2200))
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2204))
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2208))
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2300))
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2304))
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2308))
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2400))
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2404))
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2408))
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2500))
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2504))
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2508))
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2600))
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2604))
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2608))
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2700))
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2704))
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2708))
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2800))
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2804))
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2808))
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2900))
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2904))
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2908))
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A00))
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A04))
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A08))
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B00))
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B04))
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B08))
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C00))
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C04))
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C08))
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D00))
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D04))
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D08))
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E00))
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E04))
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E08))
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F00))
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F04))
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F08))
+#define DBRP_VITW_C_RESET ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3000))
+#define DBRP_VITW_C_LVA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3004))
+#define DBRP_VITW_C_PCH_CONF ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3008))
+#define DBRP_VITW_C_FIRST_FRM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x300C))
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3010))
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3014))
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3018))
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x301C))
+#define DBRP_VITW_C_SCH_DMA_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3020))
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3024))
+#define DBRP_VITW_C_SCH_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3028))
+#define DBRP_VITW_C_FCH_FULL_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x302C))
+#define DBRP_VITW_C_FCH_HALF_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3030))
+#define DBRP_VITW_C_FCH_QUAT_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3034))
+#define DBRP_VITW_C_FCH_EIGH_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3038))
+#define DBRP_VITW_C_SCH_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x303C))
+#define DBRP_VITW_C_FCH_FULL_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3040))
+#define DBRP_VITW_C_FCH_HALF_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3044))
+#define DBRP_VITW_C_FCH_QUAT_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3048))
+#define DBRP_VITW_C_FCH_EIGH_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x304C))
+#define DBRP_VITW_C_SCH_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3050))
+#define DBRP_VITW_C_FCH_FULL_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3054))
+#define DBRP_VITW_C_FCH_HALF_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3058))
+#define DBRP_VITW_C_FCH_QUAT_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x305C))
+#define DBRP_VITW_C_FCH_EIGH_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3060))
+#define DBRP_VITW_C_SCH_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3064))
+#define DBRP_VITW_C_FCH_CRC_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3068))
+#define DBRP_VITW_C_SCH_CRC_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x306C))
+#define DBRP_VITW_C_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3070))
+#define DBRP_VITW_C_DONE_VEC ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3074))
+#define DBRP_VITW_C_DONE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3078))
+#define DBRP_VITW_C_FCH_FULL_USAGE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x307C))
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3080))
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3084))
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3088))
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x308C))
+#define DBRP_VITW_C_SCH_DMA_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3090))
+#define DBRP_VITW_MPU ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4000))
+#define DBRP_VITW_MPU_VIO ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4004))
+#define DBRP_VITW_MPU0 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4008))
+#define DBRP_VITW_MPU0_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x400C))
+#define DBRP_VITW_MPU0_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4010))
+#define DBRP_VITW_MPU1 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4014))
+#define DBRP_VITW_MPU1_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4018))
+#define DBRP_VITW_MPU1_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x401C))
+#define DBRP_VITW_MPU2 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4020))
+#define DBRP_VITW_MPU2_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4024))
+#define DBRP_VITW_MPU2_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4028))
+#define DBRP_VITW_DBG0 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x402C))
+#define DBRP_VITW_DBG1 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4030))
+#define DBRP_VITW_DBG2 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4034))
+#define DBRP_VITW_DBG3 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4038))
+
+
+#define DBRP_VITW_WT_CTRL_SW_RESET_LSB (4)
+#define DBRP_VITW_WT_CTRL_SW_RESET_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_SW_RESET_MASK (0x00000010)
+#define DBRP_VITW_WT_CTRL_SW_RESET_BIT (0x00000010)
+
+#define DBRP_VITW_WT_CTRL_Mode_LSB (0)
+#define DBRP_VITW_WT_CTRL_Mode_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_Mode_MASK (0x00000001)
+#define DBRP_VITW_WT_CTRL_Mode_BIT (0x00000001)
+
+#define DBRP_VITW_WT_START_ACC_START_LSB (15)
+#define DBRP_VITW_WT_START_ACC_START_WIDTH (1)
+#define DBRP_VITW_WT_START_ACC_START_MASK (0x00008000)
+#define DBRP_VITW_WT_START_ACC_START_BIT (0x00008000)
+
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_LSB (0)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_MASK (0x00000001)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_LSB (0)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_WIDTH (1)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_MASK (0x00000001)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_BIT (0x00000001)
+
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_LSB (8)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_MASK (0x00000100)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_BIT (0x00000100)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_LSB (7)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_MASK (0x00000080)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_BIT (0x00000080)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_LSB (6)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_MASK (0x00000040)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_BIT (0x00000040)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_LSB (5)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_MASK (0x00000020)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_BIT (0x00000020)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_LSB (4)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_MASK (0x00000010)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_BIT (0x00000010)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_LSB (3)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_MASK (0x00000008)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_BIT (0x00000008)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_LSB (2)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_MASK (0x00000004)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_BIT (0x00000004)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_LSB (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_MASK (0x00000002)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_BIT (0x00000002)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_LSB (0)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_MASK (0x00000001)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_BIT (0x00000001)
+
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_LSB (15)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_WIDTH (1)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_MASK (0x00008000)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_BIT (0x00008000)
+
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_LSB (8)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_WIDTH (1)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_MASK (0x00000100)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_BIT (0x00000100)
+
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_LSB (0)
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_WIDTH (8)
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_MASK (0x000000FF)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_LSB (8)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_MASK (0x00000100)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_BIT (0x00000100)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_LSB (14)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_WIDTH (1)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_MASK (0x00004000)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_BIT (0x00004000)
+
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_LSB (0)
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_WIDTH (11)
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_MASK (0x000007FF)
+
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_LSB (0)
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_WIDTH (21)
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_LSB (0)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_MASK (0x00000001)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_BIT (0x00000001)
+
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_C_RESET_SW_RESET_LSB (0)
+#define DBRP_VITW_C_RESET_SW_RESET_WIDTH (1)
+#define DBRP_VITW_C_RESET_SW_RESET_MASK (0x00000001)
+#define DBRP_VITW_C_RESET_SW_RESET_BIT (0x00000001)
+
+#define DBRP_VITW_C_LVA_LVA_EN_LSB (0)
+#define DBRP_VITW_C_LVA_LVA_EN_WIDTH (1)
+#define DBRP_VITW_C_LVA_LVA_EN_MASK (0x00000001)
+#define DBRP_VITW_C_LVA_LVA_EN_BIT (0x00000001)
+
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_LSB (0)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_WIDTH (1)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_MASK (0x00000001)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_BIT (0x00000001)
+
+#define DBRP_VITW_C_FIRST_FRM_START_LSB (0)
+#define DBRP_VITW_C_FIRST_FRM_START_WIDTH (1)
+#define DBRP_VITW_C_FIRST_FRM_START_MASK (0x00000001)
+#define DBRP_VITW_C_FIRST_FRM_START_BIT (0x00000001)
+
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_LSB (7)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_MASK (0x00000080)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_BIT (0x00000080)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_LSB (6)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_MASK (0x00000040)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_BIT (0x00000040)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_LSB (7)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_MASK (0x00000080)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_BIT (0x00000080)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_LSB (6)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_MASK (0x00000040)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_BIT (0x00000040)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_SCH_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_SCH_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_SCH_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_SCH_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_SCH_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_SCH_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_LSB (3)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_MASK (0x00000008)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_BIT (0x00000008)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_LSB (2)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_MASK (0x00000004)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_BIT (0x00000004)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_LSB (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_MASK (0x00000002)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_BIT (0x00000002)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_LSB (0)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_MASK (0x00000001)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_LSB (0)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_WIDTH (1)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_MASK (0x00000001)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_C_STATUS_VITW_BUSY_LSB (0)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_WIDTH (1)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_MASK (0x00000001)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_BIT (0x00000001)
+
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_LSB (3)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_MASK (0x00000008)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_BIT (0x00000008)
+
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_LSB (2)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_MASK (0x00000004)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_BIT (0x00000004)
+
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_LSB (1)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_MASK (0x00000002)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_BIT (0x00000002)
+
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_LSB (0)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_MASK (0x00000001)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_BIT (0x00000001)
+
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_LSB (0)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_WIDTH (1)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_MASK (0x00000001)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_BIT (0x00000001)
+
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_WIDTH (2)
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_MASK (0x00000003)
+
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU_VIOLATE_LSB (0)
+#define DBRP_VITW_MPU_VIOLATE_WIDTH (1)
+#define DBRP_VITW_MPU_VIOLATE_MASK (0x00000001)
+#define DBRP_VITW_MPU_VIOLATE_BIT (0x00000001)
+
+#define DBRP_VITW_MPU_VIO_ADR_LSB (0)
+#define DBRP_VITW_MPU_VIO_ADR_WIDTH (32)
+#define DBRP_VITW_MPU_VIO_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU0_EN_LSB (0)
+#define DBRP_VITW_MPU0_EN_WIDTH (1)
+#define DBRP_VITW_MPU0_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU0_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU0_START_ADR_LSB (0)
+#define DBRP_VITW_MPU0_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU0_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU0_END_ADR_LSB (0)
+#define DBRP_VITW_MPU0_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU0_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU1_EN_LSB (0)
+#define DBRP_VITW_MPU1_EN_WIDTH (1)
+#define DBRP_VITW_MPU1_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU1_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU1_START_ADR_LSB (0)
+#define DBRP_VITW_MPU1_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU1_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU1_END_ADR_LSB (0)
+#define DBRP_VITW_MPU1_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU1_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU2_EN_LSB (0)
+#define DBRP_VITW_MPU2_EN_WIDTH (1)
+#define DBRP_VITW_MPU2_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU2_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU2_START_ADR_LSB (0)
+#define DBRP_VITW_MPU2_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU2_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU2_END_ADR_LSB (0)
+#define DBRP_VITW_MPU2_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU2_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_DBG0_VITW_BCH_CS_LSB (25)
+#define DBRP_VITW_DBG0_VITW_BCH_CS_WIDTH (4)
+#define DBRP_VITW_DBG0_VITW_BCH_CS_MASK (0x1E000000)
+
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_LSB (17)
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_WIDTH (8)
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_MASK (0x01FE0000)
+
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_LSB (10)
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_WIDTH (7)
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_MASK (0x0001FC00)
+
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_LSB (0)
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_WIDTH (10)
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_MASK (0x000003FF)
+
+#define DBRP_VITW_DBG1_VITW_SCH_CS_LSB (7)
+#define DBRP_VITW_DBG1_VITW_SCH_CS_WIDTH (5)
+#define DBRP_VITW_DBG1_VITW_SCH_CS_MASK (0x00000F80)
+
+#define DBRP_VITW_DBG1_VITW_FCH_CS_LSB (0)
+#define DBRP_VITW_DBG1_VITW_FCH_CS_WIDTH (7)
+#define DBRP_VITW_DBG1_VITW_FCH_CS_MASK (0x0000007F)
+
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_LSB (28)
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_WIDTH (4)
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_MASK (0xF0000000)
+
+#define DBRP_VITW_DBG2_VINFO_CS_LSB (16)
+#define DBRP_VITW_DBG2_VINFO_CS_WIDTH (11)
+#define DBRP_VITW_DBG2_VINFO_CS_MASK (0x07FF0000)
+
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_LSB (12)
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_WIDTH (3)
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_MASK (0x00007000)
+
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_LSB (9)
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_WIDTH (3)
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_MASK (0x00000E00)
+
+#define DBRP_VITW_DBG2_VDEC_CS_LSB (4)
+#define DBRP_VITW_DBG2_VDEC_CS_WIDTH (5)
+#define DBRP_VITW_DBG2_VDEC_CS_MASK (0x000001F0)
+
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_LSB (0)
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_WIDTH (4)
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_MASK (0x0000000F)
+
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_LSB (15)
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_WIDTH (7)
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_MASK (0x003F8000)
+
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_LSB (0)
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_WIDTH (15)
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_MASK (0x00007FFF)
+
+
+#endif //#ifndef _CPH_C2K_RX_BRP_DVIT_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_97.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_97.h
new file mode 100644
index 0000000..d8179bc
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrpdvit_97.h
@@ -0,0 +1,1872 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RX_BRP_DVIT_H_
+#define _CPH_C2K_RX_BRP_DVIT_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCT_DVIT_REG_BASE (0xAC870000)
+
+#define RXBRP_WCT_DVIT_end (RXBRP_WCT_DVIT_REG_BASE + 0x4038 + 1*4)
+
+
+
+#define DBRP_VITW_WT_CTRL ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0000))
+#define DBRP_VITW_WT_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0004))
+#define DBRP_VITW_WT_DONE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0008))
+#define DBRP_VITW_WT_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x000c))
+#define DBRP_VITW_WT_DONE_VEC ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0010))
+#define DBRP_VITW_WT_CHEN ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0018))
+#define DBRP_VITW_WT_BCH_DMACFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0100))
+#define DBRP_VITW_WT_BCH_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0104))
+#define DBRP_VITW_WT_BCH_SFN ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0108))
+#define DBRP_VITW_WT_BCH_SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x010c))
+#define DBRP_VITW_WT_BCH_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0110))
+#define DBRP_VITW_WT_BCH_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x0114))
+#define DBRP_VITW_WT_TRCH0_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1000))
+#define DBRP_VITW_WT_TRCH0_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1004))
+#define DBRP_VITW_WT_TRCH0_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1008))
+#define DBRP_VITW_WT_TRCH0_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x100c))
+#define DBRP_VITW_WT_TRCH0_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1010))
+#define DBRP_VITW_WT_TRCH0_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1014))
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1018))
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x101c))
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1020))
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1024))
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1028))
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x102C))
+#define DBRP_VITW_WT_TRCH0_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1030))
+#define DBRP_VITW_WT_TRCH0_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1034))
+#define DBRP_VITW_WT_TRCH1_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1100))
+#define DBRP_VITW_WT_TRCH1_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1104))
+#define DBRP_VITW_WT_TRCH1_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1108))
+#define DBRP_VITW_WT_TRCH1_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x110c))
+#define DBRP_VITW_WT_TRCH1_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1110))
+#define DBRP_VITW_WT_TRCH1_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1114))
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1118))
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x111c))
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1120))
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1124))
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1128))
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x112C))
+#define DBRP_VITW_WT_TRCH1_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1130))
+#define DBRP_VITW_WT_TRCH1_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1134))
+#define DBRP_VITW_WT_TRCH2_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1200))
+#define DBRP_VITW_WT_TRCH2_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1204))
+#define DBRP_VITW_WT_TRCH2_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1208))
+#define DBRP_VITW_WT_TRCH2_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x120c))
+#define DBRP_VITW_WT_TRCH2_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1210))
+#define DBRP_VITW_WT_TRCH2_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1214))
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1218))
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x121c))
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1220))
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1224))
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1228))
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x122C))
+#define DBRP_VITW_WT_TRCH2_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1230))
+#define DBRP_VITW_WT_TRCH2_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1234))
+#define DBRP_VITW_WT_TRCH3_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1300))
+#define DBRP_VITW_WT_TRCH3_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1304))
+#define DBRP_VITW_WT_TRCH3_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1308))
+#define DBRP_VITW_WT_TRCH3_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x130c))
+#define DBRP_VITW_WT_TRCH3_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1310))
+#define DBRP_VITW_WT_TRCH3_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1314))
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1318))
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x131c))
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1320))
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1324))
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1328))
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x132C))
+#define DBRP_VITW_WT_TRCH3_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1330))
+#define DBRP_VITW_WT_TRCH3_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1334))
+#define DBRP_VITW_WT_TRCH4_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1400))
+#define DBRP_VITW_WT_TRCH4_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1404))
+#define DBRP_VITW_WT_TRCH4_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1408))
+#define DBRP_VITW_WT_TRCH4_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x140c))
+#define DBRP_VITW_WT_TRCH4_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1410))
+#define DBRP_VITW_WT_TRCH4_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1414))
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1418))
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x141c))
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1420))
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1424))
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1428))
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x142C))
+#define DBRP_VITW_WT_TRCH4_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1430))
+#define DBRP_VITW_WT_TRCH4_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1434))
+#define DBRP_VITW_WT_TRCH5_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1500))
+#define DBRP_VITW_WT_TRCH5_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1504))
+#define DBRP_VITW_WT_TRCH5_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1508))
+#define DBRP_VITW_WT_TRCH5_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x150c))
+#define DBRP_VITW_WT_TRCH5_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1510))
+#define DBRP_VITW_WT_TRCH5_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1514))
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1518))
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x151c))
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1520))
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1524))
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1528))
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x152C))
+#define DBRP_VITW_WT_TRCH5_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1530))
+#define DBRP_VITW_WT_TRCH5_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1534))
+#define DBRP_VITW_WT_TRCH6_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1600))
+#define DBRP_VITW_WT_TRCH6_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1604))
+#define DBRP_VITW_WT_TRCH6_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1608))
+#define DBRP_VITW_WT_TRCH6_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x160c))
+#define DBRP_VITW_WT_TRCH6_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1610))
+#define DBRP_VITW_WT_TRCH6_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1614))
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1618))
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x161c))
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1620))
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1624))
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1628))
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x162C))
+#define DBRP_VITW_WT_TRCH6_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1630))
+#define DBRP_VITW_WT_TRCH6_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1634))
+#define DBRP_VITW_WT_TRCH7_TTI_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1700))
+#define DBRP_VITW_WT_TRCH7_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1704))
+#define DBRP_VITW_WT_TRCH7_TrBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1708))
+#define DBRP_VITW_WT_TRCH7_CoBK ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x170c))
+#define DBRP_VITW_WT_TRCH7_DST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1710))
+#define DBRP_VITW_WT_TRCH7_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1714))
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1718))
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x171c))
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1720))
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1724))
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1728))
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x172C))
+#define DBRP_VITW_WT_TRCH7_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1730))
+#define DBRP_VITW_WT_TRCH7_LST_ADDR ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x1734))
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2000))
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2004))
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2008))
+#define DBRP_VITW_WT_BTFD1_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2010))
+#define DBRP_VITW_WT_BTFD1_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2014))
+#define DBRP_VITW_WT_BTFD2_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2020))
+#define DBRP_VITW_WT_BTFD2_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2024))
+#define DBRP_VITW_WT_BTFD3_PARAM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2030))
+#define DBRP_VITW_WT_BTFD3_RESULT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2034))
+#define DBRP_VITW_WT_BTFD_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2080))
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2100))
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2104))
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2108))
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2200))
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2204))
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2208))
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2300))
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2304))
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2308))
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2400))
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2404))
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2408))
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2500))
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2504))
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2508))
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2600))
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2604))
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2608))
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2700))
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2704))
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2708))
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2800))
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2804))
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2808))
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2900))
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2904))
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2908))
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A00))
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A04))
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2A08))
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B00))
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B04))
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2B08))
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C00))
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C04))
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2C08))
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D00))
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D04))
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2D08))
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E00))
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E04))
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2E08))
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F00))
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F04))
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x2F08))
+#define DBRP_VITW_C_RESET ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3000))
+#define DBRP_VITW_C_LVA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3004))
+#define DBRP_VITW_C_PCH_CONF ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3008))
+#define DBRP_VITW_C_FIRST_FRM ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x300C))
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3010))
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3014))
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3018))
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x301C))
+#define DBRP_VITW_C_SCH_DMA_BASE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3020))
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3024))
+#define DBRP_VITW_C_SCH_DMA_CFG ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3028))
+#define DBRP_VITW_C_FCH_FULL_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x302C))
+#define DBRP_VITW_C_FCH_HALF_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3030))
+#define DBRP_VITW_C_FCH_QUAT_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3034))
+#define DBRP_VITW_C_FCH_EIGH_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3038))
+#define DBRP_VITW_C_SCH_S ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x303C))
+#define DBRP_VITW_C_FCH_FULL_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3040))
+#define DBRP_VITW_C_FCH_HALF_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3044))
+#define DBRP_VITW_C_FCH_QUAT_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3048))
+#define DBRP_VITW_C_FCH_EIGH_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x304C))
+#define DBRP_VITW_C_SCH_YAMA ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3050))
+#define DBRP_VITW_C_FCH_FULL_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3054))
+#define DBRP_VITW_C_FCH_HALF_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3058))
+#define DBRP_VITW_C_FCH_QUAT_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x305C))
+#define DBRP_VITW_C_FCH_EIGH_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3060))
+#define DBRP_VITW_C_SCH_E ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3064))
+#define DBRP_VITW_C_FCH_CRC_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3068))
+#define DBRP_VITW_C_SCH_CRC_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x306C))
+#define DBRP_VITW_C_STATUS ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3070))
+#define DBRP_VITW_C_DONE_VEC ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3074))
+#define DBRP_VITW_C_DONE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3078))
+#define DBRP_VITW_C_FCH_FULL_USAGE ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x307C))
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3080))
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3084))
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3088))
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x308C))
+#define DBRP_VITW_C_SCH_DMA_LAST ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x3090))
+#define DBRP_VITW_MPU ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4000))
+#define DBRP_VITW_MPU_VIO ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4004))
+#define DBRP_VITW_MPU0 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4008))
+#define DBRP_VITW_MPU0_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x400C))
+#define DBRP_VITW_MPU0_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4010))
+#define DBRP_VITW_MPU1 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4014))
+#define DBRP_VITW_MPU1_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4018))
+#define DBRP_VITW_MPU1_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x401C))
+#define DBRP_VITW_MPU2 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4020))
+#define DBRP_VITW_MPU2_START ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4024))
+#define DBRP_VITW_MPU2_END ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4028))
+#define DBRP_VITW_DBG0 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x402C))
+#define DBRP_VITW_DBG1 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4030))
+#define DBRP_VITW_DBG2 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4034))
+#define DBRP_VITW_DBG3 ((APBADDR32)(RXBRP_WCT_DVIT_REG_BASE + 0x4038))
+
+
+
+#define DBRP_VITW_WT_CTRL_IRQ_DISABLE_LSB (16)
+#define DBRP_VITW_WT_CTRL_IRQ_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_IRQ_DISABLE_MASK (0x00010000)
+#define DBRP_VITW_WT_CTRL_IRQ_DISABLE_BIT (0x00010000)
+
+#define DBRP_VITW_WT_CTRL_PWR_MODE_LSB (5)
+#define DBRP_VITW_WT_CTRL_PWR_MODE_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_PWR_MODE_MASK (0x00000020)
+#define DBRP_VITW_WT_CTRL_PWR_MODE_BIT (0x00000020)
+#define DBRP_VITW_WT_CTRL_SW_RESET_LSB (4)
+#define DBRP_VITW_WT_CTRL_SW_RESET_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_SW_RESET_MASK (0x00000010)
+#define DBRP_VITW_WT_CTRL_SW_RESET_BIT (0x00000010)
+
+#define DBRP_VITW_WT_CTRL_Mode_LSB (0)
+#define DBRP_VITW_WT_CTRL_Mode_WIDTH (1)
+#define DBRP_VITW_WT_CTRL_Mode_MASK (0x00000001)
+#define DBRP_VITW_WT_CTRL_Mode_BIT (0x00000001)
+
+#define DBRP_VITW_WT_START_ACC_START_LSB (15)
+#define DBRP_VITW_WT_START_ACC_START_WIDTH (1)
+#define DBRP_VITW_WT_START_ACC_START_MASK (0x00008000)
+#define DBRP_VITW_WT_START_ACC_START_BIT (0x00008000)
+
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_LSB (0)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_MASK (0x00000001)
+#define DBRP_VITW_WT_DONE_VITW_DEC_DONE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_LSB (0)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_WIDTH (1)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_MASK (0x00000001)
+#define DBRP_VITW_WT_STATUS_VITW_BUSY_BIT (0x00000001)
+
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_LSB (8)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_MASK (0x00000100)
+#define DBRP_VITW_WT_DONE_VEC_BCH_DONE_VEC_BIT (0x00000100)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_LSB (7)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_MASK (0x00000080)
+#define DBRP_VITW_WT_DONE_VEC_TRCH7_DONE_VEC_BIT (0x00000080)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_LSB (6)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_MASK (0x00000040)
+#define DBRP_VITW_WT_DONE_VEC_TRCH6_DONE_VEC_BIT (0x00000040)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_LSB (5)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_MASK (0x00000020)
+#define DBRP_VITW_WT_DONE_VEC_TRCH5_DONE_VEC_BIT (0x00000020)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_LSB (4)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_MASK (0x00000010)
+#define DBRP_VITW_WT_DONE_VEC_TRCH4_DONE_VEC_BIT (0x00000010)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_LSB (3)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_MASK (0x00000008)
+#define DBRP_VITW_WT_DONE_VEC_TRCH3_DONE_VEC_BIT (0x00000008)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_LSB (2)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_MASK (0x00000004)
+#define DBRP_VITW_WT_DONE_VEC_TRCH2_DONE_VEC_BIT (0x00000004)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_LSB (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_MASK (0x00000002)
+#define DBRP_VITW_WT_DONE_VEC_TRCH1_DONE_VEC_BIT (0x00000002)
+
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_LSB (0)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_MASK (0x00000001)
+#define DBRP_VITW_WT_DONE_VEC_TRCH0_DONE_VEC_BIT (0x00000001)
+
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_LSB (15)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_WIDTH (1)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_MASK (0x00008000)
+#define DBRP_VITW_WT_CHEN_BTFD_MODE_BIT (0x00008000)
+
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_LSB (8)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_WIDTH (1)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_MASK (0x00000100)
+#define DBRP_VITW_WT_CHEN_BCH_VIT_EN_BIT (0x00000100)
+
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_LSB (0)
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_WIDTH (8)
+#define DBRP_VITW_WT_CHEN_TRCH_VIT_EN_MASK (0x000000FF)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_LSB (8)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_MASK (0x00000100)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_DMA_ENAB_BIT (0x00000100)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_BCH_DMACFG_BCH_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_BCH_DST_ADDR_BCH_DMA_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_LSB (14)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_WIDTH (1)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_MASK (0x00004000)
+#define DBRP_VITW_WT_BCH_SFN_BCH_CRC_BIT (0x00004000)
+
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_LSB (0)
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_WIDTH (11)
+#define DBRP_VITW_WT_BCH_SFN_BCH_SFN_MASK (0x000007FF)
+
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_LSB (0)
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_WIDTH (21)
+#define DBRP_VITW_WT_BCH_SVALUE_BCH_SVALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_BCH_ENERGY_BCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_BCH_LST_ADDR_BCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH0_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH0_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH0_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH0_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH0_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH0_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH0_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH0_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH1_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH1_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH1_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH1_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH1_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH1_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH1_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH1_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH2_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH2_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH2_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH2_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH2_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH2_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH2_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH2_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH3_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH3_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH3_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH3_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH3_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH3_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH3_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH3_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH4_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH4_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH4_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH4_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH4_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH4_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH4_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH4_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH5_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH5_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH5_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH5_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH5_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH5_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH5_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH5_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH6_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH6_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH6_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH6_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH6_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH6_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH6_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH6_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_WIDTH (13)
+#define DBRP_VITW_WT_TRCH7_TTI_BASE_TTI_BASE_MASK (0x00001FFF)
+
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_LSB (1)
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_WIDTH (3)
+#define DBRP_VITW_WT_TRCH7_CFG_CRC_FORMAT_MASK (0x0000000E)
+
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_MASK (0x00000001)
+#define DBRP_VITW_WT_TRCH7_CFG_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_WIDTH (11)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBSIZE_MASK (0x07FF0000)
+
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_TRCH7_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_LSB (16)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBSIZE_MASK (0x03FF0000)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_LSB (4)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_WIDTH (2)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBPAD_MASK (0x00000030)
+
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_WIDTH (3)
+#define DBRP_VITW_WT_TRCH7_CoBK_CBNUM_MASK (0x00000007)
+
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_DST_ADDR_DST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_LSB (8)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_MASK (0x00000100)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_DMA_DISABLE_BIT (0x00000100)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_WT_TRCH7_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_LSB (0)
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_TBCRC_STA_TBCRC_STATUS_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB0SVALUE_CB0_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB1SVALUE_CB1_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB2SVALUE_CB2_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB3SVALUE_CB3_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_LSB (0)
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_CB4SVALUE_CB4_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_LSB (0)
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_WIDTH (21)
+#define DBRP_VITW_WT_TRCH7_ENERGY_TRCH_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_LSB (0)
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_WIDTH (32)
+#define DBRP_VITW_WT_TRCH7_LST_ADDR_TRCH_LSTADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF0_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF0_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF0_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD1_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD1_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD2_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD2_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_LSB (12)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_WIDTH (1)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_MASK (0x00001000)
+#define DBRP_VITW_WT_BTFD3_PARAM_EXPLICIT_IND_BIT (0x00001000)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_LSB (8)
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_TRCH_ID_MASK (0x00000F00)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_LSB (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_LAST_STOP_POINT_IDX_MASK (0x000000F0)
+
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_PARAM_FIRST_STOP_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_LSB (15)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_WIDTH (1)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_MASK (0x00008000)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_PASS_BIT (0x00008000)
+
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_LSB (0)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_WIDTH (4)
+#define DBRP_VITW_WT_BTFD3_RESULT_BTFD_POINT_IDX_MASK (0x0000000F)
+
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_LSB (0)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_MASK (0x00000001)
+#define DBRP_VITW_WT_BTFD_CFG_BTFD_DST_CALC_SET_BIT (0x00000001)
+
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF1_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF1_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF1_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF2_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF2_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF2_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF3_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF3_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF3_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF4_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF4_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF4_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF5_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF5_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF5_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF6_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF6_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF6_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF7_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF7_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF7_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF8_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF8_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF8_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF9_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF9_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF9_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF10_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF10_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF10_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF11_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF11_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF11_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF12_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF12_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF12_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF13_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF13_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF13_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF14_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF14_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF14_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_WIDTH (1)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_MASK (0x00000400)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_MULTI_BIT (0x00000400)
+
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF15_STOP_POINT_STOP_POINT_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_LSB (10)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_WIDTH (6)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBNUM_MASK (0x0000FC00)
+
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_WIDTH (10)
+#define DBRP_VITW_WT_BTFD_TF15_CRC_POINT_CRC_POINT_TBSIZE_MASK (0x000003FF)
+
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_LSB (0)
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_WIDTH (15)
+#define DBRP_VITW_WT_BTFD_TF15_ENERGY_EBD_TFN_ENERGY_MASK (0x00007FFF)
+
+#define DBRP_VITW_C_RESET_SW_RESET_LSB (0)
+#define DBRP_VITW_C_RESET_SW_RESET_WIDTH (1)
+#define DBRP_VITW_C_RESET_SW_RESET_MASK (0x00000001)
+#define DBRP_VITW_C_RESET_SW_RESET_BIT (0x00000001)
+
+#define DBRP_VITW_C_LVA_LVA_EN_LSB (0)
+#define DBRP_VITW_C_LVA_LVA_EN_WIDTH (1)
+#define DBRP_VITW_C_LVA_LVA_EN_MASK (0x00000001)
+#define DBRP_VITW_C_LVA_LVA_EN_BIT (0x00000001)
+
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_LSB (0)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_WIDTH (1)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_MASK (0x00000001)
+#define DBRP_VITW_C_PCH_CONF_ENHANCE_BIT (0x00000001)
+
+#define DBRP_VITW_C_FIRST_FRM_START_LSB (0)
+#define DBRP_VITW_C_FIRST_FRM_START_WIDTH (1)
+#define DBRP_VITW_C_FIRST_FRM_START_MASK (0x00000001)
+#define DBRP_VITW_C_FIRST_FRM_START_BIT (0x00000001)
+
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_FULL_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_HALF_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_QUAT_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_EIGH_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_WIDTH (32)
+#define DBRP_VITW_C_SCH_DMA_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_LSB (7)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_MASK (0x00000080)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_DMA_DISABLE_BIT (0x00000080)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_LSB (6)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_MASK (0x00000040)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_CRC_REMOVE_BIT (0x00000040)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_C_FCH_FULL_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_LSB (7)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_MASK (0x00000080)
+#define DBRP_VITW_C_SCH_DMA_CFG_DMA_DISABLE_BIT (0x00000080)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_LSB (6)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_MASK (0x00000040)
+#define DBRP_VITW_C_SCH_DMA_CFG_CRC_REMOVE_BIT (0x00000040)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_VITW_C_SCH_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_WIDTH (5)
+#define DBRP_VITW_C_SCH_DMA_CFG_BIT_OFFSET_MASK (0x0000001F)
+
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_FULL_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_HALF_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_QUAT_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_FCH_EIGH_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_SCH_S_S_VALUE_LSB (0)
+#define DBRP_VITW_C_SCH_S_S_VALUE_WIDTH (21)
+#define DBRP_VITW_C_SCH_S_S_VALUE_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_FULL_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_HALF_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_QUAT_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_FCH_EIGH_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_LSB (0)
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_WIDTH (10)
+#define DBRP_VITW_C_SCH_YAMA_YAMAMOTO_MASK (0x000003FF)
+
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_FULL_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_HALF_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_QUAT_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_FCH_EIGH_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_SCH_E_ENERGY_LSB (0)
+#define DBRP_VITW_C_SCH_E_ENERGY_WIDTH (21)
+#define DBRP_VITW_C_SCH_E_ENERGY_MASK (0x001FFFFF)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_LSB (3)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_MASK (0x00000008)
+#define DBRP_VITW_C_FCH_CRC_STATUS_EIGH_RATE_BIT (0x00000008)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_LSB (2)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_MASK (0x00000004)
+#define DBRP_VITW_C_FCH_CRC_STATUS_QUAT_RATE_BIT (0x00000004)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_LSB (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_MASK (0x00000002)
+#define DBRP_VITW_C_FCH_CRC_STATUS_HALF_RATE_BIT (0x00000002)
+
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_LSB (0)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_WIDTH (1)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_MASK (0x00000001)
+#define DBRP_VITW_C_FCH_CRC_STATUS_FULL_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_LSB (0)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_WIDTH (1)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_MASK (0x00000001)
+#define DBRP_VITW_C_SCH_CRC_STATUS_FULL_RATE_BIT (0x00000001)
+
+#define DBRP_VITW_C_STATUS_VITW_BUSY_LSB (0)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_WIDTH (1)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_MASK (0x00000001)
+#define DBRP_VITW_C_STATUS_VITW_BUSY_BIT (0x00000001)
+
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_LSB (3)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_MASK (0x00000008)
+#define DBRP_VITW_C_DONE_VEC_SCH_DONE_VEC_BIT (0x00000008)
+
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_LSB (2)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_MASK (0x00000004)
+#define DBRP_VITW_C_DONE_VEC_FCH_DONE_VEC_BIT (0x00000004)
+
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_LSB (1)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_MASK (0x00000002)
+#define DBRP_VITW_C_DONE_VEC_PCH_DONE_VEC_BIT (0x00000002)
+
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_LSB (0)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_WIDTH (1)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_MASK (0x00000001)
+#define DBRP_VITW_C_DONE_VEC_SYN_DONE_VEC_BIT (0x00000001)
+
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_LSB (0)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_WIDTH (1)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_MASK (0x00000001)
+#define DBRP_VITW_C_DONE_VITW_DEC_DONE_BIT (0x00000001)
+
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_LSB (0)
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_WIDTH (2)
+#define DBRP_VITW_C_FCH_FULL_USAGE_CFG_IDX_MASK (0x00000003)
+
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_FULL_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_HALF_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_QUAT_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_FCH_DMA_EIGH_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_LSB (0)
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_WIDTH (32)
+#define DBRP_VITW_C_SCH_DMA_LAST_ADDR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU_VIOLATE_LSB (0)
+#define DBRP_VITW_MPU_VIOLATE_WIDTH (1)
+#define DBRP_VITW_MPU_VIOLATE_MASK (0x00000001)
+#define DBRP_VITW_MPU_VIOLATE_BIT (0x00000001)
+
+#define DBRP_VITW_MPU_VIO_ADR_LSB (0)
+#define DBRP_VITW_MPU_VIO_ADR_WIDTH (32)
+#define DBRP_VITW_MPU_VIO_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU0_EN_LSB (0)
+#define DBRP_VITW_MPU0_EN_WIDTH (1)
+#define DBRP_VITW_MPU0_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU0_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU0_START_ADR_LSB (0)
+#define DBRP_VITW_MPU0_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU0_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU0_END_ADR_LSB (0)
+#define DBRP_VITW_MPU0_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU0_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU1_EN_LSB (0)
+#define DBRP_VITW_MPU1_EN_WIDTH (1)
+#define DBRP_VITW_MPU1_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU1_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU1_START_ADR_LSB (0)
+#define DBRP_VITW_MPU1_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU1_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU1_END_ADR_LSB (0)
+#define DBRP_VITW_MPU1_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU1_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU2_EN_LSB (0)
+#define DBRP_VITW_MPU2_EN_WIDTH (1)
+#define DBRP_VITW_MPU2_EN_MASK (0x00000001)
+#define DBRP_VITW_MPU2_EN_BIT (0x00000001)
+
+#define DBRP_VITW_MPU2_START_ADR_LSB (0)
+#define DBRP_VITW_MPU2_START_ADR_WIDTH (32)
+#define DBRP_VITW_MPU2_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_MPU2_END_ADR_LSB (0)
+#define DBRP_VITW_MPU2_END_ADR_WIDTH (32)
+#define DBRP_VITW_MPU2_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_VITW_DBG0_VITW_BCH_CS_LSB (25)
+#define DBRP_VITW_DBG0_VITW_BCH_CS_WIDTH (4)
+#define DBRP_VITW_DBG0_VITW_BCH_CS_MASK (0x1E000000)
+
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_LSB (17)
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_WIDTH (8)
+#define DBRP_VITW_DBG0_VITW_TRCHI_CS_MASK (0x01FE0000)
+
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_LSB (10)
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_WIDTH (7)
+#define DBRP_VITW_DBG0_VITW_BTFD_CS_MASK (0x0001FC00)
+
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_LSB (0)
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_WIDTH (10)
+#define DBRP_VITW_DBG0_VITW_CTRL_CS_MASK (0x000003FF)
+
+#define DBRP_VITW_DBG1_VITW_SCH_CS_LSB (7)
+#define DBRP_VITW_DBG1_VITW_SCH_CS_WIDTH (5)
+#define DBRP_VITW_DBG1_VITW_SCH_CS_MASK (0x00000F80)
+
+#define DBRP_VITW_DBG1_VITW_FCH_CS_LSB (0)
+#define DBRP_VITW_DBG1_VITW_FCH_CS_WIDTH (7)
+#define DBRP_VITW_DBG1_VITW_FCH_CS_MASK (0x0000007F)
+
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_LSB (28)
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_WIDTH (4)
+#define DBRP_VITW_DBG2_BTFD_TF_IDX_MASK (0xF0000000)
+
+#define DBRP_VITW_DBG2_VINFO_CS_LSB (16)
+#define DBRP_VITW_DBG2_VINFO_CS_WIDTH (11)
+#define DBRP_VITW_DBG2_VINFO_CS_MASK (0x07FF0000)
+
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_LSB (12)
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_WIDTH (3)
+#define DBRP_VITW_DBG2_CUR_BTFD_TRCH_ID_MASK (0x00007000)
+
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_LSB (9)
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_WIDTH (3)
+#define DBRP_VITW_DBG2_CUR_TRCHI_ID_MASK (0x00000E00)
+
+#define DBRP_VITW_DBG2_VDEC_CS_LSB (4)
+#define DBRP_VITW_DBG2_VDEC_CS_WIDTH (5)
+#define DBRP_VITW_DBG2_VDEC_CS_MASK (0x000001F0)
+
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_LSB (0)
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_WIDTH (4)
+#define DBRP_VITW_DBG2_VDEC_INTF_CS_MASK (0x0000000F)
+
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_LSB (15)
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_WIDTH (7)
+#define DBRP_VITW_DBG3_VDOB_TRBK_STATE_MASK (0x003F8000)
+
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_LSB (0)
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_WIDTH (15)
+#define DBRP_VITW_DBG3_VDEC_FLOW_CS_MASK (0x00007FFF)
+
+
+#endif //#ifndef _CPH_C2K_RX_BRP_DVIT_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur.h
new file mode 100644
index 0000000..76a6c4e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphc2krxbrptur_93.h"
+#elif defined(__MD95__)
+#include "cphc2krxbrptur_93.h"
+#elif defined(__MD97__)
+#include "cphc2krxbrptur_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_93.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_93.h
new file mode 100644
index 0000000..7bb2a54
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_93.h
@@ -0,0 +1,2509 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RX_BRP_TUR_H_
+#define _CPH_C2K_RX_BRP_TUR_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCTL_TUR_REG_BASE (0xad120000)
+
+#define RXBRP_WCTL_TUR_end (RXBRP_WCTL_TUR_REG_BASE + 0xD0A0 + 1*4)
+
+
+
+#define DBRP_TUR_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0000))
+#define DBRP_TUR_DSCRM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0004))
+#define DBRP_TUR_C_DBG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0008))
+#define DBRP_TUR_DSCH_TRG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2000))
+#define DBRP_TUR_DSCH_DONE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2004))
+#define DBRP_TUR_DSCH_EN ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2008))
+#define DBRP_TUR_DSCH_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x200C))
+#define DBRP_TUR_DSCH_CBBUF ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2010))
+#define DBRP_TUR_DSCH_CH0_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2014))
+#define DBRP_TUR_DSCH_CH0_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2018))
+#define DBRP_TUR_DSCH_CH0_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x201C))
+#define DBRP_TUR_DSCH_CH0_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2020))
+#define DBRP_TUR_DSCH_CH0_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2024))
+#define DBRP_TUR_DSCH_CH0_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2028))
+#define DBRP_TUR_DSCH_CH0_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x202C))
+#define DBRP_TUR_DSCH_CH0_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2030))
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2034))
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2038))
+#define DBRP_TUR_DSCH_CH1_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x203C))
+#define DBRP_TUR_DSCH_CH1_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2040))
+#define DBRP_TUR_DSCH_CH1_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2044))
+#define DBRP_TUR_DSCH_CH1_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2048))
+#define DBRP_TUR_DSCH_CH1_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x204C))
+#define DBRP_TUR_DSCH_CH1_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2050))
+#define DBRP_TUR_DSCH_CH1_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2054))
+#define DBRP_TUR_DSCH_CH1_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2058))
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x205C))
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2060))
+#define DBRP_TUR_DSCH_CH2_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2064))
+#define DBRP_TUR_DSCH_CH2_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2068))
+#define DBRP_TUR_DSCH_CH2_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x206C))
+#define DBRP_TUR_DSCH_CH2_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2070))
+#define DBRP_TUR_DSCH_CH2_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2074))
+#define DBRP_TUR_DSCH_CH2_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2078))
+#define DBRP_TUR_DSCH_CH2_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x207C))
+#define DBRP_TUR_DSCH_CH2_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2080))
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2084))
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2088))
+#define DBRP_TUR_DSCH_CH3_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x208C))
+#define DBRP_TUR_DSCH_CH3_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2090))
+#define DBRP_TUR_DSCH_CH3_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2094))
+#define DBRP_TUR_DSCH_CH3_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2098))
+#define DBRP_TUR_DSCH_CH3_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x209C))
+#define DBRP_TUR_DSCH_CH3_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A0))
+#define DBRP_TUR_DSCH_CH3_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A4))
+#define DBRP_TUR_DSCH_CH3_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A8))
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20AC))
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B0))
+#define DBRP_TUR_DSCH_CH4_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B4))
+#define DBRP_TUR_DSCH_CH4_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B8))
+#define DBRP_TUR_DSCH_CH4_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20BC))
+#define DBRP_TUR_DSCH_CH4_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C0))
+#define DBRP_TUR_DSCH_CH4_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C4))
+#define DBRP_TUR_DSCH_CH4_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C8))
+#define DBRP_TUR_DSCH_CH4_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20CC))
+#define DBRP_TUR_DSCH_CH4_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D0))
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D4))
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D8))
+#define DBRP_TUR_DSCH_CH0_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20DC))
+#define DBRP_TUR_DSCH_CH0_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E0))
+#define DBRP_TUR_DSCH_CH0_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E4))
+#define DBRP_TUR_DSCH_CH0_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E8))
+#define DBRP_TUR_DSCH_CH0_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20EC))
+#define DBRP_TUR_DSCH_CH0_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F0))
+#define DBRP_TUR_DSCH_CH0_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F4))
+#define DBRP_TUR_DSCH_CH0_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F8))
+#define DBRP_TUR_DSCH_CH1_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20FC))
+#define DBRP_TUR_DSCH_CH1_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2100))
+#define DBRP_TUR_DSCH_CH1_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2104))
+#define DBRP_TUR_DSCH_CH1_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2108))
+#define DBRP_TUR_DSCH_CH1_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x210C))
+#define DBRP_TUR_DSCH_CH1_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2110))
+#define DBRP_TUR_DSCH_CH1_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2114))
+#define DBRP_TUR_DSCH_CH1_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2118))
+#define DBRP_TUR_DSCH_CH2_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x211C))
+#define DBRP_TUR_DSCH_CH2_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2120))
+#define DBRP_TUR_DSCH_CH2_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2124))
+#define DBRP_TUR_DSCH_CH2_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2128))
+#define DBRP_TUR_DSCH_CH2_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x212C))
+#define DBRP_TUR_DSCH_CH2_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2130))
+#define DBRP_TUR_DSCH_CH2_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2134))
+#define DBRP_TUR_DSCH_CH3_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2138))
+#define DBRP_TUR_DSCH_CH3_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x213C))
+#define DBRP_TUR_DSCH_CH3_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2140))
+#define DBRP_TUR_DSCH_CH3_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2144))
+#define DBRP_TUR_DSCH_CH3_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2148))
+#define DBRP_TUR_DSCH_CH3_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x214C))
+#define DBRP_TUR_DSCH_CH3_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2150))
+#define DBRP_TUR_DSCH_CH4_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2154))
+#define DBRP_TUR_DSCH_CH4_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2158))
+#define DBRP_TUR_DSCH_CH4_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x215C))
+#define DBRP_TUR_DSCH_CH4_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2160))
+#define DBRP_TUR_DSCH_CH4_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2164))
+#define DBRP_TUR_DSCH_CH4_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2168))
+#define DBRP_TUR_DSCH_CH4_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x216C))
+#define DBRP_TUR_BUSY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2170))
+#define DBRP_TUR_LTE_TRG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3000))
+#define DBRP_TUR_LTE_DONE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3004))
+#define DBRP_TUR_LTE_LATCH ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3008))
+#define DBRP_TUR_LTE_FRM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x300C))
+#define DBRP_TUR_LTE_SI_PI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3010))
+#define DBRP_TUR_LTE_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3014))
+#define DBRP_TUR_LTE_CH0_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3018))
+#define DBRP_TUR_LTE_CH0_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x301C))
+#define DBRP_TUR_LTE_CH0_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3020))
+#define DBRP_TUR_LTE_CH0_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3024))
+#define DBRP_TUR_LTE_CH0_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3028))
+#define DBRP_TUR_LTE_CH0_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x302C))
+#define DBRP_TUR_LTE_CH1_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3030))
+#define DBRP_TUR_LTE_CH1_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3034))
+#define DBRP_TUR_LTE_CH1_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3038))
+#define DBRP_TUR_LTE_CH1_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x303C))
+#define DBRP_TUR_LTE_CH1_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3040))
+#define DBRP_TUR_LTE_CH1_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3044))
+#define DBRP_TUR_LTE_CH2_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3048))
+#define DBRP_TUR_LTE_CH2_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x304C))
+#define DBRP_TUR_LTE_CH2_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3050))
+#define DBRP_TUR_LTE_CH2_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3054))
+#define DBRP_TUR_LTE_CH2_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3058))
+#define DBRP_TUR_LTE_CH2_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x305C))
+#define DBRP_TUR_LTE_CH3_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3060))
+#define DBRP_TUR_LTE_CH3_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3064))
+#define DBRP_TUR_LTE_CH3_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3068))
+#define DBRP_TUR_LTE_CH3_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x306C))
+#define DBRP_TUR_LTE_CH3_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3070))
+#define DBRP_TUR_LTE_CH3_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3074))
+#define DBRP_TUR_LTE_CH4_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3078))
+#define DBRP_TUR_LTE_CH4_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x307C))
+#define DBRP_TUR_LTE_CH4_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3080))
+#define DBRP_TUR_LTE_CH4_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3084))
+#define DBRP_TUR_LTE_CH4_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3088))
+#define DBRP_TUR_LTE_CH4_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x308C))
+#define DBRP_TUR_LTE_CC0_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3090))
+#define DBRP_TUR_LTE_CC0_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3094))
+#define DBRP_TUR_LTE_CC0_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3098))
+#define DBRP_TUR_LTE_CC0_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x309C))
+#define DBRP_TUR_LTE_CC0_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A0))
+#define DBRP_TUR_LTE_CC0_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A4))
+#define DBRP_TUR_LTE_CC0_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A8))
+#define DBRP_TUR_LTE_CC0_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30AC))
+#define DBRP_TUR_LTE_CC0_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B0))
+#define DBRP_TUR_LTE_CC0_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B4))
+#define DBRP_TUR_LTE_CC1_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B8))
+#define DBRP_TUR_LTE_CC1_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30BC))
+#define DBRP_TUR_LTE_CC1_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C0))
+#define DBRP_TUR_LTE_CC1_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C4))
+#define DBRP_TUR_LTE_CC1_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C8))
+#define DBRP_TUR_LTE_CC1_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30CC))
+#define DBRP_TUR_LTE_CC1_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D0))
+#define DBRP_TUR_LTE_CC1_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D4))
+#define DBRP_TUR_LTE_CC1_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D8))
+#define DBRP_TUR_LTE_CC1_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30DC))
+#define DBRP_TUR_LTE_CC2_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E0))
+#define DBRP_TUR_LTE_CC2_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E4))
+#define DBRP_TUR_LTE_CC2_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E8))
+#define DBRP_TUR_LTE_CC2_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30EC))
+#define DBRP_TUR_LTE_CC2_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F0))
+#define DBRP_TUR_LTE_CC2_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F4))
+#define DBRP_TUR_LTE_CC2_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F8))
+#define DBRP_TUR_LTE_CC2_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30FC))
+#define DBRP_TUR_LTE_CC2_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3100))
+#define DBRP_TUR_LTE_CC2_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3104))
+#define DBRP_TUR_LTE_DONE_CC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3108))
+#define DBRP_TUR_LTE_CMD0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x310C))
+#define DBRP_TUR_LTE_CMD1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3110))
+#define DBRP_TUR_LTE_CC0_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3114))
+#define DBRP_TUR_LTE_CC0_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3118))
+#define DBRP_TUR_LTE_CC1_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x311C))
+#define DBRP_TUR_LTE_CC1_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3120))
+#define DBRP_TUR_LTE_CC2_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3124))
+#define DBRP_TUR_LTE_CC2_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3128))
+#define DBRP_TUR_LTE_DONE_ASSERT ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x312C))
+#define DBRP_TUR_LTE_FW_RST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3FFC))
+#define DBRP_TUR_RSRV_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x400C))
+#define DBRP_TUR_RSRV_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4010))
+#define DBRP_TUR_RSRV_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4014))
+#define DBRP_TUR_DSCH_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4018))
+#define DBRP_TUR_DSCH_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x401C))
+#define DBRP_TUR_DSCH_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4020))
+#define DBRP_TUR_LTE_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4024))
+#define DBRP_TUR_LTE_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4028))
+#define DBRP_TUR_LTE_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x402C))
+#define DBRP_TUR_MPU_VIO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4030))
+#define DBRP_TUR_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4034))
+#define DBRP_TUR_LTE_MPIF_DATA_CNT ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5000))
+#define DBRP_TUR_LTE_MPIF_DBG_0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5004))
+#define DBRP_TUR_LTE_MPIF_DBG_1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5008))
+#define DBRP_TUR_LTE_MPIF_DBG_2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x500C))
+#define DBRP_TUR_LTE_MPIF_DBG_3 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5010))
+#define DBRP_TUR_LTE_MPIF_DBG_4 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5014))
+#define DBRP_TUR_LTE_MPIF_DBG_5 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5018))
+#define DBRP_TUR_LTE_MPIF_DBG_6 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x501C))
+#define DBRP_TUR_LTE_MPIF_DBG_7 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5020))
+#define DBRP_TUR_LTE_MPIF_DBG_8 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5024))
+#define DBRP_TUR_LTE_MPIF_DBG_9 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5028))
+#define DBRP_TUR_LTE_MPIF_DBG_10 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x502C))
+#define DBRP_TUR_LTE_MPIF_DBG_11 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5030))
+#define DBRP_TUR_LTE_MPIF_DBG_12 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5034))
+#define DBRP_TUR_LTE_MPIF_DBG_13 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5038))
+#define DBRP_TUR_LTE_MPIF_DBG_14 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x503C))
+#define DBRP_TUR_LTE_MPIF_DBG_15 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5040))
+#define DBRP_TUR_LTE_MPIF_DBG_16 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5044))
+#define DBRP_TUR_LTE_MPIF_DBG_17 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5048))
+#define DBRP_TUR_LTE_MPIF_DBG_18 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x504C))
+#define DBRP_TUR_LTE_MPIF_DBG_19 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5050))
+#define DBRP_TUR_LTE_MPIF_DBG_20 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5054))
+#define DBRP_TUR_LTE_MPIF_DBG_21 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5058))
+#define DBRP_TUR_LTE_MPIF_DBG_22 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x505C))
+#define DBRP_TUR_LTE_MPIF_DBG_23 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5060))
+#define DBRP_TUR_LTE_MPIF_DBG_24 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5064))
+#define DBRP_TUR_LTE_MPIF_DBG_25 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5068))
+#define DBRP_TUR_LTE_MPIF_DBG_26 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x506C))
+#define DBRP_TUR_LTE_MPIF_DBG_27 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5070))
+#define DBRP_TUR_LTE_MPIF_DBG_28 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5074))
+#define DBRP_TUR_LTE_MPIF_DBG_29 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5078))
+#define DBRP_TUR_LTE_MPIF_DBG_30 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x507C))
+#define DBRP_TUR_LTE_MPIF_DBG_31 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5080))
+#define DBRP_TUR_LTE_MPIF_WRITE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5084))
+#define DBRP_TUR_L_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5088))
+#define DBRP_TUR_WT_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x508C))
+#define DBRP_TUR_DEC_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5090))
+#define DBRP_TUR_DOB_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5094))
+#define DBRP_TUR_C_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5098))
+#define DBRP_TUR_MODE_DBG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x509C))
+#define DBRP_TUR_RTT_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6000))
+#define DBRP_TUR_RTT_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6004))
+#define DBRP_TUR_RTT_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6008))
+#define DBRP_TUR_RTT_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x600C))
+#define DBRP_TUR_RTT_CBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6010))
+#define DBRP_TUR_RTT_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6014))
+#define DBRP_TUR_RTT_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6018))
+#define DBRP_TUR_EVDO_ITER_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7000))
+#define DBRP_TUR_EVDO_DST_PING ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7004))
+#define DBRP_TUR_EVDO_DST_PONG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7008))
+#define DBRP_TUR_EVDO_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x700C))
+#define DBRP_TUR_EVDO_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7010))
+#define DBRP_TUR_EVDO_CBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7014))
+#define DBRP_TUR_EVDO_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7018))
+#define DBRP_TUR_EVDO_HARQ ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x701C))
+#define DBRP_TUR_EVDO_PACKET ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7020))
+#define DBRP_TUR_EVDO_DST_ADR ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7024))
+#define DBRP_TUR_EVDO_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7028))
+#define DBRP_TUR_C2K_BUSY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x702C))
+#define DBRP_TUR_CB_NUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD000))
+#define DBRP_TUR_CH0_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD018))
+#define DBRP_TUR_CH0_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD028))
+#define DBRP_TUR_CH0_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD030))
+#define DBRP_TUR_CH1_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD034))
+#define DBRP_TUR_CH1_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD044))
+#define DBRP_TUR_CH1_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD04C))
+#define DBRP_TUR_CH2_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD050))
+#define DBRP_TUR_CH2_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD060))
+#define DBRP_TUR_CH2_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD068))
+#define DBRP_TUR_CH3_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD06C))
+#define DBRP_TUR_CH3_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD07C))
+#define DBRP_TUR_CH3_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD084))
+#define DBRP_TUR_CH4_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD088))
+#define DBRP_TUR_CH4_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD098))
+#define DBRP_TUR_CH4_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD0A0))
+
+
+#define DBRP_TUR_CFG_CR_TH_OFST_LSB (0)
+#define DBRP_TUR_CFG_CR_TH_OFST_WIDTH (13)
+#define DBRP_TUR_CFG_CR_TH_OFST_MASK (0x00001FFF)
+
+#define DBRP_TUR_DSCRM_BYPASS_LSB (0)
+#define DBRP_TUR_DSCRM_BYPASS_WIDTH (1)
+#define DBRP_TUR_DSCRM_BYPASS_MASK (0x00000001)
+#define DBRP_TUR_DSCRM_BYPASS_BIT (0x00000001)
+
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_LSB (4)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_WIDTH (1)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_MASK (0x00000010)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_BIT (0x00000010)
+
+#define DBRP_TUR_C_DBG_EMI_EN_LSB (0)
+#define DBRP_TUR_C_DBG_EMI_EN_WIDTH (1)
+#define DBRP_TUR_C_DBG_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_C_DBG_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_TRG_START_LSB (0)
+#define DBRP_TUR_DSCH_TRG_START_WIDTH (1)
+#define DBRP_TUR_DSCH_TRG_START_MASK (0x00000001)
+#define DBRP_TUR_DSCH_TRG_START_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_LSB (9)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_MASK (0x00000200)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_BIT (0x00000200)
+
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_LSB (8)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_MASK (0x00000100)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_BIT (0x00000100)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_LSB (6)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_MASK (0x00000040)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_BIT (0x00000040)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_LSB (4)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_MASK (0x00000010)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_LSB (3)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_MASK (0x00000008)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_LSB (2)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_MASK (0x00000004)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_BIT (0x00000004)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_LSB (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_MASK (0x00000002)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_BIT (0x00000002)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_LSB (0)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_MASK (0x00000001)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_LSB (6)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_MASK (0x00000040)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_BIT (0x00000040)
+
+#define DBRP_TUR_DSCH_EN_CHi_LSB (0)
+#define DBRP_TUR_DSCH_EN_CHi_WIDTH (5)
+#define DBRP_TUR_DSCH_EN_CHi_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_LSB (0)
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_WIDTH (5)
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_LSB (0)
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_WIDTH (12)
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_MASK (0x00000FFF)
+
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_BUSY_DSCH_LSB (1)
+#define DBRP_TUR_BUSY_DSCH_WIDTH (1)
+#define DBRP_TUR_BUSY_DSCH_MASK (0x00000002)
+#define DBRP_TUR_BUSY_DSCH_BIT (0x00000002)
+
+#define DBRP_TUR_LTE_TRG_START_LSB (0)
+#define DBRP_TUR_LTE_TRG_START_WIDTH (1)
+#define DBRP_TUR_LTE_TRG_START_MASK (0x00000001)
+#define DBRP_TUR_LTE_TRG_START_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_LSB (13)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_MASK (0x00002000)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_BIT (0x00002000)
+
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_LSB (12)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_MASK (0x00001000)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_BIT (0x00001000)
+
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_LSB (8)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_LSB (4)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_LSB (0)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_LATCH_STATUS_LSB (0)
+#define DBRP_TUR_LTE_LATCH_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_LATCH_STATUS_MASK (0x00000001)
+#define DBRP_TUR_LTE_LATCH_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_LSB (16)
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_WIDTH (10)
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_MASK (0x03FF0000)
+
+#define DBRP_TUR_LTE_FRM_SIM_IDX_LSB (4)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_WIDTH (1)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_MASK (0x00000010)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_LSB (0)
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_SI_PI_PI_TID_LSB (22)
+#define DBRP_TUR_LTE_SI_PI_PI_TID_WIDTH (10)
+#define DBRP_TUR_LTE_SI_PI_PI_TID_MASK (0xFFC00000)
+
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_LSB (16)
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_WIDTH (2)
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_MASK (0x00030000)
+
+#define DBRP_TUR_LTE_SI_PI_SI_TID_LSB (6)
+#define DBRP_TUR_LTE_SI_PI_SI_TID_WIDTH (10)
+#define DBRP_TUR_LTE_SI_PI_SI_TID_MASK (0x0000FFC0)
+
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_LSB (0)
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_WIDTH (6)
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_LSB (4)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_WIDTH (1)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_MASK (0x00000010)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_LSB (0)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_WIDTH (1)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_MASK (0x00000001)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH0_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH0_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH0_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH1_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH1_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH1_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH2_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH2_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH2_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH3_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH3_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH3_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH4_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH4_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH4_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_LSB (20)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_MASK (0x00100000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_LSB (19)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_MASK (0x00080000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_BIT (0x00080000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_LSB (18)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_MASK (0x00040000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_BIT (0x00040000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_LSB (17)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_MASK (0x00020000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_BIT (0x00020000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_LSB (16)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_MASK (0x00010000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_LSB (12)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_MASK (0x00001000)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_BIT (0x00001000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_LSB (11)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_MASK (0x00000800)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_BIT (0x00000800)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_LSB (10)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_MASK (0x00000400)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_BIT (0x00000400)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_LSB (9)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_MASK (0x00000200)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_BIT (0x00000200)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_LSB (8)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_LSB (4)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_LSB (3)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_MASK (0x00000008)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_BIT (0x00000008)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_LSB (2)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_MASK (0x00000004)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_BIT (0x00000004)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_LSB (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_MASK (0x00000002)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_BIT (0x00000002)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_LSB (0)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CMD0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CMD0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CMD0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CMD1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CMD1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CMD1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_LSB (8)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_LSB (4)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_LSB (0)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_FW_RST_FLAG_LSB (0)
+#define DBRP_TUR_LTE_FW_RST_FLAG_WIDTH (1)
+#define DBRP_TUR_LTE_FW_RST_FLAG_MASK (0x00000001)
+#define DBRP_TUR_LTE_FW_RST_FLAG_BIT (0x00000001)
+
+#define DBRP_TUR_RSRV_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_RSRV_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_RSRV_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RSRV_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_RSRV_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_RSRV_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RSRV_MPU_EN_LSB (0)
+#define DBRP_TUR_RSRV_MPU_EN_WIDTH (1)
+#define DBRP_TUR_RSRV_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_RSRV_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_DSCH_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_DSCH_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_MPU_EN_LSB (0)
+#define DBRP_TUR_DSCH_MPU_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_LTE_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_LTE_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPU_EN_LSB (0)
+#define DBRP_TUR_LTE_MPU_EN_WIDTH (1)
+#define DBRP_TUR_LTE_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_MPU_VIO_ADR_LSB (0)
+#define DBRP_TUR_MPU_VIO_ADR_WIDTH (32)
+#define DBRP_TUR_MPU_VIO_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_MPU_SW_IRQ_TRG_LSB (5)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_MASK (0x00000020)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_BIT (0x00000020)
+
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_LSB (4)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_MASK (0x00000010)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_BIT (0x00000010)
+
+#define DBRP_TUR_MPU_VIOLATE_LSB (0)
+#define DBRP_TUR_MPU_VIOLATE_WIDTH (1)
+#define DBRP_TUR_MPU_VIOLATE_MASK (0x00000001)
+#define DBRP_TUR_MPU_VIOLATE_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_WIDTH (1)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_MASK (0x00000001)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_LSB (0)
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_WIDTH (6)
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_MASK (0x0000003F)
+
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_LSB (16)
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_WIDTH (7)
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_MASK (0x007F0000)
+
+#define DBRP_TUR_L_FSM_STATE_LSB (0)
+#define DBRP_TUR_L_FSM_STATE_WIDTH (9)
+#define DBRP_TUR_L_FSM_STATE_MASK (0x000001FF)
+
+#define DBRP_TUR_WT_FSM_STATE_LSB (0)
+#define DBRP_TUR_WT_FSM_STATE_WIDTH (16)
+#define DBRP_TUR_WT_FSM_STATE_MASK (0x0000FFFF)
+
+#define DBRP_TUR_DEC_FSM_STATE_LSB (0)
+#define DBRP_TUR_DEC_FSM_STATE_WIDTH (32)
+#define DBRP_TUR_DEC_FSM_STATE_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DOB_FSM_DMA_STATE_LSB (21)
+#define DBRP_TUR_DOB_FSM_DMA_STATE_WIDTH (2)
+#define DBRP_TUR_DOB_FSM_DMA_STATE_MASK (0x00600000)
+
+#define DBRP_TUR_DOB_FSM_QUE_STATE_LSB (6)
+#define DBRP_TUR_DOB_FSM_QUE_STATE_WIDTH (15)
+#define DBRP_TUR_DOB_FSM_QUE_STATE_MASK (0x001FFFC0)
+
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_LSB (0)
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_WIDTH (6)
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_MASK (0x0000003F)
+
+#define DBRP_TUR_C_FSM_STATE_LSB (0)
+#define DBRP_TUR_C_FSM_STATE_WIDTH (10)
+#define DBRP_TUR_C_FSM_STATE_MASK (0x000003FF)
+
+#define DBRP_TUR_RTT_CFG_MIN_ITER_LSB (5)
+#define DBRP_TUR_RTT_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_RTT_CFG_MIN_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_RTT_CFG_MAX_ITER_LSB (0)
+#define DBRP_TUR_RTT_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_RTT_CFG_MAX_ITER_MASK (0x0000001F)
+
+#define DBRP_TUR_RTT_DST_ADR_LSB (0)
+#define DBRP_TUR_RTT_DST_ADR_WIDTH (32)
+#define DBRP_TUR_RTT_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_RTT_CBCRC_STATUS_LSB (0)
+#define DBRP_TUR_RTT_CBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_RTT_CBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_RTT_CBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_RTT_LST_ADR_LSB (0)
+#define DBRP_TUR_RTT_LST_ADR_WIDTH (32)
+#define DBRP_TUR_RTT_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_LSB (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_LSB (0)
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_MASK (0x0000001F)
+
+#define DBRP_TUR_EVDO_DST_PING_ADR_LSB (0)
+#define DBRP_TUR_EVDO_DST_PING_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_DST_PING_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_DST_PONG_ADR_LSB (0)
+#define DBRP_TUR_EVDO_DST_PONG_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_DST_PONG_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_CBCRC_STATUS_LSB (0)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_LST_ADR_LSB (0)
+#define DBRP_TUR_EVDO_LST_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_HARQ_ID_LSB (0)
+#define DBRP_TUR_EVDO_HARQ_ID_WIDTH (2)
+#define DBRP_TUR_EVDO_HARQ_ID_MASK (0x00000003)
+
+#define DBRP_TUR_EVDO_PACKET_SIZE_LSB (0)
+#define DBRP_TUR_EVDO_PACKET_SIZE_WIDTH (13)
+#define DBRP_TUR_EVDO_PACKET_SIZE_MASK (0x00001FFF)
+
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_LSB (0)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_WIDTH (1)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_C2K_BUSY_EVDO_LSB (1)
+#define DBRP_TUR_C2K_BUSY_EVDO_WIDTH (1)
+#define DBRP_TUR_C2K_BUSY_EVDO_MASK (0x00000002)
+#define DBRP_TUR_C2K_BUSY_EVDO_BIT (0x00000002)
+
+#define DBRP_TUR_C2K_BUSY_RTT_LSB (0)
+#define DBRP_TUR_C2K_BUSY_RTT_WIDTH (1)
+#define DBRP_TUR_C2K_BUSY_RTT_MASK (0x00000001)
+#define DBRP_TUR_C2K_BUSY_RTT_BIT (0x00000001)
+
+#define DBRP_TUR_CB_NUM_CB_NUM_LSB (0)
+#define DBRP_TUR_CB_NUM_CB_NUM_WIDTH (6)
+#define DBRP_TUR_CB_NUM_CB_NUM_MASK (0x0000003F)
+
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+
+#endif //#ifndef _CPH_C2K_RX_BRP_TUR_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_97.h b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_97.h
new file mode 100644
index 0000000..004c9cc
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxbrptur_97.h
@@ -0,0 +1,2509 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RX_BRP_TUR_H_
+#define _CPH_C2K_RX_BRP_TUR_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_WCTL_TUR_REG_BASE (0xac920000)
+
+#define RXBRP_WCTL_TUR_end (RXBRP_WCTL_TUR_REG_BASE + 0xD0A0 + 1*4)
+
+
+
+#define DBRP_TUR_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0000))
+#define DBRP_TUR_DSCRM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0004))
+#define DBRP_TUR_C_DBG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x0008))
+#define DBRP_TUR_DSCH_TRG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2000))
+#define DBRP_TUR_DSCH_DONE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2004))
+#define DBRP_TUR_DSCH_EN ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2008))
+#define DBRP_TUR_DSCH_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x200C))
+#define DBRP_TUR_DSCH_CBBUF ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2010))
+#define DBRP_TUR_DSCH_CH0_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2014))
+#define DBRP_TUR_DSCH_CH0_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2018))
+#define DBRP_TUR_DSCH_CH0_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x201C))
+#define DBRP_TUR_DSCH_CH0_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2020))
+#define DBRP_TUR_DSCH_CH0_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2024))
+#define DBRP_TUR_DSCH_CH0_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2028))
+#define DBRP_TUR_DSCH_CH0_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x202C))
+#define DBRP_TUR_DSCH_CH0_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2030))
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2034))
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2038))
+#define DBRP_TUR_DSCH_CH1_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x203C))
+#define DBRP_TUR_DSCH_CH1_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2040))
+#define DBRP_TUR_DSCH_CH1_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2044))
+#define DBRP_TUR_DSCH_CH1_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2048))
+#define DBRP_TUR_DSCH_CH1_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x204C))
+#define DBRP_TUR_DSCH_CH1_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2050))
+#define DBRP_TUR_DSCH_CH1_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2054))
+#define DBRP_TUR_DSCH_CH1_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2058))
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x205C))
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2060))
+#define DBRP_TUR_DSCH_CH2_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2064))
+#define DBRP_TUR_DSCH_CH2_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2068))
+#define DBRP_TUR_DSCH_CH2_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x206C))
+#define DBRP_TUR_DSCH_CH2_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2070))
+#define DBRP_TUR_DSCH_CH2_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2074))
+#define DBRP_TUR_DSCH_CH2_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2078))
+#define DBRP_TUR_DSCH_CH2_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x207C))
+#define DBRP_TUR_DSCH_CH2_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2080))
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2084))
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2088))
+#define DBRP_TUR_DSCH_CH3_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x208C))
+#define DBRP_TUR_DSCH_CH3_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2090))
+#define DBRP_TUR_DSCH_CH3_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2094))
+#define DBRP_TUR_DSCH_CH3_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2098))
+#define DBRP_TUR_DSCH_CH3_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x209C))
+#define DBRP_TUR_DSCH_CH3_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A0))
+#define DBRP_TUR_DSCH_CH3_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A4))
+#define DBRP_TUR_DSCH_CH3_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20A8))
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20AC))
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B0))
+#define DBRP_TUR_DSCH_CH4_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B4))
+#define DBRP_TUR_DSCH_CH4_LP0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20B8))
+#define DBRP_TUR_DSCH_CH4_LP1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20BC))
+#define DBRP_TUR_DSCH_CH4_LP2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C0))
+#define DBRP_TUR_DSCH_CH4_TrBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C4))
+#define DBRP_TUR_DSCH_CH4_CoBK ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20C8))
+#define DBRP_TUR_DSCH_CH4_DMA_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20CC))
+#define DBRP_TUR_DSCH_CH4_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D0))
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D4))
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20D8))
+#define DBRP_TUR_DSCH_CH0_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20DC))
+#define DBRP_TUR_DSCH_CH0_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E0))
+#define DBRP_TUR_DSCH_CH0_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E4))
+#define DBRP_TUR_DSCH_CH0_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20E8))
+#define DBRP_TUR_DSCH_CH0_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20EC))
+#define DBRP_TUR_DSCH_CH0_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F0))
+#define DBRP_TUR_DSCH_CH0_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F4))
+#define DBRP_TUR_DSCH_CH0_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20F8))
+#define DBRP_TUR_DSCH_CH1_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x20FC))
+#define DBRP_TUR_DSCH_CH1_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2100))
+#define DBRP_TUR_DSCH_CH1_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2104))
+#define DBRP_TUR_DSCH_CH1_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2108))
+#define DBRP_TUR_DSCH_CH1_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x210C))
+#define DBRP_TUR_DSCH_CH1_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2110))
+#define DBRP_TUR_DSCH_CH1_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2114))
+#define DBRP_TUR_DSCH_CH1_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2118))
+#define DBRP_TUR_DSCH_CH2_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x211C))
+#define DBRP_TUR_DSCH_CH2_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2120))
+#define DBRP_TUR_DSCH_CH2_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2124))
+#define DBRP_TUR_DSCH_CH2_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2128))
+#define DBRP_TUR_DSCH_CH2_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x212C))
+#define DBRP_TUR_DSCH_CH2_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2130))
+#define DBRP_TUR_DSCH_CH2_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2134))
+#define DBRP_TUR_DSCH_CH3_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2138))
+#define DBRP_TUR_DSCH_CH3_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x213C))
+#define DBRP_TUR_DSCH_CH3_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2140))
+#define DBRP_TUR_DSCH_CH3_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2144))
+#define DBRP_TUR_DSCH_CH3_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2148))
+#define DBRP_TUR_DSCH_CH3_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x214C))
+#define DBRP_TUR_DSCH_CH3_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2150))
+#define DBRP_TUR_DSCH_CH4_TBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2154))
+#define DBRP_TUR_DSCH_CH4_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2158))
+#define DBRP_TUR_DSCH_CH4_HDCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x215C))
+#define DBRP_TUR_DSCH_CH4_LP0_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2160))
+#define DBRP_TUR_DSCH_CH4_LP1_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2164))
+#define DBRP_TUR_DSCH_CH4_LP2_STORE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2168))
+#define DBRP_TUR_DSCH_CH4_iCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x216C))
+#define DBRP_TUR_BUSY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x2170))
+#define DBRP_TUR_LTE_TRG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3000))
+#define DBRP_TUR_LTE_DONE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3004))
+#define DBRP_TUR_LTE_LATCH ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3008))
+#define DBRP_TUR_LTE_FRM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x300C))
+#define DBRP_TUR_LTE_SI_PI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3010))
+#define DBRP_TUR_LTE_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3014))
+#define DBRP_TUR_LTE_CH0_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3018))
+#define DBRP_TUR_LTE_CH0_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x301C))
+#define DBRP_TUR_LTE_CH0_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3020))
+#define DBRP_TUR_LTE_CH0_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3024))
+#define DBRP_TUR_LTE_CH0_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3028))
+#define DBRP_TUR_LTE_CH0_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x302C))
+#define DBRP_TUR_LTE_CH1_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3030))
+#define DBRP_TUR_LTE_CH1_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3034))
+#define DBRP_TUR_LTE_CH1_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3038))
+#define DBRP_TUR_LTE_CH1_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x303C))
+#define DBRP_TUR_LTE_CH1_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3040))
+#define DBRP_TUR_LTE_CH1_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3044))
+#define DBRP_TUR_LTE_CH2_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3048))
+#define DBRP_TUR_LTE_CH2_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x304C))
+#define DBRP_TUR_LTE_CH2_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3050))
+#define DBRP_TUR_LTE_CH2_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3054))
+#define DBRP_TUR_LTE_CH2_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3058))
+#define DBRP_TUR_LTE_CH2_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x305C))
+#define DBRP_TUR_LTE_CH3_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3060))
+#define DBRP_TUR_LTE_CH3_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3064))
+#define DBRP_TUR_LTE_CH3_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3068))
+#define DBRP_TUR_LTE_CH3_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x306C))
+#define DBRP_TUR_LTE_CH3_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3070))
+#define DBRP_TUR_LTE_CH3_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3074))
+#define DBRP_TUR_LTE_CH4_ITER ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3078))
+#define DBRP_TUR_LTE_CH4_MAC_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x307C))
+#define DBRP_TUR_LTE_CH4_INI ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3080))
+#define DBRP_TUR_LTE_CH4_TBINFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3084))
+#define DBRP_TUR_LTE_CH4_EMI_INFO0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3088))
+#define DBRP_TUR_LTE_CH4_EMI_INFO1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x308C))
+#define DBRP_TUR_LTE_CC0_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3090))
+#define DBRP_TUR_LTE_CC0_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3094))
+#define DBRP_TUR_LTE_CC0_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3098))
+#define DBRP_TUR_LTE_CC0_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x309C))
+#define DBRP_TUR_LTE_CC0_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A0))
+#define DBRP_TUR_LTE_CC0_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A4))
+#define DBRP_TUR_LTE_CC0_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30A8))
+#define DBRP_TUR_LTE_CC0_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30AC))
+#define DBRP_TUR_LTE_CC0_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B0))
+#define DBRP_TUR_LTE_CC0_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B4))
+#define DBRP_TUR_LTE_CC1_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30B8))
+#define DBRP_TUR_LTE_CC1_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30BC))
+#define DBRP_TUR_LTE_CC1_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C0))
+#define DBRP_TUR_LTE_CC1_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C4))
+#define DBRP_TUR_LTE_CC1_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30C8))
+#define DBRP_TUR_LTE_CC1_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30CC))
+#define DBRP_TUR_LTE_CC1_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D0))
+#define DBRP_TUR_LTE_CC1_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D4))
+#define DBRP_TUR_LTE_CC1_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30D8))
+#define DBRP_TUR_LTE_CC1_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30DC))
+#define DBRP_TUR_LTE_CC2_CH0_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E0))
+#define DBRP_TUR_LTE_CC2_CH0_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E4))
+#define DBRP_TUR_LTE_CC2_CH1_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30E8))
+#define DBRP_TUR_LTE_CC2_CH1_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30EC))
+#define DBRP_TUR_LTE_CC2_CH2_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F0))
+#define DBRP_TUR_LTE_CC2_CH2_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F4))
+#define DBRP_TUR_LTE_CC2_CH3_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30F8))
+#define DBRP_TUR_LTE_CC2_CH3_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x30FC))
+#define DBRP_TUR_LTE_CC2_CH4_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3100))
+#define DBRP_TUR_LTE_CC2_CH4_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3104))
+#define DBRP_TUR_LTE_DONE_CC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3108))
+#define DBRP_TUR_LTE_CMD0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x310C))
+#define DBRP_TUR_LTE_CMD1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3110))
+#define DBRP_TUR_LTE_CC0_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3114))
+#define DBRP_TUR_LTE_CC0_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3118))
+#define DBRP_TUR_LTE_CC1_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x311C))
+#define DBRP_TUR_LTE_CC1_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3120))
+#define DBRP_TUR_LTE_CC2_CMD_RPT0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3124))
+#define DBRP_TUR_LTE_CC2_CMD_RPT1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3128))
+#define DBRP_TUR_LTE_DONE_ASSERT ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x312C))
+#define DBRP_TUR_LTE_FW_RST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x3FFC))
+#define DBRP_TUR_RSRV_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x400C))
+#define DBRP_TUR_RSRV_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4010))
+#define DBRP_TUR_RSRV_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4014))
+#define DBRP_TUR_DSCH_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4018))
+#define DBRP_TUR_DSCH_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x401C))
+#define DBRP_TUR_DSCH_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4020))
+#define DBRP_TUR_LTE_MPU_START ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4024))
+#define DBRP_TUR_LTE_MPU_END ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4028))
+#define DBRP_TUR_LTE_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x402C))
+#define DBRP_TUR_MPU_VIO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4030))
+#define DBRP_TUR_MPU ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x4034))
+#define DBRP_TUR_LTE_MPIF_DATA_CNT ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5000))
+#define DBRP_TUR_LTE_MPIF_DBG_0 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5004))
+#define DBRP_TUR_LTE_MPIF_DBG_1 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5008))
+#define DBRP_TUR_LTE_MPIF_DBG_2 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x500C))
+#define DBRP_TUR_LTE_MPIF_DBG_3 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5010))
+#define DBRP_TUR_LTE_MPIF_DBG_4 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5014))
+#define DBRP_TUR_LTE_MPIF_DBG_5 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5018))
+#define DBRP_TUR_LTE_MPIF_DBG_6 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x501C))
+#define DBRP_TUR_LTE_MPIF_DBG_7 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5020))
+#define DBRP_TUR_LTE_MPIF_DBG_8 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5024))
+#define DBRP_TUR_LTE_MPIF_DBG_9 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5028))
+#define DBRP_TUR_LTE_MPIF_DBG_10 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x502C))
+#define DBRP_TUR_LTE_MPIF_DBG_11 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5030))
+#define DBRP_TUR_LTE_MPIF_DBG_12 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5034))
+#define DBRP_TUR_LTE_MPIF_DBG_13 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5038))
+#define DBRP_TUR_LTE_MPIF_DBG_14 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x503C))
+#define DBRP_TUR_LTE_MPIF_DBG_15 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5040))
+#define DBRP_TUR_LTE_MPIF_DBG_16 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5044))
+#define DBRP_TUR_LTE_MPIF_DBG_17 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5048))
+#define DBRP_TUR_LTE_MPIF_DBG_18 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x504C))
+#define DBRP_TUR_LTE_MPIF_DBG_19 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5050))
+#define DBRP_TUR_LTE_MPIF_DBG_20 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5054))
+#define DBRP_TUR_LTE_MPIF_DBG_21 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5058))
+#define DBRP_TUR_LTE_MPIF_DBG_22 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x505C))
+#define DBRP_TUR_LTE_MPIF_DBG_23 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5060))
+#define DBRP_TUR_LTE_MPIF_DBG_24 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5064))
+#define DBRP_TUR_LTE_MPIF_DBG_25 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5068))
+#define DBRP_TUR_LTE_MPIF_DBG_26 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x506C))
+#define DBRP_TUR_LTE_MPIF_DBG_27 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5070))
+#define DBRP_TUR_LTE_MPIF_DBG_28 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5074))
+#define DBRP_TUR_LTE_MPIF_DBG_29 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5078))
+#define DBRP_TUR_LTE_MPIF_DBG_30 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x507C))
+#define DBRP_TUR_LTE_MPIF_DBG_31 ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5080))
+#define DBRP_TUR_LTE_MPIF_WRITE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5084))
+#define DBRP_TUR_L_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5088))
+#define DBRP_TUR_WT_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x508C))
+#define DBRP_TUR_DEC_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5090))
+#define DBRP_TUR_DOB_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5094))
+#define DBRP_TUR_C_FSM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x5098))
+#define DBRP_TUR_MODE_DBG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x509C))
+#define DBRP_TUR_RTT_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6000))
+#define DBRP_TUR_RTT_DST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6004))
+#define DBRP_TUR_RTT_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6008))
+#define DBRP_TUR_RTT_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x600C))
+#define DBRP_TUR_RTT_CBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6010))
+#define DBRP_TUR_RTT_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6014))
+#define DBRP_TUR_RTT_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x6018))
+#define DBRP_TUR_EVDO_ITER_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7000))
+#define DBRP_TUR_EVDO_DST_PING ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7004))
+#define DBRP_TUR_EVDO_DST_PONG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7008))
+#define DBRP_TUR_EVDO_DMA_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x700C))
+#define DBRP_TUR_EVDO_TRACE_CFG ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7010))
+#define DBRP_TUR_EVDO_CBCRC ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7014))
+#define DBRP_TUR_EVDO_LST ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7018))
+#define DBRP_TUR_EVDO_HARQ ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x701C))
+#define DBRP_TUR_EVDO_PACKET ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7020))
+#define DBRP_TUR_EVDO_DST_ADR ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7024))
+#define DBRP_TUR_EVDO_ENERGY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x7028))
+#define DBRP_TUR_C2K_BUSY ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0x702C))
+#define DBRP_TUR_CB_NUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD000))
+#define DBRP_TUR_CH0_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD018))
+#define DBRP_TUR_CH0_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD028))
+#define DBRP_TUR_CH0_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD030))
+#define DBRP_TUR_CH1_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD034))
+#define DBRP_TUR_CH1_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD044))
+#define DBRP_TUR_CH1_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD04C))
+#define DBRP_TUR_CH2_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD050))
+#define DBRP_TUR_CH2_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD060))
+#define DBRP_TUR_CH2_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD068))
+#define DBRP_TUR_CH3_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD06C))
+#define DBRP_TUR_CH3_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD07C))
+#define DBRP_TUR_CH3_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD084))
+#define DBRP_TUR_CH4_CB_SIZE ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD088))
+#define DBRP_TUR_CH4_CBNUM ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD098))
+#define DBRP_TUR_CH4_DMY_FIL_INFO ((APBADDR32)(RXBRP_WCTL_TUR_REG_BASE + 0xD0A0))
+
+
+#define DBRP_TUR_CFG_CR_TH_OFST_LSB (0)
+#define DBRP_TUR_CFG_CR_TH_OFST_WIDTH (13)
+#define DBRP_TUR_CFG_CR_TH_OFST_MASK (0x00001FFF)
+
+#define DBRP_TUR_DSCRM_BYPASS_LSB (0)
+#define DBRP_TUR_DSCRM_BYPASS_WIDTH (1)
+#define DBRP_TUR_DSCRM_BYPASS_MASK (0x00000001)
+#define DBRP_TUR_DSCRM_BYPASS_BIT (0x00000001)
+
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_LSB (4)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_WIDTH (1)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_MASK (0x00000010)
+#define DBRP_TUR_C_DBG_TIMER_LATCH_EN_BIT (0x00000010)
+
+#define DBRP_TUR_C_DBG_EMI_EN_LSB (0)
+#define DBRP_TUR_C_DBG_EMI_EN_WIDTH (1)
+#define DBRP_TUR_C_DBG_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_C_DBG_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_TRG_START_LSB (0)
+#define DBRP_TUR_DSCH_TRG_START_WIDTH (1)
+#define DBRP_TUR_DSCH_TRG_START_MASK (0x00000001)
+#define DBRP_TUR_DSCH_TRG_START_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_LSB (9)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_MASK (0x00000200)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_TRG_BIT (0x00000200)
+
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_LSB (8)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_MASK (0x00000100)
+#define DBRP_TUR_DSCH_DONE_SW_IRQ_STATUS_BIT (0x00000100)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_LSB (6)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_MASK (0x00000040)
+#define DBRP_TUR_DSCH_DONE_STATUS_DISABLE_BIT (0x00000040)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_LSB (4)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_MASK (0x00000010)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH4_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_LSB (3)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_MASK (0x00000008)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH3_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_LSB (2)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_MASK (0x00000004)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH2_BIT (0x00000004)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_LSB (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_MASK (0x00000002)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH1_BIT (0x00000002)
+
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_LSB (0)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_WIDTH (1)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_MASK (0x00000001)
+#define DBRP_TUR_DSCH_DONE_STATUS_CH0_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_LSB (6)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_MASK (0x00000040)
+#define DBRP_TUR_DSCH_EN_LOWPWR_EN_BIT (0x00000040)
+
+#define DBRP_TUR_DSCH_EN_CHi_LSB (0)
+#define DBRP_TUR_DSCH_EN_CHi_WIDTH (5)
+#define DBRP_TUR_DSCH_EN_CHi_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_LSB (0)
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_WIDTH (5)
+#define DBRP_TUR_DSCH_CFG_HDACRC_MODE_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_LSB (0)
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_WIDTH (12)
+#define DBRP_TUR_DSCH_CBBUF_BASE_ADDR_MASK (0x00000FFF)
+
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH0_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH0_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH0_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH0_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH0_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH0_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH0_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH0_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH1_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH1_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH1_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH1_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH1_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH1_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH1_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH1_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH2_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH2_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH2_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH2_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH2_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH2_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH2_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH2_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH3_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH3_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH3_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH3_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH3_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH3_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH3_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH3_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_LSB (16)
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_CFG_UEID_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_LSB (15)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_MASK (0x00008000)
+#define DBRP_TUR_DSCH_CH4_CFG_CRC_METHOD_BIT (0x00008000)
+
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_LSB (10)
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MIN_ITER_MASK (0x00007C00)
+
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_LSB (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_CFG_MAX_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_LSB (4)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_MASK (0x00000010)
+#define DBRP_TUR_DSCH_CH4_CFG_TB_EQ_BIT (0x00000010)
+
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_LSB (3)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_MASK (0x00000008)
+#define DBRP_TUR_DSCH_CH4_CFG_HDCRCES_EN_BIT (0x00000008)
+
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_LSB (0)
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_WIDTH (3)
+#define DBRP_TUR_DSCH_CH4_CFG_CRCSIZE_MASK (0x00000007)
+
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_LSB (16)
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_LP0_DSCRM_INI_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_LSB (4)
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP0_WBUF_INI_MASK (0x00003FF0)
+
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_LP0_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_WIDTH (24)
+#define DBRP_TUR_DSCH_CH4_LP1_PCRC_INI_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_LSB (21)
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP2_CBUF_INI_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_WIDTH (21)
+#define DBRP_TUR_DSCH_CH4_LP2_RDCNT_INI_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBSIZE_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_WIDTH (6)
+#define DBRP_TUR_DSCH_CH4_TrBK_TBNUM_MASK (0x0000003F)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_LSB (16)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_WIDTH (13)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBSIZE_MASK (0x1FFF0000)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_LSB (4)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_WIDTH (6)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBPAD_MASK (0x000003F0)
+
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_LSB (0)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_CoBK_CBNUM_MASK (0x0000000F)
+
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_DMA_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_DSCH_CH4_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_LSB (4)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_CB_IDX_MASK (0x000000F0)
+
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_LSB (0)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_HSRM_CFG_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH0_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH0_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH0_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH0_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH0_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH0_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_DSCH_CH0_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH1_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH1_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH1_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH1_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH1_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH1_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_DSCH_CH1_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH2_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH2_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH2_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH2_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH2_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH2_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH3_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH3_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH3_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH3_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH3_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH3_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_LSB (0)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_DSCH_CH4_TBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_CH4_LST_ADR_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LST_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_WIDTH (9)
+#define DBRP_TUR_DSCH_CH4_HDCRC_RESULT_MASK (0x000001FF)
+
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_LSB (16)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_WIDTH (16)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_DSCRM_MASK (0xFFFF0000)
+
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP0_STORE_WBUF_MASK (0x000003FF)
+
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_WIDTH (24)
+#define DBRP_TUR_DSCH_CH4_LP1_STORE_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_LSB (21)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_WIDTH (10)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_CBUF_MASK (0x7FE00000)
+
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_WIDTH (21)
+#define DBRP_TUR_DSCH_CH4_LP2_STORE_RDCNT_MASK (0x001FFFFF)
+
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_LSB (0)
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_WIDTH (32)
+#define DBRP_TUR_DSCH_CH4_iCRC_RESULT_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_BUSY_DSCH_LSB (1)
+#define DBRP_TUR_BUSY_DSCH_WIDTH (1)
+#define DBRP_TUR_BUSY_DSCH_MASK (0x00000002)
+#define DBRP_TUR_BUSY_DSCH_BIT (0x00000002)
+
+#define DBRP_TUR_LTE_TRG_START_LSB (0)
+#define DBRP_TUR_LTE_TRG_START_WIDTH (1)
+#define DBRP_TUR_LTE_TRG_START_MASK (0x00000001)
+#define DBRP_TUR_LTE_TRG_START_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_LSB (13)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_MASK (0x00002000)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_TRG_BIT (0x00002000)
+
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_LSB (12)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_MASK (0x00001000)
+#define DBRP_TUR_LTE_DONE_SW_IRQ_STATUS_BIT (0x00001000)
+
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_LSB (8)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_CC2_STATUS_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_LSB (4)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_CC1_STATUS_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_LSB (0)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_CC0_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_LATCH_STATUS_LSB (0)
+#define DBRP_TUR_LTE_LATCH_STATUS_WIDTH (1)
+#define DBRP_TUR_LTE_LATCH_STATUS_MASK (0x00000001)
+#define DBRP_TUR_LTE_LATCH_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_LSB (16)
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_WIDTH (10)
+#define DBRP_TUR_LTE_FRM_FRAME_IDX_MASK (0x03FF0000)
+
+#define DBRP_TUR_LTE_FRM_SIM_IDX_LSB (4)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_WIDTH (1)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_MASK (0x00000010)
+#define DBRP_TUR_LTE_FRM_SIM_IDX_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_LSB (0)
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_FRM_SUBF_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_SI_PI_PI_TID_LSB (22)
+#define DBRP_TUR_LTE_SI_PI_PI_TID_WIDTH (10)
+#define DBRP_TUR_LTE_SI_PI_PI_TID_MASK (0xFFC00000)
+
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_LSB (16)
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_WIDTH (2)
+#define DBRP_TUR_LTE_SI_PI_SI_SUBF_IDX_MASK (0x00030000)
+
+#define DBRP_TUR_LTE_SI_PI_SI_TID_LSB (6)
+#define DBRP_TUR_LTE_SI_PI_SI_TID_WIDTH (10)
+#define DBRP_TUR_LTE_SI_PI_SI_TID_MASK (0x0000FFC0)
+
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_LSB (0)
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_WIDTH (6)
+#define DBRP_TUR_LTE_SI_PI_SI_TYPE_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_LSB (4)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_WIDTH (1)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_MASK (0x00000010)
+#define DBRP_TUR_LTE_CBNUM_BIT_ORDER_BIG_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_LSB (0)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_WIDTH (1)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_MASK (0x00000001)
+#define DBRP_TUR_LTE_CBNUM_ELLR_CTRL_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH0_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH0_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH0_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH0_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH0_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH0_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH0_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH1_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH1_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH1_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH1_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH1_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH1_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH1_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH2_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH2_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH2_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH2_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH2_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH2_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH2_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH3_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH3_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH3_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH3_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH3_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH3_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH3_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_LSB (24)
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_COM_MIN_MASK (0x3F000000)
+
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_LSB (20)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_MASK (0x00100000)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_ELLR_DUMP_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_LSB (12)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_SECOND_MAX_MASK (0x0003F000)
+
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_LSB (8)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_ELLR_DUMP_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_LSB (0)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_ITER_FIRST_MAX_MASK (0x0000003F)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_LSB (24)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_MASK (0x01000000)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_DOB_DISABLE_BIT (0x01000000)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_LSB (16)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_WIDTH (6)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_HARQ_ID_MASK (0x003F0000)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_LSB (8)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_MASK (0x00000100)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_CW_SWITCH_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_LSB (4)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_MASK (0x00000010)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_TCRNTI_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_LSB (0)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH4_MAC_INFO_START_IDX_MASK (0x0000000F)
+
+#define DBRP_TUR_LTE_CH4_INI_PCRC_LSB (0)
+#define DBRP_TUR_LTE_CH4_INI_PCRC_WIDTH (24)
+#define DBRP_TUR_LTE_CH4_INI_PCRC_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_LSB (0)
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_WIDTH (17)
+#define DBRP_TUR_LTE_CH4_TBINFO1_TBSIZE_MASK (0x0001FFFF)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_LSB (20)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_CB_IDX_MASK (0x00F00000)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_LSB (16)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_MASK (0x00010000)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_TRACE_EN_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_LSB (0)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_WIDTH (1)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_CH4_EMI_INFO0_EMI_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_LSB (0)
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_CH4_EMI_INFO1_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC0_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC0_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC1_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC1_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH0_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH0_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH1_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH1_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH2_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH2_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH3_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH3_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_LSB (26)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MIN_MASK (0xFC000000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_LSB (20)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_WIDTH (6)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_ITER_MAX_MASK (0x03F00000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_LSB (16)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_WIDTH (1)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_MASK (0x00010000)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_TBCRC_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_WIDTH (16)
+#define DBRP_TUR_LTE_CC2_CH4_RPT0_CBCRC_MASK (0x0000FFFF)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_LSB (25)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_WIDTH (4)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_STOP_IDX_MASK (0x1E000000)
+
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_LSB (0)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_WIDTH (24)
+#define DBRP_TUR_LTE_CC2_CH4_RPT1_PCRC_RESULT_MASK (0x00FFFFFF)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_LSB (20)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_MASK (0x00100000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH4_BIT (0x00100000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_LSB (19)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_MASK (0x00080000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH3_BIT (0x00080000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_LSB (18)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_MASK (0x00040000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH2_BIT (0x00040000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_LSB (17)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_MASK (0x00020000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH1_BIT (0x00020000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_LSB (16)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_MASK (0x00010000)
+#define DBRP_TUR_LTE_DONE_CC_CC2_CH0_BIT (0x00010000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_LSB (12)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_MASK (0x00001000)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH4_BIT (0x00001000)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_LSB (11)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_MASK (0x00000800)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH3_BIT (0x00000800)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_LSB (10)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_MASK (0x00000400)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH2_BIT (0x00000400)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_LSB (9)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_MASK (0x00000200)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH1_BIT (0x00000200)
+
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_LSB (8)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_CC_CC1_CH0_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_LSB (4)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH4_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_LSB (3)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_MASK (0x00000008)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH3_BIT (0x00000008)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_LSB (2)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_MASK (0x00000004)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH2_BIT (0x00000004)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_LSB (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_MASK (0x00000002)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH1_BIT (0x00000002)
+
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_LSB (0)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_CC_CC0_CH0_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_CMD0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CMD0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CMD0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CMD1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CMD1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CMD1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC0_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC0_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC1_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC1_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC2_CMD_RPT0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_LSB (0)
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_CC2_CMD_RPT1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_LSB (8)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_MASK (0x00000100)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC2_BIT (0x00000100)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_LSB (4)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_MASK (0x00000010)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC1_BIT (0x00000010)
+
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_LSB (0)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_WIDTH (1)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_MASK (0x00000001)
+#define DBRP_TUR_LTE_DONE_ASSERT_CC0_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_FW_RST_FLAG_LSB (0)
+#define DBRP_TUR_LTE_FW_RST_FLAG_WIDTH (1)
+#define DBRP_TUR_LTE_FW_RST_FLAG_MASK (0x00000001)
+#define DBRP_TUR_LTE_FW_RST_FLAG_BIT (0x00000001)
+
+#define DBRP_TUR_RSRV_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_RSRV_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_RSRV_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RSRV_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_RSRV_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_RSRV_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RSRV_MPU_EN_LSB (0)
+#define DBRP_TUR_RSRV_MPU_EN_WIDTH (1)
+#define DBRP_TUR_RSRV_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_RSRV_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_DSCH_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_DSCH_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_DSCH_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_DSCH_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DSCH_MPU_EN_LSB (0)
+#define DBRP_TUR_DSCH_MPU_EN_WIDTH (1)
+#define DBRP_TUR_DSCH_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_DSCH_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPU_START_ADR_LSB (0)
+#define DBRP_TUR_LTE_MPU_START_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPU_END_ADR_LSB (0)
+#define DBRP_TUR_LTE_MPU_END_ADR_WIDTH (32)
+#define DBRP_TUR_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPU_EN_LSB (0)
+#define DBRP_TUR_LTE_MPU_EN_WIDTH (1)
+#define DBRP_TUR_LTE_MPU_EN_MASK (0x00000001)
+#define DBRP_TUR_LTE_MPU_EN_BIT (0x00000001)
+
+#define DBRP_TUR_MPU_VIO_ADR_LSB (0)
+#define DBRP_TUR_MPU_VIO_ADR_WIDTH (32)
+#define DBRP_TUR_MPU_VIO_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_MPU_SW_IRQ_TRG_LSB (5)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_WIDTH (1)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_MASK (0x00000020)
+#define DBRP_TUR_MPU_SW_IRQ_TRG_BIT (0x00000020)
+
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_LSB (4)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_WIDTH (1)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_MASK (0x00000010)
+#define DBRP_TUR_MPU_SW_IRQ_STATUS_BIT (0x00000010)
+
+#define DBRP_TUR_MPU_VIOLATE_LSB (0)
+#define DBRP_TUR_MPU_VIOLATE_WIDTH (1)
+#define DBRP_TUR_MPU_VIOLATE_MASK (0x00000001)
+#define DBRP_TUR_MPU_VIOLATE_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_WIDTH (1)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_MASK (0x00000001)
+#define DBRP_TUR_LTE_MPIF_DATA_CNT_MISMATCH_BIT (0x00000001)
+
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_0_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_1_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_2_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_3_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_4_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_5_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_6_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_7_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_8_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_9_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_10_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_11_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_12_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_13_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_14_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_15_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_16_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_17_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_18_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_19_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_20_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_21_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_22_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_23_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_24_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_25_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_26_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_27_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_28_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_29_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_30_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_LSB (0)
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_WIDTH (32)
+#define DBRP_TUR_LTE_MPIF_DBG_31_CMD_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_LSB (0)
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_WIDTH (6)
+#define DBRP_TUR_LTE_MPIF_WRITE_POINTER_MASK (0x0000003F)
+
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_LSB (16)
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_WIDTH (7)
+#define DBRP_TUR_L_FSM_CUR_CB_IDX_MASK (0x007F0000)
+
+#define DBRP_TUR_L_FSM_STATE_LSB (0)
+#define DBRP_TUR_L_FSM_STATE_WIDTH (9)
+#define DBRP_TUR_L_FSM_STATE_MASK (0x000001FF)
+
+#define DBRP_TUR_WT_FSM_STATE_LSB (0)
+#define DBRP_TUR_WT_FSM_STATE_WIDTH (16)
+#define DBRP_TUR_WT_FSM_STATE_MASK (0x0000FFFF)
+
+#define DBRP_TUR_DEC_FSM_STATE_LSB (0)
+#define DBRP_TUR_DEC_FSM_STATE_WIDTH (32)
+#define DBRP_TUR_DEC_FSM_STATE_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_DOB_FSM_DMA_STATE_LSB (21)
+#define DBRP_TUR_DOB_FSM_DMA_STATE_WIDTH (2)
+#define DBRP_TUR_DOB_FSM_DMA_STATE_MASK (0x00600000)
+
+#define DBRP_TUR_DOB_FSM_QUE_STATE_LSB (6)
+#define DBRP_TUR_DOB_FSM_QUE_STATE_WIDTH (15)
+#define DBRP_TUR_DOB_FSM_QUE_STATE_MASK (0x001FFFC0)
+
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_LSB (0)
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_WIDTH (6)
+#define DBRP_TUR_DOB_FSM_TRBK_STATE_MASK (0x0000003F)
+
+#define DBRP_TUR_C_FSM_STATE_LSB (0)
+#define DBRP_TUR_C_FSM_STATE_WIDTH (10)
+#define DBRP_TUR_C_FSM_STATE_MASK (0x000003FF)
+
+#define DBRP_TUR_RTT_CFG_MIN_ITER_LSB (5)
+#define DBRP_TUR_RTT_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_RTT_CFG_MIN_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_RTT_CFG_MAX_ITER_LSB (0)
+#define DBRP_TUR_RTT_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_RTT_CFG_MAX_ITER_MASK (0x0000001F)
+
+#define DBRP_TUR_RTT_DST_ADR_LSB (0)
+#define DBRP_TUR_RTT_DST_ADR_WIDTH (32)
+#define DBRP_TUR_RTT_DST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_RTT_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_RTT_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_RTT_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_RTT_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_RTT_CBCRC_STATUS_LSB (0)
+#define DBRP_TUR_RTT_CBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_RTT_CBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_RTT_CBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_RTT_LST_ADR_LSB (0)
+#define DBRP_TUR_RTT_LST_ADR_WIDTH (32)
+#define DBRP_TUR_RTT_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_RTT_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_LSB (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_WIDTH (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MIN_ITER_MASK (0x000003E0)
+
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_LSB (0)
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_WIDTH (5)
+#define DBRP_TUR_EVDO_ITER_CFG_MAX_ITER_MASK (0x0000001F)
+
+#define DBRP_TUR_EVDO_DST_PING_ADR_LSB (0)
+#define DBRP_TUR_EVDO_DST_PING_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_DST_PING_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_DST_PONG_ADR_LSB (0)
+#define DBRP_TUR_EVDO_DST_PONG_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_DST_PONG_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_LSB (7)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_WIDTH (1)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_MASK (0x00000080)
+#define DBRP_TUR_EVDO_DMA_CFG_CRC_REMOVE_BIT (0x00000080)
+
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_LSB (5)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_WIDTH (1)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_MASK (0x00000020)
+#define DBRP_TUR_EVDO_DMA_CFG_SWAP_ENDIAN_BIT (0x00000020)
+
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_LSB (0)
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_WIDTH (5)
+#define DBRP_TUR_EVDO_DMA_CFG_MAC_OFST_MASK (0x0000001F)
+
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_LSB (0)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_WIDTH (1)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_MASK (0x00000001)
+#define DBRP_TUR_EVDO_TRACE_CFG_TRACE_EN_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_CBCRC_STATUS_LSB (0)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_WIDTH (1)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_MASK (0x00000001)
+#define DBRP_TUR_EVDO_CBCRC_STATUS_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_LST_ADR_LSB (0)
+#define DBRP_TUR_EVDO_LST_ADR_WIDTH (32)
+#define DBRP_TUR_EVDO_LST_ADR_MASK (0xFFFFFFFF)
+
+#define DBRP_TUR_EVDO_HARQ_ID_LSB (0)
+#define DBRP_TUR_EVDO_HARQ_ID_WIDTH (2)
+#define DBRP_TUR_EVDO_HARQ_ID_MASK (0x00000003)
+
+#define DBRP_TUR_EVDO_PACKET_SIZE_LSB (0)
+#define DBRP_TUR_EVDO_PACKET_SIZE_WIDTH (13)
+#define DBRP_TUR_EVDO_PACKET_SIZE_MASK (0x00001FFF)
+
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_LSB (0)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_WIDTH (1)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_MASK (0x00000001)
+#define DBRP_TUR_EVDO_DST_ADR_PING_PONG_BIT (0x00000001)
+
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_LSB (0)
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_WIDTH (20)
+#define DBRP_TUR_EVDO_ENERGY_ACCUMULATE_MASK (0x000FFFFF)
+
+#define DBRP_TUR_C2K_BUSY_EVDO_LSB (1)
+#define DBRP_TUR_C2K_BUSY_EVDO_WIDTH (1)
+#define DBRP_TUR_C2K_BUSY_EVDO_MASK (0x00000002)
+#define DBRP_TUR_C2K_BUSY_EVDO_BIT (0x00000002)
+
+#define DBRP_TUR_C2K_BUSY_RTT_LSB (0)
+#define DBRP_TUR_C2K_BUSY_RTT_WIDTH (1)
+#define DBRP_TUR_C2K_BUSY_RTT_MASK (0x00000001)
+#define DBRP_TUR_C2K_BUSY_RTT_BIT (0x00000001)
+
+#define DBRP_TUR_CB_NUM_CB_NUM_LSB (0)
+#define DBRP_TUR_CB_NUM_CB_NUM_WIDTH (6)
+#define DBRP_TUR_CB_NUM_CB_NUM_MASK (0x0000003F)
+
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH0_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH0_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH0_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH0_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH0_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH1_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH1_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH1_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH1_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH1_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH2_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH2_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH2_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH2_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH2_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH3_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH3_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH3_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH3_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH3_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_WIDTH (13)
+#define DBRP_TUR_CH4_CB_SIZE_SMALL_CB_MASK (0x1FFF0000)
+
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_WIDTH (13)
+#define DBRP_TUR_CH4_CB_SIZE_LARGE_CB_MASK (0x00001FFF)
+
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_LSB (16)
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_WIDTH (5)
+#define DBRP_TUR_CH4_CBNUM_SMALL_CB_MASK (0x001F0000)
+
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_LSB (0)
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_WIDTH (5)
+#define DBRP_TUR_CH4_CBNUM_LARGE_CB_MASK (0x0000001F)
+
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_LSB (16)
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_WIDTH (6)
+#define DBRP_TUR_CH4_DMY_FIL_INFO_FILLER_NUM_MASK (0x003F0000)
+
+
+#endif //#ifndef _CPH_C2K_RX_BRP_TUR_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxdfe.h b/mcu/interface/l1/cl1/common/HW/cphc2krxdfe.h
new file mode 100644
index 0000000..b5c6e49
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxdfe.h
@@ -0,0 +1,1229 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RXDFE_H_
+#define _CPH_C2K_RXDFE_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE_FC_ACT_REG_BASE (0xA70C0000)
+
+#define RXDFE_FC_ACT_end (RXDFE_FC_ACT_REG_BASE + 0x01A0 + 1*4)
+
+
+
+#define RXDFE_FC_P_SWAP ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0000))
+#define RXDFE_FC_A_SWAP_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0004))
+#define RXDFE_FC_MS_WB_0_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0008))
+#define RXDFE_FC_MS_WB_1_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x000C))
+#define RXDFE_FC_A_SWAP_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0010))
+#define RXDFE_FC_MS_WB_0_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0014))
+#define RXDFE_FC_MS_WB_1_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0018))
+#define RXDFE_FC_P_CON_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x001C))
+#define RXDFE_FC_SW_DCOC_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0020))
+#define RXDFE_FC_P_CON_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0024))
+#define RXDFE_FC_SW_DCOC_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0028))
+#define RXDFE_FC_P_CON_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x002C))
+#define RXDFE_FC_SW_DCOC_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0030))
+#define RXDFE_FC_P_CON_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0034))
+#define RXDFE_FC_SW_DCOC_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0038))
+#define RXDFE_FC_C_CON_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x003C))
+#define RXDFE_FC_SW_DAGC_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0040))
+#define RXDFE_FC_SW_CS_DAGC_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0044))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0048))
+#define RXDFE_FC_C_CON_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x004C))
+#define RXDFE_FC_SW_DAGC_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0050))
+#define RXDFE_FC_SW_CS_DAGC_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0054))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0058))
+#define RXDFE_FC_C_CON_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x005C))
+#define RXDFE_FC_SW_DAGC_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0060))
+#define RXDFE_FC_SW_CS_DAGC_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0064))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0068))
+#define RXDFE_FC_C_CON_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x006C))
+#define RXDFE_FC_SW_DAGC_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0070))
+#define RXDFE_FC_SW_CS_DAGC_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0074))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0078))
+#define RXDFE_FC_FDPM_0_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x007C))
+#define RXDFE_FC_FDPM_1_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0080))
+#define RXDFE_FC_FDPM_2_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0084))
+#define RXDFE_FC_RFEQ_0_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0088))
+#define RXDFE_FC_RFEQ_1_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x008C))
+#define RXDFE_FC_RFEQ_2_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0090))
+#define RXDFE_FC_RFEQ_3_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0094))
+#define RXDFE_FC_RFEQ_4_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0098))
+#define RXDFE_FC_IQC_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x009C))
+#define RXDFE_FC_FDPM_0_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A0))
+#define RXDFE_FC_FDPM_1_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A4))
+#define RXDFE_FC_FDPM_2_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A8))
+#define RXDFE_FC_RFEQ_0_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00AC))
+#define RXDFE_FC_RFEQ_1_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B0))
+#define RXDFE_FC_RFEQ_2_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B4))
+#define RXDFE_FC_RFEQ_3_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B8))
+#define RXDFE_FC_RFEQ_4_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00BC))
+#define RXDFE_FC_IQC_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C0))
+#define RXDFE_FC_FDPM_0_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C4))
+#define RXDFE_FC_FDPM_1_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C8))
+#define RXDFE_FC_FDPM_2_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00CC))
+#define RXDFE_FC_RFEQ_0_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D0))
+#define RXDFE_FC_RFEQ_1_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D4))
+#define RXDFE_FC_RFEQ_2_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D8))
+#define RXDFE_FC_RFEQ_3_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00DC))
+#define RXDFE_FC_RFEQ_4_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E0))
+#define RXDFE_FC_IQC_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E4))
+#define RXDFE_FC_FDPM_0_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E8))
+#define RXDFE_FC_FDPM_1_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00EC))
+#define RXDFE_FC_FDPM_2_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F0))
+#define RXDFE_FC_RFEQ_0_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F4))
+#define RXDFE_FC_RFEQ_1_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F8))
+#define RXDFE_FC_RFEQ_2_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00FC))
+#define RXDFE_FC_RFEQ_3_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0100))
+#define RXDFE_FC_RFEQ_4_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0104))
+#define RXDFE_FC_IQC_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0108))
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x010C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x011C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x012C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x013C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x014C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x015C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x016C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x017C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NCO_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x018C))
+#define RXDFE_FC_NCO_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0190))
+#define RXDFE_FC_NCO_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0194))
+#define RXDFE_FC_NCO_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0198))
+#define RXDFE_FC_NCO_MBSFN_C0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x019C))
+#define RXDFE_FC_NCO_MBSFN_C1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x01A0))
+
+
+#define RXDFE_FC_P_SWAP_P_SWAP_LSB (0)
+#define RXDFE_FC_P_SWAP_P_SWAP_WIDTH (1)
+#define RXDFE_FC_P_SWAP_P_SWAP_MASK (0x00000001)
+#define RXDFE_FC_P_SWAP_P_SWAP_BIT (0x00000001)
+
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_LSB (0)
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_WIDTH (1)
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_MASK (0x00000001)
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_BIT (0x00000001)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_LSB (24)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_MASK (0x7F000000)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_LSB (16)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_MASK (0x007F0000)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_LSB (8)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_MASK (0x00007F00)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_LSB (0)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_MASK (0x0000007F)
+
+#define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_LSB (0)
+#define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_MASK (0x0000007F)
+
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_LSB (0)
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_WIDTH (1)
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_MASK (0x00000001)
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_BIT (0x00000001)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_LSB (24)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_MASK (0x7F000000)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_LSB (16)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_MASK (0x007F0000)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_LSB (8)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_MASK (0x00007F00)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_LSB (0)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_MASK (0x0000007F)
+
+#define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_LSB (0)
+#define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_MASK (0x0000007F)
+
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_LSB (20)
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_LSB (15)
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_LSB (14)
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_LSB (13)
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_LSB (12)
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_LSB (10)
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_LSB (9)
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_LSB (8)
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_LSB (4)
+#define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_LSB (0)
+#define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_LSB (16)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_LSB (0)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_LSB (20)
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_LSB (15)
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_LSB (14)
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_LSB (13)
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_LSB (12)
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_LSB (10)
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_LSB (9)
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_LSB (8)
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_LSB (4)
+#define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_LSB (0)
+#define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_LSB (16)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_LSB (0)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_LSB (20)
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_LSB (15)
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_LSB (14)
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_LSB (13)
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_LSB (12)
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_LSB (10)
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_LSB (9)
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_LSB (8)
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_LSB (4)
+#define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_LSB (0)
+#define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_LSB (16)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_LSB (0)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_LSB (20)
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_LSB (15)
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_LSB (14)
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_LSB (13)
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_LSB (12)
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_LSB (10)
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_LSB (9)
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_LSB (8)
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_LSB (4)
+#define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_LSB (0)
+#define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_LSB (16)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_LSB (0)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_LSB (22)
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_LSB (21)
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_LSB (20)
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_LSB (13)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_LSB (12)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_LSB (8)
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_LSB (4)
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_LSB (0)
+#define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_WIDTH (4)
+#define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_LSB (8)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_LSB (0)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_LSB (22)
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_LSB (21)
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_LSB (20)
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_LSB (13)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_LSB (12)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_LSB (8)
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_LSB (4)
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_LSB (0)
+#define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_WIDTH (4)
+#define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_LSB (8)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_LSB (0)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_LSB (22)
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_LSB (21)
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_LSB (20)
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_LSB (13)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_LSB (12)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_LSB (8)
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_LSB (4)
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_LSB (0)
+#define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_WIDTH (4)
+#define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_LSB (8)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_LSB (0)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_LSB (22)
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_LSB (21)
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_LSB (20)
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_LSB (13)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_LSB (12)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_LSB (8)
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_LSB (4)
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_LSB (0)
+#define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_WIDTH (4)
+#define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_LSB (8)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_LSB (0)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_LSB (16)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_LSB (0)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_LSB (16)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_LSB (0)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_LSB (31)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_LSB (28)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_LSB (0)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_LSB (31)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_LSB (30)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_LSB (28)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_LSB (31)
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_LSB (8)
+#define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_WIDTH (7)
+#define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_LSB (0)
+#define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_WIDTH (8)
+#define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_MASK (0x000000FF)
+
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_LSB (16)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_LSB (0)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_LSB (16)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_LSB (0)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_LSB (31)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_LSB (28)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_LSB (0)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_LSB (31)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_LSB (30)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_LSB (28)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_LSB (31)
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_LSB (8)
+#define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_WIDTH (7)
+#define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_LSB (0)
+#define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_WIDTH (8)
+#define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_MASK (0x000000FF)
+
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_LSB (16)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_LSB (0)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_LSB (16)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_LSB (0)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_LSB (31)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_LSB (28)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_LSB (0)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_LSB (31)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_LSB (30)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_LSB (28)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_LSB (31)
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_LSB (8)
+#define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_WIDTH (7)
+#define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_LSB (0)
+#define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_WIDTH (8)
+#define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_MASK (0x000000FF)
+
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_LSB (16)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_LSB (0)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_LSB (16)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_LSB (0)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_LSB (31)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_LSB (28)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_LSB (0)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_LSB (31)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_LSB (30)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_LSB (28)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_LSB (31)
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_LSB (8)
+#define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_WIDTH (7)
+#define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_LSB (0)
+#define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_WIDTH (8)
+#define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_MASK (0x000000FF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_MASK (0x00000007)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_MASK (0x00000007)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_MASK (0x00000007)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_MASK (0x00000007)
+
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_LSB (31)
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_MASK (0x80000000)
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_LSB (0)
+#define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_WIDTH (23)
+#define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_LSB (31)
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_MASK (0x80000000)
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_LSB (0)
+#define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_WIDTH (23)
+#define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_LSB (31)
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_MASK (0x80000000)
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_LSB (0)
+#define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_WIDTH (23)
+#define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_LSB (31)
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_MASK (0x80000000)
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_LSB (0)
+#define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_WIDTH (23)
+#define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_LSB (31)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_WIDTH (1)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_MASK (0x80000000)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_LSB (0)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_WIDTH (23)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_LSB (31)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_WIDTH (1)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_MASK (0x80000000)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_LSB (0)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_WIDTH (23)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_MASK (0x007FFFFF)
+
+
+#endif //#ifndef _CPH_C2K_RXDFE_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxdfefcimm.h b/mcu/interface/l1/cl1/common/HW/cphc2krxdfefcimm.h
new file mode 100644
index 0000000..2ca1c78
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxdfefcimm.h
@@ -0,0 +1,497 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RXDFE_FCIMM_H_
+#define _CPH_C2K_RXDFE_FCIMM_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE_FC_IMM_REG_BASE (0xA70C0000)
+
+#define RXDFE_FC_IMM_end (RXDFE_FC_IMM_REG_BASE + 0xFFFC + 1*4)
+
+
+
+#define RXDFE_FC_DATE ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8000))
+#define RXDFE_FC_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8004))
+#define RXDFE_FC_MIXED_IF_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8008))
+#define RXDFE_FC_TEST_IN_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x800C))
+#define RXDFE_FC_TEST_IN_STEP_SIZE ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8010))
+#define RXDFE_FC_TEST_IN_STEP_INIT ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8014))
+#define RXDFE_FC_TEST_IN_CON_IQ ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8018))
+#define RXDFE_FC_TEST_IN_DC ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x801C))
+#define RXDFE_FC_TEST_MUQ_IN_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8020))
+#define RXDFE_FC_TEST_MUQ_IN_STEP ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8024))
+#define RXDFE_FC_TEST_MUQ_IN_DC ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8028))
+#define RXDFE_FC_TEST_OUT_CON ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x802C))
+#define RXDFE_FC_TEST_OUT_ALPHA ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8030))
+#define RXDFE_FC_TEST_FORCE_OFF ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8034))
+#define RXDFE_FC_SW_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8038))
+#define RXDFE_FC_SW_INI_TRG ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x803C))
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8040))
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8044))
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8048))
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x804C))
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8050))
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8054))
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8058))
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x805C))
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8060))
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8064))
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8068))
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x806C))
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8070))
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8074))
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8078))
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x807C))
+#define RXDFE_FC_MS_WB_LPF_0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8800))
+#define RXDFE_FC_MS_WB_LPF_1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x8804))
+#define RXDFE_FC_INFO_AGCIF_REG(n) ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9000 + (n)*4)) //n is from 0 to 63
+#define RXDFE_FC_INFO_TEST_OUT_DATA_0 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9400))
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1 ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9404))
+#define RXDFE_FC_INFO_CRC32_OUT ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9408))
+#define RXDFE_FC_INFO_ALPHA_OUT ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x940C))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9410))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9414))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9418))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x941C))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9420))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9424))
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9428))
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x942C))
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9430))
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0x9434))
+#define RXDFE_FC_FPGA ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0xF000))
+#define RXDFE_FC_RESERVED ((APBADDR32)(RXDFE_FC_IMM_REG_BASE + 0xFFFC))
+
+
+#define RXDFE_FC_DATE_RXDFE_FC_DATE_LSB (0)
+#define RXDFE_FC_DATE_RXDFE_FC_DATE_WIDTH (32)
+#define RXDFE_FC_DATE_RXDFE_FC_DATE_MASK (0xFFFFFFFF)
+
+#define RXDFE_FC_CON_CONFIG_SRC_SEL_LSB (0)
+#define RXDFE_FC_CON_CONFIG_SRC_SEL_WIDTH (1)
+#define RXDFE_FC_CON_CONFIG_SRC_SEL_MASK (0x00000001)
+#define RXDFE_FC_CON_CONFIG_SRC_SEL_BIT (0x00000001)
+
+#define RXDFE_FC_MIXED_IF_CON_MIXED_IF_RPTR_INI_LSB (0)
+#define RXDFE_FC_MIXED_IF_CON_MIXED_IF_RPTR_INI_WIDTH (3)
+#define RXDFE_FC_MIXED_IF_CON_MIXED_IF_RPTR_INI_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_LSB (31)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_WIDTH (1)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_MASK (0x80000000)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_EN_BIT (0x80000000)
+
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_WIN_LSB (8)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_WIN_WIDTH (4)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_WIN_MASK (0x00000F00)
+
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_RATE_LSB (4)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_RATE_WIDTH (4)
+#define RXDFE_FC_TEST_IN_CON_TEST_IN_RATE_MASK (0x000000F0)
+
+#define RXDFE_FC_TEST_IN_CON_TEST_P_IN_EN_LSB (0)
+#define RXDFE_FC_TEST_IN_CON_TEST_P_IN_EN_WIDTH (2)
+#define RXDFE_FC_TEST_IN_CON_TEST_P_IN_EN_MASK (0x00000003)
+
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_Q_STEP_SIZE_LSB (16)
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_Q_STEP_SIZE_WIDTH (10)
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_Q_STEP_SIZE_MASK (0x03FF0000)
+
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_I_STEP_SIZE_LSB (0)
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_I_STEP_SIZE_WIDTH (10)
+#define RXDFE_FC_TEST_IN_STEP_SIZE_TEST_IN_I_STEP_SIZE_MASK (0x000003FF)
+
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_Q_STEP_INIT_LSB (16)
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_Q_STEP_INIT_WIDTH (10)
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_Q_STEP_INIT_MASK (0x03FF0000)
+
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_I_STEP_INIT_LSB (0)
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_I_STEP_INIT_WIDTH (10)
+#define RXDFE_FC_TEST_IN_STEP_INIT_TEST_IN_I_STEP_INIT_MASK (0x000003FF)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SCALE_LSB (24)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SCALE_WIDTH (4)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SCALE_MASK (0x0F000000)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_LSB (20)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_WIDTH (1)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_MASK (0x00100000)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_INV_BIT (0x00100000)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SEL_LSB (16)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SEL_WIDTH (2)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_Q_SEL_MASK (0x00030000)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SCALE_LSB (8)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SCALE_WIDTH (4)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SCALE_MASK (0x00000F00)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_LSB (4)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_WIDTH (1)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_MASK (0x00000010)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_INV_BIT (0x00000010)
+
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SEL_LSB (0)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SEL_WIDTH (2)
+#define RXDFE_FC_TEST_IN_CON_IQ_TEST_IN_I_SEL_MASK (0x00000003)
+
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_Q_DC_LSB (16)
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_Q_DC_WIDTH (15)
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_Q_DC_MASK (0x7FFF0000)
+
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_I_DC_LSB (0)
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_I_DC_WIDTH (15)
+#define RXDFE_FC_TEST_IN_DC_TEST_IN_I_DC_MASK (0x00007FFF)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_LSB (31)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_WIDTH (1)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_MASK (0x80000000)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_EN_BIT (0x80000000)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SCALE_LSB (24)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SCALE_WIDTH (4)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SCALE_MASK (0x0F000000)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_LSB (20)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_WIDTH (1)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_MASK (0x00100000)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_INV_BIT (0x00100000)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SEL_LSB (16)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SEL_WIDTH (2)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_SEL_MASK (0x00030000)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_WIN_LSB (8)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_WIN_WIDTH (4)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_WIN_MASK (0x00000F00)
+
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_RATE_LSB (4)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_RATE_WIDTH (4)
+#define RXDFE_FC_TEST_MUQ_IN_CON_TEST_MUQ_IN_RATE_MASK (0x000000F0)
+
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_SIZE_LSB (16)
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_SIZE_WIDTH (10)
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_SIZE_MASK (0x03FF0000)
+
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_INIT_LSB (0)
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_INIT_WIDTH (10)
+#define RXDFE_FC_TEST_MUQ_IN_STEP_TEST_MUQ_IN_STEP_INIT_MASK (0x000003FF)
+
+#define RXDFE_FC_TEST_MUQ_IN_DC_TEST_MUQ_IN_DC_LSB (0)
+#define RXDFE_FC_TEST_MUQ_IN_DC_TEST_MUQ_IN_DC_WIDTH (15)
+#define RXDFE_FC_TEST_MUQ_IN_DC_TEST_MUQ_IN_DC_MASK (0x00007FFF)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_LSB (31)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_WIDTH (1)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_MASK (0x80000000)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_EN_BIT (0x80000000)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_WIN_LSB (20)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_WIN_WIDTH (4)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_WIN_MASK (0x00F00000)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_RATE_LSB (16)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_RATE_WIDTH (4)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_RATE_MASK (0x000F0000)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_SEL_LSB (8)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_SEL_WIDTH (5)
+#define RXDFE_FC_TEST_OUT_CON_TEST_OUT_SEL_MASK (0x00001F00)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_C_OUT_SEL_LSB (4)
+#define RXDFE_FC_TEST_OUT_CON_TEST_C_OUT_SEL_WIDTH (4)
+#define RXDFE_FC_TEST_OUT_CON_TEST_C_OUT_SEL_MASK (0x000000F0)
+
+#define RXDFE_FC_TEST_OUT_CON_TEST_P_OUT_SEL_LSB (0)
+#define RXDFE_FC_TEST_OUT_CON_TEST_P_OUT_SEL_WIDTH (4)
+#define RXDFE_FC_TEST_OUT_CON_TEST_P_OUT_SEL_MASK (0x0000000F)
+
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_LSB (8)
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_WIDTH (1)
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_MASK (0x00000100)
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_ABS_BIT (0x00000100)
+
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_LSB (0)
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_WIDTH (3)
+#define RXDFE_FC_TEST_OUT_ALPHA_TEST_OUT_ALPHA_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_LSB (4)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_WIDTH (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_MASK (0x00000010)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_ANTI_DROOP_OFF_BIT (0x00000010)
+
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_LSB (3)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_WIDTH (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_MASK (0x00000008)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRC_OFF_BIT (0x00000008)
+
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_LSB (2)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_WIDTH (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_MASK (0x00000004)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_LWC_DAGC_OFF_BIT (0x00000004)
+
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_LSB (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_WIDTH (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_MASK (0x00000002)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_SRRC_PNAAF_OFF_BIT (0x00000002)
+
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_LSB (0)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_WIDTH (1)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_MASK (0x00000001)
+#define RXDFE_FC_TEST_FORCE_OFF_TEST_L_POSTNCO_CIC_OFF_BIT (0x00000001)
+
+#define RXDFE_FC_SW_WIN_SW_WIN_EN_LSB (31)
+#define RXDFE_FC_SW_WIN_SW_WIN_EN_WIDTH (1)
+#define RXDFE_FC_SW_WIN_SW_WIN_EN_MASK (0x80000000)
+#define RXDFE_FC_SW_WIN_SW_WIN_EN_BIT (0x80000000)
+
+#define RXDFE_FC_SW_WIN_SW_CS_WIN_LSB (16)
+#define RXDFE_FC_SW_WIN_SW_CS_WIN_WIDTH (4)
+#define RXDFE_FC_SW_WIN_SW_CS_WIN_MASK (0x000F0000)
+
+#define RXDFE_FC_SW_WIN_SW_NCO_WIN_LSB (12)
+#define RXDFE_FC_SW_WIN_SW_NCO_WIN_WIDTH (4)
+#define RXDFE_FC_SW_WIN_SW_NCO_WIN_MASK (0x0000F000)
+
+#define RXDFE_FC_SW_WIN_SW_C_WIN_LSB (8)
+#define RXDFE_FC_SW_WIN_SW_C_WIN_WIDTH (4)
+#define RXDFE_FC_SW_WIN_SW_C_WIN_MASK (0x00000F00)
+
+#define RXDFE_FC_SW_WIN_SW_P_WIN_LSB (4)
+#define RXDFE_FC_SW_WIN_SW_P_WIN_WIDTH (4)
+#define RXDFE_FC_SW_WIN_SW_P_WIN_MASK (0x000000F0)
+
+#define RXDFE_FC_SW_WIN_SW_ADC_WIN_LSB (0)
+#define RXDFE_FC_SW_WIN_SW_ADC_WIN_WIDTH (4)
+#define RXDFE_FC_SW_WIN_SW_ADC_WIN_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_LSB (31)
+#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_WIDTH (1)
+#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_MASK (0x80000000)
+#define RXDFE_FC_SW_INI_TRG_SW_INI_TRG_EN_BIT (0x80000000)
+
+#define RXDFE_FC_SW_INI_TRG_SW_C_INI_TRG_LSB (4)
+#define RXDFE_FC_SW_INI_TRG_SW_C_INI_TRG_WIDTH (4)
+#define RXDFE_FC_SW_INI_TRG_SW_C_INI_TRG_MASK (0x000000F0)
+
+#define RXDFE_FC_SW_INI_TRG_SW_P_INI_TRG_LSB (0)
+#define RXDFE_FC_SW_INI_TRG_SW_P_INI_TRG_WIDTH (4)
+#define RXDFE_FC_SW_INI_TRG_SW_P_INI_TRG_MASK (0x0000000F)
+
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0_NBIF_INI_SPUR_SEL_P0_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0_NBIF_INI_SPUR_SEL_P0_A0_WIDTH (3)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A0_NBIF_INI_SPUR_SEL_P0_A0_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0_NBIF_INI_ACCU_I_P0_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0_NBIF_INI_ACCU_I_P0_A0_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A0_NBIF_INI_ACCU_I_P0_A0_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0_NBIF_INI_ACCU_Q_P0_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0_NBIF_INI_ACCU_Q_P0_A0_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A0_NBIF_INI_ACCU_Q_P0_A0_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1_NBIF_INI_SPUR_SEL_P0_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1_NBIF_INI_SPUR_SEL_P0_A1_WIDTH (3)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P0_A1_NBIF_INI_SPUR_SEL_P0_A1_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1_NBIF_INI_ACCU_I_P0_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1_NBIF_INI_ACCU_I_P0_A1_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_I_P0_A1_NBIF_INI_ACCU_I_P0_A1_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1_NBIF_INI_ACCU_Q_P0_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1_NBIF_INI_ACCU_Q_P0_A1_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P0_A1_NBIF_INI_ACCU_Q_P0_A1_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0_NBIF_INI_SPUR_SEL_P1_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0_NBIF_INI_SPUR_SEL_P1_A0_WIDTH (3)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A0_NBIF_INI_SPUR_SEL_P1_A0_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0_NBIF_INI_ACCU_I_P1_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0_NBIF_INI_ACCU_I_P1_A0_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A0_NBIF_INI_ACCU_I_P1_A0_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0_NBIF_INI_ACCU_Q_P1_A0_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0_NBIF_INI_ACCU_Q_P1_A0_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A0_NBIF_INI_ACCU_Q_P1_A0_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1_NBIF_INI_SPUR_SEL_P1_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1_NBIF_INI_SPUR_SEL_P1_A1_WIDTH (3)
+#define RXDFE_FC_TEST_NBIF_INI_SEL_P1_A1_NBIF_INI_SPUR_SEL_P1_A1_MASK (0x00000007)
+
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1_NBIF_INI_ACCU_I_P1_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1_NBIF_INI_ACCU_I_P1_A1_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_I_P1_A1_NBIF_INI_ACCU_I_P1_A1_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1_NBIF_INI_ACCU_Q_P1_A1_LSB (0)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1_NBIF_INI_ACCU_Q_P1_A1_WIDTH (17)
+#define RXDFE_FC_TEST_NBIF_INI_Q_P1_A1_NBIF_INI_ACCU_Q_P1_A1_MASK (0x0001FFFF)
+
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0_NCO_INI_ACCU_PH_C0_A0_LSB (0)
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0_NCO_INI_ACCU_PH_C0_A0_WIDTH (23)
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A0_NCO_INI_ACCU_PH_C0_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1_NCO_INI_ACCU_PH_C0_A1_LSB (0)
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1_NCO_INI_ACCU_PH_C0_A1_WIDTH (23)
+#define RXDFE_FC_TEST_NCO_INI_PH_C0_A1_NCO_INI_ACCU_PH_C0_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0_NCO_INI_ACCU_PH_C1_A0_LSB (0)
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0_NCO_INI_ACCU_PH_C1_A0_WIDTH (23)
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A0_NCO_INI_ACCU_PH_C1_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1_NCO_INI_ACCU_PH_C1_A1_LSB (0)
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1_NCO_INI_ACCU_PH_C1_A1_WIDTH (23)
+#define RXDFE_FC_TEST_NCO_INI_PH_C1_A1_NCO_INI_ACCU_PH_C1_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_3_LSB (24)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_3_WIDTH (7)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_3_MASK (0x7F000000)
+
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_2_LSB (16)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_2_WIDTH (7)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_2_MASK (0x007F0000)
+
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_1_LSB (8)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_1_WIDTH (7)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_1_MASK (0x00007F00)
+
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_0_LSB (0)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_0_WIDTH (7)
+#define RXDFE_FC_MS_WB_LPF_0_WB_COEF_LPF_0_MASK (0x0000007F)
+
+#define RXDFE_FC_MS_WB_LPF_1_WB_COEF_LPF_4_LSB (0)
+#define RXDFE_FC_MS_WB_LPF_1_WB_COEF_LPF_4_WIDTH (7)
+#define RXDFE_FC_MS_WB_LPF_1_WB_COEF_LPF_4_MASK (0x0000007F)
+
+#define RXDFE_FC_INFO_AGCIF_REG_INFO_AGCIF_REG_LSB (0)
+#define RXDFE_FC_INFO_AGCIF_REG_INFO_AGCIF_REG_WIDTH (32)
+#define RXDFE_FC_INFO_AGCIF_REG_INFO_AGCIF_REG_MASK (0xFFFFFFFF)
+
+#define RXDFE_FC_INFO_TEST_OUT_DATA_0_INFO_TEST_OUT_DATA_LSB (0)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_0_INFO_TEST_OUT_DATA_WIDTH (32)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_0_INFO_TEST_OUT_DATA_MASK (0xFFFFFFFF)
+
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_Q_LSB (16)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_Q_WIDTH (15)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_Q_MASK (0x7FFF0000)
+
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_I_LSB (0)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_I_WIDTH (15)
+#define RXDFE_FC_INFO_TEST_OUT_DATA_1_INFO_TEST_OUT_DATA_I_MASK (0x00007FFF)
+
+#define RXDFE_FC_INFO_CRC32_OUT_INFO_CRC32_OUT_LSB (0)
+#define RXDFE_FC_INFO_CRC32_OUT_INFO_CRC32_OUT_WIDTH (32)
+#define RXDFE_FC_INFO_CRC32_OUT_INFO_CRC32_OUT_MASK (0xFFFFFFFF)
+
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_Q_LSB (16)
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_Q_WIDTH (15)
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_Q_MASK (0x7FFF0000)
+
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_I_LSB (0)
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_I_WIDTH (15)
+#define RXDFE_FC_INFO_ALPHA_OUT_INFO_ALPHA_OUT_I_MASK (0x00007FFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN_INFO_EDGE_COUNT_FC_ADC_WIN_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN_INFO_EDGE_COUNT_FC_ADC_WIN_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_ADC_WIN_INFO_EDGE_COUNT_FC_ADC_WIN_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN_INFO_EDGE_COUNT_FC_P_WIN_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN_INFO_EDGE_COUNT_FC_P_WIN_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_WIN_INFO_EDGE_COUNT_FC_P_WIN_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN_INFO_EDGE_COUNT_FC_C_WIN_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN_INFO_EDGE_COUNT_FC_C_WIN_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_WIN_INFO_EDGE_COUNT_FC_C_WIN_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN_INFO_EDGE_COUNT_FC_NCO_WIN_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN_INFO_EDGE_COUNT_FC_NCO_WIN_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_NCO_WIN_INFO_EDGE_COUNT_FC_NCO_WIN_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN_INFO_EDGE_COUNT_FC_CS_WIN_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN_INFO_EDGE_COUNT_FC_CS_WIN_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_CS_WIN_INFO_EDGE_COUNT_FC_CS_WIN_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG_INFO_EDGE_COUNT_FC_P_INI_TRG_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG_INFO_EDGE_COUNT_FC_P_INI_TRG_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_P_INI_TRG_INFO_EDGE_COUNT_FC_P_INI_TRG_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG_INFO_EDGE_COUNT_FC_C_INI_TRG_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG_INFO_EDGE_COUNT_FC_C_INI_TRG_WIDTH (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_FC_C_INI_TRG_INFO_EDGE_COUNT_FC_C_INI_TRG_MASK (0x0000FFFF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_AGCDC_FC_REQ_LSB (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_AGCDC_FC_REQ_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_AGCDC_FC_REQ_MASK (0x0000FF00)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_CQ_CONFIG_VLD_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_CQ_CONFIG_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_RXDFE_INFO_EDGE_COUNT_CQ_CONFIG_VLD_MASK (0x000000FF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_TTIMER_MUQ_VLD_LSB (16)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_TTIMER_MUQ_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_TTIMER_MUQ_VLD_MASK (0x00FF0000)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_WTIMER_MUQ_VLD_LSB (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_WTIMER_MUQ_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_WTIMER_MUQ_VLD_MASK (0x0000FF00)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_LTIMER_PRE_S_VLD_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_LTIMER_PRE_S_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_LWT_TIMER_INFO_EDGE_COUNT_LTIMER_PRE_S_VLD_MASK (0x000000FF)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_CDOTIMER_MUQ_VLD_LSB (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_CDOTIMER_MUQ_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_CDOTIMER_MUQ_VLD_MASK (0x0000FF00)
+
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_C1XTIMER_MUQ_VLD_LSB (0)
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_C1XTIMER_MUQ_VLD_WIDTH (8)
+#define RXDFE_FC_INFO_EDGE_COUNT_C_TIMER_INFO_EDGE_COUNT_C1XTIMER_MUQ_VLD_MASK (0x000000FF)
+
+#define RXDFE_FC_FPGA_FPGA_CTRL_LSB (0)
+#define RXDFE_FC_FPGA_FPGA_CTRL_WIDTH (32)
+#define RXDFE_FC_FPGA_FPGA_CTRL_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _CPH_C2K_RXDFE_FCIMM_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphcstopreg.h b/mcu/interface/l1/cl1/common/HW/cphcstopreg.h
new file mode 100644
index 0000000..b439591
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphcstopreg.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphcstopreg_93.h"
+#elif defined(__MD95__)
+#include "cphcstopreg_95.h"
+#else
+#include "cphcstopreg_97.h"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphcstopreg_93.h b/mcu/interface/l1/cl1/common/HW/cphcstopreg_93.h
new file mode 100644
index 0000000..78683ac
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphcstopreg_93.h
@@ -0,0 +1,242 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_CSTOP_REG_H_
+#define _CPH_CSTOP_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_TOP_REG_REG_BASE (0xA7800000)
+
+#define CS_TOP_REG_end (CS_TOP_REG_REG_BASE + 0x0048 + 1*4)
+
+
+
+#define CS_C1X_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0000))
+#define CS_CDO_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0004))
+#define CS_WT_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0008))
+#define CS_L_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x000c))
+#define CS_C1X_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0010))
+#define CS_CDO_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0014))
+#define CS_WT_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0018))
+#define CS_L_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x001c))
+#define CS_DFE_PHASE_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0020))
+#define CS_C1X_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0024))
+#define CS_CDO_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0028))
+#define CS_MEM_SHARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x002c))
+#define CS_MEM_STATUS ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0030))
+#define CS_PWR_AWARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0034))
+#define CS_SYS_CK_IDLE_DIV_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0038))
+#define CS_SYS_CK_IDLE_DBG_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x003c))
+#define CS_TEST_BUS_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0040))
+#define CS_RESERVED0 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0044))
+#define CS_RESERVED1 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0048))
+
+/*
+ Merlot SRAM change DELSEL claim to add
+*/
+#if defined(__MTK_TARGET__) && defined(MT6761)
+
+#define CS_CW_1X_RAM_BIST_1 ((APBADDR32)(0xA78201b0))
+#define CS_CW_1X_RAM_BIST_2 ((APBADDR32)(0xA78201b4))
+#define CS_CW_1X_RAM_NOSHARE_BIST_1 ((APBADDR32)(0xA78201c8))
+
+#endif
+
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_LSB (0)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_WIDTH (1)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_MASK (0x00000001)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_BIT (0x00000001)
+
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_LSB (0)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_WIDTH (1)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_MASK (0x00000001)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_BIT (0x00000001)
+
+#define CS_WT_CK_EN_wtcs_ck_div2_en_LSB (1)
+#define CS_WT_CK_EN_wtcs_ck_div2_en_WIDTH (1)
+#define CS_WT_CK_EN_wtcs_ck_div2_en_MASK (0x00000002)
+#define CS_WT_CK_EN_wtcs_ck_div2_en_BIT (0x00000002)
+
+#define CS_WT_CK_EN_wtcs_ck_en_LSB (0)
+#define CS_WT_CK_EN_wtcs_ck_en_WIDTH (1)
+#define CS_WT_CK_EN_wtcs_ck_en_MASK (0x00000001)
+#define CS_WT_CK_EN_wtcs_ck_en_BIT (0x00000001)
+
+#define CS_L_CK_EN_lcs_ck_en_LSB (0)
+#define CS_L_CK_EN_lcs_ck_en_WIDTH (1)
+#define CS_L_CK_EN_lcs_ck_en_MASK (0x00000001)
+#define CS_L_CK_EN_lcs_ck_en_BIT (0x00000001)
+
+#define CS_C1X_SW_RST_c1xcs_sw_rst_LSB (0)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_WIDTH (1)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_MASK (0x00000001)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_BIT (0x00000001)
+
+#define CS_CDO_SW_RST_cdocs_sw_rst_LSB (0)
+#define CS_CDO_SW_RST_cdocs_sw_rst_WIDTH (1)
+#define CS_CDO_SW_RST_cdocs_sw_rst_MASK (0x00000001)
+#define CS_CDO_SW_RST_cdocs_sw_rst_BIT (0x00000001)
+
+#define CS_WT_SW_RST_tcs_sw_rst_LSB (1)
+#define CS_WT_SW_RST_tcs_sw_rst_WIDTH (1)
+#define CS_WT_SW_RST_tcs_sw_rst_MASK (0x00000002)
+#define CS_WT_SW_RST_tcs_sw_rst_BIT (0x00000002)
+
+#define CS_WT_SW_RST_wcs_sw_rst_LSB (0)
+#define CS_WT_SW_RST_wcs_sw_rst_WIDTH (1)
+#define CS_WT_SW_RST_wcs_sw_rst_MASK (0x00000001)
+#define CS_WT_SW_RST_wcs_sw_rst_BIT (0x00000001)
+
+#define CS_L_SW_RST_lcs_sw_rst_LSB (0)
+#define CS_L_SW_RST_lcs_sw_rst_WIDTH (1)
+#define CS_L_SW_RST_lcs_sw_rst_MASK (0x00000001)
+#define CS_L_SW_RST_lcs_sw_rst_BIT (0x00000001)
+
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_LSB (0)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_WIDTH (2)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_MASK (0x00000003)
+
+#define CS_C1X_CFG_c1xcs_data_frac_scale_LSB (6)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_WIDTH (4)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_MASK (0x000003C0)
+
+#define CS_C1X_CFG_c1xcs_data_rc_sel_LSB (3)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_WIDTH (3)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_MASK (0x00000038)
+
+#define CS_C1X_CFG_c1xcs_iq_swap_LSB (2)
+#define CS_C1X_CFG_c1xcs_iq_swap_WIDTH (1)
+#define CS_C1X_CFG_c1xcs_iq_swap_MASK (0x00000004)
+#define CS_C1X_CFG_c1xcs_iq_swap_BIT (0x00000004)
+
+#define CS_C1X_CFG_c1xcs_input_sel_LSB (0)
+#define CS_C1X_CFG_c1xcs_input_sel_WIDTH (2)
+#define CS_C1X_CFG_c1xcs_input_sel_MASK (0x00000003)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_LSB (14)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_MASK (0x0003C000)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_LSB (12)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_MASK (0x00003000)
+
+#define CS_CDO_CFG_cdocs_iq_swap_div_LSB (11)
+#define CS_CDO_CFG_cdocs_iq_swap_div_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_div_MASK (0x00000800)
+#define CS_CDO_CFG_cdocs_iq_swap_div_BIT (0x00000800)
+
+#define CS_CDO_CFG_cdocs_input_sel_div_LSB (9)
+#define CS_CDO_CFG_cdocs_input_sel_div_WIDTH (2)
+#define CS_CDO_CFG_cdocs_input_sel_div_MASK (0x00000600)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_LSB (5)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_MASK (0x000001E0)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_LSB (3)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_MASK (0x00000018)
+
+#define CS_CDO_CFG_cdocs_iq_swap_main_LSB (2)
+#define CS_CDO_CFG_cdocs_iq_swap_main_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_main_MASK (0x00000004)
+#define CS_CDO_CFG_cdocs_iq_swap_main_BIT (0x00000004)
+
+#define CS_CDO_CFG_cdocs_input_sel_main_LSB (0)
+#define CS_CDO_CFG_cdocs_input_sel_main_WIDTH (2)
+#define CS_CDO_CFG_cdocs_input_sel_main_MASK (0x00000003)
+
+#define CS_MEM_SHARE_cs_c1x_mem_share_LSB (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_WIDTH (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_MASK (0x00000002)
+#define CS_MEM_SHARE_cs_c1x_mem_share_BIT (0x00000002)
+
+#define CS_MEM_SHARE_cs_wc_mem_mode_LSB (0)
+#define CS_MEM_SHARE_cs_wc_mem_mode_WIDTH (1)
+#define CS_MEM_SHARE_cs_wc_mem_mode_MASK (0x00000001)
+#define CS_MEM_SHARE_cs_wc_mem_mode_BIT (0x00000001)
+
+#define CS_MEM_STATUS_cs_mem_status_LSB (0)
+#define CS_MEM_STATUS_cs_mem_status_WIDTH (2)
+#define CS_MEM_STATUS_cs_mem_status_MASK (0x00000003)
+
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_LSB (2)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_MASK (0x00000004)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_BIT (0x00000004)
+
+#define CS_PWR_AWARE_cs_dcm_idle_en_LSB (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_MASK (0x00000002)
+#define CS_PWR_AWARE_cs_dcm_idle_en_BIT (0x00000002)
+
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_LSB (0)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_MASK (0x00000001)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_BIT (0x00000001)
+
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_MASK (0x0000001F)
+
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_MASK (0x0000001F)
+
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_LSB (0)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_WIDTH (3)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_MASK (0x00000007)
+
+#define CS_RESERVED0_cs_rsv0_LSB (0)
+#define CS_RESERVED0_cs_rsv0_WIDTH (32)
+#define CS_RESERVED0_cs_rsv0_MASK (0xFFFFFFFF)
+
+#define CS_RESERVED1_cs_rsv1_LSB (0)
+#define CS_RESERVED1_cs_rsv1_WIDTH (32)
+#define CS_RESERVED1_cs_rsv1_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _EL1D_REG_ELBRUS_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphcstopreg_95.h b/mcu/interface/l1/cl1/common/HW/cphcstopreg_95.h
new file mode 100644
index 0000000..aad6f3e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphcstopreg_95.h
@@ -0,0 +1,252 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_CSTOP_REG_H_
+#define _CPH_CSTOP_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_TOP_REG_REG_BASE (0xA7800000)
+
+#define CS_TOP_REG_end (CS_TOP_REG_REG_BASE + 0x0048 + 1*4)
+
+
+
+#define CS_C1X_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0000))
+#define CS_CDO_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0004))
+#define CS_WT_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0008))
+#define CS_L_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x000c))
+#define CS_C1X_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0010))
+#define CS_CDO_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0014))
+#define CS_WT_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0018))
+#define CS_L_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x001c))
+#define CS_DFE_PHASE_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0020))
+#define CS_C1X_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0024))
+#define CS_CDO_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0028))
+#define CS_MEM_SHARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x002c))
+#define CS_MEM_STATUS ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0030))
+#define CS_PWR_AWARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0034))
+#define CS_SYS_CK_IDLE_DIV_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0038))
+#define CS_SYS_CK_IDLE_DBG_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x003c))
+#define CS_TEST_BUS_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0040))
+#define CS_RESERVED0 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0044))
+#define CS_RESERVED1 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0048))
+
+
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_LSB (0)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_WIDTH (1)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_MASK (0x00000001)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_BIT (0x00000001)
+
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_LSB (0)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_WIDTH (1)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_MASK (0x00000001)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_BIT (0x00000001)
+
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_LSB (3)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_WIDTH (1)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_MASK (0x00000008)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_BIT (0x00000008)
+#define CS_WT_CK_EN_TCS_CK_EN_LSB (2)
+#define CS_WT_CK_EN_TCS_CK_EN_WIDTH (1)
+#define CS_WT_CK_EN_TCS_CK_EN_MASK (0x00000004)
+#define CS_WT_CK_EN_TCS_CK_EN_BIT (0x00000004)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_LSB (1)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_WIDTH (1)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_MASK (0x00000002)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_BIT (0x00000002)
+
+#define CS_WT_CK_EN_WCS_CK_EN_LSB (0)
+#define CS_WT_CK_EN_WCS_CK_EN_WIDTH (1)
+#define CS_WT_CK_EN_WCS_CK_EN_MASK (0x00000001)
+#define CS_WT_CK_EN_WCS_CK_EN_BIT (0x00000001)
+
+#define CS_L_CK_EN_LCS_CK_EN_LSB (0)
+#define CS_L_CK_EN_LCS_CK_EN_WIDTH (1)
+#define CS_L_CK_EN_LCS_CK_EN_MASK (0x00000001)
+#define CS_L_CK_EN_LCS_CK_EN_BIT (0x00000001)
+
+#define CS_C1X_SW_RST_c1xcs_sw_rst_LSB (0)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_WIDTH (1)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_MASK (0x00000001)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_BIT (0x00000001)
+
+#define CS_CDO_SW_RST_cdocs_sw_rst_LSB (0)
+#define CS_CDO_SW_RST_cdocs_sw_rst_WIDTH (1)
+#define CS_CDO_SW_RST_cdocs_sw_rst_MASK (0x00000001)
+#define CS_CDO_SW_RST_cdocs_sw_rst_BIT (0x00000001)
+
+#define CS_WT_SW_RST_TCS_SW_RST_LSB (1)
+#define CS_WT_SW_RST_TCS_SW_RST_WIDTH (1)
+#define CS_WT_SW_RST_TCS_SW_RST_MASK (0x00000002)
+#define CS_WT_SW_RST_TCS_SW_RST_BIT (0x00000002)
+
+#define CS_WT_SW_RST_WCS_SW_RST_LSB (0)
+#define CS_WT_SW_RST_WCS_SW_RST_WIDTH (1)
+#define CS_WT_SW_RST_WCS_SW_RST_MASK (0x00000001)
+#define CS_WT_SW_RST_WCS_SW_RST_BIT (0x00000001)
+
+#define CS_L_SW_RST_LCS_SW_RST_LSB (0)
+#define CS_L_SW_RST_LCS_SW_RST_WIDTH (1)
+#define CS_L_SW_RST_LCS_SW_RST_MASK (0x00000001)
+#define CS_L_SW_RST_LCS_SW_RST_BIT (0x00000001)
+
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_LSB (0)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_WIDTH (2)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_MASK (0x00000003)
+
+#define CS_C1X_CFG_c1xcs_data_frac_scale_LSB (8)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_WIDTH (4)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_MASK (0x00000F00)
+
+#define CS_C1X_CFG_c1xcs_data_rc_sel_LSB (5)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_WIDTH (3)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_MASK (0x000000E0)
+
+#define CS_C1X_CFG_c1xcs_iq_swap_LSB (4)
+#define CS_C1X_CFG_c1xcs_iq_swap_WIDTH (1)
+#define CS_C1X_CFG_c1xcs_iq_swap_MASK (0x00000010)
+#define CS_C1X_CFG_c1xcs_iq_swap_BIT (0x00000010)
+
+#define CS_C1X_CFG_c1xcs_input_sel_LSB (0)
+#define CS_C1X_CFG_c1xcs_input_sel_WIDTH (4)
+#define CS_C1X_CFG_c1xcs_input_sel_MASK (0x0000000F)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_LSB (18)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_MASK (0x003C0000)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_LSB (16)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_MASK (0x00030000)
+
+#define CS_CDO_CFG_cdocs_iq_swap_div_LSB (15)
+#define CS_CDO_CFG_cdocs_iq_swap_div_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_div_MASK (0x00008000)
+#define CS_CDO_CFG_cdocs_iq_swap_div_BIT (0x00008000)
+
+#define CS_CDO_CFG_cdocs_input_sel_div_LSB (11)
+#define CS_CDO_CFG_cdocs_input_sel_div_WIDTH (4)
+#define CS_CDO_CFG_cdocs_input_sel_div_MASK (0x00007800)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_LSB (7)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_MASK (0x00000780)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_LSB (5)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_MASK (0x00000060)
+
+#define CS_CDO_CFG_cdocs_iq_swap_main_LSB (4)
+#define CS_CDO_CFG_cdocs_iq_swap_main_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_main_MASK (0x00000010)
+#define CS_CDO_CFG_cdocs_iq_swap_main_BIT (0x00000010)
+
+#define CS_CDO_CFG_cdocs_input_sel_main_LSB (0)
+#define CS_CDO_CFG_cdocs_input_sel_main_WIDTH (4)
+#define CS_CDO_CFG_cdocs_input_sel_main_MASK (0x0000000F)
+
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_LSB (3)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_WIDTH (1)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_MASK (0x00000008)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_BIT (0x00000008)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_LSB (2)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_WIDTH (1)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_MASK (0x00000004)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_BIT (0x00000004)
+#define CS_MEM_SHARE_cs_c1x_mem_share_LSB (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_WIDTH (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_MASK (0x00000002)
+#define CS_MEM_SHARE_cs_c1x_mem_share_BIT (0x00000002)
+
+#define CS_MEM_SHARE_cs_wc_mem_mode_LSB (0)
+#define CS_MEM_SHARE_cs_wc_mem_mode_WIDTH (1)
+#define CS_MEM_SHARE_cs_wc_mem_mode_MASK (0x00000001)
+#define CS_MEM_SHARE_cs_wc_mem_mode_BIT (0x00000001)
+
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_LSB (2)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_WIDTH (1)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_MASK (0x00000004)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_BIT (0x00000004)
+#define CS_MEM_STATUS_cs_mem_status_LSB (0)
+#define CS_MEM_STATUS_cs_mem_status_WIDTH (2)
+#define CS_MEM_STATUS_cs_mem_status_MASK (0x00000003)
+
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_LSB (2)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_MASK (0x00000004)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_BIT (0x00000004)
+
+#define CS_PWR_AWARE_cs_dcm_idle_en_LSB (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_MASK (0x00000002)
+#define CS_PWR_AWARE_cs_dcm_idle_en_BIT (0x00000002)
+
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_LSB (0)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_MASK (0x00000001)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_BIT (0x00000001)
+
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_MASK (0x0000001F)
+
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_MASK (0x0000001F)
+
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_LSB (0)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_WIDTH (3)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_MASK (0x00000007)
+
+#define CS_RESERVED0_cs_rsv0_LSB (0)
+#define CS_RESERVED0_cs_rsv0_WIDTH (32)
+#define CS_RESERVED0_cs_rsv0_MASK (0xFFFFFFFF)
+
+#define CS_RESERVED1_cs_rsv1_LSB (0)
+#define CS_RESERVED1_cs_rsv1_WIDTH (32)
+#define CS_RESERVED1_cs_rsv1_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _EL1D_REG_ELBRUS_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphcstopreg_97.h b/mcu/interface/l1/cl1/common/HW/cphcstopreg_97.h
new file mode 100644
index 0000000..5e8bf0b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphcstopreg_97.h
@@ -0,0 +1,312 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_CSTOP_REG_97_H_
+#define _CPH_CSTOP_REG_97_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_TOP_REG_REG_BASE (0xA9800000)
+
+#define CS_TOP_REG_end (CS_TOP_REG_REG_BASE + 0x0060 + 1*4)
+
+
+
+#define CS_C1X_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0000))
+#define CS_CDO_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0004))
+#define CS_WT_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0008))
+#define CS_L_CK_EN ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x000c))
+#define CS_C1X_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0010))
+#define CS_CDO_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0014))
+#define CS_WT_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0018))
+#define CS_L_SW_RST ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x001c))
+#define CS_DFE_PHASE_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0020))
+#define CS_C1X_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0024))
+#define CS_CDO_CFG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0028))
+#define CS_MEM_SHARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x002c))
+#define CS_MEM_STATUS ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0030))
+#define CS_PWR_AWARE ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0034))
+#define CS_SYS_CK_IDLE_DIV_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0038))
+#define CS_SYS_CK_IDLE_DBG_MASK ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x003c))
+#define CS_TEST_BUS_SEL ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0040))
+#define CS_RESERVED0 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0044))
+#define CS_RESERVED1 ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0048))
+#define CS_ST_SYS_CNT_C1X_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x004c))
+#define CS_ST_SYS_CNT_CDO_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0050))
+#define CS_RXDFE_FC_OUT_IQ_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0054))
+#define CS_INPUT_SEL_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0058))
+#define CS_CW_MODE_SEL_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x005c))
+#define CS_DDR_EN_DBG ((APBADDR32)(CS_TOP_REG_REG_BASE + 0x0060))
+
+
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_LSB (0)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_WIDTH (1)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_MASK (0x00000001)
+#define CS_C1X_CK_EN_c1xcs_ck_div2_en_BIT (0x00000001)
+
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_LSB (0)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_WIDTH (1)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_MASK (0x00000001)
+#define CS_CDO_CK_EN_cdocs_ck_div2_en_BIT (0x00000001)
+
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_LSB (3)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_WIDTH (1)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_MASK (0x00000008)
+#define CS_WT_CK_EN_TCS_CK_DIV2_EN_BIT (0x00000008)
+
+#define CS_WT_CK_EN_TCS_CK_EN_LSB (2)
+#define CS_WT_CK_EN_TCS_CK_EN_WIDTH (1)
+#define CS_WT_CK_EN_TCS_CK_EN_MASK (0x00000004)
+#define CS_WT_CK_EN_TCS_CK_EN_BIT (0x00000004)
+
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_LSB (1)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_WIDTH (1)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_MASK (0x00000002)
+#define CS_WT_CK_EN_WCS_CK_DIV2_EN_BIT (0x00000002)
+
+#define CS_WT_CK_EN_WCS_CK_EN_LSB (0)
+#define CS_WT_CK_EN_WCS_CK_EN_WIDTH (1)
+#define CS_WT_CK_EN_WCS_CK_EN_MASK (0x00000001)
+#define CS_WT_CK_EN_WCS_CK_EN_BIT (0x00000001)
+
+#define CS_L_CK_EN_LCS_CK_EN_LSB (0)
+#define CS_L_CK_EN_LCS_CK_EN_WIDTH (1)
+#define CS_L_CK_EN_LCS_CK_EN_MASK (0x00000001)
+#define CS_L_CK_EN_LCS_CK_EN_BIT (0x00000001)
+
+#define CS_C1X_SW_RST_c1xcs_sw_rst_LSB (0)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_WIDTH (1)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_MASK (0x00000001)
+#define CS_C1X_SW_RST_c1xcs_sw_rst_BIT (0x00000001)
+
+#define CS_CDO_SW_RST_cdocs_sw_rst_LSB (0)
+#define CS_CDO_SW_RST_cdocs_sw_rst_WIDTH (1)
+#define CS_CDO_SW_RST_cdocs_sw_rst_MASK (0x00000001)
+#define CS_CDO_SW_RST_cdocs_sw_rst_BIT (0x00000001)
+
+#define CS_WT_SW_RST_TCS_SW_RST_LSB (1)
+#define CS_WT_SW_RST_TCS_SW_RST_WIDTH (1)
+#define CS_WT_SW_RST_TCS_SW_RST_MASK (0x00000002)
+#define CS_WT_SW_RST_TCS_SW_RST_BIT (0x00000002)
+
+#define CS_WT_SW_RST_WCS_SW_RST_LSB (0)
+#define CS_WT_SW_RST_WCS_SW_RST_WIDTH (1)
+#define CS_WT_SW_RST_WCS_SW_RST_MASK (0x00000001)
+#define CS_WT_SW_RST_WCS_SW_RST_BIT (0x00000001)
+
+#define CS_L_SW_RST_LCS_SW_RST_LSB (0)
+#define CS_L_SW_RST_LCS_SW_RST_WIDTH (1)
+#define CS_L_SW_RST_LCS_SW_RST_MASK (0x00000001)
+#define CS_L_SW_RST_LCS_SW_RST_BIT (0x00000001)
+
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_LSB (0)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_WIDTH (2)
+#define CS_DFE_PHASE_SEL_cs_dfe_phase_sel_MASK (0x00000003)
+
+#define CS_C1X_CFG_c1xcs_data_frac_scale_LSB (8)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_WIDTH (4)
+#define CS_C1X_CFG_c1xcs_data_frac_scale_MASK (0x00000F00)
+
+#define CS_C1X_CFG_c1xcs_data_rc_sel_LSB (5)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_WIDTH (3)
+#define CS_C1X_CFG_c1xcs_data_rc_sel_MASK (0x000000E0)
+
+#define CS_C1X_CFG_c1xcs_iq_swap_LSB (4)
+#define CS_C1X_CFG_c1xcs_iq_swap_WIDTH (1)
+#define CS_C1X_CFG_c1xcs_iq_swap_MASK (0x00000010)
+#define CS_C1X_CFG_c1xcs_iq_swap_BIT (0x00000010)
+
+#define CS_C1X_CFG_c1xcs_input_sel_LSB (0)
+#define CS_C1X_CFG_c1xcs_input_sel_WIDTH (4)
+#define CS_C1X_CFG_c1xcs_input_sel_MASK (0x0000000F)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_LSB (18)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_div_MASK (0x003C0000)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_LSB (16)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_div_MASK (0x00030000)
+
+#define CS_CDO_CFG_cdocs_iq_swap_div_LSB (15)
+#define CS_CDO_CFG_cdocs_iq_swap_div_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_div_MASK (0x00008000)
+#define CS_CDO_CFG_cdocs_iq_swap_div_BIT (0x00008000)
+
+#define CS_CDO_CFG_cdocs_input_sel_div_LSB (11)
+#define CS_CDO_CFG_cdocs_input_sel_div_WIDTH (4)
+#define CS_CDO_CFG_cdocs_input_sel_div_MASK (0x00007800)
+
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_LSB (7)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_WIDTH (4)
+#define CS_CDO_CFG_cdocs_data_frac_scale_main_MASK (0x00000780)
+
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_LSB (5)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_WIDTH (2)
+#define CS_CDO_CFG_cdocs_data_rc_sel_main_MASK (0x00000060)
+
+#define CS_CDO_CFG_cdocs_iq_swap_main_LSB (4)
+#define CS_CDO_CFG_cdocs_iq_swap_main_WIDTH (1)
+#define CS_CDO_CFG_cdocs_iq_swap_main_MASK (0x00000010)
+#define CS_CDO_CFG_cdocs_iq_swap_main_BIT (0x00000010)
+
+#define CS_CDO_CFG_cdocs_input_sel_main_LSB (0)
+#define CS_CDO_CFG_cdocs_input_sel_main_WIDTH (4)
+#define CS_CDO_CFG_cdocs_input_sel_main_MASK (0x0000000F)
+
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_LSB (3)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_WIDTH (1)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_MASK (0x00000008)
+#define CS_MEM_SHARE_CS_MEM_CONFLICT_CLR_BIT (0x00000008)
+
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_LSB (2)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_WIDTH (1)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_MASK (0x00000004)
+#define CS_MEM_SHARE_CS_MEM_SW_MODE_BIT (0x00000004)
+
+#define CS_MEM_SHARE_cs_c1x_mem_share_LSB (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_WIDTH (1)
+#define CS_MEM_SHARE_cs_c1x_mem_share_MASK (0x00000002)
+#define CS_MEM_SHARE_cs_c1x_mem_share_BIT (0x00000002)
+
+#define CS_MEM_SHARE_cs_wc_mem_mode_LSB (0)
+#define CS_MEM_SHARE_cs_wc_mem_mode_WIDTH (1)
+#define CS_MEM_SHARE_cs_wc_mem_mode_MASK (0x00000001)
+#define CS_MEM_SHARE_cs_wc_mem_mode_BIT (0x00000001)
+
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_LSB (2)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_WIDTH (1)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_MASK (0x00000004)
+#define CS_MEM_STATUS_CS_MEM_CONFLICT_BIT (0x00000004)
+#define CS_MEM_STATUS_cs_mem_status_LSB (0)
+#define CS_MEM_STATUS_cs_mem_status_WIDTH (2)
+#define CS_MEM_STATUS_cs_mem_status_MASK (0x00000003)
+
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_LSB (2)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_MASK (0x00000004)
+#define CS_PWR_AWARE_wtcs_pwr_aware_en_BIT (0x00000004)
+
+#define CS_PWR_AWARE_cs_dcm_idle_en_LSB (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_dcm_idle_en_MASK (0x00000002)
+#define CS_PWR_AWARE_cs_dcm_idle_en_BIT (0x00000002)
+
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_LSB (0)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_WIDTH (1)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_MASK (0x00000001)
+#define CS_PWR_AWARE_cs_bus_pwr_aware_en_BIT (0x00000001)
+
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DIV_MASK_cs_sys_ck_idle_div_mask_MASK (0x0000001F)
+
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_LSB (0)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_WIDTH (5)
+#define CS_SYS_CK_IDLE_DBG_MASK_cs_sys_ck_idle_dbg_mask_MASK (0x0000001F)
+
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_LSB (0)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_WIDTH (3)
+#define CS_TEST_BUS_SEL_cs_test_bus_sel_MASK (0x00000007)
+
+#define CS_RESERVED0_cs_rsv0_LSB (0)
+#define CS_RESERVED0_cs_rsv0_WIDTH (32)
+#define CS_RESERVED0_cs_rsv0_MASK (0xFFFFFFFF)
+
+#define CS_RESERVED1_cs_rsv1_LSB (0)
+#define CS_RESERVED1_cs_rsv1_WIDTH (32)
+#define CS_RESERVED1_cs_rsv1_MASK (0xFFFFFFFF)
+
+#define CS_ST_SYS_CNT_C1X_DBG_C1XCS_DFE_TGL_DBG_LSB (20)
+#define CS_ST_SYS_CNT_C1X_DBG_C1XCS_DFE_TGL_DBG_WIDTH (1)
+#define CS_ST_SYS_CNT_C1X_DBG_C1XCS_DFE_TGL_DBG_MASK (0x00100000)
+#define CS_ST_SYS_CNT_C1X_DBG_C1XCS_DFE_TGL_DBG_BIT (0x00100000)
+
+#define CS_ST_SYS_CNT_C1X_DBG_ST_SYS_CNT_C1X_DBG_LSB (0)
+#define CS_ST_SYS_CNT_C1X_DBG_ST_SYS_CNT_C1X_DBG_WIDTH (20)
+#define CS_ST_SYS_CNT_C1X_DBG_ST_SYS_CNT_C1X_DBG_MASK (0x000FFFFF)
+
+#define CS_ST_SYS_CNT_CDO_DBG_CDOCS_DFE_TGL_DBG_LSB (20)
+#define CS_ST_SYS_CNT_CDO_DBG_CDOCS_DFE_TGL_DBG_WIDTH (1)
+#define CS_ST_SYS_CNT_CDO_DBG_CDOCS_DFE_TGL_DBG_MASK (0x00100000)
+#define CS_ST_SYS_CNT_CDO_DBG_CDOCS_DFE_TGL_DBG_BIT (0x00100000)
+
+#define CS_ST_SYS_CNT_CDO_DBG_ST_SYS_CNT_CDO_DBG_LSB (0)
+#define CS_ST_SYS_CNT_CDO_DBG_ST_SYS_CNT_CDO_DBG_WIDTH (20)
+#define CS_ST_SYS_CNT_CDO_DBG_ST_SYS_CNT_CDO_DBG_MASK (0x000FFFFF)
+
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_Q_DBG_LSB (16)
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_Q_DBG_WIDTH (15)
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_Q_DBG_MASK (0x7FFF0000)
+
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_I_DBG_LSB (0)
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_I_DBG_WIDTH (15)
+#define CS_RXDFE_FC_OUT_IQ_DBG_RXDFE_FC_OUT_I_DBG_MASK (0x00007FFF)
+
+#define CS_INPUT_SEL_DBG_INPUT_SEL_DBG_LSB (0)
+#define CS_INPUT_SEL_DBG_INPUT_SEL_DBG_WIDTH (4)
+#define CS_INPUT_SEL_DBG_INPUT_SEL_DBG_MASK (0x0000000F)
+
+#define CS_CW_MODE_SEL_DBG_CS_CW_MODE_SEL_DBG_LSB (0)
+#define CS_CW_MODE_SEL_DBG_CS_CW_MODE_SEL_DBG_WIDTH (1)
+#define CS_CW_MODE_SEL_DBG_CS_CW_MODE_SEL_DBG_MASK (0x00000001)
+#define CS_CW_MODE_SEL_DBG_CS_CW_MODE_SEL_DBG_BIT (0x00000001)
+
+#define CS_DDR_EN_DBG_MS3_DDR_CLOCK_ENA_DBG_LSB (2)
+#define CS_DDR_EN_DBG_MS3_DDR_CLOCK_ENA_DBG_WIDTH (1)
+#define CS_DDR_EN_DBG_MS3_DDR_CLOCK_ENA_DBG_MASK (0x00000004)
+#define CS_DDR_EN_DBG_MS3_DDR_CLOCK_ENA_DBG_BIT (0x00000004)
+
+#define CS_DDR_EN_DBG_DCXO_DDR_CLOCK_ENA_DBG_LSB (1)
+#define CS_DDR_EN_DBG_DCXO_DDR_CLOCK_ENA_DBG_WIDTH (1)
+#define CS_DDR_EN_DBG_DCXO_DDR_CLOCK_ENA_DBG_MASK (0x00000002)
+#define CS_DDR_EN_DBG_DCXO_DDR_CLOCK_ENA_DBG_BIT (0x00000002)
+
+#define CS_DDR_EN_DBG_LTEL1_CS_TOP_DDR_EN_DBG_LSB (0)
+#define CS_DDR_EN_DBG_LTEL1_CS_TOP_DDR_EN_DBG_WIDTH (1)
+#define CS_DDR_EN_DBG_LTEL1_CS_TOP_DDR_EN_DBG_MASK (0x00000001)
+#define CS_DDR_EN_DBG_LTEL1_CS_TOP_DDR_EN_DBG_BIT (0x00000001)
+
+
+#endif //#ifndef #ifndef _CPH_CSTOP_REG_97_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphd2bif.h b/mcu/interface/l1/cl1/common/HW/cphd2bif.h
new file mode 100644
index 0000000..5ab61ec
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphd2bif.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphd2bif_93.h"
+#elif defined(__MD95__) || defined(__MD97__)
+#include "cphd2bif_95.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphd2bif_93.h b/mcu/interface/l1/cl1/common/HW/cphd2bif_93.h
new file mode 100644
index 0000000..db429a6
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphd2bif_93.h
@@ -0,0 +1,458 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_D2BIF_H_
+#define _CPH_D2BIF_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define RX_BASIC_INFO_CC0 ((APBADDR32)0xAB820028)
+#define RX_BASIC_INFO_CC1 ((APBADDR32)0xAB82004C)
+
+#define D2BIF_CW_REG_BASE (0xAB824000)/*TBD*/
+
+
+#define D2BIF_CW_end (D2BIF_CW_REG_BASE + 0x0084 + 1*4)
+
+
+
+
+#define D2BIF_CW_CON ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0000))
+#define D2BIF_CW_SW_RST ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0004))
+#define D2BIF_CW_ADDR_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0008))
+#define D2BIF_CW_ADDR_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x000C))
+#define D2BIF_CW_SYNC0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0010))
+#define D2BIF_CW_SYNC1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0014))
+#define D2BIF_CW_SYNC2 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0018))
+#define D2BIF_CW_SYNC3 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x001C))
+#define TIMER_SYNC_DATA0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0020))
+#define TIMER_SYNC_DATA1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0024))
+#define TIMER_SYNC_DATA2 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0028))
+#define TIMER_SYNC_DATA3 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x002C))
+#define D2BIF_CW_DIS ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0030))
+#define D2BIF_CW_DBG_CON ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0034))
+#define D2BIF_CW_WREQ_CNT_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0038))
+#define D2BIF_CW_WREQ_CNT_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x003C))
+#define D2BIF_CW_WR_FSM_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0040))
+#define D2BIF_CW_WR_FSM_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0044))
+#define D2BIF_CW_REQ_REC_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0048))
+#define D2BIF_CW_REQ_REC_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x004C))
+#define D2BIF_CW_REQ_REC_2 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0050))
+#define D2BIF_CW_REQ_REC_3 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0054))
+#define D2BIF_CW_W_CON_A0C0_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0058))
+#define D2BIF_CW_W_CON_A1C0_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x005C))
+#define D2BIF_CW_W_CON_A0C1_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0060))
+#define D2BIF_CW_W_CON_A1C1_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0064))
+#define D2BIF_CW_W_CON_A0C0_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0068))
+#define D2BIF_CW_W_CON_A1C0_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x006C))
+#define D2BIF_CW_W_CON_A0C1_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0070))
+#define D2BIF_CW_W_CON_A1C1_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0074))
+#define D2BIF_CW_W_CON_QLIC_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0078))
+#define D2BIF_CW_W_CON_QLIC_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x007C))
+#define D2BIF_CW_WADDR_SEL ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0080))
+#define D2BIF_CW_RESERVED0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0084))
+
+
+#define D2BIF_CW_CON_D2BIF_CW_TRANS_MODE_LSB (19)
+#define D2BIF_CW_CON_D2BIF_CW_TRANS_MODE_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_TRANS_MODE_MASK (0x00080000)
+#define D2BIF_CW_CON_D2BIF_CW_TRANS_MODE_BIT (0x00080000)
+
+
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_LSB (16)
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_WIDTH (3)
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_MASK (0x00070000)
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_BIT (0x00070000)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_3_LSB (14)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_3_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_3_MASK (0x0000C000)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_2_LSB (12)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_2_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_2_MASK (0x00003000)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_1_LSB (10)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_1_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_1_MASK (0x00000C00)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_0_LSB (8)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_0_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_0_MASK (0x00000300)
+
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_LSB (5)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_MASK (0x00000020)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_BIT (0x00000020)
+
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_LSB (4)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_MASK (0x00000010)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_BIT (0x00000010)
+
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_LSB (3)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_MASK (0x00000008)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_BIT (0x00000008)
+
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_LSB (2)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_MASK (0x00000004)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_BIT (0x00000004)
+
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_LSB (1)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_MASK (0x00000002)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_BIT (0x00000002)
+
+#define D2BIF_CW_CON_D2BIF_CW_EN_LSB (0)
+#define D2BIF_CW_CON_D2BIF_CW_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_EN_MASK (0x00000001)
+#define D2BIF_CW_CON_D2BIF_CW_EN_BIT (0x00000001)
+
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_LSB (0)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_WIDTH (1)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_MASK (0x00000001)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_BIT (0x00000001)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_1_LSB (30)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_1_WIDTH (1)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_1_MASK (0x40000000)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_1_BIT (0x40000000)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_1_LSB (16)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_1_WIDTH (14)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_1_MASK (0x3FFF0000)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_0_LSB (14)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_0_WIDTH (1)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_0_MASK (0x00004000)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_0_BIT (0x00004000)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_0_LSB (0)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_0_WIDTH (14)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_0_MASK (0x00003FFF)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_3_LSB (30)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_3_WIDTH (1)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_3_MASK (0x40000000)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_3_BIT (0x40000000)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_3_LSB (16)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_3_WIDTH (14)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_3_MASK (0x3FFF0000)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_2_LSB (14)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_2_WIDTH (1)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_2_MASK (0x00004000)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_2_BIT (0x00004000)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_2_LSB (0)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_2_WIDTH (14)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_2_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_LSB (31)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_WIDTH (1)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_MASK (0x80000000)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_LSB (14)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_WIDTH (1)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_MASK (0x00004000)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_LSB (0)
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_WIDTH (14)
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_LSB (31)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_WIDTH (1)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_MASK (0x80000000)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_LSB (14)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_WIDTH (1)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_MASK (0x00004000)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_LSB (0)
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_WIDTH (14)
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_LSB (31)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_WIDTH (1)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_MASK (0x80000000)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_LSB (14)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_WIDTH (1)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_MASK (0x00004000)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_LSB (0)
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_WIDTH (14)
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_LSB (31)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_WIDTH (1)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_MASK (0x80000000)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC3_D2BIF_CW_2SLOT_IND_SYNC_3_LSB (14)
+#define D2BIF_CW_SYNC3_D2BIF_CW_2SLOT_IND_SYNC_3_WIDTH (1)
+#define D2BIF_CW_SYNC3_D2BIF_CW_2SLOT_IND_SYNC_3_MASK (0x00004000)
+#define D2BIF_CW_SYNC3_D2BIF_CW_2SLOT_IND_SYNC_3_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC3_D2BIF_CW_ADDR_SYNC_3_LSB (0)
+#define D2BIF_CW_SYNC3_D2BIF_CW_ADDR_SYNC_3_WIDTH (14)
+#define D2BIF_CW_SYNC3_D2BIF_CW_ADDR_SYNC_3_MASK (0x00003FFF)
+
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_LSB (15)
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_WIDTH (4)
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_LSB (3)
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_WIDTH (12)
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_LSB (0)
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_WIDTH (3)
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_LSB (15)
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_WIDTH (4)
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_LSB (3)
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_WIDTH (12)
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_LSB (0)
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_WIDTH (3)
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_LSB (15)
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_WIDTH (4)
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_LSB (3)
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_WIDTH (12)
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_LSB (0)
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_WIDTH (3)
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_LSB (15)
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_WIDTH (4)
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_LSB (3)
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_WIDTH (12)
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_LSB (0)
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_WIDTH (3)
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_MASK (0x00000007)
+
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_LSB (20)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_WIDTH (1)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_MASK (0x00100000)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_BIT (0x00100000)
+
+#define D2BIF_CW_DIS_RSC_EN_DIS_LSB (17)
+#define D2BIF_CW_DIS_RSC_EN_DIS_WIDTH (1)
+#define D2BIF_CW_DIS_RSC_EN_DIS_MASK (0x00020000)
+#define D2BIF_CW_DIS_RSC_EN_DIS_BIT (0x00020000)
+
+#define D2BIF_CW_DBG_CON_DBG_CLR_LSB (4)
+#define D2BIF_CW_DBG_CON_DBG_CLR_WIDTH (1)
+#define D2BIF_CW_DBG_CON_DBG_CLR_MASK (0x00000010)
+#define D2BIF_CW_DBG_CON_DBG_CLR_BIT (0x00000010)
+
+#define D2BIF_CW_DBG_CON_DBG_EN_LSB (0)
+#define D2BIF_CW_DBG_CON_DBG_EN_WIDTH (1)
+#define D2BIF_CW_DBG_CON_DBG_EN_MASK (0x00000001)
+#define D2BIF_CW_DBG_CON_DBG_EN_BIT (0x00000001)
+
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_LSB (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_LSB (0)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_LSB (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_LSB (0)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_LSB (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_WIDTH (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_LSB (0)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_WIDTH (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_LSB (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_WIDTH (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_LSB (0)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_WIDTH (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_LSB (16)
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_WIDTH (16)
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_LSB (0)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_WIDTH (1)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_LSB (16)
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_WIDTH (16)
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_LSB (0)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_WIDTH (1)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_LSB (16)
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_WIDTH (16)
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_LSB (0)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_WIDTH (1)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_LSB (16)
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_WIDTH (16)
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_LSB (0)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_WIDTH (1)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_BIT (0x00000001)
+
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_LSB (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_LSB (0)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_LSB (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_LSB (0)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_LSB (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_LSB (0)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_LSB (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_LSB (0)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_LSB (0)
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_LSB (0)
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_LSB (0)
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_LSB (0)
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_LSB (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_LSB (0)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_LSB (0)
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_LSB (4)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_MASK (0x00000030)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_LSB (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_MASK (0x0000000C)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_LSB (0)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_MASK (0x00000003)
+
+#endif //#ifndef _CPH_D2BIF_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphd2bif_95.h b/mcu/interface/l1/cl1/common/HW/cphd2bif_95.h
new file mode 100644
index 0000000..2f07d34
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphd2bif_95.h
@@ -0,0 +1,656 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_D2BIF_H_
+#define _CPH_D2BIF_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define RX_BASIC_INFO_CC0 ((APBADDR32)0xAB820028)
+#define RX_BASIC_INFO_CC1 ((APBADDR32)0xAB82004C)
+
+#define D2BIF_CW_REG_BASE (0xAB824000)/*TBD*/
+
+
+#define D2BIF_CW_end (D2BIF_CW_REG_BASE + 0x00F4 + 1*4)
+
+
+
+
+#define D2BIF_CW_CON ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0000))
+#define D2BIF_CW_SW_RST ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0004))
+#define D2BIF_CW_CA_SEL ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0008))
+#define D2BIF_CW_CA_SEL_QLIC ((APBADDR32)(D2BIF_CW_REG_BASE + 0x000C))
+#define D2BIF_CW_IQ_SWAP ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0010))
+#define D2BIF_CW_ADDR_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0014))
+#define D2BIF_CW_ADDR_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0018))
+#define D2BIF_CW_ADDR_IC ((APBADDR32)(D2BIF_CW_REG_BASE + 0x001C))
+#define D2BIF_CW_SYNC_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0020))
+#define D2BIF_CW_SYNC_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0024))
+#define D2BIF_CW_SYNC_IC ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0028))
+#define TIMER_SYNC_FDD ((APBADDR32)(D2BIF_CW_REG_BASE + 0x002C))
+#define TIMER_SYNC_C1X ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0030))
+#define TIMER_SYNC_CDO ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0034))
+#define D2BIF_CW_DIS ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0038))
+#define D2BIF_CW_DBG_CON ((APBADDR32)(D2BIF_CW_REG_BASE + 0x003C))
+#define D2BIF_CW_WREQ_CNT_01 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0038))
+#define D2BIF_CW_WREQ_CNT_23 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x003C))
+#define D2BIF_CW_WREQ_CNT ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0040))
+#define D2BIF_CW_REQ_REC ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0044))
+#define D2BIF_CW_REQ_REC_EN ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0048))
+#define D2BIF_CW_W_CON_A0C0_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x004C))
+#define D2BIF_CW_W_CON_A1C0_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0050))
+#define D2BIF_CW_W_CON_A0C1_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0054))
+#define D2BIF_CW_W_CON_A1C1_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0058))
+#define D2BIF_CW_W_CON_A0C0_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x005C))
+#define D2BIF_CW_W_CON_A1C0_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0060))
+#define D2BIF_CW_W_CON_A0C1_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0064))
+#define D2BIF_CW_W_CON_A1C1_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0068))
+#define D2BIF_CW_W_CON_QLIC_0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x006C))
+#define D2BIF_CW_W_CON_QLIC_1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0070))
+#define D2BIF_CW_WADDR_SEL ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0074))
+#define D2BIF_CW_OUT_SEL ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0078))
+#define D2BIF_CW_IC_CONF ((APBADDR32)(D2BIF_CW_REG_BASE + 0x007C))
+#define D2BIF_CW_FIFO_STA ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0080))
+#define D2BIF_CW_FIFO_STA_L ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0084))
+#define D2BIF_CW_STA_DBG ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0088))
+#define D2BIF_CW_FDD_RSC_ALIGN ((APBADDR32)(D2BIF_CW_REG_BASE + 0x0090)) //ALPS04870355
+#define D2BIF_CW_RESERVED0 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x00F0))
+#define D2BIF_CW_RESERVED1 ((APBADDR32)(D2BIF_CW_REG_BASE + 0x00F4))
+
+
+#define D2BIF_CW_CON_BIGRAM_DONE_MODE_LSB (15)
+#define D2BIF_CW_CON_BIGRAM_DONE_MODE_WIDTH (1)
+#define D2BIF_CW_CON_BIGRAM_DONE_MODE_MASK (0x00008000)
+#define D2BIF_CW_CON_BIGRAM_DONE_MODE_BIT (0x00008000)
+
+
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_LSB (12)
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_WIDTH (3)
+#define D2BIF_CW_CON_QLIC_DATA_RC_SEL_MASK (0x00007000)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_23_LSB (10)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_23_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_23_MASK (0x00000C00)
+
+#define D2BIF_CW_CON_D2BIF_CW_MODE_01_LSB (8)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_01_WIDTH (2)
+#define D2BIF_CW_CON_D2BIF_CW_MODE_01_MASK (0x00000300)
+
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_LSB (5)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_MASK (0x00000020)
+#define D2BIF_CW_CON_D2BIF_CW_A1C1_EN_BIT (0x00000020)
+
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_LSB (4)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_MASK (0x00000010)
+#define D2BIF_CW_CON_D2BIF_CW_A0C1_EN_BIT (0x00000010)
+
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_LSB (3)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_MASK (0x00000008)
+#define D2BIF_CW_CON_D2BIF_CW_A1C0_EN_BIT (0x00000008)
+
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_LSB (2)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_MASK (0x00000004)
+#define D2BIF_CW_CON_D2BIF_CW_A0C0_EN_BIT (0x00000004)
+
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_LSB (1)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_MASK (0x00000002)
+#define D2BIF_CW_CON_D2BIF_CW_QLIC_EN_BIT (0x00000002)
+
+#define D2BIF_CW_CON_D2BIF_CW_EN_LSB (0)
+#define D2BIF_CW_CON_D2BIF_CW_EN_WIDTH (1)
+#define D2BIF_CW_CON_D2BIF_CW_EN_MASK (0x00000001)
+#define D2BIF_CW_CON_D2BIF_CW_EN_BIT (0x00000001)
+
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_LSB (0)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_WIDTH (1)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_MASK (0x00000001)
+#define D2BIF_CW_SW_RST_D2BIF_CW_SW_RST_BIT (0x00000001)
+
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P3_LSB (12)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P3_WIDTH (4)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P3_MASK (0x0000F000)
+
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P2_LSB (8)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P2_WIDTH (4)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P2_MASK (0x00000F00)
+
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P1_LSB (4)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P1_WIDTH (4)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P1_MASK (0x000000F0)
+
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P0_LSB (0)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P0_WIDTH (4)
+#define D2BIF_CW_CA_SEL_D2BIF_CW_CC_ANT_SEL_P0_MASK (0x0000000F)
+
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P1_QLIC_LSB (4)
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P1_QLIC_WIDTH (4)
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P1_QLIC_MASK (0x000000F0)
+
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P0_QLIC_LSB (0)
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P0_QLIC_WIDTH (4)
+#define D2BIF_CW_CA_SEL_QLIC_D2BIF_CW_CC_ANT_SEL_P0_QLIC_MASK (0x0000000F)
+
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_QLIC_LSB (4)
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_QLIC_WIDTH (1)
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_QLIC_MASK (0x00000010)
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_QLIC_BIT (0x00000010)
+
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_LSB (0)
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_WIDTH (4)
+#define D2BIF_CW_IQ_SWAP_D2BIF_CW_IQ_SWAP_MASK (0x0000000F)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_01_LSB (14)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_01_WIDTH (1)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_01_MASK (0x00004000)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_2SLOT_IND_01_BIT (0x00004000)
+
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_01_LSB (0)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_01_WIDTH (14)
+#define D2BIF_CW_ADDR_01_D2BIF_CW_ADDR_01_MASK (0x00003FFF)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_23_LSB (14)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_23_WIDTH (1)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_23_MASK (0x00004000)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_2SLOT_IND_23_BIT (0x00004000)
+
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_23_LSB (0)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_23_WIDTH (14)
+#define D2BIF_CW_ADDR_23_D2BIF_CW_ADDR_23_MASK (0x00003FFF)
+
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_2SLOT_IND_IC_LSB (14)
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_2SLOT_IND_IC_WIDTH (1)
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_2SLOT_IND_IC_MASK (0x00004000)
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_2SLOT_IND_IC_BIT (0x00004000)
+
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_ADDR_IC_LSB (0)
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_ADDR_IC_WIDTH (14)
+#define D2BIF_CW_ADDR_IC_D2BIF_CW_ADDR_IC_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_LSB (31)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_WIDTH (1)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_MASK (0x80000000)
+#define D2BIF_CW_SYNC0_D2BIF_CW_SYNC_RDY_0_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_LSB (14)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_WIDTH (1)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_MASK (0x00004000)
+#define D2BIF_CW_SYNC0_D2BIF_CW_2SLOT_IND_SYNC_0_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_LSB (0)
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_WIDTH (14)
+#define D2BIF_CW_SYNC0_D2BIF_CW_ADDR_SYNC_0_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_LSB (31)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_WIDTH (1)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_MASK (0x80000000)
+#define D2BIF_CW_SYNC1_D2BIF_CW_SYNC_RDY_1_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_LSB (14)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_WIDTH (1)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_MASK (0x00004000)
+#define D2BIF_CW_SYNC1_D2BIF_CW_2SLOT_IND_SYNC_1_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_LSB (0)
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_WIDTH (14)
+#define D2BIF_CW_SYNC1_D2BIF_CW_ADDR_SYNC_1_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_LSB (31)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_WIDTH (1)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_MASK (0x80000000)
+#define D2BIF_CW_SYNC2_D2BIF_CW_SYNC_RDY_2_BIT (0x80000000)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_LSB (14)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_WIDTH (1)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_MASK (0x00004000)
+#define D2BIF_CW_SYNC2_D2BIF_CW_2SLOT_IND_SYNC_2_BIT (0x00004000)
+
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_LSB (0)
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_WIDTH (14)
+#define D2BIF_CW_SYNC2_D2BIF_CW_ADDR_SYNC_2_MASK (0x00003FFF)
+
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_LSB (31)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_WIDTH (1)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_MASK (0x80000000)
+#define D2BIF_CW_SYNC3_D2BIF_CW_SYNC_RDY_3_BIT (0x80000000)
+
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_LSB (15)
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_WIDTH (4)
+#define TIMER_SYNC_DATA0_RTR_SLOT_CNT_SYNC_0_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_LSB (3)
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_WIDTH (12)
+#define TIMER_SYNC_DATA0_RTR_CHIP_SYNC_0_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_LSB (0)
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_WIDTH (3)
+#define TIMER_SYNC_DATA0_RTR_ECHIP_SYNC_0_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_LSB (15)
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_WIDTH (4)
+#define TIMER_SYNC_DATA1_RTR_SLOT_CNT_SYNC_1_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_LSB (3)
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_WIDTH (12)
+#define TIMER_SYNC_DATA1_RTR_CHIP_SYNC_1_MASK (0x00007FF8)
+
+#define TIMER_SYNC_C1X_D2BIF_CW_SYNC_RDY_C1X_LSB (31)
+#define TIMER_SYNC_C1X_D2BIF_CW_SYNC_RDY_C1X_WIDTH (1)
+#define TIMER_SYNC_C1X_D2BIF_CW_SYNC_RDY_C1X_MASK (0x80000000)
+#define TIMER_SYNC_C1X_D2BIF_CW_SYNC_RDY_C1X_BIT (0x80000000)
+
+#define TIMER_SYNC_C1X_RTR_SYS_CNT_SYNC_C1X_LSB (0)
+#define TIMER_SYNC_C1X_RTR_SYS_CNT_SYNC_C1X_WIDTH (20)
+#define TIMER_SYNC_C1X_RTR_SYS_CNT_SYNC_C1X_MASK (0x000FFFFF)
+
+#define TIMER_SYNC_CDO_D2BIF_CW_SYNC_RDY_CDO_LSB (31)
+#define TIMER_SYNC_CDO_D2BIF_CW_SYNC_RDY_CDO_WIDTH (1)
+#define TIMER_SYNC_CDO_D2BIF_CW_SYNC_RDY_CDO_MASK (0x80000000)
+#define TIMER_SYNC_CDO_D2BIF_CW_SYNC_RDY_CDO_BIT (0x80000000)
+
+#define TIMER_SYNC_CDO_RTR_SYS_CNT_SYNC_CDO_LSB (0)
+#define TIMER_SYNC_CDO_RTR_SYS_CNT_SYNC_CDO_WIDTH (20)
+#define TIMER_SYNC_CDO_RTR_SYS_CNT_SYNC_CDO_MASK (0x000FFFFF)
+
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_LSB (0)
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_WIDTH (3)
+#define TIMER_SYNC_DATA1_RTR_ECHIP_SYNC_1_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_LSB (15)
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_WIDTH (4)
+#define TIMER_SYNC_DATA2_RTR_SLOT_CNT_SYNC_2_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_LSB (3)
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_WIDTH (12)
+#define TIMER_SYNC_DATA2_RTR_CHIP_SYNC_2_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_LSB (0)
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_WIDTH (3)
+#define TIMER_SYNC_DATA2_RTR_ECHIP_SYNC_2_MASK (0x00000007)
+
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_LSB (15)
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_WIDTH (4)
+#define TIMER_SYNC_DATA3_RTR_SLOT_CNT_SYNC_3_MASK (0x00078000)
+
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_LSB (3)
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_WIDTH (12)
+#define TIMER_SYNC_DATA3_RTR_CHIP_SYNC_3_MASK (0x00007FF8)
+
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_LSB (0)
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_WIDTH (3)
+#define TIMER_SYNC_DATA3_RTR_ECHIP_SYNC_3_MASK (0x00000007)
+
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_LSB (20)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_WIDTH (1)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_MASK (0x00100000)
+#define D2BIF_CW_DIS_BIGRAM_WRITE_DIS_BIT (0x00100000)
+
+#define D2BIF_CW_DIS_RSC_EN_DIS_LSB (17)
+#define D2BIF_CW_DIS_RSC_EN_DIS_WIDTH (1)
+#define D2BIF_CW_DIS_RSC_EN_DIS_MASK (0x00020000)
+#define D2BIF_CW_DIS_RSC_EN_DIS_BIT (0x00020000)
+
+#define D2BIF_CW_DBG_CON_DBG_CLR_LSB (4)
+#define D2BIF_CW_DBG_CON_DBG_CLR_WIDTH (1)
+#define D2BIF_CW_DBG_CON_DBG_CLR_MASK (0x00000010)
+#define D2BIF_CW_DBG_CON_DBG_CLR_BIT (0x00000010)
+
+#define D2BIF_CW_DBG_CON_DBG_EN_LSB (0)
+#define D2BIF_CW_DBG_CON_DBG_EN_WIDTH (1)
+#define D2BIF_CW_DBG_CON_DBG_EN_MASK (0x00000001)
+#define D2BIF_CW_DBG_CON_DBG_EN_BIT (0x00000001)
+
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_LSB (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_LSB (0)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_01_WREQ_CNT_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_LSB (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_LSB (0)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_WIDTH (16)
+#define D2BIF_CW_WREQ_CNT_23_WREQ_CNT_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_LSB (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_WIDTH (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_LSB (0)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_WIDTH (16)
+#define D2BIF_CW_WR_FSM_01_PACK_CNT_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_LSB (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_WIDTH (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_LSB (0)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_WIDTH (16)
+#define D2BIF_CW_WR_FSM_23_PACK_CNT_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_LSB (16)
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_WIDTH (16)
+#define D2BIF_CW_REQ_REC_0_REC_DATA_0_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_LSB (0)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_WIDTH (1)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_0_REC_EN_0_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_LSB (16)
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_WIDTH (16)
+#define D2BIF_CW_REQ_REC_1_REC_DATA_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_LSB (0)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_WIDTH (1)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_1_REC_EN_1_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_LSB (16)
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_WIDTH (16)
+#define D2BIF_CW_REQ_REC_2_REC_DATA_2_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_LSB (0)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_WIDTH (1)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_2_REC_EN_2_BIT (0x00000001)
+
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_LSB (16)
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_WIDTH (16)
+#define D2BIF_CW_REQ_REC_3_REC_DATA_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_LSB (0)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_WIDTH (1)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_MASK (0x00000001)
+#define D2BIF_CW_REQ_REC_3_REC_EN_3_BIT (0x00000001)
+
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_LSB (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_ST_SAM_IDX_0_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_LSB (0)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_0_D2BIF_CW_W_BASE_ADDR_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_LSB (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_ST_SAM_IDX_1_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_LSB (0)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_0_D2BIF_CW_W_BASE_ADDR_1_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_LSB (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_ST_SAM_IDX_2_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_LSB (0)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_0_D2BIF_CW_W_BASE_ADDR_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_LSB (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_ST_SAM_IDX_3_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_LSB (0)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_0_D2BIF_CW_W_BASE_ADDR_3_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_LSB (0)
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C0_1_D2BIF_CW_W_BUF_SIZE_0_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_LSB (0)
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C0_1_D2BIF_CW_W_BUF_SIZE_1_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_LSB (0)
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_WIDTH (16)
+#define D2BIF_CW_W_CON_A0C1_1_D2BIF_CW_W_BUF_SIZE_2_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_LSB (0)
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_WIDTH (16)
+#define D2BIF_CW_W_CON_A1C1_1_D2BIF_CW_W_BUF_SIZE_3_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_LSB (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_ST_SAM_IDX_Q_MASK (0xFFFF0000)
+
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_LSB (0)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_0_D2BIF_CW_W_BASE_ADDR_Q_MASK (0x0000FFFF)
+
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_LSB (0)
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_WIDTH (16)
+#define D2BIF_CW_W_CON_QLIC_1_D2BIF_CW_W_BUF_SIZE_Q_MASK (0x0000FFFF)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_LSB (4)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_Q_MASK (0x00000030)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_LSB (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_1_MASK (0x0000000C)
+
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_LSB (0)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_WIDTH (2)
+#define D2BIF_CW_WADDR_SEL_WADDR_IDX_0_MASK (0x00000003)
+
+#define D2BIF_CW_OUT_SEL_D2BIF_CW_OUT_SEL_LSB (0)
+#define D2BIF_CW_OUT_SEL_D2BIF_CW_OUT_SEL_WIDTH (2)
+#define D2BIF_CW_OUT_SEL_D2BIF_CW_OUT_SEL_MASK (0x00000003)
+
+#define D2BIF_CW_IC_CONF_IC_CONF_MODE_LSB (1)
+#define D2BIF_CW_IC_CONF_IC_CONF_MODE_WIDTH (1)
+#define D2BIF_CW_IC_CONF_IC_CONF_MODE_MASK (0x00000002)
+#define D2BIF_CW_IC_CONF_IC_CONF_MODE_BIT (0x00000002)
+
+#define D2BIF_CW_IC_CONF_IC_CONF_EN_LSB (0)
+#define D2BIF_CW_IC_CONF_IC_CONF_EN_WIDTH (1)
+#define D2BIF_CW_IC_CONF_IC_CONF_EN_MASK (0x00000001)
+#define D2BIF_CW_IC_CONF_IC_CONF_EN_BIT (0x00000001)
+
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P23_LSB (9)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P23_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P23_MASK (0x00000200)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P23_BIT (0x00000200)
+
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P01_LSB (8)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P01_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P01_MASK (0x00000100)
+#define D2BIF_CW_FIFO_STA_AFIFO_FULL_P01_BIT (0x00000100)
+
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P23_LSB (7)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P23_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P23_MASK (0x00000080)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P23_BIT (0x00000080)
+
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P01_LSB (6)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P01_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P01_MASK (0x00000040)
+#define D2BIF_CW_FIFO_STA_WADDR_FIFO_FULL_P01_BIT (0x00000040)
+
+#define D2BIF_CW_FIFO_STA_W_DATA_P3_FIFO_FULL_LSB (5)
+#define D2BIF_CW_FIFO_STA_W_DATA_P3_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_W_DATA_P3_FIFO_FULL_MASK (0x00000020)
+#define D2BIF_CW_FIFO_STA_W_DATA_P3_FIFO_FULL_BIT (0x00000020)
+
+#define D2BIF_CW_FIFO_STA_W_DATA_P2_FIFO_FULL_LSB (4)
+#define D2BIF_CW_FIFO_STA_W_DATA_P2_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_W_DATA_P2_FIFO_FULL_MASK (0x00000010)
+#define D2BIF_CW_FIFO_STA_W_DATA_P2_FIFO_FULL_BIT (0x00000010)
+
+#define D2BIF_CW_FIFO_STA_W_DATA_P1_FIFO_FULL_LSB (3)
+#define D2BIF_CW_FIFO_STA_W_DATA_P1_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_W_DATA_P1_FIFO_FULL_MASK (0x00000008)
+#define D2BIF_CW_FIFO_STA_W_DATA_P1_FIFO_FULL_BIT (0x00000008)
+
+#define D2BIF_CW_FIFO_STA_W_DATA_P0_FIFO_FULL_LSB (2)
+#define D2BIF_CW_FIFO_STA_W_DATA_P0_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_W_DATA_P0_FIFO_FULL_MASK (0x00000004)
+#define D2BIF_CW_FIFO_STA_W_DATA_P0_FIFO_FULL_BIT (0x00000004)
+
+#define D2BIF_CW_FIFO_STA_W_IDX_FIFO_FULL_LSB (1)
+#define D2BIF_CW_FIFO_STA_W_IDX_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_W_IDX_FIFO_FULL_MASK (0x00000002)
+#define D2BIF_CW_FIFO_STA_W_IDX_FIFO_FULL_BIT (0x00000002)
+
+#define D2BIF_CW_FIFO_STA_DONE_IDX_FIFO_FULL_LSB (0)
+#define D2BIF_CW_FIFO_STA_DONE_IDX_FIFO_FULL_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_DONE_IDX_FIFO_FULL_MASK (0x00000001)
+#define D2BIF_CW_FIFO_STA_DONE_IDX_FIFO_FULL_BIT (0x00000001)
+
+#define D2BIF_CW_FIFO_STA_L_FIFO_FULL_CNT_LSB (16)
+#define D2BIF_CW_FIFO_STA_L_FIFO_FULL_CNT_WIDTH (16)
+#define D2BIF_CW_FIFO_STA_L_FIFO_FULL_CNT_MASK (0xFFFF0000)
+
+#define D2BIF_CW_FIFO_STA_L_CDO_T2_EN_LSB (12)
+#define D2BIF_CW_FIFO_STA_L_CDO_T2_EN_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_CDO_T2_EN_MASK (0x00001000)
+#define D2BIF_CW_FIFO_STA_L_CDO_T2_EN_BIT (0x00001000)
+
+#define D2BIF_CW_FIFO_STA_L_C1X_T2_EN_LSB (11)
+#define D2BIF_CW_FIFO_STA_L_C1X_T2_EN_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_C1X_T2_EN_MASK (0x00000800)
+#define D2BIF_CW_FIFO_STA_L_C1X_T2_EN_BIT (0x00000800)
+
+#define D2BIF_CW_FIFO_STA_L_FDD_T2_EN_LSB (10)
+#define D2BIF_CW_FIFO_STA_L_FDD_T2_EN_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_FDD_T2_EN_MASK (0x00000400)
+#define D2BIF_CW_FIFO_STA_L_FDD_T2_EN_BIT (0x00000400)
+
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P23_L_LSB (9)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P23_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P23_L_MASK (0x00000200)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P23_L_BIT (0x00000200)
+
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P01_L_LSB (8)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P01_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P01_L_MASK (0x00000100)
+#define D2BIF_CW_FIFO_STA_L_AFIFO_FULL_P01_L_BIT (0x00000100)
+
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P23_L_LSB (7)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P23_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P23_L_MASK (0x00000080)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P23_L_BIT (0x00000080)
+
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P01_L_LSB (6)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P01_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P01_L_MASK (0x00000040)
+#define D2BIF_CW_FIFO_STA_L_WADDR_FIFO_FULL_P01_L_BIT (0x00000040)
+
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P3_FIFO_FULL_L_LSB (5)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P3_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P3_FIFO_FULL_L_MASK (0x00000020)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P3_FIFO_FULL_L_BIT (0x00000020)
+
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P2_FIFO_FULL_L_LSB (4)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P2_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P2_FIFO_FULL_L_MASK (0x00000010)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P2_FIFO_FULL_L_BIT (0x00000010)
+
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P1_FIFO_FULL_L_LSB (3)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P1_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P1_FIFO_FULL_L_MASK (0x00000008)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P1_FIFO_FULL_L_BIT (0x00000008)
+
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P0_FIFO_FULL_L_LSB (2)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P0_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P0_FIFO_FULL_L_MASK (0x00000004)
+#define D2BIF_CW_FIFO_STA_L_W_DATA_P0_FIFO_FULL_L_BIT (0x00000004)
+
+#define D2BIF_CW_FIFO_STA_L_W_IDX_FIFO_FULL_L_LSB (1)
+#define D2BIF_CW_FIFO_STA_L_W_IDX_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_W_IDX_FIFO_FULL_L_MASK (0x00000002)
+#define D2BIF_CW_FIFO_STA_L_W_IDX_FIFO_FULL_L_BIT (0x00000002)
+
+#define D2BIF_CW_FIFO_STA_L_DONE_IDX_FIFO_FULL_L_LSB (0)
+#define D2BIF_CW_FIFO_STA_L_DONE_IDX_FIFO_FULL_L_WIDTH (1)
+#define D2BIF_CW_FIFO_STA_L_DONE_IDX_FIFO_FULL_L_MASK (0x00000001)
+#define D2BIF_CW_FIFO_STA_L_DONE_IDX_FIFO_FULL_L_BIT (0x00000001)
+
+#define D2BIF_CW_STA_DBG_WR_STATE_1_LSB (17)
+#define D2BIF_CW_STA_DBG_WR_STATE_1_WIDTH (3)
+#define D2BIF_CW_STA_DBG_WR_STATE_1_MASK (0x000E0000)
+
+#define D2BIF_CW_STA_DBG_WR_STATE_0_LSB (14)
+#define D2BIF_CW_STA_DBG_WR_STATE_0_WIDTH (3)
+#define D2BIF_CW_STA_DBG_WR_STATE_0_MASK (0x0001C000)
+
+#define D2BIF_CW_STA_DBG_W_DONE_STATE_LSB (12)
+#define D2BIF_CW_STA_DBG_W_DONE_STATE_WIDTH (2)
+#define D2BIF_CW_STA_DBG_W_DONE_STATE_MASK (0x00003000)
+
+#define D2BIF_CW_STA_DBG_DONE_STATE_Q_LSB (9)
+#define D2BIF_CW_STA_DBG_DONE_STATE_Q_WIDTH (3)
+#define D2BIF_CW_STA_DBG_DONE_STATE_Q_MASK (0x00000E00)
+
+#define D2BIF_CW_STA_DBG_DONE_STATE_1_LSB (6)
+#define D2BIF_CW_STA_DBG_DONE_STATE_1_WIDTH (3)
+#define D2BIF_CW_STA_DBG_DONE_STATE_1_MASK (0x000001C0)
+
+#define D2BIF_CW_STA_DBG_DONE_STATE_0_LSB (3)
+#define D2BIF_CW_STA_DBG_DONE_STATE_0_WIDTH (3)
+#define D2BIF_CW_STA_DBG_DONE_STATE_0_MASK (0x00000038)
+
+#define D2BIF_CW_STA_DBG_W_STATE_LSB (0)
+#define D2BIF_CW_STA_DBG_W_STATE_WIDTH (3)
+#define D2BIF_CW_STA_DBG_W_STATE_MASK (0x00000007)
+
+#define D2BIF_CW_RESERVED0_D2BIF_CW_RESERVED0_LSB (0)
+#define D2BIF_CW_RESERVED0_D2BIF_CW_RESERVED0_WIDTH (32)
+#define D2BIF_CW_RESERVED0_D2BIF_CW_RESERVED0_MASK (0xFFFFFFFF)
+
+#define D2BIF_CW_RESERVED1_D2BIF_CW_RESERVED1_LSB (0)
+#define D2BIF_CW_RESERVED1_D2BIF_CW_RESERVED1_WIDTH (32)
+#define D2BIF_CW_RESERVED1_D2BIF_CW_RESERVED1_MASK (0xFFFFFFFF)
+
+#endif //#ifndef _CPH_D2BIF_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg0.h b/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg0.h
new file mode 100644
index 0000000..a93cc5c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg0.h
@@ -0,0 +1,280 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CPH_DFESYS_GLBCON_CONFIG0_H_
+#define _CPH_DFESYS_GLBCON_CONFIG0_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define DFESYS_GLB_CON_CONFIG0_REG_BASE (0xA8990000)
+
+#define DFESYS_GLB_CON_CONFIG0_end (DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0114 + 1*4)
+
+
+
+#define DIV_TXBRP ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))
+#define DIV_TXCRP ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))
+#define DEBUG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))
+#define F208M_DEBUG_BUS ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))
+#define F208M_DEBUG_BUS2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))
+#define TXBSRP_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))
+#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))
+#define TXBSRP_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))
+#define TXBSRP_PCK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))
+#define TXBSRP_PCK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))
+#define TX_SRP_CRP_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))
+#define TX_SRP_CRP_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))
+#define TXCRP_PCK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0050))
+#define TXCRP_PCK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0054))
+#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))
+#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))
+#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))
+#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))
+#define TXCRP_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))
+#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0080))
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0084))
+#define SW_CK_IDLE_DIV ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0090))
+#define MASK_TXBSRP_CK_IDLE_DIV ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0094))
+#define R2TX_SW_DISABLE_HW ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))
+#define R2T_RDATA1 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0104))
+#define R2T_RDATA2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0108))
+#define R2T_RDATA3 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x010c))
+#define R2T_RDATA4 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0110))
+#define R2T_RDATA5 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0114))
+
+
+#define DIV_TXBRP_DIV_TXBRP_LSB (0)
+#define DIV_TXBRP_DIV_TXBRP_WIDTH (1)
+#define DIV_TXBRP_DIV_TXBRP_MASK (0x00000001)
+#define DIV_TXBRP_DIV_TXBRP_BIT (0x00000001)
+
+#define DIV_TXCRP_DIV_TXCRP_LSB (0)
+#define DIV_TXCRP_DIV_TXCRP_WIDTH (2)
+#define DIV_TXCRP_DIV_TXCRP_MASK (0x00000003)
+
+#define DEBUG_SEL_DEBUG_SEL_3_LSB (24)
+#define DEBUG_SEL_DEBUG_SEL_3_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_3_MASK (0x1F000000)
+
+#define DEBUG_SEL_DEBUG_SEL_2_LSB (16)
+#define DEBUG_SEL_DEBUG_SEL_2_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_2_MASK (0x001F0000)
+
+#define DEBUG_SEL_DEBUG_SEL_1_LSB (8)
+#define DEBUG_SEL_DEBUG_SEL_1_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_1_MASK (0x00001F00)
+
+#define DEBUG_SEL_DEBUG_SEL_0_LSB (0)
+#define DEBUG_SEL_DEBUG_SEL_0_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_0_MASK (0x0000001F)
+
+#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_LSB (0)
+#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_WIDTH (32)
+#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_LSB (0)
+#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_WIDTH (32)
+#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_MASK (0xFFFFFFFF)
+
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_LSB (0)
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_WIDTH (1)
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_MASK (0x00000001)
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_BIT (0x00000001)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_LSB (8)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_WIDTH (11)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_LSB (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_WIDTH (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_LSB (1)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_WIDTH (3)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_MASK (0x0000000E)
+
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_LSB (0)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_WIDTH (1)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_MASK (0x00000001)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_BIT (0x00000001)
+
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_LSB (16)
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_WIDTH (1)
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_LSB (1)
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_WIDTH (1)
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_MASK (0x00000002)
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_BIT (0x00000002)
+
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_LSB (0)
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_WIDTH (1)
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_LSB (0)
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_WIDTH (1)
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_MASK (0x00000001)
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_BIT (0x00000001)
+
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_LSB (0)
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_WIDTH (1)
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_MASK (0x00000001)
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_LSB (0)
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_WIDTH (1)
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_LSB (0)
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_LSB (0)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_WIDTH (1)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_MASK (0x00000001)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_LSB (0)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_WIDTH (1)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_LSB (0)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_WIDTH (1)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_LSB (0)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_WIDTH (1)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_LSB (0)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_WIDTH (1)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_LSB (0)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_LSB (0)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_WIDTH (1)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_MASK (0x00000001)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_LSB (3)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_MASK (0x00000008)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_BIT (0x00000008)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_LSB (2)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_MASK (0x00000004)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_BIT (0x00000004)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_LSB (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_MASK (0x00000002)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_BIT (0x00000002)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_BIT (0x00000001)
+
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_LSB (0)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_WIDTH (1)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_MASK (0x00000001)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_BIT (0x00000001)
+
+#define R2T_RDATA1_R2T_RDATA1_LSB (0)
+#define R2T_RDATA1_R2T_RDATA1_WIDTH (32)
+#define R2T_RDATA1_R2T_RDATA1_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA2_R2T_RDATA2_LSB (0)
+#define R2T_RDATA2_R2T_RDATA2_WIDTH (32)
+#define R2T_RDATA2_R2T_RDATA2_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA3_R2T_RDATA3_LSB (0)
+#define R2T_RDATA3_R2T_RDATA3_WIDTH (32)
+#define R2T_RDATA3_R2T_RDATA3_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA4_R2T_RDATA4_LSB (0)
+#define R2T_RDATA4_R2T_RDATA4_WIDTH (32)
+#define R2T_RDATA4_R2T_RDATA4_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA5_R2T_RDATA5_LSB (0)
+#define R2T_RDATA5_R2T_RDATA5_WIDTH (32)
+#define R2T_RDATA5_R2T_RDATA5_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _EL1D_REG_ELBRUS_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg1.h b/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg1.h
new file mode 100644
index 0000000..e4a8a5d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg1.h
@@ -0,0 +1,492 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_DFESYS_GLBCON_CONFIG1_H_
+#define _CPH_DFESYS_GLBCON_CONFIG1_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define DFESYS_GLB_CON_CONFIG1_REG_BASE (0xA8bd0000)
+
+#define DFESYS_GLB_CON_CONFIG1_end (DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0218 + 1*4)
+
+
+
+#define TXDFE_D_BSRP_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0008))
+#define TXDFE_D_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0010))
+#define TXDFE_D_F156M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0014))
+#define TXDFE_D_F26M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0018))
+#define TXDFE_D_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x001c))
+#define TPC_D_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0020))
+#define TPC_D_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0024))
+#define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0030))
+#define TDD_TTR_F6P5M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0040))
+#define LTE_TTR0_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0050))
+#define LTE_TTR1_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0054))
+#define LTE_TTR2_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0058))
+#define NR_TTR0_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0070))
+#define NR_TTR1_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0074))
+#define NR_TTR2_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0078))
+#define NR_TTR3_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x007c))
+#define SERDES_COS_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a0))
+#define SERDES_ACNT_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a4))
+#define SERDES_L3_TX_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a8))
+#define SERDES_L3_RX_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00ac))
+#define SERDES_MISC_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00b0))
+#define SERDES_GLB_OFF_BUS_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00b4))
+#define DIGRF_OFF_HW_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00bc))
+#define F312M_DEBUG_BUS ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c0))
+#define F312M_DEBUG_BUS2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c4))
+#define DFESYS_DEBUG_TRIG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c8))
+#define RXDFE_F312M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0100))
+#define RXDFE_F156M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0104))
+#define RXDFE_F26M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0108))
+#define SERDES_SWRST0_STARTB ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0200))
+#define SERDES_SWRST1_STARTB ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0204))
+#define DBG_FLAG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0208))
+#define DBG_TRIG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x020c))
+#define DFESYS_MAS_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0210))
+#define DFESYS_SLB_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0214))
+#define D_GDMA_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0218))
+
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_LSB (6)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_MASK (0x00000040)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_BIT (0x00000040)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_LSB (5)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_MASK (0x00000020)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_BIT (0x00000020)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_LSB (4)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_MASK (0x00000010)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_BIT (0x00000010)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_LSB (3)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_MASK (0x00000008)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_BIT (0x00000008)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_LSB (2)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_MASK (0x00000004)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_BIT (0x00000004)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_LSB (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_MASK (0x00000002)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_BIT (0x00000002)
+
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_LSB (0)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_WIDTH (1)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_MASK (0x00000001)
+#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_BIT (0x00000001)
+
+#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_LSB (0)
+#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_WIDTH (1)
+#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_MASK (0x00000001)
+#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_BIT (0x00000001)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_LSB (6)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_MASK (0x00000040)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_BIT (0x00000040)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_LSB (5)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_MASK (0x00000020)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_BIT (0x00000020)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_LSB (4)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_MASK (0x00000010)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_BIT (0x00000010)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_LSB (3)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_MASK (0x00000008)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_BIT (0x00000008)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_LSB (2)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_MASK (0x00000004)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_BIT (0x00000004)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_LSB (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_MASK (0x00000002)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_BIT (0x00000002)
+
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_LSB (0)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_WIDTH (1)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_MASK (0x00000001)
+#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_BIT (0x00000001)
+
+#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_LSB (0)
+#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_WIDTH (1)
+#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_MASK (0x00000001)
+#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_BIT (0x00000001)
+
+#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_LSB (0)
+#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_WIDTH (1)
+#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_MASK (0x00000001)
+#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_BIT (0x00000001)
+
+#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_LSB (1)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_MASK (0x00000002)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_BIT (0x00000002)
+
+#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_LSB (0)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_MASK (0x00000001)
+#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_BIT (0x00000001)
+
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_LSB (1)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_MASK (0x00000002)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_BIT (0x00000002)
+
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_LSB (0)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_MASK (0x00000001)
+#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_LSB (0)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_WIDTH (1)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_MASK (0x00000001)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_BIT (0x00000001)
+
+#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_LSB (0)
+#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_WIDTH (1)
+#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_MASK (0x00000001)
+#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_BIT (0x00000001)
+
+#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_LSB (0)
+#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_WIDTH (1)
+#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_BIT (0x00000001)
+
+#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_LSB (0)
+#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_WIDTH (1)
+#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_BIT (0x00000001)
+
+#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_LSB (0)
+#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_WIDTH (1)
+#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_MASK (0x00000001)
+#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_BIT (0x00000001)
+
+#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_LSB (0)
+#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_WIDTH (1)
+#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_MASK (0x00000001)
+#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_BIT (0x00000001)
+
+#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_LSB (0)
+#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_WIDTH (1)
+#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_MASK (0x00000001)
+#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_BIT (0x00000001)
+
+#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_LSB (0)
+#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_WIDTH (1)
+#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_MASK (0x00000001)
+#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_BIT (0x00000001)
+
+#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_LSB (0)
+#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_WIDTH (1)
+#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_MASK (0x00000001)
+#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_LSB (0)
+#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_WIDTH (1)
+#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_LSB (0)
+#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_WIDTH (1)
+#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_LSB (0)
+#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_WIDTH (1)
+#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_LSB (0)
+#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_WIDTH (1)
+#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_LSB (0)
+#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_WIDTH (1)
+#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_LSB (0)
+#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_WIDTH (1)
+#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_LSB (0)
+#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_WIDTH (1)
+#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_MASK (0x00000001)
+#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_BIT (0x00000001)
+
+#define F312M_DEBUG_BUS_F312M_DEBUG_BUS_LSB (0)
+#define F312M_DEBUG_BUS_F312M_DEBUG_BUS_WIDTH (32)
+#define F312M_DEBUG_BUS_F312M_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_LSB (0)
+#define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_WIDTH (32)
+#define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_MASK (0xFFFFFFFF)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_WIDTH (5)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_MASK (0x0000001F)
+
+#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_LSB (0)
+#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_WIDTH (1)
+#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_MASK (0x00000001)
+#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_BIT (0x00000001)
+
+#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_LSB (0)
+#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_WIDTH (1)
+#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_MASK (0x00000001)
+#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_BIT (0x00000001)
+
+#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_LSB (0)
+#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_WIDTH (1)
+#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_MASK (0x00000001)
+#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_BIT (0x00000001)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_LSB (13)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_MASK (0x00002000)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_BIT (0x00002000)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_LSB (12)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_MASK (0x00001000)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_BIT (0x00001000)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_LSB (11)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_MASK (0x00000800)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_BIT (0x00000800)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_LSB (10)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_MASK (0x00000400)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_BIT (0x00000400)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_LSB (9)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_MASK (0x00000200)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_BIT (0x00000200)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_LSB (8)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_MASK (0x00000100)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_BIT (0x00000100)
+
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_LSB (7)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_MASK (0x00000080)
+#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_BIT (0x00000080)
+
+#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_LSB (6)
+#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_MASK (0x00000040)
+#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_BIT (0x00000040)
+
+#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_LSB (5)
+#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_MASK (0x00000020)
+#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_BIT (0x00000020)
+
+#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_LSB (4)
+#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_MASK (0x00000010)
+#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_BIT (0x00000010)
+
+#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_LSB (3)
+#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_MASK (0x00000008)
+#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_BIT (0x00000008)
+
+#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_LSB (2)
+#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_MASK (0x00000004)
+#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_BIT (0x00000004)
+
+#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_LSB (1)
+#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_MASK (0x00000002)
+#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_BIT (0x00000002)
+
+#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_LSB (0)
+#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_MASK (0x00000001)
+#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_BIT (0x00000001)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_LSB (15)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_MASK (0x00008000)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_BIT (0x00008000)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_LSB (14)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_MASK (0x00004000)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_BIT (0x00004000)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_LSB (13)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_MASK (0x00002000)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_BIT (0x00002000)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_LSB (12)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_MASK (0x00001000)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_BIT (0x00001000)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_LSB (11)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_MASK (0x00000800)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_BIT (0x00000800)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_LSB (10)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_MASK (0x00000400)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_BIT (0x00000400)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_LSB (9)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_MASK (0x00000200)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_BIT (0x00000200)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_LSB (8)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_MASK (0x00000100)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_BIT (0x00000100)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_LSB (7)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_MASK (0x00000080)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_BIT (0x00000080)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_LSB (6)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_MASK (0x00000040)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_BIT (0x00000040)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_LSB (5)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_MASK (0x00000020)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_BIT (0x00000020)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_LSB (4)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_MASK (0x00000010)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_BIT (0x00000010)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_LSB (3)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_MASK (0x00000008)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_BIT (0x00000008)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_LSB (2)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_MASK (0x00000004)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_BIT (0x00000004)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_LSB (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_MASK (0x00000002)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_BIT (0x00000002)
+
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_LSB (0)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_WIDTH (1)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_MASK (0x00000001)
+#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_BIT (0x00000001)
+
+#define DBG_FLAG_SEL_DBG_FLAG3_SEL_LSB (24)
+#define DBG_FLAG_SEL_DBG_FLAG3_SEL_WIDTH (8)
+#define DBG_FLAG_SEL_DBG_FLAG3_SEL_MASK (0xFF000000)
+
+#define DBG_FLAG_SEL_DBG_FLAG2_SEL_LSB (16)
+#define DBG_FLAG_SEL_DBG_FLAG2_SEL_WIDTH (8)
+#define DBG_FLAG_SEL_DBG_FLAG2_SEL_MASK (0x00FF0000)
+
+#define DBG_FLAG_SEL_DBG_FLAG1_SEL_LSB (8)
+#define DBG_FLAG_SEL_DBG_FLAG1_SEL_WIDTH (8)
+#define DBG_FLAG_SEL_DBG_FLAG1_SEL_MASK (0x0000FF00)
+
+#define DBG_FLAG_SEL_DBG_FLAG0_SEL_LSB (0)
+#define DBG_FLAG_SEL_DBG_FLAG0_SEL_WIDTH (8)
+#define DBG_FLAG_SEL_DBG_FLAG0_SEL_MASK (0x000000FF)
+
+#define DBG_TRIG_SEL_DBG_TRIG_SEL_LSB (0)
+#define DBG_TRIG_SEL_DBG_TRIG_SEL_WIDTH (8)
+#define DBG_TRIG_SEL_DBG_TRIG_SEL_MASK (0x000000FF)
+
+#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_LSB (0)
+#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_LSB (0)
+#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_WIDTH (1)
+#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_MASK (0x00000001)
+#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_BIT (0x00000001)
+
+#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_LSB (0)
+#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_WIDTH (1)
+#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_MASK (0x00000001)
+#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_BIT (0x00000001)
+
+
+#endif //#ifndef _EL1D_REG_ELBRUS_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxbrp.h b/mcu/interface/l1/cl1/common/HW/cphevdorxbrp.h
new file mode 100644
index 0000000..6b214c1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxbrp.h
@@ -0,0 +1,511 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_RXBRP_H_
+#define _CPH_EVDO_RXBRP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if (defined(__MD93__))||(defined(__MD95__))
+#define RXBRP_C_EVDO_REG_BASE (0xAD230000)
+#else
+#define RXBRP_C_EVDO_REG_BASE (0xACA30000)
+#endif
+
+#define RXBRP_C_EVDO_end (RXBRP_C_EVDO_REG_BASE + 0x0204 + 1*4)
+
+
+
+#define DBRP_EVDO_START ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0000))
+#define DBRP_EVDO_DONE ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0004))
+#define DBRP_EVDO_DONE_VEC ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0008))
+#define DBRP_EVDO_CH_DET ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x000C))
+#define DBRP_EVDO_HARQ_INFO ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0010))
+#define DBRP_EVDO_C2I_SCAL_QPSK ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0014))
+#define DBRP_EVDO_C2I_SCAL_8PSK ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0018))
+#define DBRP_EVDO_C2I_SCAL_16QAM ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x001C))
+#define DBRP_EVDO_HARQ_DBG ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00A0))
+#define DBRP_EVDO_C2I_RD ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00A4))
+#define DBRP_EVDO_C2I_RD_ADDR ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00A8))
+#define DBRP_EVDO_C2I_RD_DATA ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00AC))
+#define DBRP_EVDO_HARQ_RD ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00B0))
+#define DBRP_EVDO_HARQ_RD_ADDR ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00B4))
+#define DBRP_EVDO_HARQ_RD_DATA ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00B8))
+#define DBRP_EVDO_HARQ_ABSACC_03 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00BC))
+#define DBRP_EVDO_HARQ_ABSACC_47 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00C0))
+#define DBRP_EVDO_DBG0 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00D0))
+#define DBRP_EVDO_PWR_CFG ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x00F0))
+#define DBRP_EVDO_HARQ_PARAM ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0100))
+#define DBRP_EVDO_CH0_PARAM1 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0104))
+#define DBRP_EVDO_CH0_PARAM2 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0108))
+#define DBRP_EVDO_CH0_PARAM3 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x010C))
+#define DBRP_EVDO_CH1_PARAM1 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0110))
+#define DBRP_EVDO_CH1_PARAM2 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0114))
+#define DBRP_EVDO_CH1_PARAM3 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0118))
+#define DBRP_EVDO_CH2_PARAM1 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x011C))
+#define DBRP_EVDO_CH2_PARAM2 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0120))
+#define DBRP_EVDO_CH2_PARAM3 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0124))
+#define DBRP_EVDO_CH3_PARAM1 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0128))
+#define DBRP_EVDO_CH3_PARAM2 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x012C))
+#define DBRP_EVDO_CH3_PARAM3 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0130))
+#define DBRP_EVDO_C2I_PARAM0 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0200))
+#define DBRP_EVDO_C2I_PARAM1 ((APBADDR32)(RXBRP_C_EVDO_REG_BASE + 0x0204))
+
+
+#define DBRP_EVDO_START_EVDO_START_LSB (15)
+#define DBRP_EVDO_START_EVDO_START_WIDTH (1)
+#define DBRP_EVDO_START_EVDO_START_MASK (0x00008000)
+#define DBRP_EVDO_START_EVDO_START_BIT (0x00008000)
+#define DBRP_EVDO_DONE_EVDO_SW_IRQ_TRIG_LSB (16)
+#define DBRP_EVDO_DONE_EVDO_SW_IRQ_TRIG_WIDTH (1)
+#define DBRP_EVDO_DONE_EVDO_SW_IRQ_TRIG_MASK (0x00010000)
+#define DBRP_EVDO_DONE_EVDO_SW_IRQ_TRIG_BIT (0x00010000)
+
+#define DBRP_EVDO_DONE_EVDO_DONE_LSB (0)
+#define DBRP_EVDO_DONE_EVDO_DONE_WIDTH (1)
+#define DBRP_EVDO_DONE_EVDO_DONE_MASK (0x00000001)
+#define DBRP_EVDO_DONE_EVDO_DONE_BIT (0x00000001)
+
+#define DBRP_EVDO_DONE_VEC_TURBO_DONE_LSB (1)
+#define DBRP_EVDO_DONE_VEC_TURBO_DONE_WIDTH (1)
+#define DBRP_EVDO_DONE_VEC_TURBO_DONE_MASK (0x00000002)
+#define DBRP_EVDO_DONE_VEC_TURBO_DONE_BIT (0x00000002)
+
+#define DBRP_EVDO_DONE_VEC_DRM_DONE_LSB (0)
+#define DBRP_EVDO_DONE_VEC_DRM_DONE_WIDTH (1)
+#define DBRP_EVDO_DONE_VEC_DRM_DONE_MASK (0x00000001)
+#define DBRP_EVDO_DONE_VEC_DRM_DONE_BIT (0x00000001)
+
+#define DBRP_EVDO_CH_DET_CH3_EN_LSB (3)
+#define DBRP_EVDO_CH_DET_CH3_EN_WIDTH (1)
+#define DBRP_EVDO_CH_DET_CH3_EN_MASK (0x00000008)
+#define DBRP_EVDO_CH_DET_CH3_EN_BIT (0x00000008)
+
+#define DBRP_EVDO_CH_DET_CH2_EN_LSB (2)
+#define DBRP_EVDO_CH_DET_CH2_EN_WIDTH (1)
+#define DBRP_EVDO_CH_DET_CH2_EN_MASK (0x00000004)
+#define DBRP_EVDO_CH_DET_CH2_EN_BIT (0x00000004)
+
+#define DBRP_EVDO_CH_DET_CH1_EN_LSB (1)
+#define DBRP_EVDO_CH_DET_CH1_EN_WIDTH (1)
+#define DBRP_EVDO_CH_DET_CH1_EN_MASK (0x00000002)
+#define DBRP_EVDO_CH_DET_CH1_EN_BIT (0x00000002)
+
+#define DBRP_EVDO_CH_DET_CH0_EN_LSB (0)
+#define DBRP_EVDO_CH_DET_CH0_EN_WIDTH (1)
+#define DBRP_EVDO_CH_DET_CH0_EN_MASK (0x00000001)
+#define DBRP_EVDO_CH_DET_CH0_EN_BIT (0x00000001)
+
+#define DBRP_EVDO_HARQ_INFO_CRCSIZE_LSB (3)
+#define DBRP_EVDO_HARQ_INFO_CRCSIZE_WIDTH (1)
+#define DBRP_EVDO_HARQ_INFO_CRCSIZE_MASK (0x00000008)
+#define DBRP_EVDO_HARQ_INFO_CRCSIZE_BIT (0x00000008)
+
+#define DBRP_EVDO_HARQ_INFO_INTERLANCE_LSB (1)
+#define DBRP_EVDO_HARQ_INFO_INTERLANCE_WIDTH (2)
+#define DBRP_EVDO_HARQ_INFO_INTERLANCE_MASK (0x00000006)
+
+#define DBRP_EVDO_HARQ_INFO_NDI_LSB (0)
+#define DBRP_EVDO_HARQ_INFO_NDI_WIDTH (1)
+#define DBRP_EVDO_HARQ_INFO_NDI_MASK (0x00000001)
+#define DBRP_EVDO_HARQ_INFO_NDI_BIT (0x00000001)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_NORM_TYPE_LSB (31)
+#define DBRP_EVDO_C2I_SCAL_QPSK_NORM_TYPE_WIDTH (1)
+#define DBRP_EVDO_C2I_SCAL_QPSK_NORM_TYPE_MASK (0x80000000)
+#define DBRP_EVDO_C2I_SCAL_QPSK_NORM_TYPE_BIT (0x80000000)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_SHIFT_C2I_LSB (24)
+#define DBRP_EVDO_C2I_SCAL_QPSK_SHIFT_C2I_WIDTH (5)
+#define DBRP_EVDO_C2I_SCAL_QPSK_SHIFT_C2I_MASK (0x1F000000)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_3_LSB (18)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_3_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_3_MASK (0x00FC0000)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_2_LSB (12)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_2_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_2_MASK (0x0003F000)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_1_LSB (6)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_1_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_1_MASK (0x00000FC0)
+
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_0_LSB (0)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_0_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_QPSK_DIV_C2I_0_MASK (0x0000003F)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_NORM_TYPE_LSB (31)
+#define DBRP_EVDO_C2I_SCAL_8PSK_NORM_TYPE_WIDTH (1)
+#define DBRP_EVDO_C2I_SCAL_8PSK_NORM_TYPE_MASK (0x80000000)
+#define DBRP_EVDO_C2I_SCAL_8PSK_NORM_TYPE_BIT (0x80000000)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_SHIFT_C2I_LSB (24)
+#define DBRP_EVDO_C2I_SCAL_8PSK_SHIFT_C2I_WIDTH (5)
+#define DBRP_EVDO_C2I_SCAL_8PSK_SHIFT_C2I_MASK (0x1F000000)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_3_LSB (18)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_3_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_3_MASK (0x00FC0000)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_2_LSB (12)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_2_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_2_MASK (0x0003F000)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_1_LSB (6)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_1_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_1_MASK (0x00000FC0)
+
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_0_LSB (0)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_0_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_8PSK_DIV_C2I_0_MASK (0x0000003F)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_NORM_TYPE_LSB (31)
+#define DBRP_EVDO_C2I_SCAL_16QAM_NORM_TYPE_WIDTH (1)
+#define DBRP_EVDO_C2I_SCAL_16QAM_NORM_TYPE_MASK (0x80000000)
+#define DBRP_EVDO_C2I_SCAL_16QAM_NORM_TYPE_BIT (0x80000000)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_SHIFT_C2I_LSB (24)
+#define DBRP_EVDO_C2I_SCAL_16QAM_SHIFT_C2I_WIDTH (5)
+#define DBRP_EVDO_C2I_SCAL_16QAM_SHIFT_C2I_MASK (0x1F000000)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_3_LSB (18)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_3_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_3_MASK (0x00FC0000)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_2_LSB (12)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_2_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_2_MASK (0x0003F000)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_1_LSB (6)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_1_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_1_MASK (0x00000FC0)
+
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_0_LSB (0)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_0_WIDTH (6)
+#define DBRP_EVDO_C2I_SCAL_16QAM_DIV_C2I_0_MASK (0x0000003F)
+
+#define DBRP_EVDO_HARQ_DBG_EN_LSB (0)
+#define DBRP_EVDO_HARQ_DBG_EN_WIDTH (1)
+#define DBRP_EVDO_HARQ_DBG_EN_MASK (0x00000001)
+#define DBRP_EVDO_HARQ_DBG_EN_BIT (0x00000001)
+
+#define DBRP_EVDO_C2I_RD_TRG_LSB (0)
+#define DBRP_EVDO_C2I_RD_TRG_WIDTH (1)
+#define DBRP_EVDO_C2I_RD_TRG_MASK (0x00000001)
+#define DBRP_EVDO_C2I_RD_TRG_BIT (0x00000001)
+
+#define DBRP_EVDO_C2I_RD_ADDR_AUTO_INC_LSB (15)
+#define DBRP_EVDO_C2I_RD_ADDR_AUTO_INC_WIDTH (1)
+#define DBRP_EVDO_C2I_RD_ADDR_AUTO_INC_MASK (0x00008000)
+#define DBRP_EVDO_C2I_RD_ADDR_AUTO_INC_BIT (0x00008000)
+
+#define DBRP_EVDO_C2I_RD_ADDR_MEM_ADDR_LSB (0)
+#define DBRP_EVDO_C2I_RD_ADDR_MEM_ADDR_WIDTH (6)
+#define DBRP_EVDO_C2I_RD_ADDR_MEM_ADDR_MASK (0x0000003F)
+
+#define DBRP_EVDO_C2I_RD_DATA_MEM_DATA_LSB (0)
+#define DBRP_EVDO_C2I_RD_DATA_MEM_DATA_WIDTH (12)
+#define DBRP_EVDO_C2I_RD_DATA_MEM_DATA_MASK (0x00000FFF)
+
+#define DBRP_EVDO_HARQ_RD_TRG_LSB (0)
+#define DBRP_EVDO_HARQ_RD_TRG_WIDTH (1)
+#define DBRP_EVDO_HARQ_RD_TRG_MASK (0x00000001)
+#define DBRP_EVDO_HARQ_RD_TRG_BIT (0x00000001)
+
+#define DBRP_EVDO_HARQ_RD_ADDR_AUTO_INC_LSB (15)
+#define DBRP_EVDO_HARQ_RD_ADDR_AUTO_INC_WIDTH (1)
+#define DBRP_EVDO_HARQ_RD_ADDR_AUTO_INC_MASK (0x00008000)
+#define DBRP_EVDO_HARQ_RD_ADDR_AUTO_INC_BIT (0x00008000)
+
+#define DBRP_EVDO_HARQ_RD_ADDR_MEM_ADDR_LSB (0)
+#define DBRP_EVDO_HARQ_RD_ADDR_MEM_ADDR_WIDTH (11)
+#define DBRP_EVDO_HARQ_RD_ADDR_MEM_ADDR_MASK (0x000007FF)
+
+#define DBRP_EVDO_HARQ_RD_DATA_MEM_DATA_LSB (0)
+#define DBRP_EVDO_HARQ_RD_DATA_MEM_DATA_WIDTH (32)
+#define DBRP_EVDO_HARQ_RD_DATA_MEM_DATA_MASK (0xFFFFFFFF)
+
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_3_LSB (24)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_3_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_3_MASK (0x7F000000)
+
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_2_LSB (16)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_2_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_2_MASK (0x007F0000)
+
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_1_LSB (8)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_1_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_1_MASK (0x00007F00)
+
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_0_LSB (0)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_0_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_03_ABSACC_0_MASK (0x0000007F)
+
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_7_LSB (24)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_7_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_7_MASK (0x7F000000)
+
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_6_LSB (16)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_6_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_6_MASK (0x007F0000)
+
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_5_LSB (8)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_5_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_5_MASK (0x00007F00)
+
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_4_LSB (0)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_4_WIDTH (7)
+#define DBRP_EVDO_HARQ_ABSACC_47_ABSACC_4_MASK (0x0000007F)
+
+#define DBRP_EVDO_DBG0_DET_CHNL_ITER_LSB (12)
+#define DBRP_EVDO_DBG0_DET_CHNL_ITER_WIDTH (2)
+#define DBRP_EVDO_DBG0_DET_CHNL_ITER_MASK (0x00003000)
+
+#define DBRP_EVDO_DBG0_MAIN_FSM_CS_LSB (0)
+#define DBRP_EVDO_DBG0_MAIN_FSM_CS_WIDTH (9)
+#define DBRP_EVDO_DBG0_MAIN_FSM_CS_MASK (0x000001FF)
+
+#define DBRP_EVDO_PWR_CFG_PWR_MODE_LSB (15)
+#define DBRP_EVDO_PWR_CFG_PWR_MODE_WIDTH (1)
+#define DBRP_EVDO_PWR_CFG_PWR_MODE_MASK (0x00008000)
+#define DBRP_EVDO_PWR_CFG_PWR_MODE_BIT (0x00008000)
+#define DBRP_EVDO_HARQ_PARAM_HARQ_BUF_SIZE_LSB (16)
+#define DBRP_EVDO_HARQ_PARAM_HARQ_BUF_SIZE_WIDTH (13)
+#define DBRP_EVDO_HARQ_PARAM_HARQ_BUF_SIZE_MASK (0x1FFF0000)
+
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT2_SIZE_LSB (5)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT2_SIZE_WIDTH (1)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT2_SIZE_MASK (0x00000020)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT2_SIZE_BIT (0x00000020)
+
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT1_SIZE_LSB (3)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT1_SIZE_WIDTH (2)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT1_SIZE_MASK (0x00000018)
+
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT0_SIZE_LSB (0)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT0_SIZE_WIDTH (2)
+#define DBRP_EVDO_HARQ_PARAM_PRE_QUAR_SLT0_SIZE_MASK (0x00000003)
+
+#define DBRP_EVDO_CH0_PARAM1_INTLV_D_LSB (23)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_D_WIDTH (4)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_D_MASK (0x07800000)
+
+#define DBRP_EVDO_CH0_PARAM1_INTLV_M_LSB (20)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_M_WIDTH (3)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_M_MASK (0x00700000)
+
+#define DBRP_EVDO_CH0_PARAM1_INTLV_R_LSB (17)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_R_WIDTH (3)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_R_MASK (0x000E0000)
+
+#define DBRP_EVDO_CH0_PARAM1_INTLV_K_LSB (14)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_K_WIDTH (3)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_K_MASK (0x0001C000)
+
+#define DBRP_EVDO_CH0_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_EVDO_CH0_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH0_PARAM2_CODE_RATE_LSB (20)
+#define DBRP_EVDO_CH0_PARAM2_CODE_RATE_WIDTH (1)
+#define DBRP_EVDO_CH0_PARAM2_CODE_RATE_MASK (0x00100000)
+#define DBRP_EVDO_CH0_PARAM2_CODE_RATE_BIT (0x00100000)
+
+#define DBRP_EVDO_CH0_PARAM2_ENCODED_BITS_LSB (6)
+#define DBRP_EVDO_CH0_PARAM2_ENCODED_BITS_WIDTH (14)
+#define DBRP_EVDO_CH0_PARAM2_ENCODED_BITS_MASK (0x000FFFC0)
+
+#define DBRP_EVDO_CH0_PARAM2_MOD_LSB (4)
+#define DBRP_EVDO_CH0_PARAM2_MOD_WIDTH (2)
+#define DBRP_EVDO_CH0_PARAM2_MOD_MASK (0x00000030)
+
+#define DBRP_EVDO_CH0_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_EVDO_CH0_PARAM2_REPEAT_RATE_WIDTH (4)
+#define DBRP_EVDO_CH0_PARAM2_REPEAT_RATE_MASK (0x0000000F)
+
+#define DBRP_EVDO_CH0_PARAM3_SCRAMB_INIT_13_0_LSB (0)
+#define DBRP_EVDO_CH0_PARAM3_SCRAMB_INIT_13_0_WIDTH (14)
+#define DBRP_EVDO_CH0_PARAM3_SCRAMB_INIT_13_0_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH1_PARAM1_INTLV_D_LSB (23)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_D_WIDTH (4)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_D_MASK (0x07800000)
+
+#define DBRP_EVDO_CH1_PARAM1_INTLV_M_LSB (20)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_M_WIDTH (3)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_M_MASK (0x00700000)
+
+#define DBRP_EVDO_CH1_PARAM1_INTLV_R_LSB (17)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_R_WIDTH (3)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_R_MASK (0x000E0000)
+
+#define DBRP_EVDO_CH1_PARAM1_INTLV_K_LSB (14)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_K_WIDTH (3)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_K_MASK (0x0001C000)
+
+#define DBRP_EVDO_CH1_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_EVDO_CH1_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH1_PARAM2_CODE_RATE_LSB (20)
+#define DBRP_EVDO_CH1_PARAM2_CODE_RATE_WIDTH (1)
+#define DBRP_EVDO_CH1_PARAM2_CODE_RATE_MASK (0x00100000)
+#define DBRP_EVDO_CH1_PARAM2_CODE_RATE_BIT (0x00100000)
+
+#define DBRP_EVDO_CH1_PARAM2_ENCODED_BITS_LSB (6)
+#define DBRP_EVDO_CH1_PARAM2_ENCODED_BITS_WIDTH (14)
+#define DBRP_EVDO_CH1_PARAM2_ENCODED_BITS_MASK (0x000FFFC0)
+
+#define DBRP_EVDO_CH1_PARAM2_MOD_LSB (4)
+#define DBRP_EVDO_CH1_PARAM2_MOD_WIDTH (2)
+#define DBRP_EVDO_CH1_PARAM2_MOD_MASK (0x00000030)
+
+#define DBRP_EVDO_CH1_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_EVDO_CH1_PARAM2_REPEAT_RATE_WIDTH (4)
+#define DBRP_EVDO_CH1_PARAM2_REPEAT_RATE_MASK (0x0000000F)
+
+#define DBRP_EVDO_CH1_PARAM3_SCRAMB_INIT_13_0_LSB (0)
+#define DBRP_EVDO_CH1_PARAM3_SCRAMB_INIT_13_0_WIDTH (14)
+#define DBRP_EVDO_CH1_PARAM3_SCRAMB_INIT_13_0_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH2_PARAM1_INTLV_D_LSB (23)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_D_WIDTH (4)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_D_MASK (0x07800000)
+
+#define DBRP_EVDO_CH2_PARAM1_INTLV_M_LSB (20)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_M_WIDTH (3)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_M_MASK (0x00700000)
+
+#define DBRP_EVDO_CH2_PARAM1_INTLV_R_LSB (17)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_R_WIDTH (3)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_R_MASK (0x000E0000)
+
+#define DBRP_EVDO_CH2_PARAM1_INTLV_K_LSB (14)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_K_WIDTH (3)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_K_MASK (0x0001C000)
+
+#define DBRP_EVDO_CH2_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_EVDO_CH2_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH2_PARAM2_CODE_RATE_LSB (20)
+#define DBRP_EVDO_CH2_PARAM2_CODE_RATE_WIDTH (1)
+#define DBRP_EVDO_CH2_PARAM2_CODE_RATE_MASK (0x00100000)
+#define DBRP_EVDO_CH2_PARAM2_CODE_RATE_BIT (0x00100000)
+
+#define DBRP_EVDO_CH2_PARAM2_ENCODED_BITS_LSB (6)
+#define DBRP_EVDO_CH2_PARAM2_ENCODED_BITS_WIDTH (14)
+#define DBRP_EVDO_CH2_PARAM2_ENCODED_BITS_MASK (0x000FFFC0)
+
+#define DBRP_EVDO_CH2_PARAM2_MOD_LSB (4)
+#define DBRP_EVDO_CH2_PARAM2_MOD_WIDTH (2)
+#define DBRP_EVDO_CH2_PARAM2_MOD_MASK (0x00000030)
+
+#define DBRP_EVDO_CH2_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_EVDO_CH2_PARAM2_REPEAT_RATE_WIDTH (4)
+#define DBRP_EVDO_CH2_PARAM2_REPEAT_RATE_MASK (0x0000000F)
+
+#define DBRP_EVDO_CH2_PARAM3_SCRAMB_INIT_13_0_LSB (0)
+#define DBRP_EVDO_CH2_PARAM3_SCRAMB_INIT_13_0_WIDTH (14)
+#define DBRP_EVDO_CH2_PARAM3_SCRAMB_INIT_13_0_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH3_PARAM1_INTLV_D_LSB (23)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_D_WIDTH (4)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_D_MASK (0x07800000)
+
+#define DBRP_EVDO_CH3_PARAM1_INTLV_M_LSB (20)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_M_WIDTH (3)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_M_MASK (0x00700000)
+
+#define DBRP_EVDO_CH3_PARAM1_INTLV_R_LSB (17)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_R_WIDTH (3)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_R_MASK (0x000E0000)
+
+#define DBRP_EVDO_CH3_PARAM1_INTLV_K_LSB (14)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_K_WIDTH (3)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_K_MASK (0x0001C000)
+
+#define DBRP_EVDO_CH3_PARAM1_INTLV_SIZE_LSB (0)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_SIZE_WIDTH (14)
+#define DBRP_EVDO_CH3_PARAM1_INTLV_SIZE_MASK (0x00003FFF)
+
+#define DBRP_EVDO_CH3_PARAM2_CODE_RATE_LSB (20)
+#define DBRP_EVDO_CH3_PARAM2_CODE_RATE_WIDTH (1)
+#define DBRP_EVDO_CH3_PARAM2_CODE_RATE_MASK (0x00100000)
+#define DBRP_EVDO_CH3_PARAM2_CODE_RATE_BIT (0x00100000)
+
+#define DBRP_EVDO_CH3_PARAM2_ENCODED_BITS_LSB (6)
+#define DBRP_EVDO_CH3_PARAM2_ENCODED_BITS_WIDTH (14)
+#define DBRP_EVDO_CH3_PARAM2_ENCODED_BITS_MASK (0x000FFFC0)
+
+#define DBRP_EVDO_CH3_PARAM2_MOD_LSB (4)
+#define DBRP_EVDO_CH3_PARAM2_MOD_WIDTH (2)
+#define DBRP_EVDO_CH3_PARAM2_MOD_MASK (0x00000030)
+
+#define DBRP_EVDO_CH3_PARAM2_REPEAT_RATE_LSB (0)
+#define DBRP_EVDO_CH3_PARAM2_REPEAT_RATE_WIDTH (4)
+#define DBRP_EVDO_CH3_PARAM2_REPEAT_RATE_MASK (0x0000000F)
+
+#define DBRP_EVDO_CH3_PARAM3_SCRAMB_INIT_13_0_LSB (0)
+#define DBRP_EVDO_CH3_PARAM3_SCRAMB_INIT_13_0_WIDTH (14)
+#define DBRP_EVDO_CH3_PARAM3_SCRAMB_INIT_13_0_MASK (0x00003FFF)
+
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT1_LSB (16)
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT1_WIDTH (12)
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT1_MASK (0x0FFF0000)
+
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT0_LSB (0)
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT0_WIDTH (12)
+#define DBRP_EVDO_C2I_PARAM0_C2I_QUAR_SLOT0_MASK (0x00000FFF)
+
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT3_LSB (16)
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT3_WIDTH (12)
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT3_MASK (0x0FFF0000)
+
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT2_LSB (0)
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT2_WIDTH (12)
+#define DBRP_EVDO_C2I_PARAM1_C2I_QUAR_SLOT2_MASK (0x00000FFF)
+
+
+#endif //#ifndef _CPH_EVDO_RXBRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen.h b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen.h
new file mode 100644
index 0000000..1b6cd4b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphevdorxeventgen_93.h"
+#elif defined(__MD95__)
+#include "cphevdorxeventgen_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphevdorxeventgen_97.h"
+#else
+#error "[ERROR] Invalid MD generation" modification for build error
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_93.h b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_93.h
new file mode 100644
index 0000000..2d107e7
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_93.h
@@ -0,0 +1,587 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_RX_EVENTGEN_H_
+#define _CPH_EVDO_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define STDO_RX_EVENTGEN_REG_BASE (0xA7070000)
+#define STDO_RX_EVENTGEN_end (STDO_RX_EVENTGEN_REG_BASE + 0x3000 + 34*4)
+
+
+#define STDO_RXBRP_EVENT_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0000))
+#define STDO_RXBRP_EVENT_MASK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0004))
+#define STDO_uSIP_IRQ_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0008))
+#define STDO_uSIP_IRQ_MASK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x000C))
+#define STDO_uSIP_IRQ_CLR ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0010))
+#define STDO_uSIP_IRQ_SRC ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0014))
+#define STDO_uSIP_IRQ_ISR ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0018))
+#define STDO_RXDFE_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x001C))
+#define STDO_RXDFE_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0020))
+#define STDO_DBG_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0024))
+#define STDO_DBG_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0028))
+#define STDO_TTR_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x002C))
+#define STDO_TTR_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0030))
+#define STDO_DVFS_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0034))
+#define STDO_RX_BSIRD_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0F30 + (n)*4)) //n is from 0 to 2
+#define STDO_RX_BSI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x1030 + (n)*4)) //n is from 0 to 44
+#define STDO_RX_MIPI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x2000 + (n)*4)) //n is from 0 to 76
+#define STDO_RX_BPI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x3000 + (n)*4)) //n is from 0 to 33
+
+
+
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define STDO_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define STDO_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define STDO_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define STDO_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define STDO_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define STDO_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define STDO_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define STDO_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define STDO_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define STDO_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define STDO_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define STDO_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define STDO_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define STDO_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define STDO_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define STDO_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define STDO_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define STDO_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define STDO_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define STDO_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define STDO_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define STDO_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define STDO_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define STDO_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define STDO_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define STDO_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define STDO_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define STDO_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define STDO_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define STDO_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define STDO_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define STDO_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define STDO_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define STDO_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define STDO_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define STDO_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define STDO_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define STDO_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define STDO_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define STDO_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define STDO_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define STDO_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define STDO_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define STDO_uSIP_IRQ_MASK_MSK15_LSB (15)
+#define STDO_uSIP_IRQ_MASK_MSK15_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_MASK_MSK15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_MASK_MSK14_LSB (14)
+#define STDO_uSIP_IRQ_MASK_MSK14_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_MASK_MSK14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_MASK_MSK13_LSB (13)
+#define STDO_uSIP_IRQ_MASK_MSK13_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_MASK_MSK13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_MASK_MSK12_LSB (12)
+#define STDO_uSIP_IRQ_MASK_MSK12_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_MASK_MSK12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_MASK_MSK11_LSB (11)
+#define STDO_uSIP_IRQ_MASK_MSK11_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_MASK_MSK11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_MASK_MSK10_LSB (10)
+#define STDO_uSIP_IRQ_MASK_MSK10_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_MASK_MSK10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_MASK_MSK9_LSB (9)
+#define STDO_uSIP_IRQ_MASK_MSK9_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_MASK_MSK9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_MASK_MSK8_LSB (8)
+#define STDO_uSIP_IRQ_MASK_MSK8_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_MASK_MSK8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_MASK_MSK7_LSB (7)
+#define STDO_uSIP_IRQ_MASK_MSK7_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_MASK_MSK7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_MASK_MSK6_LSB (6)
+#define STDO_uSIP_IRQ_MASK_MSK6_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_MASK_MSK6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_MASK_MSK5_LSB (5)
+#define STDO_uSIP_IRQ_MASK_MSK5_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_MASK_MSK5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_MASK_MSK4_LSB (4)
+#define STDO_uSIP_IRQ_MASK_MSK4_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_MASK_MSK4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_MASK_MSK3_LSB (3)
+#define STDO_uSIP_IRQ_MASK_MSK3_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_MASK_MSK3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_MASK_MSK2_LSB (2)
+#define STDO_uSIP_IRQ_MASK_MSK2_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_MASK_MSK2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_MASK_MSK1_LSB (1)
+#define STDO_uSIP_IRQ_MASK_MSK1_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_MASK_MSK1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_MASK_MSK0_LSB (0)
+#define STDO_uSIP_IRQ_MASK_MSK0_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_MASK_MSK0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_CLR_CLR15_LSB (15)
+#define STDO_uSIP_IRQ_CLR_CLR15_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_CLR_CLR15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_CLR_CLR14_LSB (14)
+#define STDO_uSIP_IRQ_CLR_CLR14_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_CLR_CLR14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_CLR_CLR13_LSB (13)
+#define STDO_uSIP_IRQ_CLR_CLR13_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_CLR_CLR13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_CLR_CLR12_LSB (12)
+#define STDO_uSIP_IRQ_CLR_CLR12_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_CLR_CLR12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_CLR_CLR11_LSB (11)
+#define STDO_uSIP_IRQ_CLR_CLR11_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_CLR_CLR11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_CLR_CLR10_LSB (10)
+#define STDO_uSIP_IRQ_CLR_CLR10_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_CLR_CLR10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_CLR_CLR9_LSB (9)
+#define STDO_uSIP_IRQ_CLR_CLR9_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_CLR_CLR9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_CLR_CLR8_LSB (8)
+#define STDO_uSIP_IRQ_CLR_CLR8_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_CLR_CLR8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_CLR_CLR7_LSB (7)
+#define STDO_uSIP_IRQ_CLR_CLR7_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_CLR_CLR7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_CLR_CLR6_LSB (6)
+#define STDO_uSIP_IRQ_CLR_CLR6_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_CLR_CLR6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_CLR_CLR5_LSB (5)
+#define STDO_uSIP_IRQ_CLR_CLR5_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_CLR_CLR5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_CLR_CLR4_LSB (4)
+#define STDO_uSIP_IRQ_CLR_CLR4_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_CLR_CLR4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_CLR_CLR3_LSB (3)
+#define STDO_uSIP_IRQ_CLR_CLR3_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_CLR_CLR3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_CLR_CLR2_LSB (2)
+#define STDO_uSIP_IRQ_CLR_CLR2_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_CLR_CLR2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_CLR_CLR1_LSB (1)
+#define STDO_uSIP_IRQ_CLR_CLR1_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_CLR_CLR1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_CLR_CLR0_LSB (0)
+#define STDO_uSIP_IRQ_CLR_CLR0_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_CLR_CLR0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_SRC_SRC15_LSB (15)
+#define STDO_uSIP_IRQ_SRC_SRC15_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_SRC_SRC15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_SRC_SRC14_LSB (14)
+#define STDO_uSIP_IRQ_SRC_SRC14_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_SRC_SRC14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_SRC_SRC13_LSB (13)
+#define STDO_uSIP_IRQ_SRC_SRC13_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_SRC_SRC13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_SRC_SRC12_LSB (12)
+#define STDO_uSIP_IRQ_SRC_SRC12_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_SRC_SRC12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_SRC_SRC11_LSB (11)
+#define STDO_uSIP_IRQ_SRC_SRC11_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_SRC_SRC11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_SRC_SRC10_LSB (10)
+#define STDO_uSIP_IRQ_SRC_SRC10_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_SRC_SRC10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_SRC_SRC9_LSB (9)
+#define STDO_uSIP_IRQ_SRC_SRC9_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_SRC_SRC9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_SRC_SRC8_LSB (8)
+#define STDO_uSIP_IRQ_SRC_SRC8_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_SRC_SRC8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_SRC_SRC7_LSB (7)
+#define STDO_uSIP_IRQ_SRC_SRC7_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_SRC_SRC7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_SRC_SRC6_LSB (6)
+#define STDO_uSIP_IRQ_SRC_SRC6_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_SRC_SRC6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_SRC_SRC5_LSB (5)
+#define STDO_uSIP_IRQ_SRC_SRC5_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_SRC_SRC5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_SRC_SRC4_LSB (4)
+#define STDO_uSIP_IRQ_SRC_SRC4_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_SRC_SRC4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_SRC_SRC3_LSB (3)
+#define STDO_uSIP_IRQ_SRC_SRC3_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_SRC_SRC3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_SRC_SRC2_LSB (2)
+#define STDO_uSIP_IRQ_SRC_SRC2_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_SRC_SRC2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_SRC_SRC1_LSB (1)
+#define STDO_uSIP_IRQ_SRC_SRC1_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_SRC_SRC1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_SRC_SRC0_LSB (0)
+#define STDO_uSIP_IRQ_SRC_SRC0_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_SRC_SRC0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_ISR_ISR15_LSB (15)
+#define STDO_uSIP_IRQ_ISR_ISR15_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_ISR_ISR15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_ISR_ISR14_LSB (14)
+#define STDO_uSIP_IRQ_ISR_ISR14_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_ISR_ISR14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_ISR_ISR13_LSB (13)
+#define STDO_uSIP_IRQ_ISR_ISR13_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_ISR_ISR13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_ISR_ISR12_LSB (12)
+#define STDO_uSIP_IRQ_ISR_ISR12_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_ISR_ISR12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_ISR_ISR11_LSB (11)
+#define STDO_uSIP_IRQ_ISR_ISR11_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_ISR_ISR11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_ISR_ISR10_LSB (10)
+#define STDO_uSIP_IRQ_ISR_ISR10_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_ISR_ISR10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_ISR_ISR9_LSB (9)
+#define STDO_uSIP_IRQ_ISR_ISR9_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_ISR_ISR9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_ISR_ISR8_LSB (8)
+#define STDO_uSIP_IRQ_ISR_ISR8_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_ISR_ISR8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_ISR_ISR7_LSB (7)
+#define STDO_uSIP_IRQ_ISR_ISR7_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_ISR_ISR7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_ISR_ISR6_LSB (6)
+#define STDO_uSIP_IRQ_ISR_ISR6_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_ISR_ISR6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_ISR_ISR5_LSB (5)
+#define STDO_uSIP_IRQ_ISR_ISR5_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_ISR_ISR5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_ISR_ISR4_LSB (4)
+#define STDO_uSIP_IRQ_ISR_ISR4_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_ISR_ISR4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_ISR_ISR3_LSB (3)
+#define STDO_uSIP_IRQ_ISR_ISR3_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_ISR_ISR3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_ISR_ISR2_LSB (2)
+#define STDO_uSIP_IRQ_ISR_ISR2_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_ISR_ISR2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_ISR_ISR1_LSB (1)
+#define STDO_uSIP_IRQ_ISR_ISR1_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_ISR_ISR1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_ISR_ISR0_LSB (0)
+#define STDO_uSIP_IRQ_ISR_ISR0_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_ISR_ISR0_BIT (0x00000001)
+
+#define STDO_RXDFE_ON_EVENT_EN_LSB (31)
+#define STDO_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RXDFE_OFF_EVENT_EN_LSB (31)
+#define STDO_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DBG_ON_EVENT_EN_LSB (31)
+#define STDO_DBG_ON_EVENT_EN_WIDTH (1)
+#define STDO_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_DBG_OFF_EVENT_EN_LSB (31)
+#define STDO_DBG_OFF_EVENT_EN_WIDTH (1)
+#define STDO_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_TTR_ON_EVENT_EN_LSB (31)
+#define STDO_TTR_ON_EVENT_EN_WIDTH (1)
+#define STDO_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_TTR_OFF_EVENT_EN_LSB (31)
+#define STDO_TTR_OFF_EVENT_EN_WIDTH (1)
+#define STDO_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DVFS_EVENT_EN_LSB (31)
+#define STDO_DVFS_EVENT_EN_WIDTH (1)
+#define STDO_DVFS_EVENT_EN_MASK (0x80000000)
+#define STDO_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DVFS_EVENT_MODE_LSB (30)
+#define STDO_DVFS_EVENT_MODE_WIDTH (1)
+#define STDO_DVFS_EVENT_MODE_MASK (0x40000000)
+#define STDO_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BSIRD_EVENT_EN_LSB (31)
+#define STDO_RX_BSIRD_EVENT_EN_WIDTH (1)
+#define STDO_RX_BSIRD_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BSIRD_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_LSB (2)
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_WIDTH (18)
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BSI_EVENT_EN_LSB (31)
+#define STDO_RX_BSI_EVENT_EN_WIDTH (1)
+#define STDO_RX_BSI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BSI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_LSB (2)
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_WIDTH (18)
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_MIPI_EVENT_EN_LSB (31)
+#define STDO_RX_MIPI_EVENT_EN_WIDTH (1)
+#define STDO_RX_MIPI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_MIPI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_LSB (2)
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_WIDTH (18)
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BPI_EVENT_EN_LSB (31)
+#define STDO_RX_BPI_EVENT_EN_WIDTH (1)
+#define STDO_RX_BPI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BPI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_LSB (2)
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_WIDTH (18)
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_MASK (0x000FFFFC)
+
+#endif //#ifndef _CPH_EVDO_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_95.h b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_95.h
new file mode 100644
index 0000000..17cfaf1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_95.h
@@ -0,0 +1,587 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_RX_EVENTGEN_H_
+#define _CPH_EVDO_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define STDO_RX_EVENTGEN_REG_BASE (0xA6220000)
+#define STDO_RX_EVENTGEN_end (STDO_RX_EVENTGEN_REG_BASE + 0x0130 + 1*4)
+
+
+#define STDO_RXBRP_EVENT_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0000))
+#define STDO_RXBRP_EVENT_MASK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0004))
+#define STDO_uSIP_IRQ_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0008))
+#define STDO_uSIP_IRQ_MASK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x000C))
+#define STDO_uSIP_IRQ_CLR ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0010))
+#define STDO_uSIP_IRQ_SRC ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0014))
+#define STDO_uSIP_IRQ_ISR ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0018))
+#define STDO_RXDFE_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x001C))
+#define STDO_RXDFE_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0020))
+#define STDO_DBG_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0024))
+#define STDO_DBG_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0028))
+#define STDO_TTR_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x002C))
+#define STDO_TTR_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0030))
+#define STDO_DVFS_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0034))
+#define STDO_RX_BSIRD_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0F30 + (n)*4)) //n is from 0 to 2
+#define STDO_RX_BSI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x1030 + (n)*4)) //n is from 0 to 44
+#define STDO_RX_MIPI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x2000 + (n)*4)) //n is from 0 to 76
+#define STDO_RX_BPI_EVENT(n) ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x3000 + (n)*4)) //n is from 0 to 33
+
+
+
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define STDO_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define STDO_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define STDO_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define STDO_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define STDO_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define STDO_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define STDO_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define STDO_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define STDO_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define STDO_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define STDO_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define STDO_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define STDO_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define STDO_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define STDO_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define STDO_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define STDO_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define STDO_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define STDO_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define STDO_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define STDO_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define STDO_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define STDO_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define STDO_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define STDO_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define STDO_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define STDO_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define STDO_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define STDO_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define STDO_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define STDO_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define STDO_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define STDO_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define STDO_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define STDO_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define STDO_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define STDO_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define STDO_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define STDO_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define STDO_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define STDO_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define STDO_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define STDO_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define STDO_uSIP_IRQ_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define STDO_uSIP_IRQ_MASK_MSK15_LSB (15)
+#define STDO_uSIP_IRQ_MASK_MSK15_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_MASK_MSK15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_MASK_MSK14_LSB (14)
+#define STDO_uSIP_IRQ_MASK_MSK14_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_MASK_MSK14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_MASK_MSK13_LSB (13)
+#define STDO_uSIP_IRQ_MASK_MSK13_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_MASK_MSK13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_MASK_MSK12_LSB (12)
+#define STDO_uSIP_IRQ_MASK_MSK12_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_MASK_MSK12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_MASK_MSK11_LSB (11)
+#define STDO_uSIP_IRQ_MASK_MSK11_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_MASK_MSK11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_MASK_MSK10_LSB (10)
+#define STDO_uSIP_IRQ_MASK_MSK10_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_MASK_MSK10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_MASK_MSK9_LSB (9)
+#define STDO_uSIP_IRQ_MASK_MSK9_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_MASK_MSK9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_MASK_MSK8_LSB (8)
+#define STDO_uSIP_IRQ_MASK_MSK8_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_MASK_MSK8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_MASK_MSK7_LSB (7)
+#define STDO_uSIP_IRQ_MASK_MSK7_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_MASK_MSK7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_MASK_MSK6_LSB (6)
+#define STDO_uSIP_IRQ_MASK_MSK6_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_MASK_MSK6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_MASK_MSK5_LSB (5)
+#define STDO_uSIP_IRQ_MASK_MSK5_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_MASK_MSK5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_MASK_MSK4_LSB (4)
+#define STDO_uSIP_IRQ_MASK_MSK4_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_MASK_MSK4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_MASK_MSK3_LSB (3)
+#define STDO_uSIP_IRQ_MASK_MSK3_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_MASK_MSK3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_MASK_MSK2_LSB (2)
+#define STDO_uSIP_IRQ_MASK_MSK2_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_MASK_MSK2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_MASK_MSK1_LSB (1)
+#define STDO_uSIP_IRQ_MASK_MSK1_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_MASK_MSK1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_MASK_MSK0_LSB (0)
+#define STDO_uSIP_IRQ_MASK_MSK0_WIDTH (1)
+#define STDO_uSIP_IRQ_MASK_MSK0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_MASK_MSK0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_CLR_CLR15_LSB (15)
+#define STDO_uSIP_IRQ_CLR_CLR15_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_CLR_CLR15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_CLR_CLR14_LSB (14)
+#define STDO_uSIP_IRQ_CLR_CLR14_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_CLR_CLR14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_CLR_CLR13_LSB (13)
+#define STDO_uSIP_IRQ_CLR_CLR13_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_CLR_CLR13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_CLR_CLR12_LSB (12)
+#define STDO_uSIP_IRQ_CLR_CLR12_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_CLR_CLR12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_CLR_CLR11_LSB (11)
+#define STDO_uSIP_IRQ_CLR_CLR11_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_CLR_CLR11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_CLR_CLR10_LSB (10)
+#define STDO_uSIP_IRQ_CLR_CLR10_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_CLR_CLR10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_CLR_CLR9_LSB (9)
+#define STDO_uSIP_IRQ_CLR_CLR9_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_CLR_CLR9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_CLR_CLR8_LSB (8)
+#define STDO_uSIP_IRQ_CLR_CLR8_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_CLR_CLR8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_CLR_CLR7_LSB (7)
+#define STDO_uSIP_IRQ_CLR_CLR7_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_CLR_CLR7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_CLR_CLR6_LSB (6)
+#define STDO_uSIP_IRQ_CLR_CLR6_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_CLR_CLR6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_CLR_CLR5_LSB (5)
+#define STDO_uSIP_IRQ_CLR_CLR5_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_CLR_CLR5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_CLR_CLR4_LSB (4)
+#define STDO_uSIP_IRQ_CLR_CLR4_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_CLR_CLR4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_CLR_CLR3_LSB (3)
+#define STDO_uSIP_IRQ_CLR_CLR3_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_CLR_CLR3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_CLR_CLR2_LSB (2)
+#define STDO_uSIP_IRQ_CLR_CLR2_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_CLR_CLR2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_CLR_CLR1_LSB (1)
+#define STDO_uSIP_IRQ_CLR_CLR1_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_CLR_CLR1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_CLR_CLR0_LSB (0)
+#define STDO_uSIP_IRQ_CLR_CLR0_WIDTH (1)
+#define STDO_uSIP_IRQ_CLR_CLR0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_CLR_CLR0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_SRC_SRC15_LSB (15)
+#define STDO_uSIP_IRQ_SRC_SRC15_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_SRC_SRC15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_SRC_SRC14_LSB (14)
+#define STDO_uSIP_IRQ_SRC_SRC14_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_SRC_SRC14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_SRC_SRC13_LSB (13)
+#define STDO_uSIP_IRQ_SRC_SRC13_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_SRC_SRC13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_SRC_SRC12_LSB (12)
+#define STDO_uSIP_IRQ_SRC_SRC12_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_SRC_SRC12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_SRC_SRC11_LSB (11)
+#define STDO_uSIP_IRQ_SRC_SRC11_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_SRC_SRC11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_SRC_SRC10_LSB (10)
+#define STDO_uSIP_IRQ_SRC_SRC10_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_SRC_SRC10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_SRC_SRC9_LSB (9)
+#define STDO_uSIP_IRQ_SRC_SRC9_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_SRC_SRC9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_SRC_SRC8_LSB (8)
+#define STDO_uSIP_IRQ_SRC_SRC8_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_SRC_SRC8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_SRC_SRC7_LSB (7)
+#define STDO_uSIP_IRQ_SRC_SRC7_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_SRC_SRC7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_SRC_SRC6_LSB (6)
+#define STDO_uSIP_IRQ_SRC_SRC6_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_SRC_SRC6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_SRC_SRC5_LSB (5)
+#define STDO_uSIP_IRQ_SRC_SRC5_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_SRC_SRC5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_SRC_SRC4_LSB (4)
+#define STDO_uSIP_IRQ_SRC_SRC4_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_SRC_SRC4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_SRC_SRC3_LSB (3)
+#define STDO_uSIP_IRQ_SRC_SRC3_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_SRC_SRC3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_SRC_SRC2_LSB (2)
+#define STDO_uSIP_IRQ_SRC_SRC2_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_SRC_SRC2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_SRC_SRC1_LSB (1)
+#define STDO_uSIP_IRQ_SRC_SRC1_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_SRC_SRC1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_SRC_SRC0_LSB (0)
+#define STDO_uSIP_IRQ_SRC_SRC0_WIDTH (1)
+#define STDO_uSIP_IRQ_SRC_SRC0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_SRC_SRC0_BIT (0x00000001)
+
+#define STDO_uSIP_IRQ_ISR_ISR15_LSB (15)
+#define STDO_uSIP_IRQ_ISR_ISR15_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR15_MASK (0x00008000)
+#define STDO_uSIP_IRQ_ISR_ISR15_BIT (0x00008000)
+
+#define STDO_uSIP_IRQ_ISR_ISR14_LSB (14)
+#define STDO_uSIP_IRQ_ISR_ISR14_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR14_MASK (0x00004000)
+#define STDO_uSIP_IRQ_ISR_ISR14_BIT (0x00004000)
+
+#define STDO_uSIP_IRQ_ISR_ISR13_LSB (13)
+#define STDO_uSIP_IRQ_ISR_ISR13_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR13_MASK (0x00002000)
+#define STDO_uSIP_IRQ_ISR_ISR13_BIT (0x00002000)
+
+#define STDO_uSIP_IRQ_ISR_ISR12_LSB (12)
+#define STDO_uSIP_IRQ_ISR_ISR12_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR12_MASK (0x00001000)
+#define STDO_uSIP_IRQ_ISR_ISR12_BIT (0x00001000)
+
+#define STDO_uSIP_IRQ_ISR_ISR11_LSB (11)
+#define STDO_uSIP_IRQ_ISR_ISR11_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR11_MASK (0x00000800)
+#define STDO_uSIP_IRQ_ISR_ISR11_BIT (0x00000800)
+
+#define STDO_uSIP_IRQ_ISR_ISR10_LSB (10)
+#define STDO_uSIP_IRQ_ISR_ISR10_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR10_MASK (0x00000400)
+#define STDO_uSIP_IRQ_ISR_ISR10_BIT (0x00000400)
+
+#define STDO_uSIP_IRQ_ISR_ISR9_LSB (9)
+#define STDO_uSIP_IRQ_ISR_ISR9_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR9_MASK (0x00000200)
+#define STDO_uSIP_IRQ_ISR_ISR9_BIT (0x00000200)
+
+#define STDO_uSIP_IRQ_ISR_ISR8_LSB (8)
+#define STDO_uSIP_IRQ_ISR_ISR8_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR8_MASK (0x00000100)
+#define STDO_uSIP_IRQ_ISR_ISR8_BIT (0x00000100)
+
+#define STDO_uSIP_IRQ_ISR_ISR7_LSB (7)
+#define STDO_uSIP_IRQ_ISR_ISR7_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR7_MASK (0x00000080)
+#define STDO_uSIP_IRQ_ISR_ISR7_BIT (0x00000080)
+
+#define STDO_uSIP_IRQ_ISR_ISR6_LSB (6)
+#define STDO_uSIP_IRQ_ISR_ISR6_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR6_MASK (0x00000040)
+#define STDO_uSIP_IRQ_ISR_ISR6_BIT (0x00000040)
+
+#define STDO_uSIP_IRQ_ISR_ISR5_LSB (5)
+#define STDO_uSIP_IRQ_ISR_ISR5_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR5_MASK (0x00000020)
+#define STDO_uSIP_IRQ_ISR_ISR5_BIT (0x00000020)
+
+#define STDO_uSIP_IRQ_ISR_ISR4_LSB (4)
+#define STDO_uSIP_IRQ_ISR_ISR4_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR4_MASK (0x00000010)
+#define STDO_uSIP_IRQ_ISR_ISR4_BIT (0x00000010)
+
+#define STDO_uSIP_IRQ_ISR_ISR3_LSB (3)
+#define STDO_uSIP_IRQ_ISR_ISR3_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_ISR_ISR3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_ISR_ISR2_LSB (2)
+#define STDO_uSIP_IRQ_ISR_ISR2_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_ISR_ISR2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_ISR_ISR1_LSB (1)
+#define STDO_uSIP_IRQ_ISR_ISR1_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_ISR_ISR1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_ISR_ISR0_LSB (0)
+#define STDO_uSIP_IRQ_ISR_ISR0_WIDTH (1)
+#define STDO_uSIP_IRQ_ISR_ISR0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_ISR_ISR0_BIT (0x00000001)
+
+#define STDO_RXDFE_ON_EVENT_EN_LSB (31)
+#define STDO_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RXDFE_OFF_EVENT_EN_LSB (31)
+#define STDO_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DBG_ON_EVENT_EN_LSB (31)
+#define STDO_DBG_ON_EVENT_EN_WIDTH (1)
+#define STDO_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_DBG_OFF_EVENT_EN_LSB (31)
+#define STDO_DBG_OFF_EVENT_EN_WIDTH (1)
+#define STDO_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_TTR_ON_EVENT_EN_LSB (31)
+#define STDO_TTR_ON_EVENT_EN_WIDTH (1)
+#define STDO_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_TTR_OFF_EVENT_EN_LSB (31)
+#define STDO_TTR_OFF_EVENT_EN_WIDTH (1)
+#define STDO_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DVFS_EVENT_EN_LSB (31)
+#define STDO_DVFS_EVENT_EN_WIDTH (1)
+#define STDO_DVFS_EVENT_EN_MASK (0x80000000)
+#define STDO_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DVFS_EVENT_MODE_LSB (30)
+#define STDO_DVFS_EVENT_MODE_WIDTH (1)
+#define STDO_DVFS_EVENT_MODE_MASK (0x40000000)
+#define STDO_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BSIRD_EVENT_EN_LSB (31)
+#define STDO_RX_BSIRD_EVENT_EN_WIDTH (1)
+#define STDO_RX_BSIRD_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BSIRD_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_LSB (2)
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_WIDTH (18)
+#define STDO_RX_BSIRD_EVENT_RX_BSIRD_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BSI_EVENT_EN_LSB (31)
+#define STDO_RX_BSI_EVENT_EN_WIDTH (1)
+#define STDO_RX_BSI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BSI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_LSB (2)
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_WIDTH (18)
+#define STDO_RX_BSI_EVENT_RX_BSI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_MIPI_EVENT_EN_LSB (31)
+#define STDO_RX_MIPI_EVENT_EN_WIDTH (1)
+#define STDO_RX_MIPI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_MIPI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_LSB (2)
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_WIDTH (18)
+#define STDO_RX_MIPI_EVENT_RX_MIPI_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RX_BPI_EVENT_EN_LSB (31)
+#define STDO_RX_BPI_EVENT_EN_WIDTH (1)
+#define STDO_RX_BPI_EVENT_EN_MASK (0x80000000)
+#define STDO_RX_BPI_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_LSB (2)
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_WIDTH (18)
+#define STDO_RX_BPI_EVENT_RX_BPI_EVENT_TIME_MASK (0x000FFFFC)
+
+#endif //#ifndef _CPH_EVDO_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_97.h b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_97.h
new file mode 100644
index 0000000..1899a14
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxeventgen_97.h
@@ -0,0 +1,369 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_RX_EVENTGEN_H_
+#define _CPH_EVDO_RX_EVENTGEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define STDO_RX_EVENTGEN_REG_BASE (0xA8210000)
+
+
+#define STDO_RX_EVENTGEN_end (STDO_RX_EVENTGEN_REG_BASE + 0x0100 + 1*4)
+
+
+
+
+
+#define STDO_RXBRP_EVENT_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0000))
+#define STDO_RXBRP_EVENT_MASK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0004))
+#define STDO_RXDFE_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x001C))
+#define STDO_RXDFE_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0020))
+#define STDO_DBG_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0024))
+#define STDO_DBG_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0028))
+#define STDO_TTR_ON_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x002C))
+#define STDO_TTR_OFF_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0030))
+#define STDO_DVFS_EVENT ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0034))
+#define STDO_WDG_EN ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0040))
+#define STDO_WDG_BOUND_OFFSET ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0044))
+#define STDO_WDG_CHKPT_UNCHK ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0048))
+#define STDO_WDG_CHKPT_TIME_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x004C))
+#define STDO_WDG_URGENT_SW_CLR ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0060))
+#define STDO_WDG_DBG ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0064))
+#define STDO_uSIP_IRQ_OFFSET_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0080))
+#define STDO_uSIP_IRQ_MASK_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0084))
+#define STDO_uSIP_IRQ_CLR_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0088))
+#define STDO_uSIP_IRQ_SRC_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x008C))
+#define STDO_uSIP_IRQ_ISR_0 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0090))
+#define STDO_uSIP_IRQ_OFFSET_1 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00A0))
+#define STDO_uSIP_IRQ_MASK_1 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00A4))
+#define STDO_uSIP_IRQ_CLR_1 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00A8))
+#define STDO_uSIP_IRQ_SRC_1 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00AC))
+#define STDO_uSIP_IRQ_ISR_1 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00B0))
+#define STDO_uSIP_IRQ_OFFSET_2 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00C0))
+#define STDO_uSIP_IRQ_MASK_2 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00C4))
+#define STDO_uSIP_IRQ_CLR_2 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00C8))
+#define STDO_uSIP_IRQ_SRC_2 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00CC))
+#define STDO_uSIP_IRQ_ISR_2 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00D0))
+#define STDO_uSIP_IRQ_OFFSET_3 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00E0))
+#define STDO_uSIP_IRQ_MASK_3 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00E4))
+#define STDO_uSIP_IRQ_CLR_3 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00E8))
+#define STDO_uSIP_IRQ_SRC_3 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00EC))
+#define STDO_uSIP_IRQ_ISR_3 ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x00F0))
+#define STDO_uSIP_IRQ_STATUS ((APBADDR32)(STDO_RX_EVENTGEN_REG_BASE + 0x0100))
+
+
+
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_WIDTH (12)
+#define STDO_RXBRP_EVENT_OFFSET_CHIP_OFFSET_MASK (0x00003FFC)
+
+#define STDO_RXBRP_EVENT_MASK_MSK15_LSB (15)
+#define STDO_RXBRP_EVENT_MASK_MSK15_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK15_MASK (0x00008000)
+#define STDO_RXBRP_EVENT_MASK_MSK15_BIT (0x00008000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK14_LSB (14)
+#define STDO_RXBRP_EVENT_MASK_MSK14_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK14_MASK (0x00004000)
+#define STDO_RXBRP_EVENT_MASK_MSK14_BIT (0x00004000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK13_LSB (13)
+#define STDO_RXBRP_EVENT_MASK_MSK13_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK13_MASK (0x00002000)
+#define STDO_RXBRP_EVENT_MASK_MSK13_BIT (0x00002000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK12_LSB (12)
+#define STDO_RXBRP_EVENT_MASK_MSK12_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK12_MASK (0x00001000)
+#define STDO_RXBRP_EVENT_MASK_MSK12_BIT (0x00001000)
+
+#define STDO_RXBRP_EVENT_MASK_MSK11_LSB (11)
+#define STDO_RXBRP_EVENT_MASK_MSK11_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK11_MASK (0x00000800)
+#define STDO_RXBRP_EVENT_MASK_MSK11_BIT (0x00000800)
+
+#define STDO_RXBRP_EVENT_MASK_MSK10_LSB (10)
+#define STDO_RXBRP_EVENT_MASK_MSK10_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK10_MASK (0x00000400)
+#define STDO_RXBRP_EVENT_MASK_MSK10_BIT (0x00000400)
+
+#define STDO_RXBRP_EVENT_MASK_MSK9_LSB (9)
+#define STDO_RXBRP_EVENT_MASK_MSK9_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK9_MASK (0x00000200)
+#define STDO_RXBRP_EVENT_MASK_MSK9_BIT (0x00000200)
+
+#define STDO_RXBRP_EVENT_MASK_MSK8_LSB (8)
+#define STDO_RXBRP_EVENT_MASK_MSK8_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK8_MASK (0x00000100)
+#define STDO_RXBRP_EVENT_MASK_MSK8_BIT (0x00000100)
+
+#define STDO_RXBRP_EVENT_MASK_MSK7_LSB (7)
+#define STDO_RXBRP_EVENT_MASK_MSK7_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK7_MASK (0x00000080)
+#define STDO_RXBRP_EVENT_MASK_MSK7_BIT (0x00000080)
+
+#define STDO_RXBRP_EVENT_MASK_MSK6_LSB (6)
+#define STDO_RXBRP_EVENT_MASK_MSK6_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK6_MASK (0x00000040)
+#define STDO_RXBRP_EVENT_MASK_MSK6_BIT (0x00000040)
+
+#define STDO_RXBRP_EVENT_MASK_MSK5_LSB (5)
+#define STDO_RXBRP_EVENT_MASK_MSK5_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK5_MASK (0x00000020)
+#define STDO_RXBRP_EVENT_MASK_MSK5_BIT (0x00000020)
+
+#define STDO_RXBRP_EVENT_MASK_MSK4_LSB (4)
+#define STDO_RXBRP_EVENT_MASK_MSK4_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK4_MASK (0x00000010)
+#define STDO_RXBRP_EVENT_MASK_MSK4_BIT (0x00000010)
+
+#define STDO_RXBRP_EVENT_MASK_MSK3_LSB (3)
+#define STDO_RXBRP_EVENT_MASK_MSK3_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK3_MASK (0x00000008)
+#define STDO_RXBRP_EVENT_MASK_MSK3_BIT (0x00000008)
+
+#define STDO_RXBRP_EVENT_MASK_MSK2_LSB (2)
+#define STDO_RXBRP_EVENT_MASK_MSK2_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK2_MASK (0x00000004)
+#define STDO_RXBRP_EVENT_MASK_MSK2_BIT (0x00000004)
+
+#define STDO_RXBRP_EVENT_MASK_MSK1_LSB (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK1_MASK (0x00000002)
+#define STDO_RXBRP_EVENT_MASK_MSK1_BIT (0x00000002)
+
+#define STDO_RXBRP_EVENT_MASK_MSK0_LSB (0)
+#define STDO_RXBRP_EVENT_MASK_MSK0_WIDTH (1)
+#define STDO_RXBRP_EVENT_MASK_MSK0_MASK (0x00000001)
+#define STDO_RXBRP_EVENT_MASK_MSK0_BIT (0x00000001)
+
+#define STDO_RXDFE_ON_EVENT_EN_LSB (31)
+#define STDO_RXDFE_ON_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_ON_EVENT_RXDFE_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_RXDFE_OFF_EVENT_EN_LSB (31)
+#define STDO_RXDFE_OFF_EVENT_EN_WIDTH (1)
+#define STDO_RXDFE_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_RXDFE_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_LSB (2)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_RXDFE_OFF_EVENT_RXDFE_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DBG_ON_EVENT_EN_LSB (31)
+#define STDO_DBG_ON_EVENT_EN_WIDTH (1)
+#define STDO_DBG_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_LSB (0)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_ON_EVENT_DBG_ON_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_DBG_OFF_EVENT_EN_LSB (31)
+#define STDO_DBG_OFF_EVENT_EN_WIDTH (1)
+#define STDO_DBG_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_DBG_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_LSB (0)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_WIDTH (20)
+#define STDO_DBG_OFF_EVENT_DBG_OFF_EVENT_TIME_MASK (0x000FFFFF)
+
+#define STDO_TTR_ON_EVENT_EN_LSB (31)
+#define STDO_TTR_ON_EVENT_EN_WIDTH (1)
+#define STDO_TTR_ON_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_ON_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_LSB (2)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_ON_EVENT_TTR_ON_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_TTR_OFF_EVENT_EN_LSB (31)
+#define STDO_TTR_OFF_EVENT_EN_WIDTH (1)
+#define STDO_TTR_OFF_EVENT_EN_MASK (0x80000000)
+#define STDO_TTR_OFF_EVENT_EN_BIT (0x80000000)
+
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_LSB (2)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_WIDTH (18)
+#define STDO_TTR_OFF_EVENT_TTR_OFF_EVENT_TIME_MASK (0x000FFFFC)
+
+#define STDO_DVFS_EVENT_EN_LSB (31)
+#define STDO_DVFS_EVENT_EN_WIDTH (1)
+#define STDO_DVFS_EVENT_EN_MASK (0x80000000)
+#define STDO_DVFS_EVENT_EN_BIT (0x80000000)
+
+#define STDO_DVFS_EVENT_MODE_LSB (30)
+#define STDO_DVFS_EVENT_MODE_WIDTH (1)
+#define STDO_DVFS_EVENT_MODE_MASK (0x40000000)
+#define STDO_DVFS_EVENT_MODE_BIT (0x40000000)
+
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_LSB (2)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_WIDTH (18)
+#define STDO_DVFS_EVENT_DVFS_EVNT_TIME_MASK (0x000FFFFC)
+
+#define STDO_WDG_EN_WDG_EN_LSB (0)
+#define STDO_WDG_EN_WDG_EN_WIDTH (1)
+#define STDO_WDG_EN_WDG_EN_MASK (0x00000001)
+#define STDO_WDG_EN_WDG_EN_BIT (0x00000001)
+
+#define STDO_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_LSB (3)
+#define STDO_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_WIDTH (11)
+#define STDO_WDG_BOUND_OFFSET_WDG_BOUND_OFFSET_0_MASK (0x00003FF8)
+
+#define STDO_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_LSB (0)
+#define STDO_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_WIDTH (1)
+#define STDO_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_MASK (0x00000001)
+#define STDO_WDG_CHKPT_UNCHK_WDG_CHKPT_0_UNCHK_BIT (0x00000001)
+
+#define STDO_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_LSB (3)
+#define STDO_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_WIDTH (17)
+#define STDO_WDG_CHKPT_TIME_0_WDG_CHKPT_TIME_0_MASK (0x000FFFF8)
+
+#define STDO_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_LSB (3)
+#define STDO_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_WIDTH (10)
+#define STDO_uSIP_IRQ_OFFSET_0_CHIP_OFFSET_MASK (0x00001FF8)
+
+#define STDO_uSIP_IRQ_MASK_0_MSK_LSB (0)
+#define STDO_uSIP_IRQ_MASK_0_MSK_WIDTH (32)
+#define STDO_uSIP_IRQ_MASK_0_MSK_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_CLR_0_CLR_LSB (0)
+#define STDO_uSIP_IRQ_CLR_0_CLR_WIDTH (32)
+#define STDO_uSIP_IRQ_CLR_0_CLR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_SRC_0_SRC_LSB (0)
+#define STDO_uSIP_IRQ_SRC_0_SRC_WIDTH (32)
+#define STDO_uSIP_IRQ_SRC_0_SRC_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_ISR_0_ISR_LSB (0)
+#define STDO_uSIP_IRQ_ISR_0_ISR_WIDTH (32)
+#define STDO_uSIP_IRQ_ISR_0_ISR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_LSB (3)
+#define STDO_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_WIDTH (10)
+#define STDO_uSIP_IRQ_OFFSET_1_CHIP_OFFSET_MASK (0x00001FF8)
+
+#define STDO_uSIP_IRQ_MASK_1_MSK_LSB (0)
+#define STDO_uSIP_IRQ_MASK_1_MSK_WIDTH (32)
+#define STDO_uSIP_IRQ_MASK_1_MSK_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_CLR_1_CLR_LSB (0)
+#define STDO_uSIP_IRQ_CLR_1_CLR_WIDTH (32)
+#define STDO_uSIP_IRQ_CLR_1_CLR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_SRC_1_SRC_LSB (0)
+#define STDO_uSIP_IRQ_SRC_1_SRC_WIDTH (32)
+#define STDO_uSIP_IRQ_SRC_1_SRC_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_ISR_1_ISR_LSB (0)
+#define STDO_uSIP_IRQ_ISR_1_ISR_WIDTH (32)
+#define STDO_uSIP_IRQ_ISR_1_ISR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_LSB (3)
+#define STDO_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_WIDTH (10)
+#define STDO_uSIP_IRQ_OFFSET_2_CHIP_OFFSET_MASK (0x00001FF8)
+
+#define STDO_uSIP_IRQ_MASK_2_MSK_LSB (0)
+#define STDO_uSIP_IRQ_MASK_2_MSK_WIDTH (32)
+#define STDO_uSIP_IRQ_MASK_2_MSK_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_CLR_2_CLR_LSB (0)
+#define STDO_uSIP_IRQ_CLR_2_CLR_WIDTH (32)
+#define STDO_uSIP_IRQ_CLR_2_CLR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_SRC_2_SRC_LSB (0)
+#define STDO_uSIP_IRQ_SRC_2_SRC_WIDTH (32)
+#define STDO_uSIP_IRQ_SRC_2_SRC_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_ISR_2_ISR_LSB (0)
+#define STDO_uSIP_IRQ_ISR_2_ISR_WIDTH (32)
+#define STDO_uSIP_IRQ_ISR_2_ISR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_LSB (3)
+#define STDO_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_WIDTH (10)
+#define STDO_uSIP_IRQ_OFFSET_3_CHIP_OFFSET_MASK (0x00001FF8)
+
+#define STDO_uSIP_IRQ_MASK_3_MSK_LSB (0)
+#define STDO_uSIP_IRQ_MASK_3_MSK_WIDTH (32)
+#define STDO_uSIP_IRQ_MASK_3_MSK_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_CLR_3_CLR_LSB (0)
+#define STDO_uSIP_IRQ_CLR_3_CLR_WIDTH (32)
+#define STDO_uSIP_IRQ_CLR_3_CLR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_SRC_3_SRC_LSB (0)
+#define STDO_uSIP_IRQ_SRC_3_SRC_WIDTH (32)
+#define STDO_uSIP_IRQ_SRC_3_SRC_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_ISR_3_ISR_LSB (0)
+#define STDO_uSIP_IRQ_ISR_3_ISR_WIDTH (32)
+#define STDO_uSIP_IRQ_ISR_3_ISR_MASK (0xFFFFFFFF)
+
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_3_LSB (3)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_3_WIDTH (1)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_3_MASK (0x00000008)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_3_BIT (0x00000008)
+
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_2_LSB (2)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_2_WIDTH (1)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_2_MASK (0x00000004)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_2_BIT (0x00000004)
+
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_1_LSB (1)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_1_WIDTH (1)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_1_MASK (0x00000002)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_1_BIT (0x00000002)
+
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_0_LSB (0)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_0_WIDTH (1)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_0_MASK (0x00000001)
+#define STDO_uSIP_IRQ_STATUS_STATUS_IRQ_0_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_EVDO_RX_EVENTGEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdorxslp.h b/mcu/interface/l1/cl1/common/HW/cphevdorxslp.h
new file mode 100644
index 0000000..3dcbd76
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdorxslp.h
@@ -0,0 +1,212 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_RX_SLP_H_
+#define _CPH_EVDO_RX_SLP_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define STDO_RX_SLP_REG_BASE (0x00000000)
+
+#define STDO_RX_SLP_end (STDO_RX_SLP_REG_BASE + 0xA60F0060 + 1*4)
+
+
+
+#define STDO_SM_CON ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0000))
+#define STDO_SM_PAUSE_TIME ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0004))
+#define STDO_SM_STA ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0008))
+#define STDO_SM_CFG ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F000C))
+#define STDO_SM_START_TIME ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0010))
+#define STDO_SM_SW_WAKE_CON ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0014))
+#define STDO_SM_STEP_FRAC ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0018))
+#define STDO_SM_SYSCNT_F32K_INT ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F001C))
+#define STDO_SM_SYSCNT_F32K_FRAC ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0020))
+#define STDO_SM_SUPFRM_F32K_L ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0024))
+#define STDO_SM_SUPFRM_F32K_H ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0028))
+#define STDO_SM_SLEEP_OFFSET ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F002C))
+#define STDO_SM_TIME_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0030))
+#define STDO_SM_SUPFRM_TIME_L_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0034))
+#define STDO_SM_SUPFRM_TIME_H_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0038))
+#define STDO_SM_TIME_SLTBD ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F003C))
+#define STDO_SM_SUPFRM_TIME_L_SLTBD ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0040))
+#define STDO_SM_SUPFRM_TIME_H_SLTBD ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0044))
+#define STDO_SM_TIME_WAKEUP_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0048))
+#define STDO_SM_SUPFRM_TIME_L_WAKEUP_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F004C))
+#define STDO_SM_SUPFRM_TIME_H_WAKEUP_START ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0050))
+#define STDO_SM_FINAL_PAUSE_DURATION ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0054))
+#define STDO_SM_PRESLP_CNT ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0058))
+#define STDO_SM_SLT_START_F32K ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F005C))
+#define STDO_SM_WAKEUP_START_F32K ((APBADDR32)(STDO_RX_SLP_REG_BASE + 0xA60F0060))
+
+
+#define STDO_SM_CON_CLR_CNT_LSB (15)
+#define STDO_SM_CON_CLR_CNT_WIDTH (1)
+#define STDO_SM_CON_CLR_CNT_MASK (0x00008000)
+#define STDO_SM_CON_CLR_CNT_BIT (0x00008000)
+
+#define STDO_SM_CON_PAUSE_START_LSB (1)
+#define STDO_SM_CON_PAUSE_START_WIDTH (1)
+#define STDO_SM_CON_PAUSE_START_MASK (0x00000002)
+#define STDO_SM_CON_PAUSE_START_BIT (0x00000002)
+
+#define STDO_SM_CON_PAUSE_MODE_LSB (0)
+#define STDO_SM_CON_PAUSE_MODE_WIDTH (1)
+#define STDO_SM_CON_PAUSE_MODE_MASK (0x00000001)
+#define STDO_SM_CON_PAUSE_MODE_BIT (0x00000001)
+
+#define STDO_SM_PAUSE_TIME_PAUSE_TIME_LSB (0)
+#define STDO_SM_PAUSE_TIME_PAUSE_TIME_WIDTH (32)
+#define STDO_SM_PAUSE_TIME_PAUSE_TIME_MASK (0xFFFFFFFF)
+
+#define STDO_SM_STA_SLP_EXIT_CPL_LSB (7)
+#define STDO_SM_STA_SLP_EXIT_CPL_WIDTH (1)
+#define STDO_SM_STA_SLP_EXIT_CPL_MASK (0x00000080)
+#define STDO_SM_STA_SLP_EXIT_CPL_BIT (0x00000080)
+
+#define STDO_SM_STA_PAUSE_CPL_LSB (6)
+#define STDO_SM_STA_PAUSE_CPL_WIDTH (1)
+#define STDO_SM_STA_PAUSE_CPL_MASK (0x00000040)
+#define STDO_SM_STA_PAUSE_CPL_BIT (0x00000040)
+
+#define STDO_SM_CFG_SW_WAKE_EN_LSB (8)
+#define STDO_SM_CFG_SW_WAKE_EN_WIDTH (1)
+#define STDO_SM_CFG_SW_WAKE_EN_MASK (0x00000100)
+#define STDO_SM_CFG_SW_WAKE_EN_BIT (0x00000100)
+
+#define STDO_SM_CFG_IRQ_EN_LSB (1)
+#define STDO_SM_CFG_IRQ_EN_WIDTH (1)
+#define STDO_SM_CFG_IRQ_EN_MASK (0x00000002)
+#define STDO_SM_CFG_IRQ_EN_BIT (0x00000002)
+
+#define STDO_SM_START_TIME_SYSTEM_TIME_CNT_LSB (2)
+#define STDO_SM_START_TIME_SYSTEM_TIME_CNT_WIDTH (18)
+#define STDO_SM_START_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define STDO_SM_SW_WAKE_CON_SW_EVENT_LSB (0)
+#define STDO_SM_SW_WAKE_CON_SW_EVENT_WIDTH (1)
+#define STDO_SM_SW_WAKE_CON_SW_EVENT_MASK (0x00000001)
+#define STDO_SM_SW_WAKE_CON_SW_EVENT_BIT (0x00000001)
+
+#define STDO_SM_STEP_FRAC_STEP_INT_LSB (18)
+#define STDO_SM_STEP_FRAC_STEP_INT_WIDTH (9)
+#define STDO_SM_STEP_FRAC_STEP_INT_MASK (0x07FC0000)
+
+#define STDO_SM_STEP_FRAC_STEP_FRAC_LSB (0)
+#define STDO_SM_STEP_FRAC_STEP_FRAC_WIDTH (18)
+#define STDO_SM_STEP_FRAC_STEP_FRAC_MASK (0x0003FFFF)
+
+#define STDO_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_LSB (0)
+#define STDO_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_WIDTH (20)
+#define STDO_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_MASK (0x000FFFFF)
+
+#define STDO_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_LSB (0)
+#define STDO_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_WIDTH (18)
+#define STDO_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_MASK (0x0003FFFF)
+
+#define STDO_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_LSB (0)
+#define STDO_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_WIDTH (32)
+#define STDO_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_MASK (0xFFFFFFFF)
+
+#define STDO_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_LSB (0)
+#define STDO_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_WIDTH (4)
+#define STDO_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_MASK (0x0000000F)
+
+#define STDO_SM_SLEEP_OFFSET_CHIP_OFFSET_LSB (2)
+#define STDO_SM_SLEEP_OFFSET_CHIP_OFFSET_WIDTH (14)
+#define STDO_SM_SLEEP_OFFSET_CHIP_OFFSET_MASK (0x0000FFFC)
+
+#define STDO_SM_TIME_START_SM_TIME_START_LSB (0)
+#define STDO_SM_TIME_START_SM_TIME_START_WIDTH (20)
+#define STDO_SM_TIME_START_SM_TIME_START_MASK (0x000FFFFF)
+
+#define STDO_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_LSB (0)
+#define STDO_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_WIDTH (32)
+#define STDO_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_MASK (0xFFFFFFFF)
+
+#define STDO_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_LSB (0)
+#define STDO_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_WIDTH (4)
+#define STDO_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_MASK (0x0000000F)
+
+#define STDO_SM_TIME_SLTBD_SM_TIME_SLTBD_LSB (0)
+#define STDO_SM_TIME_SLTBD_SM_TIME_SLTBD_WIDTH (20)
+#define STDO_SM_TIME_SLTBD_SM_TIME_SLTBD_MASK (0x000FFFFF)
+
+#define STDO_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define STDO_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (32)
+#define STDO_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0xFFFFFFFF)
+
+#define STDO_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define STDO_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (4)
+#define STDO_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0x0000000F)
+
+#define STDO_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_LSB (0)
+#define STDO_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_WIDTH (20)
+#define STDO_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_MASK (0x000FFFFF)
+
+#define STDO_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define STDO_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (32)
+#define STDO_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0xFFFFFFFF)
+
+#define STDO_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define STDO_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (4)
+#define STDO_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0x0000000F)
+
+#define STDO_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_LSB (0)
+#define STDO_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_WIDTH (32)
+#define STDO_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_MASK (0xFFFFFFFF)
+
+#define STDO_SM_PRESLP_CNT_SM_PRESLP_CNT_LSB (0)
+#define STDO_SM_PRESLP_CNT_SM_PRESLP_CNT_WIDTH (6)
+#define STDO_SM_PRESLP_CNT_SM_PRESLP_CNT_MASK (0x0000003F)
+
+#define STDO_SM_SLT_START_F32K_SM_SLT_START_F32K_LSB (0)
+#define STDO_SM_SLT_START_F32K_SM_SLT_START_F32K_WIDTH (6)
+#define STDO_SM_SLT_START_F32K_SM_SLT_START_F32K_MASK (0x0000003F)
+
+#define STDO_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_LSB (0)
+#define STDO_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_WIDTH (32)
+#define STDO_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _CPH_EVDO_RX_SLP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdoschreg.h b/mcu/interface/l1/cl1/common/HW/cphevdoschreg.h
new file mode 100644
index 0000000..736a8d5
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdoschreg.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphevdoschreg_93.h"
+#elif defined(__MD95__)
+#include "cphevdoschreg_95.h"
+#else
+#include "cphevdoschreg_97.h"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdoschreg_93.h b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_93.h
new file mode 100644
index 0000000..a40b930
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_93.h
@@ -0,0 +1,591 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_SCH_H_
+#define _CPH_EVDO_SCH_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_CDO_REG_BASE (0xA7850000)
+
+#define CS_CDO_end (CS_CDO_REG_BASE + 0x0800 + 1*4)
+
+
+
+#define SRDO_START ((APBADDR32)(CS_CDO_REG_BASE + 0x0000))
+#define SRDO_PAUSE ((APBADDR32)(CS_CDO_REG_BASE + 0x0004))
+#define SRDO_RST ((APBADDR32)(CS_CDO_REG_BASE + 0x0008))
+#define SRDO_INBUF_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x000C))
+#define SRDO_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0010))
+#define SRDO_MEM_SEL ((APBADDR32)(CS_CDO_REG_BASE + 0x0014))
+#define SRDO_GENSTAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0018))
+#define SRDO_GENSTAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x001C))
+#define SRDO_PATHMAINT ((APBADDR32)(CS_CDO_REG_BASE + 0x0020))
+#define SRDO_INBUF_ADR ((APBADDR32)(CS_CDO_REG_BASE + 0x0024))
+#define SRDO_INBUF_DAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0028))
+#define SRDO_STATUS0 ((APBADDR32)(CS_CDO_REG_BASE + 0x002C))
+#define SRDO_PLTINFO_CLR0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0030))
+#define SRDO_PLTINFO_CLR1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0034))
+#define SRDO_PATHINFO_CLR ((APBADDR32)(CS_CDO_REG_BASE + 0x0038))
+#define SRDO_ACQ_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x003C))
+#define SRDO_TSTCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0040))
+#define SRDO_CLKCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0048))
+#define SRDO_STATUS1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0050))
+#define SRDO_INBUF_DAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0054))
+#define SRDO_FNDO_MEMCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0058))
+#define SRDO_THRESH ((APBADDR32)(CS_CDO_REG_BASE + 0x005C))
+#define SRDO_TST_DBG ((APBADDR32)(CS_CDO_REG_BASE + 0x0060))
+#define SRDO_DONE ((APBADDR32)(CS_CDO_REG_BASE + 0x0064))
+#define SRDO_PATHINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0080))
+#define SRDO_PLTLIST ((APBADDR32)(CS_CDO_REG_BASE + 0x0100))
+#define SRDO_PLTINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0200))
+#define SRDO_PATHBUF ((APBADDR32)(CS_CDO_REG_BASE + 0x0800))
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*HWD_SRDO_START*/
+#define START_START_SHIFT 0 /* [0] */
+#define START_SRDO_START_DLY_EN_SHIFT 1 /* [1] */
+#define START_SRDO_START_DLY_CNT_SHIFT 2 /* [21:2] */
+
+#define START_START_MASK 0x00000001 << START_START_SHIFT
+#define START_SRDO_START_DLY_EN_MASK 0x00000001 << START_SRDO_START_DLY_EN_SHIFT
+#define START_SRDO_START_DLY_CNT_MASK 0x000FFFFF << START_SRDO_START_DLY_CNT_SHIFT
+
+
+/*HWD_SRDO_PAUSE*/
+#define PAUSE_PAUSE_SHIFT 0 /* [0] */
+#define PAUSE_PAUSE_MASK 0x00000001 << PAUSE_PAUSE_SHIFT
+
+/*HWD_SRDO_RST*/
+#define RST_RST_SHIFT 0 /* [0] */
+#define RST_RST_MASK 0x00000001 << RST_RST_SHIFT
+
+/*HWD_SRDO_INBUF_CTL*/
+#define INBUF_CTL_ANTENNA_INIT_EN_SHIFT 19 /* [19] */
+#define INBUF_CTL_ANTENNA_INIT_SHIFT 18 /* [18] */
+#define INBUF_CTL_IIR_A_IB_SHIFT 16 /* [17:16] */
+#define INBUF_CTL_DUAL_SHIFT 15 /* [15] */
+#define INBUF_CTL_BURST_SHIFT 14 /* [14] */
+#define INBUF_CTL_ANT_MODE_SHIFT 12 /* [13:12] */
+#define INBUF_CTL_CAPTURE_SHIFT 11 /* [11] */
+#define INBUF_CTL_CAPLEN_SHIFT 8 /* [10:8] */
+#define INBUF_CTL_BUFFCAPT_SHIFT 4 /* [7:4] */
+#define INBUF_CTL_BUFFCAPINT_SHIFT 0 /* [3:0] */
+
+#define INBUF_ANTENNA_INIT_EN_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_EN_SHIFT
+#define INBUF_ANTENNA_INIT_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_SHIFT
+#define INBUF_CTL_IIR_A_IB_MASK 0x00000003 << INBUF_CTL_IIR_A_IB_SHIFT
+#define INBUF_CTL_DUAL_MASK 0x00000001 << INBUF_CTL_DUAL_SHIFT
+#define INBUF_CTL_BURST_MASK 0x00000001 << INBUF_CTL_BURST_SHIFT
+#define INBUF_CTL_ANT_MODE_MASK 0x00000003 << INBUF_CTL_ANT_MODE_SHIFT
+#define INBUF_CTL_CAPTURE_MASK 0x00000001 << INBUF_CTL_CAPTURE_SHIFT
+#define INBUF_CTL_CAPLEN_MASK 0x00000007 << INBUF_CTL_CAPLEN_SHIFT
+#define INBUF_CTL_BUFFCAPT_MASK 0x0000000f << INBUF_CTL_BUFFCAPT_SHIFT
+#define INBUF_CTL_BUFFCAPINT_MASK 0x0000000f << INBUF_CTL_BUFFCAPINT_SHIFT
+
+
+/*HWD_SRDO_CTL*/
+#define CTL_CLEAR_SHIFT 9 /* [9] */
+#define CTL_ACQMODE_SHIFT 8 /* [8] */
+#define CTL_SEARCH_SET_SHIFT 6 /* [7:6] */
+#define CTL_SEARCH_N_SHIFT 0 /* [5:0] */
+
+#define CTL_CLEAR_MASK 0x00000001 << CTL_CLEAR_SHIFT
+#define CTL_ACQMODE_MASK 0x00000001 << CTL_ACQMODE_SHIFT
+#define CTL_SEARCH_SET_MASK 0x00000003 << CTL_SEARCH_SET_SHIFT
+#define CTL_SEARCH_N_MASK 0x0000003f << CTL_SEARCH_N_SHIFT
+
+/*HWD_SRDO_GENSTAT0*/
+#define GENSTAT0_COHLEN_SHIFT 17 /* [18:17] */
+#define GENSTAT0_PASSCNT1_SHIFT 12 /* [16:12] */
+#define GENSTAT0_PASSCNT2_SHIFT 6 /* [11:6] */
+#define GENSTAT0_SHIFT1_SHIFT 3 /* [5:3] */
+#define GENSTAT0_SHIFT2_SHIFT 0 /* [2:0] */
+
+#define GENSTAT0_COHLEN_MASK 0x00000003 << GENSTAT0_COHLEN_SHIFT
+#define GENSTAT0_PASSCNT1_MASK 0x0000001f << GENSTAT0_PASSCNT1_SHIFT
+#define GENSTAT0_PASSCNT2_MASK 0x0000003f << GENSTAT0_PASSCNT2_SHIFT
+#define GENSTAT0_SHIFT1_MASK 0x00000007 << GENSTAT0_SHIFT1_SHIFT
+#define GENSTAT0_SHIFT2_MASK 0x00000007 << GENSTAT0_SHIFT2_SHIFT
+
+/*HWD_SRDO_GENSTAT1*/
+#define GENSTAT1_THRESH1M_SHIFT 8 /* [15:8] */
+#define GENSTAT1_THRESH2M_SHIFT 0 /* [7:0] */
+#define GENSTAT1_THRESH1M_MASK 0x000000ff << GENSTAT1_THRESH1M_SHIFT
+#define GENSTAT1_THRESH2M_MASK 0x000000ff << GENSTAT1_THRESH2M_SHIFT
+
+/*HWD_SRDO_PATHMAINT*/
+#define PATHMAINT_PATHMAINT_MODE_SHIFT 3 /* [3] */
+#define PATHMAINT_CLR_NUMSEARCH_SHIFT 2 /* [2] */
+#define PATHMAINT_IIR_A_SHIFT 0 /* [1:0] */
+#define PATHMAINT_PATHMAINT_MODE_MASK 0x00000001 << PATHMAINT_PATHMAINT_MODE_SHIFT
+#define PATHMAINT_CLR_NUMSEARCH_MASK 0x00000001 << PATHMAINT_CLR_NUMSEARCH_SHIFT
+#define PATHMAINT_IIR_A_MASK 0x00000003 << PATHMAINT_IIR_A_SHIFT
+
+/*HWD_SRDO_INBUF0_ADR*/
+#define INBUF_ADR_INBUF_ADR_SHIFT 0 /* [13:0] */
+#define INBUF_ADR_INBUF_ADR_MASK 0x00003fff << INBUF_ADR_INBUF_ADR_SHIFT
+
+/*HWD_SRDO_INBUF_DAT*/
+#define INBUF_DAT_INBUF_DAT0_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT0_MASK 0x000fffff << INBUF_DAT_INBUF_DAT0_SHIFT
+
+/*HWD_SRDO_INBUF_DAT1*/
+#define INBUF_DAT_INBUF_DAT1_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT1_MASK 0x000fffff << INBUF_DAT_INBUF_DAT1_SHIFT
+
+
+/*HWD_SRDO_STATUS0*/
+#define STATUS0_ANTENNA_SHIFT 24 /* [24] */
+#define STATUS0_BUSY_SHIFT 23 /* [23] */
+#define STATUS0_INMAG_INST_SHIFT 15 /* [22:15] */
+#define STATUS0_INMAG_IIR_SHIFT 7 /* [14:7] */
+#define STATUS0_BUFCAPTMHS_SHIFT 0 /* [6:0] */
+
+#define STATUS0_ANTENNA_MASK 0x00000001 << STATUS0_ANTENNA_SHIFT
+#define STATUS0_BUSY_MASK 0x00000001 << STATUS0_BUSY_SHIFT
+#define STATUS0_INMAG_INST_MASK 0x000000ff << STATUS0_INMAG_INST_SHIFT
+#define STATUS0_INMAG_IIR_MASK 0x000000ff << STATUS0_INMAG_IIR_SHIFT
+#define STATUS0_BUFCAPTMHS_MASK 0x0000007f << STATUS0_BUFCAPTMHS_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR1*/
+#define PLTINFO_CLR1_CLR_SHIFT 0 /* [23:0] */
+#define PLTINFO_CLR1_CLR_MASK 0x00ffffff << PLTINFO_CLR1_CLR_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR0*/
+#define PLTINFO_CLR0_CLR_SHIFT 0 /* [31:0] */
+#define PLTINFO_CLR0_CLR_MASK 0xffffffff << PLTINFO_CLR0_CLR_SHIFT
+
+/*HWD_SRDO_PATHINFO_CLR*/
+#define PATHINFO_CLR_CLR_SHIFT 0 /* [19:0] */
+#define PATHINFO_CLR_CLR_MASK 0x000fffff << PATHINFO_CLR_CLR_SHIFT
+
+/*HWD_SRDO_ACQ_CTL*/
+#define ACQ_CTL_ACQ_WIN_SHIFT 11 /* [20:11] */
+#define ACQ_CTL_ACQ_OFFSET_SHIFT 0 /* [10:0] */
+#define ACQ_CTL_ACQ_WIN_MASK 0x000003ff << ACQ_CTL_ACQ_WIN_SHIFT
+#define ACQ_CTL_ACQ_OFFSET_MASK 0x000007ff << ACQ_CTL_ACQ_OFFSET_SHIFT
+
+/*HWD_SRDO_TSTCTL*/
+#define TSTCTL_INBUF_TST_MODE_SHIFT 0 /* [0] */
+#define TSTCTL_INBUF_TST_MODE_MASK 1 << TSTCTL_INBUF_TST_MODE_SHIFT
+
+/*HWD_SRDO_STATUS1, NOTE: start from bit 7*/
+#define STATUS1_INMAG_INST1_SHIFT 15 /* [22:15] */
+#define STATUS1_INMAG_IIR1_SHIFT 7 /* [14:7] */
+#define STATUS1_INMAG_INST1_MASK 0x000000ff << STATUS1_INMAG_INST1_SHIFT
+#define STATUS1_INMAG_IIR1_MASK 0x000000ff << STATUS1_INMAG_IIR1_SHIFT
+
+
+/*HWD_SRDO_TSTSEL*/
+#define TSTSEL_TST_SEL_SHIFT 0 /* [7:0] */
+#define TSTSEL_TST_SEL_MASK 0x000000ff << TSTSEL_TST_SEL_SHIFT
+
+/*HWD_SRDO_PATHINFO*/
+#define PATHINFO_MAX 20
+#define PATHINFO_LEN 4 /* byte */
+
+#define PATHINFO_ENABLE_SHIFT 22 /* [22] */
+#define PATHINFO_KEEP_SHIFT 21 /* [21] */
+#define PATHINFO_WIN_SHIFT 17 /* [20:17] */
+#define PATHINFO_PILOTPNNUM_SHIFT 8 /* [16:8] */
+#define PATHINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PATHINFO_ENABLE_MASK 0x00000001 << PATHINFO_ENABLE_SHIFT
+#define PATHINFO_KEEP_MASK 0x00000001 << PATHINFO_KEEP_SHIFT
+#define PATHINFO_WIN_MASK 0x0000000f << PATHINFO_WIN_SHIFT
+#define PATHINFO_PILOTPNNUM_MASK 0x000001ff << PATHINFO_PILOTPNNUM_SHIFT
+#define PATHINFO_SUMMAG_MASK 0x00000ff << PATHINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PLTLIST*/
+#define PLTLIST_MAX 56
+#define PLTLIST_LEN 4 /* byte */
+#define PLTLIST_ENABLE_SHIFT 26 /* [26] */
+#define PLTLIST_KEEP_SHIFT 25 /* [25] */
+#define PLTLIST_WIN_SHIFT 21 /* [24:21] */
+#define PLTLIST_ALWAYS_SEARCH_SHIFT 20 /* [20] */
+#define PLTLIST_PILOT_PN_SHIFT 11 /* [19:11] */
+#define PLTLIST_OFFSET_SHIFT 0 /* [10:0] */
+#define PLTLIST_WIN_MASK 0x0000000f << PLTLIST_WIN_SHIFT
+#define PLTLIST_ALWAYS_SEARCH_MASK 0x00000001 << PLTLIST_ALWAYS_SEARCH_SHIFT
+#define PLTLIST_PILOT_PN_MASK 0x000001ff << PLTLIST_PILOT_PN_SHIFT
+#define PLTLIST_OFFSET_MASK 0x000007ff << PLTLIST_OFFSET_SHIFT
+
+/*HWD_SRDO_PLTINFO*/
+#define PLTINFO_MAX 56
+#define PLTINFO_LEN 4 /* byte */
+#define PLTINFO_NUMSEARCH_SHIFT 8 /* [11:8] */
+#define PLTINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PLTINFO_NUMSEARCH_MASK 0x0000000f << PLTINFO_NUMSEARCH_SHIFT
+#define PLTINFO_SUMMAG_MASK 0x000000ff << PLTINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PATHBUF*/
+#define PATHBUF_MAX 16 /* total 16 path for each path ( 20 ) */
+#define PATHBUF_LEN 4 /* byte */
+#define PATHBUF_PATH_VALID_SHIFT 24 /* [24] */
+#define PATHBUF_NUMAVG_SHIFT 21 /* [23:21] */
+#define PATHBUF_ANTENNA_SHIFT 20 /* [20] */
+#define PATHBUF_OFFSET_SHIFT 8 /* [19:8] */
+#define PATHBUF_STAT_SHIFT 0 /* [7:0] */
+#define PATHBUF_PATH_VALID_MASK 0x00000001 << PATHBUF_PATH_VALID_SHIFT
+#define PATHBUF_NUMAVG_MASK 0x00000007 << PATHBUF_NUMAVG_SHIFT
+#define PATHBUF_ANTENNA_MASK 0x00000001 << PATHBUF_ANTENNA_SHIFT
+#define PATHBUF_OFFSET_MASK 0x00000fff << PATHBUF_OFFSET_SHIFT
+#define PATHBUF_STAT_MASK 0x000000ff << PATHBUF_STAT_SHIFT
+
+/*HWD_SRDO_CLKCTL*/
+#define CLKCTL_CLK_MODE_SHIFT 1 /* [1] */
+#define CLKCTL_CLKENB_SHIFT 0 /* [0] */
+#define CLKCTL_CLK_MODE_MASK (0x1 << CLKCTL_CLK_MODE_SHIFT)
+#define CLKCTL_CLKENB_MASK (0x1 << CLKCTL_CLKENB_SHIFT)
+
+/*SRDO_DONE*/
+#define SRDO_DONE_DONE_SHIFT 0
+#define SRDO_DONE_DONE_MASK 0x00000001 << SRDO_DONE_DONE_SHIFT
+
+#endif //#ifndef _CPH_EVDO_SCH_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdoschreg_95.h b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_95.h
new file mode 100644
index 0000000..b84391a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_95.h
@@ -0,0 +1,599 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_SCH_H_
+#define _CPH_EVDO_SCH_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_CDO_REG_BASE (0xA7880000)
+
+#define CS_CDO_end (CS_CDO_REG_BASE + 0x0800 + 1*4)
+
+
+
+#define SRDO_START ((APBADDR32)(CS_CDO_REG_BASE + 0x0000))
+#define SRDO_PAUSE ((APBADDR32)(CS_CDO_REG_BASE + 0x0004))
+#define SRDO_RST ((APBADDR32)(CS_CDO_REG_BASE + 0x0008))
+#define SRDO_INBUF_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x000C))
+#define SRDO_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0010))
+#define SRDO_MEM_SEL ((APBADDR32)(CS_CDO_REG_BASE + 0x0014))
+#define SRDO_GENSTAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0018))
+#define SRDO_GENSTAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x001C))
+#define SRDO_PATHMAINT ((APBADDR32)(CS_CDO_REG_BASE + 0x0020))
+#define SRDO_INBUF_ADR ((APBADDR32)(CS_CDO_REG_BASE + 0x0024))
+#define SRDO_INBUF_DAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0028))
+#define SRDO_STATUS0 ((APBADDR32)(CS_CDO_REG_BASE + 0x002C))
+#define SRDO_PLTINFO_CLR0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0030))
+#define SRDO_PLTINFO_CLR1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0034))
+#define SRDO_PATHINFO_CLR ((APBADDR32)(CS_CDO_REG_BASE + 0x0038))
+#define SRDO_ACQ_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x003C))
+#define SRDO_TSTCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0040))
+#define SRDO_CLKCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0048))
+#define SRDO_STATUS1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0050))
+#define SRDO_INBUF_DAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0054))
+#define SRDO_FNDO_MEMCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0058))
+#define SRDO_THRESH ((APBADDR32)(CS_CDO_REG_BASE + 0x005C))
+#define SRDO_TST_DBG ((APBADDR32)(CS_CDO_REG_BASE + 0x0060))
+#define SRDO_DONE ((APBADDR32)(CS_CDO_REG_BASE + 0x0064))
+#define SRDO_PATHINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0080))
+#define SRDO_PLTLIST ((APBADDR32)(CS_CDO_REG_BASE + 0x0100))
+#define SRDO_PLTINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0200))
+#define SRDO_PATHBUF ((APBADDR32)(CS_CDO_REG_BASE + 0x0800))
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*HWD_SRDO_START*/
+#define START_START_SHIFT 0 /* [0] */
+#define START_SRDO_START_DLY_EN_SHIFT 1 /* [1] */
+#define START_SRDO_START_DLY_CNT_SHIFT 2 /* [21:2] */
+
+#define START_START_MASK 0x00000001 << START_START_SHIFT
+#define START_SRDO_START_DLY_EN_MASK 0x00000001 << START_SRDO_START_DLY_EN_SHIFT
+#define START_SRDO_START_DLY_CNT_MASK 0x000FFFFF << START_SRDO_START_DLY_CNT_SHIFT
+
+
+/*HWD_SRDO_PAUSE*/
+#define PAUSE_PAUSE_SHIFT 0 /* [0] */
+#define PAUSE_PAUSE_MASK 0x00000001 << PAUSE_PAUSE_SHIFT
+
+/*HWD_SRDO_RST*/
+#define RST_RST_SHIFT 0 /* [0] */
+#define RST_RST_MASK 0x00000001 << RST_RST_SHIFT
+
+/*HWD_SRDO_INBUF_CTL*/
+#define INBUF_CTL_ANTENNA_INIT_EN_SHIFT 19 /* [19] */
+#define INBUF_CTL_ANTENNA_INIT_SHIFT 18 /* [18] */
+#define INBUF_CTL_IIR_A_IB_SHIFT 16 /* [17:16] */
+#define INBUF_CTL_DUAL_SHIFT 15 /* [15] */
+#define INBUF_CTL_BURST_SHIFT 14 /* [14] */
+#define INBUF_CTL_ANT_MODE_SHIFT 12 /* [13:12] */
+#define INBUF_CTL_CAPTURE_SHIFT 11 /* [11] */
+#define INBUF_CTL_CAPLEN_SHIFT 8 /* [10:8] */
+#define INBUF_CTL_BUFFCAPT_SHIFT 4 /* [7:4] */
+#define INBUF_CTL_BUFFCAPINT_SHIFT 0 /* [3:0] */
+
+#define INBUF_ANTENNA_INIT_EN_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_EN_SHIFT
+#define INBUF_ANTENNA_INIT_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_SHIFT
+#define INBUF_CTL_IIR_A_IB_MASK 0x00000003 << INBUF_CTL_IIR_A_IB_SHIFT
+#define INBUF_CTL_DUAL_MASK 0x00000001 << INBUF_CTL_DUAL_SHIFT
+#define INBUF_CTL_BURST_MASK 0x00000001 << INBUF_CTL_BURST_SHIFT
+#define INBUF_CTL_ANT_MODE_MASK 0x00000003 << INBUF_CTL_ANT_MODE_SHIFT
+#define INBUF_CTL_CAPTURE_MASK 0x00000001 << INBUF_CTL_CAPTURE_SHIFT
+#define INBUF_CTL_CAPLEN_MASK 0x00000007 << INBUF_CTL_CAPLEN_SHIFT
+#define INBUF_CTL_BUFFCAPT_MASK 0x0000000f << INBUF_CTL_BUFFCAPT_SHIFT
+#define INBUF_CTL_BUFFCAPINT_MASK 0x0000000f << INBUF_CTL_BUFFCAPINT_SHIFT
+
+
+/*HWD_SRDO_CTL*/
+#define CTL_CLEAR_SHIFT 9 /* [9] */
+#define CTL_ACQMODE_SHIFT 8 /* [8] */
+#define CTL_SEARCH_SET_SHIFT 6 /* [7:6] */
+#define CTL_SEARCH_N_SHIFT 0 /* [5:0] */
+
+#define CTL_CLEAR_MASK 0x00000001 << CTL_CLEAR_SHIFT
+#define CTL_ACQMODE_MASK 0x00000001 << CTL_ACQMODE_SHIFT
+#define CTL_SEARCH_SET_MASK 0x00000003 << CTL_SEARCH_SET_SHIFT
+#define CTL_SEARCH_N_MASK 0x0000003f << CTL_SEARCH_N_SHIFT
+
+/*HWD_SRDO_GENSTAT0*/
+#define GENSTAT0_COHLEN_SHIFT 17 /* [18:17] */
+#define GENSTAT0_PASSCNT1_SHIFT 12 /* [16:12] */
+#define GENSTAT0_PASSCNT2_SHIFT 6 /* [11:6] */
+#define GENSTAT0_SHIFT1_SHIFT 3 /* [5:3] */
+#define GENSTAT0_SHIFT2_SHIFT 0 /* [2:0] */
+
+#define GENSTAT0_COHLEN_MASK 0x00000003 << GENSTAT0_COHLEN_SHIFT
+#define GENSTAT0_PASSCNT1_MASK 0x0000001f << GENSTAT0_PASSCNT1_SHIFT
+#define GENSTAT0_PASSCNT2_MASK 0x0000003f << GENSTAT0_PASSCNT2_SHIFT
+#define GENSTAT0_SHIFT1_MASK 0x00000007 << GENSTAT0_SHIFT1_SHIFT
+#define GENSTAT0_SHIFT2_MASK 0x00000007 << GENSTAT0_SHIFT2_SHIFT
+
+/*HWD_SRDO_GENSTAT1*/
+#define GENSTAT1_THRESH1M_SHIFT 8 /* [15:8] */
+#define GENSTAT1_THRESH2M_SHIFT 0 /* [7:0] */
+#define GENSTAT1_THRESH1M_MASK 0x000000ff << GENSTAT1_THRESH1M_SHIFT
+#define GENSTAT1_THRESH2M_MASK 0x000000ff << GENSTAT1_THRESH2M_SHIFT
+
+/*HWD_SRDO_PATHMAINT*/
+#define PATHMAINT_PATHMAINT_MODE_SHIFT 3 /* [3] */
+#define PATHMAINT_CLR_NUMSEARCH_SHIFT 2 /* [2] */
+#define PATHMAINT_IIR_A_SHIFT 0 /* [1:0] */
+#define PATHMAINT_PATHMAINT_MODE_MASK 0x00000001 << PATHMAINT_PATHMAINT_MODE_SHIFT
+#define PATHMAINT_CLR_NUMSEARCH_MASK 0x00000001 << PATHMAINT_CLR_NUMSEARCH_SHIFT
+#define PATHMAINT_IIR_A_MASK 0x00000003 << PATHMAINT_IIR_A_SHIFT
+
+/*HWD_SRDO_INBUF0_ADR*/
+#define INBUF_ADR_INBUF_ADR_SHIFT 0 /* [13:0] */
+#define INBUF_ADR_INBUF_ADR_MASK 0x00003fff << INBUF_ADR_INBUF_ADR_SHIFT
+
+/*HWD_SRDO_INBUF_DAT*/
+#define INBUF_DAT_INBUF_DAT0_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT0_MASK 0x000fffff << INBUF_DAT_INBUF_DAT0_SHIFT
+
+/*HWD_SRDO_INBUF_DAT1*/
+#define INBUF_DAT_INBUF_DAT1_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT1_MASK 0x000fffff << INBUF_DAT_INBUF_DAT1_SHIFT
+
+
+/*HWD_SRDO_STATUS0*/
+#define STATUS0_ANTENNA_SHIFT 24 /* [24] */
+#define STATUS0_BUSY_SHIFT 23 /* [23] */
+#define STATUS0_INMAG_INST_SHIFT 15 /* [22:15] */
+#define STATUS0_INMAG_IIR_SHIFT 7 /* [14:7] */
+#define STATUS0_BUFCAPTMHS_SHIFT 0 /* [6:0] */
+
+#define STATUS0_ANTENNA_MASK 0x00000001 << STATUS0_ANTENNA_SHIFT
+#define STATUS0_BUSY_MASK 0x00000001 << STATUS0_BUSY_SHIFT
+#define STATUS0_INMAG_INST_MASK 0x000000ff << STATUS0_INMAG_INST_SHIFT
+#define STATUS0_INMAG_IIR_MASK 0x000000ff << STATUS0_INMAG_IIR_SHIFT
+#define STATUS0_BUFCAPTMHS_MASK 0x0000007f << STATUS0_BUFCAPTMHS_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR1*/
+#define PLTINFO_CLR1_CLR_SHIFT 0 /* [23:0] */
+#define PLTINFO_CLR1_CLR_MASK 0x00ffffff << PLTINFO_CLR1_CLR_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR0*/
+#define PLTINFO_CLR0_CLR_SHIFT 0 /* [31:0] */
+#define PLTINFO_CLR0_CLR_MASK 0xffffffff << PLTINFO_CLR0_CLR_SHIFT
+
+/*HWD_SRDO_PATHINFO_CLR*/
+#define PATHINFO_CLR_CLR_SHIFT 0 /* [19:0] */
+#define PATHINFO_CLR_CLR_MASK 0x000fffff << PATHINFO_CLR_CLR_SHIFT
+
+/*HWD_SRDO_ACQ_CTL*/
+#define ACQ_CTL_ACQ_WIN_SHIFT 11 /* [20:11] */
+#define ACQ_CTL_ACQ_OFFSET_SHIFT 0 /* [10:0] */
+#define ACQ_CTL_ACQ_WIN_MASK 0x000003ff << ACQ_CTL_ACQ_WIN_SHIFT
+#define ACQ_CTL_ACQ_OFFSET_MASK 0x000007ff << ACQ_CTL_ACQ_OFFSET_SHIFT
+
+/*HWD_SRDO_TSTCTL*/
+#define TSTCTL_INBUF_TST_MODE_SHIFT 0 /* [0] */
+#define TSTCTL_INBUF_TST_MODE_MASK 1 << TSTCTL_INBUF_TST_MODE_SHIFT
+
+/*HWD_SRDO_STATUS1, NOTE: start from bit 7*/
+#define STATUS1_INMAG_INST1_SHIFT 15 /* [22:15] */
+#define STATUS1_INMAG_IIR1_SHIFT 7 /* [14:7] */
+#define STATUS1_INMAG_INST1_MASK 0x000000ff << STATUS1_INMAG_INST1_SHIFT
+#define STATUS1_INMAG_IIR1_MASK 0x000000ff << STATUS1_INMAG_IIR1_SHIFT
+
+
+/*HWD_SRDO_TSTSEL*/
+#define TSTSEL_TST_SEL_SHIFT 0 /* [7:0] */
+#define TSTSEL_TST_SEL_MASK 0x000000ff << TSTSEL_TST_SEL_SHIFT
+
+/*HWD_SRDO_PATHINFO*/
+#define PATHINFO_MAX 20
+#define PATHINFO_LEN 4 /* byte */
+
+#define PATHINFO_ENABLE_SHIFT 22 /* [22] */
+#define PATHINFO_KEEP_SHIFT 21 /* [21] */
+#define PATHINFO_WIN_SHIFT 17 /* [20:17] */
+#define PATHINFO_PILOTPNNUM_SHIFT 8 /* [16:8] */
+#define PATHINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PATHINFO_ENABLE_MASK 0x00000001 << PATHINFO_ENABLE_SHIFT
+#define PATHINFO_KEEP_MASK 0x00000001 << PATHINFO_KEEP_SHIFT
+#define PATHINFO_WIN_MASK 0x0000000f << PATHINFO_WIN_SHIFT
+#define PATHINFO_PILOTPNNUM_MASK 0x000001ff << PATHINFO_PILOTPNNUM_SHIFT
+#define PATHINFO_SUMMAG_MASK 0x00000ff << PATHINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PLTLIST*/
+#define PLTLIST_MAX 56
+#define PLTLIST_LEN 4 /* byte */
+#define PLTLIST_ENABLE_SHIFT 26 /* [26] */
+#define PLTLIST_KEEP_SHIFT 25 /* [25] */
+#define PLTLIST_WIN_SHIFT 21 /* [24:21] */
+#define PLTLIST_ALWAYS_SEARCH_SHIFT 20 /* [20] */
+#define PLTLIST_PILOT_PN_SHIFT 11 /* [19:11] */
+#define PLTLIST_OFFSET_SHIFT 0 /* [10:0] */
+#define PLTLIST_WIN_MASK 0x0000000f << PLTLIST_WIN_SHIFT
+#define PLTLIST_ALWAYS_SEARCH_MASK 0x00000001 << PLTLIST_ALWAYS_SEARCH_SHIFT
+#define PLTLIST_PILOT_PN_MASK 0x000001ff << PLTLIST_PILOT_PN_SHIFT
+#define PLTLIST_OFFSET_MASK 0x000007ff << PLTLIST_OFFSET_SHIFT
+
+/*HWD_SRDO_PLTINFO*/
+#define PLTINFO_MAX 56
+#define PLTINFO_LEN 4 /* byte */
+#define PLTINFO_NUMSEARCH_SHIFT 8 /* [11:8] */
+#define PLTINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PLTINFO_NUMSEARCH_MASK 0x0000000f << PLTINFO_NUMSEARCH_SHIFT
+#define PLTINFO_SUMMAG_MASK 0x000000ff << PLTINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PATHBUF*/
+#define PATHBUF_MAX 16 /* total 16 path for each path ( 20 ) */
+#define PATHBUF_LEN 4 /* byte */
+#define PATHBUF_PATH_VALID_SHIFT 24 /* [24] */
+#define PATHBUF_NUMAVG_SHIFT 21 /* [23:21] */
+#define PATHBUF_ANTENNA_SHIFT 20 /* [20] */
+#define PATHBUF_OFFSET_SHIFT 8 /* [19:8] */
+#define PATHBUF_STAT_SHIFT 0 /* [7:0] */
+#define PATHBUF_PATH_VALID_MASK 0x00000001 << PATHBUF_PATH_VALID_SHIFT
+#define PATHBUF_NUMAVG_MASK 0x00000007 << PATHBUF_NUMAVG_SHIFT
+#define PATHBUF_ANTENNA_MASK 0x00000001 << PATHBUF_ANTENNA_SHIFT
+#define PATHBUF_OFFSET_MASK 0x00000fff << PATHBUF_OFFSET_SHIFT
+#define PATHBUF_STAT_MASK 0x000000ff << PATHBUF_STAT_SHIFT
+
+/*HWD_SRDO_CLKCTL*/
+#define CLKCTL_CLK_MODE_SHIFT 1 /* [1] */
+#define CLKCTL_CLKENB_SHIFT 0 /* [0] */
+#define CLKCTL_CLK_MODE_MASK (0x1 << CLKCTL_CLK_MODE_SHIFT)
+#define CLKCTL_CLKENB_MASK (0x1 << CLKCTL_CLKENB_SHIFT)
+
+/*SRDO_DONE*/
+#define SRDO_DONE_DONE_SHIFT 0
+#define SRDO_DONE_DONE_MASK 0x00000001 << SRDO_DONE_DONE_SHIFT
+
+#endif //#ifndef _CPH_EVDO_SCH_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdoschreg_97.h b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_97.h
new file mode 100644
index 0000000..e30df2b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdoschreg_97.h
@@ -0,0 +1,600 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_SCH_97_H_
+#define _CPH_EVDO_SCH_97_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define CS_CDO_REG_BASE (0xA9880000)
+
+#define CS_CDO_end (CS_CDO_REG_BASE + 0x0800 + 1*4)
+
+
+
+#define SRDO_START ((APBADDR32)(CS_CDO_REG_BASE + 0x0000))
+#define SRDO_PAUSE ((APBADDR32)(CS_CDO_REG_BASE + 0x0004))
+#define SRDO_RST ((APBADDR32)(CS_CDO_REG_BASE + 0x0008))
+#define SRDO_INBUF_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x000C))
+#define SRDO_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0010))
+#define SRDO_MEM_SEL ((APBADDR32)(CS_CDO_REG_BASE + 0x0014))
+#define SRDO_GENSTAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0018))
+#define SRDO_GENSTAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x001C))
+#define SRDO_PATHMAINT ((APBADDR32)(CS_CDO_REG_BASE + 0x0020))
+#define SRDO_INBUF_ADR ((APBADDR32)(CS_CDO_REG_BASE + 0x0024))
+#define SRDO_INBUF_DAT0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0028))
+#define SRDO_STATUS0 ((APBADDR32)(CS_CDO_REG_BASE + 0x002C))
+#define SRDO_PLTINFO_CLR0 ((APBADDR32)(CS_CDO_REG_BASE + 0x0030))
+#define SRDO_PLTINFO_CLR1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0034))
+#define SRDO_PATHINFO_CLR ((APBADDR32)(CS_CDO_REG_BASE + 0x0038))
+#define SRDO_ACQ_CTL ((APBADDR32)(CS_CDO_REG_BASE + 0x003C))
+#define SRDO_TSTCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0040))
+#define SRDO_CLKCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0048))
+#define SRDO_STATUS1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0050))
+#define SRDO_INBUF_DAT1 ((APBADDR32)(CS_CDO_REG_BASE + 0x0054))
+#define SRDO_FNDO_MEMCTL ((APBADDR32)(CS_CDO_REG_BASE + 0x0058))
+#define SRDO_THRESH ((APBADDR32)(CS_CDO_REG_BASE + 0x005C))
+#define SRDO_TST_DBG ((APBADDR32)(CS_CDO_REG_BASE + 0x0060))
+#define SRDO_DONE ((APBADDR32)(CS_CDO_REG_BASE + 0x0064))
+#define SRDO_PATHINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0080))
+#define SRDO_PLTLIST ((APBADDR32)(CS_CDO_REG_BASE + 0x0100))
+#define SRDO_PLTINFO ((APBADDR32)(CS_CDO_REG_BASE + 0x0200))
+#define SRDO_PATHBUF ((APBADDR32)(CS_CDO_REG_BASE + 0x0800))
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*HWD_SRDO_START*/
+#define START_START_SHIFT 0 /* [0] */
+#define START_SRDO_START_DLY_EN_SHIFT 1 /* [1] */
+#define START_SRDO_START_DLY_CNT_SHIFT 2 /* [21:2] */
+
+#define START_START_MASK 0x00000001 << START_START_SHIFT
+#define START_SRDO_START_DLY_EN_MASK 0x00000001 << START_SRDO_START_DLY_EN_SHIFT
+#define START_SRDO_START_DLY_CNT_MASK 0x000FFFFF << START_SRDO_START_DLY_CNT_SHIFT
+
+
+/*HWD_SRDO_PAUSE*/
+#define PAUSE_PAUSE_SHIFT 0 /* [0] */
+#define PAUSE_PAUSE_MASK 0x00000001 << PAUSE_PAUSE_SHIFT
+
+/*HWD_SRDO_RST*/
+#define RST_RST_SHIFT 0 /* [0] */
+#define RST_RST_MASK 0x00000001 << RST_RST_SHIFT
+
+/*HWD_SRDO_INBUF_CTL*/
+#define INBUF_CTL_ANTENNA_INIT_EN_SHIFT 19 /* [19] */
+#define INBUF_CTL_ANTENNA_INIT_SHIFT 18 /* [18] */
+#define INBUF_CTL_IIR_A_IB_SHIFT 16 /* [17:16] */
+#define INBUF_CTL_DUAL_SHIFT 15 /* [15] */
+#define INBUF_CTL_BURST_SHIFT 14 /* [14] */
+#define INBUF_CTL_ANT_MODE_SHIFT 12 /* [13:12] */
+#define INBUF_CTL_CAPTURE_SHIFT 11 /* [11] */
+#define INBUF_CTL_CAPLEN_SHIFT 8 /* [10:8] */
+#define INBUF_CTL_BUFFCAPT_SHIFT 4 /* [7:4] */
+#define INBUF_CTL_BUFFCAPINT_SHIFT 0 /* [3:0] */
+
+#define INBUF_ANTENNA_INIT_EN_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_EN_SHIFT
+#define INBUF_ANTENNA_INIT_MASK 0x00000001 << INBUF_CTL_ANTENNA_INIT_SHIFT
+#define INBUF_CTL_IIR_A_IB_MASK 0x00000003 << INBUF_CTL_IIR_A_IB_SHIFT
+#define INBUF_CTL_DUAL_MASK 0x00000001 << INBUF_CTL_DUAL_SHIFT
+#define INBUF_CTL_BURST_MASK 0x00000001 << INBUF_CTL_BURST_SHIFT
+#define INBUF_CTL_ANT_MODE_MASK 0x00000003 << INBUF_CTL_ANT_MODE_SHIFT
+#define INBUF_CTL_CAPTURE_MASK 0x00000001 << INBUF_CTL_CAPTURE_SHIFT
+#define INBUF_CTL_CAPLEN_MASK 0x00000007 << INBUF_CTL_CAPLEN_SHIFT
+#define INBUF_CTL_BUFFCAPT_MASK 0x0000000f << INBUF_CTL_BUFFCAPT_SHIFT
+#define INBUF_CTL_BUFFCAPINT_MASK 0x0000000f << INBUF_CTL_BUFFCAPINT_SHIFT
+
+
+/*HWD_SRDO_CTL*/
+#define CTL_CLEAR_SHIFT 9 /* [9] */
+#define CTL_ACQMODE_SHIFT 8 /* [8] */
+#define CTL_SEARCH_SET_SHIFT 6 /* [7:6] */
+#define CTL_SEARCH_N_SHIFT 0 /* [5:0] */
+
+#define CTL_CLEAR_MASK 0x00000001 << CTL_CLEAR_SHIFT
+#define CTL_ACQMODE_MASK 0x00000001 << CTL_ACQMODE_SHIFT
+#define CTL_SEARCH_SET_MASK 0x00000003 << CTL_SEARCH_SET_SHIFT
+#define CTL_SEARCH_N_MASK 0x0000003f << CTL_SEARCH_N_SHIFT
+
+/*HWD_SRDO_GENSTAT0*/
+#define GENSTAT0_COHLEN_SHIFT 17 /* [18:17] */
+#define GENSTAT0_PASSCNT1_SHIFT 12 /* [16:12] */
+#define GENSTAT0_PASSCNT2_SHIFT 6 /* [11:6] */
+#define GENSTAT0_SHIFT1_SHIFT 3 /* [5:3] */
+#define GENSTAT0_SHIFT2_SHIFT 0 /* [2:0] */
+
+#define GENSTAT0_COHLEN_MASK 0x00000003 << GENSTAT0_COHLEN_SHIFT
+#define GENSTAT0_PASSCNT1_MASK 0x0000001f << GENSTAT0_PASSCNT1_SHIFT
+#define GENSTAT0_PASSCNT2_MASK 0x0000003f << GENSTAT0_PASSCNT2_SHIFT
+#define GENSTAT0_SHIFT1_MASK 0x00000007 << GENSTAT0_SHIFT1_SHIFT
+#define GENSTAT0_SHIFT2_MASK 0x00000007 << GENSTAT0_SHIFT2_SHIFT
+
+/*HWD_SRDO_GENSTAT1*/
+#define GENSTAT1_THRESH1M_SHIFT 8 /* [15:8] */
+#define GENSTAT1_THRESH2M_SHIFT 0 /* [7:0] */
+#define GENSTAT1_THRESH1M_MASK 0x000000ff << GENSTAT1_THRESH1M_SHIFT
+#define GENSTAT1_THRESH2M_MASK 0x000000ff << GENSTAT1_THRESH2M_SHIFT
+
+/*HWD_SRDO_PATHMAINT*/
+#define PATHMAINT_PATHMAINT_MODE_SHIFT 3 /* [3] */
+#define PATHMAINT_CLR_NUMSEARCH_SHIFT 2 /* [2] */
+#define PATHMAINT_IIR_A_SHIFT 0 /* [1:0] */
+#define PATHMAINT_PATHMAINT_MODE_MASK 0x00000001 << PATHMAINT_PATHMAINT_MODE_SHIFT
+#define PATHMAINT_CLR_NUMSEARCH_MASK 0x00000001 << PATHMAINT_CLR_NUMSEARCH_SHIFT
+#define PATHMAINT_IIR_A_MASK 0x00000003 << PATHMAINT_IIR_A_SHIFT
+
+/*HWD_SRDO_INBUF0_ADR*/
+#define INBUF_ADR_INBUF_ADR_SHIFT 0 /* [13:0] */
+#define INBUF_ADR_INBUF_ADR_MASK 0x00003fff << INBUF_ADR_INBUF_ADR_SHIFT
+
+/*HWD_SRDO_INBUF_DAT*/
+#define INBUF_DAT_INBUF_DAT0_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT0_MASK 0x000fffff << INBUF_DAT_INBUF_DAT0_SHIFT
+
+/*HWD_SRDO_INBUF_DAT1*/
+#define INBUF_DAT_INBUF_DAT1_SHIFT 0 /* [19:0] */
+#define INBUF_DAT_INBUF_DAT1_MASK 0x000fffff << INBUF_DAT_INBUF_DAT1_SHIFT
+
+
+/*HWD_SRDO_STATUS0*/
+#define STATUS0_ANTENNA_SHIFT 24 /* [24] */
+#define STATUS0_BUSY_SHIFT 23 /* [23] */
+#define STATUS0_INMAG_INST_SHIFT 15 /* [22:15] */
+#define STATUS0_INMAG_IIR_SHIFT 7 /* [14:7] */
+#define STATUS0_BUFCAPTMHS_SHIFT 0 /* [6:0] */
+
+#define STATUS0_ANTENNA_MASK 0x00000001 << STATUS0_ANTENNA_SHIFT
+#define STATUS0_BUSY_MASK 0x00000001 << STATUS0_BUSY_SHIFT
+#define STATUS0_INMAG_INST_MASK 0x000000ff << STATUS0_INMAG_INST_SHIFT
+#define STATUS0_INMAG_IIR_MASK 0x000000ff << STATUS0_INMAG_IIR_SHIFT
+#define STATUS0_BUFCAPTMHS_MASK 0x0000007f << STATUS0_BUFCAPTMHS_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR1*/
+#define PLTINFO_CLR1_CLR_SHIFT 0 /* [23:0] */
+#define PLTINFO_CLR1_CLR_MASK 0x00ffffff << PLTINFO_CLR1_CLR_SHIFT
+
+/*HWD_SRDO_PLTINFO_CLR0*/
+#define PLTINFO_CLR0_CLR_SHIFT 0 /* [31:0] */
+#define PLTINFO_CLR0_CLR_MASK 0xffffffff << PLTINFO_CLR0_CLR_SHIFT
+
+/*HWD_SRDO_PATHINFO_CLR*/
+#define PATHINFO_CLR_CLR_SHIFT 0 /* [19:0] */
+#define PATHINFO_CLR_CLR_MASK 0x000fffff << PATHINFO_CLR_CLR_SHIFT
+
+/*HWD_SRDO_ACQ_CTL*/
+#define ACQ_CTL_ACQ_WIN_SHIFT 11 /* [20:11] */
+#define ACQ_CTL_ACQ_OFFSET_SHIFT 0 /* [10:0] */
+#define ACQ_CTL_ACQ_WIN_MASK 0x000003ff << ACQ_CTL_ACQ_WIN_SHIFT
+#define ACQ_CTL_ACQ_OFFSET_MASK 0x000007ff << ACQ_CTL_ACQ_OFFSET_SHIFT
+
+/*HWD_SRDO_TSTCTL*/
+#define TSTCTL_INBUF_TST_MODE_SHIFT 0 /* [0] */
+#define TSTCTL_INBUF_TST_MODE_MASK 1 << TSTCTL_INBUF_TST_MODE_SHIFT
+
+/*HWD_SRDO_STATUS1, NOTE: start from bit 7*/
+#define STATUS1_INMAG_INST1_SHIFT 15 /* [22:15] */
+#define STATUS1_INMAG_IIR1_SHIFT 7 /* [14:7] */
+#define STATUS1_INMAG_INST1_MASK 0x000000ff << STATUS1_INMAG_INST1_SHIFT
+#define STATUS1_INMAG_IIR1_MASK 0x000000ff << STATUS1_INMAG_IIR1_SHIFT
+
+
+/*HWD_SRDO_TSTSEL*/
+#define TSTSEL_TST_SEL_SHIFT 0 /* [7:0] */
+#define TSTSEL_TST_SEL_MASK 0x000000ff << TSTSEL_TST_SEL_SHIFT
+
+/*HWD_SRDO_PATHINFO*/
+#define PATHINFO_MAX 20
+#define PATHINFO_LEN 4 /* byte */
+
+#define PATHINFO_ENABLE_SHIFT 22 /* [22] */
+#define PATHINFO_KEEP_SHIFT 21 /* [21] */
+#define PATHINFO_WIN_SHIFT 17 /* [20:17] */
+#define PATHINFO_PILOTPNNUM_SHIFT 8 /* [16:8] */
+#define PATHINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PATHINFO_ENABLE_MASK 0x00000001 << PATHINFO_ENABLE_SHIFT
+#define PATHINFO_KEEP_MASK 0x00000001 << PATHINFO_KEEP_SHIFT
+#define PATHINFO_WIN_MASK 0x0000000f << PATHINFO_WIN_SHIFT
+#define PATHINFO_PILOTPNNUM_MASK 0x000001ff << PATHINFO_PILOTPNNUM_SHIFT
+#define PATHINFO_SUMMAG_MASK 0x00000ff << PATHINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PLTLIST*/
+#define PLTLIST_MAX 56
+#define PLTLIST_LEN 4 /* byte */
+#define PLTLIST_ENABLE_SHIFT 26 /* [26] */
+#define PLTLIST_KEEP_SHIFT 25 /* [25] */
+#define PLTLIST_WIN_SHIFT 21 /* [24:21] */
+#define PLTLIST_ALWAYS_SEARCH_SHIFT 20 /* [20] */
+#define PLTLIST_PILOT_PN_SHIFT 11 /* [19:11] */
+#define PLTLIST_OFFSET_SHIFT 0 /* [10:0] */
+#define PLTLIST_WIN_MASK 0x0000000f << PLTLIST_WIN_SHIFT
+#define PLTLIST_ALWAYS_SEARCH_MASK 0x00000001 << PLTLIST_ALWAYS_SEARCH_SHIFT
+#define PLTLIST_PILOT_PN_MASK 0x000001ff << PLTLIST_PILOT_PN_SHIFT
+#define PLTLIST_OFFSET_MASK 0x000007ff << PLTLIST_OFFSET_SHIFT
+
+/*HWD_SRDO_PLTINFO*/
+#define PLTINFO_MAX 56
+#define PLTINFO_LEN 4 /* byte */
+#define PLTINFO_NUMSEARCH_SHIFT 8 /* [11:8] */
+#define PLTINFO_SUMMAG_SHIFT 0 /* [7:0] */
+#define PLTINFO_NUMSEARCH_MASK 0x0000000f << PLTINFO_NUMSEARCH_SHIFT
+#define PLTINFO_SUMMAG_MASK 0x000000ff << PLTINFO_SUMMAG_SHIFT
+
+/*HWD_SRDO_PATHBUF*/
+#define PATHBUF_MAX 16 /* total 16 path for each path ( 20 ) */
+#define PATHBUF_LEN 4 /* byte */
+#define PATHBUF_PATH_VALID_SHIFT 24 /* [24] */
+#define PATHBUF_NUMAVG_SHIFT 21 /* [23:21] */
+#define PATHBUF_ANTENNA_SHIFT 20 /* [20] */
+#define PATHBUF_OFFSET_SHIFT 8 /* [19:8] */
+#define PATHBUF_STAT_SHIFT 0 /* [7:0] */
+#define PATHBUF_PATH_VALID_MASK 0x00000001 << PATHBUF_PATH_VALID_SHIFT
+#define PATHBUF_NUMAVG_MASK 0x00000007 << PATHBUF_NUMAVG_SHIFT
+#define PATHBUF_ANTENNA_MASK 0x00000001 << PATHBUF_ANTENNA_SHIFT
+#define PATHBUF_OFFSET_MASK 0x00000fff << PATHBUF_OFFSET_SHIFT
+#define PATHBUF_STAT_MASK 0x000000ff << PATHBUF_STAT_SHIFT
+
+/*HWD_SRDO_CLKCTL*/
+#define CLKCTL_CLK_MODE_SHIFT 1 /* [1] */
+#define CLKCTL_CLKENB_SHIFT 0 /* [0] */
+#define CLKCTL_CLK_MODE_MASK (0x1 << CLKCTL_CLK_MODE_SHIFT)
+#define CLKCTL_CLKENB_MASK (0x1 << CLKCTL_CLKENB_SHIFT)
+
+/*SRDO_DONE*/
+#define SRDO_DONE_DONE_SHIFT 0
+#define SRDO_DONE_DONE_MASK 0x00000001 << SRDO_DONE_DONE_SHIFT
+#endif //#ifndef _CPH_EVDO_SCH_97_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdotxbrp.h b/mcu/interface/l1/cl1/common/HW/cphevdotxbrp.h
new file mode 100644
index 0000000..c87a5ad
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdotxbrp.h
@@ -0,0 +1,791 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_TX_BRP_H_
+#define _CPH_EVDO_TX_BRP_H_
+
+
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXBRP_EVDO_REG_BASE (0xa8018000)
+#else
+#define TXBRP_EVDO_REG_BASE (0xa8818000)
+#endif
+
+#define TXBRP_EVDO_end (TXBRP_EVDO_REG_BASE + 0x0408 + 1*4)
+
+
+
+#define TXBRP_WORK_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0000))
+#define TXBRP_GLOBAL_IRQ ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0008))
+#define TXBRP_GLOBAL_IRQ_MASK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x000c))
+#define TXBRP_GLOBAL_IRQ_CLR ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0010))
+#define TXBRP_DO_IRQ ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0038))
+#define TXBRP_DO_IRQ_MASK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x003c))
+#define TXBRP_DO_IRQ_CLR ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0040))
+#define TXBRP_SW_CKEN ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0050))
+#define TXBRP_CLK_CTRLSEL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0054))
+#define TXBRP_DEBUG_REG_BANK_SEL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0058))
+#define TXBRP_MEM_TEST_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x005c))
+#define TXBRP_TRIGGER_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0060))
+#define TXBRP_DI_SWAP_EN ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0064))
+#define TXBRP_DI_TEST_CFG ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0068))
+#define TXBRP_I_REG_ULTRA_PRE_EN ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x006c))
+#define TXBRP_I_REG_BEGIN_ULTRA_CNT ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0070))
+#define TXBRP_I_REG_ULTRA_WATER_MARK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0074))
+#define TXBRP_DI_DEBUG ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0078))
+#define TXBRP_DEBUG_TRIG_SEL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x007c))
+#define TXBRP_DEBUG_0 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0080))
+#define TXBRP_DEBUG_1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0084))
+#define TXBRP_ENC_FSM_STATE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0090))
+#define TXBRP_CRC_DBG_FLAG ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0094))
+#define TXBRP_INTLV_B_LWT_ST_0 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0098))
+#define TXBRP_INTLV_B_LWT_ST_1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x009c))
+#define TXBRP_CTRL_FSM_STATE1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00a0))
+#define TXBRP_CTRL_FSM_STATE2 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00a4))
+#define TXBRP_RM_FSM_STATE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00a8))
+#define TXBRP_RUMAP_FSM_STATE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00ac))
+#define TXBRP_TEST_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00c4))
+#define TXBRP_CRP_SW_READ_CTRL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00c8))
+#define TXBRP_C2K_READ_RST ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00cc))
+#define TXBRP_EVDO_START ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00ec))
+#define TXBRP_DO_TX_ENABLE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0110))
+#define TXBRP_DO_RRI_DATA_ACK0 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0114))
+#define TXBRP_DO_RRI_DATA_ACK1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0118))
+#define TXBRP_DO_RRI_DATA_ACK2 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x011c))
+#define TXBRP_DO_CHNL_TYPE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0124))
+#define TXBRP_DO_PROTOCOL_SUBTYP ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x012c))
+#define TXBRP_DO_TX_BYTE_SWAP ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0130))
+#define TXBRP_DO_TX_TEST3 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0134))
+#define TXBRP_EVDO_CHNL_BASE_ADDR ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x014c))
+#define TXBRP_DO_RRI_DATA_NAK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0150))
+#define TXBRP_EVDO_CHNL_BASE_ADDR1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0154))
+#define TXBRP_DO_INTERLACE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0158))
+#define TXBRP_DBG_CRC32 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x03bc))
+#define TXBRP_DBG_CRC32_RSLT_I ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x03c0))
+#define TXBRP_DBG_CRC32_RSLT_Q ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x03c4))
+#if defined(__MD93__)||defined(__MD95__)
+#define TXBRP_EVDO_SUBTYPE2_HLARQ_RESULT ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0408))
+#else
+#define TXBRP_EVDO_SUBTYPE2_HLARQ_RESULT ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0404))
+#endif
+
+#define WORK_MODE_WORK_MODE_LSB (0)
+#define WORK_MODE_WORK_MODE_WIDTH (5)
+#define WORK_MODE_WORK_MODE_MASK (0x0000001F)
+
+#define GLOBAL_IRQ_DI_ERR_IRQ_LSB (3)
+#define GLOBAL_IRQ_DI_ERR_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_DI_ERR_IRQ_MASK (0x00000008)
+#define GLOBAL_IRQ_DI_ERR_IRQ_BIT (0x00000008)
+
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_LSB (2)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_MASK (0x00000004)
+#define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_BIT (0x00000004)
+
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_LSB (1)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_MASK (0x00000002)
+#define GLOBAL_IRQ_MODE_SWITCH_IRQ_BIT (0x00000002)
+
+#define GLOBAL_IRQ_MODE_IRQ_LSB (0)
+#define GLOBAL_IRQ_MODE_IRQ_WIDTH (1)
+#define GLOBAL_IRQ_MODE_IRQ_MASK (0x00000001)
+#define GLOBAL_IRQ_MODE_IRQ_BIT (0x00000001)
+
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_LSB (3)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_MASK (0x00000008)
+#define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_BIT (0x00000008)
+
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_LSB (2)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_MASK (0x00000004)
+#define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_BIT (0x00000004)
+
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_LSB (1)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_MASK (0x00000002)
+#define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_BIT (0x00000002)
+
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_LSB (0)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_WIDTH (1)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_MASK (0x00000001)
+#define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_BIT (0x00000001)
+
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_LSB (3)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_MASK (0x00000008)
+#define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_BIT (0x00000008)
+
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_LSB (2)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_MASK (0x00000004)
+#define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_BIT (0x00000004)
+
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_LSB (1)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_MASK (0x00000002)
+#define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_BIT (0x00000002)
+
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_LSB (0)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_WIDTH (1)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_MASK (0x00000001)
+#define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_BIT (0x00000001)
+
+#define DO_IRQ_DO_TRIG_ERR_LSB (2)
+#define DO_IRQ_DO_TRIG_ERR_WIDTH (1)
+#define DO_IRQ_DO_TRIG_ERR_MASK (0x00000004)
+#define DO_IRQ_DO_TRIG_ERR_BIT (0x00000004)
+
+#define DO_IRQ_DO_RD_ERR_LSB (1)
+#define DO_IRQ_DO_RD_ERR_WIDTH (1)
+#define DO_IRQ_DO_RD_ERR_MASK (0x00000002)
+#define DO_IRQ_DO_RD_ERR_BIT (0x00000002)
+
+#define DO_IRQ_DO_DONE_LSB (0)
+#define DO_IRQ_DO_DONE_WIDTH (1)
+#define DO_IRQ_DO_DONE_MASK (0x00000001)
+#define DO_IRQ_DO_DONE_BIT (0x00000001)
+
+#define DO_IRQ_MASK_DO_TRIG_ERR_MASK_LSB (2)
+#define DO_IRQ_MASK_DO_TRIG_ERR_MASK_WIDTH (1)
+#define DO_IRQ_MASK_DO_TRIG_ERR_MASK_MASK (0x00000004)
+#define DO_IRQ_MASK_DO_TRIG_ERR_MASK_BIT (0x00000004)
+
+#define DO_IRQ_MASK_DO_RD_ERR_MASK_LSB (1)
+#define DO_IRQ_MASK_DO_RD_ERR_MASK_WIDTH (1)
+#define DO_IRQ_MASK_DO_RD_ERR_MASK_MASK (0x00000002)
+#define DO_IRQ_MASK_DO_RD_ERR_MASK_BIT (0x00000002)
+
+#define DO_IRQ_MASK_DO_DONE_MASK_LSB (0)
+#define DO_IRQ_MASK_DO_DONE_MASK_WIDTH (1)
+#define DO_IRQ_MASK_DO_DONE_MASK_MASK (0x00000001)
+#define DO_IRQ_MASK_DO_DONE_MASK_BIT (0x00000001)
+
+#define DO_IRQ_CLR_DO_TRIG_ERR_CLR_LSB (2)
+#define DO_IRQ_CLR_DO_TRIG_ERR_CLR_WIDTH (1)
+#define DO_IRQ_CLR_DO_TRIG_ERR_CLR_MASK (0x00000004)
+#define DO_IRQ_CLR_DO_TRIG_ERR_CLR_BIT (0x00000004)
+
+#define DO_IRQ_CLR_DO_RD_ERR_CLR_LSB (1)
+#define DO_IRQ_CLR_DO_RD_ERR_CLR_WIDTH (1)
+#define DO_IRQ_CLR_DO_RD_ERR_CLR_MASK (0x00000002)
+#define DO_IRQ_CLR_DO_RD_ERR_CLR_BIT (0x00000002)
+
+#define DO_IRQ_CLR_DO_DONE_CLR_LSB (0)
+#define DO_IRQ_CLR_DO_DONE_CLR_WIDTH (1)
+#define DO_IRQ_CLR_DO_DONE_CLR_MASK (0x00000001)
+#define DO_IRQ_CLR_DO_DONE_CLR_BIT (0x00000001)
+
+#define TXBRP_SW_CKEN_APB_SW_CKEN_LSB (10)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_MASK (0x00000400)
+#define TXBRP_SW_CKEN_APB_SW_CKEN_BIT (0x00000400)
+
+#define TXBRP_SW_CKEN_OB_SW_CKEN_LSB (9)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_MASK (0x00000200)
+#define TXBRP_SW_CKEN_OB_SW_CKEN_BIT (0x00000200)
+
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_LSB (8)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_MASK (0x00000100)
+#define TXBRP_SW_CKEN_RUMAP_SW_CKEN_BIT (0x00000100)
+
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_LSB (7)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_MASK (0x00000080)
+#define TXBRP_SW_CKEN_INTL2_SW_CKEN_BIT (0x00000080)
+
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_LSB (6)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_MASK (0x00000040)
+#define TXBRP_SW_CKEN_INTL1_SW_CKEN_BIT (0x00000040)
+
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_LSB (5)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_MASK (0x00000020)
+#define TXBRP_SW_CKEN_SCR_SW_CKEN_BIT (0x00000020)
+
+#define TXBRP_SW_CKEN_RM_SW_CKEN_LSB (4)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_MASK (0x00000010)
+#define TXBRP_SW_CKEN_RM_SW_CKEN_BIT (0x00000010)
+
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_LSB (3)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_MASK (0x00000008)
+#define TXBRP_SW_CKEN_ENC_SW_CKEN_BIT (0x00000008)
+
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_LSB (2)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_MASK (0x00000004)
+#define TXBRP_SW_CKEN_CRC_SW_CKEN_BIT (0x00000004)
+
+#define TXBRP_SW_CKEN_DI_SW_CKEN_LSB (1)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_MASK (0x00000002)
+#define TXBRP_SW_CKEN_DI_SW_CKEN_BIT (0x00000002)
+
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_LSB (0)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_WIDTH (1)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_MASK (0x00000001)
+#define TXBRP_SW_CKEN_TXBRP_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_LSB (10)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_MASK (0x00000400)
+#define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_BIT (0x00000400)
+
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_LSB (9)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_MASK (0x00000200)
+#define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_BIT (0x00000200)
+
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_LSB (8)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_MASK (0x00000100)
+#define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_BIT (0x00000100)
+
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_LSB (7)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_MASK (0x00000080)
+#define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_BIT (0x00000080)
+
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_LSB (6)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_MASK (0x00000040)
+#define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_BIT (0x00000040)
+
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_LSB (5)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_MASK (0x00000020)
+#define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_BIT (0x00000020)
+
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_LSB (4)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_MASK (0x00000010)
+#define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_BIT (0x00000010)
+
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_LSB (3)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_MASK (0x00000008)
+#define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_BIT (0x00000008)
+
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_LSB (2)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_MASK (0x00000004)
+#define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_BIT (0x00000004)
+
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_LSB (1)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_MASK (0x00000002)
+#define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_BIT (0x00000002)
+
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_LSB (0)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_WIDTH (1)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_MASK (0x00000001)
+#define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_BIT (0x00000001)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_LSB (24)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_MASK (0xFF000000)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_LSB (16)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_MASK (0x00FF0000)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_LSB (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_MASK (0x0000FF00)
+
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_LSB (0)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_WIDTH (8)
+#define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_MASK (0x000000FF)
+
+#define MEM_TEST_MODE_MEM_TEST_MODE_LSB (0)
+#define MEM_TEST_MODE_MEM_TEST_MODE_WIDTH (1)
+#define MEM_TEST_MODE_MEM_TEST_MODE_MASK (0x00000001)
+#define MEM_TEST_MODE_MEM_TEST_MODE_BIT (0x00000001)
+
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_LSB (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_WIDTH (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_MASK (0x00000002)
+#define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_BIT (0x00000002)
+
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_LSB (0)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_WIDTH (1)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_MASK (0x00000001)
+#define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_BIT (0x00000001)
+
+#define DI_SWAP_EN_DI_SWAP_EN_LSB (0)
+#define DI_SWAP_EN_DI_SWAP_EN_WIDTH (3)
+#define DI_SWAP_EN_DI_SWAP_EN_MASK (0x00000007)
+
+#define DI_TEST_CFG_DI_TEST_MODE_EN_LSB (10)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_WIDTH (1)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_MASK (0x00000400)
+#define DI_TEST_CFG_DI_TEST_MODE_EN_BIT (0x00000400)
+
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_LSB (8)
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_WIDTH (2)
+#define DI_TEST_CFG_DI_TEST_DATA_SEL_MASK (0x00000300)
+
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_LSB (0)
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_WIDTH (8)
+#define DI_TEST_CFG_DI_TEST_RAND_SEED_MASK (0x000000FF)
+
+#define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_LSB (0)
+#define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_WIDTH (1)
+#define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_MASK (0x00000001)
+#define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_BIT (0x00000001)
+
+#define I_REG_BEGIN_ULTRA_CNT_I_REG_BEGIN_ULTRA_CNT_LSB (0)
+#define I_REG_BEGIN_ULTRA_CNT_I_REG_BEGIN_ULTRA_CNT_WIDTH (3)
+#define I_REG_BEGIN_ULTRA_CNT_I_REG_BEGIN_ULTRA_CNT_MASK (0x00000007)
+
+#define I_REG_ULTRA_WATER_MARK_I_REG_ULTRA_WATER_MARK_LSB (0)
+#define I_REG_ULTRA_WATER_MARK_I_REG_ULTRA_WATER_MARK_WIDTH (3)
+#define I_REG_ULTRA_WATER_MARK_I_REG_ULTRA_WATER_MARK_MASK (0x00000007)
+
+#define DI_DEBUG_DMA0_STATE_LSB (20)
+#define DI_DEBUG_DMA0_STATE_WIDTH (2)
+#define DI_DEBUG_DMA0_STATE_MASK (0x00300000)
+
+#define DI_DEBUG_RAM_RD_STATE_LSB (16)
+#define DI_DEBUG_RAM_RD_STATE_WIDTH (2)
+#define DI_DEBUG_RAM_RD_STATE_MASK (0x00030000)
+
+#define DI_DEBUG_O_DMA0_UTR_LSB (13)
+#define DI_DEBUG_O_DMA0_UTR_WIDTH (1)
+#define DI_DEBUG_O_DMA0_UTR_MASK (0x00002000)
+#define DI_DEBUG_O_DMA0_UTR_BIT (0x00002000)
+
+#define DI_DEBUG_O_DMA0_PTR_UTR_LSB (12)
+#define DI_DEBUG_O_DMA0_PTR_UTR_WIDTH (1)
+#define DI_DEBUG_O_DMA0_PTR_UTR_MASK (0x00001000)
+#define DI_DEBUG_O_DMA0_PTR_UTR_BIT (0x00001000)
+
+#define DI_DEBUG_O_DMA0_RD_REQ_LSB (10)
+#define DI_DEBUG_O_DMA0_RD_REQ_WIDTH (1)
+#define DI_DEBUG_O_DMA0_RD_REQ_MASK (0x00000400)
+#define DI_DEBUG_O_DMA0_RD_REQ_BIT (0x00000400)
+
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_LSB (9)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_WIDTH (1)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_MASK (0x00000200)
+#define DI_DEBUG_DMA_ALL_RDATA_DONE_BIT (0x00000200)
+
+#define DI_DEBUG_RAM_FULL_LSB (8)
+#define DI_DEBUG_RAM_FULL_WIDTH (1)
+#define DI_DEBUG_RAM_FULL_MASK (0x00000100)
+#define DI_DEBUG_RAM_FULL_BIT (0x00000100)
+
+#define DI_DEBUG_CHECK_DONE_LSB (7)
+#define DI_DEBUG_CHECK_DONE_WIDTH (1)
+#define DI_DEBUG_CHECK_DONE_MASK (0x00000080)
+#define DI_DEBUG_CHECK_DONE_BIT (0x00000080)
+
+#define DI_DEBUG_DI_OUT_BIT_FINISH_LSB (6)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_WIDTH (1)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_MASK (0x00000040)
+#define DI_DEBUG_DI_OUT_BIT_FINISH_BIT (0x00000040)
+
+#define DI_DEBUG_RAM_ALL_RDATA_READ_LSB (5)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_WIDTH (1)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_MASK (0x00000020)
+#define DI_DEBUG_RAM_ALL_RDATA_READ_BIT (0x00000020)
+
+#define DI_DEBUG_DI_BUSY_LSB (4)
+#define DI_DEBUG_DI_BUSY_WIDTH (1)
+#define DI_DEBUG_DI_BUSY_MASK (0x00000010)
+#define DI_DEBUG_DI_BUSY_BIT (0x00000010)
+
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_LSB (3)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_MASK (0x00000008)
+#define DI_DEBUG_CRC_BUF_PING_EMPTY_BIT (0x00000008)
+
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_LSB (2)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_WIDTH (1)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_MASK (0x00000004)
+#define DI_DEBUG_CTC_BUF_PONG_EMPTY_BIT (0x00000004)
+
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_LSB (1)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_MASK (0x00000002)
+#define DI_DEBUG_CRC_BUF_LOAD_SEL_BIT (0x00000002)
+
+#define DI_DEBUG_CRC_BUF_OUT_SEL_LSB (0)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_WIDTH (1)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_MASK (0x00000001)
+#define DI_DEBUG_CRC_BUF_OUT_SEL_BIT (0x00000001)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_LSB (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_WIDTH (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_MASK (0x0000FF00)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_WIDTH (8)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_MASK (0x000000FF)
+
+#define TXBRP_DEBUG_0_TXBRP_DEBUG_0_LSB (0)
+#define TXBRP_DEBUG_0_TXBRP_DEBUG_0_WIDTH (32)
+#define TXBRP_DEBUG_0_TXBRP_DEBUG_0_MASK (0xFFFFFFFF)
+
+#define TXBRP_DEBUG_1_TXBRP_DEBUG_1_LSB (0)
+#define TXBRP_DEBUG_1_TXBRP_DEBUG_1_WIDTH (32)
+#define TXBRP_DEBUG_1_TXBRP_DEBUG_1_MASK (0xFFFFFFFF)
+
+#define ENC_FSM_STATE_wt_conv_state_LSB (17)
+#define ENC_FSM_STATE_wt_conv_state_WIDTH (3)
+#define ENC_FSM_STATE_wt_conv_state_MASK (0x000E0000)
+
+#define ENC_FSM_STATE_lte_state_LSB (13)
+#define ENC_FSM_STATE_lte_state_WIDTH (4)
+#define ENC_FSM_STATE_lte_state_MASK (0x0001E000)
+
+#define ENC_FSM_STATE_codec_dis_state_LSB (10)
+#define ENC_FSM_STATE_codec_dis_state_WIDTH (3)
+#define ENC_FSM_STATE_codec_dis_state_MASK (0x00001C00)
+
+#define ENC_FSM_STATE_codec_en_state_LSB (6)
+#define ENC_FSM_STATE_codec_en_state_WIDTH (4)
+#define ENC_FSM_STATE_codec_en_state_MASK (0x000003C0)
+
+#define ENC_FSM_STATE_codec_w_state_LSB (3)
+#define ENC_FSM_STATE_codec_w_state_WIDTH (3)
+#define ENC_FSM_STATE_codec_w_state_MASK (0x00000038)
+
+#define ENC_FSM_STATE_codec_state_LSB (0)
+#define ENC_FSM_STATE_codec_state_WIDTH (3)
+#define ENC_FSM_STATE_codec_state_MASK (0x00000007)
+
+#define CRC_DBG_FLAG_crc_len_dbg_LSB (26)
+#define CRC_DBG_FLAG_crc_len_dbg_WIDTH (5)
+#define CRC_DBG_FLAG_crc_len_dbg_MASK (0x7C000000)
+
+#define CRC_DBG_FLAG_rtt_rc_idx_dbg_LSB (25)
+#define CRC_DBG_FLAG_rtt_rc_idx_dbg_WIDTH (1)
+#define CRC_DBG_FLAG_rtt_rc_idx_dbg_MASK (0x02000000)
+#define CRC_DBG_FLAG_rtt_rc_idx_dbg_BIT (0x02000000)
+
+#define CRC_DBG_FLAG_cqi_or_data_dbg_LSB (24)
+#define CRC_DBG_FLAG_cqi_or_data_dbg_WIDTH (1)
+#define CRC_DBG_FLAG_cqi_or_data_dbg_MASK (0x01000000)
+#define CRC_DBG_FLAG_cqi_or_data_dbg_BIT (0x01000000)
+
+#define CRC_DBG_FLAG_crc_state_dbg_LSB (16)
+#define CRC_DBG_FLAG_crc_state_dbg_WIDTH (6)
+#define CRC_DBG_FLAG_crc_state_dbg_MASK (0x003F0000)
+
+#define CRC_DBG_FLAG_bit_cnt_dbg_LSB (0)
+#define CRC_DBG_FLAG_bit_cnt_dbg_WIDTH (15)
+#define CRC_DBG_FLAG_bit_cnt_dbg_MASK (0x00007FFF)
+
+#define INTLV_B_LWT_ST_0_lte_wen_st_LSB (15)
+#define INTLV_B_LWT_ST_0_lte_wen_st_WIDTH (3)
+#define INTLV_B_LWT_ST_0_lte_wen_st_MASK (0x00038000)
+
+#define INTLV_B_LWT_ST_0_ts_w_state_LSB (12)
+#define INTLV_B_LWT_ST_0_ts_w_state_WIDTH (3)
+#define INTLV_B_LWT_ST_0_ts_w_state_MASK (0x00007000)
+
+#define INTLV_B_LWT_ST_0_ts_r_state_LSB (9)
+#define INTLV_B_LWT_ST_0_ts_r_state_WIDTH (3)
+#define INTLV_B_LWT_ST_0_ts_r_state_MASK (0x00000E00)
+
+#define INTLV_B_LWT_ST_0_pp_w_state_upa_LSB (6)
+#define INTLV_B_LWT_ST_0_pp_w_state_upa_WIDTH (3)
+#define INTLV_B_LWT_ST_0_pp_w_state_upa_MASK (0x000001C0)
+
+#define INTLV_B_LWT_ST_0_pp_w_state_dch_LSB (3)
+#define INTLV_B_LWT_ST_0_pp_w_state_dch_WIDTH (3)
+#define INTLV_B_LWT_ST_0_pp_w_state_dch_MASK (0x00000038)
+
+#define INTLV_B_LWT_ST_0_sec_intlv_state_LSB (0)
+#define INTLV_B_LWT_ST_0_sec_intlv_state_WIDTH (3)
+#define INTLV_B_LWT_ST_0_sec_intlv_state_MASK (0x00000007)
+
+#define INTLV_B_LWT_ST_1_clm_cnt_LSB (25)
+#define INTLV_B_LWT_ST_1_clm_cnt_WIDTH (5)
+#define INTLV_B_LWT_ST_1_clm_cnt_MASK (0x3E000000)
+
+#define INTLV_B_LWT_ST_1_row_cnt_LSB (22)
+#define INTLV_B_LWT_ST_1_row_cnt_WIDTH (3)
+#define INTLV_B_LWT_ST_1_row_cnt_MASK (0x01C00000)
+
+#define INTLV_B_LWT_ST_1_blk_cnt_LSB (14)
+#define INTLV_B_LWT_ST_1_blk_cnt_WIDTH (8)
+#define INTLV_B_LWT_ST_1_blk_cnt_MASK (0x003FC000)
+
+#define INTLV_B_LWT_ST_1_sec_reqo_LSB (13)
+#define INTLV_B_LWT_ST_1_sec_reqo_WIDTH (1)
+#define INTLV_B_LWT_ST_1_sec_reqo_MASK (0x00002000)
+#define INTLV_B_LWT_ST_1_sec_reqo_BIT (0x00002000)
+
+#define INTLV_B_LWT_ST_1_ppr_req_upa_LSB (9)
+#define INTLV_B_LWT_ST_1_ppr_req_upa_WIDTH (4)
+#define INTLV_B_LWT_ST_1_ppr_req_upa_MASK (0x00001E00)
+
+#define INTLV_B_LWT_ST_1_ppr_read_done_upa_LSB (5)
+#define INTLV_B_LWT_ST_1_ppr_read_done_upa_WIDTH (4)
+#define INTLV_B_LWT_ST_1_ppr_read_done_upa_MASK (0x000001E0)
+
+#define INTLV_B_LWT_ST_1_second_intlv_done_upa_LSB (4)
+#define INTLV_B_LWT_ST_1_second_intlv_done_upa_WIDTH (1)
+#define INTLV_B_LWT_ST_1_second_intlv_done_upa_MASK (0x00000010)
+#define INTLV_B_LWT_ST_1_second_intlv_done_upa_BIT (0x00000010)
+
+#define INTLV_B_LWT_ST_1_ppr_req_dch_LSB (3)
+#define INTLV_B_LWT_ST_1_ppr_req_dch_WIDTH (1)
+#define INTLV_B_LWT_ST_1_ppr_req_dch_MASK (0x00000008)
+#define INTLV_B_LWT_ST_1_ppr_req_dch_BIT (0x00000008)
+
+#define INTLV_B_LWT_ST_1_ppr_read_done_dch_LSB (2)
+#define INTLV_B_LWT_ST_1_ppr_read_done_dch_WIDTH (1)
+#define INTLV_B_LWT_ST_1_ppr_read_done_dch_MASK (0x00000004)
+#define INTLV_B_LWT_ST_1_ppr_read_done_dch_BIT (0x00000004)
+
+#define INTLV_B_LWT_ST_1_second_intlv_done_dch_LSB (1)
+#define INTLV_B_LWT_ST_1_second_intlv_done_dch_WIDTH (1)
+#define INTLV_B_LWT_ST_1_second_intlv_done_dch_MASK (0x00000002)
+#define INTLV_B_LWT_ST_1_second_intlv_done_dch_BIT (0x00000002)
+
+#define INTLV_B_LWT_ST_1_dch_edch_mode_LSB (0)
+#define INTLV_B_LWT_ST_1_dch_edch_mode_WIDTH (1)
+#define INTLV_B_LWT_ST_1_dch_edch_mode_MASK (0x00000001)
+#define INTLV_B_LWT_ST_1_dch_edch_mode_BIT (0x00000001)
+
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_LSB (20)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_WIDTH (6)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_MASK (0x03F00000)
+
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_LSB (0)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_WIDTH (20)
+#define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_MASK (0x000FFFFF)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_LSB (16)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_WIDTH (4)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_MASK (0x000F0000)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_LSB (7)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_WIDTH (9)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_MASK (0x0000FF80)
+
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_LSB (0)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_WIDTH (7)
+#define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_MASK (0x0000007F)
+
+#define RM_FSM_STATE_BIT_SEP_STATE_LSB (16)
+#define RM_FSM_STATE_BIT_SEP_STATE_WIDTH (3)
+#define RM_FSM_STATE_BIT_SEP_STATE_MASK (0x00070000)
+
+#define RM_FSM_STATE_BC_STATE_LSB (0)
+#define RM_FSM_STATE_BC_STATE_WIDTH (16)
+#define RM_FSM_STATE_BC_STATE_MASK (0x0000FFFF)
+
+#define RUMAP_FSM_STATE_BUF_STATE_LSB (5)
+#define RUMAP_FSM_STATE_BUF_STATE_WIDTH (1)
+#define RUMAP_FSM_STATE_BUF_STATE_MASK (0x00000020)
+#define RUMAP_FSM_STATE_BUF_STATE_BIT (0x00000020)
+
+#define RUMAP_FSM_STATE_RU_MAP_STATE_LSB (0)
+#define RUMAP_FSM_STATE_RU_MAP_STATE_WIDTH (5)
+#define RUMAP_FSM_STATE_RU_MAP_STATE_MASK (0x0000001F)
+
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_LSB (1)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_WIDTH (1)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_MASK (0x00000002)
+#define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_BIT (0x00000002)
+
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_LSB (0)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_WIDTH (1)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_MASK (0x00000001)
+#define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_BIT (0x00000001)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_LSB (13)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_MASK (0x00006000)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_LSB (11)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_MASK (0x00001800)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_LSB (9)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_MASK (0x00000600)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_LSB (7)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_MASK (0x00000180)
+
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_LSB (5)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_WIDTH (2)
+#define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_MASK (0x00000060)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_LSB (4)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_MASK (0x00000010)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_BIT (0x00000010)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_LSB (3)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_MASK (0x00000008)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_BIT (0x00000008)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_LSB (2)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_MASK (0x00000004)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_BIT (0x00000004)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_LSB (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_MASK (0x00000002)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_BIT (0x00000002)
+
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_LSB (0)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_WIDTH (1)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_MASK (0x00000001)
+#define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_BIT (0x00000001)
+
+#define C2K_READ_RST_C2K_READ_RST_LSB (0)
+#define C2K_READ_RST_C2K_READ_RST_WIDTH (1)
+#define C2K_READ_RST_C2K_READ_RST_MASK (0x00000001)
+#define C2K_READ_RST_C2K_READ_RST_BIT (0x00000001)
+
+#define EVDO_START_EVDO_START_LSB (0)
+#define EVDO_START_EVDO_START_WIDTH (1)
+#define EVDO_START_EVDO_START_MASK (0x00000001)
+#define EVDO_START_EVDO_START_BIT (0x00000001)
+
+#define DO_TX_ENABLE_Transmitter_Enable_LSB (0)
+#define DO_TX_ENABLE_Transmitter_Enable_WIDTH (1)
+#define DO_TX_ENABLE_Transmitter_Enable_MASK (0x00000001)
+#define DO_TX_ENABLE_Transmitter_Enable_BIT (0x00000001)
+
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Payload_Index_LSB (3)
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Payload_Index_WIDTH (4)
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Payload_Index_MASK (0x00000078)
+
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Channel_Rate_LSB (0)
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Channel_Rate_WIDTH (3)
+#define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Channel_Rate_MASK (0x00000007)
+
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_Payload_Index_LSB (3)
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_Payload_Index_WIDTH (4)
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_Payload_Index_MASK (0x00000078)
+
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_RRI_Symbol_rate_LSB (0)
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_RRI_Symbol_rate_WIDTH (3)
+#define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_RRI_Symbol_rate_MASK (0x00000007)
+
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_LSB (6)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_WIDTH (1)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_MASK (0x00000040)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_BIT (0x00000040)
+
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Payload_Index_LSB (2)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Payload_Index_WIDTH (4)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Payload_Index_MASK (0x0000003C)
+
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Sub_packet_index_LSB (0)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Sub_packet_index_WIDTH (2)
+#define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Sub_packet_index_MASK (0x00000003)
+
+#define DO_CHNL_TYPE_Channel_type_LSB (0)
+#define DO_CHNL_TYPE_Channel_type_WIDTH (1)
+#define DO_CHNL_TYPE_Channel_type_MASK (0x00000001)
+#define DO_CHNL_TYPE_Channel_type_BIT (0x00000001)
+
+#define DO_PROTOCOL_SUBTYP_Protocol_Subtype_LSB (0)
+#define DO_PROTOCOL_SUBTYP_Protocol_Subtype_WIDTH (1)
+#define DO_PROTOCOL_SUBTYP_Protocol_Subtype_MASK (0x00000001)
+#define DO_PROTOCOL_SUBTYP_Protocol_Subtype_BIT (0x00000001)
+
+#define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_LSB (0)
+#define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_WIDTH (1)
+#define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_MASK (0x00000001)
+#define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_BIT (0x00000001)
+
+#define DO_TX_TEST3_TX_ROW_ROT_LSB (0)
+#define DO_TX_TEST3_TX_ROW_ROT_WIDTH (1)
+#define DO_TX_TEST3_TX_ROW_ROT_MASK (0x00000001)
+#define DO_TX_TEST3_TX_ROW_ROT_BIT (0x00000001)
+
+#define EVDO_CHNL_BASE_ADDR_EVDO_CHNL_BASE_ADDR_LSB (0)
+#define EVDO_CHNL_BASE_ADDR_EVDO_CHNL_BASE_ADDR_WIDTH (32)
+#define EVDO_CHNL_BASE_ADDR_EVDO_CHNL_BASE_ADDR_MASK (0xFFFFFFFF)
+
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Payload_Index_LSB (2)
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Payload_Index_WIDTH (4)
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Payload_Index_MASK (0x0000003C)
+
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Sub_packet_index_LSB (0)
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Sub_packet_index_WIDTH (2)
+#define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Sub_packet_index_MASK (0x00000003)
+
+#define EVDO_CHNL_BASE_ADDR1_EVDO_CHNL_BASE_ADDR1_LSB (0)
+#define EVDO_CHNL_BASE_ADDR1_EVDO_CHNL_BASE_ADDR1_WIDTH (32)
+#define EVDO_CHNL_BASE_ADDR1_EVDO_CHNL_BASE_ADDR1_MASK (0xFFFFFFFF)
+
+#define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_LSB (0)
+#define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_WIDTH (1)
+#define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_MASK (0x00000001)
+#define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_BIT (0x00000001)
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+
+
+#endif //#ifndef _CPH_EVDO_TX_BRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdotxcrp.h b/mcu/interface/l1/cl1/common/HW/cphevdotxcrp.h
new file mode 100644
index 0000000..dfa8a61
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdotxcrp.h
@@ -0,0 +1,449 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_TXCRP_H_
+#define _CPH_EVDO_TXCRP_H_
+
+
+
+/*----------------------------------------------------------------------------
+ Global Typedefs
+----------------------------------------------------------------------------*/
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXCRP_C_EVDO_REG_BASE (0xA8100000)
+#else
+#define TXCRP_C_EVDO_REG_BASE (0xA8900000)
+#endif
+
+#define TXCRP_C_EVDO_end (TXCRP_C_EVDO_REG_BASE + 0x50110 + 1*4)
+
+
+
+#define TXCRP_DO_RRI_DATA_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50000))
+#define TXCRP_DO_RRI_DATA_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50004))
+#define TXCRP_DO_RRI_DATA_2_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50008))
+#define TXCRP_DO_RRI_DATA_2_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5000C))
+#define TXCRP_DO_DRC_COVER_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50010))
+#define TXCRP_DO_DRC_COVER_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50014))
+#define TXCRP_DO_DSC_DATA_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50018))
+#define TXCRP_DO_DSC_DATA_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5001C))
+#define TXCRP_DO_TX_LONG_PN_INITIAL1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50020))
+#define TXCRP_DO_TX_LONG_PN_INITIAL2 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50024))
+#define TXCRP_DO_LD_OFFSET ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50028))
+#define TXCRP_DO_RD_BASE_ADDR_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5002C))
+#define TXCRP_DO_RD_BASE_ADDR_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50030))
+#define TXCRP_DO_CHNL_TYPE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50034))
+#define TXCRP_DO_PROTOCOL_SUBTYP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50038))
+#define TXCRP_DO_TX_ENABLE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5003C))
+#define TXCRP_DO_TX_IQ_INV ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50040))
+#define TXCRP_DO_TX_LONG_PN_MASK2 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50044))
+#define TXCRP_DO_TX_LONG_PN_MASK1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50048))
+#define TXCRP_DO_LONGPN_LOAD ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5004C))
+#define TXCRP_DO_DRC_BOOST_LEN ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50050))
+#define TXCRP_DO_DSC_BOOST_LEN ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50054))
+#define TXCRP_DO_AUXPLT_MINPYLD ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50058))
+#define TXCRP_DO_PLT_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5005C))
+#define TXCRP_DO_AUXPLT_SCALE_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50060))
+#define TXCRP_DO_AUXPLT_SCALE_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50064))
+#define TXCRP_DO_RRI_SCALE_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50068))
+#define TXCRP_DO_RRI_SCALE_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5006C))
+#define TXCRP_DO_DSC_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50070))
+#define TXCRP_DO_DSC_SCALE_BOOST ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50074))
+#define TXCRP_DO_DRC_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50078))
+#define TXCRP_DO_DRC_SCALE_BOOST ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5007C))
+#define TXCRP_DO_BOOST_SELECT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50080))
+#define TXCRP_DO_DSC_SCALE_INDICATE_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50084))
+#define TXCRP_DO_DSC_SCALE_INDICATE_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50088))
+#define TXCRP_DO_DRC_SCALE_INDICATE_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5008C))
+#define TXCRP_DO_DRC_SCALE_INDICATE_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50090))
+#define TXCRP_DO_ACK_SCALE_SUP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50094))
+#define TXCRP_DO_ACK_SCALE_MUP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50098))
+#define TXCRP_DO_DATA_SCALE0_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5009C))
+#define TXCRP_DO_DATA_SCALE1_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500A0))
+#define TXCRP_DO_DATA_SCALE2_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500A4))
+#define TXCRP_DO_DATA_SCALE3_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500A8))
+#define TXCRP_DO_DATA_SCALE0_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500AC))
+#define TXCRP_DO_DATA_SCALE1_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500B0))
+#define TXCRP_DO_DATA_SCALE2_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500B4))
+#define TXCRP_DO_DATA_SCALE3_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500B8))
+#define TXCRP_DO_KS_TRIGGER ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500BC))
+#define TXCRP_DO_TRIGGER_SELECT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500C0))
+#define TXCRP_DO_DRC_SELECT_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500C4))
+#define TXCRP_DO_DRC_SELECT_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500C8))
+#define TXCRP_DO_SW_RST ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500CC))
+#define TXCRP_DO_PREPLT_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500D0))
+#define TXCRP_DO_ACK_ENABLE_BIT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500D4))
+#define TXCRP_DO_ACK_DATA ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500D8))
+#define TXCRP_DO_DATA_SCALE_KS_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500DC))
+#define TXCRP_DO_DATA_SCALE_KS_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500E0))
+#define TXCRP_DO_TX_FREEZE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500E4))
+#define TXCRP_DO_TIMER_TRIGGER ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500E8))
+#define TXCRP_DO_TX_TEST_MODE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500EC))
+#define TXCRP_DO_TX_TEST0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500F0))
+#define TXCRP_DO_TX_TEST1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500F4))
+#define TXCRP_DO_DRC_LENGTH ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500F8))
+#define TXCRP_DO_DRC_GATING ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500FC))
+#define TXCRP_STATE_Q ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50100))
+#define TXCRP_DO_TX_FSM ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50104))
+#define TXCRP_DRC_DATA_I ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50108))
+#define TXCRP_DOTXCRP_FSM_IS_BUSY ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5010C))
+#define TXCRP_CDO_CHIP_COUNT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50110))
+#define TXCRP_CDO_TICK_COUNT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50114))
+#define TXCRP_RAKE_TXCRP_REV_ACK_BIT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50118))
+#define TXCRP_TXCRP_KS0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5011C))
+#define TXCRP_TXCRP_KS1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50120))
+#define TXCRP_CDO_KS_VALUE_EXP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50124))
+#define TXCRP_CDO_KS_VALUE_MANTISSA ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50128))
+
+
+#define DO_RRI_DATA_0_DO_RRI_DATA_0_LSB (0)
+#define DO_RRI_DATA_0_DO_RRI_DATA_0_WIDTH (7)
+#define DO_RRI_DATA_0_DO_RRI_DATA_0_MASK (0x0000007F)
+
+#define DO_RRI_DATA_1_DO_RRI_DATA_1_LSB (0)
+#define DO_RRI_DATA_1_DO_RRI_DATA_1_WIDTH (7)
+#define DO_RRI_DATA_1_DO_RRI_DATA_1_MASK (0x0000007F)
+
+#define DO_RRI_DATA_2_ACK_DO_RRI_DATA_2_ACK_LSB (0)
+#define DO_RRI_DATA_2_ACK_DO_RRI_DATA_2_ACK_WIDTH (7)
+#define DO_RRI_DATA_2_ACK_DO_RRI_DATA_2_ACK_MASK (0x0000007F)
+
+#define DO_RRI_DATA_2_NAK_DO_RRI_DATA_2_NAK_LSB (0)
+#define DO_RRI_DATA_2_NAK_DO_RRI_DATA_2_NAK_WIDTH (7)
+#define DO_RRI_DATA_2_NAK_DO_RRI_DATA_2_NAK_MASK (0x0000007F)
+
+#define DO_DRC_COVER_0_DO_DRC_COVER_0_LSB (0)
+#define DO_DRC_COVER_0_DO_DRC_COVER_0_WIDTH (4)
+#define DO_DRC_COVER_0_DO_DRC_COVER_0_MASK (0x0000000F)
+
+#define DO_DRC_COVER_1_DO_DRC_COVER_1_LSB (0)
+#define DO_DRC_COVER_1_DO_DRC_COVER_1_WIDTH (4)
+#define DO_DRC_COVER_1_DO_DRC_COVER_1_MASK (0x0000000F)
+
+#define DO_DSC_DATA_0_DO_DSC_DATA_0_LSB (0)
+#define DO_DSC_DATA_0_DO_DSC_DATA_0_WIDTH (4)
+#define DO_DSC_DATA_0_DO_DSC_DATA_0_MASK (0x0000000F)
+
+#define DO_DSC_DATA_1_DO_DSC_DATA_1_LSB (0)
+#define DO_DSC_DATA_1_DO_DSC_DATA_1_WIDTH (4)
+#define DO_DSC_DATA_1_DO_DSC_DATA_1_MASK (0x0000000F)
+
+#define DO_TX_LONG_PN_INITIAL1_DO_TX_LONG_PN_INITIAL1_LSB (0)
+#define DO_TX_LONG_PN_INITIAL1_DO_TX_LONG_PN_INITIAL1_WIDTH (32)
+#define DO_TX_LONG_PN_INITIAL1_DO_TX_LONG_PN_INITIAL1_MASK (0xFFFFFFFF)
+
+#define DO_TX_LONG_PN_INITIAL2_DO_TX_LONG_PN_INITIAL2_LSB (0)
+#define DO_TX_LONG_PN_INITIAL2_DO_TX_LONG_PN_INITIAL2_WIDTH (10)
+#define DO_TX_LONG_PN_INITIAL2_DO_TX_LONG_PN_INITIAL2_MASK (0x000003FF)
+
+#define DO_LD_OFFSET_DO_LD_OFFSET_LSB (0)
+#define DO_LD_OFFSET_DO_LD_OFFSET_WIDTH (15)
+#define DO_LD_OFFSET_DO_LD_OFFSET_MASK (0x00007FFF)
+
+#define DO_RD_BASE_ADDR_ACK_DO_RD_BASE_ADDR_ACK_LSB (0)
+#define DO_RD_BASE_ADDR_ACK_DO_RD_BASE_ADDR_ACK_WIDTH (11)
+#define DO_RD_BASE_ADDR_ACK_DO_RD_BASE_ADDR_ACK_MASK (0x000007FF)
+
+#define DO_RD_BASE_ADDR_NAK_DO_RD_BASE_ADDR_NAK_LSB (0)
+#define DO_RD_BASE_ADDR_NAK_DO_RD_BASE_ADDR_NAK_WIDTH (11)
+#define DO_RD_BASE_ADDR_NAK_DO_RD_BASE_ADDR_NAK_MASK (0x000007FF)
+
+#define DO_CHNL_TYPE_DO_CHNL_TYPE_LSB (0)
+#define DO_CHNL_TYPE_DO_CHNL_TYPE_WIDTH (1)
+#define DO_CHNL_TYPE_DO_CHNL_TYPE_MASK (0x00000001)
+#define DO_CHNL_TYPE_DO_CHNL_TYPE_BIT (0x00000001)
+
+#define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_LSB (0)
+#define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_WIDTH (1)
+#define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_MASK (0x00000001)
+#define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_BIT (0x00000001)
+
+#define DO_TX_ENABLE_DO_TX_ENABLE_LSB (0)
+#define DO_TX_ENABLE_DO_TX_ENABLE_WIDTH (1)
+#define DO_TX_ENABLE_DO_TX_ENABLE_MASK (0x00000001)
+#define DO_TX_ENABLE_DO_TX_ENABLE_BIT (0x00000001)
+
+#define DO_TX_IQ_INV_DO_TX_IQ_INV_LSB (0)
+#define DO_TX_IQ_INV_DO_TX_IQ_INV_WIDTH (1)
+#define DO_TX_IQ_INV_DO_TX_IQ_INV_MASK (0x00000001)
+#define DO_TX_IQ_INV_DO_TX_IQ_INV_BIT (0x00000001)
+
+#define DO_TX_LONG_PN_MASK2_DO_TX_LONG_PN_MASK2_LSB (0)
+#define DO_TX_LONG_PN_MASK2_DO_TX_LONG_PN_MASK2_WIDTH (10)
+#define DO_TX_LONG_PN_MASK2_DO_TX_LONG_PN_MASK2_MASK (0x000003FF)
+
+#define DO_TX_LONG_PN_MASK1_DO_TX_LONG_PN_MASK1_LSB (0)
+#define DO_TX_LONG_PN_MASK1_DO_TX_LONG_PN_MASK1_WIDTH (32)
+#define DO_TX_LONG_PN_MASK1_DO_TX_LONG_PN_MASK1_MASK (0xFFFFFFFF)
+
+#define DO_LONGPN_LOAD_DO_LONGPN_LOAD_LSB (0)
+#define DO_LONGPN_LOAD_DO_LONGPN_LOAD_WIDTH (1)
+#define DO_LONGPN_LOAD_DO_LONGPN_LOAD_MASK (0x00000001)
+#define DO_LONGPN_LOAD_DO_LONGPN_LOAD_BIT (0x00000001)
+
+#define DO_DRC_BOOST_LEN_DO_DRC_BOOST_LEN_LSB (0)
+#define DO_DRC_BOOST_LEN_DO_DRC_BOOST_LEN_WIDTH (6)
+#define DO_DRC_BOOST_LEN_DO_DRC_BOOST_LEN_MASK (0x0000003F)
+
+#define DO_DSC_BOOST_LEN_DO_DSC_BOOST_LEN_LSB (0)
+#define DO_DSC_BOOST_LEN_DO_DSC_BOOST_LEN_WIDTH (7)
+#define DO_DSC_BOOST_LEN_DO_DSC_BOOST_LEN_MASK (0x0000007F)
+
+#define DO_AUXPLT_MINPYLD_DO_AUXPLT_MINPYLD_LSB (0)
+#define DO_AUXPLT_MINPYLD_DO_AUXPLT_MINPYLD_WIDTH (4)
+#define DO_AUXPLT_MINPYLD_DO_AUXPLT_MINPYLD_MASK (0x0000000F)
+
+#define DO_PLT_SCALE_DO_PLT_SCALE_LSB (0)
+#define DO_PLT_SCALE_DO_PLT_SCALE_WIDTH (9)
+#define DO_PLT_SCALE_DO_PLT_SCALE_MASK (0x000001FF)
+
+#define DO_AUXPLT_SCALE_ACK_DO_AUXPLT_SCALE_ACK_LSB (0)
+#define DO_AUXPLT_SCALE_ACK_DO_AUXPLT_SCALE_ACK_WIDTH (13)
+#define DO_AUXPLT_SCALE_ACK_DO_AUXPLT_SCALE_ACK_MASK (0x00001FFF)
+
+#define DO_AUXPLT_SCALE_NAK_DO_AUXPLT_SCALE_NAK_LSB (0)
+#define DO_AUXPLT_SCALE_NAK_DO_AUXPLT_SCALE_NAK_WIDTH (13)
+#define DO_AUXPLT_SCALE_NAK_DO_AUXPLT_SCALE_NAK_MASK (0x00001FFF)
+
+#define DO_RRI_SCALE_ACK_DO_RRI_SCALE_ACK_LSB (0)
+#define DO_RRI_SCALE_ACK_DO_RRI_SCALE_ACK_WIDTH (9)
+#define DO_RRI_SCALE_ACK_DO_RRI_SCALE_ACK_MASK (0x000001FF)
+
+#define DO_RRI_SCALE_NAK_DO_RRI_SCALE_NAK_LSB (0)
+#define DO_RRI_SCALE_NAK_DO_RRI_SCALE_NAK_WIDTH (9)
+#define DO_RRI_SCALE_NAK_DO_RRI_SCALE_NAK_MASK (0x000001FF)
+
+#define DO_DSC_SCALE_DO_DSC_SCALE_LSB (0)
+#define DO_DSC_SCALE_DO_DSC_SCALE_WIDTH (9)
+#define DO_DSC_SCALE_DO_DSC_SCALE_MASK (0x000001FF)
+
+#define DO_DSC_SCALE_BOOST_DO_DSC_SCALE_BOOST_LSB (0)
+#define DO_DSC_SCALE_BOOST_DO_DSC_SCALE_BOOST_WIDTH (9)
+#define DO_DSC_SCALE_BOOST_DO_DSC_SCALE_BOOST_MASK (0x000001FF)
+
+#define DO_DRC_SCALE_DO_DRC_SCALE_LSB (0)
+#define DO_DRC_SCALE_DO_DRC_SCALE_WIDTH (9)
+#define DO_DRC_SCALE_DO_DRC_SCALE_MASK (0x000001FF)
+
+#define DO_DRC_SCALE_BOOST_DO_DRC_SCALE_BOOST_LSB (0)
+#define DO_DRC_SCALE_BOOST_DO_DRC_SCALE_BOOST_WIDTH (9)
+#define DO_DRC_SCALE_BOOST_DO_DRC_SCALE_BOOST_MASK (0x000001FF)
+
+#define DO_BOOST_SELECT_DO_BOOST_SELECT_LSB (0)
+#define DO_BOOST_SELECT_DO_BOOST_SELECT_WIDTH (2)
+#define DO_BOOST_SELECT_DO_BOOST_SELECT_MASK (0x00000003)
+
+#define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_LSB (0)
+#define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_WIDTH (1)
+#define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_MASK (0x00000001)
+#define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_BIT (0x00000001)
+
+#define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_LSB (0)
+#define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_WIDTH (1)
+#define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_MASK (0x00000001)
+#define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_BIT (0x00000001)
+
+#define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_LSB (0)
+#define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_WIDTH (1)
+#define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_MASK (0x00000001)
+#define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_BIT (0x00000001)
+
+#define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_LSB (0)
+#define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_WIDTH (1)
+#define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_MASK (0x00000001)
+#define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_BIT (0x00000001)
+
+#define DO_ACK_SCALE_SUP_DO_ACK_SCALE_SUP_LSB (0)
+#define DO_ACK_SCALE_SUP_DO_ACK_SCALE_SUP_WIDTH (9)
+#define DO_ACK_SCALE_SUP_DO_ACK_SCALE_SUP_MASK (0x000001FF)
+
+#define DO_ACK_SCALE_MUP_DO_ACK_SCALE_MUP_LSB (0)
+#define DO_ACK_SCALE_MUP_DO_ACK_SCALE_MUP_WIDTH (9)
+#define DO_ACK_SCALE_MUP_DO_ACK_SCALE_MUP_MASK (0x000001FF)
+
+#define DO_DATA_SCALE0_ACK_DO_DATA_SCALE0_ACK_LSB (0)
+#define DO_DATA_SCALE0_ACK_DO_DATA_SCALE0_ACK_WIDTH (11)
+#define DO_DATA_SCALE0_ACK_DO_DATA_SCALE0_ACK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE1_ACK_DO_DATA_SCALE1_ACK_LSB (0)
+#define DO_DATA_SCALE1_ACK_DO_DATA_SCALE1_ACK_WIDTH (11)
+#define DO_DATA_SCALE1_ACK_DO_DATA_SCALE1_ACK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE2_ACK_DO_DATA_SCALE2_ACK_LSB (0)
+#define DO_DATA_SCALE2_ACK_DO_DATA_SCALE2_ACK_WIDTH (11)
+#define DO_DATA_SCALE2_ACK_DO_DATA_SCALE2_ACK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE3_ACK_DO_DATA_SCALE3_ACK_LSB (0)
+#define DO_DATA_SCALE3_ACK_DO_DATA_SCALE3_ACK_WIDTH (11)
+#define DO_DATA_SCALE3_ACK_DO_DATA_SCALE3_ACK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE0_NAK_DO_DATA_SCALE0_NAK_LSB (0)
+#define DO_DATA_SCALE0_NAK_DO_DATA_SCALE0_NAK_WIDTH (11)
+#define DO_DATA_SCALE0_NAK_DO_DATA_SCALE0_NAK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE1_NAK_DO_DATA_SCALE1_NAK_LSB (0)
+#define DO_DATA_SCALE1_NAK_DO_DATA_SCALE1_NAK_WIDTH (11)
+#define DO_DATA_SCALE1_NAK_DO_DATA_SCALE1_NAK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE2_NAK_DO_DATA_SCALE2_NAK_LSB (0)
+#define DO_DATA_SCALE2_NAK_DO_DATA_SCALE2_NAK_WIDTH (11)
+#define DO_DATA_SCALE2_NAK_DO_DATA_SCALE2_NAK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE3_NAK_DO_DATA_SCALE3_NAK_LSB (0)
+#define DO_DATA_SCALE3_NAK_DO_DATA_SCALE3_NAK_WIDTH (11)
+#define DO_DATA_SCALE3_NAK_DO_DATA_SCALE3_NAK_MASK (0x000007FF)
+
+#define DO_KS_TRIGGER_DO_KS_TRIGGER_LSB (0)
+#define DO_KS_TRIGGER_DO_KS_TRIGGER_WIDTH (1)
+#define DO_KS_TRIGGER_DO_KS_TRIGGER_MASK (0x00000001)
+#define DO_KS_TRIGGER_DO_KS_TRIGGER_BIT (0x00000001)
+
+#define DO_TRIGGER_SELECT_DO_TRIGGER_SELECT_LSB (0)
+#define DO_TRIGGER_SELECT_DO_TRIGGER_SELECT_WIDTH (3)
+#define DO_TRIGGER_SELECT_DO_TRIGGER_SELECT_MASK (0x00000007)
+
+#define DO_DRC_SELECT_0_DO_DRC_SELECT_0_LSB (0)
+#define DO_DRC_SELECT_0_DO_DRC_SELECT_0_WIDTH (2)
+#define DO_DRC_SELECT_0_DO_DRC_SELECT_0_MASK (0x00000003)
+
+#define DO_DRC_SELECT_1_DO_DRC_SELECT_1_LSB (0)
+#define DO_DRC_SELECT_1_DO_DRC_SELECT_1_WIDTH (2)
+#define DO_DRC_SELECT_1_DO_DRC_SELECT_1_MASK (0x00000003)
+
+#define DO_SW_RST_DO_SW_RST_LSB (0)
+#define DO_SW_RST_DO_SW_RST_WIDTH (1)
+#define DO_SW_RST_DO_SW_RST_MASK (0x00000001)
+#define DO_SW_RST_DO_SW_RST_BIT (0x00000001)
+
+#define DO_PREPLT_SCALE_DO_PREPLT_SCALE_LSB (0)
+#define DO_PREPLT_SCALE_DO_PREPLT_SCALE_WIDTH (9)
+#define DO_PREPLT_SCALE_DO_PREPLT_SCALE_MASK (0x000001FF)
+
+#define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_LSB (0)
+#define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_WIDTH (1)
+#define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_MASK (0x00000001)
+#define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_BIT (0x00000001)
+
+#define DO_ACK_DATA_DO_ACK_DATA_LSB (0)
+#define DO_ACK_DATA_DO_ACK_DATA_WIDTH (2)
+#define DO_ACK_DATA_DO_ACK_DATA_MASK (0x00000003)
+
+#define DO_DATA_SCALE_KS_ACK_DO_DATA_SCALE_KS_ACK_LSB (0)
+#define DO_DATA_SCALE_KS_ACK_DO_DATA_SCALE_KS_ACK_WIDTH (11)
+#define DO_DATA_SCALE_KS_ACK_DO_DATA_SCALE_KS_ACK_MASK (0x000007FF)
+
+#define DO_DATA_SCALE_KS_NAK_DO_DATA_SCALE_KS_NAK_LSB (0)
+#define DO_DATA_SCALE_KS_NAK_DO_DATA_SCALE_KS_NAK_WIDTH (11)
+#define DO_DATA_SCALE_KS_NAK_DO_DATA_SCALE_KS_NAK_MASK (0x000007FF)
+
+#define DO_TX_FREEZE_DO_TX_FREEZE_LSB (0)
+#define DO_TX_FREEZE_DO_TX_FREEZE_WIDTH (1)
+#define DO_TX_FREEZE_DO_TX_FREEZE_MASK (0x00000001)
+#define DO_TX_FREEZE_DO_TX_FREEZE_BIT (0x00000001)
+
+#define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_LSB (0)
+#define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_WIDTH (1)
+#define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_MASK (0x00000001)
+#define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_BIT (0x00000001)
+
+#define DO_TX_TEST_MODE_DO_TX_TEST_MODE_LSB (0)
+#define DO_TX_TEST_MODE_DO_TX_TEST_MODE_WIDTH (3)
+#define DO_TX_TEST_MODE_DO_TX_TEST_MODE_MASK (0x00000007)
+
+#define DO_TX_TEST0_DO_TX_TEST0_LSB (0)
+#define DO_TX_TEST0_DO_TX_TEST0_WIDTH (1)
+#define DO_TX_TEST0_DO_TX_TEST0_MASK (0x00000001)
+#define DO_TX_TEST0_DO_TX_TEST0_BIT (0x00000001)
+
+#define DO_TX_TEST1_DO_TX_TEST1_LSB (0)
+#define DO_TX_TEST1_DO_TX_TEST1_WIDTH (4)
+#define DO_TX_TEST1_DO_TX_TEST1_MASK (0x0000000F)
+
+#define DO_DRC_LENGTH_DO_DRC_LENGTH_LSB (0)
+#define DO_DRC_LENGTH_DO_DRC_LENGTH_WIDTH (2)
+#define DO_DRC_LENGTH_DO_DRC_LENGTH_MASK (0x00000003)
+
+#define DO_DRC_GATING_DO_DRC_GATING_LSB (0)
+#define DO_DRC_GATING_DO_DRC_GATING_WIDTH (1)
+#define DO_DRC_GATING_DO_DRC_GATING_MASK (0x00000001)
+#define DO_DRC_GATING_DO_DRC_GATING_BIT (0x00000001)
+
+#define STATE_Q_STATE_Q_LSB (0)
+#define STATE_Q_STATE_Q_WIDTH (5)
+#define STATE_Q_STATE_Q_MASK (0x0000001F)
+
+#define DO_TX_FSM_DO_TX_FSM_LSB (0)
+#define DO_TX_FSM_DO_TX_FSM_WIDTH (7)
+#define DO_TX_FSM_DO_TX_FSM_MASK (0x0000007F)
+
+#define DRC_DATA_I_DRC_DATA_I_LSB (0)
+#define DRC_DATA_I_DRC_DATA_I_WIDTH (4)
+#define DRC_DATA_I_DRC_DATA_I_MASK (0x0000000F)
+
+#define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_LSB (0)
+#define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_WIDTH (1)
+#define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_MASK (0x00000001)
+#define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_BIT (0x00000001)
+
+#define CDO_CHIP_COUNT_CDO_CHIP_COUNT_LSB (0)
+#define CDO_CHIP_COUNT_CDO_CHIP_COUNT_WIDTH (11)
+#define CDO_CHIP_COUNT_CDO_CHIP_COUNT_MASK (0x000007FF)
+
+#define CDO_TICK_COUNT_CDO_TICK_COUNT_LSB (0)
+#define CDO_TICK_COUNT_CDO_TICK_COUNT_WIDTH (6)
+#define CDO_TICK_COUNT_CDO_TICK_COUNT_MASK (0x0000003F)
+
+#define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_LSB (0)
+#define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_WIDTH (1)
+#define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_MASK (0x00000001)
+#define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_BIT (0x00000001)
+
+
+/*****************************************************************************
+* End of File
+*****************************************************************************/
+
+
+#endif //#ifndef _CPH_EVDO_TXCRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphevdotxtimerreg.h b/mcu/interface/l1/cl1/common/HW/cphevdotxtimerreg.h
new file mode 100644
index 0000000..21af45d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphevdotxtimerreg.h
@@ -0,0 +1,356 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_EVDO_TX_TIMER_H_
+#define _CPH_EVDO_TX_TIMER_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define DFE_W_TTR_DO_REG_BASE (0xA61B0000)
+#else
+#define DFE_W_TTR_DO_REG_BASE (0xA8190000)
+#endif
+#define DFE_W_TTR_end (DFE_W_TTR_DO_REG_BASE + 0x00F0)
+
+
+#define TX_TIMER_DO_SR_OFFSET0 ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0000))
+#define TX_TIMER_DO_SR_OFFSET1 ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0004))
+#define TX_TIMER_DO_RX_TX_LOG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0050))
+#define TX_TIMER_DO_TX_TIME_MON2 ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0064))
+#define TX_TIMER_DO_FRAME_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0070))
+#define TX_TIMER_DO_TXRXDELAY ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0074))
+#define TX_TIMER_DO_RA_DLY ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0078))
+#define TX_TIMER_DO_CDO_TTR_CRP_WIN_ON ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0080))
+#define TX_TIMER_DO_CDO_TTR_CRP_WIN_OFF ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0084))
+#if defined(__MD93__)||defined(__MD95__) /* The registers deleted in 97E1, it is moved to Txdfe-die, configed by RFD */
+#define TX_TIMER_DO_CDO_TTR_TXDFE_WIN_ON_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0088))
+#define TX_TIMER_DO_CDO_TTR_TXDFE_WIN_OFF_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x008C))
+#endif
+#define TX_TIMER_DO_CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0090))
+#define TX_TIMER_DO_CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0094))
+#if defined(__MD93__)||defined(__MD95__) /* The registers deleted in 97E1, it is moved to Txdfe-die, configed by RFD */
+#define TX_TIMER_DO_CDO_TTR_TXDAC_WIN_ON_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0098))
+#define TX_TIMER_DO_CDO_TTR_TXDAC_WIN_OFF_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x009C))
+#endif
+#define TX_TIMER_DO_CDO_TTR_TXBRP_STR ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x00C0))
+#define TX_TIMER_DO_CDO_TTR_TXCRP_STR ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x00C4))
+#define TX_TIMER_DO_CDO_TTR_KS_STR ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x00C8))
+#if (!defined(__MD93__))&&(!defined(__MD95__))
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0100))
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0110))
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0114))
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0118))
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x011C))
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0120))
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0124))
+#define TX_TIMER_TTR_WIN_DBG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x012c))
+#endif
+
+#define SR_Offset_SR_Offset_TRG_EN_LSB (20)
+#define SR_Offset_SR_Offset_TRG_EN_WIDTH (1)
+#define SR_Offset_SR_Offset_TRG_EN_MASK (0x00100000)
+#define SR_Offset_SR_Offset_TRG_EN_BIT (0x00100000)
+
+#define SR_Offset_SR_Offset_LSB (0)
+#define SR_Offset_SR_Offset_WIDTH (16)
+#define SR_Offset_SR_Offset_MASK (0x0000FFFF)
+
+#define Frame_Offset_Frame_Offset_LSB (0)
+#define Frame_Offset_Frame_Offset_WIDTH (20)
+#define Frame_Offset_Frame_Offset_MASK (0x000FFFFF)
+
+#define TxRxDelay_TxRxDelay_LSB (0)
+#define TxRxDelay_TxRxDelay_WIDTH (20)
+#define TxRxDelay_TxRxDelay_MASK (0x000FFFFF)
+
+#define RA_Dly_TXCRP_FIFO_WIN_OFF_SUBCHIP_OFFSET_LSB (0)
+#define RA_Dly_TXCRP_FIFO_WIN_OFF_SUBCHIP_OFFSET_WIDTH (3)
+#define RA_Dly_TXCRP_FIFO_WIN_OFF_SUBCHIP_OFFSET_MASK (0x00000007)
+
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_LSB (28)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_WIDTH (1)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_LSB (20)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_WIDTH (1)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_LSB (0)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_WIDTH (20)
+#define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_MASK (0x000FFFFF)
+
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_LSB (28)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_WIDTH (1)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_LSB (20)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_WIDTH (1)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_LSB (0)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_WIDTH (20)
+#define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_MASK (0x000FFFFF)
+
+#if defined(__MD93__)||defined(__MD95__)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_LSB (28)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_LSB (20)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_LSB (28)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_LSB (20)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_SYSTEM_TIME_WIDTH (12)
+#define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_SYSTEM_TIME_MASK (0x00000FFF)
+#endif
+
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_LSB (28)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_LSB (20)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_LSB (28)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_LSB (20)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#if defined(__MD93__)||defined(__MD95__)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_LSB (28)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_LSB (20)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_LSB (28)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_LSB (20)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_WIDTH (1)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_MASK (0x00100000)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_BIT (0x00100000)
+
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+#endif
+
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_LSB (28)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_LSB (22)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_WIDTH (1)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_MASK (0x00400000)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_BIT (0x00400000)
+
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_AUTO_TRIGGER_LSB (20)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_AUTO_TRIGGER_WIDTH (2)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_AUTO_TRIGGER_MASK (0x00300000)
+
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SYSTEM_TIME_WIDTH (20)
+#define CDO_TTR_TXBRP_STR_TXBRP_STR_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_LSB (28)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_WIDTH (1)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_LSB (22)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_WIDTH (1)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_MASK (0x00400000)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_BIT (0x00400000)
+
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_AUTO_TRIGGER_LSB (20)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_AUTO_TRIGGER_WIDTH (2)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_AUTO_TRIGGER_MASK (0x00300000)
+
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SYSTEM_TIME_WIDTH (12)
+#define CDO_TTR_TXCRP_STR_TXCRP_STR_SYSTEM_TIME_MASK (0x00000FFF)
+
+
+#define CDO_TTR_KS_STR_KS_STR_CMPR_ON_LSB (28)
+#define CDO_TTR_KS_STR_KS_STR_CMPR_ON_WIDTH (1)
+#define CDO_TTR_KS_STR_KS_STR_CMPR_ON_MASK (0x10000000)
+#define CDO_TTR_KS_STR_KS_STR_CMPR_ON_BIT (0x10000000)
+
+#define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_LSB (22)
+#define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_WIDTH (1)
+#define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_MASK (0x00400000)
+#define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_BIT (0x00400000)
+
+#define CDO_TTR_KS_STR_KS_STR_AUTO_TRIGGER_LSB (20)
+#define CDO_TTR_KS_STR_KS_STR_AUTO_TRIGGER_WIDTH (2)
+#define CDO_TTR_KS_STR_KS_STR_AUTO_TRIGGER_MASK (0x00300000)
+
+
+#define CDO_TTR_KS_STR_KS_STR_SYSTEM_TIME_LSB (0)
+#define CDO_TTR_KS_STR_KS_STR_SYSTEM_TIME_WIDTH (12)
+#define CDO_TTR_KS_STR_KS_STR_SYSTEM_TIME_MASK (0x00000FFF)
+
+#if (!defined(__MD93__))&&(!defined(__MD95__))
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_LSB (1)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_WIDTH (1)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_MASK (0x00000002)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_BIT (0x00000002)
+
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_LSB (0)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_WIDTH (1)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_MASK (0x00000001)
+#define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_BIT (0x00000001)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_LSB (1)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_MASK (0x00000002)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_BIT (0x00000002)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_MASK (0x00000001)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_BIT (0x00000001)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_WIDTH (32)
+#define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_MASK (0xFFFFFFFF)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_LSB (1)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_MASK (0x00000002)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_BIT (0x00000002)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_MASK (0x00000001)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_BIT (0x00000001)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_WIDTH (32)
+#define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_MASK (0xFFFFFFFF)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_LSB (28)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_MASK (0x10000000)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_BIT (0x10000000)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_LSB (27)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_MASK (0x08000000)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_BIT (0x08000000)
+
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_WIDTH (20)
+#define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_LSB (28)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_MASK (0x10000000)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_BIT (0x10000000)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_LSB (27)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_WIDTH (1)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_MASK (0x08000000)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_BIT (0x08000000)
+
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_LSB (0)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_WIDTH (20)
+#define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_LSB (0)
+#define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_WIDTH (1)
+#define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_MASK (0x00000001)
+#define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_BIT (0x00000001)
+#endif
+
+#endif //#ifndef _CPH_EVDO_TX_TIMER_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg.h b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg.h
new file mode 100644
index 0000000..618b0f1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphfesysmemconfigreg_93.h"
+#elif defined(__MD95__)
+#include "cphfesysmemconfigreg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphfesysmemconfigreg_97.h"
+#else
+#include "cphfesysmemconfigreg_97.h"/*#error "[ERROR] Invalid MD generation" modification for build error*/
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_93.h b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_93.h
new file mode 100644
index 0000000..27b290c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_93.h
@@ -0,0 +1,250 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_FESYS_MEM_CONFIG_REG_H_
+#define _CPH_FESYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MEM_CONFIG_FESYS_REG_BASE (0xA6110000)
+
+#define MEM_CONFIG_FESYS_end (MEM_CONFIG_FESYS_REG_BASE + 0x410 + 1*4)
+
+
+
+#define SW_TYPE_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x000))
+#define SW_PWDN_C0_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x004))
+#define GROUP_PWDN_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x008))
+#define WAITING_FLAG_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x00c))
+#define MBIST_MEM_ISOINTB_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x010))
+#define MBIST_MEM_PD_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x014))
+#define MBIST_PROT_STA_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x018))
+#define SRAMC_AO_IDLE_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x01c))
+#define SW_TYPE_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x100))
+#define SW_PWDN_C0_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x104))
+#define GROUP_PWDN_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x108))
+#define WAITING_FLAG_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x10c))
+#define SRAMC_AO_IDLE_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x110))
+#define SW_TYPE_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x200))
+#define SW_PWDN_C0_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x204))
+#define SW_PWDN_C1_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x208))
+#define SW_PWDN_C2_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x20c))
+#define SW_PWDN_C3_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x210))
+#define SW_PWDN_C4_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x214))
+#define GROUP_PWDN_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x218))
+#define WAITING_FLAG_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x21c))
+#define SRAMC_AO_IDLE_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x220))
+#define SW_TYPE_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x300))
+#define SW_PWDN_C0_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x304))
+#define SW_PWDN_C1_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x308))
+#define SW_PWDN_C2_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x30c))
+#define SW_PWDN_C3_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x310))
+#define SW_PWDN_C4_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x314))
+#define GROUP_PWDN_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x318))
+#define WAITING_FLAG_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x31c))
+#define SRAMC_AO_IDLE_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x320))
+#define SW_TYPE_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x400))
+#define SW_PWDN_C0_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x404))
+#define GROUP_PWDN_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x408))
+#define WAITING_FLAG_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x40c))
+#define SRAMC_AO_IDLE_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x410))
+
+
+#define SW_TYPE_MDL1AO_M_LSB (0)
+#define SW_TYPE_MDL1AO_M_WIDTH (2)
+#define SW_TYPE_MDL1AO_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_MDL1AO_M_LSB (0)
+#define SW_PWDN_C0_MDL1AO_M_WIDTH (2)
+#define SW_PWDN_C0_MDL1AO_M_MASK (0x00000003)
+
+#define GROUP_PWDN_MDL1AO_M_LSB (0)
+#define GROUP_PWDN_MDL1AO_M_WIDTH (2)
+#define GROUP_PWDN_MDL1AO_M_MASK (0x00000003)
+
+#define WAITING_FLAG_MDL1AO_M_LSB (0)
+#define WAITING_FLAG_MDL1AO_M_WIDTH (1)
+#define WAITING_FLAG_MDL1AO_M_MASK (0x00000001)
+#define WAITING_FLAG_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_MEM_ISOINTB_MDL1AO_M_LSB (0)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_WIDTH (1)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_MASK (0x00000001)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_MEM_PD_MDL1AO_M_LSB (0)
+#define MBIST_MEM_PD_MDL1AO_M_WIDTH (1)
+#define MBIST_MEM_PD_MDL1AO_M_MASK (0x00000001)
+#define MBIST_MEM_PD_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_PROT_STA_MDL1AO_M_LSB (0)
+#define MBIST_PROT_STA_MDL1AO_M_WIDTH (1)
+#define MBIST_PROT_STA_MDL1AO_M_MASK (0x00000001)
+#define MBIST_PROT_STA_MDL1AO_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_MDL1AO_M_LSB (0)
+#define SRAMC_AO_IDLE_MDL1AO_M_WIDTH (1)
+#define SRAMC_AO_IDLE_MDL1AO_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_MDL1AO_M_BIT (0x00000001)
+
+#define SW_TYPE_MD2G_M_LSB (0)
+#define SW_TYPE_MD2G_M_WIDTH (2)
+#define SW_TYPE_MD2G_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_MD2G_M_LSB (0)
+#define SW_PWDN_C0_MD2G_M_WIDTH (2)
+#define SW_PWDN_C0_MD2G_M_MASK (0x00000003)
+
+#define GROUP_PWDN_MD2G_M_LSB (0)
+#define GROUP_PWDN_MD2G_M_WIDTH (2)
+#define GROUP_PWDN_MD2G_M_MASK (0x00000003)
+
+#define WAITING_FLAG_MD2G_M_LSB (0)
+#define WAITING_FLAG_MD2G_M_WIDTH (1)
+#define WAITING_FLAG_MD2G_M_MASK (0x00000001)
+#define WAITING_FLAG_MD2G_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_MD2G_M_LSB (0)
+#define SRAMC_AO_IDLE_MD2G_M_WIDTH (1)
+#define SRAMC_AO_IDLE_MD2G_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_MD2G_M_BIT (0x00000001)
+
+#define SW_TYPE_TXSYS_M_LSB (0)
+#define SW_TYPE_TXSYS_M_WIDTH (9)
+#define SW_TYPE_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C0_TXSYS_M_LSB (0)
+#define SW_PWDN_C0_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C0_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C1_TXSYS_M_LSB (0)
+#define SW_PWDN_C1_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C1_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C2_TXSYS_M_LSB (0)
+#define SW_PWDN_C2_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C2_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C3_TXSYS_M_LSB (0)
+#define SW_PWDN_C3_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C3_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C4_TXSYS_M_LSB (0)
+#define SW_PWDN_C4_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C4_TXSYS_M_MASK (0x000001FF)
+
+#define GROUP_PWDN_TXSYS_M_LSB (0)
+#define GROUP_PWDN_TXSYS_M_WIDTH (9)
+#define GROUP_PWDN_TXSYS_M_MASK (0x000001FF)
+
+#define WAITING_FLAG_TXSYS_M_LSB (0)
+#define WAITING_FLAG_TXSYS_M_WIDTH (5)
+#define WAITING_FLAG_TXSYS_M_MASK (0x0000001F)
+
+#define SRAMC_AO_IDLE_TXSYS_M_LSB (0)
+#define SRAMC_AO_IDLE_TXSYS_M_WIDTH (1)
+#define SRAMC_AO_IDLE_TXSYS_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_TXSYS_M_BIT (0x00000001)
+
+#define SW_TYPE_CSSYS_M_LSB (0)
+#define SW_TYPE_CSSYS_M_WIDTH (6)
+#define SW_TYPE_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C0_CSSYS_M_LSB (0)
+#define SW_PWDN_C0_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C0_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C1_CSSYS_M_LSB (0)
+#define SW_PWDN_C1_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C1_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C2_CSSYS_M_LSB (0)
+#define SW_PWDN_C2_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C2_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C3_CSSYS_M_LSB (0)
+#define SW_PWDN_C3_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C3_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C4_CSSYS_M_LSB (0)
+#define SW_PWDN_C4_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C4_CSSYS_M_MASK (0x0000003F)
+
+#define GROUP_PWDN_CSSYS_M_LSB (0)
+#define GROUP_PWDN_CSSYS_M_WIDTH (6)
+#define GROUP_PWDN_CSSYS_M_MASK (0x0000003F)
+
+#define WAITING_FLAG_CSSYS_M_LSB (0)
+#define WAITING_FLAG_CSSYS_M_WIDTH (5)
+#define WAITING_FLAG_CSSYS_M_MASK (0x0000001F)
+
+#define SRAMC_AO_IDLE_CSSYS_M_LSB (0)
+#define SRAMC_AO_IDLE_CSSYS_M_WIDTH (1)
+#define SRAMC_AO_IDLE_CSSYS_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_CSSYS_M_BIT (0x00000001)
+
+#define SW_TYPE_RXDFE_M_LSB (0)
+#define SW_TYPE_RXDFE_M_WIDTH (2)
+#define SW_TYPE_RXDFE_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_RXDFE_M_LSB (0)
+#define SW_PWDN_C0_RXDFE_M_WIDTH (2)
+#define SW_PWDN_C0_RXDFE_M_MASK (0x00000003)
+
+#define GROUP_PWDN_RXDFE_M_LSB (0)
+#define GROUP_PWDN_RXDFE_M_WIDTH (2)
+#define GROUP_PWDN_RXDFE_M_MASK (0x00000003)
+
+#define WAITING_FLAG_RXDFE_M_LSB (0)
+#define WAITING_FLAG_RXDFE_M_WIDTH (1)
+#define WAITING_FLAG_RXDFE_M_MASK (0x00000001)
+#define WAITING_FLAG_RXDFE_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_RXDFE_M_LSB (0)
+#define SRAMC_AO_IDLE_RXDFE_M_WIDTH (1)
+#define SRAMC_AO_IDLE_RXDFE_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_RXDFE_M_BIT (0x00000001)
+
+
+#endif /*_CPH_FESYS_MEM_CONFIG_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_95.h b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_95.h
new file mode 100644
index 0000000..27b290c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_95.h
@@ -0,0 +1,250 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_FESYS_MEM_CONFIG_REG_H_
+#define _CPH_FESYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MEM_CONFIG_FESYS_REG_BASE (0xA6110000)
+
+#define MEM_CONFIG_FESYS_end (MEM_CONFIG_FESYS_REG_BASE + 0x410 + 1*4)
+
+
+
+#define SW_TYPE_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x000))
+#define SW_PWDN_C0_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x004))
+#define GROUP_PWDN_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x008))
+#define WAITING_FLAG_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x00c))
+#define MBIST_MEM_ISOINTB_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x010))
+#define MBIST_MEM_PD_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x014))
+#define MBIST_PROT_STA_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x018))
+#define SRAMC_AO_IDLE_MDL1AO ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x01c))
+#define SW_TYPE_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x100))
+#define SW_PWDN_C0_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x104))
+#define GROUP_PWDN_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x108))
+#define WAITING_FLAG_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x10c))
+#define SRAMC_AO_IDLE_MD2G ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x110))
+#define SW_TYPE_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x200))
+#define SW_PWDN_C0_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x204))
+#define SW_PWDN_C1_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x208))
+#define SW_PWDN_C2_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x20c))
+#define SW_PWDN_C3_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x210))
+#define SW_PWDN_C4_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x214))
+#define GROUP_PWDN_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x218))
+#define WAITING_FLAG_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x21c))
+#define SRAMC_AO_IDLE_TXSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x220))
+#define SW_TYPE_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x300))
+#define SW_PWDN_C0_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x304))
+#define SW_PWDN_C1_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x308))
+#define SW_PWDN_C2_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x30c))
+#define SW_PWDN_C3_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x310))
+#define SW_PWDN_C4_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x314))
+#define GROUP_PWDN_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x318))
+#define WAITING_FLAG_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x31c))
+#define SRAMC_AO_IDLE_CSSYS ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x320))
+#define SW_TYPE_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x400))
+#define SW_PWDN_C0_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x404))
+#define GROUP_PWDN_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x408))
+#define WAITING_FLAG_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x40c))
+#define SRAMC_AO_IDLE_RXDFE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x410))
+
+
+#define SW_TYPE_MDL1AO_M_LSB (0)
+#define SW_TYPE_MDL1AO_M_WIDTH (2)
+#define SW_TYPE_MDL1AO_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_MDL1AO_M_LSB (0)
+#define SW_PWDN_C0_MDL1AO_M_WIDTH (2)
+#define SW_PWDN_C0_MDL1AO_M_MASK (0x00000003)
+
+#define GROUP_PWDN_MDL1AO_M_LSB (0)
+#define GROUP_PWDN_MDL1AO_M_WIDTH (2)
+#define GROUP_PWDN_MDL1AO_M_MASK (0x00000003)
+
+#define WAITING_FLAG_MDL1AO_M_LSB (0)
+#define WAITING_FLAG_MDL1AO_M_WIDTH (1)
+#define WAITING_FLAG_MDL1AO_M_MASK (0x00000001)
+#define WAITING_FLAG_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_MEM_ISOINTB_MDL1AO_M_LSB (0)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_WIDTH (1)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_MASK (0x00000001)
+#define MBIST_MEM_ISOINTB_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_MEM_PD_MDL1AO_M_LSB (0)
+#define MBIST_MEM_PD_MDL1AO_M_WIDTH (1)
+#define MBIST_MEM_PD_MDL1AO_M_MASK (0x00000001)
+#define MBIST_MEM_PD_MDL1AO_M_BIT (0x00000001)
+
+#define MBIST_PROT_STA_MDL1AO_M_LSB (0)
+#define MBIST_PROT_STA_MDL1AO_M_WIDTH (1)
+#define MBIST_PROT_STA_MDL1AO_M_MASK (0x00000001)
+#define MBIST_PROT_STA_MDL1AO_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_MDL1AO_M_LSB (0)
+#define SRAMC_AO_IDLE_MDL1AO_M_WIDTH (1)
+#define SRAMC_AO_IDLE_MDL1AO_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_MDL1AO_M_BIT (0x00000001)
+
+#define SW_TYPE_MD2G_M_LSB (0)
+#define SW_TYPE_MD2G_M_WIDTH (2)
+#define SW_TYPE_MD2G_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_MD2G_M_LSB (0)
+#define SW_PWDN_C0_MD2G_M_WIDTH (2)
+#define SW_PWDN_C0_MD2G_M_MASK (0x00000003)
+
+#define GROUP_PWDN_MD2G_M_LSB (0)
+#define GROUP_PWDN_MD2G_M_WIDTH (2)
+#define GROUP_PWDN_MD2G_M_MASK (0x00000003)
+
+#define WAITING_FLAG_MD2G_M_LSB (0)
+#define WAITING_FLAG_MD2G_M_WIDTH (1)
+#define WAITING_FLAG_MD2G_M_MASK (0x00000001)
+#define WAITING_FLAG_MD2G_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_MD2G_M_LSB (0)
+#define SRAMC_AO_IDLE_MD2G_M_WIDTH (1)
+#define SRAMC_AO_IDLE_MD2G_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_MD2G_M_BIT (0x00000001)
+
+#define SW_TYPE_TXSYS_M_LSB (0)
+#define SW_TYPE_TXSYS_M_WIDTH (9)
+#define SW_TYPE_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C0_TXSYS_M_LSB (0)
+#define SW_PWDN_C0_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C0_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C1_TXSYS_M_LSB (0)
+#define SW_PWDN_C1_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C1_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C2_TXSYS_M_LSB (0)
+#define SW_PWDN_C2_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C2_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C3_TXSYS_M_LSB (0)
+#define SW_PWDN_C3_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C3_TXSYS_M_MASK (0x000001FF)
+
+#define SW_PWDN_C4_TXSYS_M_LSB (0)
+#define SW_PWDN_C4_TXSYS_M_WIDTH (9)
+#define SW_PWDN_C4_TXSYS_M_MASK (0x000001FF)
+
+#define GROUP_PWDN_TXSYS_M_LSB (0)
+#define GROUP_PWDN_TXSYS_M_WIDTH (9)
+#define GROUP_PWDN_TXSYS_M_MASK (0x000001FF)
+
+#define WAITING_FLAG_TXSYS_M_LSB (0)
+#define WAITING_FLAG_TXSYS_M_WIDTH (5)
+#define WAITING_FLAG_TXSYS_M_MASK (0x0000001F)
+
+#define SRAMC_AO_IDLE_TXSYS_M_LSB (0)
+#define SRAMC_AO_IDLE_TXSYS_M_WIDTH (1)
+#define SRAMC_AO_IDLE_TXSYS_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_TXSYS_M_BIT (0x00000001)
+
+#define SW_TYPE_CSSYS_M_LSB (0)
+#define SW_TYPE_CSSYS_M_WIDTH (6)
+#define SW_TYPE_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C0_CSSYS_M_LSB (0)
+#define SW_PWDN_C0_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C0_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C1_CSSYS_M_LSB (0)
+#define SW_PWDN_C1_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C1_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C2_CSSYS_M_LSB (0)
+#define SW_PWDN_C2_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C2_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C3_CSSYS_M_LSB (0)
+#define SW_PWDN_C3_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C3_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C4_CSSYS_M_LSB (0)
+#define SW_PWDN_C4_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C4_CSSYS_M_MASK (0x0000003F)
+
+#define GROUP_PWDN_CSSYS_M_LSB (0)
+#define GROUP_PWDN_CSSYS_M_WIDTH (6)
+#define GROUP_PWDN_CSSYS_M_MASK (0x0000003F)
+
+#define WAITING_FLAG_CSSYS_M_LSB (0)
+#define WAITING_FLAG_CSSYS_M_WIDTH (5)
+#define WAITING_FLAG_CSSYS_M_MASK (0x0000001F)
+
+#define SRAMC_AO_IDLE_CSSYS_M_LSB (0)
+#define SRAMC_AO_IDLE_CSSYS_M_WIDTH (1)
+#define SRAMC_AO_IDLE_CSSYS_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_CSSYS_M_BIT (0x00000001)
+
+#define SW_TYPE_RXDFE_M_LSB (0)
+#define SW_TYPE_RXDFE_M_WIDTH (2)
+#define SW_TYPE_RXDFE_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_RXDFE_M_LSB (0)
+#define SW_PWDN_C0_RXDFE_M_WIDTH (2)
+#define SW_PWDN_C0_RXDFE_M_MASK (0x00000003)
+
+#define GROUP_PWDN_RXDFE_M_LSB (0)
+#define GROUP_PWDN_RXDFE_M_WIDTH (2)
+#define GROUP_PWDN_RXDFE_M_MASK (0x00000003)
+
+#define WAITING_FLAG_RXDFE_M_LSB (0)
+#define WAITING_FLAG_RXDFE_M_WIDTH (1)
+#define WAITING_FLAG_RXDFE_M_MASK (0x00000001)
+#define WAITING_FLAG_RXDFE_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_RXDFE_M_LSB (0)
+#define SRAMC_AO_IDLE_RXDFE_M_WIDTH (1)
+#define SRAMC_AO_IDLE_RXDFE_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_RXDFE_M_BIT (0x00000001)
+
+
+#endif /*_CPH_FESYS_MEM_CONFIG_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_97.h b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_97.h
new file mode 100644
index 0000000..a36b2dd
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphfesysmemconfigreg_97.h
@@ -0,0 +1,140 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_FESYS_MEM_CONFIG_REG_H_
+#define _CPH_FESYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MEM_CONFIG_FESYS_REG_BASE (0xA8100000)
+
+#define MEM_CONFIG_FESYS_end (MEM_CONFIG_FESYS_REG_BASE + 0x410 + 1*4)
+
+
+
+#define CSSYS_SW_TYPE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x000))
+#define CSSYS_WAIT_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x004))
+#define CSSYS_GROUP_PWDN_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x008))
+#define CSSYS_SRAM_CTRL_AO_IDLE_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x00c))
+#define CSSYS_SW_PWDN_0_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x010))
+#define CSSYS_SW_PWDN_1_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x014))
+#define CSSYS_SW_PWDN_2_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x018))
+#define CSSYS_SW_PWDN_3_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x01c))
+#define CSSYS_SW_PWDN_4_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x020))
+#define DFESYS_PWR_WRAP_SW_TYPE ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x024))
+#define DFESYS_PWR_WRAP_WAIT_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x028))
+#define DFESYS_PWR_WRAP_GROUP_PWDN_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x02C))
+#define DFESYS_PWR_WRAP_SRAM_CTRL_AO_IDLE_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x030))
+#define DFESYS_PWR_WRAP_SW_PWDN_0_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x034))
+#define DFESYS_PWR_WRAP_SW_PWDN_1_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x038))
+#define DFESYS_PWR_WRAP_SW_PWDN_2_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x03C))
+#define DFESYS_PWR_WRAP_SW_PWDN_3_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x040))
+#define DFESYS_PWR_WRAP_SW_PWDN_4_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x044))
+#define DFESYS_PWR_WRAP_SW_PWDN_5_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x048))
+#define DFESYS_PWR_WRAP_SW_PWDN_6_ADDR ((APBADDR32)(MEM_CONFIG_FESYS_REG_BASE + 0x04C))
+
+#define CSSYS_WAIT_ADDR_C3 (0x00000008)
+#define CSSYS_WAIT_ADDR_C4 (0x00000010)
+
+#define SW_TYPE_CSSYS_M_LSB (0)
+#define SW_TYPE_CSSYS_M_WIDTH (6)
+#define SW_TYPE_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C0_CSSYS_M_LSB (0)
+#define SW_PWDN_C0_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C0_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C1_CSSYS_M_LSB (0)
+#define SW_PWDN_C1_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C1_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C2_CSSYS_M_LSB (0)
+#define SW_PWDN_C2_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C2_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C3_CSSYS_M_LSB (0)
+#define SW_PWDN_C3_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C3_CSSYS_M_MASK (0x0000003F)
+
+#define SW_PWDN_C4_CSSYS_M_LSB (0)
+#define SW_PWDN_C4_CSSYS_M_WIDTH (6)
+#define SW_PWDN_C4_CSSYS_M_MASK (0x0000003F)
+
+#define GROUP_PWDN_CSSYS_M_LSB (0)
+#define GROUP_PWDN_CSSYS_M_WIDTH (6)
+#define GROUP_PWDN_CSSYS_M_MASK (0x0000003F)
+
+#define WAITING_FLAG_CSSYS_M_LSB (0)
+#define WAITING_FLAG_CSSYS_M_WIDTH (5)
+#define WAITING_FLAG_CSSYS_M_MASK (0x0000001F)
+
+#define SRAMC_AO_IDLE_CSSYS_M_LSB (0)
+#define SRAMC_AO_IDLE_CSSYS_M_WIDTH (1)
+#define SRAMC_AO_IDLE_CSSYS_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_CSSYS_M_BIT (0x00000001)
+
+#define SW_TYPE_RXDFE_M_LSB (0)
+#define SW_TYPE_RXDFE_M_WIDTH (2)
+#define SW_TYPE_RXDFE_M_MASK (0x00000003)
+
+#define SW_PWDN_C0_RXDFE_M_LSB (0)
+#define SW_PWDN_C0_RXDFE_M_WIDTH (2)
+#define SW_PWDN_C0_RXDFE_M_MASK (0x00000003)
+
+#define GROUP_PWDN_RXDFE_M_LSB (0)
+#define GROUP_PWDN_RXDFE_M_WIDTH (2)
+#define GROUP_PWDN_RXDFE_M_MASK (0x00000003)
+
+#define WAITING_FLAG_RXDFE_M_LSB (0)
+#define WAITING_FLAG_RXDFE_M_WIDTH (1)
+#define WAITING_FLAG_RXDFE_M_MASK (0x00000001)
+#define WAITING_FLAG_RXDFE_M_BIT (0x00000001)
+
+#define SRAMC_AO_IDLE_RXDFE_M_LSB (0)
+#define SRAMC_AO_IDLE_RXDFE_M_WIDTH (1)
+#define SRAMC_AO_IDLE_RXDFE_M_MASK (0x00000001)
+#define SRAMC_AO_IDLE_RXDFE_M_BIT (0x00000001)
+
+
+#endif /*_CPH_FESYS_MEM_CONFIG_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphid.h b/mcu/interface/l1/cl1/common/HW/cphid.h
new file mode 100644
index 0000000..3cd6e1d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphid.h
@@ -0,0 +1,72 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_ID_H_
+#define _CPH_ID_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define ID_CW_REG_BASE (0xAC000000)/*TBD*/
+
+
+#define ID_CW_end (ID_CW_REG_BASE + 0x010C + 1*4)
+
+#define PEIT_CW_REG_BASE (0xAC351000)/*TBD*/
+#define CMD_RAM_CW_REG_BASE (0xAC002000)/*TBD*/
+
+
+#define ID_CON ((APBADDR32)(ID_CW_REG_BASE + 0x0000))
+#define ID_CFG_0 ((APBADDR32)(ID_CW_REG_BASE + 0x0004))
+#define ID_CFG_1 ((APBADDR32)(ID_CW_REG_BASE + 0x0008))
+#define ID_CFG_C2K ((APBADDR32)(ID_CW_REG_BASE + 0x000C))
+#define ID_LOAD_POS_FAST ((APBADDR32)(ID_CW_REG_BASE + 0x0010))
+#define ID_LOAD_POS_SLOW ((APBADDR32)(ID_CW_REG_BASE + 0x0014))
+#define ID_LOAD_POS_FAST_DO ((APBADDR32)(ID_CW_REG_BASE + 0x0018))
+#define ID_LOAD_POS_SLOW_DO ((APBADDR32)(ID_CW_REG_BASE + 0x001C))
+#define ID_DESP_BATCH ((APBADDR32)(ID_CW_REG_BASE + 0x0020))
+#define ID_DBG_0 ((APBADDR32)(ID_CW_REG_BASE + 0x0100))
+#define ID_DBG_1 ((APBADDR32)(ID_CW_REG_BASE + 0x0104))
+#define ID_DBG_2 ((APBADDR32)(ID_CW_REG_BASE + 0x0108))
+
+#endif //#ifndef _CPH_D2BIF_H_
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg.h b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg.h
new file mode 100644
index 0000000..1823c48
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphmdrxsysmemconfigreg_93.h"
+#elif defined(__MD95__)
+#include "cphmdrxsysmemconfigreg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphmdrxsysmemconfigreg_97.h"
+#else
+#include "cphmdrxsysmemconfigreg_97.h"/*#error "[ERROR] Invalid MD generation" modification for build error*/
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_93.h b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_93.h
new file mode 100644
index 0000000..fe7f56d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_93.h
@@ -0,0 +1,358 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+#define _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MDRXAO_MEM_CONFIG_REG_BASE (0xA6120000)
+
+#define MDRXAO_MEM_CONFIG_end (MDRXAO_MEM_CONFIG_REG_BASE + 0xd4 + 1*4)
+
+
+
+#define DMC_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x0))
+#define SCQ_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4))
+#define BRP_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x8))
+#define BIGRAM_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc))
+#define RAKE_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x10))
+#define DMC_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x14))
+#define SCQ_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x18))
+#define SCQ_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x1c))
+#define BRP_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x20))
+#define BRP_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x24))
+#define BRP_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x28))
+#define BRP_SW_PWDN_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x2c))
+#define BRP_SW_PWDN_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x30))
+#define BIGRAM_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x34))
+#define BIGRAM_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x38))
+#define BIGRAM_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x3c))
+#define BIGRAM_SW_PWDN_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x40))
+#define BIGRAM_SW_PWDN_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x44))
+#define RAKE_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x48))
+#define RAKE_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4c))
+#define RAKE_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x50))
+#define DMC_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x54))
+#define SCQ_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x58))
+#define BRP_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x5c))
+#define BIGRAM_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x60))
+#define RAKE_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x64))
+#define DMC_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x68))
+#define BRAM_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x74))
+#define BRAM_WAIT_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x78))
+#define BRAM_WAIT_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x7c))
+#define BRAM_WAIT_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x80))
+#define BRAM_WAIT_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x84))
+#define RAKE_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x9c))
+#define RAKE_WAIT_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa0))
+#define RAKE_WAIT_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa4))
+#define SRAM_CTRL_AO_IDLE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa8))
+#define RAKE_PM_CIPHER_EN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xb0))
+#define RAKE_PM_CIPHER_LOCK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xb4))
+#define SCQ_SPM_CIPHER_EN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc0))
+#define SCQ_SPM_CIPHER_LOCK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc4))
+#define CK_IDLE_MASK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xd0))
+#define CK_IDLE_DBG_MASK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xd4))
+
+
+#define DMC_SW_TYPE_GP_TYPE_LSB (0)
+#define DMC_SW_TYPE_GP_TYPE_WIDTH (1)
+#define DMC_SW_TYPE_GP_TYPE_MASK (0x00000001)
+#define DMC_SW_TYPE_GP_TYPE_BIT (0x00000001)
+
+#define SCQ_SW_TYPE_GP_TYPE_LSB (0)
+#define SCQ_SW_TYPE_GP_TYPE_WIDTH (11)
+#define SCQ_SW_TYPE_GP_TYPE_MASK (0x000007FF)
+
+#define BRP_SW_TYPE_GP_TYPE_LSB (0)
+#define BRP_SW_TYPE_GP_TYPE_WIDTH (6)
+#define BRP_SW_TYPE_GP_TYPE_MASK (0x0000003F)
+
+#define BIGRAM_SW_TYPE_GP_TYPE_LSB (0)
+#define BIGRAM_SW_TYPE_GP_TYPE_WIDTH (3)
+#define BIGRAM_SW_TYPE_GP_TYPE_MASK (0x00000007)
+
+#define RAKE_SW_TYPE_GP_TYPE_LSB (0)
+#define RAKE_SW_TYPE_GP_TYPE_WIDTH (8)
+#define RAKE_SW_TYPE_GP_TYPE_MASK (0x000000FF)
+
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_WIDTH (1)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_MASK (0x00000001)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_BIT (0x00000001)
+
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_WIDTH (11)
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_MASK (0x000007FF)
+
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_WIDTH (11)
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_MASK (0x000007FF)
+
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_WIDTH (6)
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_WIDTH (6)
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_WIDTH (6)
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_LSB (0)
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_WIDTH (6)
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_LSB (0)
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_WIDTH (6)
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_MASK (0x0000003F)
+
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_WIDTH (3)
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_WIDTH (3)
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_WIDTH (3)
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_LSB (0)
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_WIDTH (3)
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_LSB (0)
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_WIDTH (3)
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_MASK (0x00000007)
+
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_WIDTH (8)
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_MASK (0x000000FF)
+
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_WIDTH (8)
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_MASK (0x000000FF)
+
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_WIDTH (8)
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_MASK (0x000000FF)
+
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_WIDTH (1)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_MASK (0x00000001)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_BIT (0x00000001)
+
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_WIDTH (11)
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_MASK (0x000007FF)
+
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_WIDTH (6)
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_MASK (0x0000003F)
+
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_WIDTH (3)
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_MASK (0x00000007)
+
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_WIDTH (8)
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_MASK (0x000000FF)
+
+#define DMC_WAIT_C0_WAIT_C0_LSB (0)
+#define DMC_WAIT_C0_WAIT_C0_WIDTH (1)
+#define DMC_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define DMC_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define BRAM_WAIT_C0_WAIT_C0_LSB (0)
+#define BRAM_WAIT_C0_WAIT_C0_WIDTH (1)
+#define BRAM_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define BRAM_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define BRAM_WAIT_C1_WAIT_C1_LSB (0)
+#define BRAM_WAIT_C1_WAIT_C1_WIDTH (1)
+#define BRAM_WAIT_C1_WAIT_C1_MASK (0x00000001)
+#define BRAM_WAIT_C1_WAIT_C1_BIT (0x00000001)
+
+#define BRAM_WAIT_C2_WAIT_C2_LSB (0)
+#define BRAM_WAIT_C2_WAIT_C2_WIDTH (1)
+#define BRAM_WAIT_C2_WAIT_C2_MASK (0x00000001)
+#define BRAM_WAIT_C2_WAIT_C2_BIT (0x00000001)
+
+#define BRAM_WAIT_C3_WAIT_C3_LSB (0)
+#define BRAM_WAIT_C3_WAIT_C3_WIDTH (1)
+#define BRAM_WAIT_C3_WAIT_C3_MASK (0x00000001)
+#define BRAM_WAIT_C3_WAIT_C3_BIT (0x00000001)
+
+#define BRAM_WAIT_C4_WAIT_C4_LSB (0)
+#define BRAM_WAIT_C4_WAIT_C4_WIDTH (1)
+#define BRAM_WAIT_C4_WAIT_C4_MASK (0x00000001)
+#define BRAM_WAIT_C4_WAIT_C4_BIT (0x00000001)
+
+#define RAKE_WAIT_C0_WAIT_C0_LSB (0)
+#define RAKE_WAIT_C0_WAIT_C0_WIDTH (1)
+#define RAKE_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define RAKE_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define RAKE_WAIT_C1_WAIT_C1_LSB (0)
+#define RAKE_WAIT_C1_WAIT_C1_WIDTH (1)
+#define RAKE_WAIT_C1_WAIT_C1_MASK (0x00000001)
+#define RAKE_WAIT_C1_WAIT_C1_BIT (0x00000001)
+
+#define RAKE_WAIT_C2_WAIT_C2_LSB (0)
+#define RAKE_WAIT_C2_WAIT_C2_WIDTH (1)
+#define RAKE_WAIT_C2_WAIT_C2_MASK (0x00000001)
+#define RAKE_WAIT_C2_WAIT_C2_BIT (0x00000001)
+
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_LSB (2)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_MASK (0x00000004)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_BIT (0x00000004)
+
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_LSB (1)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_MASK (0x00000002)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_BIT (0x00000002)
+
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_LSB (0)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_MASK (0x00000001)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_BIT (0x00000001)
+
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_LSB (0)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_WIDTH (1)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_MASK (0x00000001)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_BIT (0x00000001)
+
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_LSB (0)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_WIDTH (1)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_MASK (0x00000001)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_BIT (0x00000001)
+
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_LSB (0)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_WIDTH (1)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_MASK (0x00000001)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_BIT (0x00000001)
+
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_LSB (0)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_WIDTH (1)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_MASK (0x00000001)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_BIT (0x00000001)
+
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_LSB (6)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_MASK (0x00000040)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_BIT (0x00000040)
+
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_LSB (5)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_MASK (0x00000020)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_BIT (0x00000020)
+
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_LSB (4)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_MASK (0x00000010)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_BIT (0x00000010)
+
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_LSB (3)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_MASK (0x00000008)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_BIT (0x00000008)
+
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_LSB (2)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_MASK (0x00000004)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_BIT (0x00000004)
+
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_LSB (1)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_MASK (0x00000002)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_BIT (0x00000002)
+
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_LSB (0)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_MASK (0x00000001)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_BIT (0x00000001)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_LSB (6)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_MASK (0x00000040)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_BIT (0x00000040)
+
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_LSB (5)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_MASK (0x00000020)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_BIT (0x00000020)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_LSB (4)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_MASK (0x00000010)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_BIT (0x00000010)
+
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_LSB (3)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_MASK (0x00000008)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_BIT (0x00000008)
+
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_LSB (2)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_MASK (0x00000004)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_BIT (0x00000004)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_LSB (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_MASK (0x00000002)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_BIT (0x00000002)
+
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_LSB (0)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_MASK (0x00000001)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_BIT (0x00000001)
+
+
+#endif /*_CPH_MDRXSYS_MEM_CONFIG_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_95.h b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_95.h
new file mode 100644
index 0000000..fe7f56d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_95.h
@@ -0,0 +1,358 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+#define _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MDRXAO_MEM_CONFIG_REG_BASE (0xA6120000)
+
+#define MDRXAO_MEM_CONFIG_end (MDRXAO_MEM_CONFIG_REG_BASE + 0xd4 + 1*4)
+
+
+
+#define DMC_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x0))
+#define SCQ_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4))
+#define BRP_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x8))
+#define BIGRAM_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc))
+#define RAKE_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x10))
+#define DMC_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x14))
+#define SCQ_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x18))
+#define SCQ_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x1c))
+#define BRP_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x20))
+#define BRP_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x24))
+#define BRP_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x28))
+#define BRP_SW_PWDN_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x2c))
+#define BRP_SW_PWDN_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x30))
+#define BIGRAM_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x34))
+#define BIGRAM_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x38))
+#define BIGRAM_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x3c))
+#define BIGRAM_SW_PWDN_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x40))
+#define BIGRAM_SW_PWDN_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x44))
+#define RAKE_SW_PWDN_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x48))
+#define RAKE_SW_PWDN_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4c))
+#define RAKE_SW_PWDN_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x50))
+#define DMC_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x54))
+#define SCQ_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x58))
+#define BRP_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x5c))
+#define BIGRAM_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x60))
+#define RAKE_GROUP_PWDN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x64))
+#define DMC_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x68))
+#define BRAM_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x74))
+#define BRAM_WAIT_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x78))
+#define BRAM_WAIT_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x7c))
+#define BRAM_WAIT_C3 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x80))
+#define BRAM_WAIT_C4 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x84))
+#define RAKE_WAIT_C0 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x9c))
+#define RAKE_WAIT_C1 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa0))
+#define RAKE_WAIT_C2 ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa4))
+#define SRAM_CTRL_AO_IDLE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xa8))
+#define RAKE_PM_CIPHER_EN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xb0))
+#define RAKE_PM_CIPHER_LOCK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xb4))
+#define SCQ_SPM_CIPHER_EN ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc0))
+#define SCQ_SPM_CIPHER_LOCK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc4))
+#define CK_IDLE_MASK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xd0))
+#define CK_IDLE_DBG_MASK ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xd4))
+
+
+#define DMC_SW_TYPE_GP_TYPE_LSB (0)
+#define DMC_SW_TYPE_GP_TYPE_WIDTH (1)
+#define DMC_SW_TYPE_GP_TYPE_MASK (0x00000001)
+#define DMC_SW_TYPE_GP_TYPE_BIT (0x00000001)
+
+#define SCQ_SW_TYPE_GP_TYPE_LSB (0)
+#define SCQ_SW_TYPE_GP_TYPE_WIDTH (11)
+#define SCQ_SW_TYPE_GP_TYPE_MASK (0x000007FF)
+
+#define BRP_SW_TYPE_GP_TYPE_LSB (0)
+#define BRP_SW_TYPE_GP_TYPE_WIDTH (6)
+#define BRP_SW_TYPE_GP_TYPE_MASK (0x0000003F)
+
+#define BIGRAM_SW_TYPE_GP_TYPE_LSB (0)
+#define BIGRAM_SW_TYPE_GP_TYPE_WIDTH (3)
+#define BIGRAM_SW_TYPE_GP_TYPE_MASK (0x00000007)
+
+#define RAKE_SW_TYPE_GP_TYPE_LSB (0)
+#define RAKE_SW_TYPE_GP_TYPE_WIDTH (8)
+#define RAKE_SW_TYPE_GP_TYPE_MASK (0x000000FF)
+
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_WIDTH (1)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_MASK (0x00000001)
+#define DMC_SW_PWDN_C0_GP_PWDN_C0_BIT (0x00000001)
+
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_WIDTH (11)
+#define SCQ_SW_PWDN_C0_GP_PWDN_C0_MASK (0x000007FF)
+
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_WIDTH (11)
+#define SCQ_SW_PWDN_C1_GP_PWDN_C1_MASK (0x000007FF)
+
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_WIDTH (6)
+#define BRP_SW_PWDN_C0_GP_PWDN_C0_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_WIDTH (6)
+#define BRP_SW_PWDN_C1_GP_PWDN_C1_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_WIDTH (6)
+#define BRP_SW_PWDN_C2_GP_PWDN_C2_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_LSB (0)
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_WIDTH (6)
+#define BRP_SW_PWDN_C3_GP_PWDN_C3_MASK (0x0000003F)
+
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_LSB (0)
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_WIDTH (6)
+#define BRP_SW_PWDN_C4_GP_PWDN_C4_MASK (0x0000003F)
+
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_WIDTH (3)
+#define BIGRAM_SW_PWDN_C0_GP_PWDN_C0_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_WIDTH (3)
+#define BIGRAM_SW_PWDN_C1_GP_PWDN_C1_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_WIDTH (3)
+#define BIGRAM_SW_PWDN_C2_GP_PWDN_C2_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_LSB (0)
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_WIDTH (3)
+#define BIGRAM_SW_PWDN_C3_GP_PWDN_C3_MASK (0x00000007)
+
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_LSB (0)
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_WIDTH (3)
+#define BIGRAM_SW_PWDN_C4_GP_PWDN_C4_MASK (0x00000007)
+
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_LSB (0)
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_WIDTH (8)
+#define RAKE_SW_PWDN_C0_GP_PWDN_C0_MASK (0x000000FF)
+
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_LSB (0)
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_WIDTH (8)
+#define RAKE_SW_PWDN_C1_GP_PWDN_C1_MASK (0x000000FF)
+
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_LSB (0)
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_WIDTH (8)
+#define RAKE_SW_PWDN_C2_GP_PWDN_C2_MASK (0x000000FF)
+
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_WIDTH (1)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_MASK (0x00000001)
+#define DMC_GROUP_PWDN_GP_PWR_STATUS_BIT (0x00000001)
+
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_WIDTH (11)
+#define SCQ_GROUP_PWDN_GP_PWR_STATUS_MASK (0x000007FF)
+
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_WIDTH (6)
+#define BRP_GROUP_PWDN_GP_PWR_STATUS_MASK (0x0000003F)
+
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_WIDTH (3)
+#define BIGRAM_GROUP_PWDN_GP_PWR_STATUS_MASK (0x00000007)
+
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_LSB (0)
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_WIDTH (8)
+#define RAKE_GROUP_PWDN_GP_PWR_STATUS_MASK (0x000000FF)
+
+#define DMC_WAIT_C0_WAIT_C0_LSB (0)
+#define DMC_WAIT_C0_WAIT_C0_WIDTH (1)
+#define DMC_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define DMC_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define BRAM_WAIT_C0_WAIT_C0_LSB (0)
+#define BRAM_WAIT_C0_WAIT_C0_WIDTH (1)
+#define BRAM_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define BRAM_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define BRAM_WAIT_C1_WAIT_C1_LSB (0)
+#define BRAM_WAIT_C1_WAIT_C1_WIDTH (1)
+#define BRAM_WAIT_C1_WAIT_C1_MASK (0x00000001)
+#define BRAM_WAIT_C1_WAIT_C1_BIT (0x00000001)
+
+#define BRAM_WAIT_C2_WAIT_C2_LSB (0)
+#define BRAM_WAIT_C2_WAIT_C2_WIDTH (1)
+#define BRAM_WAIT_C2_WAIT_C2_MASK (0x00000001)
+#define BRAM_WAIT_C2_WAIT_C2_BIT (0x00000001)
+
+#define BRAM_WAIT_C3_WAIT_C3_LSB (0)
+#define BRAM_WAIT_C3_WAIT_C3_WIDTH (1)
+#define BRAM_WAIT_C3_WAIT_C3_MASK (0x00000001)
+#define BRAM_WAIT_C3_WAIT_C3_BIT (0x00000001)
+
+#define BRAM_WAIT_C4_WAIT_C4_LSB (0)
+#define BRAM_WAIT_C4_WAIT_C4_WIDTH (1)
+#define BRAM_WAIT_C4_WAIT_C4_MASK (0x00000001)
+#define BRAM_WAIT_C4_WAIT_C4_BIT (0x00000001)
+
+#define RAKE_WAIT_C0_WAIT_C0_LSB (0)
+#define RAKE_WAIT_C0_WAIT_C0_WIDTH (1)
+#define RAKE_WAIT_C0_WAIT_C0_MASK (0x00000001)
+#define RAKE_WAIT_C0_WAIT_C0_BIT (0x00000001)
+
+#define RAKE_WAIT_C1_WAIT_C1_LSB (0)
+#define RAKE_WAIT_C1_WAIT_C1_WIDTH (1)
+#define RAKE_WAIT_C1_WAIT_C1_MASK (0x00000001)
+#define RAKE_WAIT_C1_WAIT_C1_BIT (0x00000001)
+
+#define RAKE_WAIT_C2_WAIT_C2_LSB (0)
+#define RAKE_WAIT_C2_WAIT_C2_WIDTH (1)
+#define RAKE_WAIT_C2_WAIT_C2_MASK (0x00000001)
+#define RAKE_WAIT_C2_WAIT_C2_BIT (0x00000001)
+
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_LSB (2)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_MASK (0x00000004)
+#define SRAM_CTRL_AO_IDLE_BRAM_SRAM_CTRL_AO_IDLE_BIT (0x00000004)
+
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_LSB (1)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_MASK (0x00000002)
+#define SRAM_CTRL_AO_IDLE_DMC_SRAM_CTRL_AO_IDLE_BIT (0x00000002)
+
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_LSB (0)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_WIDTH (1)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_MASK (0x00000001)
+#define SRAM_CTRL_AO_IDLE_RAKE_SRAM_CTRL_AO_IDLE_BIT (0x00000001)
+
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_LSB (0)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_WIDTH (1)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_MASK (0x00000001)
+#define RAKE_PM_CIPHER_EN_RAKE_CIPHER_EN_BIT (0x00000001)
+
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_LSB (0)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_WIDTH (1)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_MASK (0x00000001)
+#define RAKE_PM_CIPHER_LOCK_RAKE_CIPHER_LOCK_BIT (0x00000001)
+
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_LSB (0)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_WIDTH (1)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_MASK (0x00000001)
+#define SCQ_SPM_CIPHER_EN_SCQ_SPM_CIPHER_EN_BIT (0x00000001)
+
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_LSB (0)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_WIDTH (1)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_MASK (0x00000001)
+#define SCQ_SPM_CIPHER_LOCK_SCQ_SPM_CIPHER_LOCK_BIT (0x00000001)
+
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_LSB (6)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_MASK (0x00000040)
+#define CK_IDLE_MASK_BIGRAM_RAKE_CK_IDLE_MASK_BIT (0x00000040)
+
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_LSB (5)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_MASK (0x00000020)
+#define CK_IDLE_MASK_RAKE_RAKE_CK_IDLE_MASK_BIT (0x00000020)
+
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_LSB (4)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_MASK (0x00000010)
+#define CK_IDLE_MASK_BIGRAM_BRP_CK_IDLE_MASK_BIT (0x00000010)
+
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_LSB (3)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_MASK (0x00000008)
+#define CK_IDLE_MASK_DMC_BRP_CK_IDLE_MASK_BIT (0x00000008)
+
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_LSB (2)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_MASK (0x00000004)
+#define CK_IDLE_MASK_BRP_BRP_CK_IDLE_MASK_BIT (0x00000004)
+
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_LSB (1)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_MASK (0x00000002)
+#define CK_IDLE_MASK_BIGRAM_VDSP_CK_IDLE_MASK_BIT (0x00000002)
+
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_LSB (0)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_WIDTH (1)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_MASK (0x00000001)
+#define CK_IDLE_MASK_VDSP_VDSP_CK_IDLE_MASK_BIT (0x00000001)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_LSB (6)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_MASK (0x00000040)
+#define CK_IDLE_DBG_MASK_BIGRAM_RAKE_CK_IDLE_DBG_MASK_BIT (0x00000040)
+
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_LSB (5)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_MASK (0x00000020)
+#define CK_IDLE_DBG_MASK_RAKE_RAKE_CK_IDLE_DBG_MASK_BIT (0x00000020)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_LSB (4)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_MASK (0x00000010)
+#define CK_IDLE_DBG_MASK_BIGRAM_BRP_CK_IDLE_DBG_MASK_BIT (0x00000010)
+
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_LSB (3)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_MASK (0x00000008)
+#define CK_IDLE_DBG_MASK_DMC_BRP_CK_IDLE_DBG_MASK_BIT (0x00000008)
+
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_LSB (2)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_MASK (0x00000004)
+#define CK_IDLE_DBG_MASK_BRP_BRP_CK_IDLE_DBG_MASK_BIT (0x00000004)
+
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_LSB (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_MASK (0x00000002)
+#define CK_IDLE_DBG_MASK_BIGRAM_VDSP_CK_IDLE_DBG_MASK_BIT (0x00000002)
+
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_LSB (0)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_WIDTH (1)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_MASK (0x00000001)
+#define CK_IDLE_DBG_MASK_VDSP_VDSP_CK_IDLE_DBG_MASK_BIT (0x00000001)
+
+
+#endif /*_CPH_MDRXSYS_MEM_CONFIG_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_97.h b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_97.h
new file mode 100644
index 0000000..ddf18ec
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmdrxsysmemconfigreg_97.h
@@ -0,0 +1,205 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+#define _CPH_MDRXSYS_MEM_CONFIG_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MDRXAO_MEM_CONFIG_REG_BASE (0xA8110000)
+
+#define MDRXAO_MEM_CONFIG_end (MDRXAO_MEM_CONFIG_REG_BASE + 0x9c + 1*4)
+
+
+
+#define RAKE_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x0))
+#define RAKE_WAIT_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4))
+#define RAKE_GROUP_PWDN_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x8))
+#define RAKE_SRAM_CTRL_AO_IDLE_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0xc))
+#define RAKE_SW_PWDN_0_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x10))
+#define RAKE_SW_PWDN_1_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x14))
+#define RAKE_SW_PWDN_2_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x18))
+#define INRMM_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x1c))
+#define INRMM_WAIT_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x20))
+#define INRMM_GROUP_PWDN_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x24))
+#define INRMM_SRAM_CTRL_AO_IDLE_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x28))
+#define INRMM_SW_PWDN_0_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x2c))
+#define INRMM_SW_PWDN_1_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x30))
+#define INRMM_SW_PWDN_2_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x34))
+#define INRMM_SW_PWDN_3_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x38))
+#define INRMM_SW_PWDN_4_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x3c))
+#define INRMM_SW_PWDN_5_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x40))
+#define INRMM_SW_PWDN_6_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x44))
+#define INRMM_SW_PWDN_7_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x48))
+#define BRP_SW_TYPE ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x4c))
+#define BRP_WAIT_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x50))
+#define BRP_GROUP_PWDN_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x54))
+#define BRP_SRAM_CTRL_AO_IDLE_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x58))
+#define BRP_SW_PWDN_0_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x5c))
+#define BRP_SW_PWDN_1_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x60))
+#define BRP_SW_PWDN_2_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x64))
+#define BRP_SW_PWDN_3_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x68))
+#define BRP_SW_PWDN_4_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x6C))
+#define MDRXSYS_EFUSE_S2P_0_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x70))
+#define MDRXSYS_EFUSE_S2P_1_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x74))
+#define MDRXSYS_EFUSE_S2P_2_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x78))
+#define MDRXSYS_EFUSE_S2P_3_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x7c))
+#define MDRXSYS_EFUSE_S2P_4_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x80))
+#define MDRXSYS_EFUSE_S2P_5_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x84))
+#define MDRXSYS_EFUSE_S2P_6_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x88))
+#define MDRXSYS_EFUSE_S2P_7_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x8C))
+#define MDRXSYS_EFUSE_S2P_8_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x90))
+#define MDRXSYS_EFUSE_S2P_9_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x94))
+#define MDRXSYS_EFUSE_S2P_10_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x98))
+#define MDRXSYS_EFUSE_S2P_RX_RESET_ADDR ((APBADDR32)(MDRXAO_MEM_CONFIG_REG_BASE + 0x9C))
+
+
+#define RAKE_SW_TYPE_LSB (0)
+#define RAKE_SW_TYPE_WIDTH (7)
+#define RAKE_SW_TYPE_MASK (0x0000007F)
+#define RAKE_SW_TYPE_BIT (0x0000007F)
+
+#define RAKE_SW_PWDN_0_ADDR_LSB (0)
+#define RAKE_SW_PWDN_0_WIDTH (7)
+#define RAKE_SW_PWDN_0_MASK (0x0000007F)
+#define RAKE_SW_PWDN_0_BIT (0x0000007F)
+
+#define RAKE_SW_PWDN_1_ADDR_LSB (0)
+#define RAKE_SW_PWDN_1_WIDTH (7)
+#define RAKE_SW_PWDN_1_MASK (0x0000007F)
+#define RAKE_SW_PWDN_1_BIT (0x0000007F)
+
+#define RAKE_SW_PWDN_2_ADDR_LSB (0)
+#define RAKE_SW_PWDN_2_WIDTH (7)
+#define RAKE_SW_PWDN_2_MASK (0x0000007F)
+#define RAKE_SW_PWDN_2_BIT (0x0000007F)
+
+#define INRMM_SW_TYPE_LSB (0)
+#define INRMM_SW_TYPE_WIDTH (15)
+#define INRMM_SW_TYPE_MASK (0x00007FFF)
+#define INRMM_SW_TYPE_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_0_ADDR_LSB (0)
+#define INRMM_SW_PWDN_0_WIDTH (15)
+#define INRMM_SW_PWDN_0_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_0_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_1_ADDR_LSB (0)
+#define INRMM_SW_PWDN_1_WIDTH (15)
+#define INRMM_SW_PWDN_1_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_1_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_2_ADDR_LSB (0)
+#define INRMM_SW_PWDN_2_WIDTH (15)
+#define INRMM_SW_PWDN_2_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_2_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_3_ADDR_LSB (0)
+#define INRMM_SW_PWDN_3_WIDTH (15)
+#define INRMM_SW_PWDN_3_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_3_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_4_ADDR_LSB (0)
+#define INRMM_SW_PWDN_4_WIDTH (15)
+#define INRMM_SW_PWDN_4_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_4_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_5_ADDR_LSB (0)
+#define INRMM_SW_PWDN_5_WIDTH (15)
+#define INRMM_SW_PWDN_5_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_5_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_6_ADDR_LSB (0)
+#define INRMM_SW_PWDN_6_WIDTH (15)
+#define INRMM_SW_PWDN_6_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_6_BIT (0x00007FFF)
+
+#define INRMM_SW_PWDN_7_ADDR_LSB (0)
+#define INRMM_SW_PWDN_7_WIDTH (15)
+#define INRMM_SW_PWDN_7_MASK (0x00007FFF)
+#define INRMM_SW_PWDN_7_BIT (0x00007FFF)
+
+#define BRP_SW_TYPE_LSB (0)
+#define BRP_SW_TYPE_WIDTH (8)
+#define BRP_SW_TYPE_MASK (0x000000FF)
+#define BRP_SW_TYPE_BIT (0x000000FF)
+
+#define BRP_SW_PWDN_0_ADDR_LSB (0)
+#define BRP_SW_PWDN_0_WIDTH (8)
+#define BRP_SW_PWDN_0_MASK (0x000000FF)
+#define BRP_SW_PWDN_0_BIT (0x000000FF)
+
+#define BRP_SW_PWDN_1_ADDR_LSB (0)
+#define BRP_SW_PWDN_1_WIDTH (8)
+#define BRP_SW_PWDN_1_MASK (0x000000FF)
+#define BRP_SW_PWDN_1_BIT (0x000000FF)
+
+#define BRP_SW_PWDN_2_ADDR_LSB (0)
+#define BRP_SW_PWDN_2_WIDTH (8)
+#define BRP_SW_PWDN_2_MASK (0x000000FF)
+#define BRP_SW_PWDN_2_BIT (0x000000FF)
+
+#define BRP_SW_PWDN_3_ADDR_LSB (0)
+#define BRP_SW_PWDN_3_WIDTH (8)
+#define BRP_SW_PWDN_3_MASK (0x000000FF)
+#define BRP_SW_PWDN_3_BIT (0x000000FF)
+
+#define BRP_SW_PWDN_4_ADDR_LSB (0)
+#define BRP_SW_PWDN_4_WIDTH (8)
+#define BRP_SW_PWDN_4_MASK (0x000000FF)
+#define BRP_SW_PWDN_4_BIT (0x000000FF)
+
+#define BRP_WAIT_ADDR_C3 (0x00000008)
+#define BRP_WAIT_ADDR_C4 (0x00000010)
+
+#define INRMM_WAIT_ADDR_C3 (0x00000008)
+#define INRMM_WAIT_ADDR_C4 (0x00000010)
+
+#define RAKE_WAIT_ADDR_C1 (0x00000002)
+#define RAKE_WAIT_ADDR_C2 (0x00000004)
+
+
+
+
+#endif /*_CPH_MDRXSYS_MEM_CONFIG_REG_H_*/
diff --git a/mcu/interface/l1/cl1/common/HW/cphmrsg.h b/mcu/interface/l1/cl1/common/HW/cphmrsg.h
new file mode 100644
index 0000000..8bfa90e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmrsg.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphmrsg_93.h"
+#elif defined(__MD95__)
+#include "cphmrsg_95.h"
+#elif defined(__MD97__)
+#include "cphmrsg_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphmrsg_93.h b/mcu/interface/l1/cl1/common/HW/cphmrsg_93.h
new file mode 100644
index 0000000..8e7ac2d
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmrsg_93.h
@@ -0,0 +1,243 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MRSG_H_
+#define _CPH_MRSG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MRSG_REG_BASE (0xA7110000)
+
+#define MRSG_end (MRSG_REG_BASE + 0x00000038 + 1*4)
+
+
+
+#define MRSG_PUMP_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000000))
+#define MRSG_IQ_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000008))
+#define MRSG_IQ_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000000C))
+#define MRSG_IQ_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000010))
+#define MRSG_FIFO_UFLOW ((APBADDR32)(MRSG_REG_BASE + 0x00000014))
+#define MRSG_RSSI_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000018))
+#define MRSG_RSSI_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000001C))
+#define MRSG_RSSI_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000020))
+#define MRSG_MODE_SWITCH ((APBADDR32)(MRSG_REG_BASE + 0x00000024))
+#define MRSG_SW_RST ((APBADDR32)(MRSG_REG_BASE + 0x00000028))
+#define MRSG_DDR_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x0000002C))
+#define MRSG_CHECKSUM_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000030))
+#define MRSG_CHECKSUM_LEN ((APBADDR32)(MRSG_REG_BASE + 0x00000034))
+#define MRSG_CHECKSUM ((APBADDR32)(MRSG_REG_BASE + 0x00000038))
+
+
+#define MRSG_PUMP_CTRL_PUMP_EN_LSB (0)
+#define MRSG_PUMP_CTRL_PUMP_EN_WIDTH (1)
+#define MRSG_PUMP_CTRL_PUMP_EN_MASK (0x00000001)
+#define MRSG_PUMP_CTRL_PUMP_EN_BIT (0x00000001)
+
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_LSB (0)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_WIDTH (32)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_IQ_LENGTH_IQ_LENGTH_LSB (0)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_WIDTH (24)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_MASK (0x00FFFFFF)
+
+#define MRSG_IQ_PARA_DLY_A1C1_LSB (7)
+#define MRSG_IQ_PARA_DLY_A1C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A1C1_MASK (0x00000380)
+
+#define MRSG_IQ_PARA_RSH_A1C1_LSB (5)
+#define MRSG_IQ_PARA_RSH_A1C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A1C1_MASK (0x00000060)
+
+#define MRSG_IQ_PARA_DLY_A0C1_LSB (2)
+#define MRSG_IQ_PARA_DLY_A0C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A0C1_MASK (0x0000001C)
+
+#define MRSG_IQ_PARA_RSH_A0C1_LSB (0)
+#define MRSG_IQ_PARA_RSH_A0C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A0C1_MASK (0x00000003)
+
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_LSB (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_MASK (0x00000002)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_BIT (0x00000002)
+
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_LSB (0)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_MASK (0x00000001)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_BIT (0x00000001)
+
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_LSB (0)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_WIDTH (32)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_LSB (0)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_WIDTH (16)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_MASK (0x0000FFFF)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_LSB (13)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_MASK (0x0000E000)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_LSB (8)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_MASK (0x00001F00)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_LSB (5)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_MASK (0x000000E0)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_LSB (0)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_MASK (0x0000001F)
+
+#define MRSG_MODE_SWITCH_RXD_ON_LSB (15)
+#define MRSG_MODE_SWITCH_RXD_ON_WIDTH (1)
+#define MRSG_MODE_SWITCH_RXD_ON_MASK (0x00008000)
+#define MRSG_MODE_SWITCH_RXD_ON_BIT (0x00008000)
+
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_LSB (13)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_MASK (0x00002000)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_BIT (0x00002000)
+
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_LSB (12)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_MASK (0x00001000)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_BIT (0x00001000)
+
+#define MRSG_MODE_SWITCH_PCH_W_LSB (11)
+#define MRSG_MODE_SWITCH_PCH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_MASK (0x00000800)
+#define MRSG_MODE_SWITCH_PCH_W_BIT (0x00000800)
+
+#define MRSG_MODE_SWITCH_DFE_DBG_LSB (10)
+#define MRSG_MODE_SWITCH_DFE_DBG_WIDTH (1)
+#define MRSG_MODE_SWITCH_DFE_DBG_MASK (0x00000400)
+#define MRSG_MODE_SWITCH_DFE_DBG_BIT (0x00000400)
+
+#define MRSG_MODE_SWITCH_INR_L_LSB (9)
+#define MRSG_MODE_SWITCH_INR_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_L_MASK (0x00000200)
+#define MRSG_MODE_SWITCH_INR_L_BIT (0x00000200)
+
+#define MRSG_MODE_SWITCH_INR_Cdo_LSB (8)
+#define MRSG_MODE_SWITCH_INR_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_Cdo_MASK (0x00000100)
+#define MRSG_MODE_SWITCH_INR_Cdo_BIT (0x00000100)
+
+#define MRSG_MODE_SWITCH_INR_C1x_LSB (7)
+#define MRSG_MODE_SWITCH_INR_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_C1x_MASK (0x00000080)
+#define MRSG_MODE_SWITCH_INR_C1x_BIT (0x00000080)
+
+#define MRSG_MODE_SWITCH_INR_T_LSB (6)
+#define MRSG_MODE_SWITCH_INR_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_T_MASK (0x00000040)
+#define MRSG_MODE_SWITCH_INR_T_BIT (0x00000040)
+
+#define MRSG_MODE_SWITCH_INR_W_LSB (5)
+#define MRSG_MODE_SWITCH_INR_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_W_MASK (0x00000020)
+#define MRSG_MODE_SWITCH_INR_W_BIT (0x00000020)
+
+#define MRSG_MODE_SWITCH_CSH_L_LSB (4)
+#define MRSG_MODE_SWITCH_CSH_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_L_MASK (0x00000010)
+#define MRSG_MODE_SWITCH_CSH_L_BIT (0x00000010)
+
+#define MRSG_MODE_SWITCH_CSH_Cdo_LSB (3)
+#define MRSG_MODE_SWITCH_CSH_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_Cdo_MASK (0x00000008)
+#define MRSG_MODE_SWITCH_CSH_Cdo_BIT (0x00000008)
+
+#define MRSG_MODE_SWITCH_CSH_C1x_LSB (2)
+#define MRSG_MODE_SWITCH_CSH_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_C1x_MASK (0x00000004)
+#define MRSG_MODE_SWITCH_CSH_C1x_BIT (0x00000004)
+
+#define MRSG_MODE_SWITCH_CSH_T_LSB (1)
+#define MRSG_MODE_SWITCH_CSH_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_T_MASK (0x00000002)
+#define MRSG_MODE_SWITCH_CSH_T_BIT (0x00000002)
+
+#define MRSG_MODE_SWITCH_CSH_W_LSB (0)
+#define MRSG_MODE_SWITCH_CSH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_W_MASK (0x00000001)
+#define MRSG_MODE_SWITCH_CSH_W_BIT (0x00000001)
+
+#define MRSG_SW_RST_RST_LSB (0)
+#define MRSG_SW_RST_RST_WIDTH (1)
+#define MRSG_SW_RST_RST_MASK (0x00000001)
+#define MRSG_SW_RST_RST_BIT (0x00000001)
+
+#define MRSG_DDR_CTRL_DDR_ON_LSB (0)
+#define MRSG_DDR_CTRL_DDR_ON_WIDTH (1)
+#define MRSG_DDR_CTRL_DDR_ON_MASK (0x00000001)
+#define MRSG_DDR_CTRL_DDR_ON_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_CTRL_checksum_done_LSB (31)
+#define MRSG_CHECKSUM_CTRL_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_checksum_done_MASK (0x80000000)
+#define MRSG_CHECKSUM_CTRL_checksum_done_BIT (0x80000000)
+
+#define MRSG_CHECKSUM_CTRL_start_checksum_LSB (0)
+#define MRSG_CHECKSUM_CTRL_start_checksum_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_start_checksum_MASK (0x00000001)
+#define MRSG_CHECKSUM_CTRL_start_checksum_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_LEN_checksum_len_LSB (0)
+#define MRSG_CHECKSUM_LEN_checksum_len_WIDTH (32)
+#define MRSG_CHECKSUM_LEN_checksum_len_MASK (0xFFFFFFFF)
+
+#define MRSG_CHECKSUM_tx_checksum_LSB (16)
+#define MRSG_CHECKSUM_tx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_tx_checksum_MASK (0xFFFF0000)
+
+#define MRSG_CHECKSUM_rx_checksum_LSB (0)
+#define MRSG_CHECKSUM_rx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_rx_checksum_MASK (0x0000FFFF)
+
+
+#endif //#ifndef _CPH_MRSG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphmrsg_95.h b/mcu/interface/l1/cl1/common/HW/cphmrsg_95.h
new file mode 100644
index 0000000..e421059
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmrsg_95.h
@@ -0,0 +1,266 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MRSG_H_
+#define _CPH_MRSG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MRSG_REG_BASE (0xA7110000)
+
+#define MRSG_end (MRSG_REG_BASE + 0x00000040 + 1*4)
+
+
+
+#define MRSG_PUMP_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000000))
+#define MRSG_IQ_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000008))
+#define MRSG_IQ_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000000C))
+#define MRSG_IQ_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000010))
+#define MRSG_FIFO_UFLOW ((APBADDR32)(MRSG_REG_BASE + 0x00000014))
+#define MRSG_RSSI_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000018))
+#define MRSG_RSSI_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000001C))
+#define MRSG_RSSI_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000020))
+#define MRSG_MODE_SWITCH ((APBADDR32)(MRSG_REG_BASE + 0x00000024))
+#define MRSG_SW_RST ((APBADDR32)(MRSG_REG_BASE + 0x00000028))
+#define MRSG_DDR_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x0000002C))
+#define MRSG_CHECKSUM_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000030))
+#define MRSG_CHECKSUM_LEN ((APBADDR32)(MRSG_REG_BASE + 0x00000034))
+#define MRSG_CHECKSUM ((APBADDR32)(MRSG_REG_BASE + 0x00000038))
+#define MRSG_TICKGEN_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000040))
+
+
+#define MRSG_PUMP_CTRL_PUMP_EN_LSB (0)
+#define MRSG_PUMP_CTRL_PUMP_EN_WIDTH (1)
+#define MRSG_PUMP_CTRL_PUMP_EN_MASK (0x00000001)
+#define MRSG_PUMP_CTRL_PUMP_EN_BIT (0x00000001)
+
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_LSB (0)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_WIDTH (32)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_IQ_LENGTH_IQ_LENGTH_LSB (0)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_WIDTH (24)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_MASK (0x00FFFFFF)
+
+#define MRSG_IQ_PARA_DLY_A1C1_LSB (7)
+#define MRSG_IQ_PARA_DLY_A1C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A1C1_MASK (0x00000380)
+
+#define MRSG_IQ_PARA_RSH_A1C1_LSB (5)
+#define MRSG_IQ_PARA_RSH_A1C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A1C1_MASK (0x00000060)
+
+#define MRSG_IQ_PARA_DLY_A0C1_LSB (2)
+#define MRSG_IQ_PARA_DLY_A0C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A0C1_MASK (0x0000001C)
+
+#define MRSG_IQ_PARA_RSH_A0C1_LSB (0)
+#define MRSG_IQ_PARA_RSH_A0C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A0C1_MASK (0x00000003)
+
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_LSB (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_MASK (0x00000002)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_BIT (0x00000002)
+
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_LSB (0)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_MASK (0x00000001)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_BIT (0x00000001)
+
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_LSB (0)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_WIDTH (32)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_LSB (0)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_WIDTH (16)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_MASK (0x0000FFFF)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_LSB (13)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_MASK (0x0000E000)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_LSB (8)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_MASK (0x00001F00)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_LSB (5)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_MASK (0x000000E0)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_LSB (0)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_MASK (0x0000001F)
+
+#define MRSG_MODE_SWITCH_RXD_ON_LSB (15)
+#define MRSG_MODE_SWITCH_RXD_ON_WIDTH (1)
+#define MRSG_MODE_SWITCH_RXD_ON_MASK (0x00008000)
+#define MRSG_MODE_SWITCH_RXD_ON_BIT (0x00008000)
+
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_LSB (13)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_MASK (0x00002000)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_BIT (0x00002000)
+
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_LSB (12)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_MASK (0x00001000)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_BIT (0x00001000)
+
+#define MRSG_MODE_SWITCH_PCH_W_LSB (11)
+#define MRSG_MODE_SWITCH_PCH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_MASK (0x00000800)
+#define MRSG_MODE_SWITCH_PCH_W_BIT (0x00000800)
+
+#define MRSG_MODE_SWITCH_DFE_DBG_LSB (10)
+#define MRSG_MODE_SWITCH_DFE_DBG_WIDTH (1)
+#define MRSG_MODE_SWITCH_DFE_DBG_MASK (0x00000400)
+#define MRSG_MODE_SWITCH_DFE_DBG_BIT (0x00000400)
+
+#define MRSG_MODE_SWITCH_INR_L_LSB (9)
+#define MRSG_MODE_SWITCH_INR_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_L_MASK (0x00000200)
+#define MRSG_MODE_SWITCH_INR_L_BIT (0x00000200)
+
+#define MRSG_MODE_SWITCH_INR_Cdo_LSB (8)
+#define MRSG_MODE_SWITCH_INR_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_Cdo_MASK (0x00000100)
+#define MRSG_MODE_SWITCH_INR_Cdo_BIT (0x00000100)
+
+#define MRSG_MODE_SWITCH_INR_C1x_LSB (7)
+#define MRSG_MODE_SWITCH_INR_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_C1x_MASK (0x00000080)
+#define MRSG_MODE_SWITCH_INR_C1x_BIT (0x00000080)
+
+#define MRSG_MODE_SWITCH_INR_T_LSB (6)
+#define MRSG_MODE_SWITCH_INR_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_T_MASK (0x00000040)
+#define MRSG_MODE_SWITCH_INR_T_BIT (0x00000040)
+
+#define MRSG_MODE_SWITCH_INR_W_LSB (5)
+#define MRSG_MODE_SWITCH_INR_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_W_MASK (0x00000020)
+#define MRSG_MODE_SWITCH_INR_W_BIT (0x00000020)
+
+#define MRSG_MODE_SWITCH_CSH_L_LSB (4)
+#define MRSG_MODE_SWITCH_CSH_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_L_MASK (0x00000010)
+#define MRSG_MODE_SWITCH_CSH_L_BIT (0x00000010)
+
+#define MRSG_MODE_SWITCH_CSH_Cdo_LSB (3)
+#define MRSG_MODE_SWITCH_CSH_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_Cdo_MASK (0x00000008)
+#define MRSG_MODE_SWITCH_CSH_Cdo_BIT (0x00000008)
+
+#define MRSG_MODE_SWITCH_CSH_C1x_LSB (2)
+#define MRSG_MODE_SWITCH_CSH_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_C1x_MASK (0x00000004)
+#define MRSG_MODE_SWITCH_CSH_C1x_BIT (0x00000004)
+
+#define MRSG_MODE_SWITCH_CSH_T_LSB (1)
+#define MRSG_MODE_SWITCH_CSH_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_T_MASK (0x00000002)
+#define MRSG_MODE_SWITCH_CSH_T_BIT (0x00000002)
+
+#define MRSG_MODE_SWITCH_CSH_W_LSB (0)
+#define MRSG_MODE_SWITCH_CSH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_W_MASK (0x00000001)
+#define MRSG_MODE_SWITCH_CSH_W_BIT (0x00000001)
+
+#define MRSG_SW_RST_RST_LSB (0)
+#define MRSG_SW_RST_RST_WIDTH (1)
+#define MRSG_SW_RST_RST_MASK (0x00000001)
+#define MRSG_SW_RST_RST_BIT (0x00000001)
+
+#define MRSG_DDR_CTRL_DDR_ON_LSB (0)
+#define MRSG_DDR_CTRL_DDR_ON_WIDTH (1)
+#define MRSG_DDR_CTRL_DDR_ON_MASK (0x00000001)
+#define MRSG_DDR_CTRL_DDR_ON_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_LSB (31)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_MASK (0x80000000)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_BIT (0x80000000)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_LSB (30)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_MASK (0x40000000)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_BIT (0x40000000)
+
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_LSB (29)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_MASK (0x20000000)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_BIT (0x20000000)
+
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_LSB (28)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_MASK (0x10000000)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_BIT (0x10000000)
+
+#define MRSG_CHECKSUM_CTRL_start_checksum_LSB (0)
+#define MRSG_CHECKSUM_CTRL_start_checksum_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_start_checksum_MASK (0x00000001)
+#define MRSG_CHECKSUM_CTRL_start_checksum_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_LEN_checksum_len_LSB (0)
+#define MRSG_CHECKSUM_LEN_checksum_len_WIDTH (32)
+#define MRSG_CHECKSUM_LEN_checksum_len_MASK (0xFFFFFFFF)
+
+#define MRSG_CHECKSUM_tx_checksum_LSB (16)
+#define MRSG_CHECKSUM_tx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_tx_checksum_MASK (0xFFFF0000)
+
+#define MRSG_CHECKSUM_rx_checksum_LSB (0)
+#define MRSG_CHECKSUM_rx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_rx_checksum_MASK (0x0000FFFF)
+
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_LSB (4)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_WIDTH (1)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_MASK (0x00000010)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_BIT (0x00000010)
+
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_LSB (0)
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_WIDTH (4)
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_MASK (0x0000000F)
+
+#endif //#ifndef _CPH_MRSG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphmrsg_97.h b/mcu/interface/l1/cl1/common/HW/cphmrsg_97.h
new file mode 100644
index 0000000..ef1b0a1
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphmrsg_97.h
@@ -0,0 +1,268 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_MRSG_H_
+#define _CPH_MRSG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MRSG_REG_BASE (0xA8D60000)
+
+#define MRSG_end (MRSG_REG_BASE + 0x00000040 + 1*4)
+
+
+
+#define MRSG_PUMP_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000000))
+#define MRSG_IQ_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000008))
+#define MRSG_IQ_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000000C))
+#define MRSG_IQ_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000010))
+#define MRSG_FIFO_UFLOW ((APBADDR32)(MRSG_REG_BASE + 0x00000014))
+#define MRSG_RSSI_SRC_ADDR ((APBADDR32)(MRSG_REG_BASE + 0x00000018))
+#define MRSG_RSSI_LENGTH ((APBADDR32)(MRSG_REG_BASE + 0x0000001C))
+#define MRSG_RSSI_PARA ((APBADDR32)(MRSG_REG_BASE + 0x00000020))
+#define MRSG_MODE_SWITCH ((APBADDR32)(MRSG_REG_BASE + 0x00000024))
+#define MRSG_SW_RST ((APBADDR32)(MRSG_REG_BASE + 0x00000028))
+#define MRSG_DDR_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x0000002C))
+#define MRSG_CHECKSUM_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000030))
+#define MRSG_CHECKSUM_LEN ((APBADDR32)(MRSG_REG_BASE + 0x00000034))
+#define MRSG_CHECKSUM ((APBADDR32)(MRSG_REG_BASE + 0x00000038))
+#define MRSG_TICKGEN_CTRL ((APBADDR32)(MRSG_REG_BASE + 0x00000040))
+#define MRSG_LGAIN_DUR_LEN_GTH ((APBADDR32)(MRSG_REG_BASE + 0x00000044))
+
+
+
+#define MRSG_PUMP_CTRL_PUMP_EN_LSB (0)
+#define MRSG_PUMP_CTRL_PUMP_EN_WIDTH (1)
+#define MRSG_PUMP_CTRL_PUMP_EN_MASK (0x00000001)
+#define MRSG_PUMP_CTRL_PUMP_EN_BIT (0x00000001)
+
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_LSB (0)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_WIDTH (32)
+#define MRSG_IQ_SRC_ADDR_IQ_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_IQ_LENGTH_IQ_LENGTH_LSB (0)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_WIDTH (24)
+#define MRSG_IQ_LENGTH_IQ_LENGTH_MASK (0x00FFFFFF)
+
+#define MRSG_IQ_PARA_DLY_A1C1_LSB (7)
+#define MRSG_IQ_PARA_DLY_A1C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A1C1_MASK (0x00000380)
+
+#define MRSG_IQ_PARA_RSH_A1C1_LSB (5)
+#define MRSG_IQ_PARA_RSH_A1C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A1C1_MASK (0x00000060)
+
+#define MRSG_IQ_PARA_DLY_A0C1_LSB (2)
+#define MRSG_IQ_PARA_DLY_A0C1_WIDTH (3)
+#define MRSG_IQ_PARA_DLY_A0C1_MASK (0x0000001C)
+
+#define MRSG_IQ_PARA_RSH_A0C1_LSB (0)
+#define MRSG_IQ_PARA_RSH_A0C1_WIDTH (2)
+#define MRSG_IQ_PARA_RSH_A0C1_MASK (0x00000003)
+
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_LSB (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_MASK (0x00000002)
+#define MRSG_FIFO_UFLOW_RSSI_UFLOW_BIT (0x00000002)
+
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_LSB (0)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_WIDTH (1)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_MASK (0x00000001)
+#define MRSG_FIFO_UFLOW_IQ_UFLOW_BIT (0x00000001)
+
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_LSB (0)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_WIDTH (32)
+#define MRSG_RSSI_SRC_ADDR_RSSI_SRC_ADDRESS_MASK (0xFFFFFFFF)
+
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_LSB (0)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_WIDTH (16)
+#define MRSG_RSSI_LENGTH_RSSI_LENGTH_MASK (0x0000FFFF)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_LSB (13)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A1C1_MASK (0x0000E000)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_LSB (8)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A1C1_MASK (0x00001F00)
+
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_LSB (5)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_WIDTH (3)
+#define MRSG_RSSI_PARA_RSSI_DLY_A0C1_MASK (0x000000E0)
+
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_LSB (0)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_WIDTH (5)
+#define MRSG_RSSI_PARA_RSSI_OFFSET_A0C1_MASK (0x0000001F)
+
+#define MRSG_MODE_SWITCH_RXD_ON_LSB (15)
+#define MRSG_MODE_SWITCH_RXD_ON_WIDTH (1)
+#define MRSG_MODE_SWITCH_RXD_ON_MASK (0x00008000)
+#define MRSG_MODE_SWITCH_RXD_ON_BIT (0x00008000)
+
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_LSB (13)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_MASK (0x00002000)
+#define MRSG_MODE_SWITCH_PCH_W_SWITCH_CA_BIT (0x00002000)
+
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_LSB (12)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_MASK (0x00001000)
+#define MRSG_MODE_SWITCH_CSH_PCH_DBG_W_BIT (0x00001000)
+
+#define MRSG_MODE_SWITCH_PCH_W_LSB (11)
+#define MRSG_MODE_SWITCH_PCH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_PCH_W_MASK (0x00000800)
+#define MRSG_MODE_SWITCH_PCH_W_BIT (0x00000800)
+
+#define MRSG_MODE_SWITCH_DFE_DBG_LSB (10)
+#define MRSG_MODE_SWITCH_DFE_DBG_WIDTH (1)
+#define MRSG_MODE_SWITCH_DFE_DBG_MASK (0x00000400)
+#define MRSG_MODE_SWITCH_DFE_DBG_BIT (0x00000400)
+
+#define MRSG_MODE_SWITCH_INR_L_LSB (9)
+#define MRSG_MODE_SWITCH_INR_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_L_MASK (0x00000200)
+#define MRSG_MODE_SWITCH_INR_L_BIT (0x00000200)
+
+#define MRSG_MODE_SWITCH_INR_Cdo_LSB (8)
+#define MRSG_MODE_SWITCH_INR_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_Cdo_MASK (0x00000100)
+#define MRSG_MODE_SWITCH_INR_Cdo_BIT (0x00000100)
+
+#define MRSG_MODE_SWITCH_INR_C1x_LSB (7)
+#define MRSG_MODE_SWITCH_INR_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_C1x_MASK (0x00000080)
+#define MRSG_MODE_SWITCH_INR_C1x_BIT (0x00000080)
+
+#define MRSG_MODE_SWITCH_INR_T_LSB (6)
+#define MRSG_MODE_SWITCH_INR_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_T_MASK (0x00000040)
+#define MRSG_MODE_SWITCH_INR_T_BIT (0x00000040)
+
+#define MRSG_MODE_SWITCH_INR_W_LSB (5)
+#define MRSG_MODE_SWITCH_INR_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_INR_W_MASK (0x00000020)
+#define MRSG_MODE_SWITCH_INR_W_BIT (0x00000020)
+
+#define MRSG_MODE_SWITCH_CSH_L_LSB (4)
+#define MRSG_MODE_SWITCH_CSH_L_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_L_MASK (0x00000010)
+#define MRSG_MODE_SWITCH_CSH_L_BIT (0x00000010)
+
+#define MRSG_MODE_SWITCH_CSH_Cdo_LSB (3)
+#define MRSG_MODE_SWITCH_CSH_Cdo_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_Cdo_MASK (0x00000008)
+#define MRSG_MODE_SWITCH_CSH_Cdo_BIT (0x00000008)
+
+#define MRSG_MODE_SWITCH_CSH_C1x_LSB (2)
+#define MRSG_MODE_SWITCH_CSH_C1x_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_C1x_MASK (0x00000004)
+#define MRSG_MODE_SWITCH_CSH_C1x_BIT (0x00000004)
+
+#define MRSG_MODE_SWITCH_CSH_T_LSB (1)
+#define MRSG_MODE_SWITCH_CSH_T_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_T_MASK (0x00000002)
+#define MRSG_MODE_SWITCH_CSH_T_BIT (0x00000002)
+
+#define MRSG_MODE_SWITCH_CSH_W_LSB (0)
+#define MRSG_MODE_SWITCH_CSH_W_WIDTH (1)
+#define MRSG_MODE_SWITCH_CSH_W_MASK (0x00000001)
+#define MRSG_MODE_SWITCH_CSH_W_BIT (0x00000001)
+
+#define MRSG_SW_RST_RST_LSB (0)
+#define MRSG_SW_RST_RST_WIDTH (1)
+#define MRSG_SW_RST_RST_MASK (0x00000001)
+#define MRSG_SW_RST_RST_BIT (0x00000001)
+
+#define MRSG_DDR_CTRL_DDR_ON_LSB (0)
+#define MRSG_DDR_CTRL_DDR_ON_WIDTH (1)
+#define MRSG_DDR_CTRL_DDR_ON_MASK (0x00000001)
+#define MRSG_DDR_CTRL_DDR_ON_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_LSB (31)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_MASK (0x80000000)
+#define MRSG_CHECKSUM_CTRL_tx_checksum_done_BIT (0x80000000)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_LSB (30)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_MASK (0x40000000)
+#define MRSG_CHECKSUM_CTRL_rx16_checksum_done_BIT (0x40000000)
+
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_LSB (29)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_MASK (0x20000000)
+#define MRSG_CHECKSUM_CTRL_rx32_checksum_done_BIT (0x20000000)
+
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_LSB (28)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_MASK (0x10000000)
+#define MRSG_CHECKSUM_CTRL_rx64_checksum_done_BIT (0x10000000)
+
+#define MRSG_CHECKSUM_CTRL_start_checksum_LSB (0)
+#define MRSG_CHECKSUM_CTRL_start_checksum_WIDTH (1)
+#define MRSG_CHECKSUM_CTRL_start_checksum_MASK (0x00000001)
+#define MRSG_CHECKSUM_CTRL_start_checksum_BIT (0x00000001)
+
+#define MRSG_CHECKSUM_LEN_checksum_len_LSB (0)
+#define MRSG_CHECKSUM_LEN_checksum_len_WIDTH (32)
+#define MRSG_CHECKSUM_LEN_checksum_len_MASK (0xFFFFFFFF)
+
+#define MRSG_CHECKSUM_tx_checksum_LSB (16)
+#define MRSG_CHECKSUM_tx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_tx_checksum_MASK (0xFFFF0000)
+
+#define MRSG_CHECKSUM_rx_checksum_LSB (0)
+#define MRSG_CHECKSUM_rx_checksum_WIDTH (16)
+#define MRSG_CHECKSUM_rx_checksum_MASK (0x0000FFFF)
+
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_LSB (4)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_WIDTH (1)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_MASK (0x00000010)
+#define MRSG_TICKGEN_CTRL_C2K_MODE_SEL_BIT (0x00000002)
+
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_LSB (0)
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_WIDTH (4)
+#define MRSG_TICKGEN_CTRL_C_MODE_SEL_MASK (0x0000000F)
+
+#endif //#ifndef _CPH_MRSG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg.h b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg.h
new file mode 100644
index 0000000..42a0ef6
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphrakesysglbconreg_93.h"
+#elif defined(__MD95__)
+#include "cphrakesysglbconreg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphrakesysglbconreg_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_93.h b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_93.h
new file mode 100644
index 0000000..0d88fc0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_93.h
@@ -0,0 +1,367 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RAKESYS_GLB_CON_REG_H_
+#define _CPH_RAKESYS_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RAKESYS_GLOBAL_CON_REG_BASE (0xAC200000)
+
+#define RAKESYS_GLOBAL_CON_end (RAKESYS_GLOBAL_CON_REG_BASE + 0x90 + 1*4)
+
+
+
+#define RAKE_PWR_AWARE ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x0))
+#define CG_CON ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x4))
+#define CG_SET ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x8))
+#define CG_CLR ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xC))
+#define CG_CON_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x10))
+#define CG_SET_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x14))
+#define CG_CLR_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x18))
+#define CG_CON_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x20))
+#define CG_SET_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x24))
+#define CG_CLR_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x28))
+#define CG_CON_COMB ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x30))
+#define AXI_BUS_CFG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x40))
+#define RAKE_PM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x50))
+#define RAKE_DM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x54))
+#define RAKE_CLKCNT_CTRL ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x60))
+#define RAKE_CK_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x64))
+#define RAKE_IC_DIV3_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x68))
+#define RAKE_IC_32X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x6C))
+#define RAKE_IC_8X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x70))
+#define RAKE_DBGBUS_MUX ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x80))
+#define RAKE_DUMMY_REG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x90))
+
+
+#define RAKE_PWR_AWARE_RESERVED4_LSB (21)
+#define RAKE_PWR_AWARE_RESERVED4_WIDTH (11)
+#define RAKE_PWR_AWARE_RESERVED4_MASK (0xFFE00000)
+
+#define RAKE_PWR_AWARE_RESERVED3_LSB (20)
+#define RAKE_PWR_AWARE_RESERVED3_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED3_MASK (0x00100000)
+#define RAKE_PWR_AWARE_RESERVED3_BIT (0x00100000)
+
+#define RAKE_PWR_AWARE_BUS_ATB_LSB (19)
+#define RAKE_PWR_AWARE_BUS_ATB_WIDTH (1)
+#define RAKE_PWR_AWARE_BUS_ATB_MASK (0x00080000)
+#define RAKE_PWR_AWARE_BUS_ATB_BIT (0x00080000)
+
+#define RAKE_PWR_AWARE_RESERVED2_LSB (14)
+#define RAKE_PWR_AWARE_RESERVED2_WIDTH (5)
+#define RAKE_PWR_AWARE_RESERVED2_MASK (0x0007C000)
+
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_LSB (13)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_MASK (0x00002000)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_BIT (0x00002000)
+
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_LSB (12)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_MASK (0x00001000)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_BIT (0x00001000)
+
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_LSB (11)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_MASK (0x00000800)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_BIT (0x00000800)
+
+#define RAKE_PWR_AWARE_RESERVED1_LSB (10)
+#define RAKE_PWR_AWARE_RESERVED1_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED1_MASK (0x00000400)
+#define RAKE_PWR_AWARE_RESERVED1_BIT (0x00000400)
+
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_LSB (9)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_MASK (0x00000200)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_BIT (0x00000200)
+
+#define RAKE_PWR_AWARE_RAKE_LOADER_LSB (8)
+#define RAKE_PWR_AWARE_RAKE_LOADER_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOADER_MASK (0x00000100)
+#define RAKE_PWR_AWARE_RAKE_LOADER_BIT (0x00000100)
+
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_LSB (7)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_MASK (0x00000080)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_BIT (0x00000080)
+
+#define RAKE_PWR_AWARE_RAKE_BRIF_LSB (6)
+#define RAKE_PWR_AWARE_RAKE_BRIF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_BRIF_MASK (0x00000040)
+#define RAKE_PWR_AWARE_RAKE_BRIF_BIT (0x00000040)
+
+#define RAKE_PWR_AWARE_RESERVED0_LSB (5)
+#define RAKE_PWR_AWARE_RESERVED0_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED0_MASK (0x00000020)
+#define RAKE_PWR_AWARE_RESERVED0_BIT (0x00000020)
+
+#define RAKE_PWR_AWARE_RAKE_EXT_LSB (4)
+#define RAKE_PWR_AWARE_RAKE_EXT_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_EXT_MASK (0x00000010)
+#define RAKE_PWR_AWARE_RAKE_EXT_BIT (0x00000010)
+
+#define RAKE_PWR_AWARE_RAKE_DESP_LSB (3)
+#define RAKE_PWR_AWARE_RAKE_DESP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESP_MASK (0x00000008)
+#define RAKE_PWR_AWARE_RAKE_DESP_BIT (0x00000008)
+
+#define RAKE_PWR_AWARE_RAKE_DESIG_LSB (2)
+#define RAKE_PWR_AWARE_RAKE_DESIG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESIG_MASK (0x00000004)
+#define RAKE_PWR_AWARE_RAKE_DESIG_BIT (0x00000004)
+
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_LSB (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_MASK (0x00000002)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_BIT (0x00000002)
+
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_LSB (0)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_MASK (0x00000001)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_BIT (0x00000001)
+
+#define CG_CON_RESERVED5_LSB (2)
+#define CG_CON_RESERVED5_WIDTH (30)
+#define CG_CON_RESERVED5_MASK (0xFFFFFFFC)
+
+#define CG_CON_RAKE_BRIF_CG_CON_LSB (1)
+#define CG_CON_RAKE_BRIF_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_BRIF_CG_CON_MASK (0x00000002)
+#define CG_CON_RAKE_BRIF_CG_CON_BIT (0x00000002)
+
+#define CG_CON_RAKE_CORE_CG_CON_LSB (0)
+#define CG_CON_RAKE_CORE_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_CORE_CG_CON_MASK (0x00000001)
+#define CG_CON_RAKE_CORE_CG_CON_BIT (0x00000001)
+
+#define CG_SET_RESERVED6_LSB (2)
+#define CG_SET_RESERVED6_WIDTH (30)
+#define CG_SET_RESERVED6_MASK (0xFFFFFFFC)
+
+#define CG_SET_RAKE_BRIF_CG_CON_SET_LSB (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_MASK (0x00000002)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_BIT (0x00000002)
+
+#define CG_SET_RAKE_CORE_CG_CON_SET_LSB (0)
+#define CG_SET_RAKE_CORE_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_CORE_CG_CON_SET_MASK (0x00000001)
+#define CG_SET_RAKE_CORE_CG_CON_SET_BIT (0x00000001)
+
+#define CG_CLR_RESERVED7_LSB (2)
+#define CG_CLR_RESERVED7_WIDTH (30)
+#define CG_CLR_RESERVED7_MASK (0xFFFFFFFC)
+
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_LSB (1)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_MASK (0x00000002)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_BIT (0x00000002)
+
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_LSB (0)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_MASK (0x00000001)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_BIT (0x00000001)
+
+#define CG_CON_1X_RESERVED8_LSB (2)
+#define CG_CON_1X_RESERVED8_WIDTH (30)
+#define CG_CON_1X_RESERVED8_MASK (0xFFFFFFFC)
+
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_LSB (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_MASK (0x00000002)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_BIT (0x00000002)
+
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_LSB (0)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_MASK (0x00000001)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_BIT (0x00000001)
+
+#define CG_SET_1X_RESERVED9_LSB (2)
+#define CG_SET_1X_RESERVED9_WIDTH (30)
+#define CG_SET_1X_RESERVED9_MASK (0xFFFFFFFC)
+
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_LSB (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_MASK (0x00000002)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_BIT (0x00000002)
+
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_LSB (0)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_MASK (0x00000001)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_BIT (0x00000001)
+
+#define CG_CLR_1X_RESERVED10_LSB (2)
+#define CG_CLR_1X_RESERVED10_WIDTH (30)
+#define CG_CLR_1X_RESERVED10_MASK (0xFFFFFFFC)
+
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_LSB (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_MASK (0x00000002)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_BIT (0x00000002)
+
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_LSB (0)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_MASK (0x00000001)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_BIT (0x00000001)
+
+#define CG_CON_DO_RESERVED11_LSB (2)
+#define CG_CON_DO_RESERVED11_WIDTH (30)
+#define CG_CON_DO_RESERVED11_MASK (0xFFFFFFFC)
+
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_LSB (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_MASK (0x00000002)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_BIT (0x00000002)
+
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_LSB (0)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_MASK (0x00000001)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_BIT (0x00000001)
+
+#define CG_SET_DO_RESERVED12_LSB (2)
+#define CG_SET_DO_RESERVED12_WIDTH (30)
+#define CG_SET_DO_RESERVED12_MASK (0xFFFFFFFC)
+
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_LSB (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_MASK (0x00000002)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_BIT (0x00000002)
+
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_LSB (0)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_MASK (0x00000001)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_BIT (0x00000001)
+
+#define CG_CLR_DO_RESERVED13_LSB (2)
+#define CG_CLR_DO_RESERVED13_WIDTH (30)
+#define CG_CLR_DO_RESERVED13_MASK (0xFFFFFFFC)
+
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_LSB (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_MASK (0x00000002)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_BIT (0x00000002)
+
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_LSB (0)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_MASK (0x00000001)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_BIT (0x00000001)
+
+#define CG_CON_COMB_RESERVED14_LSB (2)
+#define CG_CON_COMB_RESERVED14_WIDTH (30)
+#define CG_CON_COMB_RESERVED14_MASK (0xFFFFFFFC)
+
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_LSB (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_MASK (0x00000002)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_BIT (0x00000002)
+
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_LSB (0)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_MASK (0x00000001)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_BIT (0x00000001)
+
+#define AXI_BUS_CFG_RESERVED15_LSB (5)
+#define AXI_BUS_CFG_RESERVED15_WIDTH (27)
+#define AXI_BUS_CFG_RESERVED15_MASK (0xFFFFFFE0)
+
+#define AXI_BUS_CFG_SAMP_SEL_LSB (4)
+#define AXI_BUS_CFG_SAMP_SEL_WIDTH (1)
+#define AXI_BUS_CFG_SAMP_SEL_MASK (0x00000010)
+#define AXI_BUS_CFG_SAMP_SEL_BIT (0x00000010)
+
+#define AXI_BUS_CFG_SLV_SYNC_SEL_LSB (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_MASK (0x0000000C)
+
+#define AXI_BUS_CFG_MST_SYNC_SEL_LSB (0)
+#define AXI_BUS_CFG_MST_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_MST_SYNC_SEL_MASK (0x00000003)
+
+#define RAKE_PM_CHK_RAKE_PM_CHK_LSB (0)
+#define RAKE_PM_CHK_RAKE_PM_CHK_WIDTH (32)
+#define RAKE_PM_CHK_RAKE_PM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_DM_CHK_RAKE_DM_CHK_LSB (0)
+#define RAKE_DM_CHK_RAKE_DM_CHK_WIDTH (32)
+#define RAKE_DM_CHK_RAKE_DM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_LSB (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_MASK (0x00000002)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_BIT (0x00000002)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_LSB (0)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_MASK (0x00000001)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_BIT (0x00000001)
+
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_LSB (0)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_WIDTH (32)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_LSB (0)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_WIDTH (32)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_LSB (0)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_WIDTH (32)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_LSB (0)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_WIDTH (32)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_LSB (0)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_WIDTH (4)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_MASK (0x0000000F)
+
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_LSB (0)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_WIDTH (32)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_MASK (0xFFFFFFFF)
+
+
+#endif /*#ifndef _CPH_RAKESYS_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_95.h b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_95.h
new file mode 100644
index 0000000..0d88fc0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_95.h
@@ -0,0 +1,367 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RAKESYS_GLB_CON_REG_H_
+#define _CPH_RAKESYS_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RAKESYS_GLOBAL_CON_REG_BASE (0xAC200000)
+
+#define RAKESYS_GLOBAL_CON_end (RAKESYS_GLOBAL_CON_REG_BASE + 0x90 + 1*4)
+
+
+
+#define RAKE_PWR_AWARE ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x0))
+#define CG_CON ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x4))
+#define CG_SET ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x8))
+#define CG_CLR ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xC))
+#define CG_CON_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x10))
+#define CG_SET_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x14))
+#define CG_CLR_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x18))
+#define CG_CON_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x20))
+#define CG_SET_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x24))
+#define CG_CLR_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x28))
+#define CG_CON_COMB ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x30))
+#define AXI_BUS_CFG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x40))
+#define RAKE_PM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x50))
+#define RAKE_DM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x54))
+#define RAKE_CLKCNT_CTRL ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x60))
+#define RAKE_CK_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x64))
+#define RAKE_IC_DIV3_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x68))
+#define RAKE_IC_32X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x6C))
+#define RAKE_IC_8X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x70))
+#define RAKE_DBGBUS_MUX ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x80))
+#define RAKE_DUMMY_REG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x90))
+
+
+#define RAKE_PWR_AWARE_RESERVED4_LSB (21)
+#define RAKE_PWR_AWARE_RESERVED4_WIDTH (11)
+#define RAKE_PWR_AWARE_RESERVED4_MASK (0xFFE00000)
+
+#define RAKE_PWR_AWARE_RESERVED3_LSB (20)
+#define RAKE_PWR_AWARE_RESERVED3_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED3_MASK (0x00100000)
+#define RAKE_PWR_AWARE_RESERVED3_BIT (0x00100000)
+
+#define RAKE_PWR_AWARE_BUS_ATB_LSB (19)
+#define RAKE_PWR_AWARE_BUS_ATB_WIDTH (1)
+#define RAKE_PWR_AWARE_BUS_ATB_MASK (0x00080000)
+#define RAKE_PWR_AWARE_BUS_ATB_BIT (0x00080000)
+
+#define RAKE_PWR_AWARE_RESERVED2_LSB (14)
+#define RAKE_PWR_AWARE_RESERVED2_WIDTH (5)
+#define RAKE_PWR_AWARE_RESERVED2_MASK (0x0007C000)
+
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_LSB (13)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_MASK (0x00002000)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_BIT (0x00002000)
+
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_LSB (12)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_MASK (0x00001000)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_BIT (0x00001000)
+
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_LSB (11)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_MASK (0x00000800)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_BIT (0x00000800)
+
+#define RAKE_PWR_AWARE_RESERVED1_LSB (10)
+#define RAKE_PWR_AWARE_RESERVED1_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED1_MASK (0x00000400)
+#define RAKE_PWR_AWARE_RESERVED1_BIT (0x00000400)
+
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_LSB (9)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_MASK (0x00000200)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_BIT (0x00000200)
+
+#define RAKE_PWR_AWARE_RAKE_LOADER_LSB (8)
+#define RAKE_PWR_AWARE_RAKE_LOADER_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOADER_MASK (0x00000100)
+#define RAKE_PWR_AWARE_RAKE_LOADER_BIT (0x00000100)
+
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_LSB (7)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_MASK (0x00000080)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_BIT (0x00000080)
+
+#define RAKE_PWR_AWARE_RAKE_BRIF_LSB (6)
+#define RAKE_PWR_AWARE_RAKE_BRIF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_BRIF_MASK (0x00000040)
+#define RAKE_PWR_AWARE_RAKE_BRIF_BIT (0x00000040)
+
+#define RAKE_PWR_AWARE_RESERVED0_LSB (5)
+#define RAKE_PWR_AWARE_RESERVED0_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED0_MASK (0x00000020)
+#define RAKE_PWR_AWARE_RESERVED0_BIT (0x00000020)
+
+#define RAKE_PWR_AWARE_RAKE_EXT_LSB (4)
+#define RAKE_PWR_AWARE_RAKE_EXT_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_EXT_MASK (0x00000010)
+#define RAKE_PWR_AWARE_RAKE_EXT_BIT (0x00000010)
+
+#define RAKE_PWR_AWARE_RAKE_DESP_LSB (3)
+#define RAKE_PWR_AWARE_RAKE_DESP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESP_MASK (0x00000008)
+#define RAKE_PWR_AWARE_RAKE_DESP_BIT (0x00000008)
+
+#define RAKE_PWR_AWARE_RAKE_DESIG_LSB (2)
+#define RAKE_PWR_AWARE_RAKE_DESIG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESIG_MASK (0x00000004)
+#define RAKE_PWR_AWARE_RAKE_DESIG_BIT (0x00000004)
+
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_LSB (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_MASK (0x00000002)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_BIT (0x00000002)
+
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_LSB (0)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_MASK (0x00000001)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_BIT (0x00000001)
+
+#define CG_CON_RESERVED5_LSB (2)
+#define CG_CON_RESERVED5_WIDTH (30)
+#define CG_CON_RESERVED5_MASK (0xFFFFFFFC)
+
+#define CG_CON_RAKE_BRIF_CG_CON_LSB (1)
+#define CG_CON_RAKE_BRIF_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_BRIF_CG_CON_MASK (0x00000002)
+#define CG_CON_RAKE_BRIF_CG_CON_BIT (0x00000002)
+
+#define CG_CON_RAKE_CORE_CG_CON_LSB (0)
+#define CG_CON_RAKE_CORE_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_CORE_CG_CON_MASK (0x00000001)
+#define CG_CON_RAKE_CORE_CG_CON_BIT (0x00000001)
+
+#define CG_SET_RESERVED6_LSB (2)
+#define CG_SET_RESERVED6_WIDTH (30)
+#define CG_SET_RESERVED6_MASK (0xFFFFFFFC)
+
+#define CG_SET_RAKE_BRIF_CG_CON_SET_LSB (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_MASK (0x00000002)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_BIT (0x00000002)
+
+#define CG_SET_RAKE_CORE_CG_CON_SET_LSB (0)
+#define CG_SET_RAKE_CORE_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_CORE_CG_CON_SET_MASK (0x00000001)
+#define CG_SET_RAKE_CORE_CG_CON_SET_BIT (0x00000001)
+
+#define CG_CLR_RESERVED7_LSB (2)
+#define CG_CLR_RESERVED7_WIDTH (30)
+#define CG_CLR_RESERVED7_MASK (0xFFFFFFFC)
+
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_LSB (1)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_MASK (0x00000002)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_BIT (0x00000002)
+
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_LSB (0)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_MASK (0x00000001)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_BIT (0x00000001)
+
+#define CG_CON_1X_RESERVED8_LSB (2)
+#define CG_CON_1X_RESERVED8_WIDTH (30)
+#define CG_CON_1X_RESERVED8_MASK (0xFFFFFFFC)
+
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_LSB (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_MASK (0x00000002)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_BIT (0x00000002)
+
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_LSB (0)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_MASK (0x00000001)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_BIT (0x00000001)
+
+#define CG_SET_1X_RESERVED9_LSB (2)
+#define CG_SET_1X_RESERVED9_WIDTH (30)
+#define CG_SET_1X_RESERVED9_MASK (0xFFFFFFFC)
+
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_LSB (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_MASK (0x00000002)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_BIT (0x00000002)
+
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_LSB (0)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_MASK (0x00000001)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_BIT (0x00000001)
+
+#define CG_CLR_1X_RESERVED10_LSB (2)
+#define CG_CLR_1X_RESERVED10_WIDTH (30)
+#define CG_CLR_1X_RESERVED10_MASK (0xFFFFFFFC)
+
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_LSB (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_MASK (0x00000002)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_BIT (0x00000002)
+
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_LSB (0)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_MASK (0x00000001)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_BIT (0x00000001)
+
+#define CG_CON_DO_RESERVED11_LSB (2)
+#define CG_CON_DO_RESERVED11_WIDTH (30)
+#define CG_CON_DO_RESERVED11_MASK (0xFFFFFFFC)
+
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_LSB (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_MASK (0x00000002)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_BIT (0x00000002)
+
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_LSB (0)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_MASK (0x00000001)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_BIT (0x00000001)
+
+#define CG_SET_DO_RESERVED12_LSB (2)
+#define CG_SET_DO_RESERVED12_WIDTH (30)
+#define CG_SET_DO_RESERVED12_MASK (0xFFFFFFFC)
+
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_LSB (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_MASK (0x00000002)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_BIT (0x00000002)
+
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_LSB (0)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_MASK (0x00000001)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_BIT (0x00000001)
+
+#define CG_CLR_DO_RESERVED13_LSB (2)
+#define CG_CLR_DO_RESERVED13_WIDTH (30)
+#define CG_CLR_DO_RESERVED13_MASK (0xFFFFFFFC)
+
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_LSB (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_MASK (0x00000002)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_BIT (0x00000002)
+
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_LSB (0)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_MASK (0x00000001)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_BIT (0x00000001)
+
+#define CG_CON_COMB_RESERVED14_LSB (2)
+#define CG_CON_COMB_RESERVED14_WIDTH (30)
+#define CG_CON_COMB_RESERVED14_MASK (0xFFFFFFFC)
+
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_LSB (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_MASK (0x00000002)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_BIT (0x00000002)
+
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_LSB (0)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_MASK (0x00000001)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_BIT (0x00000001)
+
+#define AXI_BUS_CFG_RESERVED15_LSB (5)
+#define AXI_BUS_CFG_RESERVED15_WIDTH (27)
+#define AXI_BUS_CFG_RESERVED15_MASK (0xFFFFFFE0)
+
+#define AXI_BUS_CFG_SAMP_SEL_LSB (4)
+#define AXI_BUS_CFG_SAMP_SEL_WIDTH (1)
+#define AXI_BUS_CFG_SAMP_SEL_MASK (0x00000010)
+#define AXI_BUS_CFG_SAMP_SEL_BIT (0x00000010)
+
+#define AXI_BUS_CFG_SLV_SYNC_SEL_LSB (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_MASK (0x0000000C)
+
+#define AXI_BUS_CFG_MST_SYNC_SEL_LSB (0)
+#define AXI_BUS_CFG_MST_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_MST_SYNC_SEL_MASK (0x00000003)
+
+#define RAKE_PM_CHK_RAKE_PM_CHK_LSB (0)
+#define RAKE_PM_CHK_RAKE_PM_CHK_WIDTH (32)
+#define RAKE_PM_CHK_RAKE_PM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_DM_CHK_RAKE_DM_CHK_LSB (0)
+#define RAKE_DM_CHK_RAKE_DM_CHK_WIDTH (32)
+#define RAKE_DM_CHK_RAKE_DM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_LSB (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_MASK (0x00000002)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_BIT (0x00000002)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_LSB (0)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_MASK (0x00000001)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_BIT (0x00000001)
+
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_LSB (0)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_WIDTH (32)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_LSB (0)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_WIDTH (32)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_LSB (0)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_WIDTH (32)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_LSB (0)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_WIDTH (32)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_LSB (0)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_WIDTH (4)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_MASK (0x0000000F)
+
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_LSB (0)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_WIDTH (32)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_MASK (0xFFFFFFFF)
+
+
+#endif /*#ifndef _CPH_RAKESYS_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_97.h b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_97.h
new file mode 100644
index 0000000..267e6c2
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrakesysglbconreg_97.h
@@ -0,0 +1,504 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RAKESYS_GLB_CON_REG_H_
+#define _CPH_RAKESYS_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RAKESYS_GLOBAL_CON_REG_BASE (0xACE00000)
+
+
+#define RAKESYS_GLOBAL_CON_end (RAKESYS_GLOBAL_CON_REG_BASE + 0xc0 + 1*4)
+
+
+
+
+#define RAKE_PWR_AWARE ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x0))
+#define CG_CON ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x4))
+#define CG_SET ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x8))
+#define CG_CLR ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xC))
+#define CG_CON_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x10))
+#define CG_SET_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x14))
+#define CG_CLR_1X ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x18))
+#define CG_CON_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x20))
+#define CG_SET_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x24))
+#define CG_CLR_DO ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x28))
+#define CG_CON_COMB ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x30))
+#define CG_CON_RES ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x34))
+#define CG_SET_RES ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x38))
+#define CG_CLR_RES ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x3C))
+#define AXI_BUS_CFG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x40))
+#define RAKE_PM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x50))
+#define RAKE_DM_CHK ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x54))
+#define RAKE_CLKCNT_CTRL ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x60))
+#define RAKE_CK_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x64))
+#define RAKE_IC_DIV3_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x68))
+#define RAKE_IC_32X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x6C))
+#define RAKE_IC_8X_CLKCNT ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x70))
+#define RAKE_DBGBUS_MUX ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x80))
+#define RAKE_DUMMY_REG ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0x90))
+#define RAKE_CPU_SW_RESET ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xa0))
+#define AXI2SRAM_STATUS ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xb0))
+#define SCQ_AXI2SRAM_BFABLE_EN ((APBADDR32)(RAKESYS_GLOBAL_CON_REG_BASE + 0xc0))
+
+
+#define RAKE_PWR_AWARE_RESERVED4_LSB (21)
+#define RAKE_PWR_AWARE_RESERVED4_WIDTH (11)
+#define RAKE_PWR_AWARE_RESERVED4_MASK (0xFFE00000)
+
+#define RAKE_PWR_AWARE_RESERVED3_LSB (20)
+#define RAKE_PWR_AWARE_RESERVED3_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED3_MASK (0x00100000)
+#define RAKE_PWR_AWARE_RESERVED3_BIT (0x00100000)
+
+#define RAKE_PWR_AWARE_BUS_ATB_LSB (19)
+#define RAKE_PWR_AWARE_BUS_ATB_WIDTH (1)
+#define RAKE_PWR_AWARE_BUS_ATB_MASK (0x00080000)
+#define RAKE_PWR_AWARE_BUS_ATB_BIT (0x00080000)
+
+#define RAKE_PWR_AWARE_RESERVED2_LSB (14)
+#define RAKE_PWR_AWARE_RESERVED2_WIDTH (5)
+#define RAKE_PWR_AWARE_RESERVED2_MASK (0x0007C000)
+
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_LSB (13)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_MASK (0x00002000)
+#define RAKE_PWR_AWARE_RAKE_AXI_BUS_BIT (0x00002000)
+
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_LSB (12)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_MASK (0x00001000)
+#define RAKE_PWR_AWARE_RAKE_LOGTOP_BIT (0x00001000)
+
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_LSB (11)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_MASK (0x00000800)
+#define RAKE_PWR_AWARE_RAKE_DSPLOG_BIT (0x00000800)
+
+#define RAKE_PWR_AWARE_RESERVED1_LSB (10)
+#define RAKE_PWR_AWARE_RESERVED1_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED1_MASK (0x00000400)
+#define RAKE_PWR_AWARE_RESERVED1_BIT (0x00000400)
+
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_LSB (9)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_MASK (0x00000200)
+#define RAKE_PWR_AWARE_RAKE_R2B_DMA_BIT (0x00000200)
+
+#define RAKE_PWR_AWARE_RAKE_LOADER_LSB (8)
+#define RAKE_PWR_AWARE_RAKE_LOADER_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_LOADER_MASK (0x00000100)
+#define RAKE_PWR_AWARE_RAKE_LOADER_BIT (0x00000100)
+
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_LSB (7)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_MASK (0x00000080)
+#define RAKE_PWR_AWARE_RAKE_INST_DEC_BIT (0x00000080)
+
+#define RAKE_PWR_AWARE_RAKE_BRIF_LSB (6)
+#define RAKE_PWR_AWARE_RAKE_BRIF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_BRIF_MASK (0x00000040)
+#define RAKE_PWR_AWARE_RAKE_BRIF_BIT (0x00000040)
+
+#define RAKE_PWR_AWARE_RESERVED0_LSB (5)
+#define RAKE_PWR_AWARE_RESERVED0_WIDTH (1)
+#define RAKE_PWR_AWARE_RESERVED0_MASK (0x00000020)
+#define RAKE_PWR_AWARE_RESERVED0_BIT (0x00000020)
+
+#define RAKE_PWR_AWARE_RAKE_EXT_LSB (4)
+#define RAKE_PWR_AWARE_RAKE_EXT_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_EXT_MASK (0x00000010)
+#define RAKE_PWR_AWARE_RAKE_EXT_BIT (0x00000010)
+
+#define RAKE_PWR_AWARE_RAKE_DESP_LSB (3)
+#define RAKE_PWR_AWARE_RAKE_DESP_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESP_MASK (0x00000008)
+#define RAKE_PWR_AWARE_RAKE_DESP_BIT (0x00000008)
+
+#define RAKE_PWR_AWARE_RAKE_DESIG_LSB (2)
+#define RAKE_PWR_AWARE_RAKE_DESIG_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_DESIG_MASK (0x00000004)
+#define RAKE_PWR_AWARE_RAKE_DESIG_BIT (0x00000004)
+
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_LSB (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_MASK (0x00000002)
+#define RAKE_PWR_AWARE_RAKE_CPICH_ACC_BIT (0x00000002)
+
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_LSB (0)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_WIDTH (1)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_MASK (0x00000001)
+#define RAKE_PWR_AWARE_RAKE_ACC_BUS_INTF_BIT (0x00000001)
+
+#define CG_CON_RESERVED5_LSB (3)
+#define CG_CON_RESERVED5_WIDTH (29)
+#define CG_CON_RESERVED5_MASK (0xFFFFFFF8)
+
+#define CG_CON_RAKE_MEM_CG_CON_LSB (2)
+#define CG_CON_RAKE_MEM_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_MEM_CG_CON_MASK (0x00000004)
+#define CG_CON_RAKE_MEM_CG_CON_BIT (0x00000004)
+
+#define CG_CON_RAKE_BRIF_CG_CON_LSB (1)
+#define CG_CON_RAKE_BRIF_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_BRIF_CG_CON_MASK (0x00000002)
+#define CG_CON_RAKE_BRIF_CG_CON_BIT (0x00000002)
+
+#define CG_CON_RAKE_CORE_CG_CON_LSB (0)
+#define CG_CON_RAKE_CORE_CG_CON_WIDTH (1)
+#define CG_CON_RAKE_CORE_CG_CON_MASK (0x00000001)
+#define CG_CON_RAKE_CORE_CG_CON_BIT (0x00000001)
+
+#define CG_SET_RESERVED6_LSB (3)
+#define CG_SET_RESERVED6_WIDTH (29)
+#define CG_SET_RESERVED6_MASK (0xFFFFFFF8)
+
+#define CG_SET_RAKE_MEM_CG_CON_SET_LSB (2)
+#define CG_SET_RAKE_MEM_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_MEM_CG_CON_SET_MASK (0x00000004)
+#define CG_SET_RAKE_MEM_CG_CON_SET_BIT (0x00000004)
+
+#define CG_SET_RAKE_BRIF_CG_CON_SET_LSB (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_MASK (0x00000002)
+#define CG_SET_RAKE_BRIF_CG_CON_SET_BIT (0x00000002)
+
+#define CG_SET_RAKE_CORE_CG_CON_SET_LSB (0)
+#define CG_SET_RAKE_CORE_CG_CON_SET_WIDTH (1)
+#define CG_SET_RAKE_CORE_CG_CON_SET_MASK (0x00000001)
+#define CG_SET_RAKE_CORE_CG_CON_SET_BIT (0x00000001)
+
+#define CG_CLR_RESERVED7_LSB (3)
+#define CG_CLR_RESERVED7_WIDTH (29)
+#define CG_CLR_RESERVED7_MASK (0xFFFFFFF8)
+
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_LSB (2)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_MASK (0x00000004)
+#define CG_CLR_RAKE_BRIF_CG_CON_CLR_BIT (0x00000004)
+
+#define CG_CLR_rake_brif_cg_con_clr_LSB (1)
+#define CG_CLR_rake_brif_cg_con_clr_WIDTH (1)
+#define CG_CLR_rake_brif_cg_con_clr_MASK (0x00000002)
+#define CG_CLR_rake_brif_cg_con_clr_BIT (0x00000002)
+
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_LSB (0)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_WIDTH (1)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_MASK (0x00000001)
+#define CG_CLR_RAKE_CORE_CG_CON_CLR_BIT (0x00000001)
+
+#define CG_CON_1X_RESERVED8_LSB (3)
+#define CG_CON_1X_RESERVED8_WIDTH (29)
+#define CG_CON_1X_RESERVED8_MASK (0xFFFFFFF8)
+
+#define CG_CON_1X_RAKE_MEM_CG_CON_1X_LSB (2)
+#define CG_CON_1X_RAKE_MEM_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_MEM_CG_CON_1X_MASK (0x00000004)
+#define CG_CON_1X_RAKE_MEM_CG_CON_1X_BIT (0x00000004)
+
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_LSB (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_MASK (0x00000002)
+#define CG_CON_1X_RAKE_BRIF_CG_CON_1X_BIT (0x00000002)
+
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_LSB (0)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_WIDTH (1)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_MASK (0x00000001)
+#define CG_CON_1X_RAKE_CORE_CG_CON_1X_BIT (0x00000001)
+
+#define CG_SET_1X_RESERVED9_LSB (3)
+#define CG_SET_1X_RESERVED9_WIDTH (29)
+#define CG_SET_1X_RESERVED9_MASK (0xFFFFFFF8)
+
+#define CG_SET_1X_RAKE_MEM_CG_CON_SET_1X_LSB (2)
+#define CG_SET_1X_RAKE_MEM_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_MEM_CG_CON_SET_1X_MASK (0x00000004)
+#define CG_SET_1X_RAKE_MEM_CG_CON_SET_1X_BIT (0x00000004)
+
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_LSB (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_MASK (0x00000002)
+#define CG_SET_1X_RAKE_BRIF_CG_CON_SET_1X_BIT (0x00000002)
+
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_LSB (0)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_WIDTH (1)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_MASK (0x00000001)
+#define CG_SET_1X_RAKE_CORE_CG_CON_SET_1X_BIT (0x00000001)
+
+#define CG_CLR_1X_RESERVED10_LSB (3)
+#define CG_CLR_1X_RESERVED10_WIDTH (29)
+#define CG_CLR_1X_RESERVED10_MASK (0xFFFFFFF8)
+
+#define CG_CLR_1X_RAKE_MEM_CG_CON_CLR_1X_LSB (2)
+#define CG_CLR_1X_RAKE_MEM_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_MEM_CG_CON_CLR_1X_MASK (0x00000004)
+#define CG_CLR_1X_RAKE_MEM_CG_CON_CLR_1X_BIT (0x00000004)
+
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_LSB (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_MASK (0x00000002)
+#define CG_CLR_1X_RAKE_BRIF_CG_CON_CLR_1X_BIT (0x00000002)
+
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_LSB (0)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_WIDTH (1)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_MASK (0x00000001)
+#define CG_CLR_1X_RAKE_CORE_CG_CON_CLR_1X_BIT (0x00000001)
+
+#define CG_CON_DO_RESERVED11_LSB (3)
+#define CG_CON_DO_RESERVED11_WIDTH (29)
+#define CG_CON_DO_RESERVED11_MASK (0xFFFFFFF8)
+
+#define CG_CON_DO_RAKE_MEM_CG_CON_DO_LSB (2)
+#define CG_CON_DO_RAKE_MEM_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_MEM_CG_CON_DO_MASK (0x00000004)
+#define CG_CON_DO_RAKE_MEM_CG_CON_DO_BIT (0x00000004)
+
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_LSB (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_MASK (0x00000002)
+#define CG_CON_DO_RAKE_BRIF_CG_CON_DO_BIT (0x00000002)
+
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_LSB (0)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_WIDTH (1)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_MASK (0x00000001)
+#define CG_CON_DO_RAKE_CORE_CG_CON_DO_BIT (0x00000001)
+
+#define CG_SET_DO_RESERVED12_LSB (3)
+#define CG_SET_DO_RESERVED12_WIDTH (29)
+#define CG_SET_DO_RESERVED12_MASK (0xFFFFFFF8)
+
+#define CG_SET_DO_RAKE_MEM_CG_CON_SET_DO_LSB (2)
+#define CG_SET_DO_RAKE_MEM_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_MEM_CG_CON_SET_DO_MASK (0x00000004)
+#define CG_SET_DO_RAKE_MEM_CG_CON_SET_DO_BIT (0x00000004)
+
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_LSB (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_MASK (0x00000002)
+#define CG_SET_DO_RAKE_BRIF_CG_CON_SET_DO_BIT (0x00000002)
+
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_LSB (0)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_WIDTH (1)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_MASK (0x00000001)
+#define CG_SET_DO_RAKE_CORE_CG_CON_SET_DO_BIT (0x00000001)
+
+#define CG_CLR_DO_RESERVED13_LSB (3)
+#define CG_CLR_DO_RESERVED13_WIDTH (29)
+#define CG_CLR_DO_RESERVED13_MASK (0xFFFFFFF8)
+
+#define CG_CLR_DO_RAKE_MEM_CG_CON_CLR_DO_LSB (2)
+#define CG_CLR_DO_RAKE_MEM_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_MEM_CG_CON_CLR_DO_MASK (0x00000004)
+#define CG_CLR_DO_RAKE_MEM_CG_CON_CLR_DO_BIT (0x00000004)
+
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_LSB (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_MASK (0x00000002)
+#define CG_CLR_DO_RAKE_BRIF_CG_CON_CLR_DO_BIT (0x00000002)
+
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_LSB (0)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_WIDTH (1)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_MASK (0x00000001)
+#define CG_CLR_DO_RAKE_CORE_CG_CON_CLR_DO_BIT (0x00000001)
+
+#define CG_CON_COMB_RESERVED14_LSB (3)
+#define CG_CON_COMB_RESERVED14_WIDTH (29)
+#define CG_CON_COMB_RESERVED14_MASK (0xFFFFFFF8)
+
+
+#define CG_CON_COMB_RAKE_MEM_CG_CON_COMB_LSB (2)
+#define CG_CON_COMB_RAKE_MEM_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_MEM_CG_CON_COMB_MASK (0x00000004)
+#define CG_CON_COMB_RAKE_MEM_CG_CON_COMB_BIT (0x00000004)
+
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_LSB (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_MASK (0x00000002)
+#define CG_CON_COMB_RAKE_BRIF_CG_CON_COMB_BIT (0x00000002)
+
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_LSB (0)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_WIDTH (1)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_MASK (0x00000001)
+#define CG_CON_COMB_RAKE_CORE_CG_CON_COMB_BIT (0x00000001)
+
+#define CG_CON_RES_RESERVED15_LSB (3)
+#define CG_CON_RES_RESERVED15_WIDTH (29)
+#define CG_CON_RES_RESERVED15_MASK (0xFFFFFFF8)
+
+#define CG_CON_RES_RAKE_MEM_CG_CON_RES_LSB (2)
+#define CG_CON_RES_RAKE_MEM_CG_CON_RES_WIDTH (1)
+#define CG_CON_RES_RAKE_MEM_CG_CON_RES_MASK (0x00000004)
+#define CG_CON_RES_RAKE_MEM_CG_CON_RES_BIT (0x00000004)
+
+#define CG_CON_RES_RAKE_BRIF_CG_CON_RES_LSB (1)
+#define CG_CON_RES_RAKE_BRIF_CG_CON_RES_WIDTH (1)
+#define CG_CON_RES_RAKE_BRIF_CG_CON_RES_MASK (0x00000002)
+#define CG_CON_RES_RAKE_BRIF_CG_CON_RES_BIT (0x00000002)
+
+#define CG_CON_RES_RAKE_CORE_CG_CON_RES_LSB (0)
+#define CG_CON_RES_RAKE_CORE_CG_CON_RES_WIDTH (1)
+#define CG_CON_RES_RAKE_CORE_CG_CON_RES_MASK (0x00000001)
+#define CG_CON_RES_RAKE_CORE_CG_CON_RES_BIT (0x00000001)
+
+#define CG_SET_RES_RESERVED16_LSB (3)
+#define CG_SET_RES_RESERVED16_WIDTH (29)
+#define CG_SET_RES_RESERVED16_MASK (0xFFFFFFF8)
+
+#define CG_SET_RES_RAKE_MEM_CG_CON_SET_RES_LSB (2)
+#define CG_SET_RES_RAKE_MEM_CG_CON_SET_RES_WIDTH (1)
+#define CG_SET_RES_RAKE_MEM_CG_CON_SET_RES_MASK (0x00000004)
+#define CG_SET_RES_RAKE_MEM_CG_CON_SET_RES_BIT (0x00000004)
+
+#define CG_SET_RES_RAKE_BRIF_CG_CON_SET_RES_LSB (1)
+#define CG_SET_RES_RAKE_BRIF_CG_CON_SET_RES_WIDTH (1)
+#define CG_SET_RES_RAKE_BRIF_CG_CON_SET_RES_MASK (0x00000002)
+#define CG_SET_RES_RAKE_BRIF_CG_CON_SET_RES_BIT (0x00000002)
+
+
+#define CG_SET_RES_RAKE_CORE_CG_CON_SET_RES_LSB (0)
+#define CG_SET_RES_RAKE_CORE_CG_CON_SET_RES_WIDTH (1)
+#define CG_SET_RES_RAKE_CORE_CG_CON_SET_RES_MASK (0x00000001)
+#define CG_SET_RES_RAKE_CORE_CG_CON_SET_RES_BIT (0x00000001)
+
+#define CG_CLR_RES_RESERVED17_LSB (3)
+#define CG_CLR_RES_RESERVED17_WIDTH (29)
+#define CG_CLR_RES_RESERVED17_MASK (0xFFFFFFF8)
+
+#define CG_CLR_RES_RAKE_MEM_CG_CON_CLR_RES_LSB (2)
+#define CG_CLR_RES_RAKE_MEM_CG_CON_CLR_RES_WIDTH (1)
+#define CG_CLR_RES_RAKE_MEM_CG_CON_CLR_RES_MASK (0x00000004)
+#define CG_CLR_RES_RAKE_MEM_CG_CON_CLR_RES_BIT (0x00000004)
+
+#define CG_CLR_RES_RAKE_BRIF_CG_CON_CLR_RES_LSB (1)
+#define CG_CLR_RES_RAKE_BRIF_CG_CON_CLR_RES_WIDTH (1)
+#define CG_CLR_RES_RAKE_BRIF_CG_CON_CLR_RES_MASK (0x00000002)
+#define CG_CLR_RES_RAKE_BRIF_CG_CON_CLR_RES_BIT (0x00000002)
+
+#define CG_CLR_RES_RAKE_CORE_CG_CON_CLR_RES_LSB (0)
+#define CG_CLR_RES_RAKE_CORE_CG_CON_CLR_RES_WIDTH (1)
+#define CG_CLR_RES_RAKE_CORE_CG_CON_CLR_RES_MASK (0x00000001)
+#define CG_CLR_RES_RAKE_CORE_CG_CON_CLR_RES_BIT (0x00000001)
+
+#define AXI_BUS_CFG_RESERVED18_LSB (5)
+#define AXI_BUS_CFG_RESERVED18_WIDTH (27)
+#define AXI_BUS_CFG_RESERVED18_MASK (0xFFFFFFE0)
+
+#define AXI_BUS_CFG_SAMP_SEL_LSB (4)
+#define AXI_BUS_CFG_SAMP_SEL_WIDTH (1)
+#define AXI_BUS_CFG_SAMP_SEL_MASK (0x00000010)
+#define AXI_BUS_CFG_SAMP_SEL_BIT (0x00000010)
+
+#define AXI_BUS_CFG_SLV_SYNC_SEL_LSB (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_SLV_SYNC_SEL_MASK (0x0000000C)
+
+#define AXI_BUS_CFG_MST_SYNC_SEL_LSB (0)
+#define AXI_BUS_CFG_MST_SYNC_SEL_WIDTH (2)
+#define AXI_BUS_CFG_MST_SYNC_SEL_MASK (0x00000003)
+
+#define RAKE_PM_CHK_RAKE_PM_CHK_LSB (0)
+#define RAKE_PM_CHK_RAKE_PM_CHK_WIDTH (32)
+#define RAKE_PM_CHK_RAKE_PM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_DM_CHK_RAKE_DM_CHK_LSB (0)
+#define RAKE_DM_CHK_RAKE_DM_CHK_WIDTH (32)
+#define RAKE_DM_CHK_RAKE_DM_CHK_MASK (0xFFFFFFFF)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_LSB (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_MASK (0x00000002)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_DUMP_BIT (0x00000002)
+
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_LSB (0)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_WIDTH (1)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_MASK (0x00000001)
+#define RAKE_CLKCNT_CTRL_RAKE_CLKCNT_CLR_BIT (0x00000001)
+
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_LSB (0)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_WIDTH (32)
+#define RAKE_CK_CLKCNT_RAKE_CK_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_LSB (0)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_WIDTH (32)
+#define RAKE_IC_DIV3_CLKCNT_RAKE_IC_DIV3_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_LSB (0)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_WIDTH (32)
+#define RAKE_IC_32X_CLKCNT_RAKE_IC_32X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_LSB (0)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_WIDTH (32)
+#define RAKE_IC_8X_CLKCNT_RAKE_IC_8X_CLKCNT_MASK (0xFFFFFFFF)
+
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_LSB (0)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_WIDTH (4)
+#define RAKE_DBGBUS_MUX_RAKE_DBGBUS_MUX_MASK (0x0000000F)
+
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_LSB (0)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_WIDTH (32)
+#define RAKE_DUMMY_REG_RAKE_DUMMY_REG_MASK (0xFFFFFFFF)
+
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_BRIF_LSB (1)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_BRIF_WIDTH (1)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_BRIF_MASK (0x00000002)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_BRIF_BIT (0x00000002)
+
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_MD32_LSB (0)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_MD32_WIDTH (1)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_MD32_MASK (0x00000001)
+#define RAKE_CPU_SW_RESET_RAKE_CPU_SW_RESET_MD32_BIT (0x00000001)
+
+#define AXI2SRAM_STATUS_AXI2SRAM_STATUS_LSB (0)
+#define AXI2SRAM_STATUS_AXI2SRAM_STATUS_WIDTH (32)
+#define AXI2SRAM_STATUS_AXI2SRAM_STATUS_MASK (0xFFFFFFFF)
+
+#define SCQ_AXI2SRAM_BFABLE_EN_SCQ_AXI2SRAM_BFABLE_EN_REG_LSB (0)
+#define SCQ_AXI2SRAM_BFABLE_EN_SCQ_AXI2SRAM_BFABLE_EN_REG_WIDTH (1)
+#define SCQ_AXI2SRAM_BFABLE_EN_SCQ_AXI2SRAM_BFABLE_EN_REG_MASK (0x00000001)
+#define SCQ_AXI2SRAM_BFABLE_EN_SCQ_AXI2SRAM_BFABLE_EN_REG_BIT (0x00000001)
+
+
+
+#endif //#ifndef _CPH_RAKESYS_GLB_CON_REG_H_
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrtttxtimerreg.h b/mcu/interface/l1/cl1/common/HW/cphrtttxtimerreg.h
new file mode 100644
index 0000000..e8037fc
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrtttxtimerreg.h
@@ -0,0 +1,341 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RTT_TX_TIMER_H_
+#define _CPH_RTT_TX_TIMER_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define DFE_W_TTR_REG_BASE (0xA61A0000)
+#else
+#define DFE_W_TTR_REG_BASE (0xA8180000)
+#endif
+
+#define C1X_TTR_SR_OFFSET_0 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0000))
+#define C1X_TTR_SR_OFFSET_1 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0004))
+#define C1X_TTR_FORCE_TTR_MODE ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0010))
+#define C1X_TTR_PHASE_ACC_ADJ ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0020))
+#define C1X_TTR_U_TX_DATA_OFFSET ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0024))
+#define C1X_TTR_RX_TX_LOG ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0050))
+#define C1X_TTR_RX_TIME_MON0 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0054))
+#define C1X_TTR_RX_TIME_MON1 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0058))
+#define C1X_TTR_TX_TIME_MON0 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x005C))
+#define C1X_TTR_TX_TIME_MON1 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0060))
+#define C1X_TTR_TX_TIME_MON2 ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0064))
+#define C1X_TTR_CNT_ADJ ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0068))
+
+#define C1X_TTR_FRAME_OFFSET ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0070))
+#define C1X_TTR_TXRXDELAY ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0074))
+#define C1X_TTR_RA_DLY ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0078))
+
+#define C1X_TTR_CRP_WIN_ON ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0080))
+#define C1X_TTR_CRP_WIN_OFF ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0084))
+
+#if defined(__MD93__)||defined(__MD95__)
+#define C1X_TTR_TXDFE_WIN_ON ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0088))
+#define C1X_TTR_TXDFE_WIN_OFF ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x008C))
+#endif
+
+#define C1X_TTR_TXCRP_FIFO_WIN_ON ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0090))
+#define C1X_TTR_TXCRP_FIFO_WIN_OFF ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0094))
+
+#if defined(__MD93__)||defined(__MD95__)
+#define C1X_TTR_TXDAC_WIN_ON ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0098))
+#define C1X_TTR_TXDAC_WIN_OFF ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x009C))
+#endif
+
+#define C1X_TTR_TXBRP_STR ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x00C0))
+#define C1X_TTR_TXCRP_STR ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x00C4))
+#define C1X_TTR_KS_STR ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x00C8))
+
+#define C1X_TTR_FRM_BOUNDARY ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x00D0))
+#define C1X_TTR_DEBUG_STR ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x00F0))
+
+#if (!defined(__MD93__))&&(!defined(__MD95__))
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0100))
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0110))
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0114))
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0118))
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x011C))
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0120))
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x0124))
+#define C1X_TX_TIMER_TTR_WIN_DBG ((APBADDR32)(DFE_W_TTR_REG_BASE + 0x012c))
+#endif
+
+#define USE_RX_SR_OffSET_LSB (20)
+#define USE_RX_SR_OffSET_WIDTH (1)
+#define USE_RX_SR_OffSET_MASK (0x00100000)
+#define USE_RX_SR_OffSET_BIT (0x00100000)
+
+#define SR_OFFSET_LSB (0)
+#define SR_OFFSET_WIDTH (16)
+#define SR_OFFSET_MASK (0x0000FFFF)
+
+#define TX_CNT_WO_TX_DELAY_LSB (0)
+#define TX_CNT_WO_TX_DELAY_WIDTH (20)
+#define TX_CNT_WO_TX_DELAY_MASK (0x000FFFFF)
+
+#define TX_CNT_W_TX_DELAY_LSB (0)
+#define TX_CNT_W_TX_DELAY_WIDTH (20)
+#define TX_CNT_W_TX_DELAY_MASK (0x000FFFFF)
+
+#define FRAME_OFFSET_LSB (0)
+#define FRAME_OFFSET_WIDTH (20)
+#define FRAME_OFFSET_MASK (0x000FFFFF)
+
+#define TXRXDELAY_LSB (0)
+#define TXRXDELAY_WIDTH (20)
+#define TXRXDELAY_MASK (0x000FFFFF)
+
+#define RA_DLY_LSB (0)
+#define RA_DLY_WIDTH (20)
+#define RA_DLY_MASK (0x000FFFFF)
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXDFE_WIN_ON_CMPR_ON_LSB (28)
+#define TXDFE_WIN_ON_CMPR_ON_WIDTH (1)
+#define TXDFE_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define TXDFE_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define TXDFE_WIN_ON_TRG_EN_LSB (27)
+#define TXDFE_WIN_ON_TRG_EN_WIDTH (1)
+#define TXDFE_WIN_ON_TRG_EN_MASK (0x08000000)
+#define TXDFE_WIN_ON_TRG_EN_BIT (0x08000000)
+
+#define TXDFE_WIN_ON_SYSTEM_TIME_LSB (0)
+#define TXDFE_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define TXDFE_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TXDFE_WIN_OFF_CMPR_ON_LSB (28)
+#define TXDFE_WIN_OFF_CMPR_ON_WIDTH (1)
+#define TXDFE_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define TXDFE_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define TXDFE_WIN_OFF_TRG_EN_LSB (27)
+#define TXDFE_WIN_OFF_TRG_EN_WIDTH (1)
+#define TXDFE_WIN_OFF_TRG_EN_MASK (0x08000000)
+#define TXDFE_WIN_OFF_TRG_EN_BIT (0x08000000)
+
+#define TXDFE_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define TXDFE_WIN_OFF_SYSTEM_TIME_WIDTH (20)
+#define TXDFE_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+#endif
+
+#define TXCRP_FIFO_WIN_ON_CMPR_ON_LSB (28)
+#define TXCRP_FIFO_WIN_ON_CMPR_ON_WIDTH (1)
+#define TXCRP_FIFO_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define TXCRP_FIFO_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define TXCRP_FIFO_WIN_ON_TRG_EN_LSB (27)
+#define TXCRP_FIFO_WIN_ON_TRG_EN_WIDTH (1)
+#define TXCRP_FIFO_WIN_ON_TRG_EN_MASK (0x08000000)
+#define TXCRP_FIFO_WIN_ON_TRG_EN_BIT (0x08000000)
+
+#define TXCRP_FIFO_WIN_ON_SYSTEM_TIME_LSB (0)
+#define TXCRP_FIFO_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define TXCRP_FIFO_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TXCRP_FIFO_WIN_OFF_CMPR_ON_LSB (28)
+#define TXCRP_FIFO_WIN_OFF_CMPR_ON_WIDTH (1)
+#define TXCRP_FIFO_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define TXCRP_FIFO_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define TXCRP_FIFO_WIN_OFF_TRG_EN_LSB (27)
+#define TXCRP_FIFO_WIN_OFF_TRG_EN_WIDTH (1)
+#define TXCRP_FIFO_WIN_OFF_TRG_EN_MASK (0x08000000)
+#define TXCRP_FIFO_WIN_OFF_TRG_EN_BIT (0x08000000)
+
+#define TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_WIDTH (20)
+#define TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXDAC_WIN_ON_CMPR_ON_LSB (28)
+#define TXDAC_WIN_ON_CMPR_ON_WIDTH (1)
+#define TXDAC_WIN_ON_CMPR_ON_MASK (0x10000000)
+#define TXDAC_WIN_ON_CMPR_ON_BIT (0x10000000)
+
+#define TXDAC_WIN_ON_TRG_EN_LSB (27)
+#define TXDAC_WIN_ON_TRG_EN_WIDTH (1)
+#define TXDAC_WIN_ON_TRG_EN_MASK (0x08000000)
+#define TXDAC_WIN_ON_TRG_EN_BIT (0x08000000)
+
+#define TXDAC_WIN_ON_SYSTEM_TIME_LSB (0)
+#define TXDAC_WIN_ON_SYSTEM_TIME_WIDTH (20)
+#define TXDAC_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TXDAC_WIN_OFF_CMPR_ON_LSB (28)
+#define TXDAC_WIN_OFF_CMPR_ON_WIDTH (1)
+#define TXDAC_WIN_OFF_CMPR_ON_MASK (0x10000000)
+#define TXDAC_WIN_OFF_CMPR_ON_BIT (0x10000000)
+
+#define TXDAC_WIN_OFF_TRG_EN_LSB (27)
+#define TXDAC_WIN_OFF_TRG_EN_WIDTH (1)
+#define TXDAC_WIN_OFF_TRG_EN_MASK (0x08000000)
+#define TXDAC_WIN_OFF_TRG_EN_BIT (0x08000000)
+
+#define TXDAC_WIN_OFF_SYSTEM_TIME_LSB (0)
+#define TXDAC_WIN_OFF_SYSTEM_TIME_WIDTH (20)
+#define TXDAC_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+#endif
+
+#define TXBRP_STR_CMPR_ON_LSB (28)
+#define TXBRP_STR_CMPR_ON_WIDTH (1)
+#define TXBRP_STR_CMPR_ON_MASK (0x10000000)
+#define TXBRP_STR_CMPR_ON_BIT (0x10000000)
+
+#define TXBRP_STR_SINGLE_TRIGGER_LSB (27)
+#define TXBRP_STR_SINGLE_TRIGGER_WIDTH (1)
+#define TXBRP_STR_SINGLE_TRIGGER_MASK (0x08000000)
+#define TXBRP_STR_SINGLE_TRIGGER_BIT (0x08000000)
+
+#define TXBRP_STR_SYSTEM_TIME_LSB (0)
+#define TXBRP_STR_SYSTEM_TIME_WIDTH (20)
+#define TXBRP_STR_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define TXCRP_STR_CMPR_ON_LSB (28)
+#define TXCRP_STR_CMPR_ON_WIDTH (1)
+#define TXCRP_STR_CMPR_ON_MASK (0x10000000)
+#define TXCRP_STR_CMPR_ON_BIT (0x10000000)
+
+#define TXCRP_STR_SINGLE_TRIGGER_LSB (27)
+#define TXCRP_STR_SINGLE_TRIGGER_WIDTH (1)
+#define TXCRP_STR_SINGLE_TRIGGER_MASK (0x08000000)
+#define TXCRP_STR_SINGLE_TRIGGER_BIT (0x08000000)
+
+#define TXCRP_STR_SYSTEM_TIME_LSB (0)
+#define TXCRP_STR_SYSTEM_TIME_WIDTH (20)
+#define TXCRP_STR_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define KS_STR_CMPR_ON_LSB (28)
+#define KS_STR_CMPR_ON_WIDTH (1)
+#define KS_STR_CMPR_ON_MASK (0x10000000)
+#define KS_STR_CMPR_ON_BIT (0x10000000)
+
+#define KS_STR_SINGLE_TRIGGER_LSB (27)
+#define KS_STR_SINGLE_TRIGGER_WIDTH (1)
+#define KS_STR_SINGLE_TRIGGER_MASK (0x08000000)
+#define KS_STR_SINGLE_TRIGGER_BIT (0x08000000)
+
+#define KS_STR_AUTO_TRIGGER_LSB (20)
+#define KS_STR_AUTO_TRIGGER_WIDTH (2)
+#define KS_STR_AUTO_TRIGGER_MASK (0x00300000)
+
+#define KS_STR_SYSTEM_TIME_LSB (0)
+#define KS_STR_SYSTEM_TIME_WIDTH (20)
+#define KS_STR_SYSTEM_TIME_MASK (0x000FFFFF)
+#if (!defined(__MD93__))&&(!defined(__MD95__))
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_LSB (1)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_MASK (0x00000002)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_BIT (0x00000002)
+
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_MASK (0x00000001)
+#define C1X_TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_BIT (0x00000001)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_LSB (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_MASK (0x00000002)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_BIT (0x00000002)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_MASK (0x00000001)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_BIT (0x00000001)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_WIDTH (32)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_MASK (0xFFFFFFFF)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_LSB (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_MASK (0x00000002)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_BIT (0x00000002)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_MASK (0x00000001)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_BIT (0x00000001)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_WIDTH (32)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_MASK (0xFFFFFFFF)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_LSB (28)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_MASK (0x10000000)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_BIT (0x10000000)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_LSB (27)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_MASK (0x08000000)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_BIT (0x08000000)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_WIDTH (20)
+#define C1X_TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_LSB (28)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_MASK (0x10000000)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_BIT (0x10000000)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_LSB (27)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_MASK (0x08000000)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_BIT (0x08000000)
+
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_WIDTH (20)
+#define C1X_TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_MASK (0x000FFFFF)
+
+#define C1X_TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_LSB (0)
+#define C1X_TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_WIDTH (1)
+#define C1X_TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_MASK (0x00000001)
+#define C1X_TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_BIT (0x00000001)
+#endif
+
+#endif //#ifndef _CPH_RTT_TX_TIMER_H_
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxbrpbusconfig.h b/mcu/interface/l1/cl1/common/HW/cphrxbrpbusconfig.h
new file mode 100644
index 0000000..a017072
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxbrpbusconfig.h
@@ -0,0 +1,405 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXBRP_BUS_CONFIG_H_
+#define _CPH_RXBRP_BUS_CONFIG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD95__)
+#define RXBRP_BUS_CONFIG_REG_BASE (0xAD160000)
+#else
+#define RXBRP_BUS_CONFIG_REG_BASE (0xAC960000)
+#endif
+
+#define RXBRP_BUS_CONFIG_end (RXBRP_BUS_CONFIG_REG_BASE + 0x00a4 + 1*4)
+
+
+
+#define RXBRP_BUS_CONFIG0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0000))
+#define RXBRP_BUS_CONFIG1 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0004))
+#define RXBRP_BUS_CONFIG2 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0008))
+#define RXBRP_BUS_CONFIG3 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x000c))
+#define RXBRP_BUS_CONFIG4 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0010))
+#define RXBRP_BUS_CONFIG5 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0014))
+#define RXBRP_BUS_CONFIG6 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0018))
+#define RXBRP_BUS_CONFIG7 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x001c))
+#define RXBRP_BUS_CONFIG8 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0020))
+#define RXBRP_BUS_CONFIG9 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0024))
+#define RXBRP_BUS_CONFIG10 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0028))
+#define RXBRP_BUS_STATUS0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0030))
+#define RXBRP_BUS_STATUS1 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0034))
+#define RXBRP_BUS_STATUS2 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0038))
+#define RXBRP_BUS_CONFIG11 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0040))
+#define RXBRP_BUS_CONFIG12 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0044))
+#define RXBRP_BUS_CONFIG13 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0048))
+#define RXBRP_BUS_CONFIG14 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x004c))
+#define RXBRP_SLV_BUS_CONFIG0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0080))
+#define RXBRP_SLV_BUS_STATUS0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x00a0))
+#define RXBRP_SLV_BUS_STATUS1 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x00a4))
+
+
+#define RXBRP_BUS_CONFIG0_FLUSH_THRE_LSB (30)
+#define RXBRP_BUS_CONFIG0_FLUSH_THRE_WIDTH (2)
+#define RXBRP_BUS_CONFIG0_FLUSH_THRE_MASK (0xC0000000)
+
+#define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_LSB (29)
+#define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_MASK (0x20000000)
+#define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_BIT (0x20000000)
+
+#define RXBRP_BUS_CONFIG0_MI_QOS_ON_LSB (28)
+#define RXBRP_BUS_CONFIG0_MI_QOS_ON_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_MI_QOS_ON_MASK (0x10000000)
+#define RXBRP_BUS_CONFIG0_MI_QOS_ON_BIT (0x10000000)
+
+#define RXBRP_BUS_CONFIG0_CG_DISABLE_LSB (27)
+#define RXBRP_BUS_CONFIG0_CG_DISABLE_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_CG_DISABLE_MASK (0x08000000)
+#define RXBRP_BUS_CONFIG0_CG_DISABLE_BIT (0x08000000)
+
+#define RXBRP_BUS_CONFIG0_DMA_MODE_LSB (26)
+#define RXBRP_BUS_CONFIG0_DMA_MODE_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_DMA_MODE_MASK (0x04000000)
+#define RXBRP_BUS_CONFIG0_DMA_MODE_BIT (0x04000000)
+
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_LSB (25)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_MASK (0x02000000)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_BIT (0x02000000)
+
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_LSB (24)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_MASK (0x01000000)
+#define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_BIT (0x01000000)
+
+#define RXBRP_BUS_CONFIG0_SPLIT_DIS_LSB (18)
+#define RXBRP_BUS_CONFIG0_SPLIT_DIS_WIDTH (6)
+#define RXBRP_BUS_CONFIG0_SPLIT_DIS_MASK (0x00FC0000)
+
+#define RXBRP_BUS_CONFIG0_CHNL_DISABLE_LSB (12)
+#define RXBRP_BUS_CONFIG0_CHNL_DISABLE_WIDTH (6)
+#define RXBRP_BUS_CONFIG0_CHNL_DISABLE_MASK (0x0003F000)
+
+#define RXBRP_BUS_CONFIG0_PRE_HIGH_PRIORITY_LSB (6)
+#define RXBRP_BUS_CONFIG0_PRE_HIGH_PRIORITY_WIDTH (6)
+#define RXBRP_BUS_CONFIG0_PRE_HIGH_PRIORITY_MASK (0x00000FC0)
+
+#define RXBRP_BUS_CONFIG0_HIGH_PRIORITY_LSB (0)
+#define RXBRP_BUS_CONFIG0_HIGH_PRIORITY_WIDTH (6)
+#define RXBRP_BUS_CONFIG0_HIGH_PRIORITY_MASK (0x0000003F)
+
+#define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_LSB (30)
+#define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_MASK (0x40000000)
+#define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_BIT (0x40000000)
+
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_LSB (29)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_MASK (0x20000000)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_BIT (0x20000000)
+
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_LSB (28)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_MASK (0x10000000)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_BIT (0x10000000)
+
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_LSB (27)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_MASK (0x08000000)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_BIT (0x08000000)
+
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_LSB (26)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_MASK (0x04000000)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_BIT (0x04000000)
+
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_LSB (25)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_MASK (0x02000000)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_BIT (0x02000000)
+
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_LSB (24)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_MASK (0x01000000)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_BIT (0x01000000)
+
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_LSB (23)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_MASK (0x00800000)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_BIT (0x00800000)
+
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_LSB (22)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_MASK (0x00400000)
+#define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_BIT (0x00400000)
+
+#define RXBRP_BUS_CONFIG1_RG_DBG_SEL_LSB (12)
+#define RXBRP_BUS_CONFIG1_RG_DBG_SEL_WIDTH (8)
+#define RXBRP_BUS_CONFIG1_RG_DBG_SEL_MASK (0x000FF000)
+
+#define RXBRP_BUS_CONFIG1_SLV_SYNC_SEL_LSB (10)
+#define RXBRP_BUS_CONFIG1_SLV_SYNC_SEL_WIDTH (2)
+#define RXBRP_BUS_CONFIG1_SLV_SYNC_SEL_MASK (0x00000C00)
+
+#define RXBRP_BUS_CONFIG1_MST_SYNC_SEL_LSB (8)
+#define RXBRP_BUS_CONFIG1_MST_SYNC_SEL_WIDTH (2)
+#define RXBRP_BUS_CONFIG1_MST_SYNC_SEL_MASK (0x00000300)
+
+#define RXBRP_BUS_CONFIG1_RXBRP_TOP_DBG_SEL_LSB (2)
+#define RXBRP_BUS_CONFIG1_RXBRP_TOP_DBG_SEL_WIDTH (4)
+#define RXBRP_BUS_CONFIG1_RXBRP_TOP_DBG_SEL_MASK (0x0000003C)
+
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_LSB (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_MASK (0x00000002)
+#define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_BIT (0x00000002)
+
+#define RXBRP_BUS_CONFIG1_HPRI_DIS_LSB (0)
+#define RXBRP_BUS_CONFIG1_HPRI_DIS_WIDTH (1)
+#define RXBRP_BUS_CONFIG1_HPRI_DIS_MASK (0x00000001)
+#define RXBRP_BUS_CONFIG1_HPRI_DIS_BIT (0x00000001)
+
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_LSB (23)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_MASK (0x00800000)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_BIT (0x00800000)
+
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_LSB (22)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_MASK (0x00400000)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_BIT (0x00400000)
+
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_LSB (21)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_MASK (0x00200000)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_BIT (0x00200000)
+
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_LSB (20)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_MASK (0x00100000)
+#define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_BIT (0x00100000)
+
+#define RXBRP_BUS_CONFIG2_RG_ERROR_FLAG_SELECT_LSB (18)
+#define RXBRP_BUS_CONFIG2_RG_ERROR_FLAG_SELECT_WIDTH (2)
+#define RXBRP_BUS_CONFIG2_RG_ERROR_FLAG_SELECT_MASK (0x000C0000)
+
+#define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_LSB (17)
+#define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_MASK (0x00020000)
+#define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_BIT (0x00020000)
+
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_LSB (16)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_MASK (0x00010000)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_BIT (0x00010000)
+
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_LSB (15)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_MASK (0x00008000)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_BIT (0x00008000)
+
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_LSB (14)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_MASK (0x00004000)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_BIT (0x00004000)
+
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_LSB (13)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_MASK (0x00002000)
+#define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_BIT (0x00002000)
+
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_LSB (12)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_MASK (0x00001000)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_BIT (0x00001000)
+
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_LSB (11)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_MASK (0x00000800)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_BIT (0x00000800)
+
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_LSB (10)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_MASK (0x00000400)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_BIT (0x00000400)
+
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_LSB (9)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_MASK (0x00000200)
+#define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_BIT (0x00000200)
+
+#define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_LSB (8)
+#define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_MASK (0x00000100)
+#define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_BIT (0x00000100)
+
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_LSB (7)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_MASK (0x00000080)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_BIT (0x00000080)
+
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_LSB (6)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_MASK (0x00000040)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_BIT (0x00000040)
+
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_LSB (5)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_MASK (0x00000020)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_BIT (0x00000020)
+
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_LSB (4)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_MASK (0x00000010)
+#define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_BIT (0x00000010)
+
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_LSB (3)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_MASK (0x00000008)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_BIT (0x00000008)
+
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_LSB (2)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_MASK (0x00000004)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_BIT (0x00000004)
+
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_LSB (1)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_MASK (0x00000002)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_BIT (0x00000002)
+
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_LSB (0)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_WIDTH (1)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_MASK (0x00000001)
+#define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_BIT (0x00000001)
+
+#define RXBRP_BUS_CONFIG3_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R_LSB (0)
+#define RXBRP_BUS_CONFIG3_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R_WIDTH (32)
+#define RXBRP_BUS_CONFIG3_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG4_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R1_LSB (0)
+#define RXBRP_BUS_CONFIG4_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R1_WIDTH (32)
+#define RXBRP_BUS_CONFIG4_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R1_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG5_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W_LSB (0)
+#define RXBRP_BUS_CONFIG5_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W_WIDTH (32)
+#define RXBRP_BUS_CONFIG5_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG6_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W1_LSB (0)
+#define RXBRP_BUS_CONFIG6_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W1_WIDTH (32)
+#define RXBRP_BUS_CONFIG6_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W1_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG7_AUTO_BW_LIMIT_THRESHOLD_R_SRT_THRO_LSB (0)
+#define RXBRP_BUS_CONFIG7_AUTO_BW_LIMIT_THRESHOLD_R_SRT_THRO_WIDTH (32)
+#define RXBRP_BUS_CONFIG7_AUTO_BW_LIMIT_THRESHOLD_R_SRT_THRO_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG8_AUTO_BW_LIMIT_THRESHOLD_W_SRT_THRO_LSB (0)
+#define RXBRP_BUS_CONFIG8_AUTO_BW_LIMIT_THRESHOLD_W_SRT_THRO_WIDTH (32)
+#define RXBRP_BUS_CONFIG8_AUTO_BW_LIMIT_THRESHOLD_W_SRT_THRO_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG9_AUTO_BW_LIMIT_THRESHOLD_R1_SRT_THRO_LSB (0)
+#define RXBRP_BUS_CONFIG9_AUTO_BW_LIMIT_THRESHOLD_R1_SRT_THRO_WIDTH (32)
+#define RXBRP_BUS_CONFIG9_AUTO_BW_LIMIT_THRESHOLD_R1_SRT_THRO_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG10_AUTO_BW_LIMIT_THRESHOLD_W1_SRT_THRO_LSB (0)
+#define RXBRP_BUS_CONFIG10_AUTO_BW_LIMIT_THRESHOLD_W1_SRT_THRO_WIDTH (32)
+#define RXBRP_BUS_CONFIG10_AUTO_BW_LIMIT_THRESHOLD_W1_SRT_THRO_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_STATUS0_STA0_LSB (0)
+#define RXBRP_BUS_STATUS0_STA0_WIDTH (32)
+#define RXBRP_BUS_STATUS0_STA0_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_STATUS1_STA1_LSB (0)
+#define RXBRP_BUS_STATUS1_STA1_WIDTH (32)
+#define RXBRP_BUS_STATUS1_STA1_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_STATUS2_STA2_LSB (0)
+#define RXBRP_BUS_STATUS2_STA2_WIDTH (32)
+#define RXBRP_BUS_STATUS2_STA2_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG11_AUTO_BW_LIMIT_THRESHOLD_R_BW_STATUS_LSB (0)
+#define RXBRP_BUS_CONFIG11_AUTO_BW_LIMIT_THRESHOLD_R_BW_STATUS_WIDTH (32)
+#define RXBRP_BUS_CONFIG11_AUTO_BW_LIMIT_THRESHOLD_R_BW_STATUS_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG12_AUTO_BW_LIMIT_THRESHOLD_W_BW_STATUS_LSB (0)
+#define RXBRP_BUS_CONFIG12_AUTO_BW_LIMIT_THRESHOLD_W_BW_STATUS_WIDTH (32)
+#define RXBRP_BUS_CONFIG12_AUTO_BW_LIMIT_THRESHOLD_W_BW_STATUS_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG13_AUTO_BW_LIMIT_THRESHOLD_R1_BW_STATUS_LSB (0)
+#define RXBRP_BUS_CONFIG13_AUTO_BW_LIMIT_THRESHOLD_R1_BW_STATUS_WIDTH (32)
+#define RXBRP_BUS_CONFIG13_AUTO_BW_LIMIT_THRESHOLD_R1_BW_STATUS_MASK (0xFFFFFFFF)
+
+#define RXBRP_BUS_CONFIG14_AUTO_BW_LIMIT_THRESHOLD_W1_BW_STATUS_LSB (0)
+#define RXBRP_BUS_CONFIG14_AUTO_BW_LIMIT_THRESHOLD_W1_BW_STATUS_WIDTH (32)
+#define RXBRP_BUS_CONFIG14_AUTO_BW_LIMIT_THRESHOLD_W1_BW_STATUS_MASK (0xFFFFFFFF)
+
+#define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_LSB (5)
+#define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_WIDTH (1)
+#define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_MASK (0x00000020)
+#define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_BIT (0x00000020)
+
+#define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_LSB (4)
+#define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_WIDTH (1)
+#define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_MASK (0x00000010)
+#define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_BIT (0x00000010)
+
+#define RXBRP_SLV_BUS_CONFIG0_SLV_SYNC_SEL_LSB (2)
+#define RXBRP_SLV_BUS_CONFIG0_SLV_SYNC_SEL_WIDTH (2)
+#define RXBRP_SLV_BUS_CONFIG0_SLV_SYNC_SEL_MASK (0x0000000C)
+
+#define RXBRP_SLV_BUS_CONFIG0_MST_SYNC_SEL_LSB (0)
+#define RXBRP_SLV_BUS_CONFIG0_MST_SYNC_SEL_WIDTH (2)
+#define RXBRP_SLV_BUS_CONFIG0_MST_SYNC_SEL_MASK (0x00000003)
+
+#define RXBRP_SLV_BUS_STATUS0_STA0_LSB (0)
+#define RXBRP_SLV_BUS_STATUS0_STA0_WIDTH (32)
+#define RXBRP_SLV_BUS_STATUS0_STA0_MASK (0xFFFFFFFF)
+
+#define RXBRP_SLV_BUS_STATUS1_STA1_LSB (0)
+#define RXBRP_SLV_BUS_STATUS1_STA1_WIDTH (1)
+#define RXBRP_SLV_BUS_STATUS1_STA1_MASK (0x00000001)
+#define RXBRP_SLV_BUS_STATUS1_STA1_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_RXBRP_BUS_CONFIG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg.h b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg.h
new file mode 100644
index 0000000..d83011c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphrxbrpglbconreg_93.h"
+#elif defined(__MD95__)
+#include "cphrxbrpglbconreg_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphrxbrpglbconreg_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_93.h b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_93.h
new file mode 100644
index 0000000..c3dc23a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_93.h
@@ -0,0 +1,1401 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXBRP_GLB_CON_REG_H_
+#define _CPH_RXBRP_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_GLOBAL_CON_REG_BASE (0xAD110000)
+
+#define RXBRP_GLOBAL_CON_end (RXBRP_GLOBAL_CON_REG_BASE + 0x0184 + 1*4)
+
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0000))
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0004))
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0008))
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x000C))
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0010))
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0014))
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0018))
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x001C))
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0020))
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0024))
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0028))
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x002C))
+#define RXBRP_GLOBAL_L_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0030))
+#define RXBRP_GLOBAL_WCT_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0034))
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0038))
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x003C))
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0040))
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0044))
+#define RXBRP_GLOBAL_GPIO_EN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0048))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x004C))
+#define RXBRP_GLOBAL_ASSERT_IRQ ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0050))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0054))
+#define RXBRP_GLOBAL_WT_DEBUG ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0058))
+#define RXBRP_GLOBAL_RESERVED_OUT ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x005C))
+#define RXBRP_GLOBAL_RESERVED_IN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0060))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0100))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0104))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0108))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x010C))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0110))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0114))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0118))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x011C))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0120))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0124))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0128))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x012C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0130))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0134))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0138))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x013C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0140))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0144))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0148))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x014C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0150))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0154))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0158))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x015C))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0160))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0164))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0168))
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x016C))
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0170))
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0174))
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0178))
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x017C))
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0180))
+#define RXBRP_GLOBAL_DCM_DBG_SEL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0184))
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_LSB (0)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_WIDTH (1)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_MASK (0x00000001)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_POOL_LSB (3)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_POOL_MASK (0x00000008)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_POOL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_POOL_LSB (3)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_POOL_MASK (0x00000008)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_POOL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_POOL_LSB (3)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_POOL_MASK (0x00000008)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_POOL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_LSB (8)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_LSB (7)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_LSB (11)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_MASK (0x00000800)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_LSB (10)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_MASK (0x00000400)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_LSB (9)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_MASK (0x00000200)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_LSB (8)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_MASK (0x00000100)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_LSB (7)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_MASK (0x00000080)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_LSB (6)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_LSB (5)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_LSB (3)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_MASK (0x00000008)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_LSB (2)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_LSB (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_MASK (0x00000002)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_LSB (0)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_MASK (0x00000001)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_TUR_ASSERT_LSB (5)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_TUR_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_TUR_ASSERT_MASK (0x00000020)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_TUR_ASSERT_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_LSB (4)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_MASK (0x00000010)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_LSB (3)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_MASK (0x00000008)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_LSB (2)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_MASK (0x00000004)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_LSB (0)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_MASK (0x00000001)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_LSB (0)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_WIDTH (4)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_MASK (0x0000000F)
+
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_LSB (0)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_WIDTH (5)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_MASK (0x0000001F)
+
+
+#endif /*_CPH_RXBRP_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_95.h b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_95.h
new file mode 100644
index 0000000..8ef5e4e
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_95.h
@@ -0,0 +1,1430 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXBRP_GLB_CON_REG_H_
+#define _CPH_RXBRP_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_GLOBAL_CON_REG_BASE (0xAD110000)
+
+#define RXBRP_GLOBAL_CON_end (RXBRP_GLOBAL_CON_REG_BASE + 0x0184 + 1*4)
+
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0000))
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0004))
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0008))
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x000C))
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0010))
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0014))
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0018))
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x001C))
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0020))
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0024))
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0028))
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x002C))
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0030))
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0034))
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0038))
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x003C))
+#define RXBRP_GLOBAL_L_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0040))
+#define RXBRP_GLOBAL_WCT_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0044))
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0048))
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x004C))
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0050))
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0054))
+#define RXBRP_GLOBAL_GPIO_EN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0058))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x005C))
+#define RXBRP_GLOBAL_ASSERT_IRQ ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0060))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0064))
+#define RXBRP_GLOBAL_WT_DEBUG ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0068))
+#define RXBRP_GLOBAL_RESERVED_OUT ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x006C))
+#define RXBRP_GLOBAL_RESERVED_IN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0070))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0100))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0104))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0108))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x010C))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0110))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0114))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0118))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x011C))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0120))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0124))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0128))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x012C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0130))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0134))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0138))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x013C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0140))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0144))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0148))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x014C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0150))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0154))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0158))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x015C))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0160))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0164))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0168))
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x016C))
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0170))
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0174))
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0178))
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x017C))
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0180))
+#define RXBRP_GLOBAL_DCM_DBG_SEL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0184))
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_LSB (0)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_WIDTH (1)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_MASK (0x00000001)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_LSB (8)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_LSB (7)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_LSB (11)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_MASK (0x00000800)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_LSB (10)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_MASK (0x00000400)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_LSB (9)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_MASK (0x00000200)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_LSB (8)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_MASK (0x00000100)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_LSB (7)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_MASK (0x00000080)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_LSB (6)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_LSB (5)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_LSB (3)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_MASK (0x00000008)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_LSB (2)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_LSB (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_MASK (0x00000002)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_LSB (0)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_MASK (0x00000001)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_LSB (4)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_MASK (0x00000010)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_LSB (3)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_MASK (0x00000008)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_LSB (2)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_MASK (0x00000004)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_LSB (0)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_MASK (0x00000001)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_LSB (0)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_MASK (0x00000001)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_LSB (0)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_WIDTH (4)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_MASK (0x0000000F)
+
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_LSB (0)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_WIDTH (5)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_MASK (0x0000001F)
+
+
+#endif /*_CPH_RXBRP_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_97.h b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_97.h
new file mode 100644
index 0000000..8fb27bf
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxbrpglbconreg_97.h
@@ -0,0 +1,1430 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXBRP_GLB_CON_REG_H_
+#define _CPH_RXBRP_GLB_CON_REG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXBRP_GLOBAL_CON_REG_BASE (0xAC910000)
+
+#define RXBRP_GLOBAL_CON_end (RXBRP_GLOBAL_CON_REG_BASE + 0x0184 + 1*4)
+
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0000))
+#define RXBRP_GLOBAL_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0004))
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0008))
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x000C))
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0010))
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0014))
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0018))
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x001C))
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0020))
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0024))
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0028))
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x002C))
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0030))
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0034))
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0038))
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x003C))
+#define RXBRP_GLOBAL_L_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0040))
+#define RXBRP_GLOBAL_WCT_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0044))
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0048))
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x004C))
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0050))
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0054))
+#define RXBRP_GLOBAL_GPIO_EN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0058))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x005C))
+#define RXBRP_GLOBAL_ASSERT_IRQ ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0060))
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0064))
+#define RXBRP_GLOBAL_WT_DEBUG ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0068))
+#define RXBRP_GLOBAL_RESERVED_OUT ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x006C))
+#define RXBRP_GLOBAL_RESERVED_IN ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0070))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0100))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0104))
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0108))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x010C))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0110))
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0114))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0118))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x011C))
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0120))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0124))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0128))
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x012C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0130))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0134))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0138))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x013C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0140))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0144))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2 ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0148))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x014C))
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0150))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0154))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0158))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x015C))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0160))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0164))
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0168))
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x016C))
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0170))
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0174))
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0178))
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x017C))
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0180))
+#define RXBRP_GLOBAL_DCM_DBG_SEL ((APBADDR32)(RXBRP_GLOBAL_CON_REG_BASE + 0x0184))
+
+
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_LSB (0)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_WIDTH (1)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_MASK (0x00000001)
+#define RXBRP_GLOBAL_RXBRP_CLOCK_EN_CTRL_RXBRP_FORCE_ON_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_LTE_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_LSB (2)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCTL_ACC_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_LSB (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_MASK (0x00000002)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_WCT_ACC_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_LSB (0)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_CBUS_CLOCK_EN_CTRL_L_ACC_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_CLOCK_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCT_CLOCK_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_LTE_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_FDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_TDD_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_RTT_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_EVDO_WCTL_CLOCK_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_RESET_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_RESET_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_LSB (7)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_SHR_POOL_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_RESET_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_PWR_AWARE_EN_CTRL_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_LSB (13)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_MASK (0x00002000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_POOL_BIT (0x00002000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_PWR_AWARE_EN_CTRL_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_LSB (8)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_SHR_POOL_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_LSB (7)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_BUS_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_LSB (4)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_POOL_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_PWR_AWARE_EN_CTRL_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_LSB (11)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_MASK (0x00000800)
+#define RXBRP_GLOBAL_GPIO_EN_C_EVDO_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_LSB (10)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_MASK (0x00000400)
+#define RXBRP_GLOBAL_GPIO_EN_C_RTT_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_LSB (9)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_MASK (0x00000200)
+#define RXBRP_GLOBAL_GPIO_EN_MAS_BUS_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_LSB (8)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_MASK (0x00000100)
+#define RXBRP_GLOBAL_GPIO_EN_SLV_BUS_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_LSB (7)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_MASK (0x00000080)
+#define RXBRP_GLOBAL_GPIO_EN_L_CBRP_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_LSB (6)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_GPIO_EN_L_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_LSB (5)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_GPIO_EN_W_DRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_GPIO_EN_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_LSB (3)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_MASK (0x00000008)
+#define RXBRP_GLOBAL_GPIO_EN_WT_HARQ_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_LSB (2)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_CVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_LSB (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_MASK (0x00000002)
+#define RXBRP_GLOBAL_GPIO_EN_WCTL_TUR_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_LSB (0)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_MASK (0x00000001)
+#define RXBRP_GLOBAL_GPIO_EN_WTL_HARQ_BUF_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_LSB (4)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_MASK (0x00000010)
+#define RXBRP_GLOBAL_ASSERT_IRQ_L_HARQ_ASSERT_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_LSB (3)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_MASK (0x00000008)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCT_DVIT_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_LSB (2)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_MASK (0x00000004)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TUR_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_LSB (0)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_MASK (0x00000001)
+#define RXBRP_GLOBAL_ASSERT_IRQ_MPU_WCTL_TRACE_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_LSB (0)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_WIDTH (1)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_MASK (0x00000001)
+#define RXBRP_GLOBAL_ASSERT_IRQ_WCT_DMA_ASSERT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_LSB (2)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_MASK (0x00000004)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCT_DVIT_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_LSB (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_MASK (0x00000002)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WTL_HARQ_BUF_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_LSB (0)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_MASK (0x00000001)
+#define RXBRP_GLOBAL_DDR_CLOCK_ENA_STATUS_WCTL_TUR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_LSB (0)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_WIDTH (4)
+#define RXBRP_GLOBAL_WT_DEBUG_TTI_ARBT_MASK (0x0000000F)
+
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_OUT_RESERVED_OUT_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_LSB (0)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_WIDTH (16)
+#define RXBRP_GLOBAL_RESERVED_IN_RESERVED_IN_MASK (0x0000FFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_RSRV_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_DSCH_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_TUR_R99_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU0_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU1_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_VITW_MPU2_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_HSPA_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_START_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_WIDTH (32)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_END_ADR_MASK (0xFFFFFFFF)
+
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_LSB (0)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_WIDTH (1)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_MASK (0x00000001)
+#define RXBRP_GLOBAL_DBRP_HARQ_BUF_LTE_MPU_EN_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_SW_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_SW_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_SW_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_LSB (5)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_MASK (0x00000020)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_REBRP_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_LSB (4)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_MASK (0x00000010)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_RBMAP_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_LSB (2)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_MASK (0x00000004)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_HARQ_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_LSB (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_MASK (0x00000002)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_DCI_PARSER_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_LSB (0)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_WIDTH (1)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_MASK (0x00000001)
+#define RXBRP_GLOBAL_L_DCM_FORCE_IDLE_L_CBRP_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_LSB (12)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_MASK (0x00001000)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_BRP_DMA_BIT (0x00001000)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_LSB (11)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_MASK (0x00000800)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_R99_CTRL_BIT (0x00000800)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_LSB (10)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_MASK (0x00000400)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_CORR_SER_BIT (0x00000400)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_LSB (9)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_MASK (0x00000200)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_EVDO_BIT (0x00000200)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_LSB (8)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_C_RTT_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_LSB (7)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WCT_DVIT_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_LSB (6)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_HARQ_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_LSB (5)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_CDRM_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_LSB (4)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_MASK (0x00000010)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_WT_BCH_BIT (0x00000010)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_LSB (3)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_HSRM_CAL_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_LSB (2)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_TXIF_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_LSB (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_MASK (0x00000002)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_DRM_BIT (0x00000002)
+
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_LSB (0)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_WIDTH (1)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCT_DCM_FORCE_IDLE_W_CORR_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_LSB (8)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_MASK (0x00000100)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_BUS_INTF_BIT (0x00000100)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_LSB (7)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_MASK (0x00000080)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_SLV_BUS_INTF_BIT (0x00000080)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_LSB (6)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_MASK (0x00000040)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TUR_BIT (0x00000040)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_LSB (5)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_MASK (0x00000020)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_TRACE_BIT (0x00000020)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_LSB (3)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_MASK (0x00000008)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_HARQ_BUF_BIT (0x00000008)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_LSB (2)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_MASK (0x00000004)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WCTL_ECTRL_BIT (0x00000004)
+
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_LSB (0)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_WIDTH (1)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_MASK (0x00000001)
+#define RXBRP_GLOBAL_WCTL_DCM_FORCE_IDLE_WTL_CVIT_BIT (0x00000001)
+
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_LSB (0)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_WIDTH (5)
+#define RXBRP_GLOBAL_DCM_DBG_SEL_SEL_MASK (0x0000001F)
+
+
+#endif /*_CPH_RXBRP_GLB_CON_REG_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfe2cs_rxsel.h b/mcu/interface/l1/cl1/common/HW/cphrxdfe2cs_rxsel.h
new file mode 100644
index 0000000..2a928a0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfe2cs_rxsel.h
@@ -0,0 +1,228 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXDFE2CS_RXSEL_REG_97_H_
+#define _CPH_RXDFE2CS_RXSEL_REG_97_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE2CS_RXSEL_REG_BASE (0xA8DB0000)
+
+#define RXDFE2CS_RXSEL_REG_end (RXDFE2CS_RXSEL_REG_BASE + 0x0060 + 1*4)
+
+
+#define C2K1X_CS_SEL_CTRL ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x0))
+#define C2KDO_CS_SEL_CTRL ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x4))
+#define TDD_CS_SEL_CTRL ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x8))
+#define W_CS_SEL_CTRL ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0xC))
+#define NR_CS_DATA_SEL_0 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x10))
+#define NR_CS_DATA_SEL_1 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x14))
+#define NR_CS_TRANS_START_TIMER_CC0 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x18))
+#define NR_CS_TRANS_START_TIMER_CC1 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x1C))
+#define NR_CS_TRANS_START_TIMER_CC2 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x20))
+#define NR_CS_TRANS_START_TIMER_CC3 ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x24))
+#define NR_CS_CTRL ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x28))
+#define RXDFE2CS_NR_SC_GALS_CFG ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x2C))
+#define RXDFE2CS_DBG ((APBADDR32)(RXDFE2CS_RXSEL_REG_BASE + 0x30))
+
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_trans_en_LSB (31)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_trans_en_WIDTH (1)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_trans_en_MASK (0x80000000)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_trans_en_BIT (0x80000000)
+
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_delay_LSB (30)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_delay_WIDTH (1)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_delay_MASK (0x40000000)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_delay_BIT (0x40000000)
+
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_sel_LSB (0)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_sel_WIDTH (5)
+#define C2K1X_CS_SEL_CTRL_c2k1x_cs_data_sel_MASK (0x0000001F)
+
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_trans_en_LSB (31)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_trans_en_WIDTH (1)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_trans_en_MASK (0x80000000)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_trans_en_BIT (0x80000000)
+
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_delay_LSB (30)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_delay_WIDTH (1)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_delay_MASK (0x40000000)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_delay_BIT (0x40000000)
+
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_div_LSB (8)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_div_WIDTH (5)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_div_MASK (0x00001F00)
+
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_main_LSB (0)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_main_WIDTH (5)
+#define C2KDO_CS_SEL_CTRL_c2kdo_cs_data_sel_main_MASK (0x0000001F)
+
+#define TDD_CS_SEL_CTRL_tdd_cs_data_trans_en_LSB (31)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_trans_en_WIDTH (1)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_trans_en_MASK (0x80000000)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_trans_en_BIT (0x80000000)
+
+#define TDD_CS_SEL_CTRL_tdd_cs_data_delay_LSB (0)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_delay_WIDTH (1)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_delay_MASK (0x00000001)
+#define TDD_CS_SEL_CTRL_tdd_cs_data_delay_BIT (0x00000001)
+
+#define W_CS_SEL_CTRL_w_cs_offpch_trans_en_LSB (31)
+#define W_CS_SEL_CTRL_w_cs_offpch_trans_en_WIDTH (1)
+#define W_CS_SEL_CTRL_w_cs_offpch_trans_en_MASK (0x80000000)
+#define W_CS_SEL_CTRL_w_cs_offpch_trans_en_BIT (0x80000000)
+
+#define W_CS_SEL_CTRL_w_cs_data_trans_en_LSB (30)
+#define W_CS_SEL_CTRL_w_cs_data_trans_en_WIDTH (1)
+#define W_CS_SEL_CTRL_w_cs_data_trans_en_MASK (0x40000000)
+#define W_CS_SEL_CTRL_w_cs_data_trans_en_BIT (0x40000000)
+
+#define W_CS_SEL_CTRL_w_cs_offpch_delay_LSB (4)
+#define W_CS_SEL_CTRL_w_cs_offpch_delay_WIDTH (1)
+#define W_CS_SEL_CTRL_w_cs_offpch_delay_MASK (0x00000010)
+#define W_CS_SEL_CTRL_w_cs_offpch_delay_BIT (0x00000010)
+
+#define W_CS_SEL_CTRL_w_cs_data_delay_LSB (0)
+#define W_CS_SEL_CTRL_w_cs_data_delay_WIDTH (1)
+#define W_CS_SEL_CTRL_w_cs_data_delay_MASK (0x00000001)
+#define W_CS_SEL_CTRL_w_cs_data_delay_BIT (0x00000001)
+
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a1_LSB (24)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a1_WIDTH (5)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a1_MASK (0x1F000000)
+
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a0_LSB (16)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a0_WIDTH (5)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c1a0_MASK (0x001F0000)
+
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a1_LSB (8)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a1_WIDTH (5)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a1_MASK (0x00001F00)
+
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a0_LSB (0)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a0_WIDTH (5)
+#define NR_CS_DATA_SEL_0_nr_cs_data_sel_c0a0_MASK (0x0000001F)
+
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a1_LSB (24)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a1_WIDTH (5)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a1_MASK (0x1F000000)
+
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a0_LSB (16)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a0_WIDTH (5)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c3a0_MASK (0x001F0000)
+
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a1_LSB (8)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a1_WIDTH (5)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a1_MASK (0x00001F00)
+
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a0_LSB (0)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a0_WIDTH (5)
+#define NR_CS_DATA_SEL_1_nr_cs_data_sel_c2a0_MASK (0x0000001F)
+
+#define NR_CS_TRANS_START_TIMER_CC0_nr_cs_data_trans_start_timer_cc0_LSB (0)
+#define NR_CS_TRANS_START_TIMER_CC0_nr_cs_data_trans_start_timer_cc0_WIDTH (30)
+#define NR_CS_TRANS_START_TIMER_CC0_nr_cs_data_trans_start_timer_cc0_MASK (0x3FFFFFFF)
+
+#define NR_CS_TRANS_START_TIMER_CC1_nr_cs_data_trans_start_timer_cc1_LSB (0)
+#define NR_CS_TRANS_START_TIMER_CC1_nr_cs_data_trans_start_timer_cc1_WIDTH (30)
+#define NR_CS_TRANS_START_TIMER_CC1_nr_cs_data_trans_start_timer_cc1_MASK (0x3FFFFFFF)
+
+#define NR_CS_TRANS_START_TIMER_CC2_nr_cs_data_trans_start_timer_cc2_LSB (0)
+#define NR_CS_TRANS_START_TIMER_CC2_nr_cs_data_trans_start_timer_cc2_WIDTH (30)
+#define NR_CS_TRANS_START_TIMER_CC2_nr_cs_data_trans_start_timer_cc2_MASK (0x3FFFFFFF)
+
+#define NR_CS_TRANS_START_TIMER_CC3_nr_cs_data_trans_start_timer_cc3_LSB (0)
+#define NR_CS_TRANS_START_TIMER_CC3_nr_cs_data_trans_start_timer_cc3_WIDTH (30)
+#define NR_CS_TRANS_START_TIMER_CC3_nr_cs_data_trans_start_timer_cc3_MASK (0x3FFFFFFF)
+
+#define NR_CS_CTRL_nr_cs_data_trans_en_LSB (31)
+#define NR_CS_CTRL_nr_cs_data_trans_en_WIDTH (1)
+#define NR_CS_CTRL_nr_cs_data_trans_en_MASK (0x80000000)
+#define NR_CS_CTRL_nr_cs_data_trans_en_BIT (0x80000000)
+
+#define NR_CS_CTRL_nr_cs_data_trans_rate_LSB (8)
+#define NR_CS_CTRL_nr_cs_data_trans_rate_WIDTH (1)
+#define NR_CS_CTRL_nr_cs_data_trans_rate_MASK (0x00000100)
+#define NR_CS_CTRL_nr_cs_data_trans_rate_BIT (0x00000100)
+
+#define NR_CS_CTRL_nr_cs_data_iq_swap_LSB (4)
+#define NR_CS_CTRL_nr_cs_data_iq_swap_WIDTH (1)
+#define NR_CS_CTRL_nr_cs_data_iq_swap_MASK (0x00000010)
+#define NR_CS_CTRL_nr_cs_data_iq_swap_BIT (0x00000010)
+
+#define NR_CS_CTRL_nr_cs_data_trans_mode_LSB (0)
+#define NR_CS_CTRL_nr_cs_data_trans_mode_WIDTH (1)
+#define NR_CS_CTRL_nr_cs_data_trans_mode_MASK (0x00000001)
+#define NR_CS_CTRL_nr_cs_data_trans_mode_BIT (0x00000001)
+
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_protect_mode_LSB (4)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_protect_mode_WIDTH (1)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_protect_mode_MASK (0x00000010)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_protect_mode_BIT (0x00000010)
+
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_flush_fifo_mode_LSB (3)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_flush_fifo_mode_WIDTH (1)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_flush_fifo_mode_MASK (0x00000008)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_flush_fifo_mode_BIT (0x00000008)
+
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_mst_sync_sel_LSB (1)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_mst_sync_sel_WIDTH (2)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_mst_sync_sel_MASK (0x00000006)
+
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_disable_mst_cg_LSB (0)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_disable_mst_cg_WIDTH (1)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_disable_mst_cg_MASK (0x00000001)
+#define RXDFE2CS_NR_SC_GALS_CFG_rxdfe2cs_nr_sc_GALS_rg_disable_mst_cg_BIT (0x00000001)
+
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_stimer_LSB (2)
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_stimer_WIDTH (30)
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_stimer_MASK (0xFFFFFFFC)
+
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_flag_LSB (0)
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_flag_WIDTH (1)
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_flag_MASK (0x00000001)
+#define RXDFE2CS_DBG_rxdfe2cs_nr_err_flag_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_RXDFE2CS_RXSEL_REG_97_H_
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfeatimer.h b/mcu/interface/l1/cl1/common/HW/cphrxdfeatimer.h
new file mode 100644
index 0000000..c50bce9
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfeatimer.h
@@ -0,0 +1,91 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RX_DFE_ATTIMER_H_
+#define _CPH_RX_DFE_ATTIMER_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE_ATIMER_REG_BASE (0xA70D0000)
+
+#define RXDFE_ATIMER_end (RXDFE_ATIMER_REG_BASE + 0x00000004 + 1*4)
+
+
+
+#define RG_RXDFE_ATIMER_TRG ((APBADDR32)(RXDFE_ATIMER_REG_BASE + 0x00000000))
+#define RG_RXDFE_ATIMER_RO ((APBADDR32)(RXDFE_ATIMER_REG_BASE + 0x00000004))
+
+
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_trg_LSB (31)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_trg_WIDTH (1)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_trg_MASK (0x80000000)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_trg_BIT (0x80000000)
+
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_stp_LSB (30)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_stp_WIDTH (1)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_stp_MASK (0x40000000)
+#define RG_RXDFE_ATIMER_TRG_atimer_f52m_stp_BIT (0x40000000)
+
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_trg_LSB (16)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_trg_WIDTH (1)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_trg_MASK (0x00010000)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_trg_BIT (0x00010000)
+
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_stp_LSB (15)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_stp_WIDTH (1)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_stp_MASK (0x00008000)
+#define RG_RXDFE_ATIMER_TRG_atimer_f2p17m_stp_BIT (0x00008000)
+
+#define RG_RXDFE_ATIMER_RO_atimer_f52m_status_LSB (31)
+#define RG_RXDFE_ATIMER_RO_atimer_f52m_status_WIDTH (1)
+#define RG_RXDFE_ATIMER_RO_atimer_f52m_status_MASK (0x80000000)
+#define RG_RXDFE_ATIMER_RO_atimer_f52m_status_BIT (0x80000000)
+
+#define RG_RXDFE_ATIMER_RO_atimer_f2p17m_status_LSB (16)
+#define RG_RXDFE_ATIMER_RO_atimer_f2p17m_status_WIDTH (1)
+#define RG_RXDFE_ATIMER_RO_atimer_f2p17m_status_MASK (0x00010000)
+#define RG_RXDFE_ATIMER_RO_atimer_f2p17m_status_BIT (0x00010000)
+
+
+#endif //#ifndef _CPH_RX_DFE_ATTIMER_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfefccaltc.h b/mcu/interface/l1/cl1/common/HW/cphrxdfefccaltc.h
new file mode 100644
index 0000000..9ad21f9
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfefccaltc.h
@@ -0,0 +1,153 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RX_DFE_FCCALTC_H_
+#define _CPH_RX_DFE_FCCALTC_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE_FCCALTC_REG_BASE (0xA70B0000)
+
+#define RXDFE_FCCALTC_end (RXDFE_FCCALTC_REG_BASE + 0x00000A00 + 1*4)
+
+
+
+#define RG_RXDFE_FCCALTC_OFFSET(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000000 + (n)*4)) //n is from 0 to 4
+#define RG_RXDFE_FCCALTC_TQ_SEL(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000200 + (n)*4)) //n is from 0 to 11
+#define RG_RXDFE_FCCALTC_TQ_TRG(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000280 + (n)*4)) //n is from 0 to 11
+#define RG_RXDFE_FCCALTC_TQ_RO(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000300 + (n)*4)) //n is from 0 to 11
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000600))
+#define RG_RXDFE_FCCALTC_LPM_CFG ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000800))
+#define RG_RXDFE_FCCALTC_LPM_RO(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000810 + (n)*4)) //n is from 0 to 1
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000820 + (n)*4)) //n is from 0 to 1
+#define RG_RXDFE_FCCALTC_IRQ ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000A00))
+
+
+#define RG_RXDFE_FCCALTC_OFFSET_offset_2_LSB (16)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_2_WIDTH (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_2_MASK (0x00FF0000)
+
+#define RG_RXDFE_FCCALTC_OFFSET_offset_1_LSB (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_1_WIDTH (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_1_MASK (0x0000FF00)
+
+#define RG_RXDFE_FCCALTC_OFFSET_offset_0_LSB (0)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_0_WIDTH (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_0_MASK (0x000000FF)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_LSB (24)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_WIDTH (2)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_MASK (0x03000000)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_LSB (16)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_WIDTH (5)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_MASK (0x001F0000)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_LSB (8)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_WIDTH (5)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_MASK (0x00001F00)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_LSB (0)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_MASK (0x00000001)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_BIT (0x00000001)
+
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_LSB (31)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_MASK (0x80000000)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_BIT (0x80000000)
+
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_LSB (30)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_MASK (0x40000000)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_BIT (0x40000000)
+
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_LSB (24)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_MASK (0x01000000)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_BIT (0x01000000)
+
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_LSB (0)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_WIDTH (8)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_MASK (0x000000FF)
+
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_LSB (0)
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_WIDTH (12)
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_MASK (0x00000FFF)
+
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_LSB (4)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_WIDTH (1)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_MASK (0x00000010)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_BIT (0x00000010)
+
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_LSB (0)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_WIDTH (4)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_MASK (0x0000000F)
+
+#define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_LSB (0)
+#define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_WIDTH (4)
+#define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_MASK (0x0000000F)
+
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_LSB (16)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_WIDTH (1)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_MASK (0x00010000)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_BIT (0x00010000)
+
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_LSB (0)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_WIDTH (1)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_MASK (0x00000001)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_BIT (0x00000001)
+
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_LSB (16)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_WIDTH (1)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_MASK (0x00010000)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_BIT (0x00010000)
+
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_LSB (0)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_WIDTH (1)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_MASK (0x00000001)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_RX_DFE_FCCALTC_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig.h b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig.h
new file mode 100644
index 0000000..b48d146
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig.h
@@ -0,0 +1,40 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphrxdfesysconfig_93.h"
+#else /*MD95,MD97, after MD97 mybe need update */
+#include "cphrxdfesysconfig_95.h"
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_93.h b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_93.h
new file mode 100644
index 0000000..3b23c5b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_93.h
@@ -0,0 +1,88 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXDEF_SYSCONFIG_H_
+#define _CPH_RXDEF_SYSCONFIG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFESYS_CONFIG_REG_BASE (0xA7010000)
+
+#define RXDFESYS_CONFIG_end (RXDFESYS_CONFIG_REG_BASE + 0x00000180 + 1*4)
+
+
+
+#define RG_RXDFESYS_SW_BCK_CG_EN(n) ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000000 + (n)*4)) //n is from 0 to 23
+#define RG_RXDFESYS_SW_PCK_CG_EN(n) ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000080 + (n)*4)) //n is from 0 to 23
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000100))
+#define RG_RXDFESYS_DDR_ENA_EN ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000180))
+
+
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_LSB (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_WIDTH (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_MASK (0x00000002)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_BIT (0x00000002)
+
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_LSB (0)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_WIDTH (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_MASK (0x00000001)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_RXDEF_SYSCONFIG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_95.h b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_95.h
new file mode 100644
index 0000000..3b23c5b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfesysconfig_95.h
@@ -0,0 +1,88 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RXDEF_SYSCONFIG_H_
+#define _CPH_RXDEF_SYSCONFIG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFESYS_CONFIG_REG_BASE (0xA7010000)
+
+#define RXDFESYS_CONFIG_end (RXDFESYS_CONFIG_REG_BASE + 0x00000180 + 1*4)
+
+
+
+#define RG_RXDFESYS_SW_BCK_CG_EN(n) ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000000 + (n)*4)) //n is from 0 to 23
+#define RG_RXDFESYS_SW_PCK_CG_EN(n) ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000080 + (n)*4)) //n is from 0 to 23
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000100))
+#define RG_RXDFESYS_DDR_ENA_EN ((APBADDR32)(RXDFESYS_CONFIG_REG_BASE + 0x00000180))
+
+
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_BCK_CG_EN_rxdfesys_sw_bck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_PCK_CG_EN_rxdfesys_sw_pck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_LSB (0)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_WIDTH (1)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_MASK (0x00000001)
+#define RG_RXDFESYS_SW_BUS_BCK_CG_EN_rxdfesys_sw_bus_bck_cg_en_BIT (0x00000001)
+
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_LSB (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_WIDTH (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_MASK (0x00000002)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_mas_bus_idle_en_BIT (0x00000002)
+
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_LSB (0)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_WIDTH (1)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_MASK (0x00000001)
+#define RG_RXDFESYS_DDR_ENA_EN_rxdfesys_dma_ddr_clk_ena_en_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_RXDEF_SYSCONFIG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxmmeventgen.h b/mcu/interface/l1/cl1/common/HW/cphrxmmeventgen.h
new file mode 100644
index 0000000..cb42709
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxmmeventgen.h
@@ -0,0 +1,161 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RX_MM_EVENT_GEN_H_
+#define _CPH_RX_MM_EVENT_GEN_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define MM_RX_RF_EVENTGEN_REG_BASE (0x00000000)
+
+#define MM_RX_RF_EVENTGEN_end (MM_RX_RF_EVENTGEN_REG_BASE + 0x2014 + 32*4)
+
+
+
+#define MM_EVENTGEN_LTE_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0000))
+#define MM_EVENTGEN_FDD_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0004))
+#define MM_EVENTGEN_GSM_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0008))
+#define MM_EVENTGEN_BSI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x000C))
+#define MM_EVENTGEN_BSI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0010))
+#define MM_EVENTGEN_BSI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0014 + (n)*4)) //n is from 0 to 31
+#define MM_EVENTGEN_LTE_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1000))
+#define MM_EVENTGEN_FDD_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1004))
+#define MM_EVENTGEN_GSM_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1008))
+#define MM_EVENTGEN_MIPI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x100C))
+#define MM_EVENTGEN_MIPI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1010))
+#define MM_EVENTGEN_MIPI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1014 + (n)*4)) //n is from 0 to 31
+#define MM_EVENTGEN_LTE_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2000))
+#define MM_EVENTGEN_FDD_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2004))
+#define MM_EVENTGEN_GSM_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2008))
+#define MM_EVENTGEN_BPI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x200C))
+#define MM_EVENTGEN_BPI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2010))
+#define MM_EVENTGEN_BPI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2014 + (n)*4)) //n is from 0 to 31
+
+
+#define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_LSB (0)
+#define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_WIDTH (20)
+#define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_MASK (0x000FFFFF)
+
+#define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_LSB (0)
+#define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_WIDTH (16)
+#define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_MASK (0x0000FFFF)
+
+#define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_LSB (0)
+#define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_WIDTH (14)
+#define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_MASK (0x00003FFF)
+
+#define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_LSB (0)
+#define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_WIDTH (32)
+#define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_LSB (0)
+#define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_WIDTH (32)
+#define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_BSI_EVENT_MODE_LSB (29)
+#define MM_EVENTGEN_BSI_EVENT_MODE_WIDTH (3)
+#define MM_EVENTGEN_BSI_EVENT_MODE_MASK (0xE0000000)
+
+#define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_LSB (0)
+#define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_WIDTH (20)
+#define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_MASK (0x000FFFFF)
+
+#define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_LSB (0)
+#define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_WIDTH (20)
+#define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_MASK (0x000FFFFF)
+
+#define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_LSB (0)
+#define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_WIDTH (16)
+#define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_MASK (0x0000FFFF)
+
+#define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_LSB (0)
+#define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_WIDTH (14)
+#define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_MASK (0x00003FFF)
+
+#define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_LSB (0)
+#define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_WIDTH (32)
+#define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_LSB (0)
+#define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_WIDTH (32)
+#define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_MIPI_EVENT_MODE_LSB (29)
+#define MM_EVENTGEN_MIPI_EVENT_MODE_WIDTH (3)
+#define MM_EVENTGEN_MIPI_EVENT_MODE_MASK (0xE0000000)
+
+#define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_LSB (0)
+#define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_WIDTH (20)
+#define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_MASK (0x000FFFFF)
+
+#define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_LSB (0)
+#define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_WIDTH (20)
+#define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_MASK (0x000FFFFF)
+
+#define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_LSB (0)
+#define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_WIDTH (16)
+#define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_MASK (0x0000FFFF)
+
+#define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_LSB (0)
+#define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_WIDTH (14)
+#define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_MASK (0x00003FFF)
+
+#define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_LSB (0)
+#define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_WIDTH (32)
+#define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_LSB (0)
+#define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_WIDTH (32)
+#define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_MASK (0xFFFFFFFF)
+
+#define MM_EVENTGEN_BPI_EVENT_MODE_LSB (29)
+#define MM_EVENTGEN_BPI_EVENT_MODE_WIDTH (3)
+#define MM_EVENTGEN_BPI_EVENT_MODE_MASK (0xE0000000)
+
+#define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_LSB (0)
+#define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_WIDTH (20)
+#define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_MASK (0x000FFFFF)
+
+
+#endif //#ifndef _CPH_RX_MM_EVENT_GEN_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphslpctrl.h b/mcu/interface/l1/cl1/common/HW/cphslpctrl.h
new file mode 100644
index 0000000..7f7d795
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphslpctrl.h
@@ -0,0 +1,211 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHSLPCTRL_H_
+#define _CPHSLPCTRL_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if (defined(__MD93__)||defined(__MD95__))
+#define ST_SM_REG_BASE (0xA60D0000)/*SM REG BASE 93&95*/
+#elif defined(__MD97__) || defined(__MD97P__)
+#define ST_SM_REG_BASE (0xA80D0000)/*SM REG BASE 97*/
+#endif
+
+#define ST_SM_CON(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000000))
+#define ST_SM_PAUSE_TIME(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000004))
+#define ST_SM_STA(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000008))
+#define ST_SM_CFG(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000000C))
+#define ST_SM_START_TIME(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000010))
+#define ST_SM_SW_WAKE_CON(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000014))
+#define ST_SM_STEP_FRAC(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000018))
+#define ST_SM_SYSCNT_F32K_INT(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000001C))
+#define ST_SM_SYSCNT_F32K_FRAC(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000020))
+#define ST_SM_SUPFRM_F32K_L(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000024))
+#define ST_SM_SUPFRM_F32K_H(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000028))
+#define ST_SM_SLEEP_OFFSET(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000002C))
+#define ST_SM_TIME_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000030))
+#define ST_SM_SUPFRM_TIME_L_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000034))
+#define ST_SM_SUPFRM_TIME_H_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000038))
+#define ST_SM_TIME_SLTBD(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000003C))
+#define ST_SM_SUPFRM_TIME_L_SLTBD(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000040))
+#define ST_SM_SUPFRM_TIME_H_SLTBD(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000044))
+#define ST_SM_TIME_WAKEUP_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000048))
+#define ST_SM_SUPFRM_TIME_L_WAKEUP_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000004C))
+#define ST_SM_SUPFRM_TIME_H_WAKEUP_START(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000050))
+#define ST_SM_FINAL_PAUSE_DURATION(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000054))
+#define ST_SM_PRESLP_CNT(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000058))
+#define ST_SM_SLT_START_F32K(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x0000005C))
+#define ST_SM_WAKEUP_START_F32K(i) ((APBADDR32)(ST_SM_REG_BASE +((i) << 17) + 0x00000060))
+
+
+#define ST_SM_CON_CLR_CNT_LSB (15)
+#define ST_SM_CON_CLR_CNT_WIDTH (1)
+#define ST_SM_CON_CLR_CNT_MASK (0x00008000)
+#define ST_SM_CON_CLR_CNT_BIT (0x00008000)
+
+#define ST_SM_CON_PAUSE_START_LSB (1)
+#define ST_SM_CON_PAUSE_START_WIDTH (1)
+#define ST_SM_CON_PAUSE_START_MASK (0x00000002)
+#define ST_SM_CON_PAUSE_START_BIT (0x00000002)
+
+#define ST_SM_CON_PAUSE_MODE_LSB (0)
+#define ST_SM_CON_PAUSE_MODE_WIDTH (1)
+#define ST_SM_CON_PAUSE_MODE_MASK (0x00000001)
+#define ST_SM_CON_PAUSE_MODE_BIT (0x00000001)
+
+#define ST_SM_PAUSE_TIME_PAUSE_TIME_LSB (0)
+#define ST_SM_PAUSE_TIME_PAUSE_TIME_WIDTH (32)
+#define ST_SM_PAUSE_TIME_PAUSE_TIME_MASK (0xFFFFFFFF)
+
+#define ST_SM_STA_SLP_EXIT_CPL_LSB (7)
+#define ST_SM_STA_SLP_EXIT_CPL_WIDTH (1)
+#define ST_SM_STA_SLP_EXIT_CPL_MASK (0x00000080)
+#define ST_SM_STA_SLP_EXIT_CPL_BIT (0x00000080)
+
+#define ST_SM_STA_PAUSE_CPL_LSB (6)
+#define ST_SM_STA_PAUSE_CPL_WIDTH (1)
+#define ST_SM_STA_PAUSE_CPL_MASK (0x00000040)
+#define ST_SM_STA_PAUSE_CPL_BIT (0x00000040)
+
+#define ST_SM_CFG_SW_WAKE_EN_LSB (8)
+#define ST_SM_CFG_SW_WAKE_EN_WIDTH (1)
+#define ST_SM_CFG_SW_WAKE_EN_MASK (0x00000100)
+#define ST_SM_CFG_SW_WAKE_EN_BIT (0x00000100)
+
+#define ST_SM_CFG_IRQ_EN_LSB (1)
+#define ST_SM_CFG_IRQ_EN_WIDTH (1)
+#define ST_SM_CFG_IRQ_EN_MASK (0x00000002)
+#define ST_SM_CFG_IRQ_EN_BIT (0x00000002)
+
+#define ST_SM_START_TIME_SYSTEM_TIME_CNT_LSB (2)
+#define ST_SM_START_TIME_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_SM_START_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_SM_SW_WAKE_CON_SW_EVENT_LSB (0)
+#define ST_SM_SW_WAKE_CON_SW_EVENT_WIDTH (1)
+#define ST_SM_SW_WAKE_CON_SW_EVENT_MASK (0x00000001)
+#define ST_SM_SW_WAKE_CON_SW_EVENT_BIT (0x00000001)
+
+#define ST_SM_STEP_FRAC_STEP_INT_LSB (18)
+#define ST_SM_STEP_FRAC_STEP_INT_WIDTH (9)
+#define ST_SM_STEP_FRAC_STEP_INT_MASK (0x07FC0000)
+
+#define ST_SM_STEP_FRAC_STEP_FRAC_LSB (0)
+#define ST_SM_STEP_FRAC_STEP_FRAC_WIDTH (18)
+#define ST_SM_STEP_FRAC_STEP_FRAC_MASK (0x0003FFFF)
+
+#define ST_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_LSB (0)
+#define ST_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_WIDTH (20)
+#define ST_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_MASK (0x000FFFFF)
+
+#define ST_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_LSB (0)
+#define ST_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_WIDTH (18)
+#define ST_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_MASK (0x0003FFFF)
+
+#define ST_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_LSB (0)
+#define ST_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_WIDTH (32)
+#define ST_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_MASK (0xFFFFFFFF)
+
+#define ST_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_LSB (0)
+#define ST_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_WIDTH (4)
+#define ST_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_MASK (0x0000000F)
+
+#define ST_SM_SLEEP_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST_SM_SLEEP_OFFSET_CHIP_OFFSET_WIDTH (14)
+#define ST_SM_SLEEP_OFFSET_CHIP_OFFSET_MASK (0x0000FFFC)
+
+#define ST_SM_TIME_START_SM_TIME_START_LSB (0)
+#define ST_SM_TIME_START_SM_TIME_START_WIDTH (20)
+#define ST_SM_TIME_START_SM_TIME_START_MASK (0x000FFFFF)
+
+#define ST_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_LSB (0)
+#define ST_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_WIDTH (32)
+#define ST_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_MASK (0xFFFFFFFF)
+
+#define ST_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_LSB (0)
+#define ST_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_WIDTH (4)
+#define ST_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_MASK (0x0000000F)
+
+#define ST_SM_TIME_SLTBD_SM_TIME_SLTBD_LSB (0)
+#define ST_SM_TIME_SLTBD_SM_TIME_SLTBD_WIDTH (20)
+#define ST_SM_TIME_SLTBD_SM_TIME_SLTBD_MASK (0x000FFFFF)
+
+#define ST_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define ST_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (32)
+#define ST_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0xFFFFFFFF)
+
+#define ST_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0)
+#define ST_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (4)
+#define ST_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0x0000000F)
+
+#define ST_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_LSB (0)
+#define ST_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_WIDTH (20)
+#define ST_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_MASK (0x000FFFFF)
+
+#define ST_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define ST_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (32)
+#define ST_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0xFFFFFFFF)
+
+#define ST_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0)
+#define ST_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (4)
+#define ST_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0x0000000F)
+
+#define ST_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_LSB (0)
+#define ST_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_WIDTH (32)
+#define ST_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_MASK (0xFFFFFFFF)
+
+#define ST_SM_PRESLP_CNT_SM_PRESLP_CNT_LSB (0)
+#define ST_SM_PRESLP_CNT_SM_PRESLP_CNT_WIDTH (6)
+#define ST_SM_PRESLP_CNT_SM_PRESLP_CNT_MASK (0x0000003F)
+
+#define ST_SM_SLT_START_F32K_SM_SLT_START_F32K_LSB (0)
+#define ST_SM_SLT_START_F32K_SM_SLT_START_F32K_WIDTH (6)
+#define ST_SM_SLT_START_F32K_SM_SLT_START_F32K_MASK (0x0000003F)
+
+#define ST_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_LSB (0)
+#define ST_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_WIDTH (32)
+#define ST_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_MASK (0xFFFFFFFF)
+
+
+#endif /* _CPHSLPCTRL_H_ */
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxcrpcommon.h b/mcu/interface/l1/cl1/common/HW/cphtxcrpcommon.h
new file mode 100644
index 0000000..4dd9ed0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxcrpcommon.h
@@ -0,0 +1,177 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_COMMON_TXCRP_H_
+#define _CPH_COMMON_TXCRP_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXCRP_INTERNAL_REG_BASE (0xA8170000)
+#else
+#define TXCRP_INTERNAL_REG_BASE (0xA8970000)
+#endif
+
+#define MODE_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0000))
+#define CRC_EN ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0004))
+#define CRC_LENGTH ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0008))
+#define CRC_OUT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x000C))
+#define CRC_MOD_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0010))
+#define TD_SW_TIMER_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0014))
+#define TD_SW_TIMER_CON ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0018))
+#define FDD_SW_TIMER_GTXCRP_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x001C))
+#define FDD_SW_TIMER_WTXHCH_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0020))
+#define FDD_SW_TIMER_WTXCQI_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0024))
+#define FDD_SW_TTR_GTXCRP_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0028))
+#define FDD_SW_TTR_WTXHCH_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x002C))
+#define FDD_SW_TTR_WTXCQI_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0030))
+#define FDD_SW_TTR_SLOT_CNT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0034))
+#define C1X_SW_TIMER_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0038))
+#define C1X_SW_TIMER_CON ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x003C))
+#define WRBRPMEM_TEST_START ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0040))
+#define WRBRPMEM_TEST_NUM ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0044))
+#define DO_TRIGGER_SELECT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x004C))
+#define DO_TIMER_TRIGGER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0050))
+#define DO_KS_TRIGGER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0054))
+#define DO_TX_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0058))
+#define TESTMODE_NUM ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x005C))
+#define TESTMODE_START ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0060))
+#define KS_SEL_CONFIG ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0064))
+#define MODE_SEL_ADDR_MIS ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0068))
+#define IRQ_MODE_SEL_ADDR_MIS_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x006C))
+#define IRQ_MODE_CHANGE_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0070))
+#define TXCRP_MODE_SETERR_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0074))
+#define TXCRP_IRQ_STATUS ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0078))
+#define TXCRP_IRQ_MASK ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x007C))
+#define INFO_BRP_RU1_ADDR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0080))
+#define INFO_BRP_RU1 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0084))
+#define INFO_BRP_RU2_ADDR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x008C))
+#define INFO_BRP_RU2 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0090))
+#define DBG_BUS_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0094))
+#define DUMMY_CRP ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0098))
+#define RAKE_LOG_COUNTER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x009C))
+#define RAKELOG_0 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A0))
+#define RAKELOG_1 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A4))
+#define RAKELOG_2 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A8))
+#define RAKELOG_3 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00AC))
+#define RAKELOG_4 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00B0))
+#if defined(__MD97__)
+#define TXCRP_KS0_TO_TPC ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x010C))
+#define TXCRP_KS1_TO_TPC ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0110))
+#endif
+
+#define MODE_SEL_LSB (0)
+#define MODE_SEL_WIDTH (5)
+#define MODE_SEL_MASK (0x0000001F)
+
+#define MODE_SEL_ADDR_MIS_LSB (0)
+#define MODE_SEL_ADDR_MIS_WIDTH (1)
+#define MODE_SEL_ADDR_MIS_MASK (0x00000001)
+#define MODE_SEL_ADDR_MIS_BIT (0x00000001)
+
+#define MODE_SEL_ADDR_MIS_CLR_LSB (0)
+#define MODE_SEL_ADDR_MIS_CLR_WIDTH (1)
+#define MODE_SEL_ADDR_MIS_CLR_MASK (0x00000001)
+#define MODE_SEL_ADDR_MIS_CLR_BIT (0x00000001)
+
+#define CRC_EN_LSB (0)
+#define CRC_EN_WIDTH (1)
+#define CRC_EN_MASK (0x00000001)
+#define CRC_EN_BIT (0x00000001)
+
+#define CRC_LENGTH_LSB (0)
+#define CRC_LENGTH_WIDTH (20)
+#define CRC_LENGTH_MASK (0x000FFFFF)
+
+#define CRC_OUT_LSB (0)
+#define CRC_OUT_WIDTH (32)
+#define CRC_OUT_MASK (0xFFFFFFFF)
+
+#define INFO_RU1_ADDR_LSB (0)
+#define INFO_RU1_ADDR_WIDTH (13)
+#define INFO_RU1_ADDR_MASK (0x00001FFF)
+
+#define RU1_ADDR0_DATA_LSB (24)
+#define RU1_ADDR0_DATA_WIDTH (8)
+#define RU1_ADDR0_DATA_MASK (0xFF000000)
+
+#define RU1_ADDR1_DATA_LSB (16)
+#define RU1_ADDR1_DATA_WIDTH (8)
+#define RU1_ADDR1_DATA_MASK (0x00FF0000)
+
+#define RU1_ADDR2_DATA_LSB (8)
+#define RU1_ADDR2_DATA_WIDTH (8)
+#define RU1_ADDR2_DATA_MASK (0x0000FF00)
+
+#define RU1_ADDR3_DATA_LSB (0)
+#define RU1_ADDR3_DATA_WIDTH (8)
+#define RU1_ADDR3_DATA_MASK (0x000000FF)
+
+#define INFO_RU2_ADDR_LSB (0)
+#define INFO_RU2_ADDR_WIDTH (13)
+#define INFO_RU2_ADDR_MASK (0x00001FFF)
+
+#define RU2_ADDR0_DATA_LSB (24)
+#define RU2_ADDR0_DATA_WIDTH (8)
+#define RU2_ADDR0_DATA_MASK (0xFF000000)
+
+#define RU2_ADDR1_DATA_LSB (16)
+#define RU2_ADDR1_DATA_WIDTH (8)
+#define RU2_ADDR1_DATA_MASK (0x00FF0000)
+
+#define RU2_ADDR2_DATA_LSB (8)
+#define RU2_ADDR2_DATA_WIDTH (8)
+#define RU2_ADDR2_DATA_MASK (0x0000FF00)
+
+#define RU2_ADDR3_DATA_LSB (0)
+#define RU2_ADDR3_DATA_WIDTH (8)
+#define RU2_ADDR3_DATA_MASK (0x000000FF)
+
+#define DBG_BUS_SEL_LSB (0)
+#define DBG_BUS_SEL_WIDTH (4)
+#define DBG_BUS_SEL_MASK (0x0000000F)
+
+#define CRP_LSB (0)
+#define CRP_WIDTH (32)
+#define CRP_MASK (0xFFFFFFFF)
+
+#endif //#ifndef _CPH_COMMON_TXCRP_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxdfebb.h b/mcu/interface/l1/cl1/common/HW/cphtxdfebb.h
new file mode 100644
index 0000000..84f7631
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxdfebb.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphtxdfebb_93.h"
+#elif defined(__MD95__)
+#include "cphtxdfebb_95.h"
+#elif defined(__MD97__)
+#include "cphtxdfebb_97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxdfebb_93.h b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_93.h
new file mode 100644
index 0000000..8bb0174
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_93.h
@@ -0,0 +1,270 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXDFE_BB_H_
+#define _CPH_TXDFE_BB_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define TXDFE_BB_REG_REG_BASE (0XA8300000)
+
+#define TXDFE_BB_REG_end (TXDFE_BB_REG_REG_BASE + 0x64 + 1*4)
+#define TXDFE_BB_L_CCA_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0))
+#define TXDFE_BB_L_GROUP_SEL_WIN0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x4))
+#define TXDFE_BB_L_GROUP_SEL_WIN1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x8))
+#define TXDFE_BB_DATA_RATE_G0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0xc))
+#define TXDFE_BB_DATA_RATE_G1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x10))
+#define TXDFE_BB_SW_CON_WIN ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x14))
+#define TXDFE_BB_SW_CON_MODE ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x18))
+#define TXDFE_BB_L_CON_DEL_CAL ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x1c))
+#define TXDFE_BB_SW_CON_SINE ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x20))
+#define TXDFE_BB_SRC_FIFO_PTR_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x24))
+#define TXDFE_BB_WTC_NCO_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x28))
+#define TXDFE_BB_L_NCO_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x2c))
+#define TXDFE_BB_L_NCO_CON1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x30))
+#define TXDFE_BB_L_NCO_CON2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x34))
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x38))
+#define TXDFE_BB_SW_PAPR_TH ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x3c))
+#define TXDFE_BB_CFR_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x40))
+#define TXDFE_BB_CFR_CON1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x44))
+#define TXDFE_BB_CRC_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x48))
+#define TXDFE_BB_CRC_OUT_G0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x4c))
+#define TXDFE_BB_CRC_CON1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x50))
+#define TXDFE_BB_CRC_OUT_G1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x54))
+#define TXDFE_BB_C2K_IS95_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x58))
+#define TXDFE_BB_FPGA_CON_0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x5c))
+#define TXDFE_BB_IRQ_MASK ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x60))
+#define TxDFE_BB_DBG_SEL ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x64))
+
+
+#define TXDFE_BB_L_CCA_CON_RG_LTE_CCA_MODE_LSB (0)
+#define TXDFE_BB_L_CCA_CON_RG_LTE_CCA_MODE_WIDTH (1)
+#define TXDFE_BB_L_CCA_CON_RG_LTE_CCA_MODE_MASK (0x00000001)
+#define TXDFE_BB_L_CCA_CON_RG_LTE_CCA_MODE_BIT (0x00000001)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_WIDTH (1)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_MASK (0x00000001)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_BIT (0x00000001)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_WIDTH (1)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_MASK (0x00000001)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_BIT (0x00000001)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_CCA_BW_REAL_G0_LSB (6)
+#define TXDFE_BB_DATA_RATE_G0_RG_CCA_BW_REAL_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_CCA_BW_REAL_G0_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_LSB (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_LSB (0)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_MASK (0x00000007)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_CCA_BW_REAL_G1_LSB (6)
+#define TXDFE_BB_DATA_RATE_G1_RG_CCA_BW_REAL_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_CCA_BW_REAL_G1_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_LSB (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_LSB (0)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_MASK (0x00000007)
+
+#define TXDFE_BB_SW_CON_WIN_RG_TXDFE_BB_SW_TXDFE_WIN_LSB (0)
+#define TXDFE_BB_SW_CON_WIN_RG_TXDFE_BB_SW_TXDFE_WIN_WIDTH (1)
+#define TXDFE_BB_SW_CON_WIN_RG_TXDFE_BB_SW_TXDFE_WIN_MASK (0x00000001)
+#define TXDFE_BB_SW_CON_WIN_RG_TXDFE_BB_SW_TXDFE_WIN_BIT (0x00000001)
+
+#define TXDFE_BB_SW_CON_MODE_RG_TXDFE_BB_SW_MODE_EN_LSB (0)
+#define TXDFE_BB_SW_CON_MODE_RG_TXDFE_BB_SW_MODE_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_MODE_RG_TXDFE_BB_SW_MODE_EN_MASK (0x00000001)
+#define TXDFE_BB_SW_CON_MODE_RG_TXDFE_BB_SW_MODE_EN_BIT (0x00000001)
+
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_LSB (0)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_WIDTH (1)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_MASK (0x00000001)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_BIT (0x00000001)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_LSB (8)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_MASK (0x00000100)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_BIT (0x00000100)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_LSB (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_WIDTH (3)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_MASK (0x00000070)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_LSB (0)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_WIDTH (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_LSB (0)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_WIDTH (3)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_MASK (0x00000007)
+
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_LSB (0)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_WIDTH (32)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_LSB (0)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_LSB (0)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_INIT_PHASE_LSB (0)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_INIT_PHASE_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_INIT_PHASE_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_TXDFE_BB_NCO_DELTA_F_RES_STR_LSB (0)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_TXDFE_BB_NCO_DELTA_F_RES_STR_WIDTH (1)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_TXDFE_BB_NCO_DELTA_F_RES_STR_MASK (0x00000001)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_TXDFE_BB_NCO_DELTA_F_RES_STR_BIT (0x00000001)
+
+#define TXDFE_BB_SW_PAPR_TH_RG_TXDFE_BB_SW_PAPR_RED_A_LSB (0)
+#define TXDFE_BB_SW_PAPR_TH_RG_TXDFE_BB_SW_PAPR_RED_A_WIDTH (12)
+#define TXDFE_BB_SW_PAPR_TH_RG_TXDFE_BB_SW_PAPR_RED_A_MASK (0x00000FFF)
+
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_SQRT_COEFF_LSB (2)
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_SQRT_COEFF_WIDTH (3)
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_SQRT_COEFF_MASK (0x0000001C)
+
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_ON_LSB (0)
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_ON_WIDTH (2)
+#define TXDFE_BB_CFR_CON0_RG_PAPR_RED_ON_MASK (0x00000003)
+
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W4_LSB (24)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W4_WIDTH (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W4_MASK (0x3F000000)
+
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W3_LSB (18)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W3_WIDTH (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W3_MASK (0x00FC0000)
+
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W2_LSB (12)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W2_WIDTH (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W2_MASK (0x0003F000)
+
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W1_LSB (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W1_WIDTH (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W1_MASK (0x00000FC0)
+
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W0_LSB (0)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W0_WIDTH (6)
+#define TXDFE_BB_CFR_CON1_RG_PAPR_W0_MASK (0x0000003F)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_LSB (8)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_WIDTH (24)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_LSB (4)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_WIDTH (3)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_LSB (0)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_WIDTH (1)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_LSB (0)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_LSB (8)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_WIDTH (24)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_LSB (4)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_WIDTH (3)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_LSB (0)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_WIDTH (1)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_LSB (0)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_LSB (0)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_WIDTH (1)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_MASK (0x00000001)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_BIT (0x00000001)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_LSB (1)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_WIDTH (1)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_MASK (0x00000002)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_BIT (0x00000002)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_LSB (0)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_WIDTH (1)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_MASK (0x00000001)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_BIT (0x00000001)
+
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_CLR_LSB (1)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_CLR_WIDTH (1)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_CLR_MASK (0x00000002)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_CLR_BIT (0x00000002)
+
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_MASK_LSB (0)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_MASK_WIDTH (1)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_MASK_MASK (0x00000001)
+#define TXDFE_BB_IRQ_MASK_RG_IRQ_MASK_BIT (0x00000001)
+
+#define TxDFE_BB_DBG_SEL_RG_DBG_EN_LSB (4)
+#define TxDFE_BB_DBG_SEL_RG_DBG_EN_WIDTH (1)
+#define TxDFE_BB_DBG_SEL_RG_DBG_EN_MASK (0x00000010)
+#define TxDFE_BB_DBG_SEL_RG_DBG_EN_BIT (0x00000010)
+
+#define TxDFE_BB_DBG_SEL_RG_DBG_SEL_LSB (0)
+#define TxDFE_BB_DBG_SEL_RG_DBG_SEL_WIDTH (4)
+#define TxDFE_BB_DBG_SEL_RG_DBG_SEL_MASK (0x0000000F)
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxdfebb_95.h b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_95.h
new file mode 100644
index 0000000..10dea4f
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_95.h
@@ -0,0 +1,1028 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXDFE_BB_H_
+#define _CPH_TXDFE_BB_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#define TXDFE_BB_REG_REG_BASE (0xA8302000)
+
+#define TXDFE_BB_REG_end (TXDFE_BB_REG_REG_BASE + 0xFFC + 1*4)
+
+#define TXDFE_BB_GLB_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x000))
+#define TXDFE_BB_DATA_RATE_G0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x004))
+#define TXDFE_BB_DATA_RATE_G1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x008))
+#define TXDFE_BB_DATA_RATE_G2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x00C))
+#define TXDFE_BB_L_GROUP_SEL_WIN0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x010))
+#define TXDFE_BB_L_GROUP_SEL_WIN1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x014))
+#define TXDFE_BB_L_GROUP_SEL_WIN2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x018))
+#define TXDFE_BB_L_NCO_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x01C))
+#define TXDFE_BB_L_NCO_CON1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x020))
+#define TXDFE_BB_L_NCO_CON2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x024))
+#define TXDFE_BB_L_NCO_CON3 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x028))
+#define TXDFE_BB_L_NCO_CON4 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x02C))
+#define TXDFE_BB_L_NCO_CON5 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x030))
+#define TXDFE_BB_SW_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x034))
+#define TXDFE_BB_SW_CON_SINE ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x038))
+#define TXDFE_BB_L_CON_DEL_CAL ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x03C))
+#define TXDFE_BB_SRC_FIFO_PTR_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x040))
+#define TXDFE_BB_WTC_NCO_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x044))
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x048))
+#define TXDFE_BB_C2K_IS95_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x04C))
+#define TXDFE_BB_CRC_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x050))
+#define TXDFE_BB_CRC_OUT_G0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x054))
+#define TXDFE_BB_CRC_CON1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x058))
+#define TXDFE_BB_CRC_OUT_G1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x05C))
+#define TXDFE_BB_CRC_CON2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x060))
+#define TXDFE_BB_CRC_OUT_G2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x064))
+#define TXDFE_BB_PCC_INFO ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x068))
+#define TXDFE_BB_PCC_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x06C))
+#define TXDFE_BB_TEST_SEL ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x070))
+#define TXDFE_BB_WIN_ERR_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x074))
+#define TXDFE_BB_DBG_0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x080))
+#define TXDFE_BB_DBG_1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x084))
+#define TXDFE_BB_DBG_2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x088))
+#define TXDFE_BB_DBG_3 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x08C))
+#define TXDFE_BB_DBG_4 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x090))
+#define TXDFE_BB_DBG_5 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x094))
+#define TXDFE_BB_DBG_6 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x098))
+#define TXDFE_BB_DBG_7 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x09C))
+#define TXDFE_BB_DBG_8 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0A0))
+#define TXDFE_BB_DBG_9 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0A4))
+#define TXDFE_BB_DBG_10 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0A8))
+#define TXDFE_BB_DBG_11 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0AC))
+#define TXDFE_BB_DBG_12 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0B0))
+#define TXDFE_BB_DBG_13 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0B4))
+#define TXDFE_BB_DBG_14 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0B8))
+#define TXDFE_BB_DBG_15 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0BC))
+#define TXDFE_BB_DBG_16 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x0C0))
+#define TXDFE_BB_FPGA_CON_0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x100))
+#define TXDFE_BB_P0_CFR_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x800))
+#define TXDFE_BB_P0_CFR_ROM_0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x804))
+#define TXDFE_BB_P0_CFR_ROM_1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x808))
+#define TXDFE_BB_P0_CFR_ROM_2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x80C))
+#define TXDFE_BB_P1_CFR_CON ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x810))
+#define TXDFE_BB_P1_CFR_ROM_0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x814))
+#define TXDFE_BB_P1_CFR_ROM_1 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x818))
+#define TXDFE_BB_P1_CFR_ROM_2 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x81C))
+#define TXDFE_BB_P0_CFR_SW_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x820))
+#define TXDFE_BB_P0_CFR_SW_MODE ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x824))
+#define TXDFE_BB_P1_CFR_SW_CON0 ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x830))
+#define TXDFE_BB_P1_CFR_SW_MODE ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0x834))
+#define TXDFE_BB_REG_PROTECT ((APBADDR32)(TXDFE_BB_REG_REG_BASE + 0xFFC))
+
+
+
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_LSB (4)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_WIDTH (1)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_MASK (0x00000010)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_BIT (0x00000010)
+
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_LSB (0)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_WIDTH (1)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_MASK (0x00000001)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_BIT (0x00000001)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_LSB (6)
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_LSB (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_LSB (0)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_MASK (0x00000007)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_LSB (6)
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_LSB (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_LSB (0)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_MASK (0x00000007)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_LSB (6)
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_LSB (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_LSB (0)
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_MASK (0x00000007)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_MASK (0x00000003)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_MASK (0x00000003)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_MASK (0x00000003)
+
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_LSB (0)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_LSB (0)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_LSB (0)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_LSB (0)
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_LSB (0)
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_LSB (0)
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_LSB (4)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_MASK (0x00000010)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_BIT (0x00000010)
+
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_LSB (0)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_WIDTH (1)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_MASK (0x00000001)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_BIT (0x00000001)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_LSB (8)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_MASK (0x00000100)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_BIT (0x00000100)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_LSB (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_WIDTH (3)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_MASK (0x00000070)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_LSB (0)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_WIDTH (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_LSB (0)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_WIDTH (1)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_MASK (0x00000001)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_BIT (0x00000001)
+
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_LSB (0)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_WIDTH (3)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_MASK (0x00000007)
+
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_LSB (0)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_WIDTH (32)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_LSB (0)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_WIDTH (1)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_MASK (0x00000001)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_BIT (0x00000001)
+
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_LSB (0)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_WIDTH (1)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_MASK (0x00000001)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_LSB (8)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_WIDTH (24)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_LSB (4)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_WIDTH (3)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_LSB (0)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_WIDTH (1)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_LSB (0)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_LSB (8)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_WIDTH (24)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_LSB (4)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_WIDTH (3)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_LSB (0)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_WIDTH (1)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_LSB (0)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_LSB (8)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_WIDTH (24)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_LSB (4)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_WIDTH (3)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_LSB (0)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_WIDTH (1)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_LSB (0)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_LSB (0)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_WIDTH (7)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_MASK (0x0000007F)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_LSB (4)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_WIDTH (1)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_MASK (0x00000010)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_BIT (0x00000010)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_LSB (0)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_WIDTH (3)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_MASK (0x00000007)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_LSB (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_WIDTH (1)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_MASK (0x00000010)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_BIT (0x00000010)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_LSB (0)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_WIDTH (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_LSB (0)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_WIDTH (1)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_MASK (0x00000001)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_BIT (0x00000001)
+
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_LSB (31)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_WIDTH (1)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_MASK (0x80000000)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_BIT (0x80000000)
+
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_LSB (0)
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_WIDTH (21)
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_MASK (0x001FFFFF)
+
+#define TXDFE_BB_DBG_1_RG_DBG_1_LSB (0)
+#define TXDFE_BB_DBG_1_RG_DBG_1_WIDTH (32)
+#define TXDFE_BB_DBG_1_RG_DBG_1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_2_RG_DBG_2_LSB (0)
+#define TXDFE_BB_DBG_2_RG_DBG_2_WIDTH (32)
+#define TXDFE_BB_DBG_2_RG_DBG_2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_3_RG_DBG_3_LSB (0)
+#define TXDFE_BB_DBG_3_RG_DBG_3_WIDTH (32)
+#define TXDFE_BB_DBG_3_RG_DBG_3_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_4_RG_DBG_4_LSB (0)
+#define TXDFE_BB_DBG_4_RG_DBG_4_WIDTH (32)
+#define TXDFE_BB_DBG_4_RG_DBG_4_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_5_RG_DBG_5_LSB (0)
+#define TXDFE_BB_DBG_5_RG_DBG_5_WIDTH (32)
+#define TXDFE_BB_DBG_5_RG_DBG_5_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_6_RG_DBG_6_LSB (0)
+#define TXDFE_BB_DBG_6_RG_DBG_6_WIDTH (32)
+#define TXDFE_BB_DBG_6_RG_DBG_6_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_7_RG_DBG_7_LSB (0)
+#define TXDFE_BB_DBG_7_RG_DBG_7_WIDTH (32)
+#define TXDFE_BB_DBG_7_RG_DBG_7_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_8_RG_DBG_8_LSB (0)
+#define TXDFE_BB_DBG_8_RG_DBG_8_WIDTH (32)
+#define TXDFE_BB_DBG_8_RG_DBG_8_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_9_RG_DBG_9_LSB (0)
+#define TXDFE_BB_DBG_9_RG_DBG_9_WIDTH (32)
+#define TXDFE_BB_DBG_9_RG_DBG_9_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_10_RG_DBG_10_LSB (0)
+#define TXDFE_BB_DBG_10_RG_DBG_10_WIDTH (32)
+#define TXDFE_BB_DBG_10_RG_DBG_10_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_11_RG_DBG_11_LSB (0)
+#define TXDFE_BB_DBG_11_RG_DBG_11_WIDTH (32)
+#define TXDFE_BB_DBG_11_RG_DBG_11_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_12_RG_DBG_12_LSB (0)
+#define TXDFE_BB_DBG_12_RG_DBG_12_WIDTH (32)
+#define TXDFE_BB_DBG_12_RG_DBG_12_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_13_RG_DBG_13_LSB (0)
+#define TXDFE_BB_DBG_13_RG_DBG_13_WIDTH (32)
+#define TXDFE_BB_DBG_13_RG_DBG_13_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_14_RG_DBG_14_LSB (0)
+#define TXDFE_BB_DBG_14_RG_DBG_14_WIDTH (32)
+#define TXDFE_BB_DBG_14_RG_DBG_14_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_15_RG_DBG_15_LSB (0)
+#define TXDFE_BB_DBG_15_RG_DBG_15_WIDTH (32)
+#define TXDFE_BB_DBG_15_RG_DBG_15_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_16_RG_DBG_16_LSB (0)
+#define TXDFE_BB_DBG_16_RG_DBG_16_WIDTH (32)
+#define TXDFE_BB_DBG_16_RG_DBG_16_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_LSB (24)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_WIDTH (2)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_MASK (0x03000000)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_LSB (16)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_WIDTH (5)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_MASK (0x001F0000)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_LSB (8)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_WIDTH (5)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_MASK (0x00001F00)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_LSB (0)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_WIDTH (1)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_MASK (0x00000001)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_BIT (0x00000001)
+
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_LSB (0)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_WIDTH (1)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_MASK (0x00000001)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_BIT (0x00000001)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_LSB (27)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_MASK (0x38000000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_LSB (20)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_MASK (0x07F00000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_LSB (17)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_MASK (0x000E0000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_LSB (10)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_MASK (0x0001FC00)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_LSB (27)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_MASK (0x38000000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_LSB (20)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_MASK (0x07F00000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_LSB (17)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_MASK (0x000E0000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_LSB (10)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_MASK (0x0001FC00)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_LSB (0)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_WIDTH (1)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_MASK (0x00000001)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_BIT (0x00000001)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_LSB (27)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_MASK (0x38000000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_LSB (20)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_MASK (0x07F00000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_LSB (17)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_MASK (0x000E0000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_LSB (10)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_MASK (0x0001FC00)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_LSB (27)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_MASK (0x38000000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_LSB (20)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_MASK (0x07F00000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_LSB (17)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_MASK (0x000E0000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_LSB (10)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_MASK (0x0001FC00)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_LSB (16)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_WIDTH (5)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_MASK (0x001F0000)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_LSB (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_WIDTH (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_MASK (0x0000FF00)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_LSB (0)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_WIDTH (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_MASK (0x000000FF)
+
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_LSB (0)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_WIDTH (1)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_MASK (0x00000001)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_BIT (0x00000001)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_LSB (16)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_WIDTH (5)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_MASK (0x001F0000)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_LSB (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_WIDTH (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_MASK (0x0000FF00)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_LSB (0)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_WIDTH (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_MASK (0x000000FF)
+
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_LSB (0)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_WIDTH (1)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_MASK (0x00000001)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_BIT (0x00000001)
+
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_LSB (0)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_WIDTH (4)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_MASK (0x0000000F)
+
+
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_LSB (4)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_WIDTH (1)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_MASK (0x00000010)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_BIT (0x00000010)
+
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_LSB (0)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_WIDTH (1)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_MASK (0x00000001)
+#define TXDFE_BB_GLB_CON_RG_LTE_CCA_MODE_BIT (0x00000001)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_LSB (6)
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_BW_REAL_G0_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_LSB (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_PRACH_F_G0_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_LSB (0)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G0_RG_LTE_CBW_G0_MASK (0x00000007)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_LSB (6)
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_BW_REAL_G1_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_LSB (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_PRACH_F_G1_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_LSB (0)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G1_RG_LTE_CBW_G1_MASK (0x00000007)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_LSB (6)
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_BW_REAL_G2_MASK (0x000001C0)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_LSB (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_PRACH_F_G2_MASK (0x00000038)
+
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_LSB (0)
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_WIDTH (3)
+#define TXDFE_BB_DATA_RATE_G2_RG_LTE_CBW_G2_MASK (0x00000007)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN0_RG_LTE_GROUP_SEL_WIN0_MASK (0x00000003)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN1_RG_LTE_GROUP_SEL_WIN1_MASK (0x00000003)
+
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_LSB (0)
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_WIDTH (2)
+#define TXDFE_BB_L_GROUP_SEL_WIN2_RG_LTE_GROUP_SEL_WIN2_MASK (0x00000003)
+
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_LSB (0)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON0_RG_NCO_L_DELTA_F_RES_DB0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_LSB (0)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON1_RG_NCO_L_DELTA_F_RES_DB1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_LSB (0)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_WIDTH (32)
+#define TXDFE_BB_L_NCO_CON2_RG_NCO_L_DELTA_F_RES_DB2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_LSB (0)
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON3_RG_NCO_L_INIT_PHASE_G0_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_LSB (0)
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON4_RG_NCO_L_INIT_PHASE_G1_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_LSB (0)
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_WIDTH (26)
+#define TXDFE_BB_L_NCO_CON5_RG_NCO_L_INIT_PHASE_G2_MASK (0x03FFFFFF)
+
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_LSB (4)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_MASK (0x00000010)
+#define TXDFE_BB_SW_CON_RG_DELTA_F_RES_AUTO_CLR_EN_BIT (0x00000010)
+
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_LSB (0)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_WIDTH (1)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_MASK (0x00000001)
+#define TXDFE_BB_SW_CON_RG_TXDFE_BB_SW_TXDFE_WIN_BIT (0x00000001)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_LSB (8)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_MASK (0x00000100)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_BIT (0x00000100)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_LSB (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_WIDTH (3)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_MASK (0x00000070)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_LSB (0)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_WIDTH (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_LSB (0)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_WIDTH (1)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_MASK (0x00000001)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_BIT (0x00000001)
+
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_LSB (0)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_WIDTH (3)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_MASK (0x00000007)
+
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_LSB (0)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_WIDTH (32)
+#define TXDFE_BB_WTC_NCO_CON_RG_NCO_WTC_DELTA_F_RES_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_LSB (0)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_WIDTH (1)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_MASK (0x00000001)
+#define TXDFE_BB_WTC_NCO_DELTA_F_RES_CON_SP_TXDFE_BB_NCO_DELTA_F_RES_STR_BIT (0x00000001)
+
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_LSB (0)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_WIDTH (1)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_MASK (0x00000001)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_LSB (8)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_WIDTH (24)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_LSB (4)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_WIDTH (3)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_LSB (0)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_WIDTH (1)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_LSB (0)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_G0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_LSB (8)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_WIDTH (24)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_LSB (4)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_WIDTH (3)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_LSB (0)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_WIDTH (1)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_LSB (0)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_G1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_LSB (8)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_WIDTH (24)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G2_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_LSB (4)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_WIDTH (3)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G2_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_LSB (0)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_WIDTH (1)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G2_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_LSB (0)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_G2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_LSB (0)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_WIDTH (7)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_MASK (0x0000007F)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_LSB (4)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_WIDTH (1)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_MASK (0x00000010)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_BIT (0x00000010)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_LSB (0)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_WIDTH (3)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_MASK (0x00000007)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_LSB (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_WIDTH (1)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_MASK (0x00000010)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_BIT (0x00000010)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_LSB (0)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_WIDTH (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_LSB (0)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_WIDTH (1)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_MASK (0x00000001)
+#define TXDFE_BB_WIN_ERR_CON_SP_WIN_ERR_CLR_BIT (0x00000001)
+
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_LSB (31)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_WIDTH (1)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_MASK (0x80000000)
+#define TXDFE_BB_DBG_0_RG_WIN_ERR_BIT (0x80000000)
+
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_LSB (0)
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_WIDTH (21)
+#define TXDFE_BB_DBG_0_RG_TPC_CFR_MASK (0x001FFFFF)
+
+#define TXDFE_BB_DBG_1_RG_DBG_1_LSB (0)
+#define TXDFE_BB_DBG_1_RG_DBG_1_WIDTH (32)
+#define TXDFE_BB_DBG_1_RG_DBG_1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_2_RG_DBG_2_LSB (0)
+#define TXDFE_BB_DBG_2_RG_DBG_2_WIDTH (32)
+#define TXDFE_BB_DBG_2_RG_DBG_2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_3_RG_DBG_3_LSB (0)
+#define TXDFE_BB_DBG_3_RG_DBG_3_WIDTH (32)
+#define TXDFE_BB_DBG_3_RG_DBG_3_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_4_RG_DBG_4_LSB (0)
+#define TXDFE_BB_DBG_4_RG_DBG_4_WIDTH (32)
+#define TXDFE_BB_DBG_4_RG_DBG_4_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_5_RG_DBG_5_LSB (0)
+#define TXDFE_BB_DBG_5_RG_DBG_5_WIDTH (32)
+#define TXDFE_BB_DBG_5_RG_DBG_5_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_6_RG_DBG_6_LSB (0)
+#define TXDFE_BB_DBG_6_RG_DBG_6_WIDTH (32)
+#define TXDFE_BB_DBG_6_RG_DBG_6_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_7_RG_DBG_7_LSB (0)
+#define TXDFE_BB_DBG_7_RG_DBG_7_WIDTH (32)
+#define TXDFE_BB_DBG_7_RG_DBG_7_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_8_RG_DBG_8_LSB (0)
+#define TXDFE_BB_DBG_8_RG_DBG_8_WIDTH (32)
+#define TXDFE_BB_DBG_8_RG_DBG_8_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_9_RG_DBG_9_LSB (0)
+#define TXDFE_BB_DBG_9_RG_DBG_9_WIDTH (32)
+#define TXDFE_BB_DBG_9_RG_DBG_9_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_10_RG_DBG_10_LSB (0)
+#define TXDFE_BB_DBG_10_RG_DBG_10_WIDTH (32)
+#define TXDFE_BB_DBG_10_RG_DBG_10_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_11_RG_DBG_11_LSB (0)
+#define TXDFE_BB_DBG_11_RG_DBG_11_WIDTH (32)
+#define TXDFE_BB_DBG_11_RG_DBG_11_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_12_RG_DBG_12_LSB (0)
+#define TXDFE_BB_DBG_12_RG_DBG_12_WIDTH (32)
+#define TXDFE_BB_DBG_12_RG_DBG_12_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_13_RG_DBG_13_LSB (0)
+#define TXDFE_BB_DBG_13_RG_DBG_13_WIDTH (32)
+#define TXDFE_BB_DBG_13_RG_DBG_13_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_14_RG_DBG_14_LSB (0)
+#define TXDFE_BB_DBG_14_RG_DBG_14_WIDTH (32)
+#define TXDFE_BB_DBG_14_RG_DBG_14_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_15_RG_DBG_15_LSB (0)
+#define TXDFE_BB_DBG_15_RG_DBG_15_WIDTH (32)
+#define TXDFE_BB_DBG_15_RG_DBG_15_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_16_RG_DBG_16_LSB (0)
+#define TXDFE_BB_DBG_16_RG_DBG_16_WIDTH (32)
+#define TXDFE_BB_DBG_16_RG_DBG_16_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_LSB (24)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_WIDTH (2)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_SRC_IQ_SWAP_MASK (0x03000000)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_LSB (16)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_WIDTH (5)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CK_DBG_SEL_MASK (0x001F0000)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_LSB (8)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_WIDTH (5)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_OUT_SEL_MASK (0x00001F00)
+
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_LSB (0)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_WIDTH (1)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_MASK (0x00000001)
+#define TXDFE_BB_FPGA_CON_0_RG_FPGA_CIC_CK_SEL_BIT (0x00000001)
+
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_LSB (0)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_WIDTH (1)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_MASK (0x00000001)
+#define TXDFE_BB_P0_CFR_CON_RG_CFR_P0_ON_BIT (0x00000001)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_LSB (27)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_2_MASK (0x38000000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_LSB (20)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_2_MASK (0x07F00000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_LSB (17)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_1_MASK (0x000E0000)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_LSB (10)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_1_MASK (0x0001FC00)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_E_ROM_0_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_0_RG_CFR_P0_M_ROM_0_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_LSB (27)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_5_MASK (0x38000000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_LSB (20)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_5_MASK (0x07F00000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_LSB (17)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_4_MASK (0x000E0000)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_LSB (10)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_4_MASK (0x0001FC00)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_E_ROM_3_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_1_RG_CFR_P0_M_ROM_3_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_LSB (7)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_WIDTH (3)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_E_ROM_6_MASK (0x00000380)
+
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_LSB (0)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_WIDTH (7)
+#define TXDFE_BB_P0_CFR_ROM_2_RG_CFR_P0_M_ROM_6_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_LSB (0)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_WIDTH (1)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_MASK (0x00000001)
+#define TXDFE_BB_P1_CFR_CON_RG_CFR_P1_ON_BIT (0x00000001)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_LSB (27)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_2_MASK (0x38000000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_LSB (20)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_2_MASK (0x07F00000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_LSB (17)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_1_MASK (0x000E0000)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_LSB (10)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_1_MASK (0x0001FC00)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_E_ROM_0_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_0_RG_CFR_P1_M_ROM_0_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_LSB (27)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_5_MASK (0x38000000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_LSB (20)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_5_MASK (0x07F00000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_LSB (17)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_4_MASK (0x000E0000)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_LSB (10)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_4_MASK (0x0001FC00)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_E_ROM_3_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_1_RG_CFR_P1_M_ROM_3_MASK (0x0000007F)
+
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_LSB (7)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_WIDTH (3)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_E_ROM_6_MASK (0x00000380)
+
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_LSB (0)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_WIDTH (7)
+#define TXDFE_BB_P1_CFR_ROM_2_RG_CFR_P1_M_ROM_6_MASK (0x0000007F)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_LSB (16)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_WIDTH (5)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_SCALE_MASK (0x001F0000)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_LSB (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_WIDTH (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_CLIP_MASK (0x0000FF00)
+
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_LSB (0)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_WIDTH (8)
+#define TXDFE_BB_P0_CFR_SW_CON0_RG_CFR_P0_SW_A_TH_PC_MASK (0x000000FF)
+
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_LSB (0)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_WIDTH (1)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_MASK (0x00000001)
+#define TXDFE_BB_P0_CFR_SW_MODE_RG_CFR_P0_SW_MODE_EN_BIT (0x00000001)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_LSB (16)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_WIDTH (5)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_SCALE_MASK (0x001F0000)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_LSB (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_WIDTH (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_CLIP_MASK (0x0000FF00)
+
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_LSB (0)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_WIDTH (8)
+#define TXDFE_BB_P1_CFR_SW_CON0_RG_CFR_P1_SW_A_TH_PC_MASK (0x000000FF)
+
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_LSB (0)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_WIDTH (1)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_MASK (0x00000001)
+#define TXDFE_BB_P1_CFR_SW_MODE_RG_CFR_P1_SW_MODE_EN_BIT (0x00000001)
+
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_LSB (0)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_WIDTH (4)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_MASK (0x0000000F)
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxdfebb_97.h b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_97.h
new file mode 100644
index 0000000..3f32c62
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxdfebb_97.h
@@ -0,0 +1,399 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+*
+* FILE NAME: : cphtxdfebbd
+* DESCRIPTION: Txdfebb D-die related registers
+*
+*****************************************************************************/
+
+
+
+#ifndef _CPH_TXDFE_BB_D_H_
+#define _CPH_TXDFE_BB_D_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXDFE_D_CC0_REG_BASE (0XA8AB2000)
+
+
+#define TXDFE_D_CC0_end (TXDFE_D_CC0_REG_BASE + 0x248 + 1*4)
+
+
+
+
+
+
+#define TXDFE_BB_REG_PROTECT ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x000))
+#define TXDFE_BB_GLB_CON ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x004))
+#define TXDFE_BB_SW_CON_SINE ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x008))
+#define TXDFE_BB_L_CON_DEL_CAL ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x00C))
+#define TXDFE_BB_SRC_FIFO_PTR_CON ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x010))
+#define TXDFE_BB_C2K_IS95_CON ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x014))
+#define TXDFE_BB_CRC_CON0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x018))
+#define TXDFE_BB_CRC_OUT_G0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x01C))
+#define TXDFE_BB_CRC_CON1 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x020))
+#define TXDFE_BB_CRC_OUT_G1 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x024))
+#define TXDFE_BB_CRC_CON2 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x028))
+#define TXDFE_BB_CRC_OUT_G2 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x02C))
+#define TXDFE_BB_PCC_INFO ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x030))
+#define TXDFE_BB_PCC_CON0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x034))
+#define SERDES_TICK_DELAY ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x038))
+#define IRQ_STATUS ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x040))
+#define IRQ_MASK ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x044))
+#define IRQ_CLEAR ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x048))
+#define TXDFE_BB_TEST_SEL ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x04C))
+#define TXDFE_BB_DBG_0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x050))
+#define TXDFE_BB_DBG_1 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x054))
+#define TXDFE_BB_DBG_2 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x058))
+#define TXDFE_BB_DBG_3 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x05C))
+#define TXDFE_BB_DBG_4 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x060))
+#define TXDFE_BB_DBG_5 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x064))
+#define TXDFE_BB_DBG_6 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x068))
+#define TXDFE_BB_DBG_7 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x06C))
+#define TXDFE_BB_DBG_8 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x070))
+#define TXDFE_BB_DBG_9 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x074))
+#define TXDFE_BB_DBG_10 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x078))
+#define TXDFE_BB_DBG_11 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x07C))
+#define TXDFE_BB_DBG_12 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x080))
+#define TXDFE_BB_DBG_13 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x084))
+#define TXDFE_BB_DBG_14 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x088))
+#define TXDFE_BB_DBG_15 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x08C))
+#define FIR_SUP_CON_G0_PART0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x090))
+#define FIR_SUP_CON_G0_PART1 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x094))
+#define TXDFE_WIN_REG_PROTECT ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x100))
+#define TQ_0_CON ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x110))
+#define SERDES_PRE_EN_ON_0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x200))
+#define SERDES_EN_OFF_0 ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x218))
+#define SERDES_EN_ON_OFFSET ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x230))
+#define SERDES_PRE_EN_OFF_OFFSET ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x234))
+#define SERDES_WIN_ENABLE ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x238)) /* SW can use it or not*/
+#define TXDFE_D_SERDES_PRE_EN_SW ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x240))
+#define TXDFE_D_SERDES_EN_SW ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x244))
+#define TXDFE_D_DFE_WIN_SW ((APBADDR32)(TXDFE_D_CC0_REG_BASE + 0x248))
+
+
+
+
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_LSB (0)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_WIDTH (4)
+#define TXDFE_BB_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_MASK (0x0000000F)
+
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_LSB (4)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_WIDTH (1)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_MASK (0x00000010)
+#define TXDFE_BB_GLB_CON_RG_SW_CG_EN_BIT (0x00000010)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_LSB (8)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_WIDTH (1)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_MASK (0x00000100)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_GEN_EN_BIT (0x00000100)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_LSB (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_WIDTH (3)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_AMP_MASK (0x00000070)
+
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_LSB (0)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_WIDTH (4)
+#define TXDFE_BB_SW_CON_SINE_RG_TXDFE_BB_SW_SINE_FREQ_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_LSB (0)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_WIDTH (1)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_MASK (0x00000001)
+#define TXDFE_BB_L_CON_DEL_CAL_RG_DEL_CAL_ON_BIT (0x00000001)
+
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_LSB (0)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_WIDTH (3)
+#define TXDFE_BB_SRC_FIFO_PTR_CON_RG_SRC_FIFO_WPTR_INIT_MASK (0x00000007)
+
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_LSB (0)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_WIDTH (1)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_MASK (0x00000001)
+#define TXDFE_BB_C2K_IS95_CON_RG_C2K_IS95_FLG_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_LSB (8)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_WIDTH (24)
+#define TXDFE_BB_CRC_CON0_RG_CRC_LENGTH_G0_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_LSB (4)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_WIDTH (3)
+#define TXDFE_BB_CRC_CON0_RG_CRC_POINT_G0_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_LSB (0)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_WIDTH (1)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON0_RG_CRC_EN_G0_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_LSB (0)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G0_RG_CRC_OUT_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_LSB (8)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_WIDTH (24)
+#define TXDFE_BB_CRC_CON1_RG_CRC_LENGTH_G1_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_LSB (4)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_WIDTH (3)
+#define TXDFE_BB_CRC_CON1_RG_CRC_POINT_G1_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_LSB (0)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_WIDTH (1)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON1_RG_CRC_EN_G1_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_LSB (0)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G1_RG_CRC_OUT_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G0_LSB (8)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G0_WIDTH (24)
+#define TXDFE_BB_CRC_CON2_RG_CRC_LENGTH_G0_MASK (0xFFFFFF00)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G0_LSB (4)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G0_WIDTH (3)
+#define TXDFE_BB_CRC_CON2_RG_CRC_POINT_G0_MASK (0x00000070)
+
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G0_LSB (0)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G0_WIDTH (1)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G0_MASK (0x00000001)
+#define TXDFE_BB_CRC_CON2_RG_CRC_EN_G0_BIT (0x00000001)
+
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_LSB (0)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_WIDTH (32)
+#define TXDFE_BB_CRC_OUT_G2_RG_CRC_OUT_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_0_LSB (0)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_0_WIDTH (7)
+#define TXDFE_BB_PCC_INFO_RG_PCC_INFO_0_MASK (0x0000007F)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_0_LSB (4)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_0_WIDTH (1)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_0_MASK (0x00000010)
+#define TXDFE_BB_PCC_CON0_RG_PCC_EN_0_BIT (0x00000010)
+
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_0_LSB (0)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_0_WIDTH (3)
+#define TXDFE_BB_PCC_CON0_RG_PCC_SEL_0_MASK (0x00000007)
+
+#define SERDES_TICK_DELAY_SERDES_TICK_DELAY_LSB (0)
+#define SERDES_TICK_DELAY_SERDES_TICK_DELAY_WIDTH (5)
+#define SERDES_TICK_DELAY_SERDES_TICK_DELAY_MASK (0x0000001F)
+
+#define IRQ_STATUS_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_LSB (1)
+#define IRQ_STATUS_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_WIDTH (1)
+#define IRQ_STATUS_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_MASK (0x00000002)
+#define IRQ_STATUS_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_BIT (0x00000002)
+
+#define IRQ_STATUS_TXDFE_WIN_OFF_IRQ_STATUS_LSB (0)
+#define IRQ_STATUS_TXDFE_WIN_OFF_IRQ_STATUS_WIDTH (1)
+#define IRQ_STATUS_TXDFE_WIN_OFF_IRQ_STATUS_MASK (0x00000001)
+#define IRQ_STATUS_TXDFE_WIN_OFF_IRQ_STATUS_BIT (0x00000001)
+
+#define IRQ_MASK_TXDFE_FIFO_WIN_ERROR_IRQ_MASK_LSB (1)
+#define IRQ_MASK_TXDFE_FIFO_WIN_ERROR_IRQ_MASK_WIDTH (1)
+#define IRQ_MASK_TXDFE_FIFO_WIN_ERROR_IRQ_MASK_MASK (0x00000002)
+#define IRQ_MASK_TXDFE_FIFO_WIN_ERROR_IRQ_MASK_BIT (0x00000002)
+
+#define IRQ_MASK_TXDFE_WIN_OFF_IRQ_MASK_LSB (0)
+#define IRQ_MASK_TXDFE_WIN_OFF_IRQ_MASK_WIDTH (1)
+#define IRQ_MASK_TXDFE_WIN_OFF_IRQ_MASK_MASK (0x00000001)
+#define IRQ_MASK_TXDFE_WIN_OFF_IRQ_MASK_BIT (0x00000001)
+
+#define IRQ_CLEAR_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_CLEAR_LSB (1)
+#define IRQ_CLEAR_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_CLEAR_WIDTH (1)
+#define IRQ_CLEAR_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_CLEAR_MASK (0x00000002)
+#define IRQ_CLEAR_TXDFE_FIFO_WIN_ERROR_IRQ_STATUS_CLEAR_BIT (0x00000002)
+
+#define IRQ_CLEAR_TXDFE_WIN_OFF_IRQ_STATUS_CLEAR_LSB (0)
+#define IRQ_CLEAR_TXDFE_WIN_OFF_IRQ_STATUS_CLEAR_WIDTH (1)
+#define IRQ_CLEAR_TXDFE_WIN_OFF_IRQ_STATUS_CLEAR_MASK (0x00000001)
+#define IRQ_CLEAR_TXDFE_WIN_OFF_IRQ_STATUS_CLEAR_BIT (0x00000001)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_LSB (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_WIDTH (1)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_MASK (0x00000010)
+#define TXDFE_BB_TEST_SEL_RG_TEST_EN_BIT (0x00000010)
+
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_LSB (0)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_WIDTH (4)
+#define TXDFE_BB_TEST_SEL_RG_TEST_SEL_MASK (0x0000000F)
+
+#define TXDFE_BB_DBG_0_RG_DBG_0_LSB (0)
+#define TXDFE_BB_DBG_0_RG_DBG_0_WIDTH (32)
+#define TXDFE_BB_DBG_0_RG_DBG_0_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_1_RG_DBG_1_LSB (0)
+#define TXDFE_BB_DBG_1_RG_DBG_1_WIDTH (32)
+#define TXDFE_BB_DBG_1_RG_DBG_1_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_2_RG_DBG_2_LSB (0)
+#define TXDFE_BB_DBG_2_RG_DBG_2_WIDTH (32)
+#define TXDFE_BB_DBG_2_RG_DBG_2_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_3_RG_DBG_3_LSB (0)
+#define TXDFE_BB_DBG_3_RG_DBG_3_WIDTH (32)
+#define TXDFE_BB_DBG_3_RG_DBG_3_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_4_RG_DBG_4_LSB (0)
+#define TXDFE_BB_DBG_4_RG_DBG_4_WIDTH (32)
+#define TXDFE_BB_DBG_4_RG_DBG_4_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_5_RG_DBG_5_LSB (0)
+#define TXDFE_BB_DBG_5_RG_DBG_5_WIDTH (32)
+#define TXDFE_BB_DBG_5_RG_DBG_5_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_6_RG_DBG_6_LSB (0)
+#define TXDFE_BB_DBG_6_RG_DBG_6_WIDTH (32)
+#define TXDFE_BB_DBG_6_RG_DBG_6_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_7_RG_DBG_7_LSB (0)
+#define TXDFE_BB_DBG_7_RG_DBG_7_WIDTH (32)
+#define TXDFE_BB_DBG_7_RG_DBG_7_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_8_RG_DBG_8_LSB (0)
+#define TXDFE_BB_DBG_8_RG_DBG_8_WIDTH (32)
+#define TXDFE_BB_DBG_8_RG_DBG_8_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_9_RG_DBG_9_LSB (0)
+#define TXDFE_BB_DBG_9_RG_DBG_9_WIDTH (32)
+#define TXDFE_BB_DBG_9_RG_DBG_9_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_10_RG_DBG_10_LSB (0)
+#define TXDFE_BB_DBG_10_RG_DBG_10_WIDTH (32)
+#define TXDFE_BB_DBG_10_RG_DBG_10_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_11_RG_DBG_11_LSB (0)
+#define TXDFE_BB_DBG_11_RG_DBG_11_WIDTH (32)
+#define TXDFE_BB_DBG_11_RG_DBG_11_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_12_RG_DBG_12_LSB (0)
+#define TXDFE_BB_DBG_12_RG_DBG_12_WIDTH (32)
+#define TXDFE_BB_DBG_12_RG_DBG_12_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_13_RG_DBG_13_LSB (0)
+#define TXDFE_BB_DBG_13_RG_DBG_13_WIDTH (32)
+#define TXDFE_BB_DBG_13_RG_DBG_13_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_14_RG_DBG_14_LSB (0)
+#define TXDFE_BB_DBG_14_RG_DBG_14_WIDTH (32)
+#define TXDFE_BB_DBG_14_RG_DBG_14_MASK (0xFFFFFFFF)
+
+#define TXDFE_BB_DBG_15_RG_DBG_15_LSB (0)
+#define TXDFE_BB_DBG_15_RG_DBG_15_WIDTH (32)
+#define TXDFE_BB_DBG_15_RG_DBG_15_MASK (0xFFFFFFFF)
+
+#define FIR_SUP_CON_G0_PART0_FIR_SUP_LEN_CTRL_G0_PART0_LSB (0)
+#define FIR_SUP_CON_G0_PART0_FIR_SUP_LEN_CTRL_G0_PART0_WIDTH (32)
+#define FIR_SUP_CON_G0_PART0_FIR_SUP_LEN_CTRL_G0_PART0_MASK (0xFFFFFFFF)
+
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_SEM_CTRL_LSB (22)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_SEM_CTRL_WIDTH (1)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_SEM_CTRL_MASK (0x00400000)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_SEM_CTRL_BIT (0x00400000)
+
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_GAIN_G0_LSB (10)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_GAIN_G0_WIDTH (12)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_GAIN_G0_MASK (0x003FFC00)
+
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_LEN_CTRL_G0_PART1_LSB (0)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_LEN_CTRL_G0_PART1_WIDTH (3)
+#define FIR_SUP_CON_G0_PART1_FIR_SUP_LEN_CTRL_G0_PART1_MASK (0x00000007)
+
+#define TXDFE_WIN_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_LSB (0)
+#define TXDFE_WIN_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_WIDTH (4)
+#define TXDFE_WIN_REG_PROTECT_RG_TXDFE_BB_ACCESS_RIGHT_MASK (0x0000000F)
+
+#define TQ_0_CON_RG_TQ_0_TRG_LSB (0)
+#define TQ_0_CON_RG_TQ_0_TRG_WIDTH (1)
+#define TQ_0_CON_RG_TQ_0_TRG_MASK (0x00000001)
+
+#define TQ_0_CON_RG_TQ_0_RST_LSB (1)
+#define TQ_0_CON_RG_TQ_0_RST_WIDTH (1)
+#define TQ_0_CON_RG_TQ_0_RST_MASK (0x00000002)
+
+#define TQ_0_CON_RG_G0_LSB (2)
+#define TQ_0_CON_RG_G0_WIDTH (12)
+#define TQ_0_CON_RG_G0_MASK (0x000007FC)
+
+#define SERDES_PRE_EN_ON_0_LSB (0)
+#define SERDES_PRE_EN_ON_0_WIDTH (21)
+#define SERDES_PRE_EN_ON_0_MASK (0x0001FFFF)
+
+#define SERDES_EN_OFF_0_LSB (0)
+#define SERDES_EN_OFF_0_WIDTH (21)
+#define SERDES_EN_OFF_0_MASK (0x0001FFFF)
+
+#define SERDES_EN_ON_OFFSET_LSB (0)
+#define SERDES_EN_ON_OFFSET_WIDTH (10)
+#define SERDES_EN_ON_OFFSET_MASK (0x000003FF)
+
+#define SERDES_PRE_EN_OFF_OFFSET_LSB (0)
+#define SERDES_PRE_EN_OFF_OFFSET_WIDTH (10)
+#define SERDES_PRE_EN_OFF_OFFSET_MASK (0x000003FF)
+
+#define SERDES_WIN_ENABLE_SERDES_PRE_EN_ON_0_ENABLE_LSB (0)
+#define SERDES_WIN_ENABLE_SERDES_PRE_EN_ON_0_ENABLE_WIDTH (1)
+#define SERDES_WIN_ENABLE_SERDES_PRE_EN_ON_0_ENABLE_MASK (0x00000001)
+
+#define SERDES_WIN_ENABLE_SERDES_EN_OFF_0_ENABLE_LSB (6)
+#define SERDES_WIN_ENABLE_SERDES_EN_OFF_0_ENABLE_WIDTH (1)
+#define SERDES_WIN_ENABLE_SERDES_EN_OFF_0_ENABLE_MASK (0x00000040)
+
+#define TXDFE_D_SERDES_PRE_EN_0_SW_LSB (0)
+#define TXDFE_D_SERDES_PRE_EN_0_SW_WIDTH (1)
+#define TXDFE_D_SERDES_PRE_EN_0_SW_MASK (0x00000001)
+
+#define TXDFE_D_SERDES_EN_0_SW_LSB (0)
+#define TXDFE_D_SERDES_EN_0_SW_WIDTH (1)
+#define TXDFE_D_SERDES_EN_0_SW_MASK (0x00000001)
+
+#define TXDFE_D_DFE_WIN_0_SW_LSB (0)
+#define TXDFE_D_DFE_WIN_0_SW_WIDTH (1)
+#define TXDFE_D_DFE_WIN_0_SW_MASK (0x00000001)
+
+
+
+#endif //#define _CPH_TXDFE_BB_D_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl.h
new file mode 100644
index 0000000..fd92af6
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphtxsysglbconfig0reg_resctrl_93.h"
+#elif defined(__MD95__)
+#include "cphtxsysglbconfigreg0_95.h"
+#elif defined(__MD97__) || defined(__MD97P__)
+#include "cphdfesysglbconfigreg0.h"
+#else
+#include "cphdfesysglbconfigreg0.h"/*#error "[ERROR] Invalid MD generation" For build error*/
+#endif
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_93.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_93.h
new file mode 100644
index 0000000..25f9c96
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_93.h
@@ -0,0 +1,271 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CON0_REG_RC_H_
+#define _CPH_TXSYS_GLB_CON0_REG_RC_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG0_REG_BASE (0xA8190000)
+
+#define TXSYS_GLB_CON_CONFIG0_end (TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100 + 1*4)
+
+
+
+#define DIV_TXBRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))
+#define DIV_TXCRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))
+#define BUS_TXBRP_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x000c))
+#define TXSYS_CK_DIV_DBG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0018))
+#define DEBUG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))
+#define DEBUG_WITH_CK ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))
+#define TXSYS_DEBUG_BUS ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))
+#define TXBRP_CC0_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))
+#define TXBRP_CC1_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0030))
+#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))
+#define TXBRP0_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))
+#define TXBRP1_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x003c))
+#define TXBRP_CC0_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))
+#define TXBRP_CC1_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0050))
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0054))
+#define MASK_TXCRP_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0058))
+#define MASK_TXBRP_MAS_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x005c))
+#define MASK_TXBRP_SLV_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0060))
+#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))
+#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))
+#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))
+#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))
+#define TXCRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))
+#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))
+#define SW_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x007c))
+#define MASK_MDAO_TXSYS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0080))
+#define R2TX_SW_DISABLE_HW ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))
+
+
+#define DIV_TXBRP_DIV_TXBRP_LSB (0)
+#define DIV_TXBRP_DIV_TXBRP_WIDTH (2)
+#define DIV_TXBRP_DIV_TXBRP_MASK (0x00000003)
+
+#define DIV_TXCRP_DIV_TXCRP_LSB (0)
+#define DIV_TXCRP_DIV_TXCRP_WIDTH (2)
+#define DIV_TXCRP_DIV_TXCRP_MASK (0x00000003)
+
+#define BUS_TXBRP_SW_CKCTRL_BUS_TXBRP_SW_CKCTRL_LSB (0)
+#define BUS_TXBRP_SW_CKCTRL_BUS_TXBRP_SW_CKCTRL_WIDTH (1)
+#define BUS_TXBRP_SW_CKCTRL_BUS_TXBRP_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXBRP_SW_CKCTRL_BUS_TXBRP_SW_CKCTRL_BIT (0x00000001)
+
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_LSB (0)
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_WIDTH (3)
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_MASK (0x00000007)
+
+#define DEBUG_SEL_DEBUG_SEL_3_LSB (24)
+#define DEBUG_SEL_DEBUG_SEL_3_WIDTH (4)
+#define DEBUG_SEL_DEBUG_SEL_3_MASK (0x0F000000)
+
+#define DEBUG_SEL_DEBUG_SEL_2_LSB (16)
+#define DEBUG_SEL_DEBUG_SEL_2_WIDTH (4)
+#define DEBUG_SEL_DEBUG_SEL_2_MASK (0x000F0000)
+
+#define DEBUG_SEL_DEBUG_SEL_1_LSB (8)
+#define DEBUG_SEL_DEBUG_SEL_1_WIDTH (4)
+#define DEBUG_SEL_DEBUG_SEL_1_MASK (0x00000F00)
+
+#define DEBUG_SEL_DEBUG_SEL_0_LSB (0)
+#define DEBUG_SEL_DEBUG_SEL_0_WIDTH (4)
+#define DEBUG_SEL_DEBUG_SEL_0_MASK (0x0000000F)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_WIDTH (4)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_MASK (0x0000000F)
+
+#define DEBUG_WITH_CK_DEBUG_WITH_CK_LSB (0)
+#define DEBUG_WITH_CK_DEBUG_WITH_CK_WIDTH (5)
+#define DEBUG_WITH_CK_DEBUG_WITH_CK_MASK (0x0000001F)
+
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define TXBRP_CC0_SW_CKEN_TXBRP_CC0_SW_CKEN_LSB (0)
+#define TXBRP_CC0_SW_CKEN_TXBRP_CC0_SW_CKEN_WIDTH (1)
+#define TXBRP_CC0_SW_CKEN_TXBRP_CC0_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC0_SW_CKEN_TXBRP_CC0_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_LSB (0)
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_BIT (0x00000001)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_LSB (8)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_WIDTH (11)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_LSB (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_WIDTH (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_LSB (1)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_WIDTH (3)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_MASK (0x0000000E)
+
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_LSB (0)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_WIDTH (1)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_MASK (0x00000001)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_BIT (0x00000001)
+
+#define TXBRP0_SW_RESET_TXBRP0_TXBRP_SW_RESET_LSB (16)
+#define TXBRP0_SW_RESET_TXBRP0_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP0_SW_RESET_TXBRP0_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP0_SW_RESET_TXBRP0_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP0_SW_RESET_TXBRP0_TXSRP_SW_RESET_LSB (0)
+#define TXBRP0_SW_RESET_TXBRP0_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP0_SW_RESET_TXBRP0_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP0_SW_RESET_TXBRP0_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP1_SW_RESET_TXBRP1_TXBRP_SW_RESET_LSB (16)
+#define TXBRP1_SW_RESET_TXBRP1_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP1_SW_RESET_TXBRP1_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP1_SW_RESET_TXBRP1_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP1_SW_RESET_TXBRP1_TXSRP_SW_RESET_LSB (0)
+#define TXBRP1_SW_RESET_TXBRP1_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP1_SW_RESET_TXBRP1_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP1_SW_RESET_TXBRP1_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP_CC0_BUS_CK_SW_CKEN_TXBRP_CC0_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_TXBRP_CC0_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_TXBRP_CC0_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_TXBRP_CC0_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXCRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_LSB (0)
+#define MASK_TXCRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXCRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXCRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_LSB (0)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_BIT (0x00000001)
+
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_LSB (0)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_BIT (0x00000001)
+
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_LSB (0)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_WIDTH (1)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_MASK (0x00000001)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_LSB (0)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_WIDTH (1)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_LSB (0)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_WIDTH (1)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_LSB (0)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_WIDTH (1)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_LSB (0)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_WIDTH (1)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_LSB (0)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_LSB (0)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_WIDTH (1)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_MASK (0x00000001)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_LSB (0)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_WIDTH (1)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_MASK (0x00000001)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_BIT (0x00000001)
+
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_LSB (0)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_WIDTH (1)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_MASK (0x00000001)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_BIT (0x00000001)
+
+
+#endif /*#ifndef _CPH_TXSYS_GLB_CON0_REG_RC_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_95.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_95.h
new file mode 100644
index 0000000..d91cda8
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig0reg_resctrl_95.h
@@ -0,0 +1,271 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CON0_REG_RC_H_
+#define _CPH_TXSYS_GLB_CON0_REG_RC_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG0_REG_BASE (0xA8190000)
+
+#define TXSYS_GLB_CON_CONFIG0_end (TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100 + 1*4)
+
+
+
+#define DIV_TXBRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))
+#define DIV_TXCRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))
+#define BUS_TXBRP_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x000c))
+#define DUBUG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))
+#define DUBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0020))
+#define DUBUG_WITH_CK ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))
+#define TXSYS_DEBUG_BUS_CFG0 ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))
+#define TXBRP_CC_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))
+#define TXBRP_CC1_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0030))/*93stay*/
+#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))
+#define TXBRP_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))
+#define TXBRP1_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x003c))/*93stay*/
+#define TXBRP_CC_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))
+#define TX_SRP_CRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))
+#define TXBRP_CC_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))
+#define TX_SRP_CRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0050))/*93stay--*/
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0054))
+#define MASK_TXCRP_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0058))
+#define MASK_TXBRP_MAS_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x005c))
+#define MASK_TXBRP_SLV_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0060))/*--93stay*/
+#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))
+#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))
+#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))
+#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))
+#define TXCRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))
+#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))
+#define SW_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x007c))/*93stay--*/
+#define MASK_MDAO_TXSYS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0080))/*--93stay*/
+#define R2TX_SW_DISABLE_HW ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))
+
+
+#define DIV_TXBRP_LSB (0)
+#define DIV_TXBRP_WIDTH (1)
+#define DIV_TXBRP_MASK (0x00000001)
+
+#define DIV_TXCRP_LSB (0)
+#define DIV_TXCRP_WIDTH (2)
+#define DIV_TXCRP_MASK (0x00000003)
+
+#define BUS_TXBRP_SW_CKCTRL_LSB (0)
+#define BUS_TXBRP_SW_CKCTRL_WIDTH (1)
+#define BUS_TXBRP_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXBRP_SW_CKCTRL_BIT (0x00000001)
+
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_LSB (0)/*93stay--*/
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_WIDTH (3)
+#define TXSYS_CK_DIV_DBG_SEL_TXSYS_CK_DIV_DBG_SEL_MASK (0x00000007)/*--93stay*/
+
+#define DUBUG_SEL_3_LSB (24)
+#define DUBUG_SEL_3_WIDTH (4)
+#define DUBUG_SEL_3_MASK (0x0F000000)
+
+#define DUBUG_SEL_2_LSB (16)
+#define DUBUG_SEL_2_WIDTH (4)
+#define DUBUG_SEL_2_MASK (0x000F0000)
+
+#define DUBUG_SEL_1_LSB (8)
+#define DUBUG_SEL_1_WIDTH (4)
+#define DUBUG_SEL_1_MASK (0x00000F00)
+
+#define DUBUG_SEL_0_LSB (0)
+#define DUBUG_SEL_0_WIDTH (4)
+#define DUBUG_SEL_0_MASK (0x0000000F)
+
+#define DUBUG_TRIG_SEL_LSB (0)
+#define DUBUG_TRIG_SEL_WIDTH (1)
+#define DUBUG_TRIG_SEL_MASK (0x00000001)
+
+#define DUBUG_WITH_CK_LSB (0)
+#define DUBUG_WITH_CK_WIDTH (5)
+#define DUBUG_WITH_CK_MASK (0x0000001F)
+
+#define TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define TXBRP_CC_SW_CKEN_LSB (0)
+#define TXBRP_CC_SW_CKEN_WIDTH (1)
+#define TXBRP_CC_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_LSB (0)/*93stay--*/
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_SW_CKEN_TXBRP_CC1_SW_CKEN_BIT (0x00000001)/*--93stay*/
+
+#define SW_RAKE_DATA_LSB (8)
+#define SW_RAKE_DATA_WIDTH (11)
+#define SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define SW_RAKE_ADDR_LSB (4)
+#define SW_RAKE_ADDR_WIDTH (4)
+#define SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define SW_RAKE_RSV_LSB (1)
+#define SW_RAKE_RSV_WIDTH (3)
+#define SW_RAKE_RSV_MASK (0x0000000E)
+
+#define SW_VLD_TGL_LSB (0)
+#define SW_VLD_TGL_WIDTH (1)
+#define SW_VLD_TGL_MASK (0x00000001)
+#define SW_VLD_TGL_BIT (0x00000001)
+
+#define TXBRP_TXBRP_SW_RESET_LSB (16)
+#define TXBRP_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP_TXSRP_SW_RESET_LSB (0)
+#define TXBRP_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP_CC_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKEN_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKEN_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKEN_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_LSB (0)/*93stay--*/
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_TXBRP_CC1_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_TXBRP_CC0_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_TXBRP_CC1_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK_TXBRP0_BUS2X_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK_TXBRP1_BUS2X_CK_IDLE_DIV_BIT (0x00000001)/*--93stay*/
+
+#define TX_SRP_CRP_CK_SW_CKCTRL_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKCTRL_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_LSB (0)/*93stay--*/
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK_TXBRP_MAS_BUS_IDLE_BIT (0x00000001)
+
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_LSB (0)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK_TXBRP_SLV_BUS_IDLE_BIT (0x00000001)/*--93stay*/
+
+#define TXCRP_SP_WCRP_APB_SW_RESET_LSB (0)
+#define TXCRP_SP_WCRP_APB_SW_RESET_WIDTH (1)
+#define TXCRP_SP_WCRP_APB_SW_RESET_MASK (0x00000001)
+#define TXCRP_SP_WCRP_APB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_TAPB_SW_RESET_LSB (0)
+#define TXCRP_RG_TAPB_SW_RESET_WIDTH (1)
+#define TXCRP_RG_TAPB_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_TAPB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_C1X_SW_RESET_LSB (0)
+#define TXCRP_RG_C1X_SW_RESET_WIDTH (1)
+#define TXCRP_RG_C1X_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_C1X_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_CDO_SW_RESET_LSB (0)
+#define TXCRP_RG_CDO_SW_RESET_WIDTH (1)
+#define TXCRP_RG_CDO_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_CDO_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKEN_LSB (0)
+#define TXCRP_CK_SW_CKEN_WIDTH (1)
+#define TXCRP_CK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKCTRL_LSB (0)
+#define TXCRP_CK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_LSB (0)/*93stay--*/
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_WIDTH (1)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_MASK (0x00000001)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_LSB (0)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_WIDTH (1)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_MASK (0x00000001)
+#define MASK_MDAO_TXSYS_IDLE_MASK_MDAO_TXSYS_IDLE_BIT (0x00000001)/*--93stay*/
+
+#define R2TX_SW_DISABLE_HW_LSB (0)
+#define R2TX_SW_DISABLE_HW_WIDTH (1)
+#define R2TX_SW_DISABLE_HW_MASK (0x00000001)
+#define R2TX_SW_DISABLE_HW_BIT (0x00000001)
+
+
+#endif /*#ifndef _CPH_TXSYS_GLB_CON0_REG_RC_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl.h
new file mode 100644
index 0000000..c714ade
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphtxsysglbconfig1reg_resctrl_93.h"
+#elif defined(__MD95__)
+#include "cphtxsysglbconfig1reg_resctrl_95.h"
+#elif defined(__MD97__)
+#include "cphdfesysglbconfigreg1.h"
+#else
+#include "cphdfesysglbconfigreg1.h"/*#error "[ERROR] Invalid MD generation" For build error*/
+#endif
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_93.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_93.h
new file mode 100644
index 0000000..8828d1b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_93.h
@@ -0,0 +1,151 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CON1_REG_RC_H_
+#define _CPH_TXSYS_GLB_CON1_REG_RC_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG1_REG_BASE (0xA84f0000)
+
+#define TXSYS_GLB_CON_CONFIG1_end (TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0100 + 1*4)
+
+
+
+#define BUS_BUS2X_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0014))
+#define BUS_TXDFE_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0018))
+#define TXDFE_RF_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0024))
+#define TXDFE_BB_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x002c))
+#define TPC_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0030))
+#define TPC_F208M_BCLK_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0040))
+#define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x004c))
+#define TDD_TTR_F4P3M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0054))
+#define TXK_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x006c))
+//To remove the redefinition warning, the following 2 register are also defined in cphtxsysglbconfig1reg_resctrl.h, need to check with DE is the CODA correct
+//#define TXSYS_DEBUG_BUS ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0074))
+//#define DEBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0078))
+#define LTE_TTR0_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x007C))
+#define LTE_TTR1_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0084))
+#define INTRA_BAND_CA ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0100))
+
+
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_LSB (0)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_WIDTH (1)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_MASK (0x00000001)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_BIT (0x00000001)
+
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_LSB (0)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_WIDTH (1)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_BIT (0x00000001)
+
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_LSB (0)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_WIDTH (1)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_MASK (0x00000001)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_LSB (0)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_WIDTH (1)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_MASK (0x00000001)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_BIT (0x00000001)
+
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_LSB (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_MASK (0x00000002)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_BIT (0x00000002)
+
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_LSB (0)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_MASK (0x00000001)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_BIT (0x00000001)
+
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_LSB (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_MASK (0x00000002)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_BIT (0x00000002)
+
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_LSB (0)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_MASK (0x00000001)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_LSB (0)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_WIDTH (1)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_MASK (0x00000001)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_BIT (0x00000001)
+
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_LSB (0)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_WIDTH (1)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_MASK (0x00000001)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_BIT (0x00000001)
+
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_LSB (0)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_MASK (0x00000001)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_WIDTH (4)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_MASK (0x0000000F)
+
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_LSB (0)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_WIDTH (1)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_BIT (0x00000001)
+
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_LSB (0)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_WIDTH (1)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_BIT (0x00000001)
+
+#define INTRA_BAND_CA_INTRA_BAND_CA_LSB (0)
+#define INTRA_BAND_CA_INTRA_BAND_CA_WIDTH (2)
+#define INTRA_BAND_CA_INTRA_BAND_CA_MASK (0x00000003)
+
+
+#endif /*_CPH_TXSYS_GLB_CON1_REG_RC_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_95.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_95.h
new file mode 100644
index 0000000..8828d1b
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfig1reg_resctrl_95.h
@@ -0,0 +1,151 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CON1_REG_RC_H_
+#define _CPH_TXSYS_GLB_CON1_REG_RC_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG1_REG_BASE (0xA84f0000)
+
+#define TXSYS_GLB_CON_CONFIG1_end (TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0100 + 1*4)
+
+
+
+#define BUS_BUS2X_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0014))
+#define BUS_TXDFE_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0018))
+#define TXDFE_RF_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0024))
+#define TXDFE_BB_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x002c))
+#define TPC_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0030))
+#define TPC_F208M_BCLK_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0040))
+#define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x004c))
+#define TDD_TTR_F4P3M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0054))
+#define TXK_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x006c))
+//To remove the redefinition warning, the following 2 register are also defined in cphtxsysglbconfig1reg_resctrl.h, need to check with DE is the CODA correct
+//#define TXSYS_DEBUG_BUS ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0074))
+//#define DEBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0078))
+#define LTE_TTR0_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x007C))
+#define LTE_TTR1_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0084))
+#define INTRA_BAND_CA ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0100))
+
+
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_LSB (0)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_WIDTH (1)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_MASK (0x00000001)
+#define BUS_BUS2X_SW_CKCTRL_BUS_BUS2X_SW_CKCTRL_BIT (0x00000001)
+
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_LSB (0)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_WIDTH (1)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXDFE_SW_CKCTRL_BUS_TXDFE_SW_CKCTRL_BIT (0x00000001)
+
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_LSB (0)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_WIDTH (1)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_MASK (0x00000001)
+#define TXDFE_RF_CK_SW_CKEN_TXDFE_RF_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_LSB (0)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_WIDTH (1)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_MASK (0x00000001)
+#define TXDFE_BB_CK_SW_CKEN_TXDFE_BB_CK_SW_CKEN_BIT (0x00000001)
+
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_LSB (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_MASK (0x00000002)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_GATED_BCLK_CK_SW_CKEN_BIT (0x00000002)
+
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_LSB (0)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_MASK (0x00000001)
+#define TPC_F208M_BCLK_CK_SW_CKEN_TPC_F208M_BCLK_CK_SW_CKEN_BIT (0x00000001)
+
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_LSB (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_MASK (0x00000002)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_GATED_BCLK_CK_SW_CKCTRL_BIT (0x00000002)
+
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_LSB (0)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_WIDTH (1)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_MASK (0x00000001)
+#define TPC_F208M_BCLK_CK_SW_CKCTRL_TPC_F208M_BCLK_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_LSB (0)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_WIDTH (1)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_MASK (0x00000001)
+#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_BIT (0x00000001)
+
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_LSB (0)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_WIDTH (1)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_MASK (0x00000001)
+#define TDD_TTR_F4P3M_SW_CKEN_TDD_TTR_F4P3M_SW_CKEN_BIT (0x00000001)
+
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_LSB (0)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_WIDTH (1)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_MASK (0x00000001)
+#define TXK_F208M_BCLK_CK_SW_CKEN_TXK_F208M_BCLK_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_LSB (0)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_WIDTH (4)
+#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_MASK (0x0000000F)
+
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_LSB (0)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_WIDTH (1)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR0_F104M_SW_CKEN_LTE_TTR0_F104M_SW_CKEN_BIT (0x00000001)
+
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_LSB (0)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_WIDTH (1)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_MASK (0x00000001)
+#define LTE_TTR1_F104M_SW_CKEN_LTE_TTR1_F104M_SW_CKEN_BIT (0x00000001)
+
+#define INTRA_BAND_CA_INTRA_BAND_CA_LSB (0)
+#define INTRA_BAND_CA_INTRA_BAND_CA_WIDTH (2)
+#define INTRA_BAND_CA_INTRA_BAND_CA_MASK (0x00000003)
+
+
+#endif /*_CPH_TXSYS_GLB_CON1_REG_RC_H_*/
\ No newline at end of file
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0.h
new file mode 100644
index 0000000..5821576
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0.h
@@ -0,0 +1,42 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphtxsysglbconfigreg0_93.h"
+#elif defined(__MD95__)
+#include "cphtxsysglbconfigreg0_95.h"
+#else
+#error "[ERROR] Invalid MD generation" /* The module have delete in 97, which is moved to dfesysconfigreg0 module */
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_93.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_93.h
new file mode 100644
index 0000000..b38875c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_93.h
@@ -0,0 +1,246 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CONFIG_H_
+#define _CPH_TXSYS_GLB_CONFIG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG0_REG_BASE (0xA8190000)
+
+#define TXSYS_GLB_CON_CONFIG0_end (TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0060 + 1*4)
+
+
+
+#define DIV_TXBRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))
+#define DIV_TXCRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))
+#define BUS_TXBRP_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x000c))
+#define TXSYS_CK_DIV_DBG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0018))
+#define DUBUG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))
+#define DUBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0020))
+#define DUBUG_WITH_CK ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))
+#define TXSYS_DEBUG_BUS ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))
+#define TXBRP_CC0_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))
+#define TXBRP_CC1_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0030))
+#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))
+#define TXBRP0_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))
+#define TXBRP1_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x003c))
+#define TXBRP_CC0_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))
+#define TXBRP_CC1_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0050))
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0054))
+#define MASK_TXCRP_CK_IDLE_DIV ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0058))
+#define MASK_TXBRP_MAS_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x005c))
+#define MASK_TXBRP_SLV_BUS_IDLE ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0060))
+#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))
+#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))
+#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))
+#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))
+#define TXCRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))
+#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))
+#define R2TX_SW_DISABLE_HW ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))
+
+
+#define DIV_TXBRP_LSB (0)
+#define DIV_TXBRP_WIDTH (2)
+#define DIV_TXBRP_MASK (0x00000003)
+
+#define DIV_TXCRP_LSB (0)
+#define DIV_TXCRP_WIDTH (2)
+#define DIV_TXCRP_MASK (0x00000003)
+
+#define BUS_TXBRP_SW_CKCTRL_LSB (0)
+#define BUS_TXBRP_SW_CKCTRL_WIDTH (1)
+#define BUS_TXBRP_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXBRP_SW_CKCTRL_BIT (0x00000001)
+
+#define TXSYS_CK_DIV_DBG_SEL_LSB (0)
+#define TXSYS_CK_DIV_DBG_SEL_WIDTH (2)
+#define TXSYS_CK_DIV_DBG_SEL_MASK (0x00000003)
+
+#define DUBUG_SEL_3_LSB (24)
+#define DUBUG_SEL_3_WIDTH (4)
+#define DUBUG_SEL_3_MASK (0x0F000000)
+
+#define DUBUG_SEL_2_LSB (16)
+#define DUBUG_SEL_2_WIDTH (4)
+#define DUBUG_SEL_2_MASK (0x000F0000)
+
+#define DUBUG_SEL_1_LSB (8)
+#define DUBUG_SEL_1_WIDTH (4)
+#define DUBUG_SEL_1_MASK (0x00000F00)
+
+#define DUBUG_SEL_0_LSB (0)
+#define DUBUG_SEL_0_WIDTH (4)
+#define DUBUG_SEL_0_MASK (0x0000000F)
+
+#define DUBUG_TRIG_SEL_LSB (0)
+#define DUBUG_TRIG_SEL_WIDTH (4)
+#define DUBUG_TRIG_SEL_MASK (0x0000000F)
+
+#define DUBUG_WITH_CK_LSB (0)
+#define DUBUG_WITH_CK_WIDTH (5)
+#define DUBUG_WITH_CK_MASK (0x0000001F)
+
+#define TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define TXBRP_CC0_SW_CKEN_LSB (0)
+#define TXBRP_CC0_SW_CKEN_WIDTH (1)
+#define TXBRP_CC0_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC0_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC1_SW_CKEN_LSB (0)
+#define TXBRP_CC1_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_SW_CKEN_BIT (0x00000001)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_LSB (8)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_WIDTH (11)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_LSB (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_WIDTH (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_LSB (1)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_WIDTH (3)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_MASK (0x0000000E)
+
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_LSB (0)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_WIDTH (1)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_MASK (0x00000001)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_BIT (0x00000001)
+
+#define SW_RAKE_DATA_LSB (8)
+#define SW_RAKE_DATA_WIDTH (11)
+#define SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define SW_RAKE_ADDR_LSB (4)
+#define SW_RAKE_ADDR_WIDTH (4)
+#define SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define SW_RAKE_RSV_LSB (1)
+#define SW_RAKE_RSV_WIDTH (3)
+#define SW_RAKE_RSV_MASK (0x0000000E)
+
+#define SW_VLD_TGL_LSB (0)
+#define SW_VLD_TGL_WIDTH (1)
+#define SW_VLD_TGL_MASK (0x00000001)
+#define SW_VLD_TGL_BIT (0x00000001)
+
+#define TXBRP0_TXBRP_SW_RESET_LSB (16)
+#define TXBRP0_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP0_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP0_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP0_TXSRP_SW_RESET_LSB (0)
+#define TXBRP0_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP0_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP0_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP1_TXBRP_SW_RESET_LSB (16)
+#define TXBRP1_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP1_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP1_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP1_TXSRP_SW_RESET_LSB (0)
+#define TXBRP1_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP1_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP1_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP_CC0_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC0_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC0_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC1_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP0_BUS2X_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBRP1_BUS2X_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXCRP_CK_IDLE_DIV_LSB (0)
+#define MASK_TXCRP_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXCRP_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXCRP_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBRP_MAS_BUS_IDLE_LSB (0)
+#define MASK_TXBRP_MAS_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_MAS_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_MAS_BUS_IDLE_BIT (0x00000001)
+
+#define MASK_TXBRP_SLV_BUS_IDLE_LSB (0)
+#define MASK_TXBRP_SLV_BUS_IDLE_WIDTH (1)
+#define MASK_TXBRP_SLV_BUS_IDLE_MASK (0x00000001)
+#define MASK_TXBRP_SLV_BUS_IDLE_BIT (0x00000001)
+
+#define R2TX_SW_DISABLE_HW_LSB (0)
+#define R2TX_SW_DISABLE_HW_WIDTH (1)
+#define R2TX_SW_DISABLE_HW_MASK (0x00000001)
+#define R2TX_SW_DISABLE_HW_BIT (0x00000001)
+
+#endif //#ifndef _CPH_TXSYS_GLB_CONFIG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_95.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_95.h
new file mode 100644
index 0000000..892fb10
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg0_95.h
@@ -0,0 +1,221 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLB_CONFIG_H_
+#define _CPH_TXSYS_GLB_CONFIG_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG0_REG_BASE (0xA8190000)
+
+#define TXSYS_GLB_CON_CONFIG0_end (TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100 + 1*4)
+
+
+#define DIV_TXBRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))
+#define DIV_TXCRP ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))
+#define BUS_TXBRP_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x000c))
+#define DUBUG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))
+#define DUBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0020))
+#define DUBUG_WITH_CK ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))
+#define TXSYS_DEBUG_BUS_CFG0 ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))
+#define TXBRP_CC_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))
+#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))
+#define TXBRP_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))
+#define TXBRP_CC_BUS_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))
+#define TX_SRP_CRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))
+#define TXBRP_CC_BUS_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))
+#define TX_SRP_CRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))
+#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))
+#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))
+#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))
+#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))
+#define TXCRP_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))
+#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))
+#define R2TX_SW_DISABLE_HW ((APBADDR32)(TXSYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))
+
+#define DIV_TXBRP_LSB (0)
+#define DIV_TXBRP_WIDTH (1)
+#define DIV_TXBRP_MASK (0x00000001)
+
+#define DIV_TXCRP_LSB (0)
+#define DIV_TXCRP_WIDTH (2)
+#define DIV_TXCRP_MASK (0x00000003)
+
+#define BUS_TXBRP_SW_CKCTRL_LSB (0)
+#define BUS_TXBRP_SW_CKCTRL_WIDTH (1)
+#define BUS_TXBRP_SW_CKCTRL_MASK (0x00000001)
+#define BUS_TXBRP_SW_CKCTRL_BIT (0x00000001)
+
+#define DUBUG_SEL_3_LSB (24)
+#define DUBUG_SEL_3_WIDTH (4)
+#define DUBUG_SEL_3_MASK (0x0F000000)
+
+#define DUBUG_SEL_2_LSB (16)
+#define DUBUG_SEL_2_WIDTH (4)
+#define DUBUG_SEL_2_MASK (0x000F0000)
+
+#define DUBUG_SEL_1_LSB (8)
+#define DUBUG_SEL_1_WIDTH (4)
+#define DUBUG_SEL_1_MASK (0x00000F00)
+
+#define DUBUG_SEL_0_LSB (0)
+#define DUBUG_SEL_0_WIDTH (4)
+#define DUBUG_SEL_0_MASK (0x0000000F)
+
+#define DUBUG_TRIG_SEL_LSB (0)
+#define DUBUG_TRIG_SEL_WIDTH (1)
+#define DUBUG_TRIG_SEL_MASK (0x00000001)
+
+#define DUBUG_WITH_CK_LSB (0)
+#define DUBUG_WITH_CK_WIDTH (5)
+#define DUBUG_WITH_CK_MASK (0x0000001F)
+
+#define TXSYS_DEBUG_BUS_LSB (0)
+#define TXSYS_DEBUG_BUS_WIDTH (32)
+#define TXSYS_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define TXBRP_CC_SW_CKEN_LSB (0)
+#define TXBRP_CC_SW_CKEN_WIDTH (1)
+#define TXBRP_CC_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC_SW_CKEN_BIT (0x00000001)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_LSB (8)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_WIDTH (11)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_LSB (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_WIDTH (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_LSB (1)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_WIDTH (3)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_MASK (0x0000000E)
+
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_LSB (0)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_WIDTH (1)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_MASK (0x00000001)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_BIT (0x00000001)
+
+#define SW_RAKE_DATA_LSB (8)
+#define SW_RAKE_DATA_WIDTH (11)
+#define SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define SW_RAKE_ADDR_LSB (4)
+#define SW_RAKE_ADDR_WIDTH (4)
+#define SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define SW_RAKE_RSV_LSB (1)
+#define SW_RAKE_RSV_WIDTH (3)
+#define SW_RAKE_RSV_MASK (0x0000000E)
+
+#define SW_VLD_TGL_LSB (0)
+#define SW_VLD_TGL_WIDTH (1)
+#define SW_VLD_TGL_MASK (0x00000001)
+#define SW_VLD_TGL_BIT (0x00000001)
+
+#define TXBRP_TXBRP_SW_RESET_LSB (16)
+#define TXBRP_TXBRP_SW_RESET_WIDTH (1)
+#define TXBRP_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBRP_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBRP_TXSRP_SW_RESET_LSB (0)
+#define TXBRP_TXSRP_SW_RESET_WIDTH (1)
+#define TXBRP_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBRP_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBRP_CC_BUS_CK_SW_CKEN_LSB (0)
+#define TXBRP_CC_BUS_CK_SW_CKEN_WIDTH (1)
+#define TXBRP_CC_BUS_CK_SW_CKEN_MASK (0x00000001)
+#define TXBRP_CC_BUS_CK_SW_CKEN_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKEN_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKEN_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKEN_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBRP_CC_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKCTRL_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKCTRL_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXCRP_SP_WCRP_APB_SW_RESET_LSB (0)
+#define TXCRP_SP_WCRP_APB_SW_RESET_WIDTH (1)
+#define TXCRP_SP_WCRP_APB_SW_RESET_MASK (0x00000001)
+#define TXCRP_SP_WCRP_APB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_TAPB_SW_RESET_LSB (0)
+#define TXCRP_RG_TAPB_SW_RESET_WIDTH (1)
+#define TXCRP_RG_TAPB_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_TAPB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_C1X_SW_RESET_LSB (0)
+#define TXCRP_RG_C1X_SW_RESET_WIDTH (1)
+#define TXCRP_RG_C1X_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_C1X_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_CDO_SW_RESET_LSB (0)
+#define TXCRP_RG_CDO_SW_RESET_WIDTH (1)
+#define TXCRP_RG_CDO_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_CDO_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKEN_LSB (0)
+#define TXCRP_CK_SW_CKEN_WIDTH (1)
+#define TXCRP_CK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKCTRL_LSB (0)
+#define TXCRP_CK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define R2TX_SW_DISABLE_HW_LSB (0)
+#define R2TX_SW_DISABLE_HW_WIDTH (1)
+#define R2TX_SW_DISABLE_HW_MASK (0x00000001)
+#define R2TX_SW_DISABLE_HW_BIT (0x00000001)
+#endif //#ifndef _CPH_TXSYS_GLB_CONFIG_H_
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1.h
new file mode 100644
index 0000000..0ce6366
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#if defined(__MD93__)
+#include "cphtxsysglbconfigreg1_93.h"
+#elif defined(__MD95__)
+#include "cphtxsysglbconfigreg1_95.h"
+#else
+#error "[ERROR] Invalid MD generation" /* The module have delete in 97, which is moved to dfesysconfigreg1 module */
+#endif
+
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_93.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_93.h
new file mode 100644
index 0000000..33613b0
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_93.h
@@ -0,0 +1,82 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLBCON_CONFIG1_H_
+#define _CPH_TXSYS_GLBCON_CONFIG1_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG1_REG_BASE (0xA84f0000)
+
+
+#define TXSYS_GLB_CON_CONFIG1_end (TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0088)
+
+
+
+
+#define BUS_BUS_2X_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0014))
+#define BUS_TXDFE_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0018))
+#define TXDFE_RF_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0024))
+#define TXDFE_RF_BBTX_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0028))
+#define TXDFE_BB_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x002C))
+#define TPC_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0030))
+#define TXDFE_RF_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0034))
+#define TXDFE_RF_BBTX_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0038))
+#define TXDFE_BB_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x003c))
+#define TPC_F208M_BCLK_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0040))
+#define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x004c))
+#define FDD_TTR_F13M_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0050))
+#define TDD_TTR_F4P3M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0054))
+#define TDD_TTR_F4P3M_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0058))
+#define TXK_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x006c))
+#define TXK_F208M_BCLK_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0070))
+#define TXSYS_DEBUG_BUS_CFG1 ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0074))
+#define LTE_TTR0_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x007c))
+#define LTE_TTR0_F104M_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0080))
+#define LTE_TTR1_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0084))
+#define LTE_TTR1_F104M_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0088))
+#define INTRA_BAND_CA ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0100))
+
+#endif
+
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_95.h b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_95.h
new file mode 100644
index 0000000..7cc1592
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphtxsysglbconfigreg1_95.h
@@ -0,0 +1,79 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_TXSYS_GLBCON_CONFIG1_H_
+#define _CPH_TXSYS_GLBCON_CONFIG1_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define TXSYS_GLB_CON_CONFIG1_REG_BASE (0xA84f0000)
+
+
+#define TXSYS_GLB_CON_CONFIG1_end (TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0094 + 1*4)
+
+
+
+
+#define BUS_BUS_2X_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0014))
+#define BUS_TXDFE_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0018))
+#define TXDFE_RF_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0024))
+#define TXDFE_BB_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x002C))
+#define TPC_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0030))
+#define TPC_F208M_BCLK_CK_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0040))
+#define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x004c))
+#define TDD_TTR_F4P3M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0054))
+#define TXK_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x006c))
+#define TXET_F208M_BCLK_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0070))
+#define TXSYS_DEBUG_BUS_CFG1 ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0074))
+#define TXSYS_DEBUG_TRIG_SEL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0078))
+#define LTE_TTR0_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x007c))
+#define LTE_TTR1_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0084))
+#define LTE_TTR2_F104M_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0088))
+#define AMSC_REF_B0_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x008c))
+#define AMSC_REF_B1_SW_CKCTRL ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0090))
+#define AMSC_CK_SW_CKEN ((APBADDR32)(TXSYS_GLB_CON_CONFIG1_REG_BASE + 0x0094))
+
+
+#endif
+