[Feature]Upload Modem source code

Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/cl1/common/HW/cph1xtxtmr.h b/mcu/interface/l1/cl1/common/HW/cph1xtxtmr.h
new file mode 100644
index 0000000..5e2849a
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cph1xtxtmr.h
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+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2016
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_1X_TXTRM_H_
+#define _CPH_1X_TX_TRM_H_
+typedef volatile unsigned short* SRAMADDR;         /* SRAM addr is 16 bits  */
+typedef volatile unsigned short  SRAMDATA;         /* SRAM data is 16 bits  */
+typedef volatile unsigned short* APBADDR;          /* APB addr is 16 bits   */
+typedef volatile unsigned short  APBDATA;          /* APB data is 16 bits   */
+typedef volatile unsigned long*  APBADDR32;        /* APB addr is 32 bits   */
+typedef volatile unsigned long   APBDATA32;        /* APB data is 32 bits   */
+typedef volatile unsigned short* DPRAMADDR;        /* DPRAM addr is 16 bits */
+typedef volatile signed   short* DPRAMADDR_S;      /* DPRAM addr is 16 bits */
+typedef volatile unsigned short  DPRAMDATA;        /* DPRAM data is 16 bits */
+
+#define TXTMR_C_1XRTT_REG_BASE                               (0) /**TBD*/
+    
+#define C1XTXTMR_ENABLE                                      ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0000))
+#define C1XTXTMR_FRAME_OFFSET                                ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0004))
+#define C1XTXTMR_TRX_DLY                                     ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0008))
+#define C1XTXTMR_RA_DLY                                      ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x000C))
+#define C1XTXTMR_TXDFE_WIN_ON_OFFSET                         ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0010))
+#define C1XTXTMR_TXDFE_WIN_OFF_OFFSET                        ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0014))
+#define C1XTXTMR_TXDFE_FIFO_WIN_ON_OFFSET                    ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0018))
+#define C1XTXTMR_TXDFE_FIFO_WIN_OFF_OFFSET                   ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x001C))
+#define C1XTXTMR_TXDAC_WIN_ON_OFFSET                         ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0020))
+#define C1XTXTMR_TXDAC_WIN_OFF_OFFSET                        ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0024))
+#define C1XTXTMR_TXBRP_STR                                   ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0028))
+#define C1XTXTMR_TXCRP_STR                                   ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x002C))
+#define C1XTXTMR_KS_STR                                      ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0030))
+#define C1XTXTMR_SYSTMR_CNT                                  ((APBADDR32)(TXTMR_C_1XRTT_REG_BASE + 0x0034))
+
+
+#endif