[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/cl1/common/HW/cphc2krxdfe.h b/mcu/interface/l1/cl1/common/HW/cphc2krxdfe.h
new file mode 100644
index 0000000..b5c6e49
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphc2krxdfe.h
@@ -0,0 +1,1229 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_C2K_RXDFE_H_
+#define _CPH_C2K_RXDFE_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE_FC_ACT_REG_BASE (0xA70C0000)
+
+#define RXDFE_FC_ACT_end (RXDFE_FC_ACT_REG_BASE + 0x01A0 + 1*4)
+
+
+
+#define RXDFE_FC_P_SWAP ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0000))
+#define RXDFE_FC_A_SWAP_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0004))
+#define RXDFE_FC_MS_WB_0_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0008))
+#define RXDFE_FC_MS_WB_1_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x000C))
+#define RXDFE_FC_A_SWAP_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0010))
+#define RXDFE_FC_MS_WB_0_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0014))
+#define RXDFE_FC_MS_WB_1_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0018))
+#define RXDFE_FC_P_CON_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x001C))
+#define RXDFE_FC_SW_DCOC_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0020))
+#define RXDFE_FC_P_CON_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0024))
+#define RXDFE_FC_SW_DCOC_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0028))
+#define RXDFE_FC_P_CON_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x002C))
+#define RXDFE_FC_SW_DCOC_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0030))
+#define RXDFE_FC_P_CON_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0034))
+#define RXDFE_FC_SW_DCOC_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0038))
+#define RXDFE_FC_C_CON_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x003C))
+#define RXDFE_FC_SW_DAGC_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0040))
+#define RXDFE_FC_SW_CS_DAGC_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0044))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0048))
+#define RXDFE_FC_C_CON_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x004C))
+#define RXDFE_FC_SW_DAGC_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0050))
+#define RXDFE_FC_SW_CS_DAGC_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0054))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0058))
+#define RXDFE_FC_C_CON_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x005C))
+#define RXDFE_FC_SW_DAGC_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0060))
+#define RXDFE_FC_SW_CS_DAGC_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0064))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0068))
+#define RXDFE_FC_C_CON_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x006C))
+#define RXDFE_FC_SW_DAGC_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0070))
+#define RXDFE_FC_SW_CS_DAGC_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0074))
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0078))
+#define RXDFE_FC_FDPM_0_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x007C))
+#define RXDFE_FC_FDPM_1_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0080))
+#define RXDFE_FC_FDPM_2_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0084))
+#define RXDFE_FC_RFEQ_0_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0088))
+#define RXDFE_FC_RFEQ_1_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x008C))
+#define RXDFE_FC_RFEQ_2_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0090))
+#define RXDFE_FC_RFEQ_3_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0094))
+#define RXDFE_FC_RFEQ_4_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0098))
+#define RXDFE_FC_IQC_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x009C))
+#define RXDFE_FC_FDPM_0_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A0))
+#define RXDFE_FC_FDPM_1_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A4))
+#define RXDFE_FC_FDPM_2_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A8))
+#define RXDFE_FC_RFEQ_0_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00AC))
+#define RXDFE_FC_RFEQ_1_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B0))
+#define RXDFE_FC_RFEQ_2_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B4))
+#define RXDFE_FC_RFEQ_3_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B8))
+#define RXDFE_FC_RFEQ_4_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00BC))
+#define RXDFE_FC_IQC_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C0))
+#define RXDFE_FC_FDPM_0_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C4))
+#define RXDFE_FC_FDPM_1_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C8))
+#define RXDFE_FC_FDPM_2_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00CC))
+#define RXDFE_FC_RFEQ_0_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D0))
+#define RXDFE_FC_RFEQ_1_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D4))
+#define RXDFE_FC_RFEQ_2_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D8))
+#define RXDFE_FC_RFEQ_3_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00DC))
+#define RXDFE_FC_RFEQ_4_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E0))
+#define RXDFE_FC_IQC_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E4))
+#define RXDFE_FC_FDPM_0_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E8))
+#define RXDFE_FC_FDPM_1_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00EC))
+#define RXDFE_FC_FDPM_2_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F0))
+#define RXDFE_FC_RFEQ_0_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F4))
+#define RXDFE_FC_RFEQ_1_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F8))
+#define RXDFE_FC_RFEQ_2_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00FC))
+#define RXDFE_FC_RFEQ_3_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0100))
+#define RXDFE_FC_RFEQ_4_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0104))
+#define RXDFE_FC_IQC_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0108))
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x010C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x011C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x012C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x013C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x014C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x015C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x016C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x017C + (n)*4)) //n is from 0 to 3
+#define RXDFE_FC_NCO_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x018C))
+#define RXDFE_FC_NCO_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0190))
+#define RXDFE_FC_NCO_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0194))
+#define RXDFE_FC_NCO_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0198))
+#define RXDFE_FC_NCO_MBSFN_C0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x019C))
+#define RXDFE_FC_NCO_MBSFN_C1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x01A0))
+
+
+#define RXDFE_FC_P_SWAP_P_SWAP_LSB (0)
+#define RXDFE_FC_P_SWAP_P_SWAP_WIDTH (1)
+#define RXDFE_FC_P_SWAP_P_SWAP_MASK (0x00000001)
+#define RXDFE_FC_P_SWAP_P_SWAP_BIT (0x00000001)
+
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_LSB (0)
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_WIDTH (1)
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_MASK (0x00000001)
+#define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_BIT (0x00000001)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_LSB (24)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_MASK (0x7F000000)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_LSB (16)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_MASK (0x007F0000)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_LSB (8)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_MASK (0x00007F00)
+
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_LSB (0)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_MASK (0x0000007F)
+
+#define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_LSB (0)
+#define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_WIDTH (7)
+#define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_MASK (0x0000007F)
+
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_LSB (0)
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_WIDTH (1)
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_MASK (0x00000001)
+#define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_BIT (0x00000001)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_LSB (24)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_MASK (0x7F000000)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_LSB (16)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_MASK (0x007F0000)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_LSB (8)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_MASK (0x00007F00)
+
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_LSB (0)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_MASK (0x0000007F)
+
+#define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_LSB (0)
+#define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_WIDTH (7)
+#define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_MASK (0x0000007F)
+
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_LSB (20)
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_LSB (15)
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_LSB (14)
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_LSB (13)
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_LSB (12)
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_LSB (10)
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_LSB (9)
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_LSB (8)
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_LSB (4)
+#define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_LSB (0)
+#define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_LSB (16)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_LSB (0)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_LSB (20)
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_LSB (15)
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_LSB (14)
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_LSB (13)
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_LSB (12)
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_LSB (10)
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_LSB (9)
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_LSB (8)
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_LSB (4)
+#define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_LSB (0)
+#define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_LSB (16)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_LSB (0)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_LSB (20)
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_LSB (15)
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_LSB (14)
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_LSB (13)
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_LSB (12)
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_LSB (10)
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_LSB (9)
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_LSB (8)
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_LSB (4)
+#define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_LSB (0)
+#define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_LSB (16)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_LSB (0)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_LSB (20)
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_MASK (0x00100000)
+#define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_BIT (0x00100000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_LSB (15)
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_MASK (0x00008000)
+#define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_BIT (0x00008000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_LSB (14)
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_MASK (0x00004000)
+#define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_BIT (0x00004000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_LSB (13)
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_MASK (0x00002000)
+#define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_BIT (0x00002000)
+
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_LSB (12)
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_MASK (0x00001000)
+#define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_BIT (0x00001000)
+
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_LSB (10)
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_MASK (0x00000400)
+#define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_BIT (0x00000400)
+
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_LSB (9)
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_MASK (0x00000200)
+#define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_BIT (0x00000200)
+
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_LSB (8)
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_WIDTH (1)
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_MASK (0x00000100)
+#define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_BIT (0x00000100)
+
+#define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_LSB (4)
+#define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_MASK (0x000000F0)
+
+#define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_LSB (0)
+#define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_WIDTH (4)
+#define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_LSB (16)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_LSB (0)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_WIDTH (15)
+#define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_LSB (22)
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_LSB (21)
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_LSB (20)
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_LSB (13)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_LSB (12)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_LSB (8)
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_LSB (4)
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_LSB (0)
+#define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_WIDTH (4)
+#define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_LSB (8)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_LSB (0)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_LSB (22)
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_LSB (21)
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_LSB (20)
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_LSB (13)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_LSB (12)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_LSB (8)
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_LSB (4)
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_LSB (0)
+#define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_WIDTH (4)
+#define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_LSB (8)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_LSB (0)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_LSB (22)
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_LSB (21)
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_LSB (20)
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_LSB (13)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_LSB (12)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_LSB (8)
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_LSB (4)
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_LSB (0)
+#define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_WIDTH (4)
+#define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_LSB (8)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_LSB (0)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_LSB (22)
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_MASK (0x00400000)
+#define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_BIT (0x00400000)
+
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_LSB (21)
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_MASK (0x00200000)
+#define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_BIT (0x00200000)
+
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_LSB (20)
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_MASK (0x00100000)
+#define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_BIT (0x00100000)
+
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_LSB (13)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_MASK (0x00002000)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_BIT (0x00002000)
+
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_LSB (12)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_MASK (0x00001000)
+#define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_BIT (0x00001000)
+
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_LSB (8)
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_MASK (0x00000100)
+#define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_BIT (0x00000100)
+
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_LSB (4)
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_WIDTH (1)
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_MASK (0x00000010)
+#define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_BIT (0x00000010)
+
+#define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_LSB (0)
+#define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_WIDTH (4)
+#define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_MASK (0x0000000F)
+
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_LSB (8)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_WIDTH (5)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_LSB (0)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_WIDTH (7)
+#define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_LSB (8)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_WIDTH (5)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_MASK (0x00001F00)
+
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_LSB (0)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_WIDTH (7)
+#define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_MASK (0x0000007F)
+
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_LSB (0)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_WIDTH (23)
+#define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_LSB (16)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_LSB (0)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_LSB (16)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_LSB (0)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_LSB (31)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_LSB (28)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_LSB (0)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_LSB (20)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_LSB (31)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_LSB (30)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_LSB (28)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_LSB (10)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_LSB (0)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_LSB (31)
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_LSB (8)
+#define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_WIDTH (7)
+#define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_LSB (0)
+#define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_WIDTH (8)
+#define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_MASK (0x000000FF)
+
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_LSB (16)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_LSB (0)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_LSB (16)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_LSB (0)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_LSB (31)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_LSB (28)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_LSB (0)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_LSB (20)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_LSB (31)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_LSB (30)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_LSB (28)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_LSB (10)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_LSB (0)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_LSB (31)
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_LSB (8)
+#define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_WIDTH (7)
+#define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_LSB (0)
+#define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_WIDTH (8)
+#define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_MASK (0x000000FF)
+
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_LSB (16)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_LSB (0)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_LSB (16)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_LSB (0)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_LSB (31)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_LSB (28)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_LSB (0)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_LSB (20)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_LSB (31)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_LSB (30)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_LSB (28)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_LSB (10)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_LSB (0)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_LSB (31)
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_LSB (8)
+#define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_WIDTH (7)
+#define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_LSB (0)
+#define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_WIDTH (8)
+#define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_MASK (0x000000FF)
+
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_LSB (16)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_LSB (0)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_LSB (16)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_MASK (0x07FF0000)
+
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_LSB (0)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_LSB (31)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_LSB (28)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_WIDTH (1)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_MASK (0x10000000)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_BIT (0x10000000)
+
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_LSB (0)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_WIDTH (11)
+#define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_MASK (0x000007FF)
+
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_LSB (20)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_MASK (0x1FF00000)
+
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_LSB (31)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_LSB (30)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_WIDTH (1)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_MASK (0x40000000)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_BIT (0x40000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_LSB (28)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_WIDTH (2)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_MASK (0x30000000)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_LSB (10)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_MASK (0x0007FC00)
+
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_LSB (0)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_WIDTH (9)
+#define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_MASK (0x000001FF)
+
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_LSB (31)
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_LSB (8)
+#define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_WIDTH (7)
+#define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_MASK (0x00007F00)
+
+#define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_LSB (0)
+#define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_WIDTH (8)
+#define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_MASK (0x000000FF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_MASK (0x00000007)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_MASK (0x00000007)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_MASK (0x00000007)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_LSB (16)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_MASK (0x7FFF0000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_WIDTH (15)
+#define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_MASK (0x00007FFF)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_LSB (31)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_WIDTH (1)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_MASK (0x80000000)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_LSB (0)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_WIDTH (3)
+#define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_MASK (0x00000007)
+
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_LSB (31)
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_WIDTH (1)
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_MASK (0x80000000)
+#define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_LSB (0)
+#define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_WIDTH (23)
+#define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_LSB (31)
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_WIDTH (1)
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_MASK (0x80000000)
+#define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_LSB (0)
+#define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_WIDTH (23)
+#define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_LSB (31)
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_WIDTH (1)
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_MASK (0x80000000)
+#define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_LSB (0)
+#define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_WIDTH (23)
+#define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_LSB (31)
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_WIDTH (1)
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_MASK (0x80000000)
+#define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_LSB (0)
+#define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_WIDTH (23)
+#define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_LSB (31)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_WIDTH (1)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_MASK (0x80000000)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_LSB (0)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_WIDTH (23)
+#define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_MASK (0x007FFFFF)
+
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_LSB (31)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_WIDTH (1)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_MASK (0x80000000)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_BIT (0x80000000)
+
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_LSB (0)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_WIDTH (23)
+#define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_MASK (0x007FFFFF)
+
+
+#endif //#ifndef _CPH_C2K_RXDFE_H_