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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg0.h b/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg0.h
new file mode 100644
index 0000000..a93cc5c
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg0.h
@@ -0,0 +1,280 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+#ifndef _CPH_DFESYS_GLBCON_CONFIG0_H_
+#define _CPH_DFESYS_GLBCON_CONFIG0_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define DFESYS_GLB_CON_CONFIG0_REG_BASE (0xA8990000)
+
+#define DFESYS_GLB_CON_CONFIG0_end (DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0114 + 1*4)
+
+
+
+#define DIV_TXBRP ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0000))
+#define DIV_TXCRP ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0004))
+#define DEBUG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x001C))
+#define F208M_DEBUG_BUS ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0024))
+#define F208M_DEBUG_BUS2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0028))
+#define TXBSRP_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x002c))
+#define RG_SW_ADDR_DATA_VLD ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0034))
+#define TXBSRP_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0038))
+#define TXBSRP_PCK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0040))
+#define TXBSRP_PCK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0044))
+#define TX_SRP_CRP_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0048))
+#define TX_SRP_CRP_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x004c))
+#define TXCRP_PCK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0050))
+#define TXCRP_PCK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0054))
+#define TXCRP_SP_WCRP_APB_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0064))
+#define TXCRP_RG_TAPB_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0068))
+#define TXCRP_RG_C1X_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x006C))
+#define TXCRP_RG_CDO_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0070))
+#define TXCRP_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0074))
+#define TXCRP_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0078))
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0080))
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0084))
+#define SW_CK_IDLE_DIV ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0090))
+#define MASK_TXBSRP_CK_IDLE_DIV ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0094))
+#define R2TX_SW_DISABLE_HW ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0100))
+#define R2T_RDATA1 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0104))
+#define R2T_RDATA2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0108))
+#define R2T_RDATA3 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x010c))
+#define R2T_RDATA4 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0110))
+#define R2T_RDATA5 ((APBADDR32)(DFESYS_GLB_CON_CONFIG0_REG_BASE + 0x0114))
+
+
+#define DIV_TXBRP_DIV_TXBRP_LSB (0)
+#define DIV_TXBRP_DIV_TXBRP_WIDTH (1)
+#define DIV_TXBRP_DIV_TXBRP_MASK (0x00000001)
+#define DIV_TXBRP_DIV_TXBRP_BIT (0x00000001)
+
+#define DIV_TXCRP_DIV_TXCRP_LSB (0)
+#define DIV_TXCRP_DIV_TXCRP_WIDTH (2)
+#define DIV_TXCRP_DIV_TXCRP_MASK (0x00000003)
+
+#define DEBUG_SEL_DEBUG_SEL_3_LSB (24)
+#define DEBUG_SEL_DEBUG_SEL_3_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_3_MASK (0x1F000000)
+
+#define DEBUG_SEL_DEBUG_SEL_2_LSB (16)
+#define DEBUG_SEL_DEBUG_SEL_2_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_2_MASK (0x001F0000)
+
+#define DEBUG_SEL_DEBUG_SEL_1_LSB (8)
+#define DEBUG_SEL_DEBUG_SEL_1_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_1_MASK (0x00001F00)
+
+#define DEBUG_SEL_DEBUG_SEL_0_LSB (0)
+#define DEBUG_SEL_DEBUG_SEL_0_WIDTH (5)
+#define DEBUG_SEL_DEBUG_SEL_0_MASK (0x0000001F)
+
+#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_LSB (0)
+#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_WIDTH (32)
+#define F208M_DEBUG_BUS_F208M_DEBUG_BUS_MASK (0xFFFFFFFF)
+
+#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_LSB (0)
+#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_WIDTH (32)
+#define F208M_DEBUG_BUS2_F208M_DEBUG_BUS2_MASK (0xFFFFFFFF)
+
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_LSB (0)
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_WIDTH (1)
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_MASK (0x00000001)
+#define TXBSRP_SW_CKEN_TXBSRP_SW_CKEN_BIT (0x00000001)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_LSB (8)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_WIDTH (11)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_DATA_MASK (0x0007FF00)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_LSB (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_WIDTH (4)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_ADDR_MASK (0x000000F0)
+
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_LSB (1)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_WIDTH (3)
+#define RG_SW_ADDR_DATA_VLD_SW_RAKE_RSV_MASK (0x0000000E)
+
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_LSB (0)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_WIDTH (1)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_MASK (0x00000001)
+#define RG_SW_ADDR_DATA_VLD_SW_VLD_TGL_BIT (0x00000001)
+
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_LSB (16)
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_WIDTH (1)
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_MASK (0x00010000)
+#define TXBSRP_SW_RESET_TXBRP_TXBRP_SW_RESET_BIT (0x00010000)
+
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_LSB (1)
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_WIDTH (1)
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_MASK (0x00000002)
+#define TXBSRP_SW_RESET_TXBRP_REG_SW_RESET_BIT (0x00000002)
+
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_LSB (0)
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_WIDTH (1)
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_MASK (0x00000001)
+#define TXBSRP_SW_RESET_TXBRP_TXSRP_SW_RESET_BIT (0x00000001)
+
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_LSB (0)
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_WIDTH (1)
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_MASK (0x00000001)
+#define TXBSRP_PCK_SW_CKEN_TXBSRP_PCK_SW_CKEN_BIT (0x00000001)
+
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_LSB (0)
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_WIDTH (1)
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_MASK (0x00000001)
+#define TXBSRP_PCK_SW_CKCTRL_TXBSRP_PCK_SW_CKCTRL_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKEN_TX_SRP_CRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_LSB (0)
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_WIDTH (1)
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TX_SRP_CRP_CK_SW_CKCTRL_TX_SRP_CRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_LSB (0)
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_WIDTH (1)
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_PCK_SW_CKEN_TXCRP_PCK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_LSB (0)
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_PCK_SW_CKCTRL_TXCRP_PCK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_LSB (0)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_WIDTH (1)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_MASK (0x00000001)
+#define TXCRP_SP_WCRP_APB_SW_RESET_TXCRP_SP_WCRP_APB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_LSB (0)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_WIDTH (1)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_TAPB_SW_RESET_TXCRP_RG_TAPB_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_LSB (0)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_WIDTH (1)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_C1X_SW_RESET_TXCRP_RG_C1X_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_LSB (0)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_WIDTH (1)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_MASK (0x00000001)
+#define TXCRP_RG_CDO_SW_RESET_TXCRP_RG_CDO_SW_RESET_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_LSB (0)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_WIDTH (1)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_MASK (0x00000001)
+#define TXCRP_CK_SW_CKEN_TXCRP_CK_SW_CKEN_BIT (0x00000001)
+
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_LSB (0)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_WIDTH (1)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXCRP_CK_SW_CKCTRL_TXCRP_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBSRP_MAS_BUS_CK_SW_CKCTRL_TXBSRP_MAS_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_LSB (0)
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_WIDTH (1)
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_MASK (0x00000001)
+#define TXBSRP_SLV_BUS_CK_SW_CKCTRL_TXBSRP_SLV_BUS_CK_SW_CKCTRL_BIT (0x00000001)
+
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_LSB (0)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_WIDTH (1)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_MASK (0x00000001)
+#define SW_CK_IDLE_DIV_SW_CK_IDLE_DIV_BIT (0x00000001)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_LSB (3)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_MASK (0x00000008)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_SLV_BUS_IDLE_BIT (0x00000008)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_LSB (2)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_MASK (0x00000004)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_MAS_BUS_IDLE_BIT (0x00000004)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_LSB (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_MASK (0x00000002)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXCRP_CK_IDLE_DIV_BIT (0x00000002)
+
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_LSB (0)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_WIDTH (1)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_MASK (0x00000001)
+#define MASK_TXBSRP_CK_IDLE_DIV_MASK_TXBSRP_CK_IDLE_DIV_BIT (0x00000001)
+
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_LSB (0)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_WIDTH (1)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_MASK (0x00000001)
+#define R2TX_SW_DISABLE_HW_R2TX_SW_DISABLE_HW_BIT (0x00000001)
+
+#define R2T_RDATA1_R2T_RDATA1_LSB (0)
+#define R2T_RDATA1_R2T_RDATA1_WIDTH (32)
+#define R2T_RDATA1_R2T_RDATA1_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA2_R2T_RDATA2_LSB (0)
+#define R2T_RDATA2_R2T_RDATA2_WIDTH (32)
+#define R2T_RDATA2_R2T_RDATA2_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA3_R2T_RDATA3_LSB (0)
+#define R2T_RDATA3_R2T_RDATA3_WIDTH (32)
+#define R2T_RDATA3_R2T_RDATA3_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA4_R2T_RDATA4_LSB (0)
+#define R2T_RDATA4_R2T_RDATA4_WIDTH (32)
+#define R2T_RDATA4_R2T_RDATA4_MASK (0xFFFFFFFF)
+
+#define R2T_RDATA5_R2T_RDATA5_LSB (0)
+#define R2T_RDATA5_R2T_RDATA5_WIDTH (32)
+#define R2T_RDATA5_R2T_RDATA5_MASK (0xFFFFFFFF)
+
+
+#endif //#ifndef _EL1D_REG_ELBRUS_H_