[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/cl1/common/HW/cphrxdfefccaltc.h b/mcu/interface/l1/cl1/common/HW/cphrxdfefccaltc.h
new file mode 100644
index 0000000..9ad21f9
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/HW/cphrxdfefccaltc.h
@@ -0,0 +1,153 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_RX_DFE_FCCALTC_H_
+#define _CPH_RX_DFE_FCCALTC_H_
+
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+
+#define RXDFE_FCCALTC_REG_BASE (0xA70B0000)
+
+#define RXDFE_FCCALTC_end (RXDFE_FCCALTC_REG_BASE + 0x00000A00 + 1*4)
+
+
+
+#define RG_RXDFE_FCCALTC_OFFSET(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000000 + (n)*4)) //n is from 0 to 4
+#define RG_RXDFE_FCCALTC_TQ_SEL(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000200 + (n)*4)) //n is from 0 to 11
+#define RG_RXDFE_FCCALTC_TQ_TRG(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000280 + (n)*4)) //n is from 0 to 11
+#define RG_RXDFE_FCCALTC_TQ_RO(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000300 + (n)*4)) //n is from 0 to 11
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000600))
+#define RG_RXDFE_FCCALTC_LPM_CFG ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000800))
+#define RG_RXDFE_FCCALTC_LPM_RO(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000810 + (n)*4)) //n is from 0 to 1
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE(n) ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000820 + (n)*4)) //n is from 0 to 1
+#define RG_RXDFE_FCCALTC_IRQ ((APBADDR32)(RXDFE_FCCALTC_REG_BASE + 0x00000A00))
+
+
+#define RG_RXDFE_FCCALTC_OFFSET_offset_2_LSB (16)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_2_WIDTH (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_2_MASK (0x00FF0000)
+
+#define RG_RXDFE_FCCALTC_OFFSET_offset_1_LSB (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_1_WIDTH (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_1_MASK (0x0000FF00)
+
+#define RG_RXDFE_FCCALTC_OFFSET_offset_0_LSB (0)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_0_WIDTH (8)
+#define RG_RXDFE_FCCALTC_OFFSET_offset_0_MASK (0x000000FF)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_LSB (24)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_WIDTH (2)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_atimer_sel_MASK (0x03000000)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_LSB (16)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_WIDTH (5)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_stimer_sel_MASK (0x001F0000)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_LSB (8)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_WIDTH (5)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_offset_sel_MASK (0x00001F00)
+
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_LSB (0)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_MASK (0x00000001)
+#define RG_RXDFE_FCCALTC_TQ_SEL_tq_glo_en_BIT (0x00000001)
+
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_LSB (31)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_MASK (0x80000000)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_trg_tgl_BIT (0x80000000)
+
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_LSB (30)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_MASK (0x40000000)
+#define RG_RXDFE_FCCALTC_TQ_TRG_tq_stp_tgl_BIT (0x40000000)
+
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_LSB (24)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_WIDTH (1)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_MASK (0x01000000)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_fsm_BIT (0x01000000)
+
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_LSB (0)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_WIDTH (8)
+#define RG_RXDFE_FCCALTC_TQ_RO_tq_pointer_MASK (0x000000FF)
+
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_LSB (0)
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_WIDTH (12)
+#define RG_RXDFE_FCCALTC_TQ_ALL_RO_all_tq_fsm_MASK (0x00000FFF)
+
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_LSB (4)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_WIDTH (1)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_MASK (0x00000010)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_gc_en_BIT (0x00000010)
+
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_LSB (0)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_WIDTH (4)
+#define RG_RXDFE_FCCALTC_LPM_CFG_lpm_fsm_MASK (0x0000000F)
+
+#define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_LSB (0)
+#define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_WIDTH (4)
+#define RG_RXDFE_FCCALTC_LPM_RO_lpm_fsm_MASK (0x0000000F)
+
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_LSB (16)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_WIDTH (1)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_MASK (0x00010000)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_mode_BIT (0x00010000)
+
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_LSB (0)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_WIDTH (1)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_MASK (0x00000001)
+#define RG_RXDFE_FCCALTC_LPM_SW_MODE_lpm_sw_trg_BIT (0x00000001)
+
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_LSB (16)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_WIDTH (1)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_MASK (0x00010000)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_clr_tgl_BIT (0x00010000)
+
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_LSB (0)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_WIDTH (1)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_MASK (0x00000001)
+#define RG_RXDFE_FCCALTC_IRQ_rxk_readback_status_BIT (0x00000001)
+
+
+#endif //#ifndef _CPH_RX_DFE_FCCALTC_H_