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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/cl1/common/HW/cphtxcrpcommon.h b/mcu/interface/l1/cl1/common/HW/cphtxcrpcommon.h
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+++ b/mcu/interface/l1/cl1/common/HW/cphtxcrpcommon.h
@@ -0,0 +1,177 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH_COMMON_TXCRP_H_
+#define _CPH_COMMON_TXCRP_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if defined(__MD93__)||defined(__MD95__)
+#define TXCRP_INTERNAL_REG_BASE (0xA8170000)
+#else
+#define TXCRP_INTERNAL_REG_BASE (0xA8970000)
+#endif
+
+#define MODE_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0000))
+#define CRC_EN ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0004))
+#define CRC_LENGTH ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0008))
+#define CRC_OUT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x000C))
+#define CRC_MOD_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0010))
+#define TD_SW_TIMER_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0014))
+#define TD_SW_TIMER_CON ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0018))
+#define FDD_SW_TIMER_GTXCRP_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x001C))
+#define FDD_SW_TIMER_WTXHCH_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0020))
+#define FDD_SW_TIMER_WTXCQI_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0024))
+#define FDD_SW_TTR_GTXCRP_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0028))
+#define FDD_SW_TTR_WTXHCH_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x002C))
+#define FDD_SW_TTR_WTXCQI_STR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0030))
+#define FDD_SW_TTR_SLOT_CNT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0034))
+#define C1X_SW_TIMER_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0038))
+#define C1X_SW_TIMER_CON ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x003C))
+#define WRBRPMEM_TEST_START ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0040))
+#define WRBRPMEM_TEST_NUM ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0044))
+#define DO_TRIGGER_SELECT ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x004C))
+#define DO_TIMER_TRIGGER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0050))
+#define DO_KS_TRIGGER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0054))
+#define DO_TX_ENABLE ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0058))
+#define TESTMODE_NUM ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x005C))
+#define TESTMODE_START ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0060))
+#define KS_SEL_CONFIG ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0064))
+#define MODE_SEL_ADDR_MIS ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0068))
+#define IRQ_MODE_SEL_ADDR_MIS_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x006C))
+#define IRQ_MODE_CHANGE_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0070))
+#define TXCRP_MODE_SETERR_CLR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0074))
+#define TXCRP_IRQ_STATUS ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0078))
+#define TXCRP_IRQ_MASK ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x007C))
+#define INFO_BRP_RU1_ADDR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0080))
+#define INFO_BRP_RU1 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0084))
+#define INFO_BRP_RU2_ADDR ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x008C))
+#define INFO_BRP_RU2 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0090))
+#define DBG_BUS_SEL ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0094))
+#define DUMMY_CRP ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0098))
+#define RAKE_LOG_COUNTER ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x009C))
+#define RAKELOG_0 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A0))
+#define RAKELOG_1 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A4))
+#define RAKELOG_2 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00A8))
+#define RAKELOG_3 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00AC))
+#define RAKELOG_4 ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x00B0))
+#if defined(__MD97__)
+#define TXCRP_KS0_TO_TPC ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x010C))
+#define TXCRP_KS1_TO_TPC ((APBADDR32)(TXCRP_INTERNAL_REG_BASE + 0x0110))
+#endif
+
+#define MODE_SEL_LSB (0)
+#define MODE_SEL_WIDTH (5)
+#define MODE_SEL_MASK (0x0000001F)
+
+#define MODE_SEL_ADDR_MIS_LSB (0)
+#define MODE_SEL_ADDR_MIS_WIDTH (1)
+#define MODE_SEL_ADDR_MIS_MASK (0x00000001)
+#define MODE_SEL_ADDR_MIS_BIT (0x00000001)
+
+#define MODE_SEL_ADDR_MIS_CLR_LSB (0)
+#define MODE_SEL_ADDR_MIS_CLR_WIDTH (1)
+#define MODE_SEL_ADDR_MIS_CLR_MASK (0x00000001)
+#define MODE_SEL_ADDR_MIS_CLR_BIT (0x00000001)
+
+#define CRC_EN_LSB (0)
+#define CRC_EN_WIDTH (1)
+#define CRC_EN_MASK (0x00000001)
+#define CRC_EN_BIT (0x00000001)
+
+#define CRC_LENGTH_LSB (0)
+#define CRC_LENGTH_WIDTH (20)
+#define CRC_LENGTH_MASK (0x000FFFFF)
+
+#define CRC_OUT_LSB (0)
+#define CRC_OUT_WIDTH (32)
+#define CRC_OUT_MASK (0xFFFFFFFF)
+
+#define INFO_RU1_ADDR_LSB (0)
+#define INFO_RU1_ADDR_WIDTH (13)
+#define INFO_RU1_ADDR_MASK (0x00001FFF)
+
+#define RU1_ADDR0_DATA_LSB (24)
+#define RU1_ADDR0_DATA_WIDTH (8)
+#define RU1_ADDR0_DATA_MASK (0xFF000000)
+
+#define RU1_ADDR1_DATA_LSB (16)
+#define RU1_ADDR1_DATA_WIDTH (8)
+#define RU1_ADDR1_DATA_MASK (0x00FF0000)
+
+#define RU1_ADDR2_DATA_LSB (8)
+#define RU1_ADDR2_DATA_WIDTH (8)
+#define RU1_ADDR2_DATA_MASK (0x0000FF00)
+
+#define RU1_ADDR3_DATA_LSB (0)
+#define RU1_ADDR3_DATA_WIDTH (8)
+#define RU1_ADDR3_DATA_MASK (0x000000FF)
+
+#define INFO_RU2_ADDR_LSB (0)
+#define INFO_RU2_ADDR_WIDTH (13)
+#define INFO_RU2_ADDR_MASK (0x00001FFF)
+
+#define RU2_ADDR0_DATA_LSB (24)
+#define RU2_ADDR0_DATA_WIDTH (8)
+#define RU2_ADDR0_DATA_MASK (0xFF000000)
+
+#define RU2_ADDR1_DATA_LSB (16)
+#define RU2_ADDR1_DATA_WIDTH (8)
+#define RU2_ADDR1_DATA_MASK (0x00FF0000)
+
+#define RU2_ADDR2_DATA_LSB (8)
+#define RU2_ADDR2_DATA_WIDTH (8)
+#define RU2_ADDR2_DATA_MASK (0x0000FF00)
+
+#define RU2_ADDR3_DATA_LSB (0)
+#define RU2_ADDR3_DATA_WIDTH (8)
+#define RU2_ADDR3_DATA_MASK (0x000000FF)
+
+#define DBG_BUS_SEL_LSB (0)
+#define DBG_BUS_SEL_WIDTH (4)
+#define DBG_BUS_SEL_MASK (0x0000000F)
+
+#define CRP_LSB (0)
+#define CRP_WIDTH (32)
+#define CRP_MASK (0xFFFFFFFF)
+
+#endif //#ifndef _CPH_COMMON_TXCRP_H_