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Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/cl1/common/cph1xflbrp.h b/mcu/interface/l1/cl1/common/cph1xflbrp.h
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+++ b/mcu/interface/l1/cl1/common/cph1xflbrp.h
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+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2016
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPH1XFLBRP_H_
+#define _CPH1XFLBRP_H_
+   
+#include "cl1common.h"
+#include "kal_general_types.h"
+
+#define XL1_SYNC_CORR_NUM 17
+
+typedef enum
+{
+    RTT_BRP_SYNC = 0,
+    RTT_BRP_PCH,
+    RTT_BRP_FCH,
+    RTT_BRP_ROLL_BACK
+} Cph1xBrpChSel;
+
+
+typedef struct 
+{
+/******DBRP RTT SYNC/PCH/FCH Full rate PARAM1*******/
+  kal_uint16   IntlvSize;
+  kal_uint8    IntlvM;
+  kal_uint8    IntlvJM1;
+  kal_uint8    IntlvFbEn;
+}FchSchParam1T;
+
+typedef struct 
+{
+/******DBRP RTT SYNC/PCH/FCH Full rate PARAM2*******/ 
+  kal_uint8    RepeatRate;
+  kal_uint8    PuncCfg;
+  kal_uint16  PuncPattern;
+  kal_uint16  EncodedBits;
+}FchSchParam2T;
+
+typedef struct 
+{
+/******DBRP RTT SYNC/PCH/FCH Full rate PARAM3*******/ 
+  kal_uint16  CodeBlockSize;
+  kal_uint8    CrcSize;
+  kal_uint8    CodeRate;
+  kal_uint8    SetPt;
+}FchSchParam3T;
+
+typedef struct 
+{
+ /***********************Full rata*******************/
+
+  FchSchParam1T   FchChanFullParam1;
+  FchSchParam2T   FchChanFullParam2;
+  FchSchParam3T   FchChanFullParam3;
+
+  /*******************Half rata*********************/
+  FchSchParam2T   FchChanHalfParam2;
+  FchSchParam3T   FchChanHalfParam3;
+   
+  /*******************Quarter rata*********************/
+  FchSchParam2T   FchChanQuarterParam2;
+  FchSchParam3T   FchChanQuarterParam3;
+  
+/*******************Eighth rata*********************/
+  FchSchParam2T   FchChanEighthParam2;
+  FchSchParam3T   FchChanEighthParam3;
+}FchParamsT;
+
+
+typedef struct  
+{
+  FchSchParam1T   FschChanParam1;
+  FchSchParam2T   FschChanParam2;
+  FchSchParam3T   FschChanParam3;
+} SchChanParamT;
+
+
+typedef struct  
+{
+  FchSchParam1T   PchChanParam1;
+  FchSchParam2T   PchChanParam2;
+  FchSchParam3T   PchChanParam3;
+} PchChanParamT;
+
+typedef struct
+{
+  FchSchParam1T   SyncChanParam1;
+  FchSchParam2T   SyncChanParam2;
+  FchSchParam3T   SyncChanParam3;
+} SyncChanParamT;
+
+/*****************************************************************************
+
+         DMA Vit Parameters
+
+*****************************************************************************/
+
+typedef struct 
+{
+    kal_uint8   BitOffset;
+    kal_uint8   SwapEndian;
+    kal_uint8   CrcRemove;
+    kal_uint8   DmaDisable;
+}ChanDMACfgT;
+
+typedef struct
+{
+    kal_uint32  DbrpVitFchDmaFullBase;
+    kal_uint32  DbrpVitFchDmaHalfBase;
+    kal_uint32  DbrpVitFchDmaQuatBase;
+    kal_uint32  DbrpVitFchDmaEighBase;
+    kal_uint32  DbrpVitSchDmaBase;
+    ChanDMACfgT   FchFullDmaCfg;
+    ChanDMACfgT   SchDmaCfg;
+} DmaCfgT;
+
+typedef struct  
+{
+    kal_uint8  CnfgPinSel;
+    kal_uint8  DataPingSel;
+}DbrpDmaCh3ReqT;
+
+typedef struct  
+{
+    kal_uint8 Mode;
+    kal_uint8 Cnfg;
+    kal_uint8 Priority;
+    kal_uint8 AccIdx;
+    kal_uint16 BufIdx;  
+}DbrpDmaCh3CtrlT;
+
+typedef struct  
+{
+    kal_uint16  BaseAddrIdx;
+    kal_uint16  StartSampleIdx;   
+}DbrpDmaCh3CtrlCnfgT;
+
+typedef struct  
+{
+    kal_uint32 DbrpDmaCh3;
+    DbrpDmaCh3ReqT   DbrpDmaCh3Req;
+    DbrpDmaCh3CtrlT DbrpDmaCh3Ctrl;
+    DbrpDmaCh3CtrlCnfgT  DbrpDmaCh3CtrlCnfgPing;
+    DbrpDmaCh3CtrlCnfgT  DbrpDmaCh3CtrlCnfgPong;
+    kal_uint32  DbrpDmaCh3CtrlCnfg;
+    DbrpDmaCh3CtrlCnfgT  DbrpDmaCh3CtrlDataPing;
+    DbrpDmaCh3CtrlCnfgT  DbrpDmaCh3CtrlDataPong;
+    kal_uint32 DbrpDmaCh3CtrlData;  
+}DmaChannel3T;
+
+//turbo para
+typedef struct 
+{
+    kal_uint8 MaxIter;
+    kal_uint8 MinIter;
+}DbrpTurRttCfgT;
+typedef struct 
+{
+    kal_uint8  MacOfst;
+    kal_uint8  SwapEndian;
+    kal_uint8  CrcRemove;
+}DbrpTurRttDmaCfgT;
+
+typedef struct  
+{
+    DbrpTurRttCfgT  DbrpTurRttCfg;
+    kal_uint32 DbrpTurRttDst;
+    DbrpTurRttDmaCfgT DbrpTurRttDmaCfg;
+    kal_uint32  DbrpTurRttTraceCfg;   
+}TurboParamesT;
+
+
+
+/*****************************************************************************
+
+         Control Parameters
+
+*****************************************************************************/
+typedef struct  
+{
+    kal_uint8   FchDrmDone;
+    kal_uint8   SchDrmDone;
+    kal_uint8   FchDecDone;
+    kal_uint8   SchDecDone;
+    kal_uint8   CorrDone;
+}DbrpRttDoneVecT;
+
+typedef struct  
+{
+   kal_uint8   CfgOk;
+   kal_uint8   CfgAssert;
+}DbrpRttCfgOkT;
+
+typedef struct  
+{
+   kal_uint32   FchEn;
+   kal_uint32  SchEn;
+   kal_uint32  SchEncoding;
+}DbrpRttChDetT;
+
+typedef struct 
+{
+   kal_uint32   ScaleMode;
+   kal_uint32   DereapScalMode;
+}DbrpRttScaleCfgT;
+
+typedef struct  
+{
+   kal_uint8   ChSel;
+   kal_uint8   SyncBufIdx;
+   kal_uint8   SyncDrmEn;
+   kal_uint8   SyncCorrEn;
+   kal_uint8   SyncVitEn;
+}DbrpRttFchCfgT;
+
+typedef struct 
+{
+   kal_uint16  EtPcgMap;
+   kal_bool    EtEn;
+   kal_uint16  EtQuarPcg ;
+   kal_uint16  EtHalfPcg;
+   kal_uint16  EtFullPcg;
+}DbrpRttFchEtParmaT;
+
+
+typedef struct  
+{
+   kal_uint32  DbrpRttStart;
+   kal_uint32  DbrpRttDone;
+   DbrpRttDoneVecT  DbrpRttDoneVec;
+   DbrpRttCfgOkT       DbrpRttCfgOk;  
+   DbrpRttChDetT       DbrpRttChDet;
+   DbrpRttScaleCfgT     DbrpRttScalCfg;
+   DbrpRttFchCfgT      DbrpRttFchCfg; 
+   DbrpRttFchEtParmaT   DbrpRttFchEtParam;
+}DbrpControlParamT;
+
+/*****************************************************************************
+
+        Vit Decode Parameters
+
+*****************************************************************************/
+
+typedef struct  
+{   
+   kal_bool  Full;
+   kal_bool  Half;
+   kal_bool  Quat;
+   kal_bool  Eigh;
+}VitFchCrcStatusT;  
+
+
+typedef struct  
+{   
+   kal_uint32  Full;
+   kal_uint32  Half;
+   kal_uint32  Quat;
+   kal_uint32  Eigh;
+}VitFchSStatusT;  /*End state metric(S-Value,S) 21bits,S*/
+
+typedef struct  
+{   
+   kal_uint32  Full;
+   kal_uint32  Half;
+   kal_uint32  Quat;
+   kal_uint32  Eigh;
+}VitFchYStatusT;  /*yamamoto metric(Y) 11bits, YAMA*/
+
+typedef struct  
+{   
+   kal_uint32  Full;
+   kal_uint32  Half;
+   kal_uint32  Quat;
+   kal_uint32  Eigh;
+}VitFchHStatusT;  /*Hypothesis Metric(H) 21bits,E*/
+
+
+typedef struct  
+{   
+   kal_uint32  Full;
+   kal_uint32  Half;
+   kal_uint32  Quat;
+   kal_uint32  Eigh;
+}VitFchSertatusT;  /*SER 11bits,SER*/
+
+typedef struct  
+{   
+   kal_uint32  Full;
+   kal_uint32  Half;
+   kal_uint32  Quat;
+   kal_uint32  Eigh;
+}VitFchSoftSertatusT;  /*Soft SER 11bits, PM*/
+
+
+typedef struct
+{
+    VitFchSStatusT         FchS;
+    VitFchYStatusT         FchY;
+    VitFchHStatusT         FchH;
+    VitFchSertatusT     FchSer;
+    VitFchSoftSertatusT FchSoftSer;
+    VitFchCrcStatusT       FchCrc;
+    kal_uint32             SchCrc;
+}VitRdaParamT;
+
+
+typedef struct  
+{
+   kal_uint32   DbrpVitReset;
+   kal_uint32   DbrpVitLva;
+   kal_uint32   DbrpVitPchConf;
+   kal_uint32   DbrpVitFirstFrm;
+   kal_uint32   DbrpVitSync;
+   
+   kal_uint32  DbrpVitFchDmaFullBase;
+   kal_uint32  DbrpVitFchDmaHalfBase;
+   kal_uint32  DbrpVitFchDmaQuatBase;
+   kal_uint32  DbrpVitFchDmaEighBase;
+   kal_uint32  DbrpVitSchDmaBase;
+   ChanDMACfgT   FchFullDmaCfg;
+   ChanDMACfgT   SchDmaCfg;
+   
+   VitRdaParamT  DbrpRdaParmes;
+   kal_uint32   DbrpVitStatus ;  
+   kal_uint32   DbrpVitDone;
+   kal_uint32  DbrpVitFchFullUsage;    //debug used 
+}VitChanParamT;
+
+typedef struct
+{
+    kal_uint8 MsgLength;
+    kal_uint8 CorrExtraEnable;
+}
+DbrpRttCorrPatternT;
+
+typedef struct
+{
+    kal_uint8   DbrpRttCorrBufIdx;
+    kal_uint16  DbrpRttCorrEnergy;
+    kal_int16   DbrpRttCorrRslt[XL1_SYNC_CORR_NUM];
+}BbrpRttCorrT;
+
+/*****************************************************************************
+
+        Function declaration
+
+*****************************************************************************/
+extern void Cph1xFlBrpSyncPchParamConfig(PchChanParamT *ads_ptr);
+extern void Cph1xFlBrpFchParamConfig(FchParamsT  *ads_ptr);
+extern void Cph1xFlBrpFschParamConfig(SchChanParamT  *ads_ptr);
+extern void Cph1xFlBrpCorrVitControlConfig(Cph1xBrpChSel ChSel,kal_uint8 BufIdx,kal_bool VitEn, kal_uint8 VitStartBufIdx,kal_bool CorrEn);
+extern void Cph1xFlBrpTurConfig(TurboParamesT *ads_ptr);
+extern void Cph1xFlBrpVitConfig(VitChanParamT *ads_ptr);
+extern void Cph1xFlBrpInputDmaConfig(DmaChannel3T *ads_ptr);
+extern void Cph1xFlBrpSyncSomRsltRead(BbrpRttCorrT *ads_ptr);
+extern void  Cph1xFlBrpSyncCorrExtraEnable(kal_uint16 ExtraLen);
+extern void Cph1xFlBrpFchRdaRead(VitRdaParamT  *RdaVitPtr);
+extern kal_uint32 Cph1xFlBrpVitDone();
+extern kal_uint32 Cph1xFlBrpCorrDone();
+extern kal_uint32 Cph1xFlBrpTurDone();
+extern kal_uint32 Cph1xFlBrpDrmDone();
+extern void Cph1xFlBrpDoneClr();
+extern void Cph1xFlBrpCfgDone();
+extern void Cph1xFlBrpFchCrcStateRead(VitFchCrcStatusT *ads_ptr);
+extern kal_uint32 Cph1xFlBrpSchVitCrcStateRead();
+extern kal_uint32 Cph1xFlBrpSchTurCrcStateRead();
+extern void Cph1xFlBrpEnConfig(DbrpRttChDetT *ads_ptr);
+extern void Cph1xFlBrpScaleConfig(DbrpRttScaleCfgT *ads_ptr);
+extern void Cph1xFlBrpEtParaConfig(DbrpRttFchEtParmaT *ads_ptr); 
+extern void Cph1xFlBrpChSel(DbrpRttFchCfgT *ads_ptr);
+extern void Cph1xFlBrpFchCrcStateRead(VitFchCrcStatusT *ads_ptr);
+extern void Cph1xFlBrpCodeBlcokSizeCfg(kal_uint32 CodeBlockSize);
+extern void Cph1xFlBrpVitFirstFrmCfg(kal_bool FirstFrm);
+extern kal_uint32 Cph1xFlBrpDumpCh0Enerage();
+extern kal_uint32 Cph1xFlBrpDumpCh1Enerage();
+extern kal_uint32 Cph1xFlBrpDumpCh1TurEnerage();
+extern kal_uint32 Cph1xFlBrpDoneRead();
+extern kal_uint32 Cph1xFlBrpCfgDoneRead();
+extern kal_uint32 Cph1xFlBrpVitState();
+
+#endif
+