[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/cl1/common/cphsystemtimer.h b/mcu/interface/l1/cl1/common/cphsystemtimer.h
new file mode 100644
index 0000000..2e0762f
--- /dev/null
+++ b/mcu/interface/l1/cl1/common/cphsystemtimer.h
@@ -0,0 +1,1278 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+#ifndef _CPHSYSTEMTIMER_H_
+#define _CPHSYSTEMTIMER_H_
+
+typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */
+typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */
+typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */
+typedef volatile unsigned short APBDATA; /* APB data is 16 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */
+typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */
+typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */
+typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */
+
+#if (defined(__MD93__)||defined(__MD95__))
+#define ST_RX_TIMER_REG_BASE (0xA60C0000)/*RX TIMER REG BASE 93&95*/
+#elif defined(__MD97__) || defined(__MD97P__)
+#define ST_RX_TIMER_REG_BASE (0xA80C0000)/*RX TIMER REG BASE 97*/
+#endif
+
+#define ST_ADV_RET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000000))
+#define ST_SYNC_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000004))
+#define ST_SYNC_SYSCNT_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000008))
+#define ST_SYNC_SUPFRM_CNT_L_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000000C))
+#define ST_SYNC_SUPFRM_CNT_H_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000010))
+#define ST_SYNC_TIME_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000014))
+#define ST_SUPFRM_CNT_L_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000018))
+#define ST_SUPFRM_CNT_H_INI(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000001C))
+#define ST_SUPFRM_CNT_INI_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000020))
+#define ST_FRM_TYPE(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000024))
+#define ST_CPINT_OFFSET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000028))
+#define ST_CPINT_MASK(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000002C))
+#define ST_CPINT_CLR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000030))
+#define ST_CPINT_SRC(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000034))
+#define ST_CPINT_ISR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000038))
+#define ST_HALF_CPINT_OFFSET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000003C))
+#define ST_HALF_CPINT_MASK(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000040))
+#define ST_HALF_CPINT_CLR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000044))
+#define ST_HALF_CPINT_SRC(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000048))
+#define ST_HALF_CPINT_ISR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000004C))
+#define ST_CFG_CPINT_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000050))
+#define ST_CFG_CPINT_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000054))
+#define ST_CFG_CPINT_ISR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000058))
+#define ST_CFG_CPINT_CLR(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000005C))
+#ifdef __MD93__
+#define ST_SUBFR_STATUS(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000060))
+#endif
+#define ST_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000064))
+#define ST_SUPFRM_CNT_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000068))
+#define ST_SUPFRM_CNT_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000006C))
+#define ST_FRC_TIMING_SYNC_MODE(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000070))
+#define ST_FRC_TIMING_SYNC_CMP(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000074))
+#define ST_FRC_TIMING_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000078))
+#define ST_FRC_TIMING_SYNC_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000007C))
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000080))
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000084))
+#define ST_MU_SFO(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000088))
+#define ST_MU_ACC_INI_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000008C))
+#define ST_MU_ACC_INI_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000090))
+#define ST_MU_ACC_SET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000094))
+#define ST_RAKE_CTL_TIME3(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000098))
+#define ST_GSR_CTL_TIME2(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000009C))
+#define ST_GSR_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000A0))
+#define ST_GSR_SYNC_TAG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000A4))
+#ifdef __MD93__
+#define ST_1XDO_TIMING_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000A8))
+#define ST_1XDO_TIMING_SYNC_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000AC))
+#else
+#define ST_1XDO_TIMING_SYNC_TRIG(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000C0))
+#define ST_1XDO_TIMING_SYNC_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000C4))
+#define ST_1XDO_TIMING_SYNC_SUPFRM_CNT_L(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000C8))
+#define ST_1XDO_TIMING_SYNC_SUPFRM_CNT_H(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000CC))
+#endif
+#define ST_1XDOMRG_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000B0))
+#define ST_1XDOMRG_INI_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000B4))
+#define ST_1XDOMRG_OFFSET(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000B8))
+#define ST_GPS_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x000000BC))
+#if defined(__MD97__) || defined(__MD97P__)
+#define ST_1XDO_US_SYNC_IMM_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000200))
+#define ST_1XDO_US_SYNC_IMM_UCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000204))
+#define ST_1XDO_US_SYNC_IMM_SYSCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000208))
+#define ST_1XDO_US_SYNC_SCH_EN(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000210))
+#define ST_1XDO_US_SYNC_SCH_TIME(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x0000020c))
+#define ST_1XDO_US_SYNC_SCH_UCNT(i) ((APBADDR32)(ST_RX_TIMER_REG_BASE + ((i) << 17) + 0x00000214))
+#endif
+
+
+#define ST_ADV_RET_MODE_LSB (0)
+#define ST_ADV_RET_MODE_WIDTH (2)
+#define ST_ADV_RET_MODE_MASK (0x00000003)
+#define ST_ADV_RET_MODE_ADV (0x00000001)
+#define ST_ADV_RET_MODE_RET (0x00000002)
+
+#define ST_ADV_RET_ADJ_TC8_LSB (2)
+#define ST_ADV_RET_ADJ_TC8_WIDTH (9)
+#define ST_ADV_RET_ADJ_TC8_MASK (0x000007FC)
+
+
+#define ST_SYNC_TIME_SYSTEM_TIME_CNT_LSB (2)
+#define ST_SYNC_TIME_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_SYNC_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_SYSCNT_INI_SYSTEM_TIME_CNT_LSB (0)
+#define ST_SYSCNT_INI_SYSTEM_TIME_CNT_WIDTH (20)
+#define ST_SYSCNT_INI_SYSTEM_TIME_CNT_MASK (0x000FFFFF)
+
+#define ST_SYNC_SUPFRM_CNT_L_INI_SUPFRM_CNT_LSB (0)
+#define ST_SYNC_SUPFRM_CNT_L_INI_SUPFRM_CNT_WIDTH (32)
+#define ST_SYNC_SUPFRM_CNT_L_INI_SUPFRM_CNT_MASK (0xFFFFFFFF)
+
+#define ST_SYNC_SUPFRM_CNT_H_INI_SUPFRM_CNT_LSB (0)
+#define ST_SYNC_SUPFRM_CNT_H_INI_SUPFRM_CNT_WIDTH (4)
+#define ST_SYNC_SUPFRM_CNT_H_INI_SUPFRM_CNT_MASK (0x0000000F)
+
+#define ST_SYNC_TIME_EN_EN_LSB (0)
+#define ST_SYNC_TIME_EN_EN_WIDTH (1)
+#define ST_SYNC_TIME_EN_EN_MASK (0x00000001)
+#define ST_SYNC_TIME_EN_EN_BIT (0x00000001)
+
+#define ST_SUPFRM_CNT_L_INI_SUPFRM_CNT_LSB (0)
+#define ST_SUPFRM_CNT_L_INI_SUPFRM_CNT_WIDTH (32)
+#define ST_SUPFRM_CNT_L_INI_SUPFRM_CNT_MASK (0xFFFFFFFF)
+
+#define ST_SUPFRM_CNT_H_INI_SUPFRM_CNT_LSB (0)
+#define ST_SUPFRM_CNT_H_INI_SUPFRM_CNT_WIDTH (4)
+#define ST_SUPFRM_CNT_H_INI_SUPFRM_CNT_MASK (0x0000000F)
+
+#define ST_SUPFRM_CNT_INI_TRIG_TRIG_LSB (0)
+#define ST_SUPFRM_CNT_INI_TRIG_TRIG_WIDTH (1)
+#define ST_SUPFRM_CNT_INI_TRIG_TRIG_MASK (0x00000001)
+#define ST_SUPFRM_CNT_INI_TRIG_TRIG_BIT (0x00000001)
+
+#define ST_FRM_TYPE_FRM_TYPE_LSB (0)
+#define ST_FRM_TYPE_FRM_TYPE_WIDTH (1)
+#define ST_FRM_TYPE_FRM_TYPE_MASK (0x00000001)
+#define ST_FRM_TYPE_FRM_TYPE_26MS (0x00000000)
+#define ST_FRM_TYPE_FRM_TYPE_20MS (0x00000001)
+
+#define ST_CPINT_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST_CPINT_OFFSET_CHIP_OFFSET_WIDTH (18)
+#define ST_CPINT_OFFSET_CHIP_OFFSET_MASK (0x000FFFFC)
+
+#define ST_CPINT_MASK_MSK15_LSB (15)
+#define ST_CPINT_MASK_MSK15_WIDTH (1)
+#define ST_CPINT_MASK_MSK15_MASK (0x00008000)
+#define ST_CPINT_MASK_MSK15_BIT (0x00008000)
+
+#define ST_CPINT_MASK_MSK14_LSB (14)
+#define ST_CPINT_MASK_MSK14_WIDTH (1)
+#define ST_CPINT_MASK_MSK14_MASK (0x00004000)
+#define ST_CPINT_MASK_MSK14_BIT (0x00004000)
+
+#define ST_CPINT_MASK_MSK13_LSB (13)
+#define ST_CPINT_MASK_MSK13_WIDTH (1)
+#define ST_CPINT_MASK_MSK13_MASK (0x00002000)
+#define ST_CPINT_MASK_MSK13_BIT (0x00002000)
+
+#define ST_CPINT_MASK_MSK12_LSB (12)
+#define ST_CPINT_MASK_MSK12_WIDTH (1)
+#define ST_CPINT_MASK_MSK12_MASK (0x00001000)
+#define ST_CPINT_MASK_MSK12_BIT (0x00001000)
+
+#define ST_CPINT_MASK_MSK11_LSB (11)
+#define ST_CPINT_MASK_MSK11_WIDTH (1)
+#define ST_CPINT_MASK_MSK11_MASK (0x00000800)
+#define ST_CPINT_MASK_MSK11_BIT (0x00000800)
+
+#define ST_CPINT_MASK_MSK10_LSB (10)
+#define ST_CPINT_MASK_MSK10_WIDTH (1)
+#define ST_CPINT_MASK_MSK10_MASK (0x00000400)
+#define ST_CPINT_MASK_MSK10_BIT (0x00000400)
+
+#define ST_CPINT_MASK_MSK9_LSB (9)
+#define ST_CPINT_MASK_MSK9_WIDTH (1)
+#define ST_CPINT_MASK_MSK9_MASK (0x00000200)
+#define ST_CPINT_MASK_MSK9_BIT (0x00000200)
+
+#define ST_CPINT_MASK_MSK8_LSB (8)
+#define ST_CPINT_MASK_MSK8_WIDTH (1)
+#define ST_CPINT_MASK_MSK8_MASK (0x00000100)
+#define ST_CPINT_MASK_MSK8_BIT (0x00000100)
+
+#define ST_CPINT_MASK_MSK7_LSB (7)
+#define ST_CPINT_MASK_MSK7_WIDTH (1)
+#define ST_CPINT_MASK_MSK7_MASK (0x00000080)
+#define ST_CPINT_MASK_MSK7_BIT (0x00000080)
+
+#define ST_CPINT_MASK_MSK6_LSB (6)
+#define ST_CPINT_MASK_MSK6_WIDTH (1)
+#define ST_CPINT_MASK_MSK6_MASK (0x00000040)
+#define ST_CPINT_MASK_MSK6_BIT (0x00000040)
+
+#define ST_CPINT_MASK_MSK5_LSB (5)
+#define ST_CPINT_MASK_MSK5_WIDTH (1)
+#define ST_CPINT_MASK_MSK5_MASK (0x00000020)
+#define ST_CPINT_MASK_MSK5_BIT (0x00000020)
+
+#define ST_CPINT_MASK_MSK4_LSB (4)
+#define ST_CPINT_MASK_MSK4_WIDTH (1)
+#define ST_CPINT_MASK_MSK4_MASK (0x00000010)
+#define ST_CPINT_MASK_MSK4_BIT (0x00000010)
+
+#define ST_CPINT_MASK_MSK3_LSB (3)
+#define ST_CPINT_MASK_MSK3_WIDTH (1)
+#define ST_CPINT_MASK_MSK3_MASK (0x00000008)
+#define ST_CPINT_MASK_MSK3_BIT (0x00000008)
+
+#define ST_CPINT_MASK_MSK2_LSB (2)
+#define ST_CPINT_MASK_MSK2_WIDTH (1)
+#define ST_CPINT_MASK_MSK2_MASK (0x00000004)
+#define ST_CPINT_MASK_MSK2_BIT (0x00000004)
+
+#define ST_CPINT_MASK_MSK1_LSB (1)
+#define ST_CPINT_MASK_MSK1_WIDTH (1)
+#define ST_CPINT_MASK_MSK1_MASK (0x00000002)
+#define ST_CPINT_MASK_MSK1_BIT (0x00000002)
+
+#define ST_CPINT_MASK_MSK0_LSB (0)
+#define ST_CPINT_MASK_MSK0_WIDTH (1)
+#define ST_CPINT_MASK_MSK0_MASK (0x00000001)
+#define ST_CPINT_MASK_MSK0_BIT (0x00000001)
+
+#define ST_CPINT_CLR_CLR15_LSB (15)
+#define ST_CPINT_CLR_CLR15_WIDTH (1)
+#define ST_CPINT_CLR_CLR15_MASK (0x00008000)
+#define ST_CPINT_CLR_CLR15_BIT (0x00008000)
+
+#define ST_CPINT_CLR_CLR14_LSB (14)
+#define ST_CPINT_CLR_CLR14_WIDTH (1)
+#define ST_CPINT_CLR_CLR14_MASK (0x00004000)
+#define ST_CPINT_CLR_CLR14_BIT (0x00004000)
+
+#define ST_CPINT_CLR_CLR13_LSB (13)
+#define ST_CPINT_CLR_CLR13_WIDTH (1)
+#define ST_CPINT_CLR_CLR13_MASK (0x00002000)
+#define ST_CPINT_CLR_CLR13_BIT (0x00002000)
+
+#define ST_CPINT_CLR_CLR12_LSB (12)
+#define ST_CPINT_CLR_CLR12_WIDTH (1)
+#define ST_CPINT_CLR_CLR12_MASK (0x00001000)
+#define ST_CPINT_CLR_CLR12_BIT (0x00001000)
+
+#define ST_CPINT_CLR_CLR11_LSB (11)
+#define ST_CPINT_CLR_CLR11_WIDTH (1)
+#define ST_CPINT_CLR_CLR11_MASK (0x00000800)
+#define ST_CPINT_CLR_CLR11_BIT (0x00000800)
+
+#define ST_CPINT_CLR_CLR10_LSB (10)
+#define ST_CPINT_CLR_CLR10_WIDTH (1)
+#define ST_CPINT_CLR_CLR10_MASK (0x00000400)
+#define ST_CPINT_CLR_CLR10_BIT (0x00000400)
+
+#define ST_CPINT_CLR_CLR9_LSB (9)
+#define ST_CPINT_CLR_CLR9_WIDTH (1)
+#define ST_CPINT_CLR_CLR9_MASK (0x00000200)
+#define ST_CPINT_CLR_CLR9_BIT (0x00000200)
+
+#define ST_CPINT_CLR_CLR8_LSB (8)
+#define ST_CPINT_CLR_CLR8_WIDTH (1)
+#define ST_CPINT_CLR_CLR8_MASK (0x00000100)
+#define ST_CPINT_CLR_CLR8_BIT (0x00000100)
+
+#define ST_CPINT_CLR_CLR7_LSB (7)
+#define ST_CPINT_CLR_CLR7_WIDTH (1)
+#define ST_CPINT_CLR_CLR7_MASK (0x00000080)
+#define ST_CPINT_CLR_CLR7_BIT (0x00000080)
+
+#define ST_CPINT_CLR_CLR6_LSB (6)
+#define ST_CPINT_CLR_CLR6_WIDTH (1)
+#define ST_CPINT_CLR_CLR6_MASK (0x00000040)
+#define ST_CPINT_CLR_CLR6_BIT (0x00000040)
+
+#define ST_CPINT_CLR_CLR5_LSB (5)
+#define ST_CPINT_CLR_CLR5_WIDTH (1)
+#define ST_CPINT_CLR_CLR5_MASK (0x00000020)
+#define ST_CPINT_CLR_CLR5_BIT (0x00000020)
+
+#define ST_CPINT_CLR_CLR4_LSB (4)
+#define ST_CPINT_CLR_CLR4_WIDTH (1)
+#define ST_CPINT_CLR_CLR4_MASK (0x00000010)
+#define ST_CPINT_CLR_CLR4_BIT (0x00000010)
+
+#define ST_CPINT_CLR_CLR3_LSB (3)
+#define ST_CPINT_CLR_CLR3_WIDTH (1)
+#define ST_CPINT_CLR_CLR3_MASK (0x00000008)
+#define ST_CPINT_CLR_CLR3_BIT (0x00000008)
+
+#define ST_CPINT_CLR_CLR2_LSB (2)
+#define ST_CPINT_CLR_CLR2_WIDTH (1)
+#define ST_CPINT_CLR_CLR2_MASK (0x00000004)
+#define ST_CPINT_CLR_CLR2_BIT (0x00000004)
+
+#define ST_CPINT_CLR_CLR1_LSB (1)
+#define ST_CPINT_CLR_CLR1_WIDTH (1)
+#define ST_CPINT_CLR_CLR1_MASK (0x00000002)
+#define ST_CPINT_CLR_CLR1_BIT (0x00000002)
+
+#define ST_CPINT_CLR_CLR0_LSB (0)
+#define ST_CPINT_CLR_CLR0_WIDTH (1)
+#define ST_CPINT_CLR_CLR0_MASK (0x00000001)
+#define ST_CPINT_CLR_CLR0_BIT (0x00000001)
+
+#define ST_CPINT_SRC_SRC15_LSB (15)
+#define ST_CPINT_SRC_SRC15_WIDTH (1)
+#define ST_CPINT_SRC_SRC15_MASK (0x00008000)
+#define ST_CPINT_SRC_SRC15_BIT (0x00008000)
+
+#define ST_CPINT_SRC_SRC14_LSB (14)
+#define ST_CPINT_SRC_SRC14_WIDTH (1)
+#define ST_CPINT_SRC_SRC14_MASK (0x00004000)
+#define ST_CPINT_SRC_SRC14_BIT (0x00004000)
+
+#define ST_CPINT_SRC_SRC13_LSB (13)
+#define ST_CPINT_SRC_SRC13_WIDTH (1)
+#define ST_CPINT_SRC_SRC13_MASK (0x00002000)
+#define ST_CPINT_SRC_SRC13_BIT (0x00002000)
+
+#define ST_CPINT_SRC_SRC12_LSB (12)
+#define ST_CPINT_SRC_SRC12_WIDTH (1)
+#define ST_CPINT_SRC_SRC12_MASK (0x00001000)
+#define ST_CPINT_SRC_SRC12_BIT (0x00001000)
+
+#define ST_CPINT_SRC_SRC11_LSB (11)
+#define ST_CPINT_SRC_SRC11_WIDTH (1)
+#define ST_CPINT_SRC_SRC11_MASK (0x00000800)
+#define ST_CPINT_SRC_SRC11_BIT (0x00000800)
+
+#define ST_CPINT_SRC_SRC10_LSB (10)
+#define ST_CPINT_SRC_SRC10_WIDTH (1)
+#define ST_CPINT_SRC_SRC10_MASK (0x00000400)
+#define ST_CPINT_SRC_SRC10_BIT (0x00000400)
+
+#define ST_CPINT_SRC_SRC9_LSB (9)
+#define ST_CPINT_SRC_SRC9_WIDTH (1)
+#define ST_CPINT_SRC_SRC9_MASK (0x00000200)
+#define ST_CPINT_SRC_SRC9_BIT (0x00000200)
+
+#define ST_CPINT_SRC_SRC8_LSB (8)
+#define ST_CPINT_SRC_SRC8_WIDTH (1)
+#define ST_CPINT_SRC_SRC8_MASK (0x00000100)
+#define ST_CPINT_SRC_SRC8_BIT (0x00000100)
+
+#define ST_CPINT_SRC_SRC7_LSB (7)
+#define ST_CPINT_SRC_SRC7_WIDTH (1)
+#define ST_CPINT_SRC_SRC7_MASK (0x00000080)
+#define ST_CPINT_SRC_SRC7_BIT (0x00000080)
+
+#define ST_CPINT_SRC_SRC6_LSB (6)
+#define ST_CPINT_SRC_SRC6_WIDTH (1)
+#define ST_CPINT_SRC_SRC6_MASK (0x00000040)
+#define ST_CPINT_SRC_SRC6_BIT (0x00000040)
+
+#define ST_CPINT_SRC_SRC5_LSB (5)
+#define ST_CPINT_SRC_SRC5_WIDTH (1)
+#define ST_CPINT_SRC_SRC5_MASK (0x00000020)
+#define ST_CPINT_SRC_SRC5_BIT (0x00000020)
+
+#define ST_CPINT_SRC_SRC4_LSB (4)
+#define ST_CPINT_SRC_SRC4_WIDTH (1)
+#define ST_CPINT_SRC_SRC4_MASK (0x00000010)
+#define ST_CPINT_SRC_SRC4_BIT (0x00000010)
+
+#define ST_CPINT_SRC_SRC3_LSB (3)
+#define ST_CPINT_SRC_SRC3_WIDTH (1)
+#define ST_CPINT_SRC_SRC3_MASK (0x00000008)
+#define ST_CPINT_SRC_SRC3_BIT (0x00000008)
+
+#define ST_CPINT_SRC_SRC2_LSB (2)
+#define ST_CPINT_SRC_SRC2_WIDTH (1)
+#define ST_CPINT_SRC_SRC2_MASK (0x00000004)
+#define ST_CPINT_SRC_SRC2_BIT (0x00000004)
+
+#define ST_CPINT_SRC_SRC1_LSB (1)
+#define ST_CPINT_SRC_SRC1_WIDTH (1)
+#define ST_CPINT_SRC_SRC1_MASK (0x00000002)
+#define ST_CPINT_SRC_SRC1_BIT (0x00000002)
+
+#define ST_CPINT_SRC_SRC0_LSB (0)
+#define ST_CPINT_SRC_SRC0_WIDTH (1)
+#define ST_CPINT_SRC_SRC0_MASK (0x00000001)
+#define ST_CPINT_SRC_SRC0_BIT (0x00000001)
+
+#define ST_CPINT_ISR_ISR15_LSB (15)
+#define ST_CPINT_ISR_ISR15_WIDTH (1)
+#define ST_CPINT_ISR_ISR15_MASK (0x00008000)
+#define ST_CPINT_ISR_ISR15_BIT (0x00008000)
+
+#define ST_CPINT_ISR_ISR14_LSB (14)
+#define ST_CPINT_ISR_ISR14_WIDTH (1)
+#define ST_CPINT_ISR_ISR14_MASK (0x00004000)
+#define ST_CPINT_ISR_ISR14_BIT (0x00004000)
+
+#define ST_CPINT_ISR_ISR13_LSB (13)
+#define ST_CPINT_ISR_ISR13_WIDTH (1)
+#define ST_CPINT_ISR_ISR13_MASK (0x00002000)
+#define ST_CPINT_ISR_ISR13_BIT (0x00002000)
+
+#define ST_CPINT_ISR_ISR12_LSB (12)
+#define ST_CPINT_ISR_ISR12_WIDTH (1)
+#define ST_CPINT_ISR_ISR12_MASK (0x00001000)
+#define ST_CPINT_ISR_ISR12_BIT (0x00001000)
+
+#define ST_CPINT_ISR_ISR11_LSB (11)
+#define ST_CPINT_ISR_ISR11_WIDTH (1)
+#define ST_CPINT_ISR_ISR11_MASK (0x00000800)
+#define ST_CPINT_ISR_ISR11_BIT (0x00000800)
+
+#define ST_CPINT_ISR_ISR10_LSB (10)
+#define ST_CPINT_ISR_ISR10_WIDTH (1)
+#define ST_CPINT_ISR_ISR10_MASK (0x00000400)
+#define ST_CPINT_ISR_ISR10_BIT (0x00000400)
+
+#define ST_CPINT_ISR_ISR9_LSB (9)
+#define ST_CPINT_ISR_ISR9_WIDTH (1)
+#define ST_CPINT_ISR_ISR9_MASK (0x00000200)
+#define ST_CPINT_ISR_ISR9_BIT (0x00000200)
+
+#define ST_CPINT_ISR_ISR8_LSB (8)
+#define ST_CPINT_ISR_ISR8_WIDTH (1)
+#define ST_CPINT_ISR_ISR8_MASK (0x00000100)
+#define ST_CPINT_ISR_ISR8_BIT (0x00000100)
+
+#define ST_CPINT_ISR_ISR7_LSB (7)
+#define ST_CPINT_ISR_ISR7_WIDTH (1)
+#define ST_CPINT_ISR_ISR7_MASK (0x00000080)
+#define ST_CPINT_ISR_ISR7_BIT (0x00000080)
+
+#define ST_CPINT_ISR_ISR6_LSB (6)
+#define ST_CPINT_ISR_ISR6_WIDTH (1)
+#define ST_CPINT_ISR_ISR6_MASK (0x00000040)
+#define ST_CPINT_ISR_ISR6_BIT (0x00000040)
+
+#define ST_CPINT_ISR_ISR5_LSB (5)
+#define ST_CPINT_ISR_ISR5_WIDTH (1)
+#define ST_CPINT_ISR_ISR5_MASK (0x00000020)
+#define ST_CPINT_ISR_ISR5_BIT (0x00000020)
+
+#define ST_CPINT_ISR_ISR4_LSB (4)
+#define ST_CPINT_ISR_ISR4_WIDTH (1)
+#define ST_CPINT_ISR_ISR4_MASK (0x00000010)
+#define ST_CPINT_ISR_ISR4_BIT (0x00000010)
+
+#define ST_CPINT_ISR_ISR3_LSB (3)
+#define ST_CPINT_ISR_ISR3_WIDTH (1)
+#define ST_CPINT_ISR_ISR3_MASK (0x00000008)
+#define ST_CPINT_ISR_ISR3_BIT (0x00000008)
+
+#define ST_CPINT_ISR_ISR2_LSB (2)
+#define ST_CPINT_ISR_ISR2_WIDTH (1)
+#define ST_CPINT_ISR_ISR2_MASK (0x00000004)
+#define ST_CPINT_ISR_ISR2_BIT (0x00000004)
+
+#define ST_CPINT_ISR_ISR1_LSB (1)
+#define ST_CPINT_ISR_ISR1_WIDTH (1)
+#define ST_CPINT_ISR_ISR1_MASK (0x00000002)
+#define ST_CPINT_ISR_ISR1_BIT (0x00000002)
+
+#define ST_CPINT_ISR_ISR0_LSB (0)
+#define ST_CPINT_ISR_ISR0_WIDTH (1)
+#define ST_CPINT_ISR_ISR0_MASK (0x00000001)
+#define ST_CPINT_ISR_ISR0_BIT (0x00000001)
+
+#define ST_HALF_CPINT_OFFSET_CHIP_OFFSET_LSB (2)
+#define ST_HALF_CPINT_OFFSET_CHIP_OFFSET_WIDTH (11)
+#define ST_HALF_CPINT_OFFSET_CHIP_OFFSET_MASK (0x00001FFC)
+
+#define ST_HALF_CPINT_MASK_MSK31_LSB (31)
+#define ST_HALF_CPINT_MASK_MSK31_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK31_MASK (0x80000000)
+#define ST_HALF_CPINT_MASK_MSK31_BIT (0x80000000)
+
+#define ST_HALF_CPINT_MASK_MSK30_LSB (30)
+#define ST_HALF_CPINT_MASK_MSK30_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK30_MASK (0x40000000)
+#define ST_HALF_CPINT_MASK_MSK30_BIT (0x40000000)
+
+#define ST_HALF_CPINT_MASK_MSK29_LSB (29)
+#define ST_HALF_CPINT_MASK_MSK29_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK29_MASK (0x20000000)
+#define ST_HALF_CPINT_MASK_MSK29_BIT (0x20000000)
+
+#define ST_HALF_CPINT_MASK_MSK28_LSB (28)
+#define ST_HALF_CPINT_MASK_MSK28_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK28_MASK (0x10000000)
+#define ST_HALF_CPINT_MASK_MSK28_BIT (0x10000000)
+
+#define ST_HALF_CPINT_MASK_MSK27_LSB (27)
+#define ST_HALF_CPINT_MASK_MSK27_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK27_MASK (0x08000000)
+#define ST_HALF_CPINT_MASK_MSK27_BIT (0x08000000)
+
+#define ST_HALF_CPINT_MASK_MSK26_LSB (26)
+#define ST_HALF_CPINT_MASK_MSK26_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK26_MASK (0x04000000)
+#define ST_HALF_CPINT_MASK_MSK26_BIT (0x04000000)
+
+#define ST_HALF_CPINT_MASK_MSK25_LSB (25)
+#define ST_HALF_CPINT_MASK_MSK25_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK25_MASK (0x02000000)
+#define ST_HALF_CPINT_MASK_MSK25_BIT (0x02000000)
+
+#define ST_HALF_CPINT_MASK_MSK24_LSB (24)
+#define ST_HALF_CPINT_MASK_MSK24_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK24_MASK (0x01000000)
+#define ST_HALF_CPINT_MASK_MSK24_BIT (0x01000000)
+
+#define ST_HALF_CPINT_MASK_MSK23_LSB (23)
+#define ST_HALF_CPINT_MASK_MSK23_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK23_MASK (0x00800000)
+#define ST_HALF_CPINT_MASK_MSK23_BIT (0x00800000)
+
+#define ST_HALF_CPINT_MASK_MSK22_LSB (22)
+#define ST_HALF_CPINT_MASK_MSK22_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK22_MASK (0x00400000)
+#define ST_HALF_CPINT_MASK_MSK22_BIT (0x00400000)
+
+#define ST_HALF_CPINT_MASK_MSK21_LSB (21)
+#define ST_HALF_CPINT_MASK_MSK21_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK21_MASK (0x00200000)
+#define ST_HALF_CPINT_MASK_MSK21_BIT (0x00200000)
+
+#define ST_HALF_CPINT_MASK_MSK20_LSB (20)
+#define ST_HALF_CPINT_MASK_MSK20_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK20_MASK (0x00100000)
+#define ST_HALF_CPINT_MASK_MSK20_BIT (0x00100000)
+
+#define ST_HALF_CPINT_MASK_MSK19_LSB (19)
+#define ST_HALF_CPINT_MASK_MSK19_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK19_MASK (0x00080000)
+#define ST_HALF_CPINT_MASK_MSK19_BIT (0x00080000)
+
+#define ST_HALF_CPINT_MASK_MSK18_LSB (18)
+#define ST_HALF_CPINT_MASK_MSK18_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK18_MASK (0x00040000)
+#define ST_HALF_CPINT_MASK_MSK18_BIT (0x00040000)
+
+#define ST_HALF_CPINT_MASK_MSK17_LSB (17)
+#define ST_HALF_CPINT_MASK_MSK17_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK17_MASK (0x00020000)
+#define ST_HALF_CPINT_MASK_MSK17_BIT (0x00020000)
+
+#define ST_HALF_CPINT_MASK_MSK16_LSB (16)
+#define ST_HALF_CPINT_MASK_MSK16_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK16_MASK (0x00010000)
+#define ST_HALF_CPINT_MASK_MSK16_BIT (0x00010000)
+
+#define ST_HALF_CPINT_MASK_MSK15_LSB (15)
+#define ST_HALF_CPINT_MASK_MSK15_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK15_MASK (0x00008000)
+#define ST_HALF_CPINT_MASK_MSK15_BIT (0x00008000)
+
+#define ST_HALF_CPINT_MASK_MSK14_LSB (14)
+#define ST_HALF_CPINT_MASK_MSK14_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK14_MASK (0x00004000)
+#define ST_HALF_CPINT_MASK_MSK14_BIT (0x00004000)
+
+#define ST_HALF_CPINT_MASK_MSK13_LSB (13)
+#define ST_HALF_CPINT_MASK_MSK13_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK13_MASK (0x00002000)
+#define ST_HALF_CPINT_MASK_MSK13_BIT (0x00002000)
+
+#define ST_HALF_CPINT_MASK_MSK12_LSB (12)
+#define ST_HALF_CPINT_MASK_MSK12_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK12_MASK (0x00001000)
+#define ST_HALF_CPINT_MASK_MSK12_BIT (0x00001000)
+
+#define ST_HALF_CPINT_MASK_MSK11_LSB (11)
+#define ST_HALF_CPINT_MASK_MSK11_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK11_MASK (0x00000800)
+#define ST_HALF_CPINT_MASK_MSK11_BIT (0x00000800)
+
+#define ST_HALF_CPINT_MASK_MSK10_LSB (10)
+#define ST_HALF_CPINT_MASK_MSK10_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK10_MASK (0x00000400)
+#define ST_HALF_CPINT_MASK_MSK10_BIT (0x00000400)
+
+#define ST_HALF_CPINT_MASK_MSK9_LSB (9)
+#define ST_HALF_CPINT_MASK_MSK9_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK9_MASK (0x00000200)
+#define ST_HALF_CPINT_MASK_MSK9_BIT (0x00000200)
+
+#define ST_HALF_CPINT_MASK_MSK8_LSB (8)
+#define ST_HALF_CPINT_MASK_MSK8_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK8_MASK (0x00000100)
+#define ST_HALF_CPINT_MASK_MSK8_BIT (0x00000100)
+
+#define ST_HALF_CPINT_MASK_MSK7_LSB (7)
+#define ST_HALF_CPINT_MASK_MSK7_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK7_MASK (0x00000080)
+#define ST_HALF_CPINT_MASK_MSK7_BIT (0x00000080)
+
+#define ST_HALF_CPINT_MASK_MSK6_LSB (6)
+#define ST_HALF_CPINT_MASK_MSK6_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK6_MASK (0x00000040)
+#define ST_HALF_CPINT_MASK_MSK6_BIT (0x00000040)
+
+#define ST_HALF_CPINT_MASK_MSK5_LSB (5)
+#define ST_HALF_CPINT_MASK_MSK5_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK5_MASK (0x00000020)
+#define ST_HALF_CPINT_MASK_MSK5_BIT (0x00000020)
+
+#define ST_HALF_CPINT_MASK_MSK4_LSB (4)
+#define ST_HALF_CPINT_MASK_MSK4_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK4_MASK (0x00000010)
+#define ST_HALF_CPINT_MASK_MSK4_BIT (0x00000010)
+
+#define ST_HALF_CPINT_MASK_MSK3_LSB (3)
+#define ST_HALF_CPINT_MASK_MSK3_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK3_MASK (0x00000008)
+#define ST_HALF_CPINT_MASK_MSK3_BIT (0x00000008)
+
+#define ST_HALF_CPINT_MASK_MSK2_LSB (2)
+#define ST_HALF_CPINT_MASK_MSK2_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK2_MASK (0x00000004)
+#define ST_HALF_CPINT_MASK_MSK2_BIT (0x00000004)
+
+#define ST_HALF_CPINT_MASK_MSK1_LSB (1)
+#define ST_HALF_CPINT_MASK_MSK1_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK1_MASK (0x00000002)
+#define ST_HALF_CPINT_MASK_MSK1_BIT (0x00000002)
+
+#define ST_HALF_CPINT_MASK_MSK0_LSB (0)
+#define ST_HALF_CPINT_MASK_MSK0_WIDTH (1)
+#define ST_HALF_CPINT_MASK_MSK0_MASK (0x00000001)
+#define ST_HALF_CPINT_MASK_MSK0_BIT (0x00000001)
+
+#define ST_HALF_CPINT_CLR_CLR31_LSB (31)
+#define ST_HALF_CPINT_CLR_CLR31_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR31_MASK (0x80000000)
+#define ST_HALF_CPINT_CLR_CLR31_BIT (0x80000000)
+
+#define ST_HALF_CPINT_CLR_CLR30_LSB (30)
+#define ST_HALF_CPINT_CLR_CLR30_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR30_MASK (0x40000000)
+#define ST_HALF_CPINT_CLR_CLR30_BIT (0x40000000)
+
+#define ST_HALF_CPINT_CLR_CLR29_LSB (29)
+#define ST_HALF_CPINT_CLR_CLR29_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR29_MASK (0x20000000)
+#define ST_HALF_CPINT_CLR_CLR29_BIT (0x20000000)
+
+#define ST_HALF_CPINT_CLR_CLR28_LSB (28)
+#define ST_HALF_CPINT_CLR_CLR28_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR28_MASK (0x10000000)
+#define ST_HALF_CPINT_CLR_CLR28_BIT (0x10000000)
+
+#define ST_HALF_CPINT_CLR_CLR27_LSB (27)
+#define ST_HALF_CPINT_CLR_CLR27_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR27_MASK (0x08000000)
+#define ST_HALF_CPINT_CLR_CLR27_BIT (0x08000000)
+
+#define ST_HALF_CPINT_CLR_CLR26_LSB (26)
+#define ST_HALF_CPINT_CLR_CLR26_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR26_MASK (0x04000000)
+#define ST_HALF_CPINT_CLR_CLR26_BIT (0x04000000)
+
+#define ST_HALF_CPINT_CLR_CLR25_LSB (25)
+#define ST_HALF_CPINT_CLR_CLR25_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR25_MASK (0x02000000)
+#define ST_HALF_CPINT_CLR_CLR25_BIT (0x02000000)
+
+#define ST_HALF_CPINT_CLR_CLR24_LSB (24)
+#define ST_HALF_CPINT_CLR_CLR24_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR24_MASK (0x01000000)
+#define ST_HALF_CPINT_CLR_CLR24_BIT (0x01000000)
+
+#define ST_HALF_CPINT_CLR_CLR23_LSB (23)
+#define ST_HALF_CPINT_CLR_CLR23_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR23_MASK (0x00800000)
+#define ST_HALF_CPINT_CLR_CLR23_BIT (0x00800000)
+
+#define ST_HALF_CPINT_CLR_CLR22_LSB (22)
+#define ST_HALF_CPINT_CLR_CLR22_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR22_MASK (0x00400000)
+#define ST_HALF_CPINT_CLR_CLR22_BIT (0x00400000)
+
+#define ST_HALF_CPINT_CLR_CLR21_LSB (21)
+#define ST_HALF_CPINT_CLR_CLR21_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR21_MASK (0x00200000)
+#define ST_HALF_CPINT_CLR_CLR21_BIT (0x00200000)
+
+#define ST_HALF_CPINT_CLR_CLR20_LSB (20)
+#define ST_HALF_CPINT_CLR_CLR20_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR20_MASK (0x00100000)
+#define ST_HALF_CPINT_CLR_CLR20_BIT (0x00100000)
+
+#define ST_HALF_CPINT_CLR_CLR19_LSB (19)
+#define ST_HALF_CPINT_CLR_CLR19_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR19_MASK (0x00080000)
+#define ST_HALF_CPINT_CLR_CLR19_BIT (0x00080000)
+
+#define ST_HALF_CPINT_CLR_CLR18_LSB (18)
+#define ST_HALF_CPINT_CLR_CLR18_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR18_MASK (0x00040000)
+#define ST_HALF_CPINT_CLR_CLR18_BIT (0x00040000)
+
+#define ST_HALF_CPINT_CLR_CLR17_LSB (17)
+#define ST_HALF_CPINT_CLR_CLR17_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR17_MASK (0x00020000)
+#define ST_HALF_CPINT_CLR_CLR17_BIT (0x00020000)
+
+#define ST_HALF_CPINT_CLR_CLR16_LSB (16)
+#define ST_HALF_CPINT_CLR_CLR16_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR16_MASK (0x00010000)
+#define ST_HALF_CPINT_CLR_CLR16_BIT (0x00010000)
+
+#define ST_HALF_CPINT_CLR_CLR15_LSB (15)
+#define ST_HALF_CPINT_CLR_CLR15_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR15_MASK (0x00008000)
+#define ST_HALF_CPINT_CLR_CLR15_BIT (0x00008000)
+
+#define ST_HALF_CPINT_CLR_CLR14_LSB (14)
+#define ST_HALF_CPINT_CLR_CLR14_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR14_MASK (0x00004000)
+#define ST_HALF_CPINT_CLR_CLR14_BIT (0x00004000)
+
+#define ST_HALF_CPINT_CLR_CLR13_LSB (13)
+#define ST_HALF_CPINT_CLR_CLR13_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR13_MASK (0x00002000)
+#define ST_HALF_CPINT_CLR_CLR13_BIT (0x00002000)
+
+#define ST_HALF_CPINT_CLR_CLR12_LSB (12)
+#define ST_HALF_CPINT_CLR_CLR12_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR12_MASK (0x00001000)
+#define ST_HALF_CPINT_CLR_CLR12_BIT (0x00001000)
+
+#define ST_HALF_CPINT_CLR_CLR11_LSB (11)
+#define ST_HALF_CPINT_CLR_CLR11_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR11_MASK (0x00000800)
+#define ST_HALF_CPINT_CLR_CLR11_BIT (0x00000800)
+
+#define ST_HALF_CPINT_CLR_CLR10_LSB (10)
+#define ST_HALF_CPINT_CLR_CLR10_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR10_MASK (0x00000400)
+#define ST_HALF_CPINT_CLR_CLR10_BIT (0x00000400)
+
+#define ST_HALF_CPINT_CLR_CLR9_LSB (9)
+#define ST_HALF_CPINT_CLR_CLR9_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR9_MASK (0x00000200)
+#define ST_HALF_CPINT_CLR_CLR9_BIT (0x00000200)
+
+#define ST_HALF_CPINT_CLR_CLR8_LSB (8)
+#define ST_HALF_CPINT_CLR_CLR8_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR8_MASK (0x00000100)
+#define ST_HALF_CPINT_CLR_CLR8_BIT (0x00000100)
+
+#define ST_HALF_CPINT_CLR_CLR7_LSB (7)
+#define ST_HALF_CPINT_CLR_CLR7_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR7_MASK (0x00000080)
+#define ST_HALF_CPINT_CLR_CLR7_BIT (0x00000080)
+
+#define ST_HALF_CPINT_CLR_CLR6_LSB (6)
+#define ST_HALF_CPINT_CLR_CLR6_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR6_MASK (0x00000040)
+#define ST_HALF_CPINT_CLR_CLR6_BIT (0x00000040)
+
+#define ST_HALF_CPINT_CLR_CLR5_LSB (5)
+#define ST_HALF_CPINT_CLR_CLR5_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR5_MASK (0x00000020)
+#define ST_HALF_CPINT_CLR_CLR5_BIT (0x00000020)
+
+#define ST_HALF_CPINT_CLR_CLR4_LSB (4)
+#define ST_HALF_CPINT_CLR_CLR4_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR4_MASK (0x00000010)
+#define ST_HALF_CPINT_CLR_CLR4_BIT (0x00000010)
+
+#define ST_HALF_CPINT_CLR_CLR3_LSB (3)
+#define ST_HALF_CPINT_CLR_CLR3_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR3_MASK (0x00000008)
+#define ST_HALF_CPINT_CLR_CLR3_BIT (0x00000008)
+
+#define ST_HALF_CPINT_CLR_CLR2_LSB (2)
+#define ST_HALF_CPINT_CLR_CLR2_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR2_MASK (0x00000004)
+#define ST_HALF_CPINT_CLR_CLR2_BIT (0x00000004)
+
+#define ST_HALF_CPINT_CLR_CLR1_LSB (1)
+#define ST_HALF_CPINT_CLR_CLR1_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR1_MASK (0x00000002)
+#define ST_HALF_CPINT_CLR_CLR1_BIT (0x00000002)
+
+#define ST_HALF_CPINT_CLR_CLR0_LSB (0)
+#define ST_HALF_CPINT_CLR_CLR0_WIDTH (1)
+#define ST_HALF_CPINT_CLR_CLR0_MASK (0x00000001)
+#define ST_HALF_CPINT_CLR_CLR0_BIT (0x00000001)
+
+#define ST_HALF_CPINT_SRC_SRC31_LSB (31)
+#define ST_HALF_CPINT_SRC_SRC31_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC31_MASK (0x80000000)
+#define ST_HALF_CPINT_SRC_SRC31_BIT (0x80000000)
+
+#define ST_HALF_CPINT_SRC_SRC30_LSB (30)
+#define ST_HALF_CPINT_SRC_SRC30_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC30_MASK (0x40000000)
+#define ST_HALF_CPINT_SRC_SRC30_BIT (0x40000000)
+
+#define ST_HALF_CPINT_SRC_SRC29_LSB (29)
+#define ST_HALF_CPINT_SRC_SRC29_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC29_MASK (0x20000000)
+#define ST_HALF_CPINT_SRC_SRC29_BIT (0x20000000)
+
+#define ST_HALF_CPINT_SRC_SRC28_LSB (28)
+#define ST_HALF_CPINT_SRC_SRC28_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC28_MASK (0x10000000)
+#define ST_HALF_CPINT_SRC_SRC28_BIT (0x10000000)
+
+#define ST_HALF_CPINT_SRC_SRC27_LSB (27)
+#define ST_HALF_CPINT_SRC_SRC27_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC27_MASK (0x08000000)
+#define ST_HALF_CPINT_SRC_SRC27_BIT (0x08000000)
+
+#define ST_HALF_CPINT_SRC_SRC26_LSB (26)
+#define ST_HALF_CPINT_SRC_SRC26_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC26_MASK (0x04000000)
+#define ST_HALF_CPINT_SRC_SRC26_BIT (0x04000000)
+
+#define ST_HALF_CPINT_SRC_SRC25_LSB (25)
+#define ST_HALF_CPINT_SRC_SRC25_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC25_MASK (0x02000000)
+#define ST_HALF_CPINT_SRC_SRC25_BIT (0x02000000)
+
+#define ST_HALF_CPINT_SRC_SRC24_LSB (24)
+#define ST_HALF_CPINT_SRC_SRC24_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC24_MASK (0x01000000)
+#define ST_HALF_CPINT_SRC_SRC24_BIT (0x01000000)
+
+#define ST_HALF_CPINT_SRC_SRC23_LSB (23)
+#define ST_HALF_CPINT_SRC_SRC23_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC23_MASK (0x00800000)
+#define ST_HALF_CPINT_SRC_SRC23_BIT (0x00800000)
+
+#define ST_HALF_CPINT_SRC_SRC22_LSB (22)
+#define ST_HALF_CPINT_SRC_SRC22_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC22_MASK (0x00400000)
+#define ST_HALF_CPINT_SRC_SRC22_BIT (0x00400000)
+
+#define ST_HALF_CPINT_SRC_SRC21_LSB (21)
+#define ST_HALF_CPINT_SRC_SRC21_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC21_MASK (0x00200000)
+#define ST_HALF_CPINT_SRC_SRC21_BIT (0x00200000)
+
+#define ST_HALF_CPINT_SRC_SRC20_LSB (20)
+#define ST_HALF_CPINT_SRC_SRC20_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC20_MASK (0x00100000)
+#define ST_HALF_CPINT_SRC_SRC20_BIT (0x00100000)
+
+#define ST_HALF_CPINT_SRC_SRC19_LSB (19)
+#define ST_HALF_CPINT_SRC_SRC19_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC19_MASK (0x00080000)
+#define ST_HALF_CPINT_SRC_SRC19_BIT (0x00080000)
+
+#define ST_HALF_CPINT_SRC_SRC18_LSB (18)
+#define ST_HALF_CPINT_SRC_SRC18_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC18_MASK (0x00040000)
+#define ST_HALF_CPINT_SRC_SRC18_BIT (0x00040000)
+
+#define ST_HALF_CPINT_SRC_SRC17_LSB (17)
+#define ST_HALF_CPINT_SRC_SRC17_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC17_MASK (0x00020000)
+#define ST_HALF_CPINT_SRC_SRC17_BIT (0x00020000)
+
+#define ST_HALF_CPINT_SRC_SRC16_LSB (16)
+#define ST_HALF_CPINT_SRC_SRC16_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC16_MASK (0x00010000)
+#define ST_HALF_CPINT_SRC_SRC16_BIT (0x00010000)
+
+#define ST_HALF_CPINT_SRC_SRC15_LSB (15)
+#define ST_HALF_CPINT_SRC_SRC15_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC15_MASK (0x00008000)
+#define ST_HALF_CPINT_SRC_SRC15_BIT (0x00008000)
+
+#define ST_HALF_CPINT_SRC_SRC14_LSB (14)
+#define ST_HALF_CPINT_SRC_SRC14_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC14_MASK (0x00004000)
+#define ST_HALF_CPINT_SRC_SRC14_BIT (0x00004000)
+
+#define ST_HALF_CPINT_SRC_SRC13_LSB (13)
+#define ST_HALF_CPINT_SRC_SRC13_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC13_MASK (0x00002000)
+#define ST_HALF_CPINT_SRC_SRC13_BIT (0x00002000)
+
+#define ST_HALF_CPINT_SRC_SRC12_LSB (12)
+#define ST_HALF_CPINT_SRC_SRC12_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC12_MASK (0x00001000)
+#define ST_HALF_CPINT_SRC_SRC12_BIT (0x00001000)
+
+#define ST_HALF_CPINT_SRC_SRC11_LSB (11)
+#define ST_HALF_CPINT_SRC_SRC11_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC11_MASK (0x00000800)
+#define ST_HALF_CPINT_SRC_SRC11_BIT (0x00000800)
+
+#define ST_HALF_CPINT_SRC_SRC10_LSB (10)
+#define ST_HALF_CPINT_SRC_SRC10_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC10_MASK (0x00000400)
+#define ST_HALF_CPINT_SRC_SRC10_BIT (0x00000400)
+
+#define ST_HALF_CPINT_SRC_SRC9_LSB (9)
+#define ST_HALF_CPINT_SRC_SRC9_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC9_MASK (0x00000200)
+#define ST_HALF_CPINT_SRC_SRC9_BIT (0x00000200)
+
+#define ST_HALF_CPINT_SRC_SRC8_LSB (8)
+#define ST_HALF_CPINT_SRC_SRC8_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC8_MASK (0x00000100)
+#define ST_HALF_CPINT_SRC_SRC8_BIT (0x00000100)
+
+#define ST_HALF_CPINT_SRC_SRC7_LSB (7)
+#define ST_HALF_CPINT_SRC_SRC7_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC7_MASK (0x00000080)
+#define ST_HALF_CPINT_SRC_SRC7_BIT (0x00000080)
+
+#define ST_HALF_CPINT_SRC_SRC6_LSB (6)
+#define ST_HALF_CPINT_SRC_SRC6_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC6_MASK (0x00000040)
+#define ST_HALF_CPINT_SRC_SRC6_BIT (0x00000040)
+
+#define ST_HALF_CPINT_SRC_SRC5_LSB (5)
+#define ST_HALF_CPINT_SRC_SRC5_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC5_MASK (0x00000020)
+#define ST_HALF_CPINT_SRC_SRC5_BIT (0x00000020)
+
+#define ST_HALF_CPINT_SRC_SRC4_LSB (4)
+#define ST_HALF_CPINT_SRC_SRC4_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC4_MASK (0x00000010)
+#define ST_HALF_CPINT_SRC_SRC4_BIT (0x00000010)
+
+#define ST_HALF_CPINT_SRC_SRC3_LSB (3)
+#define ST_HALF_CPINT_SRC_SRC3_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC3_MASK (0x00000008)
+#define ST_HALF_CPINT_SRC_SRC3_BIT (0x00000008)
+
+#define ST_HALF_CPINT_SRC_SRC2_LSB (2)
+#define ST_HALF_CPINT_SRC_SRC2_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC2_MASK (0x00000004)
+#define ST_HALF_CPINT_SRC_SRC2_BIT (0x00000004)
+
+#define ST_HALF_CPINT_SRC_SRC1_LSB (1)
+#define ST_HALF_CPINT_SRC_SRC1_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC1_MASK (0x00000002)
+#define ST_HALF_CPINT_SRC_SRC1_BIT (0x00000002)
+
+#define ST_HALF_CPINT_SRC_SRC0_LSB (0)
+#define ST_HALF_CPINT_SRC_SRC0_WIDTH (1)
+#define ST_HALF_CPINT_SRC_SRC0_MASK (0x00000001)
+#define ST_HALF_CPINT_SRC_SRC0_BIT (0x00000001)
+
+#define ST_HALF_CPINT_ISR_ISR31_LSB (31)
+#define ST_HALF_CPINT_ISR_ISR31_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR31_MASK (0x80000000)
+#define ST_HALF_CPINT_ISR_ISR31_BIT (0x80000000)
+
+#define ST_HALF_CPINT_ISR_ISR30_LSB (30)
+#define ST_HALF_CPINT_ISR_ISR30_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR30_MASK (0x40000000)
+#define ST_HALF_CPINT_ISR_ISR30_BIT (0x40000000)
+
+#define ST_HALF_CPINT_ISR_ISR29_LSB (29)
+#define ST_HALF_CPINT_ISR_ISR29_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR29_MASK (0x20000000)
+#define ST_HALF_CPINT_ISR_ISR29_BIT (0x20000000)
+
+#define ST_HALF_CPINT_ISR_ISR28_LSB (28)
+#define ST_HALF_CPINT_ISR_ISR28_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR28_MASK (0x10000000)
+#define ST_HALF_CPINT_ISR_ISR28_BIT (0x10000000)
+
+#define ST_HALF_CPINT_ISR_ISR27_LSB (27)
+#define ST_HALF_CPINT_ISR_ISR27_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR27_MASK (0x08000000)
+#define ST_HALF_CPINT_ISR_ISR27_BIT (0x08000000)
+
+#define ST_HALF_CPINT_ISR_ISR26_LSB (26)
+#define ST_HALF_CPINT_ISR_ISR26_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR26_MASK (0x04000000)
+#define ST_HALF_CPINT_ISR_ISR26_BIT (0x04000000)
+
+#define ST_HALF_CPINT_ISR_ISR25_LSB (25)
+#define ST_HALF_CPINT_ISR_ISR25_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR25_MASK (0x02000000)
+#define ST_HALF_CPINT_ISR_ISR25_BIT (0x02000000)
+
+#define ST_HALF_CPINT_ISR_ISR24_LSB (24)
+#define ST_HALF_CPINT_ISR_ISR24_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR24_MASK (0x01000000)
+#define ST_HALF_CPINT_ISR_ISR24_BIT (0x01000000)
+
+#define ST_HALF_CPINT_ISR_ISR23_LSB (23)
+#define ST_HALF_CPINT_ISR_ISR23_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR23_MASK (0x00800000)
+#define ST_HALF_CPINT_ISR_ISR23_BIT (0x00800000)
+
+#define ST_HALF_CPINT_ISR_ISR22_LSB (22)
+#define ST_HALF_CPINT_ISR_ISR22_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR22_MASK (0x00400000)
+#define ST_HALF_CPINT_ISR_ISR22_BIT (0x00400000)
+
+#define ST_HALF_CPINT_ISR_ISR21_LSB (21)
+#define ST_HALF_CPINT_ISR_ISR21_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR21_MASK (0x00200000)
+#define ST_HALF_CPINT_ISR_ISR21_BIT (0x00200000)
+
+#define ST_HALF_CPINT_ISR_ISR20_LSB (20)
+#define ST_HALF_CPINT_ISR_ISR20_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR20_MASK (0x00100000)
+#define ST_HALF_CPINT_ISR_ISR20_BIT (0x00100000)
+
+#define ST_HALF_CPINT_ISR_ISR19_LSB (19)
+#define ST_HALF_CPINT_ISR_ISR19_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR19_MASK (0x00080000)
+#define ST_HALF_CPINT_ISR_ISR19_BIT (0x00080000)
+
+#define ST_HALF_CPINT_ISR_ISR18_LSB (18)
+#define ST_HALF_CPINT_ISR_ISR18_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR18_MASK (0x00040000)
+#define ST_HALF_CPINT_ISR_ISR18_BIT (0x00040000)
+
+#define ST_HALF_CPINT_ISR_ISR17_LSB (17)
+#define ST_HALF_CPINT_ISR_ISR17_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR17_MASK (0x00020000)
+#define ST_HALF_CPINT_ISR_ISR17_BIT (0x00020000)
+
+#define ST_HALF_CPINT_ISR_ISR16_LSB (16)
+#define ST_HALF_CPINT_ISR_ISR16_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR16_MASK (0x00010000)
+#define ST_HALF_CPINT_ISR_ISR16_BIT (0x00010000)
+
+#define ST_HALF_CPINT_ISR_ISR15_LSB (15)
+#define ST_HALF_CPINT_ISR_ISR15_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR15_MASK (0x00008000)
+#define ST_HALF_CPINT_ISR_ISR15_BIT (0x00008000)
+
+#define ST_HALF_CPINT_ISR_ISR14_LSB (14)
+#define ST_HALF_CPINT_ISR_ISR14_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR14_MASK (0x00004000)
+#define ST_HALF_CPINT_ISR_ISR14_BIT (0x00004000)
+
+#define ST_HALF_CPINT_ISR_ISR13_LSB (13)
+#define ST_HALF_CPINT_ISR_ISR13_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR13_MASK (0x00002000)
+#define ST_HALF_CPINT_ISR_ISR13_BIT (0x00002000)
+
+#define ST_HALF_CPINT_ISR_ISR12_LSB (12)
+#define ST_HALF_CPINT_ISR_ISR12_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR12_MASK (0x00001000)
+#define ST_HALF_CPINT_ISR_ISR12_BIT (0x00001000)
+
+#define ST_HALF_CPINT_ISR_ISR11_LSB (11)
+#define ST_HALF_CPINT_ISR_ISR11_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR11_MASK (0x00000800)
+#define ST_HALF_CPINT_ISR_ISR11_BIT (0x00000800)
+
+#define ST_HALF_CPINT_ISR_ISR10_LSB (10)
+#define ST_HALF_CPINT_ISR_ISR10_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR10_MASK (0x00000400)
+#define ST_HALF_CPINT_ISR_ISR10_BIT (0x00000400)
+
+#define ST_HALF_CPINT_ISR_ISR9_LSB (9)
+#define ST_HALF_CPINT_ISR_ISR9_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR9_MASK (0x00000200)
+#define ST_HALF_CPINT_ISR_ISR9_BIT (0x00000200)
+
+#define ST_HALF_CPINT_ISR_ISR8_LSB (8)
+#define ST_HALF_CPINT_ISR_ISR8_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR8_MASK (0x00000100)
+#define ST_HALF_CPINT_ISR_ISR8_BIT (0x00000100)
+
+#define ST_HALF_CPINT_ISR_ISR7_LSB (7)
+#define ST_HALF_CPINT_ISR_ISR7_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR7_MASK (0x00000080)
+#define ST_HALF_CPINT_ISR_ISR7_BIT (0x00000080)
+
+#define ST_HALF_CPINT_ISR_ISR6_LSB (6)
+#define ST_HALF_CPINT_ISR_ISR6_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR6_MASK (0x00000040)
+#define ST_HALF_CPINT_ISR_ISR6_BIT (0x00000040)
+
+#define ST_HALF_CPINT_ISR_ISR5_LSB (5)
+#define ST_HALF_CPINT_ISR_ISR5_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR5_MASK (0x00000020)
+#define ST_HALF_CPINT_ISR_ISR5_BIT (0x00000020)
+
+#define ST_HALF_CPINT_ISR_ISR4_LSB (4)
+#define ST_HALF_CPINT_ISR_ISR4_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR4_MASK (0x00000010)
+#define ST_HALF_CPINT_ISR_ISR4_BIT (0x00000010)
+
+#define ST_HALF_CPINT_ISR_ISR3_LSB (3)
+#define ST_HALF_CPINT_ISR_ISR3_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR3_MASK (0x00000008)
+#define ST_HALF_CPINT_ISR_ISR3_BIT (0x00000008)
+
+#define ST_HALF_CPINT_ISR_ISR2_LSB (2)
+#define ST_HALF_CPINT_ISR_ISR2_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR2_MASK (0x00000004)
+#define ST_HALF_CPINT_ISR_ISR2_BIT (0x00000004)
+
+#define ST_HALF_CPINT_ISR_ISR1_LSB (1)
+#define ST_HALF_CPINT_ISR_ISR1_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR1_MASK (0x00000002)
+#define ST_HALF_CPINT_ISR_ISR1_BIT (0x00000002)
+
+#define ST_HALF_CPINT_ISR_ISR0_LSB (0)
+#define ST_HALF_CPINT_ISR_ISR0_WIDTH (1)
+#define ST_HALF_CPINT_ISR_ISR0_MASK (0x00000001)
+#define ST_HALF_CPINT_ISR_ISR0_BIT (0x00000001)
+
+#define ST_CFG_CPINT_TIME_SYSTEM_TIME_CNT_LSB (2)
+#define ST_CFG_CPINT_TIME_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_CFG_CPINT_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_CFG_CPINT_EN_EN_LSB (0)
+#define ST_CFG_CPINT_EN_EN_WIDTH (1)
+#define ST_CFG_CPINT_EN_EN_MASK (0x00000001)
+#define ST_CFG_CPINT_EN_EN_BIT (0x00000001)
+
+#define ST_CFG_CPINT_ISR_ISR_LSB (0)
+#define ST_CFG_CPINT_ISR_ISR_WIDTH (1)
+#define ST_CFG_CPINT_ISR_ISR_MASK (0x00000001)
+#define ST_CFG_CPINT_ISR_ISR_BIT (0x00000001)
+
+#define ST_CFG_CPINT_CLR_CLR_LSB (0)
+#define ST_CFG_CPINT_CLR_CLR_WIDTH (1)
+#define ST_CFG_CPINT_CLR_CLR_MASK (0x00000001)
+#define ST_CFG_CPINT_CLR_CLR_BIT (0x00000001)
+
+#define ST_SUBFR_STATUS_SUBFR_STATUS_LSB (0)
+#define ST_SUBFR_STATUS_SUBFR_STATUS_WIDTH (6)
+#define ST_SUBFR_STATUS_SUBFR_STATUS_MASK (0x0000003F)
+
+#define ST_SYSCNT_SYSTEM_TIME_CNT_LSB (0)
+#define ST_SYSCNT_SYSTEM_TIME_CNT_WIDTH (20)
+#define ST_SYSCNT_SYSTEM_TIME_CNT_MASK (0x000FFFFF)
+#define ST_SYSCNT_SYSTEM_TIME_CNT_MAX (0x000BFFFF)
+#define ST_SYSCNT_SYSTEM_TIME_CNT_ROUND (0x000C0000)
+
+#define ST_SUPFRM_CNT_L_SUPFRM_CNT_LSB (0)
+#define ST_SUPFRM_CNT_L_SUPFRM_CNT_WIDTH (32)
+#define ST_SUPFRM_CNT_L_SUPFRM_CNT_MASK (0xFFFFFFFF)
+
+#define ST_SUPFRM_CNT_H_SUPFRM_CNT_LSB (0)
+#define ST_SUPFRM_CNT_H_SUPFRM_CNT_WIDTH (4)
+#define ST_SUPFRM_CNT_H_SUPFRM_CNT_MASK (0x0000000F)
+
+#define ST_FRC_TIMING_SYNC_MODE_MODE_LSB (0)
+#define ST_FRC_TIMING_SYNC_MODE_MODE_WIDTH (1)
+#define ST_FRC_TIMING_SYNC_MODE_MODE_MASK (0x00000001)
+#define ST_FRC_TIMING_SYNC_MODE_MODE_BIT (0x00000001)
+
+#define ST_FRC_TIMING_SYNC_CMP_SYSTEM_TIME_CNT_LSB (2)
+#define ST_FRC_TIMING_SYNC_CMP_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_FRC_TIMING_SYNC_CMP_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_FRC_TIMING_SYNC_TRIG_TRIG_LSB (0)
+#define ST_FRC_TIMING_SYNC_TRIG_TRIG_WIDTH (1)
+#define ST_FRC_TIMING_SYNC_TRIG_TRIG_MASK (0x00000001)
+#define ST_FRC_TIMING_SYNC_TRIG_TRIG_BIT (0x00000001)
+
+#define ST_FRC_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_LSB (0)
+#define ST_FRC_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_WIDTH (20)
+#define ST_FRC_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_MASK (0x000FFFFF)
+
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L_SUPFRM_CNT_LSB (0)
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L_SUPFRM_CNT_WIDTH (32)
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_L_SUPFRM_CNT_MASK (0xFFFFFFFF)
+
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H_SUPFRM_CNT_LSB (0)
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H_SUPFRM_CNT_WIDTH (4)
+#define ST_FRC_TIMING_SYNC_SUPFRM_CNT_H_SUPFRM_CNT_MASK (0x0000000F)
+
+#define ST_MU_SFO_EN_LSB (31)
+#define ST_MU_SFO_EN_WIDTH (1)
+#define ST_MU_SFO_EN_MASK (0x80000000)
+#define ST_MU_SFO_EN_BIT (0x80000000)
+
+#define ST_MU_SFO_AFC_PPB_LSB (0)
+#define ST_MU_SFO_AFC_PPB_WIDTH (16)
+#define ST_MU_SFO_AFC_PPB_MASK (0x0000FFFF)
+
+#define ST_MU_ACC_INI_L_MU_ACC_INI_LSB_LSB (0)
+#define ST_MU_ACC_INI_L_MU_ACC_INI_LSB_WIDTH (32)
+#define ST_MU_ACC_INI_L_MU_ACC_INI_LSB_MASK (0xFFFFFFFF)
+
+#define ST_MU_ACC_INI_H_MU_ACC_INI_MSB_LSB (0)
+#define ST_MU_ACC_INI_H_MU_ACC_INI_MSB_WIDTH (8)
+#define ST_MU_ACC_INI_H_MU_ACC_INI_MSB_MASK (0x000000FF)
+
+#define ST_MU_ACC_SET_EN_LSB (31)
+#define ST_MU_ACC_SET_EN_WIDTH (1)
+#define ST_MU_ACC_SET_EN_MASK (0x80000000)
+#define ST_MU_ACC_SET_EN_BIT (0x80000000)
+
+#define ST_MU_ACC_SET_SYSTEM_TIME_CNT_LSB (2)
+#define ST_MU_ACC_SET_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_MU_ACC_SET_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_RAKE_CTL_TIME3_EN_LSB (31)
+#define ST_RAKE_CTL_TIME3_EN_WIDTH (1)
+#define ST_RAKE_CTL_TIME3_EN_MASK (0x80000000)
+#define ST_RAKE_CTL_TIME3_EN_BIT (0x80000000)
+
+#define ST_RAKE_CTL_TIME3_SYSTEM_TIME_CNT_LSB (7)
+#define ST_RAKE_CTL_TIME3_SYSTEM_TIME_CNT_WIDTH (13)
+#define ST_RAKE_CTL_TIME3_SYSTEM_TIME_CNT_MASK (0x000FFF80)
+
+#define ST_GSR_CTL_TIME2_SYSTEM_TIME_CNT_LSB (2)
+#define ST_GSR_CTL_TIME2_SYSTEM_TIME_CNT_WIDTH (18)
+#define ST_GSR_CTL_TIME2_SYSTEM_TIME_CNT_MASK (0x000FFFFC)
+
+#define ST_GSR_SYNC_TRIG_TRIG_LSB (31)
+#define ST_GSR_SYNC_TRIG_TRIG_WIDTH (1)
+#define ST_GSR_SYNC_TRIG_TRIG_MASK (0x80000000)
+#define ST_GSR_SYNC_TRIG_TRIG_BIT (0x80000000)
+
+#define ST_GSR_SYNC_TAG_GSR_SAMPLE_CNT_LSB (2)
+#define ST_GSR_SYNC_TAG_GSR_SAMPLE_CNT_WIDTH (18)
+#define ST_GSR_SYNC_TAG_GSR_SAMPLE_CNT_MASK (0x000FFFFC)
+
+#define ST_1XDO_TIMING_SYNC_TRIG_TRIG_LSB (0)
+#define ST_1XDO_TIMING_SYNC_TRIG_TRIG_WIDTH (1)
+#define ST_1XDO_TIMING_SYNC_TRIG_TRIG_MASK (0x00000001)
+#define ST_1XDO_TIMING_SYNC_TRIG_TRIG_BIT (0x00000001)
+
+#define ST_1XDO_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_LSB (0)
+#define ST_1XDO_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_WIDTH (20)
+#define ST_1XDO_TIMING_SYNC_SYSCNT_SYSTEM_TIME_CNT_MASK (0x000FFFFF)
+
+#define ST_1XDOMRG_EN_EN_LSB (0)
+#define ST_1XDOMRG_EN_EN_WIDTH (1)
+#define ST_1XDOMRG_EN_EN_MASK (0x00000001)
+#define ST_1XDOMRG_EN_EN_BIT (0x00000001)
+
+#define ST_1XDOMRG_INI_TIME_SYSTEM_TIME_CNT_LSB (3)
+#define ST_1XDOMRG_INI_TIME_SYSTEM_TIME_CNT_WIDTH (17)
+#define ST_1XDOMRG_INI_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFF8)
+
+#define ST_1XDOMRG_OFFSET_SYSTEM_TIME_CNT_OFFSET_LSB (3)
+#define ST_1XDOMRG_OFFSET_SYSTEM_TIME_CNT_OFFSET_WIDTH (17)
+#define ST_1XDOMRG_OFFSET_SYSTEM_TIME_CNT_OFFSET_MASK (0x000FFFF8)
+
+#define ST_GPS_EN_GPS_EN_LSB (0)
+#define ST_GPS_EN_GPS_EN_WIDTH (1)
+#define ST_GPS_EN_GPS_EN_MASK (0x00000001)
+#define ST_GPS_EN_GPS_EN_BIT (0x00000001)
+
+#endif