[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/gl1/external/hal_l1_def.h b/mcu/interface/l1/gl1/external/hal_l1_def.h
new file mode 100644
index 0000000..b1c21f2
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/hal_l1_def.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * hal_l1_def.h
+ *
+ * Project:
+ * --------
+ * GSM_Software
+ *
+ * Description:
+ * ------------
+ * This file contains common typedef, definition prototypes exported by L1 for MMI/Middleware
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _HAL_L1_DEF_H
+#define _HAL_L1_DEF_H
+
+#if defined(__L1_GPS_REF_TIME_SUPPORT__) || defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__)
+/* Shihyao, add it to support GPS time sync procedure*/
+typedef enum
+{
+ MPH_FINE_TIME_ASSISTANCE_APP=0,
+ MPH_REFERENCE_TIME_UNCERTAINTY_APP,
+ MPH_FRAME_TIME_AIDING_APP,
+ MPH_AGPS_FRAME_SYNC_APP_END
+}mph_agps_frame_sync_app_enum;
+
+typedef enum
+{
+ MPH_NO_FAILURE=0,
+ MPH_CELL_NOT_FOUND,
+ MPH_2G_NOT_ACTIVE,
+ MPH_TIMING_ERROR_CHECK_FAIL,
+ MPH_TIMING_CALC_IN_OTHER_RAT,
+ MPH_SERVING_CELL_NOT_MATCHED_FOR_TYPE1_2,
+ MPH_LEAVE_DEDICATED_FOR_TYPE1_2,
+ MPH_LEAVE_SCELL_BEFORE_FOR_TYPE3,
+ MPH_AGPS_FRAME_SYNC_FAIL_END
+}mph_agps_frame_sync_fail_enum;
+
+#endif /* end of (__L1_GPS_REF_TIME_SUPPORT__) || (__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__)*/
+
+
+#endif
diff --git a/mcu/interface/l1/gl1/external/hal_l1_struct.h b/mcu/interface/l1/gl1/external/hal_l1_struct.h
new file mode 100644
index 0000000..3166809
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/hal_l1_struct.h
@@ -0,0 +1,135 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * hal_l1_struct.h
+ *
+ * Project:
+ * --------
+ * GSM_Software
+ *
+ * Description:
+ * ------------
+ * 2G Layer 1 and Protocol Stack message and callback function definition for MMI/Middleware
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _HAL_L1_STRUCT_H
+#define _HAL_L1_STRUCT_H
+
+#include "hal_l1_def.h"
+#include "kal_public_defs.h"
+
+#if defined(__L1_GPS_REF_TIME_SUPPORT__) || defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__)
+/***************************************************************************
+* PRIMITIVE STRUCTURE
+* hal_l1_gps_time_sync_req_struct
+*
+* DESCRIPTION
+*
+***************************************************************************/
+typedef struct
+{
+ /* Shihyao, add it to support GPS time sync procedure*/
+ LOCAL_PARA_HDR
+ mph_agps_frame_sync_app_enum application_type;
+
+ kal_int16 arfcn;
+ kal_int8 bsic;
+
+ kal_bool is_maintain_phase; /* true : maintain phase*/
+}hal_l1_gps_time_sync_req_struct;
+
+/***************************************************************************
+* PRIMITIVE STRUCTURE
+* hal_l1_gps_time_sync_ind_struct
+*
+* DESCRIPTION
+*
+***************************************************************************/
+typedef struct
+{
+ /* Shihyao, add it to support GPS time sync procedure*/
+ LOCAL_PARA_HDR
+ mph_agps_frame_sync_app_enum application_type;
+ mph_agps_frame_sync_fail_enum fail_cause;
+
+ kal_bool result_valid;
+ kal_int32 frame;
+ kal_int32 ebit;
+
+ kal_bool local_time_valid;
+ kal_uint64 local_time;
+
+ kal_int16 serving_arfcn;
+ kal_int8 serving_bsic;
+
+}hal_l1_gps_time_sync_ind_struct;
+#endif
+
+
+#endif /*_HAL_UL1_STRUCT_H*/
+
diff --git a/mcu/interface/l1/gl1/external/l1_gemini_def.h b/mcu/interface/l1/gl1/external/l1_gemini_def.h
new file mode 100644
index 0000000..289be5b
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1_gemini_def.h
@@ -0,0 +1,137 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1_gemini_option.h
+ *
+ * Project:
+ * --------
+ * MT6290
+ *
+ * Description:
+ * ------------
+ * The global gemini compile option definition of L1
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
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+ * removed!
+ *******************************************************************************/
+
+#ifndef __L1_GEMINI_DEF_H__
+#define __L1_GEMINI_DEF_H__
+
+/* define GEMINI related GL1A/GL1C internal option */
+/***********************************************************
+ * SGLTE(__SGLTE__) SGLTE DSDS
+ * __GEMINI__ N Y
+ * __GEMINI_PLUS_GSM_ N 3
+ * __SGLTE__ Y Y
+ * =============== above: project option ==================
+ * =============== below: GL1 internal option =============
+ * __GL1_GEMINI__ Y Y
+ * GL1_GEMINI_NUM 2 3
+ ***********************************************************/
+#if defined(__GEMINI__)
+#define __GL1_GEMINI__
+
+ #if defined(__GEMINI_WCDMA__)
+#define __GL1_GEMINI_WCDMA__
+ #if defined(GEMINI_PLUS_WCDMA)
+#define GL1_GEMINI_WCDMA_NUM GEMINI_PLUS_WCDMA
+ #else
+#define GL1_GEMINI_WCDMA_NUM 2
+ #endif
+ #endif /* __GEMINI_WCDMA__ */
+
+ #if defined(GEMINI_PLUS_GSM)
+#define GL1_GEMINI_NUM GEMINI_PLUS_GSM
+ #else
+#define GL1_GEMINI_NUM 2
+ #endif
+
+
+#define SEARCH_VIRTUAL_PLMN_BSIC_IN_IDLE_FRAME 1
+
+/* MULTIPLE_PS will be enabled by default on UMOLY */
+#define __IRAT_MEAS_SUPPORT_IN_VIRTUAL_MODE__ 1
+
+
+#endif
+
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1_interface_reg.h b/mcu/interface/l1/gl1/external/l1_interface_reg.h
new file mode 100644
index 0000000..dca2333
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1_interface_reg.h
@@ -0,0 +1,622 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1_interface_reg.h
+ *
+ * Project:
+ * --------
+ * MT6280
+ *
+ * Description:
+ * ------------
+ * Registers and constants definitions for interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
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+ *******************************************************************************/
+
+#ifndef _L1_INTERFACE_REG_H_
+#define _L1_INTERFACE_REG_H_
+
+#include "drvpdn.h"
+
+#include "reg_base.h"
+#include "l1_option.h"
+
+#ifndef _COMMON_REG_H_
+typedef volatile unsigned short* APBADDR; /* APB addr is 32 bits */
+typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */
+#endif
+
+#if defined(L1_SIM)
+ #if MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+/* Here are new and old regbase nameing remapping since xL1SIM HW simu code still uses old regbase naming. */
+#define TDMA_base L1_BASE_MADDR_TDMA_BASE
+#define MD2GCONFG_base L1_BASE_MADDR_MD2G_CONFG
+ #endif
+#endif
+
+
+#if MD_DRV_IS_CHIP_MT6297
+#define BASE_NADDR_TXSYS_DIGRF_TXDFE_BB (0xB9450000)
+#define BASE_MADDR_TXSYS_DIGRF_TXDFE_BB (0xB9450000)
+#endif
+/***************************************************************************************************************************
+ * Rigister definition for other modules *
+ ***************************************************************************************************************************/
+
+/*====================*\
+|* TDMA *|
+\*====================*/
+#if MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+/*TK6291~*/ #define EVENT_ENA_OFFSET(n) (((n)>7)?2176:0)
+/*TK6291~*/
+/*TK6291~*/ /* TDMA timer */
+/*TK6291~*/ #define TQ_CURRENT_COUNT ((APBADDR )(L1_BASE_MADDR_TDMA_BASE+0x0000)) /* read quater bit counter [13:0] */
+/*TK6291~*/ #define TQ_EVENT_VALID ((APBADDR )(L1_BASE_MADDR_TDMA_BASE+0x000C)) /* event latch position [13:0] */
+/*TK6291~*/ #define CTIRQ1 ((APBADDR )(L1_BASE_MADDR_TDMA_BASE+0x0014)) /* CPU tdma interrupt 1 [13:0] */
+/*TK6291~*/ #define EVENT_ENA(n) ((APBADDR32)(L1_BASE_MADDR_TDMA_BASE+0x0150+((n)*4)+EVENT_ENA_OFFSET(n))) /* event enable control n */
+/*TK6291~*/ #define TQ_BIAS_CONT ((APBADDR )(L1_BASE_MADDR_TDMA_BASE+0x0174)) /* Qbit Timer Biasing Control Register */
+/*TK6291~*/ #define TDMA_AUXEV0 ((APBADDR )(L1_BASE_MADDR_TDMA_BASE+0x0400)) /* Auxiliary ADC event 0 */
+/*TK6291~*/ #define TDMA_AUXEV1 ((APBADDR )(L1_BASE_MADDR_TDMA_BASE+0x0404)) /* Auxiliary ADC event 1 */
+/*TK6291~*/ #define TDMA_AUXEVENA EVENT_ENA(7) /* Auxiliary ADC event enable register */
+/*TK6291~*/ /* TDMA sleep */
+ #if MD_DRV_IS_2G_BANK_B_ENABLE
+/*MT6293~*/ #define TQ_WRAP ((APBADDR )(L1_BASE_NADDR_TDMA_SLP +0x0004)) /* latched Qbit counter reset position [13:0] */
+ #else
+/*TK6291~*/ #define TQ_WRAP ((APBADDR )(L1_BASE_MADDR_TDMA_SLP +0x0004)) /* latched Qbit counter reset position [13:0] */
+ #endif
+#else
+/*else */ #error "Please check TDMA related settings"
+#endif
+/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
+
+/* Sleep mode */
+#if defined(L1_SIM)
+ #if MD_DRV_IS_CENTRALIZED_SMM_CHIP
+#define SleepMode_base TOPSM_base
+ #else
+#define SleepMode_base SM_base
+ #endif
+
+ #if MD_DRV_IS_CENTRALIZED_SMM_CHIP
+#define RTCCOUNT ((APBADDR32)(SleepMode_base+0x0104)) /* 32K count */
+ #else
+#define RTCCOUNT ((APBADDR32)(SleepMode_base+0x0030)) /* 32K count */
+ #endif
+
+ #if MD_DRV_IS_CENTRALIZED_SMM_CHIP
+#define SM_FRC_CON ((APBADDR32)(SleepMode_base+0x0080)) /* Free Running Counter Control Register */
+#define SM_FM_CAL ((APBADDR32)(SleepMode_base+0x00B4)) /* Frequency Measurement Calibration Control */
+#define SM_FM_T0 ((APBADDR32)(SleepMode_base+0x00B8)) /* Frequency Measurement Start Time */
+#define SM_FM_T1 ((APBADDR32)(SleepMode_base+0x00BC)) /* Frequency Measurement End Time */
+#define SM_FM_CON ((APBADDR32)(SleepMode_base+0x00B0)) /* Frequency Measurement Control Register */
+ #endif
+#endif /* defined(L1_SIM) */
+
+/*====================*\
+|* IDMA *|
+\*====================*/
+#if MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+/*TK6291~*/ #define IDMA_LONG (L1_BASE_MADDR_SHORTMODE_IDMA)
+ #if MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+ #if MD_DRV_IS_2G_BANK_B_ENABLE
+/*MT6293~*/ #define L1_BASE_MADDR_CM_IDMA BASE_NADDR_MD2GSYS_IDMA_CM
+/*MT6293~*/ #define L1_BASE_MADDR_PM_IDMA BASE_NADDR_MD2GSYS_IDMA_PM
+/*MT6293~*/ #define L1_BASE_MADDR_DM_IDMA BASE_NADDR_MD2GSYS_IDMA_DM
+ #if MD_DRV_IS_CHIP_MT6297
+/*MT6297~*/ #define L1_BASE_MADDR_TDMA_BASE BASE_NADDR_MODEML1_AO_TDMA_TMR
+ #else
+/*MT6293~*/ #define L1_BASE_MADDR_TDMA_BASE BASE_NADDR_MD2GSYS_TDMA_BASE
+ #endif
+/*MT6293~*/ #define L1_BASE_MADDR_MD2G_CONFG BASE_NADDR_MD2GSYS_MD2G_CONFG
+/*MT6293~*/ #define L1_BASE_MADDR_SHARE_D1 BASE_NADDR_MD2GSYS_SHARE_D1
+/*MT6293~*/ #define L1_BASE_MADDR_PATCH BASE_NADDR_MD2GSYS_PATCH
+ #if MD_DRV_IS_CHIP_MT6297
+/*MT6297~*/ #define L1_BASE_MADDR_APC BASE_NADDR_DIFRF_OFF_TOP_DIGRF_APC
+ #else
+/*MT6293~*/ #define L1_BASE_MADDR_APC BASE_NADDR_MD2GSYS_APC
+ #endif
+ #if MD_DRV_IS_CHIP_MT6297
+/*MT6297~*/ #define L1_BASE_MADDR_D2BIF_TDMA (BASE_NADDR_BIGRAM0_BIGRAM_D2BIF + 0x0000C000) // D2BIF_TDMA for 2g
+/*MT6297~*/ #define L1_BASE_MADDR_TX_DFE_D_DIE BASE_NADDR_DFESYS_TXDFE_D
+/*MT6297~*/ #define L1_BASE_MADDR_MDPAR_DBGON BASE_NADDR_MDPERI_MDPAR_DBGMON
+/*MT6297~*/ #define L1_BASE_MADDR_BFE BASE_NADDR_DFESYS_RXDFE_BB_BFE0
+/*MT6297~*/ #define L1_BASE_MADDR_BFE_1 BASE_NADDR_DFESYS_RXDFE_BB_BFE1
+/*MT6297~*/ #define L1_BASE_MADDR_TX_DFE_A_DIE (BASE_NADDR_TXSYS_DIGRF_TXDFE_BB + 0x0000F000) //Tx DFE A DIE
+/*MT6297~*/ #define L1_BASE_MADDR_TX_DFESYS_GLB_CON BASE_NADDR_DFESYS_GLB_CON_CONFIG1
+/*MT6297~*/ #define L1_BASE_TOP_DIGRF_EVT_GEN BASE_NADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN
+/*MT6297~*/ #define L1_BASE_MADDR_TXK_DFE_A_DIE BASE_NADDR_DIGRF_TX_TOP_TXK_WRAP_2 //TXK BASE RG
+/*MT6297~*/ #define L1_BASE_MADDR_L1D_TXK_CLK BASE_NADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL //TXK CLK
+ #else
+/*MT6293~*/ #define L1_BASE_MADDR_BFE BASE_NADDR_MD2GSYS_BFE
+ #if MD_DRV_IS_CHIP_MT6765 || MD_DRV_IS_CHIP_MT6295
+/*MT6765~*/ #define L1_BASE_MADDR_BFE_1 BASE_NADDR_MD2GSYS_BFE_2ND
+ #endif /* MD_DRV_IS_CHIP_MT6765 */
+ #endif
+/*MT6293~*/ #define L1_BASE_MADDR_MD2G_MEM_CONFG BASE_NADDR_MODEML1_AO_FESYS_P2P_TX
+ #if defined (L1D_TEST)
+/*MT6293~*/ #define L1_BASE_MADDR_IRDMA BASE_NADDR_MD2GSYS_IRDBG
+ #else
+/*MT6293~*/ #define L1_BASE_MADDR_IRDMA BASE_NADDR_FESYS_MD2G_IRDMA
+ #endif
+ #else
+/*MT6293~*/ #define L1_BASE_MADDR_CM_IDMA BASE_MADDR_MD2GSYS_IDMA_CM
+/*MT6293~*/ #define L1_BASE_MADDR_PM_IDMA BASE_MADDR_MD2GSYS_IDMA_PM
+/*MT6293~*/ #define L1_BASE_MADDR_DM_IDMA BASE_MADDR_MD2GSYS_IDMA_DM
+ #if MD_DRV_IS_CHIP_MT6297
+/*MT6297~*/ #define L1_BASE_MADDR_TDMA_BASE BASE_MADDR_MODEML1_AO_TDMA_TMR
+ #else
+/*MT6293~*/ #define L1_BASE_MADDR_TDMA_BASE L1_TDMA_BASE
+ #endif
+/*MT6293~*/ #define L1_BASE_MADDR_MD2G_CONFG BASE_MADDR_MD2G_CONFG
+/*MT6293~*/ #define L1_BASE_MADDR_SHARE_D1 BASE_MADDR_MD2GSYS_SHARE_D1
+/*MT6293~*/ #define L1_BASE_MADDR_PATCH BASE_MADDR_MD2GSYS_PATCH
+ #if MD_DRV_IS_CHIP_MT6297
+/*MT6297~*/ #define L1_BASE_MADDR_APC BASE_MADDR_DIFRF_OFF_TOP_DIGRF_APC
+ #else
+/*MT6293~*/ #define L1_BASE_MADDR_APC BASE_MADDR_MD2GSYS_APC
+ #endif
+ #if MD_DRV_IS_CHIP_MT6297
+/*MT6297~*/ #define L1_BASE_MADDR_D2BIF_TDMA (BASE_MADDR_BIGRAM0_BIGRAM_D2BIF + 0x0000C000) // D2BIF_TDMA for 2g
+/*MT6297~*/ #define L1_BASE_MADDR_TX_DFE_D_DIE BASE_MADDR_DFESYS_TXDFE_D
+/*MT6297~*/ #define L1_BASE_MADDR_MDPAR_DBGON BASE_MADDR_MDPERI_MDPAR_DBGMON
+/*MT6297~*/ #define L1_BASE_MADDR_BFE BASE_MADDR_DFESYS_RXDFE_BB_BFE0
+/*MT6297~*/ #define L1_BASE_MADDR_BFE_1 BASE_MADDR_DFESYS_RXDFE_BB_BFE1
+/*MT6297~*/ #define L1_BASE_MADDR_TX_DFE_A_DIE (BASE_MADDR_TXSYS_DIGRF_TXDFE_BB + 0x0000F000) //Tx DFE A DIE
+/*MT6297~*/ #define L1_BASE_MADDR_TX_DFESYS_GLB_CON BASE_MADDR_DFESYS_GLB_CON_CONFIG1
+/*MT6297~*/ #define L1_BASE_TOP_DIGRF_EVT_GEN BASE_MADDR_DIFRF_OFF_TOP_DIGRF_EVT_GEN
+/*MT6297~*/ #define L1_BASE_MADDR_TXK_DFE_A_DIE BASE_MADDR_DIGRF_TX_TOP_TXK_WRAP_2 //TXK BASE RG
+/*MT6297~*/ #define L1_BASE_MADDR_L1D_TXK_CLK BASE_MADDR_DIGRF_TX_TOP_TXDFE_TOP_CTRL //TXK CLK
+
+ #else
+/*MT6293~*/ #define L1_BASE_MADDR_BFE BASE_MADDR_MD2GSYS_BFE
+ #if MD_DRV_IS_CHIP_MT6765 || MD_DRV_IS_CHIP_MT6295
+/*MT6765~*/ #define L1_BASE_MADDR_BFE_1 BASE_MADDR_MD2GSYS_BFE_2ND
+ #endif /* MD_DRV_IS_CHIP_MT6765 */
+ #endif
+/*MT6293~*/ #define L1_BASE_MADDR_MD2G_MEM_CONFG BASE_MADDR_MODEML1_AO_FESYS_P2P_TX
+ #if defined (L1D_TEST)
+/*MT6293~*/ #define L1_BASE_MADDR_IRDMA BASE_MADDR_MD2GSYS_IRDBG
+ #else
+/*MT6293~*/ #define L1_BASE_MADDR_IRDMA BASE_MADDR_FESYS_MD2G_IRDMA
+ #endif
+ #endif
+ /* IDMA short access is not supported in MT6293 */
+ #else
+/*TK6291~*/ #define IDMA_SHORT (L1_BASE_MADDR_SHORTMODE_IDMA)
+ #endif /* MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297 */
+/*TK6291~*/ #define IDMA_CM0 (L1_BASE_MADDR_CM_IDMA)
+/*TK6291~*/ #define IDMA_PM0 (L1_BASE_MADDR_PM_IDMA)
+/*TK6291~*/ #define IDMA_DM0 (L1_BASE_MADDR_DM_IDMA)
+#else
+/*else */ #error "Please check IDMA related settings"
+#endif
+#if defined(__MD93__) && (defined(L1_SIM) && (MD_DRV_IS_CHIP_MT6292))
+#define L1_BASE_MADDR_CM_IDMA (0xA7200000)
+#define L1_BASE_MADDR_PM_IDMA (0xA7300000)
+#define L1_BASE_MADDR_DM_IDMA (0xA7400000)
+#define L1_BASE_MADDR_TDMA_BASE (0xA7720000)
+#define L1_BASE_MADDR_MD2G_CONFG (0xA7700000)
+#define L1_BASE_MADDR_SHARE_D1 (0xA77A0000)
+#define L1_BASE_MADDR_PATCH (0xA77C0000)
+#define L1_BASE_MADDR_APC (0xA7730000)
+#define L1_BASE_MADDR_BFE (0xA77E0000)
+#if MD_DRV_IS_CHIP_MT6765 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+#define L1_BASE_MADDR_BFE_1 (0xA6F40000)
+#endif
+/*MT6293~*/ #define L1_BASE_MADDR_IRDMA BASE_MADDR_FESYS_MD2G_IRDMA
+#define L1_BASE_MADDR_MD2G_BSI_BASE (0xA7780000)
+#define L1_BASE_MADDR_MD2G_BPI_BASE (0xA7790000)
+#define L1_BASE_MADDR_MD2G_BPI_BAS (L1_BASE_MADDR_MD2G_BPI_BASE)
+#define L1_BASE_MADDR_MD2G_MEM_CONFG (0xA77F0000)
+#endif
+
+/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
+
+/*====================*\
+|* MCU PDN *|
+\*====================*/
+#if MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+/*TK6291~*/ #define TDMA_CLK_MUX ((APBADDR32)(L1_BASE_MADDR_MDL1_CONF+0x0080)) /* Qbit Timer Biasing Control Register */
+/*TK6291~*/ #define MDL1AO_PERI_CG_CON ((APBADDR32)(L1_BASE_MADDR_MDL1_CONF+0x0000)) /* MDL1AO_PERI_CG_CON_REG */
+/*TK6291~*/ #define MDL1AO_PERI_CG_SET ((APBADDR32)(L1_BASE_MADDR_MDL1_CONF+0x0004)) /* MDL1AO_PERI_CG_CON WRITE 1 SET REG */
+/*TK6291~*/ #define MDL1AO_PERI_CG_CLR ((APBADDR32)(L1_BASE_MADDR_MDL1_CONF+0x0008)) /* MDL1AO_PERI_CG_CON WRITE 1 CLEAR REG */
+/*TK6291~*/
+ #if MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+/*TK6291~*/ #define MODEM_PDNCON_TDMA_SLP 0x0010
+ #else
+/*TK6291~*/ #define MODEM_PDNCON_TDMA_SLP 0x0004
+ #endif /* MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297 */
+#else
+/*else */ #error "Please check MCU PDN related settings"
+#endif
+/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
+
+/*====================*\
+|* MD2G PDN *|
+\*====================*/
+#if MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+/*TK6291~*/ #define MD2GSYS_CG_CON0 ((APBADDR)(L1_BASE_MADDR_MD2G_CONFG+0x000)) /* Power Down Control 0 Register */
+/*TK6291~*/ #define MD2GSYS_CG_CON2 ((APBADDR)(L1_BASE_MADDR_MD2G_CONFG+0x008)) /* Power Down Control 2 Register */
+/*TK6291~*/ #define MD2GSYS_CG_CON4 ((APBADDR)(L1_BASE_MADDR_MD2G_CONFG+0x030)) /* Power Down Control 4 Register */
+/*TK6291~*/ #define MD2GSYS_CG_SET0 ((APBADDR)(L1_BASE_MADDR_MD2G_CONFG+0x010)) /* Power Down Disable 0 Register */
+/*TK6291~*/ #define MD2GSYS_CG_SET2 ((APBADDR)(L1_BASE_MADDR_MD2G_CONFG+0x018)) /* Power Down Disable 2 Register */
+/*TK6291~*/ #define MD2GSYS_CG_SET4 ((APBADDR)(L1_BASE_MADDR_MD2G_CONFG+0x034)) /* Power Down Disable 4 Register */
+/*TK6291~*/ #define MD2GSYS_CG_CLR0 ((APBADDR)(L1_BASE_MADDR_MD2G_CONFG+0x020)) /* Power Down Enable 0 Register */
+/*TK6291~*/ #define MD2GSYS_CG_CLR2 ((APBADDR)(L1_BASE_MADDR_MD2G_CONFG+0x028)) /* Power Down Enable 2 Register */
+/*TK6291~*/ #define MD2GSYS_CG_CLR4 ((APBADDR)(L1_BASE_MADDR_MD2G_CONFG+0x038)) /* Power Down Enable 4 Register */
+/*TK6291~*/ #define MD2G_PDN_CON0 MD2GSYS_CG_CON0 /* not used */
+/*TK6291~*/ #define MD2G_PDN_CON2 MD2GSYS_CG_CON2 /* not used */
+/*TK6291~*/ #define MD2G_PDN_CON4 MD2GSYS_CG_CON4 /* not used */
+/*TK6291~*/ #define MD2G_PDN_SET0 MD2GSYS_CG_SET0
+/*TK6291~*/ #define MD2G_PDN_SET2 MD2GSYS_CG_SET2
+/*TK6291~*/ #define MD2G_PDN_SET4 MD2GSYS_CG_SET4
+/*TK6291~*/ #define MD2G_PDN_CLR0 MD2GSYS_CG_CLR0
+/*TK6291~*/ #define MD2G_PDN_CLR2 MD2GSYS_CG_CLR2
+/*TK6291~*/ #define MD2G_PDN_CLR4 MD2GSYS_CG_CLR4
+/*TK6291~*/
+/*TK6291~*/ #define MD2G_PDNCON_TDMA_TMR 0x0001
+/*TK6291~*/ #define MD2G_PDNCON_BSI_G 0x0004
+/*TK6291~*/ #define MD2G_PDNCON_BPI_G 0x0008
+/*TK6291~*/ #define MD2G_PDNCON_APC 0x0020
+/*TK6291~*/ #define MD2G_PDNCON_BFE 0x0200
+#else
+/*else */ #error "Please check MD2G PDN related settings"
+#endif
+/* ======================================================================================================================= */
+
+/***************************************************************************************************************************
+ * Power Down Managerment *
+ ***************************************************************************************************************************/
+#if MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+/*TK6291~*/ #define HW_IRDBG_CLK_ON()
+/*TK6291~*/ #define HW_IRDBG_CLK_OFF()
+/*TK6291~*/ #define HW_IRDMA_CLK_ON() HW_WRITE(MD2G_PDN_CLR0,0x0040)
+/*TK6291~*/ #define HW_IRDMA_CLK_OFF() HW_WRITE(MD2G_PDN_SET0,0x0040)
+/*TK6291~*/ #define HW_DIVIDER_CLK_ON()
+/*TK6291~*/ #define HW_DIVIDER_CLK_OFF()
+/*TK6291~*/ #define HW_FCS_CLK_ON()
+/*TK6291~*/ #define HW_FCS_CLK_OFF()
+#else
+/*Else */ #define HW_IRDBG_CLK_ON()
+/*Else */ #define HW_IRDBG_CLK_OFF()
+/*Else */ #define HW_IRDMA_CLK_ON() HW_WRITE(MD2G_PDN_CLR0,0x0040)
+/*Else */ #define HW_IRDMA_CLK_OFF() HW_WRITE(MD2G_PDN_SET0,0x0040)
+/*Else */ #define HW_DIVIDER_CLK_ON() HW_WRITE(PDN_CLR2 ,0x0800)
+/*Else */ #define HW_DIVIDER_CLK_OFF() HW_WRITE(PDN_SET2 ,0x0800)
+/*Else */ #define HW_FCS_CLK_ON() HW_WRITE(PDN_CLR2 ,0x1000)
+/*Else */ #define HW_FCS_CLK_OFF() HW_WRITE(PDN_SET2 ,0x1000)
+#endif
+
+#if MD_DRV_IS_CHIP_MT6297
+ #if MD_DRV_IS_2G_BANK_B_ENABLE
+#define BIG_RAM_2G_CG_CLR ((APBADDR32)(BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON + 0x0078))
+#define BIG_RAM_2G_CG_SET ((APBADDR32)(BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON + 0x007C))
+#define BIG_RAM_2G_CG_CON ((APBADDR32)(BASE_NADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON + 0x0080))
+ #else
+#define BIG_RAM_2G_CG_CLR ((APBADDR32)(BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON + 0x0078))
+#define BIG_RAM_2G_CG_SET ((APBADDR32)(BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON + 0x007C))
+#define BIG_RAM_2G_CG_CON ((APBADDR32)(BASE_MADDR_BIGRAM0_BIGRAMSYS_GLOBAL_CON + 0x0080))
+ #endif
+#endif
+
+
+/* ======================================================================================================================= */
+
+/***************************************************************************************************************************
+ * Global constant and data definition for other modules *
+ ***************************************************************************************************************************/
+
+/* PDN mask and sleep mode settings */
+
+#if MD_DRV_IS_CHIP_MT6297
+/*TK6293~*/ #define MD2G_MASK1 0x0002 // MD2G(CLR0): GCC
+/*TK6293~*/ #define MD2G_MASK2 0x0000 // MD2G(CLR2): BFE, APC, TDMA_TMR
+/*TK6293~*/ #define MODEMSYS_MASK 0x0010 // ModemSYS(CLR): TDMA_SLP
+/*TK6293~*/ #define MODEM_SLPON 0x0010 // Clock on module in sleep mode: TDMA_SLP
+/*TK6293~*/ #define MODEM_SLPOFF 0x0000 // Clock off module in sleep mode: none
+/*TK6293~*/ #define MD2G_SLPON 0x0000 // Clock on module in sleep mode: TDMA_TMR
+/*TK6293~*/ #define MD2G_SLPOFF 0x0002 // Clock off module in sleep mode: BFE,APC,GCC
+#elif MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295
+/*TK6293~*/ #define MD2G_MASK1 0x0002 // MD2G(CLR0): GCC
+/*TK6293~*/ #define MD2G_MASK2 0x0221 // MD2G(CLR2): BFE, APC, TDMA_TMR
+/*TK6293~*/ #define MODEMSYS_MASK 0x0010 // ModemSYS(CLR): TDMA_SLP
+/*TK6293~*/ #define MODEM_SLPON 0x0010 // Clock on module in sleep mode: TDMA_SLP
+/*TK6293~*/ #define MODEM_SLPOFF 0x0000 // Clock off module in sleep mode: none
+/*TK6293~*/ #define MD2G_SLPON 0x0001 // Clock on module in sleep mode: TDMA_TMR
+/*TK6293~*/ #define MD2G_SLPOFF 0x0222 // Clock off module in sleep mode: BFE,APC,GCC
+
+#elif MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292
+/*TK6291~*/ #define MODEMSYS_MASK 0x0004 // ModemSYS(CLR): TDMA_SLP
+/*TK6291~*/ #define MODEM_SLPON 0x0004 // Clock on module in sleep mode: TDMA_SLP
+/*TK6291~*/ #define MODEM_SLPOFF 0x0000 // Clock off module in sleep mode: none
+/*TK6291~*/
+/*TK6291~*/ #define MD2G_MASK1 0x0002 // MD2G(CLR0): GCC
+/*TK6291~*/ #define MD2G_MASK2 0x022D // MD2G(CLR2): BFE, APC, BPI_G, BSI_G, TDMA_TMR
+ #if IS_TK6291_HW_BUG_SW_WORKAROUND_SUPPORT
+/*TK6291~*/ #define MD2G_SLPON 0x000D // Clock on module in sleep mode: TDMA_TMR,BPI_G,BSI_G
+/*TK6291~*/ #define MD2G_SLPOFF 0x0222 // Clock off module in sleep mode: BFE,APC,GCC
+ #else
+/*TK6291~*/ #define MD2G_SLPON 0x0001 // Clock on module in sleep mode: TDMA_TMR
+/*TK6291~*/ #define MD2G_SLPOFF 0x022E // Clock off module in sleep mode: BFE,APC,BPI_G,BSI_G,GCC
+ #endif
+#else
+/*else */ #error "Please check PDN mask and sleep mode settings"
+#endif
+/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
+
+#if MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+ #if (defined L1D_TEST)
+/*TK6291~*/ #define PWR_ON_SETTLE 4
+ #else
+/*TK6291~*/ #define PWR_ON_SETTLE 2
+ #endif
+#endif
+/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
+
+/* TDMA timing */
+#if MD_DRV_IS_AST_B2S_SUPPORT
+#define MD_DRV_TQ_AFC_READY 245
+#else
+#define MD_DRV_TQ_AFC_READY 256
+#endif
+
+#if MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+#define MD_DRV_TQ_MAXIMUM 16383 /*16383: 0x3FFF*/
+#endif
+#define MD_DRV_TQ_SLOT_LEN (156*4)
+#define MD_DRV_TQ_WRAP_COUNT 5000
+#define MD_DRV_TQ_VALIDATE_COUNT 4939
+#define MD_DRV_TQ_CTIRQ1 (MD_DRV_TQ_AFC_READY+625*5)
+/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
+
+#define MD_DRV_EVTENA0_SLOW_EN_SEL (0)
+/*=========================================================================================================================*/
+
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1_kal.h b/mcu/interface/l1/gl1/external/l1_kal.h
new file mode 100644
index 0000000..591947b
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1_kal.h
@@ -0,0 +1,1124 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1_kal.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Layer 1 system service adaption interface
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _L1_KAL_H
+#define _L1_KAL_H
+
+//#include "stack_ltlcom.h"
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h" //MSBB change #include "stack_config.h"
+#include "kal_hrt_api.h"
+#include "md_sap.h"
+#include "l1_gemini_def.h"
+#include "global_def.h"
+#include "mph_types.h"
+
+#if GL1C_PROFILE_ENABLE
+//#include "l1_core_private.h"
+#include "us_timer.h"
+#endif
+
+/* Maruco 20090108, for fix build error of L1 simulation for MONZA2G_GEMINI
+ * For target load, codegen and build should not include stdlib.h
+ * For MODIS/L1 simulation, codegen should not include stdlib.h
+ * but build should include it (GEN_FOR_PC is enabled when codegen) */
+#ifndef GEN_FOR_PC
+#ifndef __MTK_TARGET__
+#include <stdlib.h>
+#endif /* end of __MTK_TARGET__ */
+#endif /* end of GEN_FOR_PC */
+
+#ifdef DUMMY_PROTOCOL
+#define MOD_MPAL_FDD MOD_DUMMYMPAL
+#endif
+
+#define ENABLE_L1_CC_SERVICE
+
+// Remove this because the definitions are put in kal_public_defs.h
+//MT6280 GCC Porting : build in function
+//#if defined(__MTK_TARGET__)
+//#if defined (__ARMCC_VERSION)
+//#define INLINE __inline
+//#elif defined (__GNUC__)
+//#define INLINE extern inline
+//#endif /* ARMCC , GNUC */
+//#else /* __MTK_TARGET__ */
+//#define INLINE __inline
+//#endif /* __MTK_TARGET__ */
+
+/*******************************************************************************
+ * Destination queue id definition
+ *******************************************************************************/
+#ifdef L1_SIM
+#ifdef __UMTS_FDD_MODE__
+#define MOD_MPAL MOD_MPAL_FDD
+#if defined(__GL1_GEMINI__)
+#define MOD_MPAL_2 MOD_MPAL_FDD_2
+#if (GL1_GEMINI_NUM >= 3)
+#define MOD_MPAL_3 MOD_MPAL_FDD_3
+#if (GL1_GEMINI_NUM >= 4)
+#define MOD_MPAL_4 MOD_MPAL_FDD_4
+#endif /* end of (GL1_GEMINI_NUM >= 4) */
+#endif /* end of (GL1_GEMINI_NUM >= 3) */
+#endif /* endi of __GL1_GEMINI__ */
+#else /*__UMTS_FDD_MODE__*/
+#define MOD_MPAL MOD_MPAL_TDD
+#if defined(__GL1_GEMINI__)
+#define MOD_MPAL_2 MOD_MPAL_TDD_2
+#if (GL1_GEMINI_NUM >= 3)
+#define MOD_MPAL_3 MOD_MPAL_TDD_3
+#if (GL1_GEMINI_NUM >= 4)
+#define MOD_MPAL_4 MOD_MPAL_TDD_4
+#endif /* end of (GL1_GEMINI_NUM >= 4) */
+#endif /* end of (GL1_GEMINI_NUM >= 3) */
+#endif /* endi of __GL1_GEMINI__ */
+#endif /*__UMTS_FDD_MODE__*/
+#endif /*L1_SIM*/
+
+#if 0 /* elly */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+#define GS_QUEUE_LAYER_1 MOD_L1
+#define GS_QUEUE_LAYER_2 MOD_MPAL_FDD /* this is only used for UT */
+#define GS_QUEUE_RR MOD_MPAL_FDD
+#define GS_QUEUE_CB MOD_MPAL_FDD /* should be supported in another file */
+#define GS_QUEUE_RLCMAC MOD_MPAL_FDD
+#define GS_QUEUE_L1HISR MOD_L1HISR
+#define GS_MAX_QUEUE END_OF_MOD_ID
+#if defined(__L1_GPS_REF_TIME_SUPPORT__) || defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__)
+#define GS_QUEUE_GPS MOD_GPS /* Shihyao, add it to support GPS time sync procedure*/
+#endif
+
+#ifdef L1A_SIM_WO_TL1
+#define GS_QUEUE_TL1 MOD_TL1
+#endif /* L1A_SIM_WO_TL1 */
+
+#if defined(__GL1_GEMINI__)
+#define GS_QUEUE_LAYER_1_2 MOD_L1_2
+#define GS_QUEUE_LAYER_2_2 MOD_MPAL_FDD_2
+#define GS_QUEUE_RR_2 MOD_MPAL_FDD_2
+#define GS_QUEUE_CB_2 MOD_MPAL_FDD_2 /* should be supported in another file */
+#define GS_QUEUE_RLCMAC_2 MOD_MPAL_FDD_2
+#define GS_QUEUE_RSVAS MOD_RSVAS /* Shihyao 20100315, add it becuase suspend procedure is handled by RSVAS instead of MPAL*/
+#define GS_MAX_QUEUE_2 END_OF_MOD_ID
+
+#if (GL1_GEMINI_NUM >= 3)
+#define GS_QUEUE_LAYER_1_3 MOD_L1_3
+#define GS_QUEUE_LAYER_2_3 MOD_MPAL_FDD_3
+#define GS_QUEUE_RR_3 MOD_MPAL_FDD_3
+#define GS_QUEUE_CB_3 MOD_MPAL_FDD_3 /* should be supported in another file */
+#define GS_QUEUE_RLCMAC_3 MOD_MPAL_FDD_3
+#define GS_MAX_QUEUE_3 END_OF_MOD_ID
+
+#if (GL1_GEMINI_NUM >= 4)
+#define GS_QUEUE_LAYER_1_4 MOD_L1_4
+#define GS_QUEUE_LAYER_2_4 MOD_MPAL_FDD_4
+#define GS_QUEUE_RR_4 MOD_MPAL_FDD_4
+#define GS_QUEUE_CB_4 MOD_MPAL_FDD_4 /* should be supported in another file */
+#define GS_QUEUE_RLCMAC_4 MOD_MPAL_FDD_4
+#define GS_MAX_QUEUE_4 END_OF_MOD_ID
+#endif /* end of (GL1_GEMINI_NUM >= 4) */
+
+#endif /* end of (GL1_GEMINI_NUM >= 3) */
+
+#else
+#ifdef L1A_SIM
+#define GS_QUEUE_RSVAS MOD_RSVAS /* Shihyao 20100315, add it becuase suspend procedure is handled by RSVAS instead of MPAL*/
+#endif /* end of L1A_SIM */
+#endif
+#endif
+
+/*******************************************************************************
+ * L1 system service related MACRO definition
+ *******************************************************************************/
+ #if defined( __MTK_TARGET__) || defined(__UE_SIMULATOR__) || defined(__UL1_ON_MNT__) || defined(UNIT_TEST)
+
+/*William 20120613 for ilm global passing */
+#if defined( __MTK_TARGET__)
+extern ilm_struct l1_ilm_pool[];
+#endif
+
+/*******************************************************************************
+ * Destination module id definition
+ *******************************************************************************/
+
+#if ( defined( __MTK_TARGET__) || defined(__UE_SIMULATOR__) ) && (!defined(__L1_STANDALONE__))
+/* for U4G, send msg to GISE rather than MPAL */
+/* Initialize the module to _FDD. While sending the message, GL1 will query_real_module to get the actual
+ destination _FDD/_TDD */
+#define MOD_MPH_RR MOD_GISE_FDD
+#define MOD_MPH_L2 MOD_GISE_FDD
+#define MOD_MPH_CB MOD_GISE_FDD
+#define MOD_MPH_MAC MOD_GISE_FDD
+#define MOD_MPH_L1 MOD_L1
+
+#if defined(__GL1_GEMINI__)
+#define MOD_MPH_L1_2 MOD_L1_2
+#define MOD_MPH_RSVAS MOD_RSVAS /* Shihyao 20100315, add it becuase suspend procedure is handled by RSVAS instead of MPAL*/
+
+#if (GL1_GEMINI_NUM >= 3)
+#define MOD_MPH_L1_3 MOD_L1_3
+
+#if (GL1_GEMINI_NUM >= 4)
+#define MOD_MPH_L1_4 MOD_L1_4
+#endif /* end of (GL1_GEMINI_NUM >= 4) */
+#endif /* end of (GL1_GEMINI_NUM >= 3) */
+#endif /* end of __GL1_GEMINI__ */
+
+#else
+/* This is only used in xL1SIM */
+#define MOD_MPH_RR MOD_MPAL_FDD
+#define MOD_MPH_L2 MOD_MPAL_FDD
+#define MOD_MPH_CB MOD_MPAL_FDD
+#define MOD_MPH_MAC MOD_MPAL_FDD
+#define MOD_MPH_L1 MOD_L1
+
+#if defined(__GL1_GEMINI__)
+#define MOD_MPH_L1_2 MOD_L1_2
+#define MOD_MPH_RSVAS MOD_RSVAS /* Shihyao 20100315, add it becuase suspend procedure is handled by RSVAS instead of MPAL*/
+
+#if (GL1_GEMINI_NUM >= 3)
+#define MOD_MPH_L1_3 MOD_L1_3
+
+#if (GL1_GEMINI_NUM >= 4)
+#define MOD_MPH_L1_4 MOD_L1_4
+#endif /* end of (GL1_GEMINI_NUM >= 4) */
+#endif /* end of (GL1_GEMINI_NUM >= 3) */
+#endif /* end of __GL1_GEMINI__ */
+
+#endif /*__MTK_TARGET__ || __UE_SIMULATOR__ */
+
+#ifdef __MTK_TARGET__
+#ifndef __L1_STANDALONE__
+/* Maruco20081223, add for using RF tool in engineering mode
+ * L4C sends 4 new primitives(in em_sap.h) to L1A,
+ * and L1A call L1C's function(in Rftool_types.h) to set parameters
+ * then L1C calls L1A's function to return primitive to MOD_UEM(module of L4C),
+ * so L1A needs to define module(MOD_UEM) and EM(engineering mode)_SAP */
+#define MOD_MPH_UEM MOD_UEM
+#endif /* end of __L1_STANDALONE__*/
+#endif /* end of __MTK_TARGET__ */
+#if defined(__L1_GPS_REF_TIME_SUPPORT__) || defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__)
+/* Shihyao, add it to support GPS time sync procedure*/
+#define MOD_MPH_GPS MOD_GPS
+#endif
+
+
+
+/* elly, already defined in ul1_kal.h */
+/* Joy 070401 for MONZA keep the definition*/
+//#ifndef __MTK_UL1_FDD__
+#define MOD_MPH_UL1 MOD_UL1
+//#define MOD_MPH_UL1HISR MOD_UL1HISR
+//#endif
+
+
+/* After LISR2HISR, users of MOD_MPH_L1HISR: MOD_L1, MOD_LAPDM, MOD_FT */
+
+#define MOD_MPH_L1HISR MOD_L1HISR
+
+#define MOD_MPH_TL1 MOD_TL1
+
+#define MOD_MPH_LL1 MOD_MLL1
+/*******************************************************************************
+ * Sap id definition
+ *******************************************************************************/
+#define MPH_L1_L1_SAP L1_L1_SAP
+#define MPH_L1_RR_SAP L1_MPAL_SAP
+#define MPH_RR_L1_SAP MPAL_L1_SAP
+#define MPH_L1_L2_SAP L1_MPAL_SAP
+#define MPH_L2_L1_SAP MPAL_L1_SAP
+#define MPH_L1_CB_SAP L1_MPAL_SAP
+#define MPH_CB_L1_SAP MPAL_L1_SAP
+#define MPH_L1_MAC_SAP L1_MPAL_SAP
+#define MPH_MAC_L1_SAP MPAL_L1_SAP
+#define MPH_UL1_L1_SAP UL1_L1_SAP
+#define MPH_TL1_L1_SAP TL1_LL1_SAP
+
+#define MPH_L1_LL1_SAP L1_MLL1_SAP
+
+#if defined(__GL1_GEMINI__)
+#define MPH_L1_RSVAS_SAP RSVAS_SAP /* Shihyao 20100315, add it becuase suspend procedure is handled by RSVAS instead of MPAL*/
+#endif
+
+#if defined(__L1_GPS_REF_TIME_SUPPORT__) || defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__)
+/* Shihyao, add it to support GPS time sync procedure*/
+#define MPH_L1_GPS_SAP GPS_L1_SAP
+#endif
+
+#ifdef __MTK_TARGET__
+#ifndef __L1_STANDALONE__
+/* Maruco20081223, add for using RF tool in engineering mode
+ * L4C sends 4 new primitives(in em_sap.h) to L1A,
+ * and L1A call L1C's function(in Rftool_types.h) to set parameters
+ * then L1C calls L1A's function to return primitive to MOD_UEM(module of L4C),
+ * so L1A needs to define module(MOD_UEM) and EM(engineering mode)_SAP */
+#define MPH_L1_UEM_SAP L1_EM_SAP
+#endif /* end of __L1_STANDALONE__*/
+#endif /* end of __MTK_TARGET__ */
+
+
+inline void *L1_ALLOC_BUF(kal_uint32 byte_size) {
+ void *buf_ptr = get_ctrl_buffer(byte_size);
+ kal_mem_set(buf_ptr, 0, byte_size);
+ return buf_ptr;
+}
+
+#define L1_FREE_BUF(buf) free_ctrl_buffer(buf)
+
+#define L1TST_FREE_BUF(buf) \
+ free_ctrl_buffer(buf); \
+ buf=NULL;
+
+#define L1_OPEN_MESSAGE_QUEUE(queue) (KAL_SUCCESS)
+
+/*William 20120613 for ilm global passing */
+typedef enum
+{
+ ilm_MOD_MPH_L1
+#if defined(__GL1_GEMINI__)
+ ,ilm_MOD_MPH_L1_2
+#if (GL1_GEMINI_NUM >= 3)
+ ,ilm_MOD_MPH_L1_3
+#if (GL1_GEMINI_NUM >= 4)
+ ,ilm_MOD_MPH_L1_4
+#endif
+#endif
+#endif
+ ,ilm_MOD_MPH_L1HISR
+ ,ilm_MOD_MPH_UL1
+ ,ilm_MOD_MPH_TL1
+ ,ilm_POOL_SIZE
+} ENUM_ILM_ID;
+
+inline void L1_SEND_MSG(module_type src_mod, module_type dest_mod, sap_type sap_id, ilm_struct *ilm_ptr) {
+ if( ilm_ptr->local_para_ptr == NULL )
+ msg_send4( src_mod, dest_mod, sap_id, ilm_ptr->msg_id);
+ else
+ msg_send5( src_mod, dest_mod, sap_id, ilm_ptr->msg_id, ilm_ptr->local_para_ptr);
+}
+
+inline void L1_SEND_MSG_TO_NVRAM(module_type src_mod, module_type dest_mod, sap_type sap_id, ilm_struct *ilm_ptr) {
+ msg_send6( src_mod, dest_mod, sap_id, ilm_ptr->msg_id, ilm_ptr->local_para_ptr, ilm_ptr->peer_buff_ptr );
+}
+
+inline void LL1_SEND_MSG(module_type src_mod, module_type dest_mod, sap_type sap_id, ilm_struct *ilm_ptr) {
+ if( ilm_ptr->local_para_ptr == NULL )
+ msg_send4( src_mod, dest_mod, sap_id, ilm_ptr->msg_id);
+ else
+ msg_send5( src_mod, dest_mod, sap_id, ilm_ptr->msg_id, ilm_ptr->local_para_ptr);
+}
+
+#if defined(ENABLE_L1_CC_SERVICE) && defined(__MTK_TARGET__)
+
+#define L1_SEND_CC_MSG(src_mod, dest_mod, sap, ilm_ptr) \
+{ \
+ msg_send6_cc((src_mod), (dest_mod), (sap), (ilm_ptr->msg_id), (local_para_struct*)(ilm_ptr->local_para_ptr), (peer_buff_struct *) (ilm_ptr->peer_buff_ptr)); \
+}
+
+#define L1_FREE_CC_MSG(ilm_ptr) { destroy_shared_ilm_r(ilm_ptr); }
+
+inline ilm_struct* L1_ALLOC_CC_MSG(module_type ilm_id, kal_uint16 size, kal_uint32 direction)
+{
+ ilm_struct *ilm_ptr;
+ ilm_ptr = &l1_ilm_pool[ilm_id];
+ if (size)
+ ilm_ptr->local_para_ptr = construct_cc_non_cached_local_para(size, direction);
+ else
+ ilm_ptr->local_para_ptr = NULL;
+ return ilm_ptr;
+}
+
+#endif //ENABLE_L1_CC_SERVICE && MTK_TARGET
+
+
+#define L1_RECV_MSG(ilm_ptr) \
+ msg_receive_extq( ilm_ptr )
+#if defined(__GL1_GEMINI__)
+#define L1_RECV_MSG_2(ilm_ptr) \
+ msg_receive_extq( ilm_ptr )
+#if (GL1_GEMINI_NUM >= 3)
+#define L1_RECV_MSG_3(ilm_ptr) \
+ msg_receive_extq( ilm_ptr )
+#if (GL1_GEMINI_NUM >= 4)
+#define L1_RECV_MSG_4(ilm_ptr) \
+ msg_receive_extq( ilm_ptr )
+#endif /* end of (GL1_GEMINI_NUM >= 4) */
+#endif /* end of (GL1_GEMINI_NUM >= 3) */
+#endif
+
+#define L1_FREE_MSG(ilm_ptr) { destroy_ilm(ilm_ptr); }
+
+#if defined( __MTK_TARGET__)
+
+/*William 20120613 for ilm global passing */
+#define L1_ALLOC_MSG(mod_id, size) _L1_ALLOC_MSG(ilm_##mod_id, size)
+
+//MT6280 GCC Porting
+inline ilm_struct* _L1_ALLOC_MSG(module_type ilm_id, kal_uint16 size)
+{
+ ilm_struct *ilm_ptr;
+ ilm_ptr = &l1_ilm_pool[ilm_id];
+ if (size)
+ ilm_ptr->local_para_ptr = construct_local_para(size, TD_RESET);
+ else
+ ilm_ptr->local_para_ptr = NULL;
+ return ilm_ptr;
+}
+
+#endif
+
+
+#else /* for simulation */
+
+extern ilm_struct simu_ilm_pool[];
+
+typedef unsigned long dword; /* 4 byte variable */
+typedef unsigned short word; /* 2 byte variable */
+typedef signed short sword; /* 2 byte variable */
+typedef unsigned char boolean; /* 1 byte variable */
+
+/*******************************************************************************
+ * Destination module id definition
+ *******************************************************************************/
+#define MOD_MPH_RR GS_QUEUE_RR
+#define MOD_MPH_L2 GS_QUEUE_LAYER_2
+#define MOD_MPH_CB GS_QUEUE_CB
+#define MOD_MPH_MAC GS_QUEUE_RLCMAC
+#define MOD_MPH_L1 GS_QUEUE_LAYER_1
+#define MOD_MPH_UL1 MOD_UL1
+
+#define MOD_MPH_LL1 MOD_MLL1
+
+/*Maruco20071024, define module of Slave*/
+#if defined(__GL1_GEMINI__)
+#define MOD_MPH_RR_2 GS_QUEUE_RR_2
+#define MOD_MPH_L2_2 GS_QUEUE_LAYER_2_2
+#define MOD_MPH_CB_2 GS_QUEUE_CB_2
+#define MOD_MPH_MAC_2 GS_QUEUE_RLCMAC_2
+#define MOD_MPH_L1_2 GS_QUEUE_LAYER_1_2
+
+#if (GL1_GEMINI_NUM >= 3)
+#define MOD_MPH_RR_3 GS_QUEUE_RR_3
+#define MOD_MPH_L2_3 GS_QUEUE_LAYER_2_3
+#define MOD_MPH_CB_3 GS_QUEUE_CB_3
+#define MOD_MPH_MAC_3 GS_QUEUE_RLCMAC_3
+#define MOD_MPH_L1_3 GS_QUEUE_LAYER_1_3
+
+#if (GL1_GEMINI_NUM >= 4)
+#define MOD_MPH_RR_4 GS_QUEUE_RR_4
+#define MOD_MPH_L2_4 GS_QUEUE_LAYER_2_4
+#define MOD_MPH_CB_4 GS_QUEUE_CB_4
+#define MOD_MPH_MAC_4 GS_QUEUE_RLCMAC_4
+#define MOD_MPH_L1_4 GS_QUEUE_LAYER_1_4
+#endif /* end of (GL1_GEMINI_NUM >= 4) */
+
+#endif /* end of (GL1_GEMINI_NUM >= 3) */
+
+#endif
+
+#if defined(L1A_SIM) || defined(__GL1_GEMINI__)
+#define MOD_MPH_RSVAS MOD_RSVAS /* Shihyao 20100315, add it becuase suspend procedure is handled by RSVAS instead of MPAL*/
+#endif
+
+#if defined(__L1_GPS_REF_TIME_SUPPORT__) || defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__)
+/* Shihyao, add it to support GPS time sync procedure*/
+#define MOD_MPH_GPS GS_QUEUE_GPS
+#endif
+
+/* elly, already defined in ul1_kal.h */
+//#define MOD_MPH_UL1 GS_QUEUE_UL1
+#if 0 /* elly */
+/* under construction !*/
+#else
+#define MOD_MPH_L1HISR GS_QUEUE_L1HISR
+#endif
+
+/*******************************************************************************
+ * Sap id definition
+ *******************************************************************************/
+#define MPH_L1_L1_SAP L1_L1_SAP
+#define MPH_L1_RR_SAP L1_MPAL_SAP
+#define MPH_RR_L1_SAP MPAL_L1_SAP
+#define MPH_L1_L2_SAP L1_MPAL_SAP
+#define MPH_L2_L1_SAP MPAL_L1_SAP
+#define MPH_L1_CB_SAP L1_MPAL_SAP
+#define MPH_CB_L1_SAP MPAL_L1_SAP
+#define MPH_L1_MAC_SAP L1_MPAL_SAP
+#define MPH_MAC_L1_SAP MPAL_L1_SAP
+#define MPH_UL1_L1_SAP UL1_L1_SAP
+#define MPH_TL1_L1_SAP TL1_MLL1_SAP
+#define MPH_L1_TL1_SAP TL1_MLL1_SAP //for TD half simulation
+
+#define MPH_L1_LL1_SAP L1_MLL1_SAP
+
+
+#if defined(L1A_SIM) || defined(__GL1_GEMINI__)
+#define MPH_L1_RSVAS_SAP RSVAS_SAP /* Shihyao 20100315, add it becuase suspend procedure is handled by RSVAS instead of MPAL*/
+#endif
+
+#if defined(__L1_GPS_REF_TIME_SUPPORT__) || defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__)
+/* Shihyao, add it to support GPS time sync procedure*/
+#define MPH_L1_GPS_SAP GPS_L1_SAP
+#endif
+
+extern kal_status gs_open_message_queue(module_type);
+extern void script_send_message(module_type, void *, kal_bool);
+extern void script_send_message_byMod(const int dest_mod, void *msg, kal_bool wait);
+extern kal_status gs_send_message(module_type, module_type, void *, kal_bool);
+extern kal_status gs_read_message(module_type, void *, kal_uint16, kal_bool);
+
+
+inline void *L1_ALLOC_BUF(kal_uint32 byte_size) {
+ void *buf_ptr = malloc(byte_size);
+ memset(buf_ptr, 0, byte_size);
+ return buf_ptr;
+}
+
+
+#define L1_FREE_BUF(buf) free(buf)
+
+#define L1TST_FREE_BUF(buf) \
+ free(buf); \
+ buf=NULL;
+
+#define L1_OPEN_MESSAGE_QUEUE(queue) \
+ gs_open_message_queue((queue))
+
+#ifndef __UE_SIMULATOR__
+#if 1 //(defined L1A_SIM)
+#define L1_SEND_MSG(src_mod, dest_mod, sap, ilm_ptr) \
+ ilm_ptr->src_mod_id = src_mod; \
+ ilm_ptr->dest_mod_id = dest_mod; \
+ ilm_ptr->sap_id = sap; \
+ gs_send_message((module_type)src_mod, (module_type)dest_mod, (void*)ilm_ptr, KAL_TRUE);
+
+#define LL1_SEND_MSG L1_SEND_MSG /* elly */
+
+#else /* L1A_SIM */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* L1A_SIM */
+
+#if defined(ENABLE_L1_CC_SERVICE)
+
+static INLINE void L1_SEND_CC_MSG(module_type src_mod, module_type dest_mod, sap_type sap_id, ilm_struct *ilm_ptr)
+{
+ L1_SEND_MSG( src_mod, dest_mod, sap_id,ilm_ptr);
+}
+
+#endif //ENABLE_L1_CC_SERVICE
+
+#define L1_RECV_MSG(ilm_ptr) \
+ gs_read_message(GS_QUEUE_LAYER_1, ilm_ptr, sizeof(ilm_struct), true)
+#if defined(__GL1_GEMINI__)
+#define L1_RECV_MSG_2(ilm_ptr) \
+ gs_read_message(GS_QUEUE_LAYER_1_2, ilm_ptr, sizeof(ilm_struct), true)
+#if (GL1_GEMINI_NUM >= 3)
+#define L1_RECV_MSG_3(ilm_ptr) \
+ gs_read_message(GS_QUEUE_LAYER_1_3, ilm_ptr, sizeof(ilm_struct), true)
+#if (GL1_GEMINI_NUM >= 4)
+#define L1_RECV_MSG_4(ilm_ptr) \
+ gs_read_message(GS_QUEUE_LAYER_1_4, ilm_ptr, sizeof(ilm_struct), true)
+#endif /* end of (GL1_GEMINI_NUM >= 4) */
+#endif /* end of (GL1_GEMINI_NUM >= 3) */
+#endif
+
+#endif //__UE_SIMULATOR__
+
+#define L1_FREE_MSG(ilm_ptr) if ((ilm_ptr)->src_mod_id != MOD_TIMER) free(ilm_ptr.local_para_ptr[0])
+
+//MT6280 GCC Porting
+inline ilm_struct* L1_ALLOC_MSG(module_type mod_id, kal_uint16 size)
+{
+ ilm_struct *ilm_ptr;
+
+ ilm_ptr = &simu_ilm_pool[mod_id];
+
+ if (size == 0)
+ size = 4;
+
+ {
+ ilm_ptr->local_para_ptr = (local_para_struct *) malloc(size);
+ memset(ilm_ptr->local_para_ptr, 0, size);
+ ilm_ptr->local_para_ptr->msg_len = size;
+ ilm_ptr->local_para_ptr->ref_count = 1;
+ }
+ return ilm_ptr;
+}
+
+#if defined(ENABLE_L1_CC_SERVICE)
+
+inline ilm_struct* L1_ALLOC_CC_MSG(module_type mod_id, kal_uint16 size, kal_uint32 direction)
+{
+ return L1_ALLOC_MSG(mod_id,size);
+}
+
+
+#endif //ENABLE_L1_CC_SERVICE
+
+#endif /* __MTK_TARGET__ */
+
+
+/***************************** MT6292 begin *********************************/
+/*
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void kal_hrt_RestoreIRQMask(kal_uint32 irq);
+extern kal_uint32 kal_hrt_SaveAndSetIRQMask(void);
+extern void kal_hrt_revoke_dummy_lisr(kal_itc_lock_id);
+extern kal_status kal_hrt_trigger_dummy_lisr(kal_itc_lock_id);
+*/
+#if 1 //IS_GL1C_TO_NORMAL_DOMAIN
+/* after move L1C to normal domain, we use spinlock for l1t/l1i */
+extern kal_spinlockid gl1c_spinlock;
+
+#define L1_INTERRUPT_HANDLING_PREREQUISITE \
+kal_uint32 saveMask; \
+kal_status itc_status;
+
+#define GL1_HWITC_HANDLING_PREREQUISITE //L1_INTERRUPT_HANDLING_PREREQUISITE
+
+#define L1_DISABLE_INTERRUPT
+
+#define L1_ENABLE_INTERRUPT
+
+#define L1_ENTER_LISR_PREREQUISITE
+
+#define L1_LEAVE_LISR_PREREQUISITE
+
+#define FRC_WRAP_CHECK(f) ( (f)<0? (f)+USCNT_WRAP : (f) )
+
+#if GL1C_PROFILE_ENABLE
+extern kal_uint32 gl1c_spinlock_profile[10];
+extern kal_int64 spinlock_begin_frc;
+extern kal_int64 spinlock_end_frc;
+
+#define GL1C_SPINLOCK_PROFILE \
+do{ \
+ kal_int64 duration; \
+ \
+ duration = FRC_WRAP_CHECK(spinlock_end_frc - spinlock_begin_frc); \
+ duration = (duration>999)? 999:duration; /*clip*/ \
+ \
+ gl1c_spinlock_profile[duration/100]++; \
+}while(0);
+
+#define GL1C_TAKE_SPINLOCK \
+do{ \
+ kal_take_spinlock(gl1c_spinlock, KAL_INFINITE_WAIT); \
+ spinlock_begin_frc = ust_get_current_time(); \
+}while(0);
+
+#define GL1C_GIVE_SPINLOCK \
+do{ \
+ spinlock_end_frc = ust_get_current_time(); \
+ kal_give_spinlock(gl1c_spinlock); \
+ GL1C_SPINLOCK_PROFILE; \
+}while(0);
+
+#else
+#define GL1C_TAKE_SPINLOCK \
+do{ \
+ kal_take_spinlock(gl1c_spinlock, KAL_INFINITE_WAIT); \
+}while(0);
+
+#define GL1C_GIVE_SPINLOCK \
+do{ \
+ kal_give_spinlock(gl1c_spinlock); \
+}while(0);
+#endif
+
+#define GL1_TAKE_HWITC \
+do{ \
+ kal_hrt_take_itc_lock(KAL_ITC_23G_L1_LOCK, KAL_INFINITE_WAIT); \
+}while(0);
+
+#define GL1_GIVE_HWITC \
+do{ \
+ kal_hrt_give_itc_lock(KAL_ITC_23G_L1_LOCK); \
+}while(0);
+
+
+
+#else /* IS_GL1C_TO_NORMAL_DOMAIN */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* end of IS_GL1C_TO_NORMAL_DOMAIN */
+/***************************** MT6292 end *********************************/
+
+
+#endif /* _L1_KAL_H */
+
+
diff --git a/mcu/interface/l1/gl1/external/l1_nvram_utas_ras_params.h b/mcu/interface/l1/gl1/external/l1_nvram_utas_ras_params.h
new file mode 100644
index 0000000..6910cb4
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1_nvram_utas_ras_params.h
@@ -0,0 +1,409 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1_nvram_utas_ras_params.h
+ *
+ * Project:
+ * --------
+ * MT6295
+ *
+ * Description:
+ * ------------
+ * Gen95 UTAS RAS nvram parameters required for L1C
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ *
+ *
+ *******************************************************************************/
+
+#ifndef _L1_NVRAM_UTAS_RAS_PARAMS_H_
+#define _L1_NVRAM_UTAS_RAS_PARAMS_H_
+/* ------------------------------------------------------------------------- */
+ /* Threshold parameters needed for GL1C UTAS */
+ /* utas_1RX_PublicParams for Idle */
+ /* Timeout thresholds for Idle*/
+#define PERIOD_IDLE 816
+#define PERIOD_DEDICATED 208
+#define L1_1RX_TIMEOUT_HIGH_QUAL_THD_I -60
+#define L1_1RX_TIMEOUT_LOW_QUAL_THD_I -108
+#define L1_1RX_TIMEOUT_LONG_COUNT_THD_I (102*240)
+#define L1_1RX_TIMEOUT_SHORT_COUNT_THD_I (102*80)
+ /* adaptive threshold control for Idle*/
+#define L1_1RX_tSTEP_I (102*8)
+#define L1_1RX_tBOUND_I (102*160)
+
+ /* Event trigger parameters for Idle*/
+#define L1_1RX_N_CB_I (102*5)
+#define L1_1RX_EVENT_LOW_QUAL_THD_I -108
+#define L1_1RX_EVENT_RXLEV_CB_THD_I -4
+#define L1_1RX_EVENT_HR_ABS_THD_I 1
+
+ /* Dynamic barrier control for Idle*/
+#define L1_1RX_RXLEV_FLAG_DB_I 1
+#define L1_1RX_RXLEV_DB_L_BOUND_I 0
+#define L1_1RX_RXLEV_DB_U_BOUND_I 9
+#define L1_1RX_RXLEV_DB_FAIL_STEP_I 4
+#define L1_1RX_RXLEV_DB_TO_STEP_I 1
+#define L1_1RX_RXLEV_DB_T_RELAX_I (102*40)
+
+#define L1_1RX_HR_FLAG_DB_I 1
+#define L1_1RX_HR_DB_L_BOUND_I 0
+#define L1_1RX_HR_DB_U_BOUND_I 100
+#define L1_1RX_HR_DB_FAIL_STEP_I 50
+#define L1_1RX_HR_DB_TO_STEP_I 20
+#define L1_1RX_HR_DB_T_RELAX_I (102*40)
+
+ /* Switch back thresholds for Idle*/
+#define L1_1Rx_SB_SNR_BLOCK_I 6
+#define L1_1RX_SB_RXLEV_PRE_SWT_THD_I -2
+#define L1_1RX_SB_HR_ABS_THD_I 1
+#define L1_1RX_SB_PCL_CB_PRE_SWT_THD_I 0
+#define L1_1RX_SB_PCL_RXLEV_CB_PRE_SWT_THD_I 1
+
+
+ /* utas_1RX_PublicParams for dedicate */
+ /* Timeout thresholds for dedicate*/
+
+#define L1_1RX_TIMEOUT_HIGH_QUAL_THD_D -60
+#define L1_1RX_TIMEOUT_LOW_QUAL_THD_D -108
+#define L1_1RX_TIMEOUT_LONG_COUNT_THD_D (104*60)
+#define L1_1RX_TIMEOUT_SHORT_COUNT_THD_D (104*20)
+ /* adaptive threshold control for dedicate*/
+#define L1_1RX_tSTEP_D (104*2)
+#define L1_1RX_tBOUND_D (104*40)
+
+ /* Event trigger parameters for dedicate*/
+#define L1_1RX_N_CB_D (104*4)
+#define L1_1RX_EVENT_LOW_QUAL_THD_D -108
+#define L1_1RX_EVENT_RXLEV_CB_THD_D -4
+#define L1_1RX_EVENT_HR_ABS_THD_D 1
+
+ /* Dynamic barrier control for dedicate*/
+#define L1_1RX_RXLEV_FLAG_DB_D 1
+#define L1_1RX_RXLEV_DB_L_BOUND_D 0
+#define L1_1RX_RXLEV_DB_U_BOUND_D 9
+#define L1_1RX_RXLEV_DB_FAIL_STEP_D 4
+#define L1_1RX_RXLEV_DB_TO_STEP_D 1
+#define L1_1RX_RXLEV_DB_T_RELAX_D (104*40)
+
+#define L1_1RX_HR_FLAG_DB_D 1
+#define L1_1RX_HR_DB_L_BOUND_D 0
+#define L1_1RX_HR_DB_U_BOUND_D 100
+#define L1_1RX_HR_DB_FAIL_STEP_D 50
+#define L1_1RX_HR_DB_TO_STEP_D 20
+#define L1_1RX_HR_DB_T_RELAX_D (104*40)
+
+ /* Switch back thresholds for dedicate*/
+#define L1_1Rx_SB_SNR_BLOCK_D 6
+#define L1_1RX_SB_RXLEV_PRE_SWT_THD_D -2
+#define L1_1RX_SB_HR_ABS_THD_D 1
+#define L1_1RX_SB_PCL_CB_PRE_SWT_THD_D 0
+#define L1_1RX_SB_PCL_RXLEV_CB_PRE_SWT_THD_D 1
+
+ /* utas_RXD_sTxPublicParams for Idle */
+ /* Switch over thresholds for Idle*/
+
+#define L1_RXD_STX_SO_PHR_ABS_THD_I 1
+#define L1_RXD_STX_SO_PPCL_GAIN_THD_I -2
+#define L1_RXD_STX_SO_PHR_GAIN_THD_I 2
+
+ /* Switch Back thresholds for Idle*/
+#define L1_RXD_STX_SB_N_PRE_SWT_I (104*2)
+#define L1_RXD_STX_SB_PCL_CB_PRE_SWT_THD_I 0
+#define L1_RXD_STX_SB_HR_CB_PRE_SWT_THD_I 1
+#define L1_RXD_STX_SB_PCL_RXLEV_CB_PRE_SWT_THD_I 1
+
+ /* Dynamic barrier control for Idle*/
+#define L1_RXD_STX_PHR_PPCL_FLAG_DB_I 1
+#define L1_RXD_STX_DB_L_BOUND_I 0
+#define L1_RXD_STX_DB_U_BOUND_I 9
+#define L1_RXD_STX_DB_FAIL_STEP_I 4
+#define L1_RXD_STX_DB_TO_STEP_I 1
+#define L1_RXD_STX_DB_T_RELAX_I (102*40)
+
+ /* utas_RXD_sTxPublicParams for dedicate */
+ /* Switch over thresholds for dedicate*/
+
+#define L1_RXD_STX_SO_PHR_ABS_THD_D 1
+#define L1_RXD_STX_SO_PPCL_GAIN_THD_D -2
+#define L1_RXD_STX_SO_PHR_GAIN_THD_D 2
+
+ /* Switch Back thresholds for dedicate*/
+#define L1_RXD_STX_SB_N_PRE_SWT_D (104*2)
+#define L1_RXD_STX_SB_PCL_CB_PRE_SWT_THD_D 0
+#define L1_RXD_STX_SB_HR_CB_PRE_SWT_THD_D 1
+#define L1_RXD_STX_SB_PCL_RXLEV_CB_PRE_SWT_THD_D 1
+
+ /* Dynamic barrier control for dedicate*/
+#define L1_RXD_STX_PHR_PPCL_FLAG_DB_D 1
+#define L1_RXD_STX_DB_L_BOUND_D 0
+#define L1_RXD_STX_DB_U_BOUND_D 9
+#define L1_RXD_STX_DB_FAIL_STEP_D 4
+#define L1_RXD_STX_DB_TO_STEP_D 1
+#define L1_RXD_STX_DB_T_RELAX_D (104*40)
+
+
+ /* utas_RXD_BTxPublicParams for Idle*/
+ /* Switch over thresholds for Idle*/
+#define L1_RXD_BTX_EVENT_SO_N_CB_I (102*5)
+#define L1_RXD_BTX_EVENT_SO_RXLEV_CB_THD_I -4
+#define L1_RXD_BTX_EVENT_SO_HR_ABS_THD_I 1
+#define L1_RXD_BTX_PERIOD_SO_RXLEV_THD_I -90
+#define L1_RXD_BTX_PERIOD_SO_t_BTX_I (102*80)
+#define L1_RXD_BTX_PERIOD_SO_t_BTX_STEP_I (102*4)
+#define L1_RXD_BTX_PERIOD_SO_t_BTX_BOUND_I (102*160)
+
+ /* Switch back thresholds for Idle*/
+#define L1_RXD_BTX_S_SNR_BLOCK_I 7
+#define L1_RXD_BTX_SB_HR_ABS_THD_I 1
+#define L1_RXD_BTX_SB_RXLEV_CB_PRE_SWT_THD_I 1
+#define L1_RXD_BTX_SB_PCL_CB_PRE_SWT_THD_I 0
+#define L1_RXD_BTX_SB_PCL_RXLEV_CB_PRE_SWT_THD_I 1
+
+ /* Dynamic barrier control for Idle*/
+#define L1_RXD_BTX_RXLEV_FLAG_DB_I 1
+#define L1_RXD_BTX_RXLEV_DB_L_BOUND_I 0
+#define L1_RXD_BTX_RXLEV_DB_U_BOUND_I 9
+#define L1_RXD_BTX_RXLEV_DB_FAIL_STEP_I 4
+#define L1_RXD_BTX_RXLEV_DB_TO_STEP_I 1
+#define L1_RXD_BTX_RXLEV_DB_T_RELAX_I (102*40)
+
+#define L1_RXD_BTX_HR_FLAG_DB_I 1
+#define L1_RXD_BTX_HR_DB_L_BOUND_I 0
+#define L1_RXD_BTX_HR_DB_U_BOUND_I 100
+#define L1_RXD_BTX_HR_DB_FAIL_STEP_I 50
+#define L1_RXD_BTX_HR_DB_TO_STEP_I 20
+#define L1_RXD_BTX_HR_DB_T_RELAX_I (102*40)
+
+
+ /* utas_RXD_BTxPublicParams for dedicate*/
+ /* Switch over thresholds for dedicate*/
+#define L1_RXD_BTX_EVENT_SO_N_CB_D (104*4)
+#define L1_RXD_BTX_EVENT_SO_RXLEV_CB_THD_D -4
+#define L1_RXD_BTX_EVENT_SO_HR_ABS_THD_D 1
+#define L1_RXD_BTX_PERIOD_SO_RXLEV_THD_D -90
+#define L1_RXD_BTX_PERIOD_SO_t_BTX_D (104*20)
+#define L1_RXD_BTX_PERIOD_SO_t_BTX_STEP_D 104
+#define L1_RXD_BTX_PERIOD_SO_t_BTX_BOUND_D (104*40)
+
+ /* Switch back thresholds for dedicate*/
+#define L1_RXD_BTX_S_SNR_BLOCK_D 7
+#define L1_RXD_BTX_SB_HR_ABS_THD_D 1
+#define L1_RXD_BTX_SB_RXLEV_CB_PRE_SWT_THD_D 1
+#define L1_RXD_BTX_SB_PCL_CB_PRE_SWT_THD_D 0
+#define L1_RXD_BTX_SB_PCL_RXLEV_CB_PRE_SWT_THD_D 1
+ /* Dynamic barrier control for dedicate*/
+#define L1_RXD_BTX_RXLEV_FLAG_DB_D 1
+#define L1_RXD_BTX_RXLEV_DB_L_BOUND_D 0
+#define L1_RXD_BTX_RXLEV_DB_U_BOUND_D 9
+#define L1_RXD_BTX_RXLEV_DB_FAIL_STEP_D 4
+#define L1_RXD_BTX_RXLEV_DB_TO_STEP_D 1
+#define L1_RXD_BTX_RXLEV_DB_T_RELAX_D (104*40)
+
+#define L1_RXD_BTX_HR_FLAG_DB_D 1
+#define L1_RXD_BTX_HR_DB_L_BOUND_D 0
+#define L1_RXD_BTX_HR_DB_U_BOUND_D 100
+#define L1_RXD_BTX_HR_DB_FAIL_STEP_D 50
+#define L1_RXD_BTX_HR_DB_TO_STEP_D 20
+#define L1_RXD_BTX_HR_DB_T_RELAX_D (104*40)
+
+ /* utas_RXD_BRxPublicParams for Idle */
+ /* Switch over thresholds for Idle*/
+
+#define L1_RXD_BRX_EVENT_SO_N_CB_I (102*5)
+#define L1_RXD_BRX_EVENT_SO_LOW_QUAL_THD_I -108
+#define L1_RXD_BRX_EVENT_SO_RXLEV_CB_THD_I -6
+#define L1_RXD_BRX_EVENT_SO_SNR_THD_I 64
+
+#define L1_RXD_BRX_PERIOD_SO_RXLEV_THD_I -90
+#define L1_RXD_BRX_PERIOD_SO_t_BRX_I (102*80)
+#define L1_RXD_BRX_PERIOD_SO_t_BRX_STEP_I (102*4)
+#define L1_RXD_BRX_PERIOD_SO_t_BRX_BOUND_I (102*160)
+
+ /* Switch back thresholds for Idle*/
+#define L1_RXD_BRX_S_SNR_BLOCK_I 6
+#define L1_RXD_BRX_SB_N_PRE_SWT_I (102*8)
+#define L1_RXD_BRX_SB_RXLEV_CB_PRE_SWT_THD_I -2
+
+ /* Dynamic barrier control for Idle*/
+#define L1_RXD_BRX_RXLEV_FLAG_DB_I 1
+#define L1_RXD_BRX_RXLEV_DB_L_BOUND_I 0
+#define L1_RXD_BRX_RXLEV_DB_U_BOUND_I 9
+#define L1_RXD_BRX_RXLEV_DB_FAIL_STEP_I 4
+#define L1_RXD_BRX_RXLEV_DB_TO_STEP_I 1
+#define L1_RXD_BRX_RXLEV_DB_T_RELAX_I (104*40)
+
+ /* utas_RXD_BRxPublicParams for dedicate */
+ /* Switch over thresholds for dedicate*/
+
+#define L1_RXD_BRX_EVENT_SO_N_CB_D (104*4)
+#define L1_RXD_BRX_EVENT_SO_LOW_QUAL_THD_D -108
+#define L1_RXD_BRX_EVENT_SO_RXLEV_CB_THD_D -6
+#define L1_RXD_BRX_EVENT_SO_SNR_THD_D 64
+
+#define L1_RXD_BRX_PERIOD_SO_RXLEV_THD_D -90
+#define L1_RXD_BRX_PERIOD_SO_t_BRX_D (104*20)
+#define L1_RXD_BRX_PERIOD_SO_t_BRX_STEP_D 104
+#define L1_RXD_BRX_PERIOD_SO_t_BRX_BOUND_D (104*40)
+
+ /* Switch back thresholds for dedicate*/
+#define L1_RXD_BRX_S_SNR_BLOCK_D 6
+#define L1_RXD_BRX_SB_N_PRE_SWT_D (104*2)
+#define L1_RXD_BRX_SB_RXLEV_CB_PRE_SWT_THD_D -2
+
+ /* Dynamic barrier control for dedicate*/
+#define L1_RXD_BRX_RXLEV_FLAG_DB_D 1
+#define L1_RXD_BRX_RXLEV_DB_L_BOUND_D 0
+#define L1_RXD_BRX_RXLEV_DB_U_BOUND_D 9
+#define L1_RXD_BRX_RXLEV_DB_FAIL_STEP_D 4
+#define L1_RXD_BRX_RXLEV_DB_TO_STEP_D 1
+#define L1_RXD_BRX_RXLEV_DB_T_RELAX_D (104*40)
+
+/* RAS Parameters*/
+
+#if IS_2G_RXD_SUPPORT
+#define RXD_MODE L1D_RAS_MODE
+#define C1_P_THD_HIGH_RXLEV -32768
+#define C1_THD_HIGH_RXLEV -110
+#define C1_THD_LOW_RXLEV -105
+#define C1_P_D_THD_RXLEV_DIFF 20
+#define C2_THD_RXLEV -80
+#define C2_THD_TSCSNR 32767
+#define C2_THD_PRESNR 256
+#define C3_THD_OBB_DEDICATED 4
+#define C3_THD_OBB_IDLE 0
+ #if IS_2G_RAS_CROSS_MODE_SUPPORT
+#define RXD_THD_RXLEV_DIFF 3
+ #else
+#define RXD_THD_RXLEV_DIFF 32767
+ #endif
+#define PERIOD_IDLE 816
+#define PERIOD_DEDICATED 208
+ #if IS_2G_RXD_ENHANCEMENT_SUPPORT
+#define OBB_PERIOD_DEDICATED 26
+ #endif
+ #if IS_2G_RAS_DECISION_INCLUDE_DSP_POW_SUPPORT
+#define C1_THD_RLV_PROTECT -93
+#define C1_THD_DSP_POW_PROTECT 6
+#define C1_THD_RLV_DSP_POW_PROTECT 20
+ #endif /* IS_2G_RAS_DECISION_INCLUDE_DSP_POW_SUPPORT */
+ #if IS_2G_C_VALUE_SUPPORT
+#define C1_THD_CVALUE_L 16
+#define C1_THD_CVALUE_H 128
+ #endif
+ #if IS_2G_RXD_BLACKLIST_SUPPORT
+#define GSM850_RXD_BLACKLIST_ENABLE L1D_BLACKLIST_BAND_DISABLE
+#define GSM_RXD_BLACKLIST_ENABLE L1D_BLACKLIST_BAND_DISABLE
+#define DCS_RXD_BLACKLIST_ENABLE L1D_BLACKLIST_BAND_DISABLE
+#define PCS_RXD_BLACKLIST_ENABLE L1D_BLACKLIST_BAND_DISABLE
+#define BLACKLIST_CH0 846
+#define BLACKLIST_CH1 0x7FFF
+#define BLACKLIST_CH2 0x7FFF
+#define BLACKLIST_CH3 0x7FFF
+#define BLACKLIST_CH4 0x7FFF
+#define BLACKLIST_CH5 0x7FFF
+#define BLACKLIST_CH6 0x7FFF
+#define BLACKLIST_CH7 0x7FFF
+#define BLACKLIST_CH8 0x7FFF
+#define BLACKLIST_CH9 0x7FFF
+#define BLACKLIST_CH10 0x7FFF
+#define BLACKLIST_CH11 0x7FFF
+#define BLACKLIST_CH12 0x7FFF
+#define BLACKLIST_CH13 0x7FFF
+#define BLACKLIST_CH14 0x7FFF
+#define BLACKLIST_CH15 0x7FFF
+#define BLACKLIST_CH16 0x7FFF
+#define BLACKLIST_CH17 0x7FFF
+#define BLACKLIST_CH18 0x7FFF
+#define BLACKLIST_CH19 0x7FFF
+#define BLACKLIST_CH20 0x7FFF
+#define BLACKLIST_CH21 0x7FFF
+#define BLACKLIST_CH22 0x7FFF
+#define BLACKLIST_CH23 0x7FFF
+#define BLACKLIST_CH24 0x7FFF
+#define BLACKLIST_CH25 0x7FFF
+#define BLACKLIST_CH26 0x7FFF
+#define BLACKLIST_CH27 0x7FFF
+#define BLACKLIST_CH28 0x7FFF
+#define BLACKLIST_CH29 0x7FFF
+#define BLACKLIST_CH30 0x7FFF
+#define BLACKLIST_CH31 0x7FFF
+ #endif /* IS_2G_RXD_BLACKLIST_SUPPORT */
+#endif
+#endif
+
diff --git a/mcu/interface/l1/gl1/external/l1_option.h b/mcu/interface/l1/gl1/external/l1_option.h
new file mode 100644
index 0000000..2d3c8bd
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1_option.h
@@ -0,0 +1,888 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1_option.h
+ *
+ * Project:
+ * --------
+ * MT6280
+ *
+ * Description:
+ * ------------
+ * The global compile option definition of L1
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *******************************************************************************/
+
+#ifndef __L1_OPTION_H__
+#define __L1_OPTION_H__
+
+/***************************************************************************************************************************
+ * Chip ID & compile option definition for other modules *
+ ***************************************************************************************************************************/
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT && L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD
+ #if !defined(__UMTS_FDD_MODE__)
+#define __UMTS_FDD_MODE__ 1
+ #endif
+ #if !defined(__MTK_UL1_FDD__)
+#define __MTK_UL1_FDD__ 1
+ #endif
+ #if !defined(__AST_TL1_TDD__)
+#define __AST_TL1_TDD__ 1
+ #endif
+ #if !defined(__UMTS_TDD128_MODE__)
+#define __UMTS_TDD128_MODE__ 1
+ #endif
+#endif
+
+/* Chip ID */
+#if defined(L1_SIM) || defined(ESIM_BUILD_CONFIG) || defined(__UE_SIMULATOR__)/* L1_SIM, ESIM-MOLY and UESIM-MOLY */
+ #ifdef L1D_TEST
+#define MD_DRV_IS_CHIP_MT6293 ((defined MT6293) || (defined MT6763) || (defined MT6739) || (defined MT6771) || (defined MT6765))
+#define MD_DRV_IS_CHIP_MT6763 (defined MT6763)
+#define MD_DRV_IS_CHIP_MT6739 (defined MT6739)
+#define MD_DRV_IS_CHIP_MT6771 (defined MT6771)
+#define MD_DRV_IS_CHIP_MT6765 (defined MT6765)
+#define MD_DRV_IS_CHIP_MT6295 ((defined MT6295M) || (defined MT3967) || (defined MT6779))
+#define MD_DRV_IS_CHIP_MT3967 (defined MT3967)
+#define MD_DRV_IS_CHIP_MT6779 (defined MT6779)
+#define MD_DRV_IS_CHIP_MT6297 ((defined MT6297) || (defined MT6885) || (defined MERCURY) || (defined MT6873) || (defined MT6853) || (defined MT6833) || (defined MT6880) || (defined MT6890) || (defined MT2735) || (defined MT6893) || (defined MT6877) || (defined MT6855))
+#define MD_DRV_IS_CHIP_MT6885 ((defined MT6885) || (defined MERCURY) || (defined MT6873) || (defined MT6853) || (defined MT6833) || (defined MT6880) || (defined MT6890) || (defined MT2735) || (defined MT6893) || (defined MT6877) || (defined MT6855))
+#define MD_DRV_IS_CHIP_MERCURY (defined MERCURY)
+#define MD_DRV_IS_CHIP_MT6873 (defined MT6873)
+#define MD_DRV_IS_CHIP_MT6853 (defined MT6853)
+#define MD_DRV_IS_CHIP_MT6833 (defined MT6833)
+#define MD_DRV_IS_CHIP_MT6880 (defined MT6880)
+#define MD_DRV_IS_CHIP_MT6890 (defined MT6890)
+#define MD_DRV_IS_CHIP_MT2735 (defined MT2735)
+#define MD_DRV_IS_CHIP_MT6893 (defined MT6893)
+#define MD_DRV_IS_CHIP_MT6877 (defined MT6877)
+#define MD_DRV_IS_CHIP_MT6855 (defined MT6855)
+#define MD_DRV_IS_CHIP_MT6292 (defined ELBRUS) || (defined MT6799)
+#define MD_DRV_IS_CHIP_MT6755 (defined MT6755)
+#define MD_DRV_IS_CHIP_TK6291 (defined TK6291) || (defined MT6291)
+ #else
+#define MD_DRV_IS_CHIP_TK6291 (defined TK6291) || (defined MT6291)
+#define MD_DRV_IS_CHIP_MT6755 (defined MT6755)
+#define MD_DRV_IS_CHIP_MT6292 ((defined ELBRUS) || (defined MT6799))
+#define MD_DRV_IS_CHIP_MT6293 ((defined MT6293) || (defined MT6763) || (defined MT6739) || (defined MT6771) || (defined MT6765))
+#define MD_DRV_IS_CHIP_MT6763 (defined MT6763)
+#define MD_DRV_IS_CHIP_MT6739 (defined MT6739)
+#define MD_DRV_IS_CHIP_MT6771 (defined MT6771)
+#define MD_DRV_IS_CHIP_MT6765 (defined MT6765)
+#define MD_DRV_IS_CHIP_MT6295 ((defined MT6295M) || (defined MT3967) || (defined MT6779))
+#define MD_DRV_IS_CHIP_MT3967 (defined MT3967)
+#define MD_DRV_IS_CHIP_MT6779 (defined MT6779)
+#define MD_DRV_IS_CHIP_MT6297 ((defined MT6297) || (defined MT6885) || (defined MERCURY) || (defined MT6873) || (defined MT6853) || (defined MT6833) || (defined MT6880) || (defined MT6890) || (defined MT2735) || (defined MT6893) || (defined MT6877) || (defined MT6855))
+#define MD_DRV_IS_CHIP_MT6885 ((defined MT6885) || (defined MERCURY) || (defined MT6873) || (defined MT6853) || (defined MT6833) || (defined MT6880) || (defined MT6890) || (defined MT2735) || (defined MT6893) || (defined MT6877) || (defined MT6855))
+#define MD_DRV_IS_CHIP_MERCURY (defined MERCURY)
+#define MD_DRV_IS_CHIP_MT6873 (defined MT6873)
+#define MD_DRV_IS_CHIP_MT6853 (defined MT6853)
+#define MD_DRV_IS_CHIP_MT6833 (defined MT6833)
+#define MD_DRV_IS_CHIP_MT6880 (defined MT6880)
+#define MD_DRV_IS_CHIP_MT6890 (defined MT6890)
+#define MD_DRV_IS_CHIP_MT2735 (defined MT2735)
+#define MD_DRV_IS_CHIP_MT6893 (defined MT6893)
+#define MD_DRV_IS_CHIP_MT6877 (defined MT6877)
+#define MD_DRV_IS_CHIP_MT6855 (defined MT6855)
+ #endif
+#else
+#define MD_DRV_IS_CHIP_MT6276 (defined MT6276)
+#define MD_DRV_IS_CHIP_MT6573 (defined MT6573)
+#define MD_DRV_IS_CHIP_MT6575 ((defined MT6575) || (defined MT6577))
+#define MD_DRV_IS_CHIP_MT6250 (defined MT6250)
+#define MD_DRV_IS_CHIP_MT6280 (defined MT6280)
+#define MD_DRV_IS_CHIP_MT6583_MD1 ((((defined MT6583)||(defined MT6589)) && (defined __MD1__)))
+#define MD_DRV_IS_CHIP_MT6583_MD2 ((((defined MT6583)||(defined MT6589)) && (defined __MD2__)))
+#define MD_DRV_IS_CHIP_MT6572 ((defined MT6572) || (defined MT6582))
+#define MD_DRV_IS_CHIP_MT6582 (defined MT6582)
+#define MD_DRV_IS_CHIP_MT6290 (defined MT6290)
+#define MD_DRV_IS_CHIP_MT6595 ((defined MT6595))
+#define MD_DRV_IS_CHIP_MT6752_MD1 ((defined MT6752) && (defined __MD1__))
+#define MD_DRV_IS_CHIP_MT6752_MD2 ((defined MT6752) && (defined __MD2__))
+#define MD_DRV_IS_CHIP_TK6291 (defined TK6291)
+#define MD_DRV_IS_CHIP_MT6755 (defined MT6755)
+#define MD_DRV_IS_CHIP_MT6292 ((defined ELBRUS) || (defined MT6799))
+#define MD_DRV_IS_CHIP_MT6799 (defined MT6799)
+#define MD_DRV_IS_CHIP_MT6293 ((defined MT6293) || (defined MT6763) || (defined MT6739) || (defined MT6771) || (defined MT6765))
+#define MD_DRV_IS_CHIP_MT6763 (defined MT6763)
+#define MD_DRV_IS_CHIP_MT6739 (defined MT6739)
+#define MD_DRV_IS_CHIP_MT6771 (defined MT6771)
+#define MD_DRV_IS_CHIP_MT6765 (defined MT6765)
+#define MD_DRV_IS_CHIP_MT6295 ((defined MT6295M) || (defined MT3967) || (defined MT6779))
+#define MD_DRV_IS_CHIP_MT3967 (defined MT3967)
+#define MD_DRV_IS_CHIP_MT6779 (defined MT6779)
+#define MD_DRV_IS_CHIP_MT6297 ((defined MT6297) || (defined MT6885) || (defined MERCURY) || (defined MT6873) || (defined MT6853) || (defined MT6833) || (defined MT6880) || (defined MT6890) || (defined MT2735) || (defined MT6893) || (defined MT6877) || (defined MT6855))
+#define MD_DRV_IS_CHIP_MT6885 ((defined MT6885) || (defined MERCURY) || (defined MT6873) || (defined MT6853) || (defined MT6833) || (defined MT6880) || (defined MT6890) || (defined MT2735) || (defined MT6893) || (defined MT6877) || (defined MT6855))
+#define MD_DRV_IS_CHIP_MERCURY (defined MERCURY)
+#define MD_DRV_IS_CHIP_MT6873 (defined MT6873)
+#define MD_DRV_IS_CHIP_MT6853 (defined MT6853)
+#define MD_DRV_IS_CHIP_MT6833 (defined MT6833)
+#define MD_DRV_IS_CHIP_MT6880 (defined MT6880)
+#define MD_DRV_IS_CHIP_MT6890 (defined MT6890)
+#define MD_DRV_IS_CHIP_MT2735 (defined MT2735)
+#define MD_DRV_IS_CHIP_MT6893 (defined MT6893)
+#define MD_DRV_IS_CHIP_MT6877 (defined MT6877)
+#define MD_DRV_IS_CHIP_MT6855 (defined MT6855)
+#endif
+
+// follow l1d_cid.h for build pass
+// Should be deleted when running MT6293
+#if ( defined(L1_SIM) || (defined(ESIM_BUILD_CONFIG) && (ESIM_BUILD_CONFIG == ESIM_MULTI_MODE_ON_FIBERS)) )&& ( MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297 )
+ #ifdef L1D_TEST
+ #if (defined __MD93__)
+#undef MD_DRV_IS_CHIP_MT6293
+#define MD_DRV_IS_CHIP_MT6293 (1)
+#undef MD_DRV_IS_CHIP_MT6292
+#define MD_DRV_IS_CHIP_MT6292 (0)
+ #endif
+ #else
+ #if (defined __MD93__)
+#undef MD_DRV_IS_CHIP_MT6293
+#define MD_DRV_IS_CHIP_MT6293 (0)
+#undef MD_DRV_IS_CHIP_MT6295
+#define MD_DRV_IS_CHIP_MT6295 (0)
+#undef MD_DRV_IS_CHIP_MT6297
+#define MD_DRV_IS_CHIP_MT6297 (0)
+#undef MD_DRV_IS_CHIP_MT6292
+#define MD_DRV_IS_CHIP_MT6292 (1)
+ #endif
+ #if (defined __MD95__)
+#undef MD_DRV_IS_CHIP_MT6293
+#define MD_DRV_IS_CHIP_MT6293 (0)
+#undef MD_DRV_IS_CHIP_MT6295
+#define MD_DRV_IS_CHIP_MT6295 (1)
+#undef MD_DRV_IS_CHIP_MT6297
+#define MD_DRV_IS_CHIP_MT6297 (0)
+#undef MD_DRV_IS_CHIP_MT6292
+#define MD_DRV_IS_CHIP_MT6292 (0)
+ #endif
+ #endif
+#endif
+
+#if MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+#define MD_DRV_IS_MD_DSP_DM_4BYTE_ALIGN_CHIP (1)
+#else
+#define MD_DRV_IS_MD_DSP_DM_4BYTE_ALIGN_CHIP (0)
+#endif
+
+/* Chip ID consistency check */
+#if MD_DRV_IS_CHIP_MT6276 || MD_DRV_IS_CHIP_MT6573 || MD_DRV_IS_CHIP_MT6575 || MD_DRV_IS_CHIP_MT6250 || MD_DRV_IS_CHIP_MT6280 || MD_DRV_IS_CHIP_MT6583_MD1 || MD_DRV_IS_CHIP_MT6583_MD2 || MD_DRV_IS_CHIP_MT6572 || MD_DRV_IS_CHIP_MT6290 || MD_DRV_IS_CHIP_MT6595 || MD_DRV_IS_CHIP_MT6752_MD1 || MD_DRV_IS_CHIP_MT6752_MD2 || MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+#else
+#error "Please check the chip ID defined in l1d_cid.h"
+#endif
+
+/* RF ID */
+#define MD_DRV_IS_RF_MT6280RF (defined MT6280RF_2G_RF)
+#define MD_DRV_IS_RF_MT6169 (defined MT6169_2G_RF)
+#define MD_DRV_IS_RF_MT6166 (defined MT6166_2G_RF)
+#define MD_DRV_IS_RF_MT6165 (defined MT6165_2G_RF)
+#define MD_DRV_IS_RF_MT6176 (defined MT6176_2G_RF)
+#define MD_DRV_IS_RF_MT6179 (defined MT6179_2G_RF)
+#define MD_DRV_IS_RF_MT6177L (defined MT6177L_2G_RF)
+#define MD_DRV_IS_RF_MT6177M (defined MT6177M_2G_RF)
+#define MD_DRV_IS_RF_TRINITYE1 (defined TRINITYE1_2G_RF)
+#define MD_DRV_IS_RF_TRINITYL ((defined TRINITYL_2G_RF)||(defined MT6185M_2G_RF))
+#define MD_DRV_IS_RF_MT6186 (defined MT6186_2G_RF)
+#define MD_DRV_IS_RF_MT6186M (defined MT6186M_2G_RF)
+#define MD_DRV_IS_RF_MT6190T ((defined MT6190T_2G_RF)||(defined MT6190_2G_RF)||(defined MT6190M_2G_RF)||(defined MT6195_2G_RF))
+#define MD_DRV_IS_RF_MT6190 ((defined MT6190_2G_RF)||(defined MT6190M_2G_RF))
+#define MD_DRV_IS_RF_MT6190M (defined MT6190M_2G_RF)
+
+
+/* ======================================================================================================================= */
+
+// Definition of GSM/GPRS/EGPRS support
+#if (defined MODE_EGPRS) || (defined MTK_EGPRS_ENABLE) || (defined __EGPRS_MODE__)
+#define MD_DRV_IS_GSM 0
+#define MD_DRV_IS_GPRS 1
+#define MD_DRV_IS_EGPRS 1
+#elif ((defined MODE_GPRS) || (defined __PS_SERVICE__) || (defined MTK_GPRS_ENABLE) || (GPRS==1))
+#define MD_DRV_IS_GSM 0
+#define MD_DRV_IS_GPRS 1
+#define MD_DRV_IS_EGPRS 0
+#else
+#define MD_DRV_IS_GSM 1
+#define MD_DRV_IS_GPRS 0
+#define MD_DRV_IS_EGPRS 0
+#endif
+
+// EPSK TX Support
+#if (defined __EPSK_TX__)
+#define MD_DRV_IS_EPSK_TX_SUPPORT 1
+#else
+#define MD_DRV_IS_EPSK_TX_SUPPORT 0
+#endif
+
+// Centralized sleep mode
+#define MD_DRV_IS_CENTRALIZED_SMM_CHIP 1
+
+// TDD Dual Mode Feature Option
+#if ((defined __UMTS_TDD128_MODE__) && MD_DRV_IS_CHIP_MT6250)
+#define MD_DRV_IS_AST_B2S_SUPPORT 1
+#else
+#define MD_DRV_IS_AST_B2S_SUPPORT 0
+#endif
+
+// For feature of split binary: MAUI/FACTORY bin
+#if (defined __FACTORY_BIN__) || !(defined __SPLIT_BINARY__)
+#define MD_DRV_IS_FOR_FACTORY_MODE_ONLY 1
+#else
+#define MD_DRV_IS_FOR_FACTORY_MODE_ONLY 0
+#endif
+
+// Factory mode compile option: FHC & NSFT
+#if MD_DRV_IS_FOR_FACTORY_MODE_ONLY
+#define MD_DRV_IS_FHC_SUPPORT 1
+#define MD_DRV_IS_NSFT_SUPPORT 1
+#define MD_DRV_IS_SINGLE_END_BER_SUPPORT 1
+#define MD_DRV_IS_NSFT_SACCH_TEST_ITEM_SUPPORT 1
+#else
+#define MD_DRV_IS_FHC_SUPPORT 0
+#define MD_DRV_IS_NSFT_SUPPORT 0
+#define MD_DRV_IS_SINGLE_END_BER_SUPPORT 0
+#define MD_DRV_IS_NSFT_SACCH_TEST_ITEM_SUPPORT 0
+#endif
+
+#if MD_DRV_IS_NSFT_SUPPORT && MD_DRV_IS_EPSK_TX_SUPPORT
+#define MD_DRV_IS_NSFT_LIST_MODE_SUPPORT 1
+#else
+#define MD_DRV_IS_NSFT_LIST_MODE_SUPPORT 0
+#endif
+
+// Multi-slot TX Support in GSM only
+#if MD_DRV_IS_FHC_SUPPORT && MD_DRV_IS_GSM
+#define MD_DRV_IS_MULTISLOT_TX_SUPPORT 0
+#else
+#define MD_DRV_IS_MULTISLOT_TX_SUPPORT 0
+#endif
+
+// AFC 33-section Calibration
+#if defined MT6253T || defined MT6253L
+#define MD_DRV_IS_VCXO_LC_SUPPORT 1
+#else
+#define MD_DRV_IS_VCXO_LC_SUPPORT 0
+#endif
+
+// TX Power Compensation
+#if defined (__2G_TX_POWER_CONTROL_SUPPORT__)
+#define MD_DRV_IS_TX_POWER_CONTROL_SUPPORT 1
+ #if MD_DRV_IS_CHIP_MT6276 || MD_DRV_IS_CHIP_MT6573
+#define MD_DRV_IS_TXPC_CL_AUXADC_SUPPORT 1 // Closed-loop TX Power Compensation (Vdet from AUXADC)
+ #else
+#define MD_DRV_IS_TXPC_CL_AUXADC_SUPPORT 0
+ #endif
+#else
+#define MD_DRV_IS_TX_POWER_CONTROL_SUPPORT 0
+#define MD_DRV_IS_TXPC_CL_AUXADC_SUPPORT 0
+#endif
+
+// W cancellation
+#if (defined L1D_TEST) || (defined L1_SIM)
+#define MD_DRV_IS_W_CANCELLATION_SUPPORT 0
+#elif MD_DRV_IS_CHIP_MT6250 || MD_DRV_IS_CHIP_MT6280 || MD_DRV_IS_CHIP_MT6583_MD1 || MD_DRV_IS_CHIP_MT6572 || MD_DRV_IS_CHIP_MT6290 || MD_DRV_IS_CHIP_MT6595 || MD_DRV_IS_CHIP_MT6752_MD1 || MD_DRV_IS_CHIP_MT6752_MD2 || MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+#define MD_DRV_IS_W_CANCELLATION_SUPPORT 1
+#else
+#define MD_DRV_IS_W_CANCELLATION_SUPPORT 0
+#endif
+
+// 2G RF Custom Tool
+#if defined(__2G_RF_CUSTOM_TOOL_SUPPORT__)
+#define MD_DRV_IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 1
+#else
+#define MD_DRV_IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 0
+#endif
+
+// UDVT Frequency Hopping
+#if ((defined __UDVT__) && (MD_DRV_IS_CHIP_MT6250 || MD_DRV_IS_CHIP_MT6280))
+#define MD_DRV_IS_UDVT_FH_SUPPORT 1
+#else
+#define MD_DRV_IS_UDVT_FH_SUPPORT 0
+#endif
+
+// Feature of 32k crystal removal
+#if defined(__F32_XOSC_REMOVAL_SUPPORT__)
+#define MD_DRV_IS_32K_CRYSTAL_REMOVAL_SUPPORT 1
+#else
+#define MD_DRV_IS_32K_CRYSTAL_REMOVAL_SUPPORT 0
+#endif
+
+// Feature of TX gain RF calibration
+#if defined(__2G_TX_GAIN_RF_CALIBRATION__)
+#define MD_DRV_IS_TX_GAIN_RF_CALIBRATION_SUPPORT 1
+#else
+#define MD_DRV_IS_TX_GAIN_RF_CALIBRATION_SUPPORT 0
+#endif
+
+// For chip with 48-bit of BPI_DATA
+#if MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292
+#define MD_DRV_IS_BPI_DATA_48_BIT_CHIP 1
+#else
+#define MD_DRV_IS_BPI_DATA_48_BIT_CHIP 0
+#endif
+
+// For chip with 32-bit of BPI_DATA
+#if MD_DRV_IS_CHIP_MT6583_MD1 || MD_DRV_IS_CHIP_MT6583_MD2 || MD_DRV_IS_CHIP_MT6572 || MD_DRV_IS_CHIP_MT6290 || MD_DRV_IS_CHIP_MT6595 || MD_DRV_IS_CHIP_MT6752_MD1 || MD_DRV_IS_CHIP_MT6752_MD2 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+#define MD_DRV_IS_BPI_DATA_32_BIT_CHIP 1
+#else
+#define MD_DRV_IS_BPI_DATA_32_BIT_CHIP 0
+#endif
+
+// For MD2G SW mode
+#if MD_DRV_IS_CHIP_MT6276 || MD_DRV_IS_CHIP_MT6573 || MD_DRV_IS_CHIP_MT6575 || MD_DRV_IS_CHIP_MT6280 || MD_DRV_IS_CHIP_MT6583_MD1 || MD_DRV_IS_CHIP_MT6583_MD2 || MD_DRV_IS_CHIP_MT6572 || MD_DRV_IS_CHIP_MT6290 || MD_DRV_IS_CHIP_MT6595 || MD_DRV_IS_CHIP_MT6752_MD1 || MD_DRV_IS_CHIP_MT6752_MD2 || MD_DRV_IS_CHIP_TK6291 || MD_DRV_IS_CHIP_MT6755 || MD_DRV_IS_CHIP_MT6292 || MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295 || MD_DRV_IS_CHIP_MT6297
+#define MD_DRV_IS_MD2G_PWD_DEFAULT_SW_MODE 0
+#else
+#define MD_DRV_IS_MD2G_PWD_DEFAULT_SW_MODE 1
+#endif
+
+// Feature of Fix AFC
+#define MD_DRV_IS_DUAL_LOOP_AFC_CONTROL_SUPPORT 1
+
+// Feature of MIPI Control
+#if defined(__2G_MIPI_SUPPORT__)
+#define MD_DRV_IS_2G_MIPI_SUPPORT 1
+#else
+#define MD_DRV_IS_2G_MIPI_SUPPORT 0
+#endif
+
+#if MD_DRV_IS_2G_MIPI_SUPPORT && defined(__2G_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT__)
+/* Macro MD_DRV_IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT has been removed from GL1 code after TK6291 */
+#define MD_DRV_IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT 1
+#else
+#define MD_DRV_IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT 0
+#endif
+
+#if defined (__TX_POWER_OFFSET_SUPPORT__)
+#define MD_DRV_IS_TX_POWER_OFFSET_SUPPORT 1 /* Enable Tx power offset */
+#else
+#define MD_DRV_IS_TX_POWER_OFFSET_SUPPORT 0 /* Disable Tx power offset */
+#endif /*__TX_POWER_OFFSET_SUPPORT__*/
+
+#if defined (__NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__)
+#define MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT 1 /* Enable Tx power offset */
+#else
+#define MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT 0 /* Disable Tx power offset */
+#endif//__NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__
+
+#if defined(__TAS_SUPPORT__)
+ #if defined(__MD93__)
+#define MD_DRV_IS_2G_TAS_SUPPORT 1
+#define MD_DRV_IS_2G_Gen95_UTAS_SUPPORT 0
+#define MD_DRV_IS_2G_Gen97_UTAS_SUPPORT 0
+#define MD_DRV_IS_2G_TAS_INHERIT_4G_ANT 1
+ #elif defined(__MD95__) /*GL1D is not involved from Gen95 onwards since GL1C is taking care of it*/
+#define MD_DRV_IS_2G_TAS_SUPPORT 0
+#define MD_DRV_IS_2G_Gen95_UTAS_SUPPORT 1
+#define MD_DRV_IS_2G_Gen97_UTAS_SUPPORT 0
+#define MD_DRV_IS_2G_TAS_INHERIT_4G_ANT 0
+ #elif (defined(__MD97__) || defined(__MD97P__))
+#define MD_DRV_IS_2G_TAS_SUPPORT 0
+#define MD_DRV_IS_2G_Gen95_UTAS_SUPPORT 0
+#define MD_DRV_IS_2G_Gen97_UTAS_SUPPORT 1
+#define MD_DRV_IS_2G_TAS_INHERIT_4G_ANT 0
+ #else
+ #error "[ERROR] Invalid MD generation"
+ #endif
+#define MD_DRV_IS_2G_TAS_ANT_IDX_FOR_PM_WINDOW_SUPPORT 1
+#else
+#define MD_DRV_IS_2G_TAS_SUPPORT 0
+#define MD_DRV_IS_2G_TAS_ANT_IDX_FOR_PM_WINDOW_SUPPORT 0
+#define MD_DRV_IS_2G_TAS_INHERIT_4G_ANT 0
+#define MD_DRV_IS_2G_Gen95_UTAS_SUPPORT 0
+#define MD_DRV_IS_2G_Gen97_UTAS_SUPPORT 0
+#endif
+
+#if defined(__DYNAMIC_ANTENNA_TUNING__)
+ #if defined(__MD93__)
+ #define MD_DRV_IS_2G_DAT_SUPPORT 1
+ #define MD_DRV_IS_2G_Gen95_UDAT_SUPPORT 0
+ #elif defined(__MD95__)
+ #define MD_DRV_IS_2G_DAT_SUPPORT 0
+ #define MD_DRV_IS_2G_Gen95_UDAT_SUPPORT 1
+ #else
+ #error "[ERROR] Invalid MD generation"
+ #endif
+#else
+#define MD_DRV_IS_2G_DAT_SUPPORT 0
+#define MD_DRV_IS_2G_Gen95_UDAT_SUPPORT 0
+#endif
+
+/* Support using external LNA and adjust RX gain table in L1 code flow */
+#if MD_DRV_IS_RF_MT6179 || MD_DRV_IS_RF_MT6177L || MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T || MD_DRV_IS_RF_MT6177M
+#define MD_DRV_IS_2G_EXTERNAL_LNA_SUPPORT 1
+#else
+#define MD_DRV_IS_2G_EXTERNAL_LNA_SUPPORT 0
+#endif
+
+/* Support using BYPASS and adjust RX gain table in L1 code flow */
+#if MD_DRV_IS_2G_EXTERNAL_LNA_SUPPORT
+ #if MD_DRV_IS_RF_MT6177L || MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T || MD_DRV_IS_RF_MT6177M
+#define MD_DRV_IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 1
+ #else
+#define MD_DRV_IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 0
+ #endif
+#else
+#define MD_DRV_IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 0
+#endif
+
+#if MD_DRV_IS_CHIP_MT6293 || MD_DRV_IS_CHIP_MT6295
+#define MD_DRV_IS_2G_BANK_B_ENABLE 1
+#else
+ #if defined(L1_SIM) && !MD_DRV_IS_CHIP_MT6292
+//#error "need to use bank B at simulation"
+ #endif
+#define MD_DRV_IS_2G_BANK_B_ENABLE 0
+#endif
+
+#if MD_DRV_IS_CHIP_MT6295
+#define IS_DYNAMICAL_NOISE_FLOOR_AND_SATURATION_SUPPORT 1
+#else
+#define IS_DYNAMICAL_NOISE_FLOOR_AND_SATURATION_SUPPORT 0
+#endif
+
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1_public_defs.h b/mcu/interface/l1/gl1/external/l1_public_defs.h
new file mode 100644
index 0000000..a3bb7f6
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1_public_defs.h
@@ -0,0 +1,99 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+ /*******************************************************************************
+ * Filename:
+ * ---------
+ * l1_public_defs.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Layer1 global macro definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: 1.21 $
+ * $Modtime: Aug 05 2005 10:12:46 $
+ * $Log: //mtkvs01/vmdata/Maui_sw/archives/mcu/l1/common/l1_types_public.h-arc $
+ *
+ * 05 21 2021 shrikant.nandagawali
+ * [MOLY00665438] [Colgin][MT2735][New feature][MD] Wide temperature.[EWSP0000255811]
+ *
+ * 05 29 2015 sherman.chung
+ * [MOLY00116464] [UMOLY] 2G L1 TAS Check in
+ * .
+ *
+ *
+ *******************************************************************************/
+
+#ifndef _L1_PUBLIC_DEFS_H_
+#define _L1_PUBLIC_DEFS_H_
+#include "l1_option.h"
+
+#if MD_DRV_IS_FHC_SUPPORT
+#define FHC_PRE_CAPID_SEARCH_NUM 9
+#define FHC_MAX_CAPID_SEARCH_NUM (7 + FHC_PRE_CAPID_SEARCH_NUM)
+#endif
+
+#if defined (__COTMS_TELEMATICS_SUPPORT__)
+#define L1D_CALIB_TEMPERATURE_TMS_TYPE_1 (16384) //Partial Voltage corresponding to 25 deg celsius
+#define L1D_CALIB_TEMPERATURE_TMS_TYPE_2 (14336) //Partial Voltage corresponding to 30.5 deg celsius
+#define MAX_SIM_SUPPORTED 4
+extern unsigned int l1d_calib_temperature;
+extern unsigned int L1D_getCurrTemperature();
+extern int L1D_getScurveFrequencyOffsetValueInDAC(unsigned int tfc_u);
+#endif
+
+typedef enum
+{
+ FrequencyBand400,
+ FrequencyBand850,
+ FrequencyBand900,
+ FrequencyBand1800,
+ FrequencyBand1900,
+
+ FrequencyBandCount
+
+} FrequencyBand;
+
+#endif /* _L1_PUBLIC_DEFS_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1_types_public.h b/mcu/interface/l1/gl1/external/l1_types_public.h
new file mode 100644
index 0000000..f3e86e0
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1_types_public.h
@@ -0,0 +1,1436 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+ /*******************************************************************************
+ * Filename:
+ * ---------
+ * l1_types_public.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Layer1 global types
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ *
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+ * removed!
+ * removed!
+ *
+ *******************************************************************************/
+
+#ifndef l1_types_public_h
+#define l1_types_public_h
+
+#include "l1_option.h"
+#include "l1_public_defs.h"
+#include "mph_types.h"
+#include "kal_general_types.h"
+
+#include "l1_gemini_def.h"
+
+#include "l1d_cid.h"
+
+#if (defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+#include "mml1_fe_public.h"
+#endif
+
+typedef kal_int8 int8;
+typedef kal_int16 int16;
+typedef kal_int32 int32;
+typedef kal_int64 int64;
+typedef kal_int32 intx;
+typedef kal_uint8 uint8;
+typedef kal_uint16 uint16;
+typedef kal_uint32 uint32;
+typedef kal_uint32 uintx;
+typedef kal_bool bool;
+
+#define false KAL_FALSE
+#define true KAL_TRUE
+
+#if (defined(__MD97__) || defined(__MD97P__))
+#define L1D_MAX_SPLIT_NUM 4
+#define L1D_MAX_FORCE_RXTX_SUBBAND_NUM 3
+#define L1D_DAT_MAX_STATE_NUM 8
+#elif defined(__MD95__)
+#define L1D_MAX_SPLIT_NUM 5
+#define L1D_MAX_FORCE_RXTX_SUBBAND_NUM 3
+#define L1D_DAT_MAX_STATE_NUM 8
+#endif
+
+/* --- GSM primitive types ------------------------------------------------- */
+
+typedef int16 Gain; /* in 0.125 dB *//* !!important: please update the copy in m12194.c */
+typedef uint32 TimeStamp; /* redefine in l1-CORE_PRIVATE.H */
+
+/*
+@enum ReportType_FT | Type of a report for factory testing.
+*/
+typedef enum
+{
+ ReportFTNone, /* @emem No valid report. */
+ ReportFTReportPeriodDone, /* @emem End of report period. */
+ ReportFTPowerScanDone, /* @emem Power scan results. */
+ ReportFTFCCh, /* @emem FCCh result. */
+#if MD_DRV_IS_FHC_SUPPORT
+ ReportFTDTS,
+ ReportFTUTS,
+#endif
+#if MD_DRV_IS_NSFT_SUPPORT
+ ReportFTNSFT,
+#endif
+ ReportFTEnd /* @emem No valid report. Marks end of <t ReportType> enumeration */
+} ReportType_FT;
+
+/* For Gemini*/
+typedef enum
+{
+ L1C_SIM1 = 0x00
+#if defined(__GL1_GEMINI__)
+ ,L1C_SIM2 = 0x01
+#endif
+#if (GL1_GEMINI_NUM >= 3)
+ ,L1C_SIM3 = 0x02
+#endif
+#if (GL1_GEMINI_NUM >= 4)
+ ,L1C_SIM4 = 0x03
+#endif
+ ,L1C_SIM_NUM
+} l1c_sim_mode_enum;
+
+
+/* Create a general enum for LWG or LTG to represent the number of MM SIMs.
+Currently only WCDMA may have SIMx service */
+typedef enum
+{
+#ifdef __GL1_MULTI_MODE__
+ L1C_MM_SIM1 = 0x00,
+#if defined(__GL1_GEMINI_WCDMA__)
+ L1C_MM_SIM2 = 0x01,
+#endif
+#if (GL1_GEMINI_WCDMA_NUM >= 3)
+ L1C_MM_SIM3 = 0x02,
+#endif
+#if (GL1_GEMINI_WCDMA_NUM >= 4)
+ L1C_MM_SIM4 = 0x03,
+#endif
+#endif /* __GL1_MULTI_MODE__ */
+ L1C_MM_SIM_NUM
+} l1c_mm_sim_mode_enum;
+/*
+@struct Time | GSM time.
+*/
+typedef struct
+{
+ FrameNumber frame; /* @field Frame number */
+ intx ebits; /* @field Eighth bits */
+} Time;
+
+typedef struct MeasurementsStruct Measurements;
+struct MeasurementsStruct
+{
+/* --- must be initialised by called of L1I_StartMeasurements() --- */
+
+ /* not changed by measurement manager */
+
+ ARFCN ( *get )( Measurements* meas, int index );
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ void ( *put )( Measurements* meas, int index, Power power, Power power_drx );
+#else
+ void ( *put )( Measurements* meas, int index, Power power);
+#endif
+ void ( *done )( Measurements* meas, intx measurementsDone );
+
+ intx indexCount;
+ intx measurementCount; /* number of measurements to be performed */
+
+/* --- private data of measurement manager --- */
+
+ intx started; /* total number of measurements started */
+ intx finished; /* total number of measurements completed */
+ intx sessionLimit; /* total number of measurments to be done before session ends */
+ intx startIndex;
+ intx resultIndex;
+ uint8 runIndex; /* record the index of session run*/
+ bool is_stopped;
+#if defined(__GL1_GEMINI__)
+ l1c_sim_mode_enum sim_mode;
+#endif
+};
+
+#define GSM_ANT_RXM_IDX 0
+#define GSM_ANT_RXD_IDX 1
+//typedef enum
+//{
+// GSM_ANT_RXM_IDX = 0,
+// GSM_ANT_RXD_IDX = 1,
+// GSM_ANT_BOTH = 2
+//} GSM_AntDimension;
+
+typedef enum
+{
+ GSM_ANT_MASK_NULL = 0x0,
+ GSM_ANT_MASK_RXM = 0x1,
+ GSM_ANT_MASK_RXD = 0x2,
+ GSM_ANT_MASK_BOTH = 0x3
+} GSM_AntDimension; // L1D_RX_PATH_MASK_E
+
+
+
+#define GSM_RF_MAX_RX_ANT_NUM 2
+#define GSM_RF_MAX_RX_GAIN_NUM_V5 6
+
+#if MD_DRV_IS_FHC_SUPPORT
+
+#define L1_MAX_DTS_STEP_CNT 512
+#define L1_MAX_UTS_STEP_CNT 512
+
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+typedef struct
+{
+ int32 power[GSM_RF_MAX_RX_ANT_NUM][L1_MAX_DTS_STEP_CNT-2];
+ int16 valid_sample[GSM_RF_MAX_RX_ANT_NUM][L1_MAX_DTS_STEP_CNT-2];
+ bool ok;
+} ResultDSSPL; //RfTestResultDSSPL_512P_V5
+#else
+typedef struct
+{
+ int32 power[L1_MAX_DTS_STEP_CNT-2];
+ int16 valid_sample[L1_MAX_DTS_STEP_CNT-2];
+ bool ok;
+} ResultDSSPL;
+#endif
+
+typedef struct
+{
+ int32 freq_offset[33]; // only valid when 33 stage calibration is True
+ int32 deviation[33]; // only valid when 33 stage calibration is True
+ int16 fcb_ok_number[33];
+ int32 capid; // only valid when capid calibration is True
+ #if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ uint16 init_dac_value; // only valid when 33 stage calibration is False
+ #else
+ int16 init_dac_value; // only valid when 33 stage calibration is False
+ #endif
+ int32 slope; // only valid when 33 stage calibration is False
+ bool ok;
+} ResultDSSAfc;
+
+typedef struct
+{
+ int32 cload_freq_offset;
+ bool ok;
+ bool is_perform_cal;
+} ResultDSSLPM;
+
+typedef struct
+{
+ ResultDSSPL PLResult;
+ ResultDSSAfc AfcResult;
+ ResultDSSLPM LPMResult;
+// bool ok;
+} ResultDTS;
+#endif
+
+
+typedef enum
+{
+ AdditionalSB,
+ PeekSB,
+ ThermalSB
+} SBType; //The same with L1I_Str_ServingSB
+
+
+/*
+@struct SChData | Report data for sync burst reporting.
+*/
+typedef struct
+{
+ ARFCN arfcn;
+ bool ok; /* @field Sync burst status. Set by the baseband driver.
+ @flag false | Burst was bad. Other fields in this structure are invalid.
+ @flag true | Burst was OK. Other fields in this structure are valid. */
+ bool fcb_ok;
+ intx frameDelay; /* @field Frame where sync burst has been received relative to the frame where <f L1T_FCChStart> was called. . Set by the baseband driver. */
+ intx ebitDelay; /* @field Position of sync burst relative to current frame start in eighth bits. Set by the baseband driver. */
+ BlockData data[ 4 ]; /* @field Sync burst data. Set by the baseband driver. */
+
+ Time bsTimingOffset; /* @field Timing offset of the base station relative to the mobiles current
+ synchronisation. Calculated by layer1 */
+ FrameNumber bsFrame; /* @field Frame number decoded from the sync burst. Calculated by layer1. */
+ BSIC bsic; /* @field BSIC number decoded from the sync burst. Calculated by layer1. */
+ Time rxTime; /* @field Time the sync burst has been received. Calculated by layer1. */
+
+ bool hardwareUnavailable; /* special flag returned by SChT only if SCh was aborted because hardware
+ was occupied by higher priority operation */
+ bool extBsic; /* @field A flag to indicate if Extended measurement BSIC */
+ bool manual; /* @distinguish manual or surrounding */
+ bool enhancePM; /* default value is false*/
+ /* Set true for usage enhanced power measurement to update AGC ahead of FB/SB search in blind handover*/
+
+/* Tier-1 Modem */ int16 snr;
+/* Tier-1 Modem */ intx bitErrorCount;
+#if IS_SB_ENHANCE_TRACE_SUPPORT
+ uint8 wb_filter;
+ uint8 saic;
+ int16 wsnr;
+ int16 pre_snr;
+#endif
+ uint8 bsic_tid; /* for distinguish from different transaction */
+
+#ifdef __UMTS_RAT__
+ bool ready_to_report; /* True if L1C is ready to report SCh result to L1A, false otherwise. */
+ TimeStamp timeStamp;
+#endif
+#ifdef __GL1_MULTI_MODE__
+ uint8 fbWinOffDelay; /* FB win will be closed after "fbWinOffDelay" CT1 when L1C gets FCCh report. */
+#endif
+ Power power;
+} SChData;
+
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+typedef struct
+{
+ int32 power[GSM_RF_MAX_RX_ANT_NUM];
+ int32 iOffset[GSM_RF_MAX_RX_ANT_NUM];
+ int32 qOffset[GSM_RF_MAX_RX_ANT_NUM];
+ int32 deviation[GSM_RF_MAX_RX_ANT_NUM];
+ int32 validSamples[GSM_RF_MAX_RX_ANT_NUM];
+ Gain usedGain[GSM_RF_MAX_RX_ANT_NUM]; //For RF Tool PM & Rx AT CMD set gain
+ Measurements meas;
+} PM_TST_Data;
+#else
+typedef struct
+{
+ int32 power;
+ int32 iOffset;
+ int32 qOffset;
+ int32 deviation;
+ int32 validSamples;
+ Gain usedGain;
+ Measurements meas;
+} PM_TST_Data;
+#endif
+
+/*
+@union ReportData | Contains report information for factory testing
+*/
+typedef union
+{
+ SChData *sch; /* @field Results of FCB and SB search */
+ PM_TST_Data *pm_tst; /* @field power meas results in test mode */
+#if MD_DRV_IS_FHC_SUPPORT
+ ResultDTS *dts_result;
+#endif
+} ReportData_FT;
+
+/*
+@struct Report | Results of operations for factory testing.
+*/
+typedef struct
+{
+ ReportType_FT type; /* @field Type of report */
+ ReportData_FT data; /* @field Contains information dependent on the <e Report.type> field */
+} Report_FT;
+
+/*
+@struct sBBTXCfg | used to set/get run-time BBTX param
+*/
+typedef struct
+{
+ int8 TxTrimI;
+ int8 TxTrimQ;
+ int8 TxOffsetI;
+ int8 TxOffsetQ;
+ int8 TxCalbias;
+ int8 TxIQSwap;
+ int8 TxCMV;
+ int8 TxGain;
+ int8 TxCalrcsel;
+ int8 TxPhasesel;
+ int8 TxDccoarseI;
+ int8 TxDccoarseQ;
+} sBBTXCfg;
+
+#if (defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)) /*Need to change when we need to support differently for gen97*/
+typedef enum
+{
+ L1D_TAS_STATE0,
+ L1D_TAS_STATE1,
+ L1D_TAS_STATE2,
+ L1D_TAS_STATE3,
+ L1D_TAS_STATE4,
+ L1D_TAS_STATE5,
+ L1D_TAS_STATE6,
+ L1D_TAS_STATE7,
+ L1D_TAS_STATE8,
+ L1D_TAS_STATE9,
+ L1D_TAS_STATE10,
+ L1D_TAS_STATE11,
+ L1D_TAS_STATE12,
+ L1D_TAS_STATE13,
+ L1D_TAS_STATE14,
+ L1D_TAS_STATE15,
+ L1D_TAS_STATE16,
+ L1D_TAS_STATE17,
+ L1D_TAS_STATE18,
+ L1D_TAS_STATE19,
+ L1D_TAS_STATE20,
+ L1D_TAS_STATE21,
+ L1D_TAS_STATE22,
+ L1D_TAS_STATE23,
+ L1D_TAS_STATE_NUM,
+ L1D_TAS_STATE_NULL,
+}L1D_CUSTOM_TAS_STATE_E;
+#else /*Legacy TAS platform*/
+typedef enum
+{
+ L1D_TAS_STATE0,
+ L1D_TAS_STATE1,
+ L1D_TAS_STATE2,
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ L1D_TAS_STATE3,
+#endif /* (__2G_RX_DIVERSITY_PATH_SUPPORT__) */
+ //L1D_TAS_STATE4,
+ //L1D_TAS_STATE5,
+ //L1D_TAS_STATE6,
+ //L1D_TAS_STATE7,
+ L1D_TAS_STATE_NUM,
+ L1D_TAS_STATE_NULL,
+}L1D_CUSTOM_TAS_STATE_E;
+#endif
+
+#if (defined(__MD97__) || defined(__MD97P__) || defined(__MD95__))
+typedef enum
+{
+ GL1_ANT_STATE_0 = MMRFD_TAS_STATE0,
+ GL1_ANT_STATE_1 = MMRFD_TAS_STATE1,
+ GL1_ANT_STATE_2 = MMRFD_TAS_STATE2,
+ GL1_ANT_STATE_3 = MMRFD_TAS_STATE3,
+ GL1_ANT_STATE_4 = MMRFD_TAS_STATE4,
+ GL1_ANT_STATE_5 = MMRFD_TAS_STATE5,
+ GL1_ANT_STATE_6 = MMRFD_TAS_STATE6,
+ GL1_ANT_STATE_7 = MMRFD_TAS_STATE7,
+ GL1_ANT_STATE_8 = MMRFD_TAS_STATE8,
+ GL1_ANT_STATE_9 = MMRFD_TAS_STATE9,
+ GL1_ANT_STATE_10 = MMRFD_TAS_STATE10,
+ GL1_ANT_STATE_11 = MMRFD_TAS_STATE11,
+ GL1_ANT_STATE_12 = MMRFD_TAS_STATE12,
+ GL1_ANT_STATE_13 = MMRFD_TAS_STATE13,
+ GL1_ANT_STATE_14 = MMRFD_TAS_STATE14,
+ GL1_ANT_STATE_15 = MMRFD_TAS_STATE15,
+ GL1_ANT_STATE_16 = MMRFD_TAS_STATE16,
+ GL1_ANT_STATE_17 = MMRFD_TAS_STATE17,
+ GL1_ANT_STATE_18 = MMRFD_TAS_STATE18,
+ GL1_ANT_STATE_19 = MMRFD_TAS_STATE19,
+ GL1_ANT_STATE_20 = MMRFD_TAS_STATE20,
+ GL1_ANT_STATE_21 = MMRFD_TAS_STATE21,
+ GL1_ANT_STATE_22 = MMRFD_TAS_STATE22,
+ GL1_ANT_STATE_23 = MMRFD_TAS_STATE23,
+ GL1_ANT_STATE_NUM = MMRFD_TAS_STATE_NUM,
+ GL1_ANT_STATE_NULL = MMRFD_ANT_INVALID_PATTERN
+} AntennaStatus;
+#else
+typedef enum
+{
+ GL1_ANT_STATE_0,
+ GL1_ANT_STATE_1,
+ GL1_ANT_STATE_2,
+ GL1_ANT_STATE_3,
+ GL1_ANT_STATE_NUM
+} AntennaStatus;
+
+typedef struct
+{
+ AntennaStatus status;
+ uint8 rxd_mode; //only valid when RXD is enabled
+} TransmitAntenna;
+#endif /* __MD95__ */
+
+typedef enum
+{
+ L1D_TAS_VER_1_0 = 0,
+ L1D_TAS_VER_2_0 = 1,
+ L1D_MAX_TAS_VER_NUM,
+} L1D_CUSTOM_TAS_VER_E;
+
+typedef enum
+{
+ L1D_TAS_DISABLE,
+ L1D_TAS_ENABLE,
+}L1D_CUSTOM_TAS_SWITCH_E;
+
+typedef enum
+{
+ L1D_NUM_TAS_STATES_NA = 0,
+ L1D_NUM_TAS_STATES_1 = 1,
+ L1D_NUM_TAS_STATES_2 = 2,
+ L1D_NUM_TAS_STATES_3 = 3,
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ L1D_NUM_TAS_STATES_4 = 4,
+#endif
+ L1D_NUM_TAS_STATES_MAX,
+}L1D_CUSTOM_TAS_NUM_STATES_E;
+
+#if defined (__MD93__)
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+typedef struct
+{
+ /* STx SB Threshhold*/
+ kal_int16 RXD_STX_SB_PCL_CB_PRE_SWT_THD;
+ kal_int16 RXD_STX_SB_HR_CB_PRE_SWT_THD;
+ /*BTx and BRx threshhold*/
+ kal_int32 RXD_BTX_EVENT_SO_N_CB;
+ kal_int16 RXD_BTX_EVENT_SO_HR_ABS_THD;
+ kal_int16 RXD_BTX_EVENT_SO_RXLEV_CB_THD;
+ kal_int32 RXD_BRX_EVENT_SO_N_CB;
+ kal_int16 RXD_BRX_EVENT_SO_LOW_QUAL_THD;
+ kal_int16 RXD_BRX_EVENT_SO_RXLEV_CB_THD;
+ kal_uint16 RXD_BRX_EVENT_SO_SNR_THD;
+ /*BTx and BRx Threshhold*/
+ kal_int16 RXD_BTX_SB_HR_ABS_THD;
+ kal_int16 RXD_BTX_SB_PCL_CB_PRE_SWT_THD;
+ kal_int16 RXD_BTX_SB_HR_CB_PRE_SWT_THD;
+ kal_int16 RXD_BRX_SB_RXLEV_CB_PRE_SWT_THD;
+ kal_uint8 RXD_BTX_S_SNR_BLOCK;
+ kal_uint8 RXD_BRX_S_SNR_BLOCK;
+ /* STx SO Threshhold*/
+ kal_int32 RXD_STX_SO_PHR_ABS_THD;
+ kal_int32 RXD_STX_SO_PPCL_GAIN_THD;
+ kal_int32 RXD_STX_SO_PHR_GAIN_THD;
+}L1D_CUSTOM_RXD_THRESHOLD_T;
+#endif /* __2G_RX_DIVERSITY_PATH_SUPPORT__ */
+
+typedef struct
+{
+ kal_int16 TH_RXLEV; /* Enable TAS if RXLEV < TH_RXLEV */
+ kal_int16 TH_RXLEV_PS; /* Enable TAS if RXLEV < TH_RXLEV_PS in PTM */
+ kal_int16 S_RXLEV; /* Hysteresis for RXLEV comparison between 2 antennas(dB) */
+ kal_int32 FORCE_CHANGE_IDLE; /* Maximal period that adopted antenna remains unchanged at idle mode */
+ kal_int32 FORCE_CHANGE_DEDICATED; /* Maximal period that adopted antenna remains unchanged at dedicated mod */
+ kal_int32 PERIOD_IDLE; /* Checking period of TAS criterion at idle mode */
+ kal_int32 PERIOD_DEDICATED; /* Checking period of TAS criterion at dedicated mode; unit: 208 frames */
+ kal_uint16 TH_SNR; /* SNR threshold, used in criterion 1 */
+ kal_uint8 TH_PCL[FrequencyBandCount]; /* PCL threshold, used in criterion 1 in connected mode */
+ kal_uint8 S_SNR_BLOCK; /* Hysteresis for block-average SNR comparison between 2 antennas, need to divide by 8 */
+ kal_uint8 S_SNR_SMOOTH; /* Hysteresis for smoothing SNR comparison between 2 antennas, need to divide by 8 */
+ kal_bool FORCE_POWER_SCAN_ANT; /* 0: off 1: Force antenna utilizing in power scan state */
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ /*BTx DB parameters*/
+ kal_int16 RXD_BTX_PERIOD_SO_RXLEV_THD;
+ kal_int32 RXD_BTX_PERIOD_SO_t_BTX_D;
+ kal_int32 RXD_BTX_PERIOD_SO_t_BTX_I;
+ kal_int16 RXD_BTX_PERIOD_SO_t_BTX_STEP_D;
+ kal_int16 RXD_BTX_PERIOD_SO_t_BTX_STEP_I;
+ kal_int32 RXD_BTX_PERIOD_SO_t_BTX_BOUND_D;
+ kal_int32 RXD_BTX_PERIOD_SO_t_BTX_BOUND_I;
+ kal_int32 RXD_BTX_HR_DB_L_BOUND;
+ kal_int32 RXD_BTX_HR_DB_U_BOUND;
+ kal_int32 RXD_BTX_HR_DB_FAIL_STEP;
+ kal_int32 RXD_BTX_HR_DB_TO_STEP;
+ kal_int32 RXD_BTX_HR_DB_T_RELAX_D;
+ kal_int32 RXD_BTX_HR_DB_T_RELAX_I;
+ kal_int16 RXD_BTX_RXLEV_DB_L_BOUND;
+ kal_int16 RXD_BTX_RXLEV_DB_U_BOUND;
+ kal_int16 RXD_BTX_RXLEV_DB_FAIL_STEP;
+ kal_int16 RXD_BTX_RXLEV_DB_TO_STEP;
+ kal_int32 RXD_BTX_RXLEV_DB_T_RELAX_D;
+ kal_int32 RXD_BTX_RXLEV_DB_T_RELAX_I;
+ /*BRx DB Parameters*/
+ kal_int16 RXD_BRX_PERIOD_SO_RXLEV_THD;
+ kal_int32 RXD_BRX_PERIOD_SO_t_BRX_D;
+ kal_int32 RXD_BRX_PERIOD_SO_t_BRX_I;
+ kal_int16 RXD_BRX_PERIOD_SO_t_BRX_STEP_D;
+ kal_int16 RXD_BRX_PERIOD_SO_t_BRX_STEP_I;
+ kal_int32 RXD_BRX_PERIOD_SO_t_BRX_BOUND_D;
+ kal_int32 RXD_BRX_PERIOD_SO_t_BRX_BOUND_I;
+ kal_int16 RXD_BRX_RXLEV_DB_L_BOUND;
+ kal_int16 RXD_BRX_RXLEV_DB_U_BOUND;
+ kal_int16 RXD_BRX_RXLEV_DB_FAIL_STEP;
+ kal_int16 RXD_BRX_RXLEV_DB_TO_STEP;
+ kal_int32 RXD_BRX_RXLEV_DB_T_RELAX;
+ /*STx PPCL DB Parameters*/
+ kal_int16 RXD_STX_PPCL_DB_L_BOUND;
+ kal_int16 RXD_STX_PPCL_DB_U_BOUND;
+ kal_int16 RXD_STX_PPCL_DB_FAIL_STEP;
+ kal_int16 RXD_STX_PPCL_DB_TO_STEP;
+ kal_int32 RXD_STX_PPCL_DB_T_RELAX_D;
+ kal_int32 RXD_STX_PPCL_DB_T_RELAX_I;
+#endif /* __2G_RX_DIVERSITY_PATH_SUPPORT__ */
+} TASPrivateParams;
+#endif /* __MD93__ */
+
+#if (defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+
+ #if (defined(__MD97__) || defined(__MD97P__))
+ typedef struct
+ {
+ kal_uint32 freq;
+ MMRFD_ANT_TUNER_CONFIG_SETTING_IDX_E ant_tuner_config_setting_idx;
+ #if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__)
+ MMRFD_DAT_CONFIG_INDEX_E ant_dat_config_index;
+ #endif
+ }L1D_TAS_SPLIT_CONFIG_T;
+
+ typedef struct
+ {
+ kal_uint8 L1D_TAS_RX_SPLIT_NUM; /* 0: off 1: enable TAS feature */
+ L1D_TAS_SPLIT_CONFIG_T L1D_TAS_RX_SPLIT_PART[L1D_MAX_SPLIT_NUM]; /* Real SIM Default antenna */
+ kal_uint8 L1D_TAS_TX_SPLIT_NUM; /* 0: off 1: enable TAS feature */
+ L1D_TAS_SPLIT_CONFIG_T L1D_TAS_TX_SPLIT_PART[L1D_MAX_SPLIT_NUM]; /* Real SIM Default antenna */
+ }L1D_CUSTOM_TAS_SPLIT_CONFIG_T;
+
+ typedef struct
+ {
+ MMRFD_ANT_TUNER_CONFIG_SETTING_IDX_E rx_ant_tuner_config_setting_idx;
+ MMRFD_ANT_TUNER_CONFIG_SETTING_IDX_E tx_ant_tuner_config_setting_idx;
+ #if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__)
+ MMRFD_DAT_CONFIG_INDEX_E rx_ant_dat_config_index;
+ MMRFD_DAT_CONFIG_INDEX_E tx_ant_dat_config_index;
+ #endif
+ }L1D_CUSTOM_TAS_SINGLE_CONFIG_T;
+
+ typedef struct
+ {
+ L1D_CUSTOM_TAS_SPLIT_CONFIG_T l1d_custom_tas_split_database[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SINGLE_CONFIG_T l1d_custom_tas_single_database[FrequencyBandCount];
+ }L1D_CUSTOM_SPLIT_BAND_SETTING_T;
+
+ typedef struct
+ {
+ /*Since GL1C needed TAS by band parameters, we are using global variable for passing the parameters to GL1C*/
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_REAL_SIM_TAS_ENABLE; /* 0: off 1: enable TAS feature */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_REAL_SIM_TX_INIT_SETTING; /* Real SIM Default antenna for TX */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_REAL_SIM_RX_INIT_SETTING; /* Real SIM Default antenna for RX */
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TEST_SIM_TAS_ENABLE; /* 0: off 1: enable TAS feature */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_TEST_SIM_TX_INIT_SETTING; /* Test SIM Default antenna for TX */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_TEST_SIM_RX_INIT_SETTING; /* Test SIM Default antenna for RX */
+ kal_uint32 L1_TAS_LAYOUT_GROUP_IDX;
+ MMRFD_ANT_FE_SWITCH_NW_GROUP_E L1_TAS_SWITCH_NW_GROUP_IDX; /* switch network group idx for accessing scheme table and getting switch settings from MMRF*/
+ }L1CD_UTAS_BY_BAND_PARAMS;
+
+ typedef struct
+ {
+ L1CD_UTAS_BY_BAND_PARAMS UTAS_BY_BAND_SETTING[FrequencyBandCount];
+ }L1CD_UTAS_BY_BAND_PARAMS_T;
+ #endif
+
+ #if defined(__MD95__)
+ typedef struct
+ {
+ ARFCN arfcn;
+ MMRFD_ANT_TUNER_CONFIG_SETTING_IDX_E ant_tuner_config_setting_idx;
+ }L1D_TAS_SPLIT_CONFIG_T;
+
+ typedef struct
+ {
+ kal_uint8 L1D_TAS_RX_SPLIT_NUM; /* 0: off 1: enable TAS feature */
+ L1D_TAS_SPLIT_CONFIG_T L1D_TAS_RX_SPLIT_PART[L1D_MAX_SPLIT_NUM]; /* Real SIM Default antenna */
+ kal_uint8 L1D_TAS_TX_SPLIT_NUM; /* 0: off 1: enable TAS feature */
+ L1D_TAS_SPLIT_CONFIG_T L1D_TAS_TX_SPLIT_PART[L1D_MAX_SPLIT_NUM]; /* Real SIM Default antenna */
+ }L1D_CUSTOM_TAS_SPLIT_CONFIG_T;
+ #endif
+
+typedef struct
+{
+ #if (defined(__MD97__) || defined(__MD97P__))
+ /* TAS by band params are maintained by MMRF on Gen97, So we are removing TAS by band params from TAS NVRAM LID */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_CALIBRATION_TX_INIT_SETTING; /* Calibration Default antenna state for tx */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_CALIBRATION_RX_INIT_SETTING; /* Calibration Default antenna state for rx */
+ #else
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_REAL_SIM_TAS_ENABLE; /* 0: off 1: enable TAS feature */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_REAL_SIM_INIT_SETTING; /* Real SIM Default antenna */
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TEST_SIM_TAS_ENABLE; /* 0: off 1: enable TAS feature */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_TEST_SIM_INIT_SETTING; /* Test SIM Default antenna */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_CALIBRATION_INIT_SETTING; /* Calibration Default antenna state */
+ kal_uint32 L1_TAS_LAYOUT_GROUP_IDX;
+ #endif
+}L1D_CUSTOM_TAS_SB_OPTION_T;
+
+typedef struct
+{
+ ARFCN arfcn;
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_FORCE_TX_INIT_SETTING;
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_FORCE_RX_INIT_SETTING;
+}L1D_CUSTOM_TAS_FORCE_SETTING_PER_SUBBAND_T;
+
+typedef struct
+{
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_FORCE_RXTX_ENABLE_BY_BAND;
+ L1D_CUSTOM_TAS_FORCE_SETTING_PER_SUBBAND_T L1_TAS_FORCE_SETTING_PER_SUBBAND[L1D_MAX_FORCE_RXTX_SUBBAND_NUM];
+}L1D_CUSTOM_TAS_FORCE_SETTING_T;
+
+typedef struct UTAS_1RX_PublicParams
+{
+ /* Timeout thresholds */
+ kal_int16 L1_1RX_TIMEOUT_HIGH_QUAL_THD;
+ kal_int16 L1_1RX_TIMEOUT_LOW_QUAL_THD;
+ kal_int32 L1_1RX_TIMEOUT_LONG_COUNT_THD;
+ kal_int32 L1_1RX_TIMEOUT_SHORT_COUNT_THD;
+
+ /* adaptive threshold control */
+ kal_int32 L1_1RX_tSTEP;
+ kal_int32 L1_1RX_tBOUND;
+
+ /* Event trigger parameters */
+ kal_int32 L1_1RX_N_CB;
+ kal_int16 L1_1RX_EVENT_LOW_QUAL_THD;
+ kal_int16 L1_1RX_EVENT_RXLEV_CB_THD;
+ kal_int16 L1_1RX_EVENT_HR_ABS_THD;
+
+ /* Dynamic barrier control */
+ kal_bool L1_1RX_RXLEV_FLAG_DB;
+ kal_int16 L1_1RX_RXLEV_DB_L_BOUND;
+ kal_int16 L1_1RX_RXLEV_DB_U_BOUND;
+ kal_int16 L1_1RX_RXLEV_DB_FAIL_STEP;
+ kal_int16 L1_1RX_RXLEV_DB_TO_STEP;
+ kal_int32 L1_1RX_RXLEV_DB_T_RELAX;
+
+ kal_bool L1_1RX_HR_FLAG_DB;
+ kal_int16 L1_1RX_HR_DB_L_BOUND;
+ kal_int16 L1_1RX_HR_DB_U_BOUND;
+ kal_int16 L1_1RX_HR_DB_FAIL_STEP;
+ kal_int16 L1_1RX_HR_DB_TO_STEP;
+ kal_int32 L1_1RX_HR_DB_T_RELAX;
+
+ /* Switch back thresholds */
+ kal_uint8 L1_1Rx_SB_SNR_BLOCK;
+ // kal_int32 L1_1RX_SB_N_PRE_SWT;
+ kal_int16 L1_1RX_SB_RXLEV_PRE_SWT_THD;
+ kal_int16 L1_1RX_SB_HR_ABS_THD;
+ kal_int16 L1_1RX_SB_PCL_CB_PRE_SWT_THD;
+ kal_int16 L1_1RX_SB_PCL_RXLEV_CB_PRE_SWT_THD;
+
+} UTAS_1RX_PublicParams;
+
+typedef struct UTAS_RXD_STxPublicParams
+{
+ /* Switch over thresholds */
+ kal_int8 L1_RXD_STX_SO_PHR_ABS_THD;
+ kal_int8 L1_RXD_STX_SO_PPCL_GAIN_THD;
+ kal_int8 L1_RXD_STX_SO_PHR_GAIN_THD;
+
+ /* Switch Back thresholds */
+ kal_int32 L1_RXD_STX_SB_N_PRE_SWT;
+ kal_int16 L1_RXD_STX_SB_PCL_CB_PRE_SWT_THD;
+ kal_int16 L1_RXD_STX_SB_HR_CB_PRE_SWT_THD;
+ kal_int16 L1_RXD_STX_SB_PCL_RXLEV_CB_PRE_SWT_THD;
+
+ /* Dynamic barrier control */
+ kal_bool L1_RXD_STX_PHR_PPCL_FLAG_DB;
+ kal_int8 L1_RXD_STX_DB_L_BOUND;
+ kal_int8 L1_RXD_STX_DB_U_BOUND;
+ kal_int8 L1_RXD_STX_DB_FAIL_STEP;
+ kal_int8 L1_RXD_STX_DB_TO_STEP;
+ kal_int32 L1_RXD_STX_DB_T_RELAX;
+
+} UTAS_RXD_STxPublicParams;
+
+typedef struct UTAS_RXD_BTxPublicParams
+{
+ /* Switch over thresholds */
+ kal_int32 L1_RXD_BTX_EVENT_SO_N_CB;
+ kal_int16 L1_RXD_BTX_EVENT_SO_RXLEV_CB_THD;
+ kal_int16 L1_RXD_BTX_EVENT_SO_HR_ABS_THD;
+ kal_int16 L1_RXD_BTX_PERIOD_SO_RXLEV_THD;
+ kal_int32 L1_RXD_BTX_PERIOD_SO_t_BTX;
+ kal_int32 L1_RXD_BTX_PERIOD_SO_t_BTX_STEP;
+ kal_int32 L1_RXD_BTX_PERIOD_SO_t_BTX_BOUND;
+
+ /* Switch back thresholds */
+ kal_uint8 L1_RXD_BTX_S_SNR_BLOCK;
+ kal_int16 L1_RXD_BTX_SB_HR_ABS_THD;
+ kal_int16 L1_RXD_BTX_SB_RXLEV_CB_PRE_SWT_THD;
+ kal_int16 L1_RXD_BTX_SB_PCL_CB_PRE_SWT_THD;
+ kal_int16 L1_RXD_BTX_SB_PCL_RXLEV_CB_PRE_SWT_THD;
+
+ /* Dynamic barrier control */
+ kal_bool L1_RXD_BTX_RXLEV_FLAG_DB;
+ kal_int16 L1_RXD_BTX_RXLEV_DB_L_BOUND;
+ kal_int16 L1_RXD_BTX_RXLEV_DB_U_BOUND;
+ kal_int16 L1_RXD_BTX_RXLEV_DB_FAIL_STEP;
+ kal_int16 L1_RXD_BTX_RXLEV_DB_TO_STEP;
+ kal_int32 L1_RXD_BTX_RXLEV_DB_T_RELAX;
+
+ kal_bool L1_RXD_BTX_HR_FLAG_DB;
+ kal_int16 L1_RXD_BTX_HR_DB_L_BOUND;
+ kal_int16 L1_RXD_BTX_HR_DB_U_BOUND;
+ kal_int16 L1_RXD_BTX_HR_DB_FAIL_STEP;
+ kal_int16 L1_RXD_BTX_HR_DB_TO_STEP;
+ kal_int32 L1_RXD_BTX_HR_DB_T_RELAX;
+
+} UTAS_RXD_BTxPublicParams;
+
+typedef struct UTAS_RXD_BRxPublicParams
+{
+ /* Switch over thresholds */
+ kal_int32 L1_RXD_BRX_EVENT_SO_N_CB;
+ kal_int16 L1_RXD_BRX_EVENT_SO_LOW_QUAL_THD;
+ kal_int16 L1_RXD_BRX_EVENT_SO_RXLEV_CB_THD;
+ kal_uint16 L1_RXD_BRX_EVENT_SO_SNR_THD;
+
+ kal_int16 L1_RXD_BRX_PERIOD_SO_RXLEV_THD;
+ kal_int32 L1_RXD_BRX_PERIOD_SO_t_BRX;
+ kal_int32 L1_RXD_BRX_PERIOD_SO_t_BRX_STEP;
+ kal_int32 L1_RXD_BRX_PERIOD_SO_t_BRX_BOUND;
+
+ /* Switch back thresholds */
+ kal_uint8 L1_RXD_BRX_S_SNR_BLOCK;
+ kal_int32 L1_RXD_BRX_SB_N_PRE_SWT;
+ kal_int16 L1_RXD_BRX_SB_RXLEV_CB_PRE_SWT_THD;
+
+ /* Dynamic barrier control */
+ kal_bool L1_RXD_BRX_RXLEV_FLAG_DB;
+ kal_int16 L1_RXD_BRX_RXLEV_DB_L_BOUND;
+ kal_int16 L1_RXD_BRX_RXLEV_DB_U_BOUND;
+ kal_int16 L1_RXD_BRX_RXLEV_DB_FAIL_STEP;
+ kal_int16 L1_RXD_BRX_RXLEV_DB_TO_STEP;
+ kal_int32 L1_RXD_BRX_RXLEV_DB_T_RELAX;
+} UTAS_RXD_BRxPublicParams;
+
+#if (defined(__MD97__) || defined(__MD97P__))
+typedef struct UTAS_CommonPublicParams
+{
+ kal_int16 L1_TAS_PBO_LIMIT[MMRFD_MAX_ANT_SUPPORT_NUM]; /* Power-back off for maximum poewr reduction */
+ kal_int16 L1_TAS_RXLEV_BIAS[FrequencyBandCount][MMRFD_MAX_ANT_SUPPORT_NUM]; /* RxLev Bias for antenna imbalance */
+} UTAS_CommonPublicParams;
+#else
+typedef struct UTAS_CommonPublicParams
+{
+ kal_int16 L1_TAS_PBO_LIMIT[MMRFD_PHYSICAL_ANT_MAX_NUM]; /* Power-back off for maximum poewr reduction */
+ kal_int16 L1_TAS_RXLEV_BIAS[FrequencyBandCount][MMRFD_PHYSICAL_ANT_MAX_NUM]; /* RxLev Bias for antenna imbalance */
+} UTAS_CommonPublicParams;
+#endif
+
+typedef struct
+{
+ kal_int32 PERIOD_IDLE; /* Checking period of TAS criterion at idle mode */
+ kal_int32 PERIOD_DEDICATED; /* Checking period of TAS criterion at dedicated mode; unit: 208 frames */
+
+ UTAS_1RX_PublicParams gl1_1RX_PublicParams_I; /* Idle */
+ UTAS_1RX_PublicParams gl1_1RX_PublicParams_D; /* CS */
+
+ UTAS_RXD_STxPublicParams gl1_RXD_STxPublicParams_I; /* Idle */
+ UTAS_RXD_STxPublicParams gl1_RXD_STxPublicParams_D; /* CS */
+
+ UTAS_RXD_BTxPublicParams gl1_RXD_BTxPublicParams_I;
+ UTAS_RXD_BTxPublicParams gl1_RXD_BTxPublicParams_D;
+
+ UTAS_RXD_BRxPublicParams gl1_RXD_BRxPublicParams_I; /* Idle */
+ UTAS_RXD_BRxPublicParams gl1_RXD_BRxPublicParams_D; /* CS */
+
+ UTAS_CommonPublicParams gl1_CommonPublicParams;
+
+} UTASPublicParams;
+#endif
+
+typedef struct
+{
+#if (defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_FORCE_RXTX_ENABLE; /* 0: off 1: Don't change antenna */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_FORCE_TX_INIT_SETTING; /* The antenna which user forces to stay */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_FORCE_RX_INIT_SETTING; /* The antenna which user forces to stay */
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_ENABLE_ON_REAL_SIM; /* 0: off 1: enable TAS feature */
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_ENABLE_ON_TEST_SIM; /* 0: off 1: enable TAS feature */
+ L1D_CUSTOM_TAS_SB_OPTION_T L1_TAS_SB_OPTION[FrequencyBandCount]; /* */
+ L1D_CUSTOM_TAS_FORCE_SETTING_T L1_TAS_FORCE_SETTING[FrequencyBandCount];
+ UTASPublicParams L1_UTAS_THD_VALUES;
+#else
+ L1D_CUSTOM_TAS_VER_E L1_TAS_VERSION; /* TAS1.0 or TAS2.0 */
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_FORCE_ENABLE; /* 0: off 1: Don't change antenna */
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_FORCE_INIT_SETTING; /* The antenna which user forces to stay */
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_ENABLE_ON_REAL_SIM; /* 0: off 1: enable TS feature */
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_ENABLE_ON_TEST_SIM; /* 0: off 1: enable TS feature */
+ L1D_CUSTOM_TAS_NUM_STATES_E L1_TAS_STATE_NUM [FrequencyBandCount]; /* total antenna number for each band */
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_REAL_SIM_TAS_ENABLE [FrequencyBandCount];
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_REAL_SIM_INIT_SETTING [FrequencyBandCount]; /* Default antenna */
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TEST_SIM_TAS_ENABLE [FrequencyBandCount];
+ L1D_CUSTOM_TAS_STATE_E L1_TAS_TEST_SIM_INIT_SETTING [FrequencyBandCount]; /* Default antenna */
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ L1D_CUSTOM_RXD_THRESHOLD_T L1_RXD_THD_VALUES;
+ #endif /* __2G_RX_DIVERSITY_PATH_SUPPORT__ */
+#endif
+ }TASPublicParams;
+
+
+typedef struct
+{
+ kal_uint8 TAS_INIT_ANT_IDX[FrequencyBandCount];
+} TASInitANTParams;
+
+typedef TASPublicParams L1D_CUSTOM_TAS_NVRAM_T ;
+typedef TASPublicParams sL1_TAS_CUSTOM_PARAMS;
+
+#if defined (__MD93__)
+typedef TASPrivateParams sL1_TAS_LIB_PARAMS ;
+#endif /* __MD93__*/
+
+typedef enum
+{
+ L1D_DAT_STATE_NULL = -1,
+ L1D_DAT_STATE0,
+ L1D_DAT_STATE1,
+ L1D_DAT_STATE2,
+ L1D_DAT_STATE3,
+ L1D_DAT_STATE4,
+ L1D_DAT_STATE5,
+ L1D_DAT_STATE6,
+ L1D_DAT_STATE7,
+ L1D_DAT_STATE_NUM,
+}L1D_CUSTOM_DAT_STATE_E;
+
+#if defined(__MD95__)
+typedef struct
+{
+ MMRFD_CUSTOM_ANT_SWITCH_IDX_E switch_config_index;
+ MMRFD_CUSTOM_ANT_TUNER_IDX_E tuner_config_index;
+}L1D_DAT_SPLIT_CONFIG_STATE_T;
+typedef struct
+{
+ ARFCN arfcn;
+ L1D_DAT_SPLIT_CONFIG_STATE_T l1d_dat_split_config_state[L1D_DAT_MAX_STATE_NUM];
+}L1D_DAT_SPLIT_CONFIG_T;
+
+typedef struct
+{
+ kal_uint8 L1D_DAT_RX_SPLIT_NUM; /* 0: off 1: enable DAT feature */
+ L1D_DAT_SPLIT_CONFIG_T L1D_DAT_RX_SPLIT_PART[L1D_MAX_SPLIT_NUM]; /* Real SIM Default antenna */
+ kal_uint8 L1D_DAT_TX_SPLIT_NUM; /* 0: off 1: enable DAT feature */
+ L1D_DAT_SPLIT_CONFIG_T L1D_DAT_TX_SPLIT_PART[L1D_MAX_SPLIT_NUM]; /* Real SIM Default antenna */
+}L1D_CUSTOM_DAT_SPLIT_CONFIG_T;
+
+#endif
+
+//NVRAM related feature (custom file)do not follow defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) to prevent structure change
+//#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+typedef enum
+{
+ RXD_MODE_CROSS_MASK =0x10, //(CROSS Mask bit for cross mode)
+ RXD_MODE_OBB_MASK =0x20,
+
+ /*Following 3 enum can be apply to BFE setting and SW control*/
+ RXD_MODE_LEGACY =0x0, //(LEGACY/SA :RX and TX are at primary, only can apply when RxD disable and FB/SB/PKT)
+ RXD_MODE_1RX_DESENSE =0x1, //(1RX_DESENSE :Two RF path ON for AGC power but only PRX is uesd in data)
+ RXD_MODE_RXD =0x3, //(RXD :Two RF path ON, P-ANT to BFE PRX and D-ANT to BFE DRX )
+
+#if (defined(__MD97__) || defined(__MD97P__))
+ RXD_MODE_OBB =(RXD_MODE_OBB_MASK|RXD_MODE_1RX_DESENSE), //(RXD_MODE_OBB)
+ RXD_MODE_DISABLE =RXD_MODE_LEGACY, //(RXD_Disable = RXD_Legacy}
+#else
+ RXD_MODE_OBB =(RXD_MODE_OBB_MASK|RXD_MODE_LEGACY), //(RXD_MODE_OBB)
+ RXD_MODE_DISABLE =RXD_MODE_OBB, //(RXD_Disable = RXD_MODE_OBB)
+#endif
+
+ /*Below enum only apply for SW only , for cross case */
+ RXD_MODE_1RX_DESENSE_CROSS =(RXD_MODE_CROSS_MASK|RXD_MODE_1RX_DESENSE), //(1RX_DESENSE CROSS :Two RF path ON for AGC power but only DRX is uesd in data)
+ RXD_MODE_RXD_CROSS =(RXD_MODE_CROSS_MASK|RXD_MODE_RXD), //(RXD CROSS :Two RF path ON , D-ANT to BFE PRX and P-ANT to BFE DRX )
+
+ /*Below enum only apply for SW only, GL1C free runing */
+ RXD_MODE_RAS =0x5, //(RAS :MODE CHANGE BY GL1C NOTE:This enum only used by GL1C )
+}L1D_RXD_MODE;
+
+
+#define CHECK_RXD_MODE_CROSS_MASK(v) (((v)&(RXD_MODE_CROSS_MASK))==RXD_MODE_CROSS_MASK)
+#define EXCLUDE_RXD_MODE_CROSS_MASK(v) ((~RXD_MODE_CROSS_MASK)&(v))
+#define CHECK_RXD_MODE_OBB_MASK(v) (((v)&(RXD_MODE_OBB_MASK))==RXD_MODE_OBB_MASK)
+#define EXCLUDE_RXD_MODE_OBB_MASK(v) ((~RXD_MODE_OBB_MASK)&(v))
+#define EXCLUDE_RXD_MODE_ALL_MASK(v) ((~(RXD_MODE_OBB_MASK|RXD_MODE_CROSS_MASK))&(v))
+
+
+typedef enum
+{
+ L1D_RAS_MODE =RXD_MODE_RAS, //(RAS:MODE CHANGE BY GL1C) NOTE:This enum only used by GL1C (excluding AGC)
+
+ /*Below enum only apply for custom force mode*/
+ L1D_FORCE_RXD_MODE =RXD_MODE_RXD, //(RXD :Two RF path ON)
+ L1D_FORCE_P_PATH_ONLY =RXD_MODE_1RX_DESENSE, //(1RX_DESENSE :Two RF path ON for AGC power but only PRX is uesd in data)
+ L1D_FORCE_D_PATH_ONLY =RXD_MODE_1RX_DESENSE_CROSS, //(1RX_DESENSE Cross :RX is at diversity, TX is at primary) NOTE:This enum only used in RF, BPI and MIPI.(excluding AGC)
+}L1D_CUSTOM_RXD_MODE;
+
+
+#define L1D_RXD_MODE_LEGACY_CROSS (RXD_MODE_LEGACY|RXD_MODE_CROSS_MASK)
+#define L1D_RXD_MODE_FSI (RXD_MODE_LEGACY)
+#define L1D_RXD_MODE_FSI_CROSS (L1D_RXD_MODE_LEGACY_CROSS)
+#define L1D_RXD_MODE_PM (RXD_MODE_RXD) //test for ARX please use RXD_MODE_LEGACY
+#define L1D_RXD_MODE_RX_NOT_GSM (RXD_MODE_LEGACY) //RXD_MODE_RXD only in single slot
+#define L1D_RXD_MODE_PKT (RXD_MODE_LEGACY) //RXD_MODE_RXD only in single slot
+#define L1D_RXD_MODE_PKT_CROSS (L1D_RXD_MODE_LEGACY_CROSS)
+
+#define L1D_RXD_RFIC_GGE_PATH KAL_TRUE
+#define L1D_RXD_RFIC_LTE_PATH KAL_FALSE
+
+
+typedef enum
+{
+ L1D_RX_PATH_OFF,
+ L1D_RX_PATH_ON,
+}L1D_RX_PATH_ENABLE_E;
+
+typedef enum
+{
+ L1D_RXD_DISABLE,
+ L1D_RXD_ENABLE,
+}L1D_RXD_EN;
+
+#if IS_2G_RXD_BLACKLIST_SUPPORT
+#define BLACKLIST_ARFCN_COUNT 32
+
+typedef enum
+{
+ L1D_BLACKLIST_BAND_DISABLE,
+ L1D_BLACKLIST_BAND_ENABLE,
+}L1D_BLACKLIST_BAND_E;
+#endif /* IS_2G_RXD_BLACKLIST_SUPPORT */
+
+typedef enum
+{
+ L1D_RX_PRX,
+ L1D_RX_DRX,
+ L1D_RX_NUM,
+}L1D_RX_PATH_E;
+
+typedef enum
+{
+ L1D_RX_PATH_MASK_NULL = 0x0,
+ L1D_RX_PATH_MASK_PRX = 0x1,
+ L1D_RX_PATH_MASK_DRX = 0x2,
+}L1D_RX_PATH_MASK_E;
+
+#if (defined(__MD97__) || defined(__MD97P__))
+typedef struct
+{
+ kal_uint32 PRX;
+ kal_uint32 DRX;
+ kal_uint32 PRX_2;
+ kal_uint32 DRX_2;
+} L1D_RX_PATH;
+
+typedef struct
+{
+ kal_uint32 PRX;
+ kal_uint32 DRX;
+} L1D_TX_PATH;
+
+#else
+typedef struct
+{
+ unsigned int PRX;
+ unsigned int DRX;
+} L1D_RX_PATH;
+#endif
+
+typedef struct
+{
+ Power PRX; /* in 0.125 dBm */
+ Power DRX; /* in 0.125 dBm */
+} L1D_RX_POWER;
+
+typedef struct
+{
+ Gain PRX; /* in 0.125 dB *//* !!important: please update the copy in m12194.c */
+ Gain DRX; /* in 0.125 dB *//* !!important: please update the copy in m12194.c */
+} L1D_RX_GAIN;
+
+typedef struct
+{
+ uint32 PRX; /* Code Word for RF*/
+ uint32 DRX; /* Code Word for RF*/
+} L1D_RX_SETTING;
+
+typedef struct
+{
+ int PRX;
+ int DRX;
+} L1D_RX_ELNA_TYPE;
+
+typedef struct
+{
+ Gain PRX;
+ Gain DRX;
+} L1D_RX_PATHLOSS;
+
+typedef struct
+{
+ short PRX;
+ short DRX;
+} L1D_RX_RANGE_ERROR;
+
+typedef enum
+{
+ BFE_RXSWAP_PARALLEL,
+ BFE_RXSWAP_CROSS,
+} L1D_BFE_MUX_SETTING;
+
+typedef struct
+{
+ L1D_RXD_EN RXD_ENABLE[FrequencyBandCount]; /* RxD enable flag by band */
+ L1D_CUSTOM_RXD_MODE RXD_MODE; /* RxD mode, by RAS or forced mode */
+ kal_int32 C1_P_THD_HIGH_RXLEV;
+ kal_int16 C1_THD_HIGH_RXLEV; /* C1 threshold for 1 Rx de-sense detection; if rxlev < C1, go to sub-rxd */
+ kal_int16 C1_THD_LOW_RXLEV; /* C1 threshold for 1 Rx de-sense detection; if rxlev < C1, go to sub-rxd */
+ kal_int16 C1_P_D_THD_RXLEV_DIFF;
+ kal_int16 C2_THD_RXLEV; /* C2 rxlev threshold */
+ kal_uint16 C2_THD_TSCSNR; /* C2 tscsnr threshold */
+ kal_uint32 C2_THD_PRESNR; /* C2 presnr threshold; if all C2 criterion are met, go to single antenna */
+ kal_uint16 C3_THD_OBB_DEDICATED; /* C3 OBB detection threshold; if accumulate OBB detected during one period, go to sub-rxd */
+ kal_uint16 C3_THD_OBB_IDLE; /* C3 OBB detection threshold; if accumulate OBB detected during one period, go to sub-rxd */
+ kal_int16 RXD_THD_RXLEV_DIFF; /* */
+ kal_int32 PERIOD_IDLE; /* RAS check period in idle mode (frame) */
+ kal_int32 PERIOD_DEDICATED; /* RAS check period in dedi mode (frame)*/
+ kal_int32 OBB_PERIOD_DEDICATED; /* RAS check period in dedi mode (frame)*/
+ #if IS_2G_RAS_DECISION_INCLUDE_DSP_POW_SUPPORT
+ kal_int32 C1_THD_RLV_PROTECT;
+ kal_int32 C1_THD_DSP_POW_PROTECT;
+ kal_int32 C1_THD_RLV_DSP_POW_PROTECT;
+ #endif /* IS_2G_RAS_DECISION_INCLUDE_DSP_POW_SUPPORT */
+ #if IS_2G_C_VALUE_SUPPORT
+ kal_int16 C1_THD_CVALUE_L;
+ kal_int16 C1_THD_CVALUE_H;
+ #endif
+ #if IS_2G_RXD_BLACKLIST_SUPPORT
+ L1D_BLACKLIST_BAND_E BLACKLIST_ENABLE[FrequencyBandCount]; /* Enable band to be blacklisted */
+ ARFCN BLACKLIST_ARFCN[BLACKLIST_ARFCN_COUNT]; /* ARFCN list to be blacklisted */
+ #endif /* IS_2G_RXD_BLACKLIST_SUPPORT */
+} RASPublicParams;
+
+#define GL1_RASPUBLICPARAMS_VERSION 0x0001
+
+typedef RASPublicParams L1D_CUSTOM_RAS_NVRAM_T ;
+
+//#endif /* #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) */
+
+typedef enum
+{
+ CONT_TX_ALL_ZEROS
+ ,CONT_TX_ALL_ONES
+ ,CONT_TX_ALTERNATE_BITS
+ ,CONT_TX_PSEUDO_RANDOM
+ ,CONT_TX_PATTERN_WITHOUT_TSC
+} ContTxPattern;
+
+typedef enum
+{
+ AB_TX_RANDOM_WITH_SYNC_SEQ
+ ,NB_TX_ALL_ZEROS_WITHOUT_TSC
+ ,NB_TX_ALL_ONES_WITHOUT_TSC
+ ,NB_TX_ALTER_BITS_WITHOUT_TSC
+ ,NB_TX_RANDOM_WITH_TSC
+ ,NB_TX_PATTERN_WITHOUT_TSC
+ ,NB_TX_FIXED_RANDOM_WITH_TSC
+ ,NB_TX_FIXED_ALL_ZEROS_WITH_TSC
+ ,NB_TX_FIXED_ALTER_BITS_WITH_TSC
+ ,NB_TX_FIXED_ALL_ONES_WITH_TSC
+ ,NB_TX_FIXED_OE_PATTERN_WITH_TSC
+} APCTxPattern;
+
+/*****************************************************************************************************
+For platform after Gen95, define struct/enum for antenna related feature such as RxD/UTAS/RAS : Temporary change
+*****************************************************************************************************/
+
+#if (defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)) /*Need to change when we need to support differently for gen97*/
+/* contain info to indicate how antenna is configured */
+typedef struct GL1_AntennaInfo
+{
+ //use global option of UTAS
+ AntennaStatus antenna_state_tx; //will be announced by MMRF ant mapping table
+ AntennaStatus antenna_state_rx; //will be announced by MMRF ant mapping table
+ MMRFD_ANT_INDEX_TYPE_E gl1_phy_ant_idx_tx;
+ //use global option of RXD
+ uint8 rxd_mode; /* 0: single antenna; 1: sub-rxd; 3: rxd; 2 is reserved */
+}GL1_AntennaInfo;
+
+typedef struct
+{
+ kal_int32 UTAS_PERIOD_IDLE; /* Checking period of UTAS criterion at idle mode */
+ kal_int32 UTAS_PERIOD_DEDICATED; /* Checking period of UTAS criterion at dedicated mode; unit: 208 frames */
+}UTASPrivateParams;
+
+typedef UTASPrivateParams sL1_UTAS_LIB_PARAMS ;
+
+#endif
+
+ #if defined(__GSM_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT__)
+#define L1D_RF_INTERFERENCE_ARFCN_INDICATION_SET_NUM 16
+#define L1D_RF_INTERFERENCE_ARFCN_INDICATION_TABLE_NUM 6
+#define ARFCN_EMPTY -1
+
+typedef struct
+{
+ ARFCN interference_arfcn_start;
+ ARFCN interference_arfcn_end;
+} L1D_RF_INTERFERENCE_ARFCN_INDICATION_SET_T;
+
+typedef struct
+{
+ L1D_RF_INTERFERENCE_ARFCN_INDICATION_SET_T interference_arfcn_table_a[L1D_RF_INTERFERENCE_ARFCN_INDICATION_SET_NUM];
+ L1D_RF_INTERFERENCE_ARFCN_INDICATION_SET_T interference_arfcn_table_b[L1D_RF_INTERFERENCE_ARFCN_INDICATION_SET_NUM];
+} L1D_RF_INTERFERENCE_ARFCN_INDICATION_TABLE_T;
+
+typedef struct
+{
+ kal_uint8 table_enable_mask;
+ L1D_RF_INTERFERENCE_ARFCN_INDICATION_TABLE_T interference_arfcn_table[L1D_RF_INTERFERENCE_ARFCN_INDICATION_TABLE_NUM];
+} L1D_RF_INTERFERENCE_ARFCN_INDICATION_T;
+ #endif
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1cal.h b/mcu/interface/l1/gl1/external/l1cal.h
new file mode 100644
index 0000000..f6f2e34
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1cal.h
@@ -0,0 +1,2389 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1cal.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * The structure definition of L1 calibration data
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+#ifndef L1CAL_H
+#define L1CAL_H
+
+#include "kal_general_types.h"
+#include "l1_option.h"
+#include "l1_types_public.h"
+ #if MD_DRV_IS_2G_MIPI_SUPPORT
+#include "l1d_mipi_data_common.h"
+ #endif
+#include "l1d_rf_data_common.h"
+ #include "l1_public_defs.h"
+#if defined(__TAS_SUPPORT__)
+#include "l1_types_public.h"
+ #if (defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+#include "l1d_rf_utas_typedef.h"
+ #else
+#include "l1d_rf_tas_typedef.h"
+ #endif
+#endif
+#if MD_DRV_IS_TX_POWER_OFFSET_SUPPORT
+#include "mmrf_cc_global.h"
+#endif
+
+#if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__)
+#include "l1_types_public.h"
+#include "l1d_rf_dat_typedef.h"
+#endif//__DYNAMIC_ANTENNA_TUNING__
+/* ------------------------------------------------------------------------- */
+
+unsigned long L1D_RF_GetID( void );
+void L1D_RF_SetImmediateBSI( unsigned long bsidata );
+void L1D_RF_GetImmediateBSI( unsigned long bsi_addr, unsigned long *bsi_data );
+void L1D_RF_PowerOn( void );
+void L1D_RF_PowerOff( void );
+
+/* ------------------------------------------------------------------------- */
+
+typedef struct
+{
+ signed short status;
+ signed short tadc_dac;
+ signed short temperature;
+ signed short temp_idx;
+}L1D_TEMPINFO_T;
+void L1D_RF_GetTemperatureInfo(L1D_TEMPINFO_T* tempinfo);
+
+/* ------------------------------------------------------------------------- */
+
+/*
+This enum has been move to l1_public_defs.h for proper location
+#ifndef l1_types_public_h
+typedef enum
+{
+ FrequencyBand400,
+ FrequencyBand850,
+ FrequencyBand900,
+ FrequencyBand1800,
+ FrequencyBand1900,
+
+ FrequencyBandCount
+
+} FrequencyBand;
+#endif
+*/
+
+#define PLTABLE_SIZE (13)
+
+typedef struct
+{
+ short max_arfcn;
+ signed char gain_offset;
+
+} sAGCGAINOFFSET;
+
+typedef struct
+{
+ sAGCGAINOFFSET agcPathLoss[FrequencyBandCount][PLTABLE_SIZE];
+}l1cal_agcPathLoss_T;
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+typedef enum
+{
+ L1D_LNA_HIGH_SENSITIVITY, //elna+g6
+ L1D_LNA_HIGH,
+ L1D_LNA_MIDDLE,
+ L1D_LNA_LOW,
+ L1D_LNA_LOW_MAXPIN, //elna_bypass+g1
+} L1D_LNA_TYPE_E;
+#endif
+
+#if IS_GSM_TX_DETECTOR_SUPPORT
+typedef enum
+{
+ L1D_TXD_DISABLE,
+ L1D_TXD_ENABLE,
+} L1D_TXD_E;
+#endif
+
+
+typedef struct
+{
+ signed char gain_offset_middle;
+ signed char gain_offset_middle_sawless;
+ signed char gain_offset_low;
+ signed char gain_offset_high_sensitivity; //elna+g6
+ signed char gain_offset_low_maxpin; //elna_bypass+g1
+} sLNAGAINOFFSET;
+
+typedef struct
+{
+ sLNAGAINOFFSET lnaPathLoss[FrequencyBandCount][PLTABLE_SIZE];
+} sLNAPATHLOSS_L1CAL;
+
+typedef sLNAPATHLOSS_L1CAL l1cal_lnaPathLoss_T;
+
+void L1D_RF_SetPathLossTable( int rf_band, void *table );
+#if defined(__RX_POWER_OFFSET_SUPPORT__)
+void L1D_RF_SetPathLoss_Offset_Table( int rf_band, void *table );
+void L1D_RF_GetPathLoss_Offset_Table( int rf_band, void *table );
+#endif
+
+void L1D_RF_SetLnaPathLossTable( sLNAPATHLOSS_L1CAL *table );
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+void L1D_RF_GetPathLossTable( int rf_band, void *table );
+#endif
+void L1D_RF_GetLnaPathLossTable( sLNAPATHLOSS_L1CAL *table );
+
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+void L1D_RF_SetPathLossTable_RXD( int rf_band, void *table );
+void L1D_RF_SetPathLoss_Offset_Table_RXD( int rf_band, void *table );
+void L1D_RF_SetLnaPathLossTable_RXD( sLNAPATHLOSS_L1CAL *table );
+
+void L1D_RF_GetPathLossTable_RXD( int rf_band, void *table );
+void L1D_RF_GetPathLoss_Offset_Table_RXD( int rf_band, void *table );
+void L1D_RF_GetLnaPathLossTable_RXD( sLNAPATHLOSS_L1CAL *table );
+#endif
+
+
+/* ------------------------------------------------------------------------- */
+/*****************************************************************************/
+/***************************RX Power Offset Begin*******************************/
+/*****************************************************************************/
+#if defined(__RX_POWER_OFFSET_SUPPORT__)
+typedef struct
+{
+ short max_arfcn;
+ signed char gain_offset;
+ #if defined(__MULTI_LNA_MODE_CALIBRATION_SUPPORT__)
+ signed char gain_offset_middle;
+ signed char gain_offset_low;
+ #endif
+} sAGCLNAGAINOFFSET;
+
+typedef struct
+{
+ sAGCLNAGAINOFFSET agcPathLoss[FrequencyBandCount][PLTABLE_SIZE];
+}l1cal_agclnaPathLoss_T;
+
+
+typedef struct
+{
+ sAGCLNAGAINOFFSET* agcPathLoss[FrequencyBandCount];
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ sAGCLNAGAINOFFSET* agcPathLoss_RXD[FrequencyBandCount];
+ #endif
+}sL1D_AGCLNA_Gain_Offset_Data;
+
+#endif/*__RX_POWER_OFFSET_SUPPORT__*/
+
+
+/*****************************************************************************/
+/***************************RX Power Offset End*********************************/
+/*****************************************************************************/
+
+#if defined(__ANT_RXPWR_OFFSET_SUPPORT__)
+typedef struct
+{
+ kal_int16 arfcn;
+ kal_int16 threshold;
+ kal_int16 offset;
+
+}sANTENNARXPWROFFSET_DATA;
+
+typedef struct
+{
+ kal_uint32 pcell_id;
+ sANTENNARXPWROFFSET_DATA arfcn_list[PLTABLE_SIZE];
+
+}sANTENNARXPWROFFSET_PLIST;
+
+typedef struct
+{
+ kal_bool is_enable;
+ sANTENNARXPWROFFSET_PLIST pcell_list[PLTABLE_SIZE];
+
+}sL1D_ANT_RxPWR_Offset_T;
+#endif
+
+/*****************************************************************************/
+
+#define PROFILE_NUM 16
+#define ARFCN_SECTION_NUM 12
+
+typedef struct
+{
+ unsigned char point[2][16];
+
+} sRAMPAREADATA;
+
+typedef struct
+{
+ signed short max_arfcn;
+ unsigned short mid_level;
+ unsigned short hi_weight;
+ unsigned short low_weight;
+
+} sARFCN_SECTION;
+
+typedef struct
+{
+ signed long lowest_power;
+ unsigned short power[16];
+ sRAMPAREADATA ramp[ PROFILE_NUM ];
+ sARFCN_SECTION arfcn_weight[ ARFCN_SECTION_NUM ];
+ #if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT
+ unsigned short battery_compensate[5/*volt*/][5/*temp*/];
+ #else
+ unsigned short battery_compensate[3/*volt*/][3/*temp*/];
+ #endif
+} sRAMPDATA;
+
+typedef struct
+{
+ sRAMPDATA rampData;
+}l1cal_rampTable_T;
+
+void L1D_RF_SetRampTable( int rf_band, void *table );
+#if MD_DRV_IS_TX_POWER_OFFSET_SUPPORT
+void L1D_RF_SetTxPowerOffsetData_GMSK( int rf_band, void *table );
+ #if MD_DRV_IS_EPSK_TX_SUPPORT
+void L1D_RF_SetTxPowerOffsetData_EPSK( int rf_band, void *table );
+ #endif
+#endif // IS_TX_POWER_OFFSET_SUPPORT
+#if MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT
+void L1D_RF_SetAdjustTPOData_GMSK( int rf_band, void *table );
+ #if MD_DRV_IS_EPSK_TX_SUPPORT
+void L1D_RF_SetAdjustTPOData_EPSK( int rf_band, void *table );
+ #endif
+#endif // __NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__
+
+unsigned long L1D_RF_GetITC_PCL(void);
+
+#if MD_DRV_IS_EPSK_TX_SUPPORT
+void L1D_RF_SetRampTableEPSK( int rf_band, void *table );
+void L1D_RF_SetPAGainTable( int rf_band, void *table );
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+typedef struct
+{
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint32 dacValue;
+#else
+ kal_uint16 dacValue;
+#endif /* IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT */
+ kal_int32 slopeInv;
+}l1cal_afcData_T;
+
+void L1D_RF_SetCrystalAFCData( void *table );
+void L1D_RF_SetCrystalCap( int cap_no );
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+void L1D_RF_SetCrystalDac( int32 dacValue );
+#else
+void L1D_RF_SetCrystalDac( short dacValue );
+#endif /* IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT */
+
+/* ------------------------------------------------------------------------- */
+
+typedef struct
+{
+ kal_int16 filter_coefficient[60];
+}l1spfc_T;
+
+/* ------------------------------------------------------------------------- */
+
+typedef struct
+{
+ unsigned char bbtx_common_mode_voltage;
+ unsigned char bbtx_gain;
+ unsigned char bbtx_calrcsel;
+ unsigned char bbtx_trimI; // need to set
+ unsigned char bbtx_trimQ; // need to set
+ unsigned char bbtx_dccoarseI; // need to set
+ unsigned char bbtx_dccoarseQ; // need to set
+ unsigned char bbtx_offsetI; // need to set
+ unsigned char bbtx_offsetQ; // need to set
+ unsigned char bbtx_isCalibrated; // need to set
+ #if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT
+ int apc_bat_voltage_threshold[4];
+ int apc_bat_temperature_threshold[4];
+ #else
+ int apc_bat_low_voltage;
+ int apc_bat_high_voltage;
+ int apc_bat_low_temperature;
+ int apc_bat_high_temperature;
+ #endif
+ int ap_update_volinfo_period;
+ unsigned char bbtx_common_mode_voltage_h;
+ unsigned char bbtx_gain_h;
+ unsigned char bbtx_calrcsel_h;
+ unsigned char bbtx_trimI_h;
+ unsigned char bbtx_trimQ_h;
+ unsigned char bbtx_dccoarseI_h;
+ unsigned char bbtx_dccoarseQ_h;
+ unsigned char bbtx_offsetI_h;
+ unsigned char bbtx_offsetQ_h;
+ unsigned char bbtx_phsel;
+ unsigned char bbtx_phsel_h;
+ unsigned char bbrx_gsm850_gsm900_swap;
+ unsigned char bbrx_dcs1800_pcs1900_swap;
+} sBBTXParameters;
+
+typedef struct
+{
+ sBBTXParameters BBTXParameters;
+}l1cal_txiq_T;
+
+
+typedef unsigned char sMIDRAMPDATA[16];
+
+
+void L1D_RF_SetInterSlotRampTable( int rf_band, void *table );
+
+#if MD_DRV_IS_EPSK_TX_SUPPORT
+void L1D_RF_EPSK_SetInterSlotRampTable( int rf_band, int _8G_mode, void *table );
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+typedef struct
+{
+ kal_uint8 interRampData[16];
+}l1cal_interRampData_T;
+
+#define InterRampData_count 4
+/* ------------------------------------------------------------------------- */
+
+#if MD_DRV_IS_EPSK_TX_SUPPORT
+typedef struct
+{
+ kal_uint8 EPSK_interRampData[4][16];
+}l1cal_EPSK_interRampData_T;
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#if MD_DRV_IS_VCXO_LC_SUPPORT
+#define XO_SlopeArea_Num 33
+#else
+#define XO_SlopeArea_Num 4
+#endif
+
+typedef struct
+{
+ long min_freq;
+ short min_dac;
+// long inv_slope;
+} XO_SLOPE_AREA_DATA;
+
+typedef struct
+{
+ XO_SLOPE_AREA_DATA XO_SlopeAreaData[XO_SlopeArea_Num];
+}l1cal_crystalAfcData_T;
+
+typedef struct
+{
+ kal_int32 cap_id;
+}l1cal_crystalCapData_T;
+
+extern const XO_SLOPE_AREA_DATA XO_SlopeAreaData_RO[XO_SlopeArea_Num];
+
+
+/* ------------------------------------------------------------------------- */
+
+#if MD_DRV_IS_FHC_SUPPORT
+void L1D_RF_GetAFCDacTRxOffset( short *afcdactrxoffset );
+void L1D_RF_SetAFCDacTRxOffset( short *afcdactrxoffset );
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+typedef struct
+{
+ unsigned long icorrection;
+ unsigned long qcorrection;
+} skyip2coef;
+
+typedef struct
+{
+ unsigned long ipol;
+ unsigned long qpol;
+} sky117ip2pol;
+
+typedef struct
+{
+ unsigned long acode;
+ unsigned long amcode;
+} mt6139ip2coef;
+
+typedef struct
+{
+ signed short w_re;
+ signed short w_im;
+} w_coef;
+
+typedef struct
+{
+ unsigned char map[16];
+} gain_rf_map;
+
+
+#define WCTABLE_SIZE 19
+typedef union
+{
+ struct
+ {
+ skyip2coef data[5/*band*/];
+ } skyip2; //for sky74045
+ struct
+ {
+ skyip2coef data[5/*band*/];
+ sky117ip2pol pol[5/*band*/];
+ } sky117ip2;
+ struct
+ {
+ mt6139ip2coef data[5/*band*/];
+ unsigned long rxamcalmode;
+ } mt6139ip2;
+ struct
+ {
+ unsigned char fixgain_enable;
+ } sky74137; //for sky74137
+ struct
+ { // borrowed for mpll_fh chip, should not have rf rx_coff
+ unsigned char fixed_mpll_clk;
+ unsigned short mpll_freq_idx;
+ unsigned char fixed_spll_clk;
+ unsigned short spll_freq_idx;
+ } mpll_fh;
+ struct
+ { // reserved for mpll_fh
+ unsigned char fixed_mpll_clk;
+ unsigned short mpll_freq_idx;
+ w_coef w_data[WCTABLE_SIZE];
+ } mt6256_51rf;
+ struct
+ { // reserved for mpll_fh
+ unsigned char fixed_mpll_clk;
+ unsigned short mpll_freq_idx;
+ unsigned short is_md2g_log_on;
+ } md2g_log; // for chip support md2g logger
+ struct
+ { // reserved for mpll_fh
+ unsigned char fixed_mpll_clk;
+ unsigned short mpll_freq_idx;
+ unsigned short is_md2g_log_on;
+ gain_rf_map gain_rf_table[4/*band*/];
+ } mt6162_gain_rf;
+#if MD_DRV_IS_DUAL_LOOP_AFC_CONTROL_SUPPORT
+ //Fix AFC Enable Setting move to MMRF after UMOLY/TK6291.
+#endif
+} sRxip2;
+
+/*...................................*/
+
+typedef struct
+{
+ unsigned long word6_4_0;
+ unsigned long word6_5_0;
+ unsigned long word6_6_0;
+ unsigned long word6_7_0;
+ unsigned long bvmode;
+ unsigned long c3mode;
+ unsigned long wordC3;
+} b5ptxcoef;
+
+typedef struct
+{
+ short pcl_index;
+ unsigned char pa_vbias;
+#if MD_DRV_IS_RF_MT6280RF || MD_DRV_IS_RF_MT6169 || MD_DRV_IS_RF_MT6166 || MD_DRV_IS_RF_MT6165 || MD_DRV_IS_RF_MT6176 || MD_DRV_IS_RF_MT6179 || MD_DRV_IS_RF_MT6177L || MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T || MD_DRV_IS_RF_MT6177M
+ unsigned short pa_gain;
+#endif
+} pa_vbias;
+
+typedef struct
+{
+ pa_vbias GSM850_pa_vbias[8];
+ pa_vbias GSM900_pa_vbias[8];
+ pa_vbias DCS1800_pa_vbias[8];
+ pa_vbias PCS1900_pa_vbias[8];
+} mt6140tx_pa_vbias;
+
+typedef struct
+{
+ pa_vbias GSM850_pa_vbias[8];
+ pa_vbias GSM900_pa_vbias[8];
+ pa_vbias DCS1800_pa_vbias[8];
+ pa_vbias PCS1900_pa_vbias[8];
+} mt6162tx_pa_vbias;
+
+typedef struct
+{
+ pa_vbias GSM850_pa_vbias[8];
+ pa_vbias GSM900_pa_vbias[8];
+ pa_vbias DCS1800_pa_vbias[8];
+ pa_vbias PCS1900_pa_vbias[8];
+} mt6256tx_pa_vbias;
+
+typedef struct
+{
+ pa_vbias GSM850_pa_vbias[16];
+ pa_vbias GSM900_pa_vbias[16];
+ pa_vbias DCS1800_pa_vbias[16];
+ pa_vbias PCS1900_pa_vbias[16];
+} orionRFtx_pa_vbias;
+
+typedef struct
+{
+ unsigned char REFDET_SLOPE_SKEW;
+ unsigned char AM_FB_DAC;
+} ad6546txcoef;
+
+typedef struct
+{
+ signed char MID_GAMA_THRESHOLD;
+ signed char LOW_GAMA_THRESHOLD;
+ signed char MID_DELTA_SLOPE_SKEW;
+ signed char LOW_DELTA_SLOPE_SKEW;
+ signed char MID_DELTA_APC_CAP;
+ signed char LOW_DELTA_APC_CAP;
+} ad6546tx_reg8_highband_delta;
+
+typedef union
+{
+#if MD_DRV_IS_RF_MT6280RF || MD_DRV_IS_RF_MT6169 || MD_DRV_IS_RF_MT6166 || MD_DRV_IS_RF_MT6165 || MD_DRV_IS_RF_MT6176 || MD_DRV_IS_RF_MT6179 || MD_DRV_IS_RF_MT6177L || MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T || MD_DRV_IS_RF_MT6177M
+ struct
+ {
+ orionRFtx_pa_vbias data;
+ } mt6280tx; /* Reserve mt6280tx for META Backward Capability */
+ struct
+ {
+ orionRFtx_pa_vbias data;
+ } orionRFtx;
+#else
+ struct
+ {
+ b5ptxcoef data;
+ } b5ptx;
+ struct
+ {
+ mt6140tx_pa_vbias data;
+ } mt6140tx;
+ struct
+ {
+ unsigned char ref_temp;
+ unsigned char LB_GMSK_TX_PGA_GC;
+ unsigned char HB_GMSK_TX_PGA_GC;
+ char isDCXO;
+ } CMOSEDGEtx;
+ struct
+ {
+ ad6546txcoef CalData[4];
+ unsigned long Reg8_default[4];
+ ad6546tx_reg8_highband_delta AMLoopDelta;
+ } ad6546tx;
+ struct
+ {
+ mt6162tx_pa_vbias data;
+ } mt6162tx;
+ struct
+ {
+ mt6256tx_pa_vbias data;
+ } mt6256tx;
+/* struct
+ {
+ unsigned long dummy;
+ } sTXdummy;
+ */
+#endif
+} sTxepsk;
+
+typedef struct
+{
+ sRxip2 rx;
+ sTxepsk tx;
+} sRFSpecialCoef;
+
+typedef struct
+{
+ sRFSpecialCoef RFSpecialCoef;
+}l1cal_rfspecialcoef_T;
+
+typedef struct
+{
+ w_coef Wcoef_data[WCTABLE_SIZE];
+}l1cal_wcoef_T;
+
+extern sRFSpecialCoef RFSpecialCoef;
+
+void L1D_RF_SetRFSpecialCoef( void *table );
+
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+extern l1cal_wcoef_T RFSpecial_wcoef_rxd;
+
+void L1D_RF_SetWCoef_RXD( void *table );
+
+void L1D_RF_SetRASParameters( void *table );
+#endif
+/* ------------------------------------------------------------------------- */
+
+typedef struct
+{
+ signed char rollback_2t; /* Rollback (2t/F2I_Resolution) dB when 2 TX slots */
+ signed char rollback_3t; /* Rollback (3t/F2I_Resolution) dB when 3 TX slots */
+ signed char rollback_4t; /* Rollback (4t/F2I_Resolution) dB when 4 TX slots */
+ signed char rollback_5t; /* Rollback (5t/F2I_Resolution) dB when 5 TX slots */
+} sTX_POWER_ROLLBACK;
+
+typedef struct
+{
+ sTX_POWER_ROLLBACK rollback_data[FrequencyBandCount];
+}l1cal_tx_power_rollback_T;
+
+#if MD_DRV_IS_GPRS
+void L1D_RF_SetTxPowerRollbackData( int rf_band, void *table );
+ #if MD_DRV_IS_EGPRS
+void L1D_RF_SetTxPowerRollbackData_EPSK( int rf_band, void *table );
+ #endif
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+typedef struct
+{
+ unsigned short data[16]; /* for closed-loop AUXADC/BSI TXPC */
+} sTXPC_ADCDATA;
+
+typedef struct
+{
+ unsigned short data[8]; /* for closed-loop BSI TXPC */
+} sTXPC_TEMPDATA;
+
+typedef struct
+{
+ char is_calibrated;
+ sTXPC_ADCDATA adc[FrequencyBandCount];
+ short temperature;
+ sTXPC_TEMPDATA temp[FrequencyBandCount];
+} sTXPC_L1CAL;
+
+typedef sTXPC_L1CAL l1cal_txpc_T;
+
+void L1D_RF_TXPC_SET_CAL( sTXPC_L1CAL *cal, int is_EPSK, int update_type );
+void L1D_RF_TXPC_GET_L1_SETTING( sTXPC_L1CAL *buff, int is_EPSK );
+
+/* ------------------------------------------------------------------------- */
+
+typedef struct
+{
+ unsigned short data[8]; /* for temperature ADC */
+} sTEMPERATURE_ADC_L1CAL;
+
+typedef sTEMPERATURE_ADC_L1CAL l1cal_temperatureADC_T;
+
+void L1D_RF_TXPC_Get_Temp_ADC( sTEMPERATURE_ADC_L1CAL *buff );
+
+/* ------------------------------------------------------------------------- */
+/* API for meta DCS 2nd path TX power check */
+void L1D_RF_Set_TX_Notch_Path( kal_uint8 notch_en );
+/* ------------------------------------------------------------------------- */
+
+#if MD_DRV_IS_BPI_DATA_48_BIT_CHIP
+typedef unsigned long long BPI_DATA_SIZE; /* unsigned 64 bits */
+#elif MD_DRV_IS_BPI_DATA_32_BIT_CHIP
+typedef signed long BPI_DATA_SIZE;
+#else
+typedef signed short BPI_DATA_SIZE;
+#endif
+
+#if MD_DRV_IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2
+typedef struct
+{
+ signed short P_SR0; /* BPI data sent at SR0 */
+ signed short P_SR3; /* BPI data sent at SR3 */
+ signed short P_ST0; /* BPI data sent at ST0 */
+ signed short P_ST3; /* BPI data sent at ST3 */
+}sRF_PDATA_OFFCHIP_ITEM;
+
+typedef struct
+{
+ sRF_PDATA_OFFCHIP_ITEM GSM850;
+ sRF_PDATA_OFFCHIP_ITEM GSM;
+ sRF_PDATA_OFFCHIP_ITEM DCS;
+ sRF_PDATA_OFFCHIP_ITEM PCS;
+}sRF_PDATA_OFFCHIP;
+
+#if (defined(__MD93__) || defined(__MD95__))
+typedef struct
+{
+ BPI_DATA_SIZE xPDATA_GSM850_PR1;
+ BPI_DATA_SIZE xPDATA_GSM850_PR2;
+ BPI_DATA_SIZE xPDATA_GSM850_PR2B;
+ BPI_DATA_SIZE xPDATA_GSM850_PR3;
+ BPI_DATA_SIZE xPDATA_GSM850_PR3A;
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR1;
+ BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR2;
+ BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR2B;
+ BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR3;
+ BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR3A;
+ #endif
+ BPI_DATA_SIZE xPDATA_GSM850_PT1;
+ BPI_DATA_SIZE xPDATA_GSM850_PT2;
+ BPI_DATA_SIZE xPDATA_GSM850_PT2B;
+ BPI_DATA_SIZE xPDATA_GSM850_PT3;
+ BPI_DATA_SIZE xPDATA_GSM850_PT3A;
+ BPI_DATA_SIZE xPDATA_GSM_PR1;
+ BPI_DATA_SIZE xPDATA_GSM_PR2;
+ BPI_DATA_SIZE xPDATA_GSM_PR2B;
+ BPI_DATA_SIZE xPDATA_GSM_PR3;
+ BPI_DATA_SIZE xPDATA_GSM_PR3A;
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR1;
+ BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR2;
+ BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR2B;
+ BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR3;
+ BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR3A;
+ #endif
+ BPI_DATA_SIZE xPDATA_GSM_PT1;
+ BPI_DATA_SIZE xPDATA_GSM_PT2;
+ BPI_DATA_SIZE xPDATA_GSM_PT2B;
+ BPI_DATA_SIZE xPDATA_GSM_PT3;
+ BPI_DATA_SIZE xPDATA_GSM_PT3A;
+ BPI_DATA_SIZE xPDATA_DCS_PR1;
+ BPI_DATA_SIZE xPDATA_DCS_PR2;
+ BPI_DATA_SIZE xPDATA_DCS_PR2B;
+ BPI_DATA_SIZE xPDATA_DCS_PR3;
+ BPI_DATA_SIZE xPDATA_DCS_PR3A;
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR1;
+ BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR2;
+ BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR2B;
+ BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR3;
+ BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR3A;
+ #endif
+ BPI_DATA_SIZE xPDATA_DCS_PT1;
+ BPI_DATA_SIZE xPDATA_DCS_PT2;
+ BPI_DATA_SIZE xPDATA_DCS_PT2B;
+ BPI_DATA_SIZE xPDATA_DCS_PT3;
+ BPI_DATA_SIZE xPDATA_DCS_PT3A;
+ BPI_DATA_SIZE xPDATA_PCS_PR1;
+ BPI_DATA_SIZE xPDATA_PCS_PR2;
+ BPI_DATA_SIZE xPDATA_PCS_PR2B;
+ BPI_DATA_SIZE xPDATA_PCS_PR3;
+ BPI_DATA_SIZE xPDATA_PCS_PR3A;
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR1;
+ BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR2;
+ BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR2B;
+ BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR3;
+ BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR3A;
+ #endif
+ BPI_DATA_SIZE xPDATA_PCS_PT1;
+ BPI_DATA_SIZE xPDATA_PCS_PT2;
+ BPI_DATA_SIZE xPDATA_PCS_PT2B;
+ BPI_DATA_SIZE xPDATA_PCS_PT3;
+ BPI_DATA_SIZE xPDATA_PCS_PT3A;
+ BPI_DATA_SIZE xPDATA_GSM850_PR2M1;
+ BPI_DATA_SIZE xPDATA_GSM850_PR2M2;
+ BPI_DATA_SIZE xPDATA_GSM850_PR2M3;
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR2M1;
+ BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR2M2;
+ BPI_DATA_SIZE xPDATA_GSM850_DIVERSITY_PR2M3;
+ #endif
+ BPI_DATA_SIZE xPDATA_GSM850_PT2M1_G8;
+ BPI_DATA_SIZE xPDATA_GSM850_PT2M2_G8;
+ BPI_DATA_SIZE xPDATA_GSM850_PT2M3_G8;
+ BPI_DATA_SIZE xPDATA_GSM850_PT2M1_8G;
+ BPI_DATA_SIZE xPDATA_GSM850_PT2M2_8G;
+ BPI_DATA_SIZE xPDATA_GSM850_PT2M3_8G;
+ BPI_DATA_SIZE xPDATA_GSM_PR2M1;
+ BPI_DATA_SIZE xPDATA_GSM_PR2M2;
+ BPI_DATA_SIZE xPDATA_GSM_PR2M3;
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR2M1;
+ BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR2M2;
+ BPI_DATA_SIZE xPDATA_GSM_DIVERSITY_PR2M3;
+ #endif
+ BPI_DATA_SIZE xPDATA_GSM_PT2M1_G8;
+ BPI_DATA_SIZE xPDATA_GSM_PT2M2_G8;
+ BPI_DATA_SIZE xPDATA_GSM_PT2M3_G8;
+ BPI_DATA_SIZE xPDATA_GSM_PT2M1_8G;
+ BPI_DATA_SIZE xPDATA_GSM_PT2M2_8G;
+ BPI_DATA_SIZE xPDATA_GSM_PT2M3_8G;
+ BPI_DATA_SIZE xPDATA_DCS_PR2M1;
+ BPI_DATA_SIZE xPDATA_DCS_PR2M2;
+ BPI_DATA_SIZE xPDATA_DCS_PR2M3;
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR2M1;
+ BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR2M2;
+ BPI_DATA_SIZE xPDATA_DCS_DIVERSITY_PR2M3;
+ #endif
+ BPI_DATA_SIZE xPDATA_DCS_PT2M1_G8;
+ BPI_DATA_SIZE xPDATA_DCS_PT2M2_G8;
+ BPI_DATA_SIZE xPDATA_DCS_PT2M3_G8;
+ BPI_DATA_SIZE xPDATA_DCS_PT2M1_8G;
+ BPI_DATA_SIZE xPDATA_DCS_PT2M2_8G;
+ BPI_DATA_SIZE xPDATA_DCS_PT2M3_8G;
+ BPI_DATA_SIZE xPDATA_PCS_PR2M1;
+ BPI_DATA_SIZE xPDATA_PCS_PR2M2;
+ BPI_DATA_SIZE xPDATA_PCS_PR2M3;
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR2M1;
+ BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR2M2;
+ BPI_DATA_SIZE xPDATA_PCS_DIVERSITY_PR2M3;
+ #endif
+ BPI_DATA_SIZE xPDATA_PCS_PT2M1_G8;
+ BPI_DATA_SIZE xPDATA_PCS_PT2M2_G8;
+ BPI_DATA_SIZE xPDATA_PCS_PT2M3_G8;
+ BPI_DATA_SIZE xPDATA_PCS_PT2M1_8G;
+ BPI_DATA_SIZE xPDATA_PCS_PT2M2_8G;
+ BPI_DATA_SIZE xPDATA_PCS_PT2M3_8G;
+ BPI_DATA_SIZE xPDATA_INIT;
+ BPI_DATA_SIZE xPDATA_IDLE;
+ BPI_DATA_SIZE xPDATA_GMSK;
+ BPI_DATA_SIZE xPDATA_8PSK;
+ sRF_PDATA_OFFCHIP xPDATA_OFFCHIP;
+}sRF_BPI_VARIABLE;
+#endif
+/*...................................*/
+
+typedef struct
+{
+ signed short xQB_RX_FENA_2_FSYNC;
+ signed short xQB_RX_FSYNC_2_FENA;
+ signed short xQB_TX_FENA_2_FSYNC;
+ signed short xQB_TX_FSYNC_2_FENA;
+ signed short xQB_SR0; //OH
+ signed short xQB_SR1;
+ signed short xQB_SR2;
+ signed short xQB_SR3;
+ signed short xQB_SR2M;
+ #if defined(__MD97__)
+ #else
+ signed short xQB_PR1;
+ signed short xQB_PR2;
+ signed short xQB_PR2B;
+ signed short xQB_PR3;
+ signed short xQB_PR3A;
+ signed short xQB_PR2M1;
+ signed short xQB_PR2M2;
+ #endif
+ signed short xQB_ST0; //OH
+ signed short xQB_ST1;
+ signed short xQB_ST2;
+ signed short xQB_ST2B;
+ signed short xQB_ST3;
+ signed short xQB_ST2M_G8;
+ signed short xQB_ST2M_8G;
+ #if defined(__MD97__)
+ #else
+ signed short xQB_PT1;
+ signed short xQB_PT2;
+ signed short xQB_PT2B;
+ signed short xQB_PT3;
+ signed short xQB_PT3A;
+ signed short xQB_PT2M1_G8;
+ signed short xQB_PT2M2_G8;
+ signed short xQB_PT2M3_G8;
+ signed short xQB_PT2M1_8G;
+ signed short xQB_PT2M2_8G;
+ signed short xQB_PT2M3_8G;
+ #endif
+ signed short xQB_APCON;
+ signed short xQB_APCMID;
+ signed short xQB_APCOFF;
+ signed short xQB_APCDACON; //OH
+ signed short xQR_BOFF_2_IDLE;
+} sRF_TIMING_VARIABLE;
+
+/*...................................*/
+
+typedef struct
+{
+ int xBAT_VOLTAGE_SAMPLE_PERIOD;
+ int xBAT_VOLTAGE_AVERAGE_COUNT;
+ int xBAT_TEMPERATURE_SAMPLE_PERIOD;
+ int xBAT_TEMPERATURE_AVERAGE_COUNT;
+ //int xBAT_LOW_VOLTAGE;
+ //int xBAT_HIGH_VOLTAGE;
+ //int xBAT_LOW_TEMPERATURE;
+ //int xBAT_HIGH_TEMPERATURE;
+ int xRF_TEMPERATURE_SAMPLE_PERIOD; //OH
+ int xRF_TEMPERATURE_AVERAGE_COUNT; //OH
+} sRF_APC_COMPENSATE_VARIABLE;
+
+/*...................................*/
+
+typedef struct
+{
+ signed short txios_highpcl_850_GMSK;
+ signed short txios_highpcl_900_GMSK;
+ signed short txios_highpcl_DCS_GMSK;
+ signed short txios_highpcl_PCS_GMSK;
+ signed short txios_highpcl_850_EPSK;
+ signed short txios_highpcl_900_EPSK;
+ signed short txios_highpcl_DCS_EPSK;
+ signed short txios_highpcl_PCS_EPSK;
+ signed short txios_lowpcl_850_GMSK;
+ signed short txios_lowpcl_900_GMSK;
+ signed short txios_lowpcl_DCS_GMSK;
+ signed short txios_lowpcl_PCS_GMSK;
+ signed short txios_lowpcl_850_EPSK;
+ signed short txios_lowpcl_900_EPSK;
+ signed short txios_lowpcl_DCS_EPSK;
+ signed short txios_lowpcl_PCS_EPSK;
+
+}sRF_PCL_VARIABLE;
+
+/*...................................*/
+
+typedef struct
+{
+ signed short lbmod_gc_highpcl_850_GMSK;
+ signed short lbmod_gc_highpcl_900_GMSK;
+ signed short lbmod_gc_highpcl_DCS_GMSK;
+ signed short lbmod_gc_highpcl_PCS_GMSK;
+ signed short lbmod_gc_highpcl_850_EPSK;
+ signed short lbmod_gc_highpcl_900_EPSK;
+ signed short lbmod_gc_highpcl_DCS_EPSK;
+ signed short lbmod_gc_highpcl_PCS_EPSK;
+ signed short lbmod_gc_lowpcl_850_GMSK;
+ signed short lbmod_gc_lowpcl_900_GMSK;
+ signed short lbmod_gc_lowpcl_DCS_GMSK;
+ signed short lbmod_gc_lowpcl_PCS_GMSK;
+ signed short lbmod_gc_lowpcl_850_EPSK;
+ signed short lbmod_gc_lowpcl_900_EPSK;
+ signed short lbmod_gc_lowpcl_DCS_EPSK;
+ signed short lbmod_gc_lowpcl_PCS_EPSK;
+}sRF_LBMOD_GC_VARIABLE;
+
+/*...................................*/
+
+typedef struct
+{
+ signed short hbmod_gc_highpcl_850_GMSK;
+ signed short hbmod_gc_highpcl_900_GMSK;
+ signed short hbmod_gc_highpcl_DCS_GMSK;
+ signed short hbmod_gc_highpcl_PCS_GMSK;
+ signed short hbmod_gc_highpcl_850_EPSK;
+ signed short hbmod_gc_highpcl_900_EPSK;
+ signed short hbmod_gc_highpcl_DCS_EPSK;
+ signed short hbmod_gc_highpcl_PCS_EPSK;
+ signed short hbmod_gc_lowpcl_850_GMSK;
+ signed short hbmod_gc_lowpcl_900_GMSK;
+ signed short hbmod_gc_lowpcl_DCS_GMSK;
+ signed short hbmod_gc_lowpcl_PCS_GMSK;
+ signed short hbmod_gc_lowpcl_850_EPSK;
+ signed short hbmod_gc_lowpcl_900_EPSK;
+ signed short hbmod_gc_lowpcl_DCS_EPSK;
+ signed short hbmod_gc_lowpcl_PCS_EPSK;
+
+}sRF_HBMOD_GC_VARIABLE;
+
+/*...................................*/
+
+typedef struct
+{
+ signed short txitc_highpcl_850_GMSK;
+ signed short txitc_highpcl_900_GMSK;
+ signed short txitc_highpcl_DCS_GMSK;
+ signed short txitc_highpcl_PCS_GMSK;
+ signed short txitc_highpcl_850_EPSK;
+ signed short txitc_highpcl_900_EPSK;
+ signed short txitc_highpcl_DCS_EPSK;
+ signed short txitc_highpcl_PCS_EPSK;
+ signed short txitc_lowpcl_850_GMSK;
+ signed short txitc_lowpcl_900_GMSK;
+ signed short txitc_lowpcl_DCS_GMSK;
+ signed short txitc_lowpcl_PCS_GMSK;
+ signed short txitc_lowpcl_850_EPSK;
+ signed short txitc_lowpcl_900_EPSK;
+ signed short txitc_lowpcl_DCS_EPSK;
+ signed short txitc_lowpcl_PCS_EPSK;
+}sRF_ITC_PCL_VARIABLE;
+
+/*...................................*/
+
+typedef struct
+{
+ signed char xCLOSED_LOOP_TXPC_TYPE; //OH
+ signed short xQB_TX_SAMPLE_OFFSET_GMSK; //OH
+ signed short xQB_TX_SAMPLE_OFFSET_EPSK; //OH
+ signed short xTXPC_EPSK_TP_SLOPE_LB; //OH
+ signed short xTXPC_EPSK_TP_SLOPE_HB; //OH
+} sRF_TX_POWERFEEDBACK_VARIABLE; //OH
+
+/*...................................*/
+
+typedef struct
+{
+ //int xXO_CapID;
+ //signed short xafc_dac_default;
+ //signed short xafc_inv_slope;
+ signed char xEGSM_DISABLE;
+ //unsigned char xGSM850_GSM900_SWAP;
+ //unsigned char xDCS1800_PCS1900_SWAP;
+ unsigned char xGSM_ERR_DET_ID; //OH
+ signed short xTX_PROPAGATION_DELAY;
+ signed short xTQ_EPSK_TX_DELAY;
+ char xIS_RAMPPROFILE_ROLLBACK_ENABLE;
+} sRF_OTHERS_VARIABLE;
+
+/*...................................*/
+
+typedef struct
+{
+ sTX_POWER_ROLLBACK GSM850_tx_power_rollback_gmsk;
+ sTX_POWER_ROLLBACK GSM_tx_power_rollback_gmsk;
+ sTX_POWER_ROLLBACK DCS_tx_power_rollback_gmsk;
+ sTX_POWER_ROLLBACK PCS_tx_power_rollback_gmsk;
+ sTX_POWER_ROLLBACK GSM850_tx_power_rollback_epsk;
+ sTX_POWER_ROLLBACK GSM_tx_power_rollback_epsk;
+ sTX_POWER_ROLLBACK DCS_tx_power_rollback_epsk;
+ sTX_POWER_ROLLBACK PCS_tx_power_rollback_epsk;
+}sRF_TX_POWER_ROLLBACK_VARIABLE;
+
+/*...................................*/
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#else
+typedef struct
+{
+ //PRIMARARY
+ GGE_IORX_E xGSM850_PATH_SEL;
+ GGE_IORX_E xGSM_PATH_SEL;
+ GGE_IORX_E xDCS_PATH_SEL;
+ GGE_IORX_E xPCS_PATH_SEL;
+
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ //DIVERSITY
+ GGE_IORX_E xGSM850_DIVERSITY_PATH_SEL;
+ GGE_IORX_E xGSM_DIVERSITY_PATH_SEL;
+ GGE_IORX_E xDCS_DIVERSITY_PATH_SEL;
+ GGE_IORX_E xPCS_DIVERSITY_PATH_SEL;
+#endif
+}sRF_RX_BAND_VARIABLE;
+#endif
+/*...................................*/
+
+typedef struct
+{
+ unsigned char xAFC_PREDICTION_ON;
+ unsigned short xAFC_PREDICTION_INTERVAL;
+ unsigned char xAFC_PREDICTION_DECAYING_FACTOR;
+}sRF_AFC_TRACKING_VARIABLE;
+
+/*...................................*/
+
+typedef struct
+{
+ unsigned char xCLK1_EN;
+ unsigned char xCLK2_EN;
+ unsigned char xCLK3_EN;
+ unsigned char xCLK4_EN;
+}sRF_CLK_BUFFER_VARIABLE;
+
+/*...................................*/
+
+#if IS_GSM_TX_DETECTOR_SUPPORT
+typedef struct
+{
+ L1D_TXD_E TXD_ENABLE[FrequencyBandCount];
+}sRF_TX_POWER_DETECT_VARIABLE;
+#endif
+
+/*...................................*/
+
+typedef struct
+{
+ int start; // the special pattern of start position
+ int version; // Struct Version ID
+ int RF_Type; // RF type
+ char is_data_update; // default is false, and will be changed as true after tool update
+#if defined(__MD97__)
+#else
+ sRF_BPI_VARIABLE RF_BPI_Variable;
+#endif
+ sRF_TIMING_VARIABLE RF_Timing_Variable;
+ sRF_APC_COMPENSATE_VARIABLE RF_APC_Compensate_Variable;
+ sRF_PCL_VARIABLE RF_PCL_Varaible;
+ sRF_LBMOD_GC_VARIABLE RF_Lbmod_GC_Variable;
+ sRF_HBMOD_GC_VARIABLE RF_Hbmod_GC_Variable;
+ sRF_ITC_PCL_VARIABLE RF_ITC_PCL_Variable;
+ sRF_TX_POWERFEEDBACK_VARIABLE RF_TX_PowerFeedback_Variable;
+ //sRF_TX_POWER_ROLLBACK_VARIABLE RF_TX_Power_Rollback_Variable;
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#else
+ sRF_RX_BAND_VARIABLE RF_RX_Band_Variable;
+#endif
+ sRF_OTHERS_VARIABLE RF_Others_Variable;
+ sRF_AFC_TRACKING_VARIABLE RF_AFC_Tracking_Variable;
+ sRF_CLK_BUFFER_VARIABLE RF_CLK_Buffer_Variable;
+#if defined(__GSM_INCREASE_RACH_TX_POWER_SUPPORT__)
+ int RACH_Tx_Offset[FrequencyBandCount - 1];//For RACH TX OFFSET
+#endif
+#if IS_GSM_TX_DETECTOR_SUPPORT
+ sRF_TX_POWER_DETECT_VARIABLE RF_TX_PowerDetect_Variable;
+#endif
+ #if defined(__2G_FAST_TIMING_ADJUST_SUPPORT__)
+ bool Fast_Timing_Control;
+ #endif
+ int end; // the special pattern of end1 position
+}sL1D_RF_CUSTOM_INPUT_DATA;
+
+typedef sL1D_RF_CUSTOM_INPUT_DATA l1d_rf_custom_input_data_T;
+
+#endif
+
+void L1D_RF_CAPID_Update( void );
+void L1D_RF_Custom_BBTXParameter_Update( void );
+void L1D_RF_Custom_TX_Power_Rollback_Table_Update_GPRS( void );
+void L1D_RF_Custom_TX_Power_Rollback_Table_Update_EGPRS( void );
+
+/* ------------------------------------------------------------------------- */
+
+typedef struct
+{
+ kal_int32 cload_freq_offset;
+}l1cal_cload_freq_offset_T;
+
+#if MD_DRV_IS_32K_CRYSTAL_REMOVAL_SUPPORT
+void L1D_RF_GetCLoadFreqOffset( int* buff );
+#endif
+/* ------------------------------------------------------------------------- */
+
+#if MD_DRV_IS_TX_GAIN_RF_CALIBRATION_SUPPORT
+ #if MD_DRV_IS_RF_MT6165
+#define TX_GAIN_STEP_NUM 13
+ #else
+#error "please define TX_GAIN_STEP_NUM for this RF"
+ #endif
+#else
+#define TX_GAIN_STEP_NUM 13
+#endif
+
+typedef struct
+{
+ kal_int16 gain_rf[FrequencyBandCount][TX_GAIN_STEP_NUM];
+}l1cal_gainrf_T;
+
+typedef struct
+{
+ short data[TX_GAIN_STEP_NUM];
+} sTXGAIN_RFDATA;
+
+
+typedef enum
+{
+ EPSKTxGainNormalState,
+ EPSKTxGainCalibrationState,
+
+} TXGainRFState;
+
+/* ------------------------------------------------------------------------- */
+
+#if MD_DRV_IS_2G_MIPI_SUPPORT
+
+typedef struct
+{
+ unsigned short mipi_data_st; //mipi data start index
+ unsigned short mipi_data_sp; //mipi data stop index
+} sGGE_MIPIDATA_STSP;
+
+typedef struct
+{
+ unsigned short mipi_elm_type; //mipi element type
+ sGGE_MIPIDATA_STSP mipi_data_stsp; //mipi data table start index and end index
+ unsigned short mipi_evt_type; //event type
+ signed short mipi_evt_timing; //event timing
+} sGGE_MIPIEVENT;
+
+typedef struct
+{
+ unsigned short mipi_elm_type; //mipi element type
+ unsigned short mipi_port_sel; //port where data to send
+ unsigned short mipi_data_seq; //data write sequence format
+ unsigned long mipi_data; //mipi data
+} sGGE_MIPIDATA;
+
+typedef struct
+{
+ signed short subband_arfcn; //subband arfcn
+ unsigned short mipi_addr; //mipi address
+ unsigned long mipi_data; //mipi data
+} sGGE_MIPISUBDATA;
+
+typedef struct
+{
+ unsigned short mipi_elm_type; //mipi element type
+ unsigned short mipi_port_sel; //port where data to send
+ unsigned short mipi_data_seq; //data write sequence format
+ unsigned short mipi_usid; //mipi usid
+ sGGE_MIPISUBDATA mipi_subband_data[GGE_MIPI_SUBBAND_NUM]; //mipi subband data
+} sGGE_MIPIDATA_SUBBAND;
+
+typedef struct
+{
+ unsigned long mipi_gmsk_data[GGE_MIPI_SUBBAND_PA_DATA_NUM][GGE_MIPI_SUBBAND_NUM]; //PA GMSK data
+ unsigned long mipi_8psk_data[GGE_MIPI_SUBBAND_PA_DATA_NUM][GGE_MIPI_SUBBAND_NUM]; //PA 8PSK data
+} sGGE_MIPIPADATA;
+
+typedef struct {
+ sGGE_MIPIEVENT mipi_rxctrl_event[GGE_MIPI_RTX_EVENT_NUM];
+ sGGE_MIPIDATA_SUBBAND mipi_rxctrl_data[GGE_MIPI_RTX_DATA_NUM];
+}sGGE_MIPI_RXCTRL_TABLE;
+
+typedef struct {
+ sGGE_MIPIEVENT mipi_txctrl_event[GGE_MIPI_RTX_EVENT_NUM];
+ sGGE_MIPIDATA_SUBBAND mipi_txctrl_data[GGE_MIPI_RTX_DATA_NUM];
+ sGGE_MIPIPADATA mipi_txctrl_pa_data;
+}sGGE_MIPI_TXCTRL_TABLE;
+
+typedef struct {
+ sGGE_MIPIEVENT mipi_txmidctrl_event[GGE_MIPI_TXMID_TYPE_NUM][GGE_MIPI_TXMID_EVENT_NUM];
+ sGGE_MIPIDATA_SUBBAND mipi_txmidctrl_data[GGE_MIPI_TXMID_DATA_NUM];
+}sGGE_MIPI_TXMIDCTRL_TABLE;
+
+typedef struct
+{
+ sGGE_MIPI_RXCTRL_TABLE mipi_rx_ctrl_table;
+ sGGE_MIPI_TXCTRL_TABLE mipi_tx_ctrl_table;
+ sGGE_MIPI_TXMIDCTRL_TABLE mipi_txmid_ctrl_table;
+}sGGE_MIPI_CTRL_TABLE_BAND;
+
+ #if MD_DRV_IS_2G_TAS_SUPPORT
+typedef struct {
+ sGGE_MIPIEVENT tas_mipi_rtxctrl_event[L1D_TAS_FE_CAT_MAX_NUM*L1D_TAS_MAX_MIPI_EVNET_NUM];
+ sGGE_MIPIDATA_SUBBAND tas_mipi_rtxctrl_data[L1D_TAS_FE_CAT_MAX_NUM*L1D_TAS_MAX_MIPI_DATA_NUM];
+ }sGGE_TAS_MIPI_RTXCTRL_TABLE;
+ #endif
+
+ #if defined(__DYNAMIC_ANTENNA_TUNING__)
+typedef struct
+{
+ sGGE_MIPIEVENT dat_mipi_rtxctrl_event[L1D_DAT_FE_CAT_MAX_NUM*L1D_DAT_MAX_MIPI_EVNET_NUM];
+ sGGE_MIPIDATA_SUBBAND dat_mipi_rtxctrl_data[L1D_DAT_FE_CAT_MAX_NUM*L1D_DAT_MAX_MIPI_DATA_NUM];
+}sGGE_DAT_MIPI_RTXCTRL_TABLE;
+
+typedef sGGE_DAT_MIPI_RTXCTRL_TABLE l1cal_dat_mipi_ctrl_table_T;
+ #endif//__DYNAMIC_ANTENNA_TUNING__
+
+typedef struct
+{
+ sGGE_MIPI_CTRL_TABLE_BAND* band400_mipi_table;
+ sGGE_MIPI_CTRL_TABLE_BAND* band850_mipi_table;
+ sGGE_MIPI_CTRL_TABLE_BAND* band900_mipi_table;
+ sGGE_MIPI_CTRL_TABLE_BAND* band1800_mipi_table;
+ sGGE_MIPI_CTRL_TABLE_BAND* band1900_mipi_table;
+}sGGE_MIPI_CTRL_TABLE_SET;
+
+typedef sGGE_MIPI_CTRL_TABLE_BAND l1cal_mipi_ctrl_table_band_T;
+
+#endif
+
+typedef struct
+{
+ unsigned short l1d_drdi_status;
+
+ /* for Index debug */
+ unsigned short l1d_combined_config_index;
+ unsigned char l1d_first_config_index_base;
+ unsigned char l1d_second_config_index_base;
+ unsigned char l1d_third_config_index_base;
+
+ /* for GPIO debug */
+ unsigned long l1d_gpio_get_pin_rpc_status;
+ unsigned long l1d_gpio_combined_pin_value;
+
+ /* for ADC debug */
+ signed long l1d_adc_get_ch_num_rpc_status;
+ signed long l1d_adc_dcl_handle_status;
+ signed long l1d_adc_cal_dcl_handle_status;
+ unsigned long l1d_adc_get_ch_num;
+ unsigned long l1d_adc_dac_read_result;
+ unsigned long l1d_adc_volt_translate_result;
+ unsigned char l1d_adc_volt_level;
+
+ /* for Barcode debug */
+ unsigned char l1d_barcode_lid_read_status;
+ unsigned char l1d_barcode_digit_read_result;
+
+ unsigned short l1d_custom_2grfparameters_lid_wr_status;
+ unsigned short l1d_custom_gsm850_mipitable_lid_wr_status;
+ unsigned short l1d_custom_gsm900_mipitable_lid_wr_status;
+ unsigned short l1d_custom_dcs1800_mipitable_lid_wr_status;
+ unsigned short l1d_custom_pcs1900_mipitable_lid_wr_status;
+
+ /* for Band support debug */
+ unsigned char l1d_band_support_switch;
+
+ /* for PDATA debug */
+ unsigned long l1d_custom_pdata_txport_debug[4][2];
+
+ signed long l1d_custom_pdata_gmsk_debug;
+ signed long l1d_custom_pdata_8psk_debug;
+ signed long l1d_custom_pdata_init_debug;
+ signed long l1d_custom_pdata_idle_debug;
+
+#if defined (__RX_POWER_OFFSET_SUPPORT__)
+ unsigned short l1d_custom_rxpoweroffset_lid_wr_status;
+ unsigned short l1d_custom_2grf_rx_parameters_ext_lid_wr_status;
+#endif/*__RX_POWER_OFFSET_SUPPORT__*/
+}sl1CustomDRDIStautaDebugInfo;
+
+typedef struct
+{
+ unsigned char bandsupport_gsm850;
+ unsigned char bandsupport_gsm900;
+ unsigned char bandsupport_dcs1800;
+ unsigned char bandsupport_pcs1900;
+}sl1CustomBandSupport;
+typedef sl1CustomDRDIStautaDebugInfo l1cal_l1CustomDRDIStautaDebugInfo_T;
+
+typedef sl1CustomBandSupport l1cal_l1CustomBandSupport_T;
+extern sl1CustomDRDIStautaDebugInfo l1d_custom_drdi_status_debug_info;
+
+#if MD_DRV_IS_TX_POWER_OFFSET_SUPPORT || defined (__SAR_TX_POWER_BACKOFF_SUPPORT__)
+
+#define TPO_2G_TABLE_NUM (1)
+#define L1D_TAS_ANT_NUM (4)
+
+#if defined (__SAR_TX_POWER_BACKOFF_SUPPORT__)
+typedef enum
+{
+ GGE_SAR_RF_STATE_DEFAULT = 0, /* 0, apply default table (table 0) */
+ GGE_SAR_RF_STATE_1,
+ GGE_SAR_RF_STATE_2,
+ GGE_SAR_RF_STATE_3,
+ GGE_SAR_RF_STATE_4,
+ GGE_SAR_RF_STATE_5,
+ GGE_SAR_RF_STATE_6,
+ GGE_SAR_RF_STATE_7,
+ GGE_SAR_RF_STATE_8,
+ GGE_SAR_RF_STATE_9,
+ GGE_SAR_RF_STATE_10,
+ GGE_SAR_RF_STATE_11,
+ GGE_SAR_RF_STATE_12,
+ GGE_SAR_RF_STATE_13,
+ GGE_SAR_RF_STATE_14,
+ GGE_SAR_RF_STATE_15,
+ GGE_SAR_RF_STATE_16,
+ GGE_SAR_RF_STATE_17,
+ GGE_SAR_RF_STATE_18,
+ GGE_SAR_RF_STATE_19,
+ GGE_SAR_RF_STATE_20,
+ GGE_SAR_RF_STATE_END = 21, /* >=21, apply default table (table 0) */
+
+} GGE_TPO_SAR_STATE_INDEX; /* SAR STATE INDEX from AP*/
+#endif//__SAR_TX_POWER_BACKOFF_SUPPORT__
+
+ #if defined(__TX_POWER_OFFSET_SUPPORT__)&&(defined(__TAS_SUPPORT__))
+
+ #if (defined(__MD97__) || defined(__MD97P__))
+ #define SAR_TPO_ANT_NUM MMRFD_MAX_ANT_SUPPORT_NUM
+ #elif defined(__MD95__)
+ #define SAR_TPO_ANT_NUM MMRFD_PHYSICAL_ANT_MAX_NUM
+ #elif defined(__MD93__)
+ #define SAR_TPO_ANT_NUM L1D_TAS_ANT_NUM //For TAS2.0, ANT0/ANT1/ANT2
+ #endif
+typedef struct
+{
+ unsigned short hi_weight;
+ unsigned short low_weight;
+}s_Weight_Power_Offset;
+
+typedef struct
+{
+ signed short max_arfcn;
+ unsigned short mid_level;
+ s_Weight_Power_Offset wt[SAR_TPO_ANT_NUM];
+} sARFCN_SECTION_Power_Offset;
+
+typedef struct
+{
+ short power_offset[SAR_TPO_ANT_NUM][16]; /* unit:DAC */
+ sARFCN_SECTION_Power_Offset arfcn_weight[ ARFCN_SECTION_NUM ];
+} sTX_POWER_OFFSET_TABLE;
+ #else
+typedef struct
+{
+ short power_offset[16]; /* unit:DAC */
+ sARFCN_SECTION arfcn_weight[ ARFCN_SECTION_NUM ];
+} sTX_POWER_OFFSET_TABLE;
+ #endif /* defined(__TX_POWER_OFFSET_SUPPORT__) && defined(__TAS_SUPPORT__) */
+
+typedef struct
+{
+ sTX_POWER_OFFSET_TABLE table[TPO_2G_TABLE_NUM];
+} sTX_POWER_OFFSET;
+
+typedef sTX_POWER_OFFSET tx_power_offset_t;
+
+ #if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__)
+#define MOD_TYPE_COUNT (2)
+#define TX_SLOT_COUNT (4)
+ #if (defined(__MD97__) || defined(__MD97P__))
+ #define SAR_TPB_ANT_NUM MMRFD_MAX_ANT_SUPPORT_NUM
+ #elif defined(__MD95__)
+ #define SAR_TPB_ANT_NUM MMRFD_PHYSICAL_ANT_MAX_NUM
+ #elif defined(__MD93__)
+ #define SAR_TPB_ANT_NUM L1D_TAS_ANT_NUM //For TAS2.0, ANT0/ANT1/ANT2
+ #endif
+typedef struct
+{
+ int power_decrement[FrequencyBandCount-1][SAR_TPB_ANT_NUM][MOD_TYPE_COUNT][TX_SLOT_COUNT];
+} SAR_TX_BACKOFF_TABLE_Params;
+
+
+typedef struct
+{
+ SAR_TX_BACKOFF_TABLE_Params SAR_RF_STATE[GGE_SAR_RF_STATE_END - 1];
+} SAR_TX_BACKOFF_STATE_Params;
+
+typedef SAR_TX_BACKOFF_STATE_Params L1D_CUSTOM_SAR_TX_BACKOFF_DB_NVRAM_T;
+
+ #endif
+#endif /* MD_DRV_IS_TX_POWER_OFFSET_SUPPORT || __SAR_TX_POWER_BACKOFF_SUPPORT__*/
+/* ------------------------------------------------------------------------- */
+
+/* ------------------------------------------------------------------------- */
+#if defined(__RX_POWER_OFFSET_SUPPORT__)
+
+typedef struct
+{
+ kal_uint16 RPO_enable; /* Enable Rx power offset */
+ kal_uint16 RPO_meta_enable; /* The main purpose of "meta_Rx_power_offset_enable" is to disable power offset during calibration */
+} sRX_POWER_OFFSET_SETTING;
+
+typedef struct
+{
+ sRX_POWER_OFFSET_SETTING rx_power_offset_setting;
+} s2G_RF_RX_PARAMETER_EXT;
+
+typedef s2G_RF_RX_PARAMETER_EXT l1_2g_rf_rx_parameter_ext_t;
+
+#endif /* __RX_POWER_OFFSET_SUPPORT__ */
+#if MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT
+#define NSFT_ADJUST_TPO_TABLE_NUM (1)
+
+typedef struct
+{
+ short power_apcdac_offset[16]; /* unit:DAC */
+ short power_dB_offset[16]; /* unit:0.125dB */
+ sARFCN_SECTION arfcn_weight[ ARFCN_SECTION_NUM ];
+} sNSFT_ADJUST_TPO_TABLE;
+
+typedef struct
+{
+ sNSFT_ADJUST_TPO_TABLE table[NSFT_ADJUST_TPO_TABLE_NUM];
+} sNSFT_ADJUST_TPO;
+
+typedef sNSFT_ADJUST_TPO nsft_adjust_tpo_t;
+
+#endif /* MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT */
+#if MD_DRV_IS_RF_MT6176 || MD_DRV_IS_RF_MT6179 || MD_DRV_IS_RF_MT6177L || MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T || MD_DRV_IS_RF_MT6177M
+typedef struct
+{
+ int version;
+ unsigned short is_calibrated;
+ unsigned short lf_fine[4];
+ MMRFC_GSM_RESULT_PER_BAND_T g_result[4];
+#if MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T
+ MMRFC_GSM_POC_PGA_BIAS_T gsm_tx_pga_bias[4];
+#endif
+} MMRFC_GSM_RESULT_T;
+
+typedef MMRFC_GSM_RESULT_T l1cal_mmrfc_result_T;
+
+void L1D_RF_RFCData_Init_Pcore(void);
+void L1D_RF_Get_RFC_Result(MMRFC_GSM_RESULT_T *buff);
+#endif
+/* ------------------------------------------------------------------------- */
+ /* TX gain table */
+#if MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T
+typedef struct
+{
+ unsigned int slice_group;
+ signed int gain_step;
+ unsigned long cw_setting;
+} L1D_TX_GAIN_SETTING_T;
+
+typedef struct
+{
+ L1D_TX_GAIN_SETTING_T lb_tx_gain_setting[MMRFC_GSM_TX_DNL_PGA_TOTAL_GAIN_STEPS]; /* LB TX gain setting */
+ L1D_TX_GAIN_SETTING_T hb_tx_gain_setting[MMRFC_GSM_TX_DNL_PGA_TOTAL_GAIN_STEPS]; /* HB TX gain setting */
+}L1D_TX_GAIN_TABLE_T;
+
+#endif
+/* ------------------------------------------------------------------------- */
+
+#if defined(__TAS_SUPPORT__)
+ #if (defined(__MD93__) || defined(__MD95__)) /*Not supported for Gen97*/
+typedef struct
+{
+ #if MD_DRV_IS_2G_Gen95_UTAS_SUPPORT
+ L1D_CUSTOM_TAS_SPLIT_CONFIG_T l1d_custom_tas_split_database[FrequencyBandCount];
+ #else
+ L1D_CUSTOM_TAS_FE_DATABASE_T l1d_custom_tas_fe_database;
+ L1D_CUSTOM_TAS_FE_CAT_A_T* l1d_custom_tas_fe_cat_a_ptr;
+ L1D_CUSTOM_TAS_FE_CAT_A_T l1d_custom_tas_fe_cat_a;
+ #if MD_DRV_IS_2G_MIPI_SUPPORT
+ sGGE_MIPIEVENT* l1d_tas_cat_a_mipi_event_ptr[L1D_TAS_MAX_CAT_A_CONFIG_NUM];
+ sGGE_MIPIEVENT l1d_tas_cat_a_mipi_event[L1D_TAS_MAX_CAT_A_CONFIG_NUM][L1D_TAS_MAX_MIPI_EVNET_NUM];
+ sGGE_MIPIDATA_SUBBAND* l1d_tas_cat_a_mipi_data_ptr[L1D_TAS_MAX_CAT_A_CONFIG_NUM];
+ sGGE_MIPIDATA_SUBBAND l1d_tas_cat_a_mipi_data[L1D_TAS_MAX_CAT_A_CONFIG_NUM][L1D_TAS_MAX_MIPI_DATA_NUM];
+ #endif
+ L1D_CUSTOM_TAS_FE_CAT_B_T* l1d_custom_tas_fe_cat_b_ptr;
+ L1D_CUSTOM_TAS_FE_CAT_B_T l1d_custom_tas_fe_cat_b;
+ #if MD_DRV_IS_2G_MIPI_SUPPORT
+ sGGE_MIPIEVENT* l1d_tas_cat_b_mipi_event_ptr[L1D_TAS_MAX_CAT_B_CONFIG_NUM];
+ sGGE_MIPIEVENT l1d_tas_cat_b_mipi_event[L1D_TAS_MAX_CAT_B_CONFIG_NUM][L1D_TAS_MAX_MIPI_EVNET_NUM];
+ sGGE_MIPIDATA_SUBBAND* l1d_tas_cat_b_mipi_data_ptr[L1D_TAS_MAX_CAT_B_CONFIG_NUM];
+ sGGE_MIPIDATA_SUBBAND l1d_tas_cat_b_mipi_data[L1D_TAS_MAX_CAT_B_CONFIG_NUM][L1D_TAS_MAX_MIPI_DATA_NUM];
+ #endif
+ L1D_CUSTOM_TAS_FE_CAT_C_T* l1d_custom_tas_fe_cat_c_ptr;
+ L1D_CUSTOM_TAS_FE_CAT_C_T l1d_custom_tas_fe_cat_c;
+ #if MD_DRV_IS_2G_MIPI_SUPPORT
+ sGGE_MIPIEVENT* l1d_tas_cat_c_mipi_event_ptr[L1D_TAS_MAX_CAT_C_CONFIG_NUM];
+ sGGE_MIPIEVENT l1d_tas_cat_c_mipi_event[L1D_TAS_MAX_CAT_C_CONFIG_NUM][L1D_TAS_MAX_MIPI_EVNET_NUM];
+ sGGE_MIPIDATA_SUBBAND* l1d_tas_cat_c_mipi_data_ptr[L1D_TAS_MAX_CAT_C_CONFIG_NUM];
+ sGGE_MIPIDATA_SUBBAND l1d_tas_cat_c_mipi_data[L1D_TAS_MAX_CAT_C_CONFIG_NUM][L1D_TAS_MAX_MIPI_DATA_NUM];
+ #endif
+ #endif
+}L1D_CUSTOM_TAS_FE_NVRAM_T;
+
+typedef struct
+{
+ #if MD_DRV_IS_2G_Gen95_UTAS_SUPPORT
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE0_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE1_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE2_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE3_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE4_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE5_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE6_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE7_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE8_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE9_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE10_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE11_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE12_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE13_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE14_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE15_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE16_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE17_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE18_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE19_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE20_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE21_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE22_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE23_ENABLE[FrequencyBandCount];
+ #else
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE0_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE1_ENABLE[FrequencyBandCount];
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE2_ENABLE[FrequencyBandCount];
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ L1D_CUSTOM_TAS_SWITCH_E L1_TAS_TST_STATE3_ENABLE[FrequencyBandCount];
+ #endif /* __2G_RX_DIVERSITY_PATH_SUPPORT__ */
+ #endif
+}L1D_CUSTOM_TAS_TST_T;
+ #endif
+
+ #if MD_DRV_IS_2G_TAS_INHERIT_4G_ANT
+typedef struct
+{
+ LTE_Band inherit_lte_band;
+}L1D_CUSTOM_TAS_INHERIT_LTE_BAND_T;
+
+typedef struct
+{
+ L1D_CUSTOM_TAS_INHERIT_LTE_BAND_T* l1_inherit_lte_ant_gsmBand_ptr;
+ kal_uint32 inherit_lte_band_bitmap[L1D_TAS_INHERIT_LTE_BAND_BITMAP_NUM];
+}L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_T;
+
+typedef struct
+{
+ L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_T inherit_lte_band_bitmap_table[FrequencyBandCount];
+}L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T;
+ #endif
+#endif
+
+#if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__)
+typedef enum
+{
+ L1D_DAT_DISABLE,
+ L1D_DAT_ENABLE,
+}L1D_CUSTOM_DAT_SWITCH_E;
+
+typedef struct
+{
+ L1D_CUSTOM_DAT_SWITCH_E l1d_dat_enable;
+}L1D_CUSTOM_DAT_DATABASE_T;
+
+#if MD_DRV_IS_2G_DAT_SUPPORT || MD_DRV_IS_2G_Gen95_UDAT_SUPPORT
+typedef struct
+{
+ #if MD_DRV_IS_2G_Gen95_UDAT_SUPPORT
+ L1D_CUSTOM_DAT_SPLIT_CONFIG_T l1d_custom_dat_split_database[FrequencyBandCount];
+ #else
+ L1D_CUSTOM_SB_DAT_FE_DATABASE_T l1d_dat_sb_fe_db[FrequencyBandCount];
+ #endif
+}L1D_CUSTOM_DAT_FE_DATABASE_T;
+#endif
+
+typedef struct
+{
+ L1D_CUSTOM_DAT_SWITCH_E L1_DAT_ENABLE; /* 0: off 1: DAT force mode */
+ #if MD_DRV_IS_2G_DAT_SUPPORT || MD_DRV_IS_2G_Gen95_UDAT_SUPPORT
+ L1D_CUSTOM_DAT_FE_DATABASE_T l1d_custom_dat_fe_database;
+ #endif
+}L1D_CUSTOM_DAT_FE_ROUTE_NVRAM_T;
+
+
+typedef struct
+{
+ L1D_CUSTOM_DAT_FE_CAT_A_T* l1d_custom_dat_fe_cat_a_ptr;
+ L1D_CUSTOM_DAT_FE_CAT_A_T l1d_custom_dat_fe_cat_a;
+ #if MD_DRV_IS_2G_MIPI_SUPPORT
+ sGGE_MIPIEVENT* l1d_dat_cat_a_mipi_event_ptr[L1D_DAT_MAX_CAT_A_CONFIG_NUM];
+ sGGE_MIPIEVENT l1d_dat_cat_a_mipi_event[L1D_DAT_MAX_CAT_A_CONFIG_NUM][L1D_DAT_MAX_MIPI_EVNET_NUM];
+ sGGE_MIPIDATA_SUBBAND* l1d_dat_cat_a_mipi_data_ptr[L1D_DAT_MAX_CAT_A_CONFIG_NUM];
+ sGGE_MIPIDATA_SUBBAND l1d_dat_cat_a_mipi_data[L1D_DAT_MAX_CAT_A_CONFIG_NUM][L1D_DAT_MAX_MIPI_DATA_NUM];
+ #endif
+}L1D_CUSTOM_DAT_FE_CAT_A_NVRAM_T;
+
+typedef struct
+{
+ L1D_CUSTOM_DAT_FE_CAT_B_T* l1d_custom_dat_fe_cat_b_ptr;
+ L1D_CUSTOM_DAT_FE_CAT_B_T l1d_custom_dat_fe_cat_b;
+ #if MD_DRV_IS_2G_MIPI_SUPPORT
+ sGGE_MIPIEVENT* l1d_dat_cat_b_mipi_event_ptr[L1D_DAT_MAX_CAT_B_CONFIG_NUM];
+ sGGE_MIPIEVENT l1d_dat_cat_b_mipi_event[L1D_DAT_MAX_CAT_B_CONFIG_NUM][L1D_DAT_MAX_MIPI_EVNET_NUM];
+ sGGE_MIPIDATA_SUBBAND* l1d_dat_cat_b_mipi_data_ptr[L1D_DAT_MAX_CAT_B_CONFIG_NUM];
+ sGGE_MIPIDATA_SUBBAND l1d_dat_cat_b_mipi_data[L1D_DAT_MAX_CAT_B_CONFIG_NUM][L1D_DAT_MAX_MIPI_DATA_NUM];
+ #endif
+}L1D_CUSTOM_DAT_FE_CAT_B_NVRAM_T;
+
+typedef L1D_CUSTOM_DAT_FE_ROUTE_NVRAM_T l1_dat_custom_fe_route_params_T;
+ #if defined(__MD93__)
+typedef L1D_CUSTOM_DAT_FE_CAT_A_NVRAM_T l1_dat_custom_fe_cata_params_T;
+typedef L1D_CUSTOM_DAT_FE_CAT_B_NVRAM_T l1_dat_custom_fe_catb_params_T;
+ #endif
+#endif
+/*------------------------------Start UMOLY DRDI struct define--------------------*/
+
+typedef struct
+{
+#if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT
+ int BAT_VOLTAGE_THRESHOLD[4];
+ int BAT_TEMPERATURE_THRESHOLD[4];
+#else
+ int BAT_LOW_VOLTAGE;
+ int BAT_HIGH_VOLTAGE;
+ int BAT_LOW_TEMPERATURE;
+ int BAT_HIGH_TEMPERATURE;
+#endif
+ int AP_UPDATE_VOLTINFO_PERIOD;
+}sTX_POWER_VOLTAGE_COMPENSATION;
+
+typedef struct
+{
+ /*capid*/
+ long AFC_XO_CapID;
+
+}sCrystalParameter;
+
+#if MD_DRV_IS_32K_CRYSTAL_REMOVAL_SUPPORT
+typedef struct
+{
+ /*cload freqoffset*/
+ int CLoad_FreqOffset;
+}sCloadParameter;
+
+typedef sCloadParameter l1cal_CloadParameter_T;
+#endif
+
+
+
+#if MD_DRV_IS_2G_MIPI_SUPPORT
+/*DRDI MIPI point define*/
+typedef struct
+{
+ sGGE_MIPI_CTRL_TABLE_BAND* GGE_MIPI_CTRL_TABLE[FrequencyBandCount];
+}sGGE_DRDI_MIPI_CTRL_TABLE;
+#endif
+
+/*DRDI Calibration Data Struct define*/
+
+#if defined(__RX_POWER_OFFSET_SUPPORT__)
+typedef struct
+{
+ s2G_RF_RX_PARAMETER_EXT* RX_Power_Offset_Setting;
+ sL1D_AGCLNA_Gain_Offset_Data RX_Power_Offset_Table;
+} sL1D_RX_POWER_OFFSET_DATA;
+#endif /* __RX_POWER_OFFSET_SUPPORT__ */
+
+#if MD_DRV_IS_TX_POWER_OFFSET_SUPPORT
+typedef struct
+{
+ sTX_POWER_OFFSET* Tx_Power_Offset_GMSK[FrequencyBandCount];
+ #if MD_DRV_IS_EPSK_TX_SUPPORT
+ sTX_POWER_OFFSET* Tx_Power_Offset_EPSK[FrequencyBandCount];
+ #endif
+} sL1D_TX_POWER_OFFSET_DATA;
+#endif /*__TX_POWER_OFFSET_SUPPORT__ || __SAR_TX_POWER_BACKOFF_SUPPORT__*/
+#if MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT
+typedef struct
+{
+ sNSFT_ADJUST_TPO* Adjust_TPO_GMSK[FrequencyBandCount];
+ #if MD_DRV_IS_EPSK_TX_SUPPORT
+ #if defined(__EPSK_ADJUST_TPO_SUPPORT__)
+ sNSFT_ADJUST_TPO* Adjust_TPO_EPSK[FrequencyBandCount];
+ #endif//__EPSK_ADJUST_TPO_SUPPORT__
+ #endif
+} sL1D_ADJUST_TPO_DATA;
+#endif /*MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT*/
+
+typedef struct
+{
+ sAGCGAINOFFSET* AGC_PATHLOSS_TABLE[FrequencyBandCount];
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ sAGCGAINOFFSET* AGC_PATHLOSS_RXD_TABLE[FrequencyBandCount];
+ #endif
+ sRAMPDATA* RampData[FrequencyBandCount];
+#if MD_DRV_IS_EPSK_TX_SUPPORT
+ sRAMPDATA* RampData_EPSK[FrequencyBandCount];
+#endif
+ sTX_POWER_VOLTAGE_COMPENSATION* tx_apc_voltage_compensation;
+ sMIDRAMPDATA* InterRampData[FrequencyBandCount];
+#if MD_DRV_IS_EPSK_TX_SUPPORT
+ sMIDRAMPDATA** EPSK_InterRampData[FrequencyBandCount];
+#endif
+ sCrystalParameter* afc_crystal_data;
+#if MD_DRV_IS_32K_CRYSTAL_REMOVAL_SUPPORT
+ sCloadParameter* Cload_FreqOffset_Data;
+#endif
+#if MD_DRV_IS_GPRS
+ sTX_POWER_ROLLBACK* tx_power_rollback_gmsk[FrequencyBandCount];
+ #if MD_DRV_IS_EGPRS
+ sTX_POWER_ROLLBACK* tx_power_rollback_epsk[FrequencyBandCount];
+ #endif
+#endif
+#if MD_DRV_IS_TX_POWER_CONTROL_SUPPORT
+ #if MD_DRV_IS_TXPC_CL_AUXADC_SUPPORT || IS_TXPC_CL_BSI_SUPPORT
+ sTXPC_ADCDATA* TXADC_Data[FrequencyBandCount];
+ sTXPC_TEMPDATA* TXTEMP_Data[FrequencyBandCount];
+ #if MD_DRV_IS_EPSK_TX_SUPPORT
+ sTXPC_ADCDATA* TXADC_Data_EPSK[FrequencyBandCount];
+ sTXPC_TEMPDATA* TXTEMP_Data_EPSK[FrequencyBandCount];
+ #endif
+ #endif
+#endif
+ sLNAGAINOFFSET* LNA_PATHLOSS_TABLE[FrequencyBandCount];
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ sLNAGAINOFFSET* LNA_PATHLOSS_RXD_TABLE[FrequencyBandCount];
+#endif
+ l1cal_afcData_T* afc_crystal_data_dac_slop;
+ w_coef* w_coef_data;
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ w_coef* w_coef_rxd_data;
+#endif
+ orionRFtx_pa_vbias* pa_data;
+}sL1D_CAL_DATA;
+
+/*DRDI Front End data*/
+typedef struct
+{
+ #if defined(__2G_RF_CUSTOM_TOOL_SUPPORT__)
+ sL1D_RF_CUSTOM_INPUT_DATA* l1d_rf_custom_input_data;
+ #endif
+ #if defined(__TAS_SUPPORT__)
+ L1D_CUSTOM_TAS_NVRAM_T* L1_TAS_Custom_NVRAM;
+ #if (defined(__MD93__) || defined(__MD95__)) /*Not supported for Gen97*/
+ L1D_CUSTOM_TAS_FE_NVRAM_T* L1_TAS_Custom_FE_NVRAM;
+ L1D_CUSTOM_TAS_TST_T* L1_TAS_Custom_TST;
+ #endif
+ #if IS_2G_TAS_INHERIT_4G_ANT
+ L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T* L1_TAS_Custom_InheritLteAntTable;
+ #endif
+ #endif
+ #if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__)
+ L1D_CUSTOM_DAT_FE_ROUTE_NVRAM_T* L1_DAT_Custom_FE_ROUTE_NVRAM;
+ #if defined(__MD93__)
+ L1D_CUSTOM_DAT_FE_CAT_A_NVRAM_T* L1_DAT_Custom_FE_CAT_A_NVRAM;
+ L1D_CUSTOM_DAT_FE_CAT_B_NVRAM_T* L1_DAT_Custom_FE_CAT_B_NVRAM;
+ #endif
+ #endif
+ #if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__)
+ L1D_CUSTOM_RAS_NVRAM_T* L1_RAS_Custom_NVRAM;
+ #endif
+ char dummy; //avoid build error
+} sL1D_FRONT_END_DATA;
+
+typedef struct
+{
+ #if defined(__RX_POWER_OFFSET_SUPPORT__)
+ sL1D_RX_POWER_OFFSET_DATA L1D_RX_Power_Offset_Data;
+ #endif
+ #if MD_DRV_IS_TX_POWER_OFFSET_SUPPORT
+ sL1D_TX_POWER_OFFSET_DATA L1D_TX_Power_Offset_Data;
+ #endif
+ #if MD_DRV_IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT
+ sL1D_ADJUST_TPO_DATA adjust_tpo_data;
+ #endif
+ #if defined(__ANT_RXPWR_OFFSET_SUPPORT__)
+ sL1D_ANT_RxPWR_Offset_T* L1D_ANT_RxPWR_Offset_NVRAM;
+ #endif
+ #if defined(__GSM_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT__)
+ L1D_RF_INTERFERENCE_ARFCN_INDICATION_T* L1_Custom_HW_CLK_NVRAM;
+ #endif
+ #if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__)
+ L1D_CUSTOM_SAR_TX_BACKOFF_DB_NVRAM_T* L1_Custom_SAR_TX_BACKOFF_DB_NVRAM;
+ #endif
+ char dummy; //avoid build error
+}sL1D_CUSTOM_FEATURE_DATA;
+
+/*-----------------------------------End UMOLY DRDI Struct define-----------------------*/
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1d_cid.h b/mcu/interface/l1/gl1/external/l1d_cid.h
new file mode 100644
index 0000000..975258c
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_cid.h
@@ -0,0 +1,7059 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_cid.h
+ *
+ * Project:
+ * --------
+ * MT6208
+ *
+ * Description:
+ * ------------
+ * Compile option definitoin
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
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+ *******************************************************************************/
+
+#ifndef _L1D_CID_H_
+#define _L1D_CID_H_
+
+/*===================================================================*/
+/* UMOLY Build Error Bypass before New Feature Ready. */
+/*===================================================================*/
+
+#define IS_TK6291_BYPASS_BUILD_ERR_DRDI 1
+
+
+/*===============================================================================================*/
+
+/*------------------------------------------*/
+/* Compile Option : */
+/* (1) MODE_GSM */
+/* (2) MODE_GPRS */
+/* (3) MODE_EGPRS */
+/* ------------- */
+/* (*) MTK_EGPRS_ENABLE */
+/* (*) __EGPRS_MODE__ */
+/* (*) MTK_GPRS_ENABLE */
+/* (*) __PS_SERVICE__ */
+/* (*) GPRS==1 */
+/*------------------------------------------*/
+/* Use in L1D : */
+/* (1) IS_GSM */
+/* (2) IS_GPRS */
+/* (3) IS_EGPRS */
+/*------------------------------------------*/
+
+#define MODE_ID_GSM 0x0001
+#define MODE_ID_GPRS 0x0002
+#define MODE_ID_EGPRS 0x0004
+
+#ifdef MODE_GSM
+#define MODE_ID MODE_ID_GSM
+#endif
+#ifdef MODE_GPRS
+#define MODE_ID MODE_ID_GPRS
+#endif
+#ifdef MODE_EGPRS
+#define MODE_ID MODE_ID_EGPRS
+#endif
+
+#define IS_GSM (MODE_ID==MODE_ID_GSM )
+#define IS_GPRS ((MODE_ID==MODE_ID_GPRS) || (MODE_ID==MODE_ID_EGPRS))
+#define IS_EGPRS (MODE_ID==MODE_ID_EGPRS)
+/*.......................................................*/
+
+#ifndef MODE_ID
+ #ifdef __EGPRS_MODE__
+/*EGPRS*/ #define MODE_ID MODE_ID_EGPRS
+ #endif
+#endif
+
+#ifndef MODE_ID
+ #ifdef MTK_EGPRS_ENABLE
+/*EGPRS*/ #define MODE_ID MODE_ID_EGPRS
+ #endif
+#endif
+
+#ifndef MODE_ID
+ #ifdef __PS_SERVICE__
+/*GPRS*/ #define MODE_ID MODE_ID_GPRS
+ #endif
+#endif
+
+#ifndef MODE_ID
+ #ifdef MTK_GPRS_ENABLE
+/*GPRS*/ #define MODE_ID MODE_ID_GPRS
+ #endif
+#endif
+
+#ifndef MODE_ID
+ #ifdef GPRS
+ #if GPRS==1
+/*GPRS*/ #define MODE_ID MODE_ID_GPRS
+ #else
+/*GSM*/ #define MODE_ID MODE_ID_GSM
+ #endif
+ #endif
+#endif
+
+/* default setting */
+#ifndef MODE_ID
+/*GSM*/ #define MODE_ID MODE_ID_GSM
+#endif
+/*===============================================================================================*/
+
+/*---------------------------------------------------*/
+/* Compile Option : */
+/* (1) FPGA */
+/* (2) CHIP_MT6208 */
+/* (3) CHIP_MT6205 (A) */
+/* (4) CHIP_MT6205B (B) */
+/* (5) CHIP_MT6218 (A) */
+/* (6) CHIP_MT6218B (B) */
+/* (7) CHIP_MT6219 */
+/* (8) CHIP_MT6217 */
+/* (9) CHIP_MT6227 */
+/* (10)CHIP_MT6228 */
+/* (11)CHIP_MT6229 */
+/* (12)CHIP_MT6225 */
+/* (13)CHIP_MT6223 */
+/* (14)CHIP_MT6238 */
+/* --------------- */
+/* (*) CHIP_TARGET */
+/*---------------------------------------------------*/
+/* Use in L1D : */
+/* (1) IS_FPGA_TARGET */
+/* (2) IS_CHIP_TARGET */
+/* (3) IS_CHIP_MT6208 */
+/* (4) IS_CHIP_MT6205A */
+/* (5) IS_CHIP_MT6205B */
+/* (6) IS_CHIP_MT6205 (A/B) */
+/* (7) IS_CHIP_MT6218A */
+/* (8) IS_CHIP_MT6218B */
+/* (9) IS_CHIP_MT6218 */
+/* (10)IS_CHIP_MT6219 */
+/* (11)IS_CHIP_MT6228 */
+/* (12)IS_CHIP_MT6229 */
+/* (13)IS_CHIP_MT6227 */
+/* (14)IS_CHIP_MT6208_AND_LATTER_VERSION */
+/* (15)IS_CHIP_MT6205_AND_LATTER_VERSION (A/B) */
+/* (16)IS_CHIP_MT6205A_AND_LATTER_VERSION (A/B) */
+/* (17)IS_CHIP_MT6205B_AND_LATTER_VERSION */
+/* (18)IS_CHIP_MT6218_AND_LATTER_VERSION (A/B) */
+/* (19)IS_CHIP_MT6218A_AND_LATTER_VERSION (A/B) */
+/* (20)IS_CHIP_MT6218B_AND_LATTER_VERSION */
+/* (21)IS_CHIP_MT6219_AND_LATTER_VERSION */
+/* (22)IS_CHIP_MT6228_AND_LATTER_VERSION */
+/* (23)IS_CHIP_MT6227_AND_LATTER_VERSION */
+/* (24)IS_CHIP_MT6218B_AN2DN */
+/* (25)IS_CHIP_MT6218B_EN */
+/* (26)IS_CHIP_MT6218B_FN */
+/* (27)IS_CHIP_MT6219_AV */
+/* (28)IS_CHIP_MT6219_BV */
+/* (29)IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION */
+/* (30)IS_CHIP_MT6225 */
+/* (31)IS_CHIP_MT6225_AND_LATTER_VERSION */
+/* (32)IS_CHIP_MT6223 */
+/* (33)IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION */
+/* (34)IS_CHIP_MT6238 */
+/* (35)IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION */
+/*---------------------------------------------------*/
+
+#define CHIP_ID_FPGA 0x00000000
+
+/* Divide chips into Series+Number */
+
+#define CHIP_SER(ID) (0xFFFFFF00&ID)
+#define CHIP_NUM(ID) (0x000000FF&ID)
+
+/*---------------------*/
+/* For GSM/GPRS Group */
+/*---------------------*/
+/* GSM */ /* 0x00000100+number */
+#define CHIP_ID_MT6208 0x00000101 //0x00000001
+#define CHIP_ID_MT6205A 0x00000102 //0x00000002
+#define CHIP_ID_MT6205B 0x00000103 //0x00000004
+/* GPRS */ /* 0x00000200+number */
+#define CHIP_ID_MT6218A 0x00000201 //0x00000008
+#define CHIP_ID_MT6218B 0x00000202 //0x00000010
+#define CHIP_ID_MT6219 0x00000203 //0x00000020
+/* AMR */ /* 0x00000400+number */
+#define CHIP_ID_MT6227 0x00000401 //0x00000100
+#define CHIP_ID_MT6228 0x00000402 //0x00000040
+#define CHIP_ID_MT6225 0x00000403 //0x00000200
+
+/*----------------------------------*/
+/* For Dual DSP Group (EGPRS Group) */
+/*----------------------------------*/
+/* EDGE */ /* 0x00000800+number */
+#define CHIP_ID_MT6229 0x00000801 //0x00000080
+#define CHIP_ID_MT6268T 0x00000802 //0x00000400
+/* GPRS SAIC */ /* 0x00001000+number */
+#define CHIP_ID_MT6223 0x00001001 //0x00000800
+/* EDGE SAIC */ /* 0x00002000+number */
+#define CHIP_ID_MT6235 0x00002001 //0x00001000
+#define CHIP_ID_MT6238 0x00002002 //0x00002000
+#define CHIP_ID_TK6516 0x00002003 //0x00004000
+#define CHIP_ID_MT6268A 0x00002004 //0x00008000
+#define CHIP_ID_MT6516 0x00002005 //0x00010000
+#define CHIP_ID_MT6268 0x00002006 //0x00040000
+#define CHIP_ID_MT6236 0x00002007 //0x00100000
+/* SOC */ /* 0x00004000+number */
+#define CHIP_ID_MT6253T 0x00004001 //0x00020000
+#define CHIP_ID_MT6253 0x00004002 //0x00080000
+#define CHIP_ID_MT6252L 0x00004003
+#define CHIP_ID_MT6252H 0x00004004
+/* Dual MAC DSP */ /* 0x00008000+number */
+#define CHIP_ID_MT6268T_DMAC 0x00008001 //0x00200000
+#define CHIP_ID_MT6270A 0x00008002 //0x00400000
+#define CHIP_ID_MT6276 0x00008003 //0x00800000
+#define CHIP_ID_MT6573 0x00008004 //0x00000000
+#define CHIP_ID_MT6575 0x00008005 //0x00000000
+#define CHIP_ID_MT6577 0x00008006 //0x00000000
+/* DLIF */ /* 0x00010000+number */
+#define CHIP_ID_MT6256 0x00010001 //0x01000000
+#define CHIP_ID_MT6251 0x00010002 //0x02000000
+#define CHIP_ID_MT6255 0x00010003
+#define CHIP_ID_MT6250 0x00010004
+#define CHIP_ID_MT6260 0x00010005
+#define CHIP_ID_MT6261 0x00010006
+#define CHIP_ID_MT6280 0x00010080
+#define CHIP_ID_MT6583_MD1 0x00010081
+#define CHIP_ID_MT6583_MD2 0x00010082
+#define CHIP_ID_MT6572 0x00010083
+#define CHIP_ID_MT6582 0x00010084
+#define CHIP_ID_MT6290 0x00010085
+#define CHIP_ID_MT6595 0x00010088
+#define CHIP_ID_MT6752_MD1 0x00010089
+#define CHIP_ID_MT6752_MD2 0x00010090
+#define CHIP_ID_TK6291 0x00010091
+#define CHIP_ID_MT6755 0x00010092
+#define CHIP_ID_MT6292 0x000100A0
+#define CHIP_ID_MT6799 0x000100A1
+#define CHIP_ID_MT6293 0x000100B0
+#define CHIP_ID_MT6763 0X000100B1
+#define CHIP_ID_MT6739 0X000100B2
+#define CHIP_ID_TRINITYE1 0X000100B3
+#define CHIP_ID_TRINITYL 0X000100B4
+#define CHIP_ID_MT6771 0x000100B5
+#define CHIP_ID_MT6765 0x000100B6
+#define CHIP_ID_MT6295M 0X000100C0
+#define CHIP_ID_MT3967 0X000100C1
+#define CHIP_ID_MT6779 0X000100C2
+#define CHIP_ID_MT6297 0X000100D0
+#define CHIP_ID_MT6885 0X000100D1
+#define CHIP_ID_MERCURY 0X000100D2
+#define CHIP_ID_MT6873 0X000100D3
+#define CHIP_ID_MT6853 0X000100D4
+#define CHIP_ID_MT6833 0X000100D5
+#define CHIP_ID_MT6880 0X000100D6
+#define CHIP_ID_MT6890 0X000100D7
+#define CHIP_ID_MT2735 0X000100D8
+#define CHIP_ID_MT6893 0X000100D9/*D6, D7, D8 is used for Colgin*/
+#define CHIP_ID_MT6877 0X000100DA
+#define CHIP_ID_MT6855 0X000100DB
+#ifdef FPGA
+#define CHIP_ID CHIP_ID_FPGA
+#endif
+#ifdef CHIP_MT6208
+#define CHIP_ID CHIP_ID_MT6208
+#endif
+#ifdef CHIP_MT6205
+#define CHIP_ID CHIP_ID_MT6205A
+#endif
+#ifdef CHIP_MT6205B
+#define CHIP_ID CHIP_ID_MT6205B
+#endif
+#ifdef CHIP_MT6218
+#define CHIP_ID CHIP_ID_MT6218A
+#endif
+#ifdef CHIP_MT6218B
+#define CHIP_ID CHIP_ID_MT6218B
+#endif
+#ifdef CHIP_MT6217
+#define CHIP_ID CHIP_ID_MT6218B
+#endif
+#ifdef CHIP_MT6219
+#define CHIP_ID CHIP_ID_MT6219
+#endif
+#ifdef CHIP_MT6228
+#define CHIP_ID CHIP_ID_MT6228
+#endif
+#ifdef CHIP_MT6229
+#define CHIP_ID CHIP_ID_MT6229
+#endif
+#ifdef CHIP_MT6230
+#define CHIP_ID CHIP_ID_MT6229 /* For L1 MT6230==MT6229 */
+#endif
+#ifdef CHIP_MT6226
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226==MT6227 */
+#endif
+#ifdef CHIP_MT6227
+#define CHIP_ID CHIP_ID_MT6227
+#endif
+#ifdef CHIP_MT6226M
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226M==MT6227 */
+#endif
+#ifdef CHIP_MT6226D
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226D==MT6227 */
+#endif
+#ifdef CHIP_MT6227D
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6227D==MT6227 */
+#endif
+#ifdef CHIP_MT6226DS
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226DS==MT6227 */
+#endif
+#ifdef CHIP_MT6227DS
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6227DS==MT6227 */
+#endif
+#ifdef CHIP_MT6225
+#define CHIP_ID CHIP_ID_MT6225
+#endif
+#ifdef CHIP_MT6268T
+ #ifdef __DSP_FCORE4__
+#define CHIP_ID CHIP_ID_MT6268T_DMAC
+ #else
+#define CHIP_ID CHIP_ID_MT6268T
+ #endif
+#endif
+#ifdef CHIP_MT6268H
+#define CHIP_ID CHIP_ID_MT6268T/* For L1 MT6268H==MT6268T*/
+#endif
+#ifdef CHIP_MT6223
+#define CHIP_ID CHIP_ID_MT6223
+#endif
+#ifdef CHIP_MT6223P
+#define CHIP_ID CHIP_ID_MT6223 /* For L1 MT6223P==MT6223 */
+#endif
+#ifdef CHIP_MT6235
+#define CHIP_ID CHIP_ID_MT6238 /* For L1 MT6235==MT6238 */
+#endif
+#ifdef CHIP_MT6238
+#define CHIP_ID CHIP_ID_MT6238
+#endif
+#ifdef CHIP_MT6235B
+#define CHIP_ID CHIP_ID_MT6238 /* For L1 MT6235B==MT6238 */
+#endif
+#ifdef CHIP_MT6239
+#define CHIP_ID CHIP_ID_MT6238
+#endif
+#ifdef CHIP_TK6516
+#define CHIP_ID CHIP_ID_TK6516
+#endif
+#ifdef CHIP_MT6268A
+#define CHIP_ID CHIP_ID_MT6268A
+#endif
+#ifdef CHIP_MT6268
+#define CHIP_ID CHIP_ID_MT6268
+#endif
+#ifdef CHIP_MT6516
+#define CHIP_ID CHIP_ID_MT6516
+#endif
+#ifdef CHIP_MT6253T
+#define CHIP_ID CHIP_ID_MT6253T
+#endif
+#ifdef CHIP_MT6253
+#define CHIP_ID CHIP_ID_MT6253
+#endif
+#ifdef CHIP_MT6253E
+#define CHIP_ID CHIP_ID_MT6252H
+#endif
+#ifdef CHIP_MT6253L
+#define CHIP_ID CHIP_ID_MT6252L
+#endif
+#ifdef CHIP_MT6252
+#define CHIP_ID CHIP_ID_MT6252L
+#endif
+#ifdef CHIP_MT6252H
+#define CHIP_ID CHIP_ID_MT6252H
+#endif
+#ifdef CHIP_MT6236
+#define CHIP_ID CHIP_ID_MT6236
+#endif
+#ifdef CHIP_MT6236B
+#define CHIP_ID CHIP_ID_MT6236 /* For L1 MT6236B==MT6236 */
+#endif
+#ifdef CHIP_MT6270A
+#define CHIP_ID CHIP_ID_MT6270A
+#endif
+#ifdef CHIP_MT6276
+#define CHIP_ID CHIP_ID_MT6276
+#endif
+#ifdef CHIP_MT6256
+#define CHIP_ID CHIP_ID_MT6256
+#endif
+#ifdef CHIP_MT6255
+#define CHIP_ID CHIP_ID_MT6255
+#endif
+#ifdef CHIP_MT6251
+#define CHIP_ID CHIP_ID_MT6251
+#endif
+#ifdef CHIP_MT6573
+#define CHIP_ID CHIP_ID_MT6573
+#endif
+#ifdef CHIP_MT6575
+#define CHIP_ID CHIP_ID_MT6575
+#endif
+#ifdef CHIP_MT6577
+#define CHIP_ID CHIP_ID_MT6577
+#endif
+#ifdef CHIP_MT6250
+#define CHIP_ID CHIP_ID_MT6250
+#endif
+#ifdef CHIP_MT6280
+#define CHIP_ID CHIP_ID_MT6280
+#endif
+#ifdef CHIP_TK6280
+#define CHIP_ID CHIP_ID_MT6270A /* For TK6280 FPGA development, The 2G part is similar to MT6270A FPGA */
+#endif
+#ifdef CHIP_MT6583
+ #if defined(__MD1__)
+#define CHIP_ID CHIP_ID_MT6583_MD1
+ #elif defined(__MD2__)
+#define CHIP_ID CHIP_ID_MT6583_MD2
+ #else
+#error
+ #endif
+#endif
+#ifdef CHIP_MT6752
+ #if defined(__MD1__)
+#define CHIP_ID CHIP_ID_MT6752_MD1
+ #elif defined(__MD2__)
+#define CHIP_ID CHIP_ID_MT6752_MD2
+ #else
+#error
+ #endif
+#endif
+#ifdef CHIP_MT6572
+#define CHIP_ID CHIP_ID_MT6572
+#endif
+#ifdef CHIP_MT6582
+#define CHIP_ID CHIP_ID_MT6582
+#endif
+#ifdef CHIP_MT6290
+#define CHIP_ID CHIP_ID_MT6290
+#endif
+#ifdef CHIP_MT6595
+#define CHIP_ID CHIP_ID_MT6595
+#endif
+#ifdef MT6293
+#define CHIP_ID CHIP_ID_MT6293
+#endif
+#ifdef MT6763
+#define CHIP_ID CHIP_ID_MT6763
+#endif
+#ifdef MT6739
+#define CHIP_ID CHIP_ID_MT6739
+#endif
+#ifdef MT6771
+#define CHIP_ID CHIP_ID_MT6771
+#endif
+#ifdef MT6765
+#define CHIP_ID CHIP_ID_MT6765
+#endif
+#ifdef MT6295M
+#define CHIP_ID CHIP_ID_MT6295M
+#endif
+#ifdef MT3967
+#define CHIP_ID CHIP_ID_MT3967
+#endif
+#ifdef MT6779
+#define CHIP_ID CHIP_ID_MT6779
+#endif
+#ifdef MT6297
+#define CHIP_ID CHIP_ID_MT6297
+#endif
+#ifdef MT6885
+#define CHIP_ID CHIP_ID_MT6885
+#endif
+#ifdef MERCURY
+#define CHIP_ID CHIP_ID_MERCURY
+#endif
+#ifdef MT6873
+#define CHIP_ID CHIP_ID_MT6873
+#endif
+#ifdef MT6853
+#define CHIP_ID CHIP_ID_MT6853
+#endif
+#ifdef MT6833
+#define CHIP_ID CHIP_ID_MT6833
+#endif
+#if (defined(MT6880) || ((defined(MT6880) && defined(CHIP10992))))
+#define CHIP_ID CHIP_ID_MT6880
+#endif
+#if (defined(MT6890) || ((defined(MT6890) && defined(CHIP10992))))
+#define CHIP_ID CHIP_ID_MT6890
+#endif
+#if (defined(MT2735) || ((defined(MT2735) && defined(CHIP10992))))
+#define CHIP_ID CHIP_ID_MT2735
+#endif
+#ifdef MT6893
+#undef CHIP_ID /* we are undefining the chip id since MT6885 is also enabled for MT6893 project*/
+#define CHIP_ID CHIP_ID_MT6893
+#endif
+#ifdef MT6877
+#define CHIP_ID CHIP_ID_MT6877
+#endif
+#ifdef MT6855
+#define CHIP_ID CHIP_ID_MT6855
+#endif
+
+#if defined(L1_SIM) || (defined(ESIM_BUILD_CONFIG) && (ESIM_BUILD_CONFIG == ESIM_MULTI_MODE_ON_FIBERS))
+ #ifdef L1D_TEST
+#undef CHIP_ID
+#define CHIP_ID CHIP_ID_MT6293
+
+ #else
+
+ #if (defined __MD93__)
+#undef CHIP_ID
+#define CHIP_ID CHIP_ID_MT6292
+ #endif
+ #endif
+#endif
+
+
+#define IS_CHIP_SER(ID) ( CHIP_SER(CHIP_ID)==CHIP_SER(ID) )
+#define IS_CHIP_SER_AND_LATTER(ID) ( CHIP_NUM(CHIP_ID)>=CHIP_NUM(ID) && IS_CHIP_SER(ID) )
+#define IS_CHIP_SER_AND_BEFORE(ID) ( CHIP_NUM(CHIP_ID)<=CHIP_NUM(ID) && IS_CHIP_SER(ID) )
+
+#define IS_FPGA_TARGET ( CHIP_ID==CHIP_ID_FPGA )
+#define IS_CHIP_TARGET ( CHIP_ID!=CHIP_ID_FPGA )
+
+#define IS_CHIP_MT6208 ( CHIP_ID==CHIP_ID_MT6208 )
+#define IS_CHIP_MT6205A ( CHIP_ID==CHIP_ID_MT6205A)
+#define IS_CHIP_MT6205B ( CHIP_ID==CHIP_ID_MT6205B)
+#define IS_CHIP_MT6205 ((CHIP_ID==CHIP_ID_MT6205A) || (CHIP_ID==CHIP_ID_MT6205B))
+#define IS_CHIP_MT6218A ( CHIP_ID==CHIP_ID_MT6218A)
+#define IS_CHIP_MT6218B ( CHIP_ID==CHIP_ID_MT6218B)
+#define IS_CHIP_MT6218 ((CHIP_ID==CHIP_ID_MT6218A) || (CHIP_ID==CHIP_ID_MT6218B))
+#define IS_CHIP_MT6219 ( CHIP_ID==CHIP_ID_MT6219 )
+#define IS_CHIP_MT6228 ( CHIP_ID==CHIP_ID_MT6228 )
+#define IS_CHIP_MT6229 ( CHIP_ID==CHIP_ID_MT6229 )
+#define IS_CHIP_MT6227 ( CHIP_ID==CHIP_ID_MT6227 )
+#define IS_CHIP_MT6225 ( CHIP_ID==CHIP_ID_MT6225 )
+#define IS_CHIP_MT6268T ( CHIP_ID==CHIP_ID_MT6268T)
+#define IS_CHIP_MT6268T_DMAC ( CHIP_ID==CHIP_ID_MT6268T_DMAC )
+#define IS_CHIP_MT6268H ((CHIP_ID==CHIP_ID_MT6268T) && (defined MT6268H) )
+#define IS_CHIP_MT6223 ( CHIP_ID==CHIP_ID_MT6223 )
+#define IS_CHIP_MT6238 ( CHIP_ID==CHIP_ID_MT6238 )
+#define IS_CHIP_TK6516 ( CHIP_ID==CHIP_ID_TK6516 )
+#define IS_CHIP_MT6268A ( CHIP_ID==CHIP_ID_MT6268A)
+#define IS_CHIP_MT6268B ( CHIP_ID==CHIP_ID_MT6268 )
+#define IS_CHIP_MT6268 ((CHIP_ID==CHIP_ID_MT6268A) || (CHIP_ID==CHIP_ID_MT6268)) /* MT6268 includes MT6268A and MT6268 */
+#define IS_CHIP_MT6516 ( CHIP_ID==CHIP_ID_MT6516 )
+#define IS_CHIP_MT6253T ( CHIP_ID==CHIP_ID_MT6253T)
+#define IS_CHIP_MT6253 ((CHIP_ID==CHIP_ID_MT6253T) || (CHIP_ID==CHIP_ID_MT6253) || (CHIP_ID==CHIP_ID_MT6252L) || (CHIP_ID==CHIP_ID_MT6252H)) /* MT6253 includes MT6253T,MT6253,MT6252L,MT6252H */
+#define IS_CHIP_MT6252L ( CHIP_ID==CHIP_ID_MT6252L)
+#define IS_CHIP_MT6252H ( CHIP_ID==CHIP_ID_MT6252H)
+#define IS_CHIP_MT6252 ((CHIP_ID==CHIP_ID_MT6252L) || (CHIP_ID==CHIP_ID_MT6252H))
+#define IS_CHIP_MT6253EL ( IS_CHIP_MT6252 )
+#define IS_CHIP_MT6236 ( CHIP_ID==CHIP_ID_MT6236 )
+#define IS_CHIP_MT6270A ( CHIP_ID==CHIP_ID_MT6270A)
+#define IS_CHIP_MT6276 ( CHIP_ID==CHIP_ID_MT6276 )
+#define IS_CHIP_MT6256 ( CHIP_ID==CHIP_ID_MT6256 )
+#define IS_CHIP_MT6251 ( CHIP_ID==CHIP_ID_MT6251 )
+#define IS_CHIP_MT6573 ( CHIP_ID==CHIP_ID_MT6573 )
+#define IS_CHIP_MT6575 ((CHIP_ID==CHIP_ID_MT6575) || (CHIP_ID==CHIP_ID_MT6577))
+#define IS_CHIP_MT6577 ( CHIP_ID==CHIP_ID_MT6577 )
+#define IS_CHIP_MT6250 ( CHIP_ID==CHIP_ID_MT6250 )
+#define IS_CHIP_MT6280 ( CHIP_ID==CHIP_ID_MT6280 )
+#define IS_CHIP_MT6925 ( CHIP_ID==CHIP_ID_MT6229 ) /* Temp add for MT6925 simulation */
+#define IS_CHIP_TK6280 ( CHIP_ID==CHIP_ID_MT6270A) /* For TK6280 FPGA */
+#define IS_CHIP_MT6583_MD1 ( CHIP_ID==CHIP_ID_MT6583_MD1 )
+#define IS_CHIP_MT6583_MD2 ( CHIP_ID==CHIP_ID_MT6583_MD2 )
+#define IS_CHIP_MT6572 ((CHIP_ID==CHIP_ID_MT6572) || (CHIP_ID==CHIP_ID_MT6582))
+#define IS_CHIP_MT6582 ( CHIP_ID==CHIP_ID_MT6582 )
+#define IS_CHIP_MT6290 ( CHIP_ID==CHIP_ID_MT6290 )
+#define IS_CHIP_MT6595 ( CHIP_ID==CHIP_ID_MT6595 )
+#define IS_CHIP_MT6752_MD1 ( CHIP_ID==CHIP_ID_MT6752_MD1 )
+#define IS_CHIP_MT6752_MD2 ( CHIP_ID==CHIP_ID_MT6752_MD2 )
+#define IS_CHIP_TK6291 ( CHIP_ID==CHIP_ID_TK6291 )
+#define IS_CHIP_MT6755 ( CHIP_ID==CHIP_ID_MT6755 )
+#define IS_CHIP_MT6292 (( CHIP_ID==CHIP_ID_MT6292 ) || (CHIP_ID==CHIP_ID_MT6799))
+#define IS_CHIP_MT6799 ( CHIP_ID==CHIP_ID_MT6799 )
+#define IS_CHIP_MT6293 ((CHIP_ID==CHIP_ID_MT6293) || (CHIP_ID==CHIP_ID_MT6763) || (CHIP_ID==CHIP_ID_MT6739) || (CHIP_ID==CHIP_ID_MT6771) || (CHIP_ID==CHIP_ID_MT6765) || (CHIP_ID==CHIP_ID_TRINITYE1) || (CHIP_ID==CHIP_ID_TRINITYL))
+#define IS_CHIP_MT6763 (CHIP_ID==CHIP_ID_MT6763)
+#define IS_CHIP_MT6739 (CHIP_ID==CHIP_ID_MT6739)
+#define IS_CHIP_MT6771 (CHIP_ID==CHIP_ID_MT6771)
+#define IS_CHIP_MT6765 (CHIP_ID==CHIP_ID_MT6765)
+#define IS_CHIP_MT6295 ((CHIP_ID==CHIP_ID_MT6295M) || (CHIP_ID==CHIP_ID_MT3967) || (CHIP_ID==CHIP_ID_MT6779))
+#define IS_CHIP_MT3967 (CHIP_ID==CHIP_ID_MT3967)
+#define IS_CHIP_MT6779 (CHIP_ID==CHIP_ID_MT6779)
+#define IS_CHIP_MT6297 ((CHIP_ID==CHIP_ID_MT6297) || (CHIP_ID==CHIP_ID_MT6885) || (CHIP_ID==CHIP_ID_MERCURY) || (CHIP_ID==CHIP_ID_MT6873) || (CHIP_ID==CHIP_ID_MT6853) || (CHIP_ID==CHIP_ID_MT6833) || (CHIP_ID==CHIP_ID_MT6880) || (CHIP_ID==CHIP_ID_MT6890) || (CHIP_ID==CHIP_ID_MT2735) || (CHIP_ID==CHIP_ID_MT6893) || (CHIP_ID==CHIP_ID_MT6877) || (CHIP_ID==CHIP_ID_MT6855))
+#define IS_CHIP_MT6885 ((CHIP_ID==CHIP_ID_MT6885) || (CHIP_ID==CHIP_ID_MERCURY) || (CHIP_ID==CHIP_ID_MT6873) || (CHIP_ID==CHIP_ID_MT6853) || (CHIP_ID==CHIP_ID_MT6833) || (CHIP_ID==CHIP_ID_MT6880) || (CHIP_ID==CHIP_ID_MT6890) || (CHIP_ID==CHIP_ID_MT2735) || (CHIP_ID==CHIP_ID_MT6893) || (CHIP_ID==CHIP_ID_MT6877) || (CHIP_ID==CHIP_ID_MT6855))
+#define IS_CHIP_MERCURY (CHIP_ID==CHIP_ID_MERCURY)
+#define IS_CHIP_MT6873 (CHIP_ID==CHIP_ID_MT6873)
+#define IS_CHIP_MT6853 (CHIP_ID==CHIP_ID_MT6853)
+#define IS_CHIP_MT6833 (CHIP_ID==CHIP_ID_MT6833)
+#define IS_CHIP_MT6880 (CHIP_ID==CHIP_ID_MT6880)
+#define IS_CHIP_MT6890 (CHIP_ID==CHIP_ID_MT6890)
+#define IS_CHIP_MT2735 (CHIP_ID==CHIP_ID_MT2735)
+#define IS_CHIP_MT6893 (CHIP_ID==CHIP_ID_MT6893)
+#define IS_CHIP_MT6877 (CHIP_ID==CHIP_ID_MT6877)
+#define IS_CHIP_MT6855 (CHIP_ID==CHIP_ID_MT6855)
+
+/* For L1C usage */
+/* CS3 requirement, CS3 would request us to update them */
+#define IS_CHIP_MT623538 IS_CHIP_MT6238
+#define IS_CHIP_MT6235_SER defined(MT6235B)
+#define IS_CHIP_MT6238_SER ( IS_CHIP_MT623538 && !IS_CHIP_MT6235_SER )
+#define IS_HYPER_SLEEP_MODE_CHIP ((IS_CHIP_MT6238_SER || IS_CHIP_MT6516 || IS_CHIP_MT6268B || IS_CHIP_MT6253 || IS_CHIP_MT6236 || IS_CHIP_MT6256 || IS_CHIP_MT6251 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297) && !defined(MT6516_S00) )
+// SM_EINT_ABORT_DEFECT: 27, 28, 25, 29, 23, (35,38), 6516
+#define IS_SM_EINT_ABORT_DEFECT ( IS_CHIP_MT6227 || IS_CHIP_MT6228 || IS_CHIP_MT6225 || IS_CHIP_MT6229 || IS_CHIP_MT6223 || IS_CHIP_MT6238 )
+// Total settling time = 26M settling time + PLL settling time
+#define IS_SEPARATE_PLL_SETTLING_CHIP ( IS_CHIP_MT6256 || IS_CHIP_MT6251 || IS_CHIP_MT6255 )
+
+#ifdef __HYPER_SLEEP_MODE_CHIP__
+#undef IS_HYPER_SLEEP_MODE_CHIP
+#define IS_HYPER_SLEEP_MODE_CHIP 1
+#endif
+
+/*--------------------*/
+/* For Dual MAC Group */
+/*--------------------*/
+#define IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6270A) )
+
+/*------------------*/
+/* For New 2G Modem */
+/*------------------*/
+#define IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6256) )
+
+/*---------------------*/
+/* For GSM/GPRS Group */
+/*---------------------*/
+#define IS_CHIP_MT6208_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6208) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6205_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6205A) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6205A_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6205A) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6205B_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6205B) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6218_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6218A_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6218B_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6218B) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6219_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6219) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6227_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6228_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6228) )
+#define IS_CHIP_MT6225_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6225) )
+#define IS_CHIP_MT6295_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6295M) )
+#define IS_CHIP_MT6297_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6297) )
+#define IS_CHIP_MT6885_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6885) )
+#define IS_CHIP_MT6853_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6853) )
+
+
+/*----------------------------------*/
+/* For Dual DSP Group (EGPRS Group) */
+/*----------------------------------*/
+#define IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6229) || IS_CHIP_SER(CHIP_ID_MT6223) || IS_CHIP_SER(CHIP_ID_MT6238) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+/* For SAIC group */
+/* Be careful!! MT6223 is a special chip without EDGE */
+#define IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6223) || IS_CHIP_SER(CHIP_ID_MT6238) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+#define IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6238) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+#define IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6268A) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+/* Be careful!! MT6253(T) is a special chip without EDGE */
+#define IS_SAIC_CHIP_MT6253T_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6253T) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6236) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+#define IS_SAIC_CHIP_MT6253_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6253) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6236) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+#define IS_EDGE_SAIC_CHIP_MT6236_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6236) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+
+/*-------------------*/
+/* For 2G RxD Group */
+/*-------------------*/
+#define IS_2GRXD_CHIP_MT6765_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6765) )
+
+/*----------------------*/
+/* For 2G MMDFE Group */
+/*----------------------*/
+#define IS_MMDFE_CHIP_MT6297_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6297) )
+
+/*--------------------*/
+/* For Specific Group */
+/*--------------------*/
+/* For SmartPhone Group */
+#define IS_SMARTPHONE_CHIP_TK6516_AND_LATTER_VERSION ( IS_CHIP_TK6516 || IS_CHIP_MT6516 )
+/* For 65NM chip Group */
+#define IS_65NM_CHIP ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6268A) || IS_CHIP_SER(CHIP_ID_MT6256) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6276) )
+/* For 65NM with BSI/BPI power down group*/
+#define IS_65NM_CHIP_BSI_BPI_PWN ( IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_SER(CHIP_ID_MT6256) )
+/* For Support us counter chip Group */
+#define IS_USC_CHIP ( IS_CHIP_MT6268B || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6270A) || IS_CHIP_MT6268H || IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) )
+/* For TDMA 8R/(6T), AuxADC chip */
+#define IS_NEW_TDMA_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) || IS_CHIP_MT6252 )
+/* For chip with 32-bit of BSI_ENA */
+#define IS_BSI_REG_32_BIT_CHIP ( IS_CHIP_MT6268T || IS_CHIP_MT6268 || IS_CHIP_MT6268H || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) )
+/* For chip with 32-bit of BPI_ENA */
+#define IS_BPI_REG_32_BIT_CHIP ( IS_CHIP_MT6268T || IS_CHIP_MT6268 || IS_CHIP_MT6268H || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) )
+/* For chip with 48-bit of BPI_DATA */
+#define IS_BPI_DATA_48_BIT_CHIP ( IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 )
+/* For chip with 32-bit of BPI_DATA */
+#define IS_BPI_DATA_32_BIT_CHIP ( !IS_BPI_DATA_48_BIT_CHIP )
+/* For chip with 32-bit of BSI_CON */
+#define IS_BSI_CON_32_BIT_CHIP ( IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293)
+/* For HW 8RWIN PM chip */
+#define IS_HW_8RXWIN_PM_SUPPORT_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) || IS_CHIP_MT6252 )
+/* For SOC chip Group */
+#define IS_SOC_CHIP ( IS_CHIP_SER(CHIP_ID_MT6253) || (IS_CHIP_SER(CHIP_ID_MT6256)&&(!IS_CHIP_MT6583_MD1)&&(!IS_CHIP_MT6583_MD2)&&(!IS_CHIP_MT6572)&&(!IS_CHIP_MT6290)&&(!IS_CHIP_MT6595)&&(!IS_CHIP_MT6752_MD1)&&(!IS_CHIP_MT6752_MD2)&&(!IS_CHIP_TK6291)&&(!IS_CHIP_MT6755)&&(!IS_CHIP_MT6292)&&(!IS_CHIP_MT6293)) )
+/* For 3G group */
+#define IS_3G_CHIP ( IS_CHIP_MT6268 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6276) )
+/* For EDGE MTBF PSHO group */
+#define IS_EDGE_MTBF_PSHO_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) )
+/* For EDGE RTTI FANR group */
+#define IS_EDGE_RTTI_FANR_CHIP ( 0 ) // temp, RTTI and FANR is still under development
+
+#define IS_FM_ON_26M_CHIP ( IS_CHIP_MT6268 || IS_CHIP_MT6236 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+#define IS_DUAL_DSP_CHIP ( IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION && !(IS_CACHE_DSP_SUPPORT || IS_DSP_ARCHITECTURE_V4_SUPPORT) )
+#define IS_DUAL_MAC_DSP_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) )
+#define IS_FD216_DSP_CHIP ( !IS_DUAL_MAC_DSP_CHIP )
+/*IS_CHIP_EQ34311 (DSP central weighting window) is defined for L1C to adjust the upper bound to recalibrate 32k Xtal : 1=> upper bound 24; 0=> upper bound 32*/
+#define IS_CHIP_EQ34311 ( IS_CHIP_MT6225 || IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION )
+/* Modified By James, to avoid VC++ bug of that defined(MT6217) is always false */
+#define IS_CHIP_MT6218B_AN2DN ( (defined MT6218B_AN) || (defined MT6218B_BN) || (defined MT6218B_CN) || (defined MT6218B_DN) )
+#define IS_CHIP_MT6218B_EN ( (defined MT6218B_EN) )
+#define IS_CHIP_MT6218B_FN ( (defined MT6218B_FN) )
+#define IS_CHIP_MT6219_AV ( (defined MT6219_AV) )
+#define IS_CHIP_MT6219_BV ( (defined MT6219_BV) )
+#define IS_CHIP_MT6219_EV ( (defined MT6219_EV) )
+#define IS_CHIP_MT6217 ( (defined CHIP_MT6217) || (defined MT6217) )
+#define IS_CHIP_MT6227_S00 ( (defined MT6227_S00) || (defined MT6226_S00) || (defined MT6226M_S00) )
+#define IS_CHIP_MT6227_S01 ( (defined MT6227_S01) || (defined MT6226_S01) || (defined MT6226M_S01) ) // !Caution:Plz also take care of chip MT6226 & MT6226M as using this compile option
+#define IS_CHIP_MT6227_S02 ( (defined MT6227_S02) || (defined MT6226_S02) || (defined MT6226M_S02) ) // !Caution:Plz also take care of chip MT6226 & MT6226M as using this compile option
+#define IS_CHIP_MT6227_D00 ( (defined MT6227D_S00) || (defined MT6226D_S00) || (defined MT6227DS_S00) || (defined MT6226DS_S00) )
+#define IS_CHIP_MT6228_S00 ( (defined MT6228_S00) )
+#define IS_CHIP_MT6228_S01 ( (defined MT6228_S01) )
+#define IS_CHIP_MT6228_S02 ( (defined MT6228_S02) )
+#define IS_CHIP_MT6225_S00 ( (defined MT6225_S00) )
+#define IS_CHIP_MT6229_FPGA1 ( defined MT6229_FPGA1 )
+#define IS_CHIP_MT6229_FPGA2 ( defined MT6229_FPGA2 )
+#define IS_CHIP_MT6229_FPGA3 ( defined MT6229_FPGA3 )
+#define IS_CHIP_MT6229_S00 ( (defined MT6229_S00) || (defined MT6230_S00) )
+#define IS_CHIP_MT6229_S01 ( (defined MT6229_S01) || (defined MT6230_S01) )
+#define IS_CHIP_MT6229_S02 ( (defined MT6229_S02) || (defined MT6230_S02) )
+#define IS_CHIP_MT6223_S00 ( (defined MT6223_S00) || (defined MT6223P_S00) )
+#define IS_CHIP_MT6268_S00 ( (defined MT6268_S00) )
+#define IS_CHIP_MT6256_S00 ( (defined MT6256_S00) )
+#define IS_CHIP_MT6256_S01 ( (defined MT6256_S01) )
+#define IS_CHIP_MT6256_S02 ( (defined MT6256_S02) )
+#define IS_CHIP_MT6251_S00 ( (defined MT6251_S00) )
+#define IS_CHIP_MT6252_S00 ( (defined MT6253E_S00) || (defined MT6253L_S00) || (defined MT6252_S00) || (defined MT6252H_S00) )
+#define IS_CHIP_MT6252_S01 ( (defined MT6253E_S01) || (defined MT6253L_S01) || (defined MT6252_S01) || (defined MT6252H_S01) )
+#define IS_CHIP_MT6270A_E1 ( (defined MT6270A_S00) && !(defined __MT6270A_FPGA_HW_VER_E2__) )
+#define IS_CHIP_MT6270A_E2 ( (defined MT6270A_S00) && (defined __MT6270A_FPGA_HW_VER_E2__) )
+#define IS_CHIP_MT6276_S00 ( (defined MT6276_S00) )
+#define IS_CHIP_MT6276_S01 ( (defined MT6276_S01) )
+#define IS_CHIP_MT6573_S00 ( (defined MT6573_S00) )
+#define IS_CHIP_MT6573_S01 ( (defined MT6573_S01) )
+#define IS_CHIP_MT6575_S00 ( (defined MT6575_S00) )
+#define IS_CHIP_MT6280_S00 ( (defined MT6280_S00) )
+#define IS_CHIP_MT6280_S01 ( (defined MT6280_S01) )
+#define IS_CHIP_MT6290_S00 ( (defined MT6290_S00) )
+#define IS_CHIP_MT6290_S01 ( (defined MT6290_S01) )
+
+/* For temparially modification */
+/* Remove the compile option once MT6229 has been verified */
+/* For FPGA old architecture without IR and Exchange Buffer on External SRAM */
+/* 1: Full Function 6229 0: For FPGA old architecture */
+#define IS_DSP_FULLFUNCTION_OF_6229 0
+#define IS_EPSK_TX_SUPPORT (defined __EPSK_TX__)
+#define IS_PS_EPSK_TX_DISABLE (defined __EPSK_TX_SW_SWITCH_OFF__)
+/*.......................................................*/
+
+#ifndef CHIP_ID
+ #ifdef FPGA
+/*FPGA*/ #define CHIP_ID CHIP_ID_FPGA
+ #endif
+ #ifdef MT6208
+/*MT6208*/ #define CHIP_ID CHIP_ID_MT6208
+ #endif
+ #ifdef MT6205
+/*MT6205*/ #define CHIP_ID CHIP_ID_MT6205A
+ #endif
+ #ifdef MT6205A
+/*MT6205A*/ #define CHIP_ID CHIP_ID_MT6205A
+ #endif
+ #ifdef MT6205B
+/*MT6205B*/ #define CHIP_ID CHIP_ID_MT6205B
+ #endif
+ #ifdef MT6218
+/*MT6218*/ #define CHIP_ID CHIP_ID_MT6218A
+ #endif
+ #ifdef MT6218A
+/*MT6218A*/ #define CHIP_ID CHIP_ID_MT6218A
+ #endif
+ #ifdef MT6218B
+/*MT6218B*/ #define CHIP_ID CHIP_ID_MT6218B
+ #endif
+ #ifdef MT6219
+/*MT6219*/ #define CHIP_ID CHIP_ID_MT6219
+ #endif
+ #ifdef MT6217
+/*MT6217*/ #define CHIP_ID CHIP_ID_MT6218B
+ #endif
+ #ifdef MT6228
+/*MT6228*/ #define CHIP_ID CHIP_ID_MT6228
+ #endif
+ #ifdef MT6229
+/*MT6229*/ #define CHIP_ID CHIP_ID_MT6229
+ #endif
+ #ifdef MT6230
+/*MT6229*/ #define CHIP_ID CHIP_ID_MT6229
+ #endif
+ #ifdef MT6226 /* For L1 MT6226==MT6227 */
+/*MT6226*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6227
+/*MT6227*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6226M /* For L1 MT6226M==MT6227 */
+/*MT6226M*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6226D /* For L1 MT6226D==MT6227 */
+/*MT6226*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6227D /* For L1 MT6227D==MT6227 */
+/*MT6227*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6226DS /* For L1 MT6226DS==MT6227 */
+/*MT6226*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6227DS /* For L1 MT6227DS==MT6227 */
+/*MT6227*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6225
+/*MT6225*/ #define CHIP_ID CHIP_ID_MT6225
+ #endif
+ #ifdef MT6268T
+ #ifdef __DSP_FCORE4__
+/*MT6268T*/ #define CHIP_ID CHIP_ID_MT6268T_DMAC
+ #else
+/*MT6268T*/ #define CHIP_ID CHIP_ID_MT6268T
+ #endif
+ #endif
+ #ifdef MT6268H /* For L1 MT6268H==MT6268T*/
+/*MT6268H*/ #define CHIP_ID CHIP_ID_MT6268T
+ #endif
+ #ifdef MT6223
+/*MT6223*/ #define CHIP_ID CHIP_ID_MT6223
+ #endif
+ #ifdef MT6223P /* For L1 MT6223P==MT6223 */
+/*MT6223*/ #define CHIP_ID CHIP_ID_MT6223
+ #endif
+ #ifdef MT6238
+/*MT6238*/ #define CHIP_ID CHIP_ID_MT6238
+ #endif
+ #ifdef MT6235B /* For L1 MT6235B==MT6238 */
+/*MT6235B*/ #define CHIP_ID CHIP_ID_MT6238
+ #endif
+ #ifdef MT6239 /* For L1 MT6239==MT6238 */
+/*MT6239*/ #define CHIP_ID CHIP_ID_MT6238
+ #endif
+ #ifdef TK6516
+/*TK6516*/ #define CHIP_ID CHIP_ID_TK6516
+ #endif
+ #ifdef MT6268A
+/*MT6268A*/ #define CHIP_ID CHIP_ID_MT6268A
+ #endif
+ #ifdef MT6268
+/*MT6268*/ #define CHIP_ID CHIP_ID_MT6268
+ #endif
+ #ifdef MT6516
+/*MT6516*/ #define CHIP_ID CHIP_ID_MT6516
+ #endif
+ #ifdef MT6253T
+/*MT6253T*/ #define CHIP_ID CHIP_ID_MT6253T
+ #endif
+ #ifdef MT6253L
+/*MT6253*/ #define CHIP_ID CHIP_ID_MT6252L
+ #endif
+ #ifdef MT6270A
+/*MT6270A*/ #define CHIP_ID CHIP_ID_MT6270A
+ #endif
+ #ifdef TK6280
+/*TK6280*/ #define CHIP_ID CHIP_ID_MT6270A /* For TK6280 FPGA development, The 2G part is similar to MT6270A FPGA */
+ #endif
+ #ifdef MT6583
+ #if defined(__MD1__)
+/*MT6583*/ #define CHIP_ID CHIP_ID_MT6583_MD1
+ #elif defined(__MD2__)
+/*MT6583*/ #define CHIP_ID CHIP_ID_MT6583_MD2
+ #else
+#error
+ #endif
+ #endif
+ #ifdef MT6752
+ #if defined(__MD1__)
+/*MT6583*/ #define CHIP_ID CHIP_ID_MT6752_MD1
+ #elif defined(__MD2__)
+/*MT6583*/ #define CHIP_ID CHIP_ID_MT6752_MD2
+ #else
+#error
+ #endif
+ #endif
+
+ /* UESIM-MOLY */
+ #if defined(__UE_SIMULATOR__)
+ #ifdef L1D_TEST
+/*MT6290*/ #undef CHIP_ID
+/*MT6290*/ #define CHIP_ID CHIP_ID_MT6290
+ #else
+/*MT6280*/ #undef CHIP_ID
+/*MT6280*/ #define CHIP_ID CHIP_ID_MT6280
+ #endif
+ #endif
+#endif
+
+/* default setting */
+#ifndef CHIP_ID
+ #ifdef CHIP_TARGET
+/*CHIP*/ #define CHIP_ID CHIP_ID_MT6208
+ #else
+/*FPGA*/ #define CHIP_ID CHIP_ID_FPGA
+ #endif
+#endif
+
+//CH modify for simulation environment
+#ifdef L1_SIM
+ #if defined(MT6205)
+#define SIM_MT6205 MT6205
+ #elif defined(MT6208)
+#define SIM_MT6208 MT6208
+ #elif defined(MT6218)
+#define SIM_MT6218 MT6218
+ #elif defined(MT6229)
+#define SIM_MT6229 MT6229
+ #elif defined(MT6268T)
+#define SIM_MT6229 MT6268T
+ #elif defined(MT6268)
+#define SIM_MT6229 MT6268
+ #elif defined(MT6268H)
+#define SIM_MT6229 MT6268T
+ #elif defined(MT6583)
+#define SIM_MT6229 MT6583
+ #elif defined(MT6752)
+#define SIM_MT6229 MT6752
+ #elif defined(MT6291)
+#define SIM_MT6229 TK6291
+ #elif defined(MT6293)
+#define SIM_MT6229 MT6293
+ #elif defined(MT6763)
+#define SIM_MT6229 MT6763
+ #elif defined(MT6739)
+#define SIM_MT6229 MT6739
+ #elif defined(MT6771)
+#define SIM_MT6229 MT6771
+ #elif defined(MT6765)
+#define SIM_MT6229 MT6765
+ #elif defined(MT6295M)
+#define SIM_MT6229 MT6295M
+ #elif defined(MT3967)
+#define SIM_MT6229 MT3967
+ #elif defined(MT6779)
+#define SIM_MT6229 MT6779
+ #elif ((defined(MT6297)) || (defined MT6885) || (defined MERCURY) || (defined MT6873) || (defined MT6853) || (defined MT6833) || (defined MT6880) || (defined MT6890) || (defined MT2735) || (defined MT6893) || (defined MT6877) || (defined MT6855))
+#define SIM_MT6229 MT3967
+// #else
+//#error
+ #endif
+#endif
+
+/*===============================================================================================*/
+
+/*------------------------------------------*/
+/* Compile Option : */
+/* ( 1) RF_BRIGHT2 */
+/* ( 2) RF_BRIGHT4 */
+/* ( 3) RF_AERO */
+/* ( 4) RF_AERO1PLUS */
+/* ( 5) RF_MT6116 */
+/* ( 6) RF_MT6119 */
+/* ( 7) RF_MT6119C */
+/* ( 8) RF_MT6129A */
+/* ( 9) RF_MT6129B */
+/* (10) RF_MT6129C */
+/* (11) RF_MT6129D */
+/* (12) RF_MT6139B */
+/* (13) RF_MT6139C */
+/* (14) RF_MT6140A */
+/* (16) RF_MT6139E */
+/* ------------- */
+/* (*) BRIGHT2_RF */
+/*------------------------------------------*/
+/* Use in L1D : */
+/* ( 1) IS_RF_BRIGHT2 */
+/* ( 2) IS_RF_BRIGHT4 */
+/* ( 3) IS_RF_AERO */
+/* ( 4) IS_RF_AERO1PLUS */
+/* ( 5) IS_RF_MT6116 */
+/* ( 6) IS_RF_MT6119 */
+/* ( 7) IS_RF_MT6119C */
+/* ( 8) IS_RF_MT6129A */
+/* ( 9) IS_RF_MT6129B */
+/* (10) IS_RF_MT6129C */
+/* (11) IS_RF_MT6129D */
+/*------------------------------------------*/
+
+#define RF_ID_BRIGHT2 0x00000001
+#define RF_ID_BRIGHT4 0x00000002
+#define RF_ID_AERO 0x00000004
+#define RF_ID_AERO1PLUS 0x00000008
+#define RF_ID_POLARIS1 0x00000010
+#define RF_ID_POLARIS2 0x00000020
+#define RF_ID_SKY74045 0x00000040
+#define RF_ID_BRIGHT5P 0x00000080
+#define RF_ID_MT6116 0x00000100
+#define RF_ID_MT6119 0x00000200
+#define RF_ID_MT6119C 0x00000400
+#define RF_ID_MT6129A 0x00000800
+#define RF_ID_MT6129B 0x00001000
+#define RF_ID_MT6129C 0x00002000
+#define RF_ID_MT6129D 0x00004000
+#define RF_ID_MT6139B 0x00008000
+#define RF_ID_MT6139C 0x00010000
+#define RF_ID_MT6140A 0x00020000
+#define RF_ID_SKY74117 0x00040000
+#define RF_ID_SKY74400 0x00080000
+#define RF_ID_AERO2 0x00100000
+#define RF_ID_MT6140B 0x00200000
+#define RF_ID_MT6139E 0x00800000
+#define RF_ID_SKY74137 0x01000000
+#define RF_ID_MT6140C 0x02000000
+#define RF_ID_GRF6201 0x04000000
+#define RF_ID_IRFS3001 0x08000000
+#define RF_ID_MT6140D 0x10000000
+#define RF_ID_AG2550 0x10000001
+#define RF_ID_AERO2E 0x10000002
+#define RF_ID_QS1000 0x10000003
+#define RF_ID_QS1001 0x10000004
+#define RF_ID_AD6548 0x10000005
+#define RF_ID_AD6546 0x10000006
+#define RF_ID_CMOSEDGE 0x10000007
+#define RF_ID_MTKSOC1 0x10000008
+#define RF_ID_MT6256RF 0x10000009
+#define RF_ID_MT6251RF 0x1000000a
+#define RF_ID_MT6253ELRF 0x1000000b // the same as MT6252RF
+#define RF_ID_MT6252RF 0x1000000c
+#define RF_ID_MT6162 0x1000000d
+#define RF_ID_MT6163 0x1000000e
+#define RF_ID_MT6255RF 0x1000000f
+#define RF_ID_MT6250RF 0x10000010
+#define RF_ID_MT6280RF 0x10000011
+#define RF_ID_MT6167 0x10000012
+#define RF_ID_MT6160 0x10000013
+#define RF_ID_MT6166 0x10000014
+#define RF_ID_MT6169 0x10000015
+#define RF_ID_MT6165 0x10000016
+#define RF_ID_MT6261RF 0x10000017
+#define RF_ID_MT6580RF 0x10000018
+#define RF_ID_MT6176 0x10000019
+#define RF_ID_MT6179 0x1000001a
+#define RF_ID_MT6570RF 0x1000001b
+#define RF_ID_MT6177L 0x1000001c
+#define RF_ID_MT6177M 0x1000001d
+#define RF_ID_TRINITYE1 0x1000001e
+#define RF_ID_TRINITYL 0x1000001f
+#define RF_ID_MT6186 0x10000020
+#define RF_ID_MT6186M 0x10000021
+#define RF_ID_MT6190T 0x10000022
+#define RF_ID_MT6190 0x10000023
+#define RF_ID_MT6190M 0x10000024
+#define RF_ID_MT6195 0x10000025
+
+
+
+
+
+/* ------------------------------------------- */
+/* Note that the RF ID should be named */
+/* as a variable rather than BITMask */
+/* from 0x10000000, */
+/* the next RF ID should be 0x10000007...etc */
+/* ------------------------------------------- */
+
+#ifdef L1_SIM
+ #ifdef BRIGHT2_EVB
+/*BRIGHT2*/ #define RF_ID RF_ID_BRIGHT2
+ #endif
+ #ifdef BRIGHT4_EVB
+/*BRIGHT4*/ #define RF_ID RF_ID_BRIGHT4
+ #endif
+ #ifdef BRIGHT5P_EVB
+/*BRIGHT5P*/#define RF_ID RF_ID_BRIGHT5P
+ #endif
+ #ifdef AERO_EVB
+/*AERO*/ #define RF_ID RF_ID_AERO
+ #endif
+ #ifdef SPRING_EVB
+/*AERO*/ #define RF_ID RF_ID_AERO
+ #endif
+ #ifdef POLARIS1_EVB
+/*RFMD*/ #define RF_ID RF_ID_POLARIS1
+ #endif
+ #ifdef MT6119_EVB
+/*MT6119*/ #define RF_ID RF_ID_MT6119
+ #endif
+ #ifdef FOUNTAIN_EVB
+/*MT6119*/ #define RF_ID RF_ID_MT6119
+ #endif
+ #ifdef FOUNTAIN2_EVB
+/*MT6119*/ #define RF_ID RF_ID_MT6119C
+ #endif
+ #ifdef MT6129A_EVB
+/*MT6129A*/ #define RF_ID RF_ID_MT6129A
+ #endif
+ #ifdef OCEAN_EVB
+/*MT6129C*/ #define RF_ID RF_ID_MT6129C
+ #endif
+ #ifdef MT6139B_EVB
+/*MT6139B*/ #define RF_ID RF_ID_MT6139B
+ #endif
+ #ifdef MT6139C_EVB
+/*MT6139C*/ #define RF_ID RF_ID_MT6139C
+ #endif
+ #ifdef MT6139E_EVB
+/*MT6139E*/ #define RF_ID RF_ID_MT6139E
+ #endif
+ #ifdef MT6140A_EVB
+/*MT6140A*/ #define RF_ID RF_ID_MT6140A
+ #endif
+ #ifdef SKY74045_EVB
+/*SKY74045*/#define RF_ID RF_ID_SKY74045
+ #endif
+ #ifdef SKY74117_EVB
+/*SKY74117*/#define RF_ID RF_ID_SKY74117
+ #endif
+ #ifdef SKY74137_EVB
+/*SKY74137*/#define RF_ID RF_ID_SKY74137
+ #endif
+ #ifdef GRF6201_EVB
+/*GRF6201*/ #define RF_ID RF_ID_GRF6201
+ #endif
+ #ifdef IRFS3001_EVB
+/*IRFS3001*/#define RF_ID RF_ID_IRFS3001
+ #endif
+ #ifdef AD6546_EVB
+/*AD6546*/ #define RF_ID RF_ID_AD6546
+ #endif
+#endif
+
+#define IS_RF_BRIGHT2 ( RF_ID==RF_ID_BRIGHT2 )
+#define IS_RF_BRIGHT4 ( RF_ID==RF_ID_BRIGHT4 )
+#define IS_RF_BRIGHT5P ( RF_ID==RF_ID_BRIGHT5P )
+#define IS_RF_AERO ( RF_ID==RF_ID_AERO )
+#define IS_RF_AERO1PLUS ( RF_ID==RF_ID_AERO1PLUS )
+#define IS_RF_POLARIS1 ( RF_ID==RF_ID_POLARIS1 )
+#define IS_RF_MT6116 ( RF_ID==RF_ID_MT6116 )
+#define IS_RF_MT6119 ( RF_ID==RF_ID_MT6119 )
+#define IS_RF_MT6119C ( RF_ID==RF_ID_MT6119C )
+#define IS_RF_MT6129A ( RF_ID==RF_ID_MT6129A )
+#define IS_RF_MT6129B ( RF_ID==RF_ID_MT6129B )
+#define IS_RF_MT6129C ( RF_ID==RF_ID_MT6129C )
+#define IS_RF_MT6129D ( RF_ID==RF_ID_MT6129D )
+#define IS_RF_MT6139B ( RF_ID==RF_ID_MT6139B )
+#define IS_RF_MT6139C ( RF_ID==RF_ID_MT6139C )
+#define IS_RF_MT6139E ( RF_ID==RF_ID_MT6139E )
+#define IS_RF_MT6140A ( RF_ID==RF_ID_MT6140A )
+#define IS_RF_MT6140B ( RF_ID==RF_ID_MT6140B )
+#define IS_RF_MT6140C ( RF_ID==RF_ID_MT6140C )
+#define IS_RF_MT6140D ( RF_ID==RF_ID_MT6140D )
+#define IS_RF_CMOSEDGE ( RF_ID==RF_ID_CMOSEDGE )
+#define IS_RF_MTKSOC1 ( RF_ID==RF_ID_MTKSOC1 && CHIP_ID==CHIP_ID_MT6253 )
+#define IS_RF_MTKSOC1T ( RF_ID==RF_ID_MTKSOC1 && CHIP_ID==CHIP_ID_MT6253T )
+#define IS_RF_MT6253ELRF ( RF_ID==RF_ID_MT6252RF )
+#define IS_RF_MT6252RF ( RF_ID==RF_ID_MT6252RF )
+#define IS_RF_SKY74045 ( RF_ID==RF_ID_SKY74045 )
+#define IS_RF_SKY74117 ( RF_ID==RF_ID_SKY74117 )
+#define IS_RF_SKY74400 ( RF_ID==RF_ID_SKY74400 )
+#define IS_RF_AERO2 ( RF_ID==RF_ID_AERO2 )
+#define IS_RF_SKY74137 ( RF_ID==RF_ID_SKY74137 )
+#define IS_RF_GRF6201 ( RF_ID==RF_ID_GRF6201 )
+#define IS_RF_IRFS3001 ( RF_ID==RF_ID_IRFS3001 )
+#define IS_RF_AD6548 ( RF_ID==RF_ID_AD6548 )
+#define IS_RF_AD6546 ( RF_ID==RF_ID_AD6546 )
+#define IS_RF_MT6256RF ( RF_ID==RF_ID_MT6256RF )
+#define IS_RF_MT6255RF ( RF_ID==RF_ID_MT6255RF )
+#define IS_RF_MT6251RF ( RF_ID==RF_ID_MT6251RF )
+#define IS_RF_MT6162 ( ((defined RF_ID) && RF_ID==RF_ID_MT6162) || ((defined UL1D_RF_ID) && UL1D_RF_ID==UL1D_RF_ID_MT6162) )
+#define IS_RF_MT6163 ( RF_ID==RF_ID_MT6163 )
+#define IS_RF_MT6250RF ( RF_ID==RF_ID_MT6250RF )
+#define IS_RF_MT6280RF ( RF_ID==RF_ID_MT6280RF )
+#define IS_RF_MT6167 ( RF_ID==RF_ID_MT6167 )
+#define IS_RF_MT6166 ( RF_ID==RF_ID_MT6166 )
+#define IS_RF_MT6169 ( RF_ID==RF_ID_MT6169 )
+#define IS_RF_MT6165 ( RF_ID==RF_ID_MT6165 )
+#define IS_RF_MT6176 ( RF_ID==RF_ID_MT6176 )
+#define IS_RF_MT6179 ( RF_ID==RF_ID_MT6179 )
+#define IS_RF_MT6177L ( RF_ID==RF_ID_MT6177L )
+#define IS_RF_MT6177M ( RF_ID==RF_ID_MT6177M )
+#define IS_RF_TRINITYE1 ( RF_ID==RF_ID_TRINITYE1 )
+#define IS_RF_TRINITYL ( RF_ID==RF_ID_TRINITYL )
+#define IS_RF_MT6186 ( RF_ID==RF_ID_MT6186 )
+#define IS_RF_MT6186M ( RF_ID==RF_ID_MT6186M )
+#define IS_RF_MT6190T (( RF_ID==RF_ID_MT6190T )||( RF_ID==RF_ID_MT6190 )||( RF_ID==RF_ID_MT6190M )) || ( RF_ID == RF_ID_MT6195 )
+#define IS_RF_MT6190 (( RF_ID==RF_ID_MT6190 )||( RF_ID==RF_ID_MT6190M )) || ( RF_ID == RF_ID_MT6195 )
+#define IS_RF_MT6190M ( RF_ID==RF_ID_MT6190M )
+#define IS_RF_MT6195 ( RF_ID==RF_ID_MT6195 )
+
+/*.......................................................*/
+
+#ifndef RF_ID
+ #ifdef BRIGHT2_RF
+/*BRIGHT2*/ #define RF_ID RF_ID_BRIGHT2
+ #endif
+ #ifdef BRIGHT4_RF
+/*BRIGHT4*/ #define RF_ID RF_ID_BRIGHT4
+ #endif
+ #ifdef BRIGHT5P_RF
+/*BRIGHT5P*/#define RF_ID RF_ID_BRIGHT5P
+ #endif
+ #ifdef AERO_RF
+/*AERO*/ #define RF_ID RF_ID_AERO
+ #endif
+ #ifdef AERO1PLUS_RF
+/*AERO*/ #define RF_ID RF_ID_AERO1PLUS
+ #endif
+ #ifdef POLARIS1_RF
+/*RFMD*/ #define RF_ID RF_ID_POLARIS1
+ #endif
+ #ifdef MT6116_RF
+/*MT6116*/ #define RF_ID RF_ID_MT6116
+ #endif
+ #ifdef MT6119_RF
+/*MT6119*/ #define RF_ID RF_ID_MT6119
+ #endif
+ #ifdef MT6119C_RF
+/*MT6119*/ #define RF_ID RF_ID_MT6119C
+ #endif
+ #ifdef MT6129A_RF
+/*MT6129A*/ #define RF_ID RF_ID_MT6129A
+ #endif
+ #ifdef MT6129B_RF
+/*MT6129B*/ #define RF_ID RF_ID_MT6129B
+ #endif
+ #ifdef MT6129C_RF
+/*MT6129C*/ #define RF_ID RF_ID_MT6129C
+ #endif
+ #ifdef MT6129D_RF
+/*MT6129D*/ #define RF_ID RF_ID_MT6129D
+ #endif
+ #ifdef MT6139B_RF
+/*MT6139B*/ #define RF_ID RF_ID_MT6139B
+ #endif
+ #ifdef MT6139C_RF
+/*MT6139C*/ #define RF_ID RF_ID_MT6139C
+ #endif
+ #ifdef MT6139E_RF
+/*MT6139E*/ #define RF_ID RF_ID_MT6139E
+ #endif
+ #ifdef MT6140A_RF
+/*MT6140A*/ #define RF_ID RF_ID_MT6140A
+ #endif
+ #ifdef MT6140B_RF
+/*MT6140B*/ #define RF_ID RF_ID_MT6140B
+ #endif
+ #ifdef MT6140C_RF
+/*MT6140C*/ #define RF_ID RF_ID_MT6140C
+ #endif
+ #ifdef MT6140D_RF
+/*MT6140D*/ #define RF_ID RF_ID_MT6140D
+ #endif
+ #ifdef CMOSEDGE_RF
+/*CMOSEDGE*/#define RF_ID RF_ID_CMOSEDGE
+ #endif
+ #ifdef MTKSOC1_RF
+/*MTKSOC1*/ #define RF_ID RF_ID_MTKSOC1
+ #endif
+ #ifdef MT6256RF_RF
+/*MT6256RF*/#define RF_ID RF_ID_MT6256RF
+ #endif
+ #ifdef MT6255RF_RF
+/*MT6255RF*/#define RF_ID RF_ID_MT6255RF
+ #endif
+ #ifdef MT6250RF_RF
+/*MT6250RF*/#define RF_ID RF_ID_MT6250RF
+ #endif
+ #ifdef MT6280RF_2G_RF
+/*MT6280RF*/#define RF_ID RF_ID_MT6280RF
+ #endif
+ #ifdef MT6169_2G_RF
+/*MT6169*/ #define RF_ID RF_ID_MT6169
+ #endif
+ #ifdef MT6166_2G_RF
+/*MT6166*/ #define RF_ID RF_ID_MT6166
+ #endif
+ #ifdef MT6165_2G_RF
+/*MT6165*/ #define RF_ID RF_ID_MT6165
+ #endif
+ #ifdef MT6176_2G_RF
+/*MT6176*/ #define RF_ID RF_ID_MT6176
+ #endif
+ #ifdef MT6179_2G_RF
+/*MT6179*/ #define RF_ID RF_ID_MT6179
+ #endif
+ #ifdef MT6177L_2G_RF
+/*MT6177L*/ #define RF_ID RF_ID_MT6177L
+ #endif
+ #ifdef MT6177M_2G_RF
+/*MT6177M*/ #define RF_ID RF_ID_MT6177M
+ #endif
+ #ifdef TRINITYE1_2G_RF
+/*Trinity*/ #define RF_ID RF_ID_TRINITYE1
+ #endif
+ #ifdef TRINITYL_2G_RF
+/*Trinity*/ #define RF_ID RF_ID_TRINITYL
+ #endif
+ #ifdef MT6185M_2G_RF
+/*Trinity*/ #define RF_ID RF_ID_TRINITYL
+ #endif
+ #ifdef MT6186_2G_RF
+/*Trinity*/ #define RF_ID RF_ID_MT6186
+ #endif
+ #ifdef MT6186M_2G_RF
+/*Trinity*/ #define RF_ID RF_ID_MT6186M
+ #endif
+ #ifdef TRINITYE1_RF
+// #define RF_ID RF_ID_TRINITYE1
+ #endif
+ #ifdef MT6190T_2G_RF
+/*MT6190T*/ #define RF_ID RF_ID_MT6190T
+ #endif
+ #ifdef MT6190_2G_RF
+/*MT6190*/ #define RF_ID RF_ID_MT6190
+ #endif
+ #ifdef MT6190M_2G_RF
+/*MT6190M*/ #define RF_ID RF_ID_MT6190M
+ #endif
+ #ifdef MT6195_2G_RF
+/*COLUMBUSP*/ #define RF_ID RF_ID_MT6195
+ #endif
+ #ifdef MT6251RF_RF
+/*MT6251RF*/#define RF_ID RF_ID_MT6251RF
+ #endif
+ #ifdef MT6253ELRF_RF
+/*MT6253EL*/#define RF_ID RF_ID_MT6252RF
+ #endif
+ #ifdef MT6252RF_RF
+/*MT6252RF*/#define RF_ID RF_ID_MT6252RF
+ #endif
+ #ifdef SKY74045_RF
+/*SKY74045*/#define RF_ID RF_ID_SKY74045
+ #endif
+ #ifdef SKY74117_RF
+/*SKY74117*/#define RF_ID RF_ID_SKY74117
+ #endif
+ #ifdef SKY74400_RF
+/*SKY74400*/#define RF_ID RF_ID_SKY74400
+ #endif
+ #ifdef AERO2_RF
+/*AERO2*/ #define RF_ID RF_ID_AERO2
+ #endif
+ #ifdef SKY74137_RF
+/*SKY74137*/#define RF_ID RF_ID_SKY74137
+ #endif
+ #ifdef GRF6201_RF
+/*GRF6201*/ #define RF_ID RF_ID_GRF6201
+ #endif
+ #ifdef IRFS3001_RF
+/*IRFS3001*/#define RF_ID RF_ID_IRFS3001
+ #endif
+ #ifdef AD6548_RF
+/*AD6548*/ #define RF_ID RF_ID_AD6548
+ #endif
+ #ifdef AD6546_RF
+/*AD6546*/ #define RF_ID RF_ID_AD6546
+ #endif
+ #ifdef MT6162_RF
+/*MT6162*/ #define RF_ID RF_ID_MT6162
+ #endif
+ #ifdef MT6163_2G_RF
+/*MT6163*/ #define RF_ID RF_ID_MT6163
+ #endif
+ #ifdef MT6168_2G_RF
+/*MT6163*/ #define RF_ID RF_ID_MT6163
+ #endif
+ #ifdef MT6162_DUAL_RF /* This is used just for TK6280 FPGA from Jay's request */
+/*MT6162*/ #define RF_ID RF_ID_MT6162
+ #endif
+#endif
+
+/* default setting */
+#ifndef RF_ID
+/*BRIGHT2*/ #define RF_ID RF_ID_BRIGHT2
+#endif
+/*...........................................................................................................*/
+
+#define IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT 1
+
+#if defined(L1_SIM) && IS_CHIP_MT6292
+#undef IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT
+#define IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT 0
+#endif
+
+#if IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT
+ #if IS_BPI_DATA_48_BIT_CHIP
+ #error "dynamic allocation does not support 48 bits BPI"
+ #endif
+#endif
+
+#if IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT && IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_GL1D_CDF_SUPPORT 1
+#else
+#define IS_GL1D_CDF_SUPPORT 0
+#endif
+
+
+#define TURN_ON_PHONE_CALL_TRACE 0 //mtk13381
+#define l1D_RXDFE_RCC_SYN_REG_SW_CNTRL 0
+#define L1D_BASEBAND_MT6297_CHANGES 0 //mtk10455
+#define TURN_ON_PHONE_CALL_TRACE_97 1 //debug trace for 97
+
+//Usip restart process same as fd 216 flow
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_L1D_MML1_LPWR_DSP_ENABLE 1
+#else
+#define IS_L1D_MML1_LPWR_DSP_ENABLE 0
+#endif
+
+#if defined(L1D_SIM)
+#define IS_GSIM_PATTERN_CHECK_ENABLE 0
+#else
+#define IS_GSIM_PATTERN_CHECK_ENABLE 0
+#endif
+
+/*===================================================================*/
+/* CHIP Feature settings */
+/*===================================================================*/
+#if defined(__UMTS_NEW_ARCH__)
+#define L1D_WT_COBIN_ARCHITECTURE_SUPPORT 1
+#define L1D_WT_COBIN_RUNTIME_SWITCH_SUPPORT 1
+#else
+#define L1D_WT_COBIN_ARCHITECTURE_SUPPORT 0
+#define L1D_WT_COBIN_RUNTIME_SWITCH_SUPPORT 0
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+ #if defined(L1_SIM) || (IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297)
+#define IS_GL1D_TW_COEXIST_SUPPORT 1 /* This feature can support W and T in SIM1. SIM2 is always W */
+ #else
+#define IS_GL1D_TW_COEXIST_SUPPORT 0
+ #endif /* IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 */
+#else
+#define IS_GL1D_TW_COEXIST_SUPPORT 0
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT || L1D_WT_COBIN_RUNTIME_SWITCH_SUPPORT
+#define L1D_WT_COBIN_UT_BEBUG 0
+ #if defined(__UMTS_FDD_MODE__) && !defined(__UMTS_TDD128_MODE__)
+#define L1D_WT_COBIN_UT_W_ONLY_BUILD 1
+ #else
+#define L1D_WT_COBIN_UT_W_ONLY_BUILD 0
+ #endif
+ #if !defined(__UMTS_FDD_MODE__) && defined(__UMTS_TDD128_MODE__)
+#define L1D_WT_CBBIN_UT_T_ONLY_BUILD 1
+ #else
+#define L1D_WT_CBBIN_UT_T_ONLY_BUILD 0
+ #endif
+#else
+#define L1D_WT_COBIN_UT_BEBUG 0
+#define L1D_WT_COBIN_UT_W_ONLY_BUILD 0
+#define L1D_WT_CBBIN_UT_T_ONLY_BUILD 0
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT && L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD
+ #if !defined(__UMTS_FDD_MODE__)
+#define __UMTS_FDD_MODE__ 1
+ #endif
+ #if !defined(__MTK_UL1_FDD__)
+#define __MTK_UL1_FDD__ 1
+ #endif
+ #if !defined(__AST_TL1_TDD__)
+#define __AST_TL1_TDD__ 1
+ #endif
+ #if !defined(__UMTS_TDD128_MODE__)
+#define __UMTS_TDD128_MODE__ 1
+ #endif
+#endif
+
+#if defined(L1D_SIM) && defined(L1D_TEST) && (IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6260)||IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1))
+#define IS_COSIM_ON_L1SIM_SUPPORT 1
+#define IS_COSIM_ON_L1SIM_BYPASS_RF 1
+#else
+#define IS_COSIM_ON_L1SIM_SUPPORT 0
+#define IS_COSIM_ON_L1SIM_BYPASS_RF 0
+#endif
+
+#if (IS_CHIP_MT6227_AND_LATTER_VERSION && !IS_CHIP_MT6227_S00 && !IS_CHIP_MT6228_S00 && !IS_CHIP_MT6228_S01) || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01)
+#define L1D_PCH_2BURST_DECODE 1
+#else
+#define L1D_PCH_2BURST_DECODE 0
+#endif
+
+#if IS_CHIP_MT6227_D00 || IS_CHIP_MT6225_AND_LATTER_VERSION || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01)
+ #if defined(__MA_L1__) // MONZA29 and VENUS do not suppport PCH_1BURST_DECODE
+#define L1D_PCH_1BURST_DECODE 0
+ #else
+ #if IS_CHIP_MT6223 && defined(L1D_TEST)
+#define L1D_PCH_1BURST_DECODE 0
+ #else
+#define L1D_PCH_1BURST_DECODE 1
+ #endif
+ #endif
+ #if IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION
+#define L1D_PCH_EMPTY_PATTERN 1
+ #else
+#define L1D_PCH_EMPTY_PATTERN 0
+ #endif
+#else
+#define L1D_PCH_1BURST_DECODE 0
+#define L1D_PCH_EMPTY_PATTERN 0
+#endif
+
+#if L1D_PCH_1BURST_DECODE
+ #ifdef __MONITOR_PAGE_DURING_TRANSFER__
+ #if IS_NEW_L1D_ARCH_SUPPORT
+ #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 1
+ #elif defined(__UMTS_TDD128_MODE__)
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 0
+ #else
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 1
+ #endif
+ #else
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 1
+ #endif
+ #else
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 0
+ #endif
+#else
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 0
+#endif
+
+#if defined (__COTMS_TELEMATICS_SUPPORT__)
+#define IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT 1
+#define IS_TELEMATICS_HIGH_TEMPERATURE_SUPPORT 1
+#else
+#define IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT 0
+#define IS_TELEMATICS_HIGH_TEMPERATURE_SUPPORT 0
+#endif /* __COTMS_TELEMATICS_SUPPORT__ */
+
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ #if IS_TELEMATICS_HIGH_TEMPERATURE_SUPPORT
+#define TURN_ON_TELEMATICS_TRACE 1
+ #endif
+#endif
+
+/* Add for short PM */
+#if IS_GPRS
+#define L1D_PM_ENHANCE 1
+ #if IS_CHIP_MT6227_D00 || IS_CHIP_MT6225_AND_LATTER_VERSION || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01)
+ #if defined(__MA_L1__) // MONZA29 and VENUS do not suppport 1R7PM
+#define L1D_PM_1R7PM 0
+ #else
+ #if IS_CHIP_MT6223 && defined(L1D_TEST)
+#define L1D_PM_1R7PM 0
+ #else
+#define L1D_PM_1R7PM 1
+ #endif
+ #endif
+ #else
+#define L1D_PM_1R7PM 0
+ #endif
+#else // IS_GSM
+ #if IS_HW_8RXWIN_PM_SUPPORT_CHIP
+#define L1D_PM_ENHANCE 1
+#define L1D_PM_1R7PM 1
+ #else
+#define L1D_PM_ENHANCE 0
+#define L1D_PM_1R7PM 0
+ #endif
+#endif
+
+#if IS_GPRS || L1D_PM_ENHANCE
+#define IS_RTX_5CWIN_SUPPORT 1
+#else
+#define IS_RTX_5CWIN_SUPPORT 0
+#endif
+
+/*Repeated ACCH*/
+#if IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION
+#define IS_REPEATED_ACCH_SUPPORT 1
+#else
+#define IS_REPEATED_ACCH_SUPPORT 0
+#endif
+
+#if defined(FOUNTAIN2_EVB) || defined(MT6129A_EVB)
+#define RFVCO_SW_CONTROL
+#endif
+
+#if IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION
+#define FILLING_BYTES_2ND_DECODE
+#endif
+
+#ifdef __HO_IMPROVE__
+#define NONSYNC_HO_IMPROVEMENT
+#endif
+
+#if IS_FD216_DSP_CHIP
+ #if IS_CHIP_MT6268T || IS_CHIP_MT6268 || IS_EDGE_SAIC_CHIP_MT6236_AND_LATTER_VERSION
+#define IS_UPDATE_TIMESTAMP_FOR_DSP_CHIP 1
+ #else
+#define IS_UPDATE_TIMESTAMP_FOR_DSP_CHIP 0
+ #endif
+#else
+#define IS_UPDATE_TIMESTAMP_FOR_DSP_CHIP 1
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION
+#define IS_PM_DONE_CHECK_SUPPORT 1
+#elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+ #if defined(L1_SIM)
+#define IS_PM_DONE_CHECK_SUPPORT 1
+ #else
+#define IS_PM_DONE_CHECK_SUPPORT 0
+ #endif
+#else
+#define IS_PM_DONE_CHECK_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION && !IS_CHIP_TK6516
+#define IS_HYBRID_SAIC_SUPPORT 1
+#else
+#define IS_HYBRID_SAIC_SUPPORT 0
+#endif
+
+#if defined(__GEMINI__)
+
+#if defined(L1_SIM)
+ #ifdef IS_GEMINI_SUPPORT
+ #undef IS_GEMINI_SUPPORT
+ #endif
+#endif
+
+#define IS_GEMINI_SUPPORT 1
+#else
+#define IS_GEMINI_SUPPORT 0
+#endif
+
+#if IS_GEMINI_SUPPORT
+ #ifdef GEMINI_PLUS_GSM
+#define NUM_OF_SIM GEMINI_PLUS_GSM
+ #else
+#define NUM_OF_SIM 2
+ #endif
+#else
+#define NUM_OF_SIM 1
+#endif
+
+#define IS_GEMINI_1_2_SUPPORT 1 /*Gemini 1.2*/
+
+#if defined(__GEMINI__) && defined(__UMTS_FDD_MODE__)
+#define IS_GEMINI_WGG_SUPPORT 1 /*WG+G*/
+#else
+#define IS_GEMINI_WGG_SUPPORT 0
+#endif
+
+#if defined(__GEMINI__) && defined(__UMTS_TDD128_MODE__)
+#define IS_GEMINI_TGG_SUPPORT 1 /*TG+G*/
+#else
+#define IS_GEMINI_TGG_SUPPORT 0
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+
+ #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_GEMINI_WGG_SUPPORT
+#undef IS_GEMINI_TGG_SUPPORT
+#define IS_GEMINI_TGG_SUPPORT 1
+ #endif
+ #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_GEMINI_TGG_SUPPORT
+#undef IS_GEMINI_WGG_SUPPORT
+#define IS_GEMINI_WGG_SUPPORT 1
+ #endif
+
+ #if (IS_GEMINI_WGG_SUPPORT && !IS_GEMINI_TGG_SUPPORT) || (!IS_GEMINI_WGG_SUPPORT && IS_GEMINI_TGG_SUPPORT)
+ #if L1D_WT_COBIN_UT_W_ONLY_BUILD || L1D_WT_CBBIN_UT_T_ONLY_BUILD
+ #else
+#error "IS_GEMINI_WGG_SUPPORT and IS_GEMINI_TGG_SUPPORT should be aligned with WT Co-bin feature!"
+ #endif
+ #endif
+#endif
+
+#if defined(__GEMINI_WCDMA__)
+#define IS_GEMINI_WCDMA_SUPPORT 1
+#else
+#define IS_GEMINI_WCDMA_SUPPORT 0
+#endif
+
+#if IS_GEMINI_SUPPORT
+ #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_FORCE_ENHENCE_PM_SUPPORT 1
+ #else
+#define IS_FORCE_ENHENCE_PM_SUPPORT 0
+ #endif
+#else
+#define IS_FORCE_ENHENCE_PM_SUPPORT 0
+#endif
+#if defined(__MTK_TARGET__)
+ #if IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_SB_ENHANCE_TRACE_SUPPORT 1
+ #else
+#define IS_SB_ENHANCE_TRACE_SUPPORT 0
+ #endif
+#else
+#define IS_SB_ENHANCE_TRACE_SUPPORT 0
+#endif
+
+// workaround for APC HW bug, APC cannot work when DCM with 13M. In RFTOOL mode, L1D need to disable DCM by itself
+#if IS_CHIP_MT6227 || IS_CHIP_MT6228
+#define IS_RFTOOL_MODE_DCM_DISABLE 1
+#define IS_IDLE_MODE_TX_DCM_26M 1
+#else
+#define IS_RFTOOL_MODE_DCM_DISABLE 0
+#define IS_IDLE_MODE_TX_DCM_26M 0
+#endif
+
+#if IS_CHIP_MT6268
+#define IS_HANDLE_TX_DCM_SUPPORT 1
+#else
+#define IS_HANDLE_TX_DCM_SUPPORT 0
+#endif
+
+#if defined(L1D_TEST) // loopback no APC/BSI issue
+#undef IS_RFTOOL_MODE_DCM_DISABLE
+#undef IS_IDLE_MODE_TX_DCM_26M
+#undef IS_HANDLE_TX_DCM_SUPPORT
+#define IS_RFTOOL_MODE_DCM_DISABLE 0
+#define IS_IDLE_MODE_TX_DCM_26M 0
+#define IS_HANDLE_TX_DCM_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_CHIP_MT6252
+#define __NEW_L1D_ARCH__
+#endif
+
+#if IS_COSIM_ON_L1SIM_SUPPORT
+#elif defined(L1D_TEST) // loopback not ready for NEW L1D ARCH
+#undef __NEW_L1D_ARCH__
+#endif
+
+// new AGC/AFC update scheme
+#if defined(__NEW_L1D_ARCH__)
+#define IS_NEW_L1D_ARCH_SUPPORT 1
+ #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_CHIP_MT6252
+#define IS_NEW_L1D_ARCH_6R_SUPPORT 0
+#define IS_NEW_L1D_ARCH_8R_SUPPORT 1
+ #else
+#define IS_NEW_L1D_ARCH_6R_SUPPORT 1
+#define IS_NEW_L1D_ARCH_8R_SUPPORT 0
+ #endif
+ #if IS_CHIP_MT6256_S00
+#define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0
+ #elif IS_CHIP_MT6256
+#define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0
+ #else
+#define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0
+ #endif
+#else
+#define IS_NEW_L1D_ARCH_SUPPORT 0
+#define IS_NEW_L1D_ARCH_6R_SUPPORT 0
+#define IS_NEW_L1D_ARCH_8R_SUPPORT 0
+#define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0
+#endif
+
+#define IS_OLD_L1D_ARCH_SUPPORT !IS_NEW_L1D_ARCH_SUPPORT
+
+#if defined(L1_SIM) && IS_NEW_L1D_ARCH_8R_SUPPORT
+#undef IS_NEW_TDMA_CHIP
+#undef IS_HW_8RXWIN_PM_SUPPORT_CHIP
+#define IS_NEW_TDMA_CHIP 1
+#define IS_HW_8RXWIN_PM_SUPPORT_CHIP 1
+#endif
+
+#if IS_OLD_L1D_ARCH_SUPPORT && IS_HYPER_SLEEP_MODE_CHIP
+#define IS_OLD_L1D_ARCH_NEW_SLEEP_SUPPORT 1
+#else
+#define IS_OLD_L1D_ARCH_NEW_SLEEP_SUPPORT 0
+#endif
+
+// GSM mode slot2, slot3 CCCH handling
+#if IS_GPRS
+#define IS_GSM_ONLY_HANDLE_R23_SUPPORT 0
+#else
+ #if IS_NEW_L1D_ARCH_SUPPORT
+#define IS_GSM_ONLY_HANDLE_R23_SUPPORT 0
+ #else
+#define IS_GSM_ONLY_HANDLE_R23_SUPPORT 1
+ #endif
+#endif
+
+/* 3G RF chip preotection */
+#if defined(__MTK_UL1_FDD__) && !defined(L1_SIM) && !defined(L1D_TEST) && !defined(UL1D_TEST)
+ #ifdef MT6160_RF
+#define IS_3GRF_DETECT 1
+ #else
+#define IS_3GRF_DETECT 0
+ #endif
+#else
+#define IS_3GRF_DETECT 0
+#endif
+
+/* Align ul1d_cid.h*/
+#ifdef MT6160_RF
+#define RF_3G_ID_Rev2p1 0x000000F9
+#define RF_3G_ID_Rev3p0 0x000000EF
+#endif
+
+#if IS_CHIP_MT6276_S00 && defined(__UMTS_RAT__) && !defined(L1D_TEST) // only for MT6276E1
+#define IS_MT6276_ADCMUX_CHECK_CHIP 1
+#else
+#define IS_MT6276_ADCMUX_CHECK_CHIP 0
+#endif
+
+#if IS_CHIP_MT6276_S00 && IS_RF_MT6162
+#undef IS_MT6276_ADCMUX_CHECK_CHIP
+#define IS_MT6276_ADCMUX_CHECK_CHIP 0
+#endif
+
+#if IS_CHIP_MT6276_S01 && defined(__UMTS_RAT__) && !defined(L1D_TEST) // only for MT6276E2
+#define IS_MT6276_DACMODE_CHECK_CHIP 1
+#else
+#define IS_MT6276_DACMODE_CHECK_CHIP 0
+#endif
+
+#if IS_CHIP_MT6276 || IS_CHIP_MT6573
+#define IS_MD2G_LOGGER_SUPPORT_CHIP 1
+#else
+#define IS_MD2G_LOGGER_SUPPORT_CHIP 0
+#endif
+
+#if defined(__CACHED_BASE_DSP__)
+#define IS_CACHE_DSP_SUPPORT 1
+#else
+#define IS_CACHE_DSP_SUPPORT 0
+#endif
+
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define DSP_ARCHITECTURE_VERSION 4
+#elif IS_CACHE_DSP_SUPPORT
+#define DSP_ARCHITECTURE_VERSION 3
+#elif IS_DUAL_MAC_DSP_CHIP
+#define DSP_ARCHITECTURE_VERSION 2
+#else
+#define DSP_ARCHITECTURE_VERSION 1
+#endif
+
+#define IS_DSP_ARCHITECTURE_V1_SUPPORT (DSP_ARCHITECTURE_VERSION==1)
+#define IS_DSP_ARCHITECTURE_V2_SUPPORT (DSP_ARCHITECTURE_VERSION==2)
+#define IS_DSP_ARCHITECTURE_V3_SUPPORT (DSP_ARCHITECTURE_VERSION==3)
+#define IS_DSP_ARCHITECTURE_V4_SUPPORT (DSP_ARCHITECTURE_VERSION==4)
+
+// DSP Watchdog configuration
+#if IS_CHIP_MT6225_AND_LATTER_VERSION || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01)
+#define IS_DSP_WATCHDOG 1
+ #if IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION
+#define IS_DSP2_WATCHDOG 1
+ #else
+#define IS_DSP2_WATCHDOG 0
+ #endif
+#else
+#define IS_DSP_WATCHDOG 0
+#define IS_DSP2_WATCHDOG 0
+#endif
+
+#if !IS_DUAL_DSP_CHIP
+#undef IS_DSP2_WATCHDOG
+#define IS_DSP2_WATCHDOG 0
+#endif
+
+/* For 65NM IRDBG bug group*/ /* MT6268A, MT6516E0 has this bug */
+#if IS_CHIP_MT6268A // only for MT6268A FT Test, CM is not protected so we have this solution
+#define IS_IRDBG_SW_WORKAROUND 1
+#else
+#define IS_IRDBG_SW_WORKAROUND 0
+#endif
+
+/* Disable 65NM in L1Sim */
+#if IS_COSIM_ON_L1SIM_SUPPORT
+#elif defined(L1_SIM)
+#undef IS_65NM_CHIP
+#define IS_65NM_CHIP 0
+#endif
+
+/* For Support Centralized Sleep Mode Manager Group */
+/* We used to define IS_CENTRALIZED_SMM_CHIP as chip option */
+/* It's better to align with feature option */
+#if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_CENTRALIZED_SMM_CHIP 1
+#else
+#define IS_CENTRALIZED_SMM_CHIP 0
+#endif
+
+#if defined(ESIM_BUILD_CONFIG) && (ESIM_BUILD_CONFIG == ESIM_MULTI_MODE_ON_FIBERS) && defined(MTK_SLEEP_ENABLE)
+#define IS_TDMAIRQ_TIMING_CHECK_BYPASS_SUPPORT 1
+#elif ( IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6582 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 ) && defined(MTK_SLEEP_ENABLE)
+#define IS_TDMAIRQ_TIMING_CHECK_BYPASS_SUPPORT 1
+#else
+#define IS_TDMAIRQ_TIMING_CHECK_BYPASS_SUPPORT 0
+#endif
+
+/* Dual Mode Chip should always use SW_MODE, MT6516 has problem with HW_MODE */
+#if IS_65NM_CHIP
+ #if IS_CHIP_MT6268 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6251 || IS_CHIP_MT6575 || IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+ #if defined(MT6516_S00) || IS_CHIP_MT6251_S00 || IS_CHIP_MT6256_S00
+#define IS_MD2G_PWD_SUPPORT 0
+ #else
+#define IS_MD2G_PWD_SUPPORT 1
+ #endif
+ #if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_MD2G_PWD_DEFAULT_SW_MODE 0
+ #else
+#define IS_MD2G_PWD_DEFAULT_SW_MODE 1
+ #endif
+#define IS_IRDBG_LOG_STATUS 1
+ #else
+#define IS_MD2G_PWD_SUPPORT 0
+#define IS_MD2G_PWD_DEFAULT_SW_MODE 0
+#define IS_IRDBG_LOG_STATUS 1
+ #endif
+
+ #if IS_CHIP_MT6268 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6251 || IS_CHIP_MT6575 || IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250 //Later chip should apply new control flow
+#define IS_NEW_MD2G_PWD_CONTROL_SUPPORT 0
+ #else //For MT6280 and later chip
+#define IS_NEW_MD2G_PWD_CONTROL_SUPPORT 1
+ #endif
+
+ #if IS_CHIP_MT6268 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6256_S00
+#define IS_BACKUP_DPRAM_CHIP 1
+#define IS_RESTORE_PATCH_RAM_CHIP 1
+ #else
+#define IS_BACKUP_DPRAM_CHIP 0
+#define IS_RESTORE_PATCH_RAM_CHIP 0
+ #endif
+
+ #if IS_CHIP_MT6251_S00 && defined(L1D_TEST)
+#undef IS_BACKUP_DPRAM_CHIP
+#undef IS_RESTORE_PATCH_RAM_CHIP
+#define IS_BACKUP_DPRAM_CHIP 1
+#define IS_RESTORE_PATCH_RAM_CHIP 1
+ #endif
+
+ #if IS_CENTRALIZED_SMM_CHIP
+#define IS_MD2G_STANDALONE_MTCMOS_CHIP 1
+ #elif defined(__UMTS_RAT__) // 68 MD2G MTCMOS
+#define IS_MD2G_STANDALONE_MTCMOS_CHIP 0
+ #else
+#define IS_MD2G_STANDALONE_MTCMOS_CHIP 1
+ #endif
+
+ #if IS_CHIP_MT6575
+ #if defined(__UMTS_RAT__) && defined(__MTK_UL1_FDD__)
+#define IS_DEFAULT_TURNOFF_3GMTCMOS 0
+ #else
+#define IS_DEFAULT_TURNOFF_3GMTCMOS 1
+ #endif
+ #else
+#define IS_DEFAULT_TURNOFF_3GMTCMOS 0
+ #endif
+#endif
+
+#if defined(MTK_SLEEP_ENABLE) && IS_65NM_CHIP && IS_DSP_ARCHITECTURE_V4_SUPPORT
+ #if IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DSP_INIT_FLOW_V2_SUPPORT 1
+ #else
+#define IS_DSP_INIT_FLOW_V2_SUPPORT 0
+ #endif
+#else
+#define IS_DSP_INIT_FLOW_V2_SUPPORT 0
+#endif
+#if (L1D_TEST)
+#undef IS_DSP_INIT_FLOW_V2_SUPPORT
+#define IS_DSP_INIT_FLOW_V2_SUPPORT 0
+#endif
+#if IS_DSP_INIT_FLOW_V2_SUPPORT
+ #if IS_BACKUP_DPRAM_CHIP || IS_RESTORE_PATCH_RAM_CHIP || IS_COMPARE_DPRAM_CHIP
+#error "IS_DSP_INIT_FLOW_V2_SUPPORT does not support these feature."
+ #endif
+#else
+ #if IS_CHIP_MT6280
+#define IS_AFE_PRESENT 0
+ #else
+#define IS_AFE_PRESENT 1
+ #endif
+#endif
+
+#if defined(__2G_FAST_TIMING_ADJUST_SUPPORT__)
+#define IS_FAST_TIMING_ADJUST_SUPPORT 1
+#else
+#define IS_FAST_TIMING_ADJUST_SUPPORT 0
+#endif
+
+#if defined(__2G_FAST_TIMING_ADJUST_ENABLE__)
+#define IS_FAST_TIMING_ADJUST_ENABLE 1
+#else
+#define IS_FAST_TIMING_ADJUST_ENABLE 0
+#endif
+
+// For SOC chip MPLL FH Feature
+#if (IS_SOC_CHIP && !defined(__L1D_SOC_NO_MPLLFH__)) || IS_CHIP_MT6236 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MPLL_FH_SUPPORT 1
+ #if IS_CHIP_MT6252_S00
+#define IS_MPLL_FH_V2 0
+#define IS_MPLL_TX_RULE_CHECKED 0
+#define IS_SPLL_FH_SUPPORT 0
+#define IS_SPLL_FH_V2 0
+ #elif IS_CHIP_MT6252
+#define IS_MPLL_FH_V2 1
+#define IS_MPLL_TX_RULE_CHECKED 1
+#define IS_SPLL_FH_SUPPORT 1
+#define IS_SPLL_FH_V2 1
+ #else
+#define IS_MPLL_FH_V2 0
+#define IS_MPLL_TX_RULE_CHECKED 0
+#define IS_SPLL_FH_SUPPORT 0
+#define IS_SPLL_FH_V2 0
+ #endif
+#else
+#define IS_MPLL_FH_SUPPORT 0
+#define IS_MPLL_FH_V2 0
+#define IS_MPLL_TX_RULE_CHECKED 0
+#define IS_SPLL_FH_SUPPORT 0
+#define IS_SPLL_FH_V2 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+#define IS_MPLLFH_FREE_RUN_SUPPORT_CHIP 1
+#else
+#define IS_MPLLFH_FREE_RUN_SUPPORT_CHIP 0
+#endif
+
+#if IS_MPLLFH_FREE_RUN_SUPPORT_CHIP
+ #if IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_MPLLFH_FREE_RUN_ON 1
+ #elif IS_CHIP_MT6251
+#define IS_MPLLFH_FREE_RUN_ON 0
+ #else
+#define IS_MPLLFH_FREE_RUN_ON 0
+ #endif
+#else
+#define IS_MPLLFH_FREE_RUN_ON 0
+#endif
+
+#if defined(L1_SIM)
+#undef IS_MPLL_FH_SUPPORT
+#define IS_MPLL_FH_SUPPORT 0
+#endif
+
+#ifdef __CYCLIC_MPLLFH__
+#define IS_MPLL_CYCLIC_FH_SUPPORT 1
+#else
+#define IS_MPLL_CYCLIC_FH_SUPPORT 0
+#endif
+
+#ifdef __FIXED_MPLLFH__
+#define IS_MPLL_FIXED_LOWEST_SUPPORT 1
+#define IS_SPLL_FIXED_LOWEST_SUPPORT 1
+#else
+#define IS_MPLL_FIXED_LOWEST_SUPPORT 0
+#define IS_SPLL_FIXED_LOWEST_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6276_S00 // For MT6276E1 MPLL FH, MT6276E1 has only partial FH
+#define IS_MT6276E1_TEMP_MPLL_FH_SUPPORT 1
+#else
+#define IS_MT6276E1_TEMP_MPLL_FH_SUPPORT 0
+#endif
+
+#if defined(L1_SIM)
+#undef IS_MT6276E1_TEMP_MPLL_FH_SUPPORT
+#define IS_MT6276E1_TEMP_MPLL_FH_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6276_S01
+#define IS_MT6276_FREERUN_SUPPORT 1
+#else
+#define IS_MT6276_FREERUN_SUPPORT 0
+#endif
+
+#if defined(L1_SIM)
+#undef IS_MT6276_FREERUN_SUPPORT
+#define IS_MT6276_FREERUN_SUPPORT 0
+#endif
+
+#if IS_MPLL_FH_SUPPORT
+ #if IS_CHIP_MT6251
+#define IS_MPLL_DYNAMIC_FH_SUPPORT 1
+ #else
+#define IS_MPLL_DYNAMIC_FH_SUPPORT 0
+ #endif
+#endif
+
+#if IS_SOC_CHIP
+#define TX_DCOC_RF_LOOPBACK 1
+#else
+#define TX_DCOC_RF_LOOPBACK 0
+#endif
+
+// if need 33 sections calibration
+#if IS_CHIP_MT6253
+#define IS_VCXO_LC_NEED 1
+#else
+#define IS_VCXO_LC_NEED 0
+#endif
+
+// AFC linear compensation support
+#if IS_VCXO_LC_NEED
+#define IS_VCXO_LC_SUPPORT 1
+ #if IS_CHIP_MT6252
+#define IS_VCXO_LC_TRXOFFSET_COMPENSATE_SUPPORT 1
+ #else
+#define IS_VCXO_LC_TRXOFFSET_COMPENSATE_SUPPORT 0
+ #endif
+#else
+#define IS_VCXO_LC_SUPPORT 0
+#define IS_VCXO_LC_TRXOFFSET_COMPENSATE_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6251 || IS_CHIP_MT6252 || IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_TWO_STEP_AFC_TRACKING_SUPPORT 1
+#else
+#define IS_TWO_STEP_AFC_TRACKING_SUPPORT 0
+#endif
+
+// PM with DSP2MCU Interrupt
+#if IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION
+#define IS_PM_DSP2MCU_SUPPORT 1
+#else
+#define IS_PM_DSP2MCU_SUPPORT 0
+#endif
+
+// For feature of split binary: MAUI/FACTORY bin
+#if defined(__FACTORY_BIN__) || !defined(__SPLIT_BINARY__)
+#define IS_FOR_FACTORY_MODE_ONLY 1
+#else
+// This case means only __SPLIT_BINARY__ is defined, which is used for generating MAUI bin.
+#define IS_FOR_FACTORY_MODE_ONLY 0
+#endif
+
+// Fast Handset Calibration (FHC) Support
+#if IS_FOR_FACTORY_MODE_ONLY && (IS_CHIP_MT6229 || IS_CHIP_MT6238 || IS_CHIP_MT6223 || IS_CHIP_MT6253 || IS_CHIP_MT6225 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6268 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION)
+#define IS_FHC_SUPPORT 1
+#else
+#define IS_FHC_SUPPORT 0
+#endif
+
+// Non-Signaling Final Test (NSFT) Support
+#if IS_FOR_FACTORY_MODE_ONLY
+#define IS_NSFT_SUPPORT 1
+#else
+#define IS_NSFT_SUPPORT 0
+#endif
+
+// Single-End BER Support
+#if IS_NSFT_SUPPORT
+#define IS_SINGLE_END_BER_SUPPORT 1
+#define IS_NSFT_SACCH_TEST_ITEM_SUPPORT 1
+#else
+#define IS_SINGLE_END_BER_SUPPORT 0
+#define IS_NSFT_SACCH_TEST_ITEM_SUPPORT 0
+#endif
+
+//add __UMTS_RAT__, because for 2G Only target, control buffer size = 2K/4K, L1_ALLOC_BUF(sizeof(NsftList_CMD_Q_ENTRY_T)*NsftList_MAX_CMD_QUEUE_SIZE) will overflow
+// size define can reference to "interface/service/config/kal_user_mem.h" 2G only case: RPS_CREATED_CTRL_BUFF_POOLS=8, custom_ctrl_num_buff_pool_size=4096
+// Note: even if MAX support size=4KB, it may only 2K buffer can use, the supported buffer number of every size pool are decided by project
+#if IS_NSFT_SUPPORT && IS_EPSK_TX_SUPPORT && (defined(__UMTS_RAT__))
+#define IS_NSFT_LIST_MODE_SUPPORT 1
+#else
+#define IS_NSFT_LIST_MODE_SUPPORT 0
+#endif
+
+// MS Capability v2.0
+#if 1 // use v2.0 by default
+#define IS_MS_CAPABILITY_V2_SUPPORT 1
+#else
+/* under construction !*/
+#endif
+
+// Multi-slot TX Support in GSM only
+#if IS_FHC_SUPPORT && IS_GSM
+ #if 0 // TBD
+/* under construction !*/
+ #else
+#define IS_MULTISLOT_TX_SUPPORT 0
+ #endif
+#else
+#define IS_MULTISLOT_TX_SUPPORT 0
+#endif
+
+// FWBW-DCOC support: including DSP FWBW DCOC support and L1 alpha filtering enhance FWBW DCOC feature
+#if (IS_SAIC_CHIP_MT6253_AND_LATTER_VERSION && !IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION) || IS_CHIP_MT6583_MD2
+// MT6583 modem 2 is the DCR architecture
+ #if defined(L1D_TEST)
+#define IS_FWBW_DCOC_SUPPORT 0
+#define IS_AM_SUPPRESSION_ALPHA_FILTERING_SUPPORT 0
+ #else
+#define IS_FWBW_DCOC_SUPPORT 1
+#define IS_AM_SUPPRESSION_ALPHA_FILTERING_SUPPORT 1
+ #endif
+#else
+#define IS_FWBW_DCOC_SUPPORT 0
+#define IS_AM_SUPPRESSION_ALPHA_FILTERING_SUPPORT 0
+#endif
+
+// Force 2G TDMA and/or RF NO Sleep
+#if IS_CHIP_MT6268A
+#define IS_2G_TDMA_RF_NO_SLEEP 0 // 1
+#else
+#define IS_2G_TDMA_RF_NO_SLEEP 0
+#endif
+
+// Define TDMA/RF no Sleep default setting
+#if IS_2G_TDMA_RF_NO_SLEEP
+ #if IS_CHIP_MT6268A
+#define IS_2G_TDMA_NO_SLEEP 1
+#define IS_2G_RF_NO_SLEEP 0
+ #else
+#define IS_2G_TDMA_NO_SLEEP 0
+#define IS_2G_RF_NO_SLEEP 0
+ #endif
+#else
+#define IS_2G_TDMA_NO_SLEEP 0
+#define IS_2G_RF_NO_SLEEP 0
+#endif
+
+#if IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_SLEEP_DSPCLK_GATE 0
+#elif IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+#define IS_SLEEP_DSPCLK_GATE 1
+#else
+#define IS_SLEEP_DSPCLK_GATE 0
+#endif
+
+#if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2
+#define IS_SLEEP_HW_DIVIDER_INIT 1
+#else
+// For MT6280, MT6572/82, and later chips, the divider will be turned on or off by DIVIDE() and MODULO() defined in Divider_Public.h
+#define IS_SLEEP_HW_DIVIDER_INIT 0
+#endif
+
+// For 36 latter chips, slave DSP crash is moved to IO(0x7)
+#if IS_EDGE_SAIC_CHIP_MT6236_AND_LATTER_VERSION && !(IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280))
+#define IS_DSP2_CRASH_ON_IO7_CHIP 1
+#else
+#define IS_DSP2_CRASH_ON_IO7_CHIP 0
+#endif
+
+#if IS_DUAL_MAC_DSP_CHIP
+#define IS_DSP_CRASH_WORKAROUND 1
+#else
+#define IS_DSP_CRASH_WORKAROUND 0
+#endif
+
+#if (IS_CHIP_MT6295_AND_LATTER_VERSION && defined(__MTK_TARGET__))
+#define IS_GL1D_CAL_DATA_DOWNLOAD_CHECK_SUPPORT 1
+#else
+#define IS_GL1D_CAL_DATA_DOWNLOAD_CHECK_SUPPORT 0
+#endif
+#if IS_CHIP_MT6295_AND_LATTER_VERSION
+#define IS_GL1D_DSP_V2_FLOW_SINGLE_USER_SUPPORT 1
+#else
+#define IS_GL1D_DSP_V2_FLOW_SINGLE_USER_SUPPORT 0
+#endif
+// IRDMA power control
+#if IS_FD216_DSP_CHIP && (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION || IS_CHIP_MT6225_AND_LATTER_VERSION)
+#define IS_IRDMA_POWER_CTRL_CHIP 1
+#else
+#define IS_IRDMA_POWER_CTRL_CHIP 0
+#endif
+
+/* The De-interleaving buffer was moved to external memory */
+/* So, IRDMA would be used when wake-up, and the IR memory size should be increased */
+#if IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_DEINTERLEAVING_BUFFER_MOVED_CHIP 1
+#else
+#define IS_DEINTERLEAVING_BUFFER_MOVED_CHIP 0
+#endif
+
+#if defined(__MTK_MODEM_REMOVED__)
+#define IS_MTK_MODEM_REMOVED 1
+#else
+#define IS_MTK_MODEM_REMOVED 0
+#endif
+
+#if defined(__2G_RF_CUSTOM_TOOL_SUPPORT__)
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT 0
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 1
+#elif IS_CHIP_MT6516
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT 1
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 0
+#else
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT 0
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 0
+#endif
+
+#if IS_CHIP_MT6236
+#define IS_BT_CO_CLOCK_SW_SUPPORT 0
+#define IS_BT_CO_CLOCK_HW_SUPPORT 1
+#else
+#define IS_BT_CO_CLOCK_SW_SUPPORT 0
+#define IS_BT_CO_CLOCK_HW_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_SMP_ARCHITECTURE 1
+#else
+#define IS_SMP_ARCHITECTURE 0
+#endif
+
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6292) || defined(__UE_SIMULATOR__)
+#define IS_SIMULTANEOUS_L1CD_ENABLE 1
+#else
+#error "Remove dummy LISR is mandatory feature since LR12"
+#endif
+
+#if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MD2G_BUS_LOW_POWER_MODE 1
+#else
+#define IS_MD2G_BUS_LOW_POWER_MODE 0
+#endif
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_2G_L1D_ROBUST_MODEM_ENABLE 1
+#else
+#define IS_2G_L1D_ROBUST_MODEM_ENABLE 0
+#endif
+
+#if IS_CHIP_MT6293
+#define IS_2G_BANK_B_ENABLE 1
+#else
+#define IS_2G_BANK_B_ENABLE 0
+#endif
+
+#if (IS_CHIP_MT6761) && (defined __MTK_TARGET__)
+#define IS_L1D_DELSEL_MEMORY_DUMP_ENABLE 1
+#else
+#define IS_L1D_DELSEL_MEMORY_DUMP_ENABLE 0
+#endif
+//FDD Dual Mode Feature Option
+#if defined(__UMTS_FDD_MODE__)
+#define IS_FDD_DUAL_MODE_SUPPORT 1
+#else
+#define IS_FDD_DUAL_MODE_SUPPORT 0
+#endif
+
+//TDD Dual Mode Feature Option
+#if defined(__UMTS_TDD128_MODE__)
+#define IS_TDD_DUAL_MODE_SUPPORT 1
+#else
+#define IS_TDD_DUAL_MODE_SUPPORT 0 //To do TDD dual mode L1S and loopback test, this feature should be opened
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+
+ #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_FDD_DUAL_MODE_SUPPORT
+#undef IS_TDD_DUAL_MODE_SUPPORT
+#define IS_TDD_DUAL_MODE_SUPPORT 1
+ #endif
+ #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_TDD_DUAL_MODE_SUPPORT
+#undef IS_FDD_DUAL_MODE_SUPPORT
+#define IS_FDD_DUAL_MODE_SUPPORT 1
+ #endif
+
+ #if (IS_FDD_DUAL_MODE_SUPPORT && !IS_TDD_DUAL_MODE_SUPPORT) || (!IS_FDD_DUAL_MODE_SUPPORT && IS_TDD_DUAL_MODE_SUPPORT)
+ #if L1D_WT_COBIN_UT_W_ONLY_BUILD || L1D_WT_CBBIN_UT_T_ONLY_BUILD
+ #else
+#error "IS_FDD_DUAL_MODE_SUPPORT and IS_TDD_DUAL_MODE_SUPPORT should be aligned with WT Co-bin feature!"
+ #endif
+ #endif
+
+ #if (IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT) && !defined(__MULTI_RAT_AFC_TADC_SHARE_SUPPORT__)
+ #if L1D_WT_COBIN_UT_W_ONLY_BUILD || L1D_WT_CBBIN_UT_T_ONLY_BUILD
+ #else
+#error "WT Co-bin feature needs multi-mode AFC Temp ADC sharing feature when dual-mode or multi-mode!"
+ #endif
+ #endif
+
+#endif
+
+//Multi Mode Feature Option
+#if defined(__UMTS_RAT__) || defined(__LTE_RAT__)
+#define IS_GL1_MULTI_MODE_SUPPORT 1
+#else
+#define IS_GL1_MULTI_MODE_SUPPORT 0
+#endif
+
+#if ( IS_GL1_MULTI_MODE_SUPPORT && IS_TDD_DUAL_MODE_SUPPORT ) || IS_GEMINI_TGG_SUPPORT
+#define IS_TDD_5PM_NORMAL_CTIRQ2_SUPPORT 1
+#else
+#define IS_TDD_5PM_NORMAL_CTIRQ2_SUPPORT 0
+#endif
+#if defined(L1_SIM)//Here we are undefining the macro IS_MULTI_MODE_AFC_SUPPORT since while running on XL1sim
+#undef IS_MULTI_MODE_AFC_SUPPORT //we are facing the warning as macro is redefined since 3G is also using same macro definition
+#endif
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+ #if IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT
+#define IS_MULTI_MODE_AFC_SUPPORT 1
+ #else
+#define IS_MULTI_MODE_AFC_SUPPORT 0
+ #endif
+#else
+#define IS_MULTI_MODE_AFC_SUPPORT 0
+#endif
+
+#if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MULTI_MODE_AFC_WITH_SHM_SUPPORT 1
+#else
+#define IS_MULTI_MODE_AFC_WITH_SHM_SUPPORT 0
+#endif
+
+#if defined(__COTMS_TELEMATICS_SUPPORT__)
+#define IS_MULTI_MODE_AFC_IN_32BITS 1
+#else
+#define IS_MULTI_MODE_AFC_IN_32BITS 0
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+ #if (IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT) && !IS_MULTI_MODE_AFC_SUPPORT
+#error "WT Co-bin feature needs multi-mode AFC feature when dual-mode or multi-mode!"
+ #endif
+#endif
+
+#if IS_TDD_DUAL_MODE_SUPPORT && (IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297)
+#define IS_AST3002_SUPPORT 1
+#else
+#define IS_AST3002_SUPPORT 0
+#endif
+
+#if IS_TDD_DUAL_MODE_SUPPORT
+ #if ( IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #elif IS_CHIP_MT6575 && defined(__AST3001__)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 1 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 1 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 1 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 1 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 1 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #elif (IS_CHIP_MT6583_MD2 || IS_CHIP_MT6280) && defined(__AST3001__)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 1 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 1 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 1 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 1 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #elif IS_AST3002_SUPPORT && (IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 1 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #elif ( IS_CHIP_MT6255 || IS_CHIP_MT6256 ) && defined(__AST3001__)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #elif IS_GEMINI_TGG_SUPPORT && defined(__AST2001__)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #else
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0
+ #endif
+#else
+ #if IS_CHIP_MT6583_MD2
+/* For MT6583_MD2 2G Only Project, VRF28 is trigger by SRCLKENA */
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 1 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #else
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0
+ #endif
+#endif
+
+//TDD Dual Mode Feature Option
+#if IS_TDD_DUAL_MODE_SUPPORT
+ #if IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250
+#define IS_AST_B2S_SUPPORT 1
+ #else
+#define IS_AST_B2S_SUPPORT 0
+ #endif
+#else
+#define IS_AST_B2S_SUPPORT 0
+#endif
+
+//TDD Dual Mode Feature Option
+#if IS_TDD_DUAL_MODE_SUPPORT
+ #if IS_CHIP_MT6256 || IS_CHIP_MT6255 || ((IS_CHIP_MT6575||IS_CHIP_MT6280||IS_CHIP_MT6583_MD2) && defined(__AST3001__))
+#define IS_CO_CRYSTAL_SUPPORT 1
+#define IS_CO_TEMPADC_SUPPORT 0
+ #elif IS_CHIP_MT6572
+#define IS_CO_CRYSTAL_SUPPORT 1
+#define IS_CO_TEMPADC_SUPPORT 1
+ #else
+#define IS_CO_CRYSTAL_SUPPORT 0
+#define IS_CO_TEMPADC_SUPPORT 0
+ #endif
+#else
+#define IS_CO_CRYSTAL_SUPPORT 0
+#define IS_CO_TEMPADC_SUPPORT 0
+#endif
+
+#if defined(__MULTI_RAT_AFC_TADC_SHARE_SUPPORT__)
+ #if IS_CHIP_MT6290_S00
+#define IS_MULTI_RAT_AFC_SHARE_SUPPORT 0
+#define IS_MULTI_RAT_TADC_SHARE_SUPPORT 0
+ #else
+#define IS_MULTI_RAT_AFC_SHARE_SUPPORT 1
+#define IS_MULTI_RAT_TADC_SHARE_SUPPORT 1
+ #endif
+#else
+#define IS_MULTI_RAT_AFC_SHARE_SUPPORT 0
+#define IS_MULTI_RAT_TADC_SHARE_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6752_MD2
+#define IS_2G_ONLY_MODEM_SUPPORT 1
+#else
+#define IS_2G_ONLY_MODEM_SUPPORT 0
+#endif
+
+//TDD Dual Mode Short FBSB Feature
+#if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
+#define IS_DSP_ENHANCE_SHORT_FBSB_PATCH 0
+#elif IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6268T) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6223) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6268) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6253) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6276)
+#define IS_DSP_ENHANCE_SHORT_FBSB_PATCH 0
+#else
+#define IS_DSP_ENHANCE_SHORT_FBSB_PATCH 1
+#endif
+
+#if IS_TDD_DUAL_MODE_SUPPORT && !IS_DSP_ENHANCE_SHORT_FBSB_PATCH
+#error "DSP enhanced short FB/SB patch is mandatory for TDD dual mode"
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+#define IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT 1
+#else
+ #if IS_TDD_DUAL_MODE_SUPPORT
+#define IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT 1
+ #else
+#define IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT 0
+ #endif
+#endif
+
+#if IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT
+ #if defined(L1_SIM)
+#define IS_DSP_SHORT_FBSB_V1 0
+#define IS_DSP_SHORT_FBSB_V2 1
+ #endif
+#define IS_DSP_SHORT_SB_ENABLED 1
+#endif
+
+#if IS_TDD_DUAL_MODE_SUPPORT
+ #ifdef L1_SIM
+#define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 0
+ #else
+ #if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 1
+ #else
+#define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 0
+ #endif
+ #endif
+#else
+#define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 0
+#endif
+//TDD Dual Mode AFC Control Rule
+#if IS_TDD_DUAL_MODE_SUPPORT
+ #if defined(__AST2001__)
+#define IS_TDDM_AFC_TRANSFORM_SUPPORT 1 /* TD AFC HW has different DAC/slope from 2G */
+ #else
+#define IS_TDDM_AFC_TRANSFORM_SUPPORT 0
+ #endif
+#else
+#define IS_TDDM_AFC_TRANSFORM_SUPPORT 0
+#endif
+
+// Define L1D full pm test mode setting
+/*
+#define __L1D_FULL_PM_TEST__
+#define __L1D_FULL_PM_TEST_DEFAULT_OFF__
+ */
+#if defined(__L1D_FULL_PM_TEST__)
+#define IS_L1D_FULL_PM_TEST_SUPPORT 1
+#else
+#define IS_L1D_FULL_PM_TEST_SUPPORT 0
+#endif
+
+#if IS_L1D_FULL_PM_TEST_SUPPORT
+ #if !defined(__L1D_FULL_PM_TEST_DEFAULT_OFF__)
+#define IS_L1D_FULL_PM_TEST_DEFAULT_ON 1
+ #else
+#define IS_L1D_FULL_PM_TEST_DEFAULT_ON 0
+ #endif
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_WB_AMR_SUPPORT 1
+#define IS_FB_SNIFFER_SUPPORT 1
+#else
+#define IS_WB_AMR_SUPPORT 0
+#define IS_FB_SNIFFER_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6583_MD2
+#define IS_DLIF_CHIP 0
+#define IS_DCR_IN_DLIF_CHIP 1 /* MT6583_MD2 is DCR but re-uses the DLIF architecture */
+#define IS_DYNAMIC_SETPOINT_SUPPORT 0
+#define IS_HEADROOM_DETECTION_SUPPORT 0
+#define IS_SET_TX_BSI_CW_NEEDED 0
+#elif IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+#define IS_DLIF_CHIP 1
+#define IS_DCR_IN_DLIF_CHIP 0
+#define IS_DYNAMIC_SETPOINT_SUPPORT 1
+#define IS_HEADROOM_DETECTION_SUPPORT 1
+ #if IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_SET_TX_BSI_CW_NEEDED 0
+ #else
+#define IS_SET_TX_BSI_CW_NEEDED 1
+ #endif
+#else
+#define IS_DLIF_CHIP 0
+#define IS_DCR_IN_DLIF_CHIP 0
+#define IS_DYNAMIC_SETPOINT_SUPPORT 0
+#define IS_HEADROOM_DETECTION_SUPPORT 0
+#define IS_SET_TX_BSI_CW_NEEDED 0
+#endif
+
+#if IS_HEADROOM_DETECTION_SUPPORT
+ #if IS_CHIP_MT6256 || IS_CHIP_MT6251 || IS_CHIP_MT6255 || IS_CHIP_MT6250
+#define IS_IM_HEADROOM_DETECTION_SUPPORT 1
+ #else
+#define IS_IM_HEADROOM_DETECTION_SUPPORT 0
+ #endif
+#else
+#define IS_IM_HEADROOM_DETECTION_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_INBAND_BLOCKER_DETECTION_SUPPORT 1
+#else
+#define IS_INBAND_BLOCKER_DETECTION_SUPPORT 0
+#endif
+
+#if defined(L1_SIM)
+#define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 0
+#elif IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 1
+#else
+#define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 0
+#endif
+
+#if IS_OUTBAND_BLOCKER_DETECTION_SUPPORT
+#define IS_DSP_RX_DCOC_SUPPORT 1
+#else
+#define IS_DSP_RX_DCOC_SUPPORT 0
+#endif
+
+#if IS_RF_MT6179
+#define IS_DUAL_RF_SIP_CHIP_SUPPORT 1
+#else
+#define IS_DUAL_RF_SIP_CHIP_SUPPORT 0
+#endif
+
+#if IS_INBAND_BLOCKER_DETECTION_SUPPORT
+ #if IS_CHIP_MT6250
+#define IS_IM_INBAND_BLOCKER_DETECTION_SUPPORT 1
+ #else
+#define IS_IM_INBAND_BLOCKER_DETECTION_SUPPORT 0
+ #endif
+#else
+#define IS_IM_INBAND_BLOCKER_DETECTION_SUPPORT 0
+#endif
+
+#if IS_RF_MT6256RF || IS_RF_MT6251RF || IS_RF_MT6252RF || IS_RF_MT6255RF || IS_RF_MT6162 || IS_RF_MT6163 || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_DYNAMIC_MACRO_SUPPORT 1
+#else
+#define IS_DYNAMIC_MACRO_SUPPORT 0
+#endif
+
+#if IS_RF_MT6256RF
+#define IS_DYNAMIC_TC_GAIN_SUPPORT 1
+#define IS_TEMP_COMP_TC_GAIN_SUPPORT 1
+#elif IS_RF_MT6255RF
+#define IS_DYNAMIC_TC_GAIN_SUPPORT 0
+#define IS_TEMP_COMP_TC_GAIN_SUPPORT 0
+#else
+#define IS_DYNAMIC_TC_GAIN_SUPPORT 0
+#define IS_TEMP_COMP_TC_GAIN_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6583_MD2
+#define IS_GCMACHINE_SUPPORT 1
+#elif IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_CHIP_MT6252
+#define IS_GCMACHINE_SUPPORT 0
+#else
+#define IS_GCMACHINE_SUPPORT 1
+#endif
+
+#if IS_CHIP_MT6256
+#define IS_MT6251_DCR_MODE 0
+#define IS_MT6256_DCR_MODE 0
+#define IS_MT6251_E1_FT 0
+ #if IS_MT6256_DCR_MODE
+#define IS_W_CANCELLATION_SUPPORT 0
+ #else
+#define IS_W_CANCELLATION_SUPPORT 1
+ #endif
+#elif IS_CHIP_MT6251
+#define IS_MT6251_DCR_MODE 0
+#define IS_MT6256_DCR_MODE 0
+#define IS_MT6251_E1_FT 0
+ #if IS_MT6251_DCR_MODE
+#define IS_W_CANCELLATION_SUPPORT 0
+ #else
+#define IS_W_CANCELLATION_SUPPORT 1
+ #endif
+#elif IS_CHIP_MT6255 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MT6251_DCR_MODE 0
+#define IS_MT6256_DCR_MODE 0
+#define IS_W_CANCELLATION_SUPPORT 1
+#define IS_MT6251_E1_FT 0
+#else
+#define IS_MT6251_DCR_MODE 0
+#define IS_MT6256_DCR_MODE 0
+#define IS_W_CANCELLATION_SUPPORT 0
+#define IS_MT6251_E1_FT 0
+#endif
+
+#if IS_CHIP_MT6256
+ #if defined(__BT_SUPPORT__)
+#define IS_BT_R_CAL_SUPPORT 1
+ #else
+#define IS_BT_R_CAL_SUPPORT 0
+ #endif
+#else
+#define IS_BT_R_CAL_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256_S00
+#define IS_SWITD_SUPPORT 0
+#elif IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_SWITD_SUPPORT 1
+#else
+#define IS_SWITD_SUPPORT 0
+#endif
+
+#if IS_SWITD_SUPPORT
+ #if IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250
+#define IS_IM_SWITD_SUPPORT 1
+ #else
+#define IS_IM_SWITD_SUPPORT 0
+ #endif
+#else
+#define IS_IM_SWITD_SUPPORT 0
+#endif
+
+#if IS_DSP_INIT_FLOW_V2_SUPPORT
+#define IS_POLLING_SHERIF_AFTER_DSP_RESET_NEEDED 1
+#else
+#define IS_POLLING_SHERIF_AFTER_DSP_RESET_NEEDED 0
+#endif
+
+/* IS_SPEECH_RESYNC_SUPPORT :L1D inform Audio to trigger VBI-Reset(DSP-Speech reset) */
+/* IS_SPEECH_RESYNC_SUPPORT_V2:L1D provide API to Audio, Audio query these API to trigger speech resync */
+/* MT6582 or latter version use IS_SPEECH_RESYNC_SUPPORT_V2*/
+#if IS_DSP_ARCHITECTURE_V1_SUPPORT || IS_DSP_ARCHITECTURE_V2_SUPPORT || IS_DSP_ARCHITECTURE_V3_SUPPORT
+#define IS_SPEECH_RESYNC_SUPPORT 0
+#define IS_SPEECH_RESYNC_SUPPORT_V2 0
+#elif IS_CHIP_MT6582 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_SPEECH_RESYNC_SUPPORT 0
+#define IS_SPEECH_RESYNC_SUPPORT_V2 1
+#elif IS_LOCK_AFCDAC_AT_STARTUP_SUPPORT
+#define IS_SPEECH_RESYNC_SUPPORT 0
+#define IS_SPEECH_RESYNC_SUPPORT_V2 1
+#else
+#define IS_SPEECH_RESYNC_SUPPORT 1
+#define IS_SPEECH_RESYNC_SUPPORT_V2 0
+#endif
+
+#if defined(L1D_TEST)
+#undef IS_HEADROOM_DETECTION_SUPPORT
+#undef IS_INBAND_BLOCKER_DETECTION_SUPPORT
+#undef IS_OUTBAND_BLOCKER_DETECTION_SUPPORT
+#undef IS_DYNAMIC_SETPOINT_SUPPORT
+#undef IS_W_CANCELLATION_SUPPORT
+#undef IS_SWITD_SUPPORT
+#define IS_HEADROOM_DETECTION_SUPPORT 0
+#define IS_INBAND_BLOCKER_DETECTION_SUPPORT 0
+#define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 0
+#define IS_DYNAMIC_SETPOINT_SUPPORT 0
+#define IS_W_CANCELLATION_SUPPORT 0
+#define IS_SWITD_SUPPORT 0
+#endif
+
+#if defined(L1_SIM)
+#undef IS_W_CANCELLATION_SUPPORT
+#undef IS_SPEECH_RESYNC_SUPPORT
+#define IS_W_CANCELLATION_SUPPORT 0
+#define IS_SPEECH_RESYNC_SUPPORT 0
+#endif
+
+#if IS_W_CANCELLATION_SUPPORT
+#define IS_WC_SLOW_TRACKING_SUPPORT 1
+ #if IS_WC_SLOW_TRACKING_SUPPORT
+#define IS_WC_SUB_KEEP_GAIN_DIM 0
+ #else
+#define IS_WC_SUB_KEEP_GAIN_DIM 1
+ #endif
+ #if IS_CHIP_MT6251_S00 || IS_CHIP_MT6256_S00
+#define IS_WC_IMM_MODE_ENABLE 0
+ #else
+#define IS_WC_IMM_MODE_ENABLE 1
+ #endif
+#else
+#define IS_WC_SLOW_TRACKING_SUPPORT 0
+#define IS_WC_SUB_KEEP_GAIN_DIM 0
+#define IS_WC_IMM_MODE_ENABLE 0
+#endif
+
+#if IS_EPSK_TX_SUPPORT
+ #if IS_RF_MT6256RF || IS_RF_MT6162 || IS_RF_MT6163 || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_EPSK_TX_GAIN_CONTROL_SUPPORT 1
+ #else
+#define IS_EPSK_TX_GAIN_CONTROL_SUPPORT 0
+ #endif
+#else
+#define IS_EPSK_TX_GAIN_CONTROL_SUPPORT 0
+#endif
+
+#if IS_RF_MT6252RF
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 1
+#elif IS_RF_MT6162
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 1
+#elif IS_RF_MT6251RF
+ #if IS_MT6251_E1_FT
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 0
+ #else
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 1
+ #endif
+#elif IS_RF_MT6255RF
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 1
+#else
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 0
+#endif
+
+#if IS_CHIP_MT6252_S00
+#define IS_RF_TX_SLEEP_MODE_SUPPORT 0
+#elif IS_CHIP_MT6252
+#define IS_RF_TX_SLEEP_MODE_SUPPORT 1
+#elif IS_CHIP_MT6251_S00
+#define IS_RF_TX_SLEEP_MODE_SUPPORT 0
+#elif IS_CHIP_MT6251
+#define IS_RF_TX_SLEEP_MODE_SUPPORT 1
+#else
+#define IS_RF_TX_SLEEP_MODE_SUPPORT 0
+#endif
+
+#if IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_OBB_DETECTION_SUPPORT 1
+#else
+#define IS_OBB_DETECTION_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6251_S00 || IS_CHIP_MT6252_S00
+#define IS_DSP_PIO_GLITCH_FIXED_NEEDED 0
+#elif IS_CHIP_MT6251 || IS_CHIP_MT6252
+#define IS_DSP_PIO_GLITCH_FIXED_NEEDED 1
+#else
+#define IS_DSP_PIO_GLITCH_FIXED_NEEDED 0
+#endif
+
+#if IS_CHIP_MT6251_S00 || IS_CHIP_MT6256_S00
+#define IS_FB_LONG_WINDOW_RXWIN_MULTIPLY_SUPPORT 1
+#else
+#define IS_FB_LONG_WINDOW_RXWIN_MULTIPLY_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256_S00
+#define IS_RTX_BUFFER_POWER_CTRL_SUPPORT 0
+#define IS_IDMA_SHORT_PORT_MODE_V2_SUPPORT 0
+#define IS_ACCESS_SHERIF_BY_IDMA_SUPPORT 0
+#elif IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_RTX_BUFFER_POWER_CTRL_SUPPORT 1
+#define IS_IDMA_SHORT_PORT_MODE_V2_SUPPORT 1
+#define IS_ACCESS_SHERIF_BY_IDMA_SUPPORT 1
+#else
+#define IS_RTX_BUFFER_POWER_CTRL_SUPPORT 0
+#define IS_IDMA_SHORT_PORT_MODE_V2_SUPPORT 0
+#define IS_ACCESS_SHERIF_BY_IDMA_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256_S00
+#define IS_DYNAMIC_SWITCH_DDS_SUPPORT 0
+#elif IS_CHIP_MT6256
+#define IS_DYNAMIC_SWITCH_DDS_SUPPORT 1
+#else
+#define IS_DYNAMIC_SWITCH_DDS_SUPPORT 0
+#endif
+
+#if defined(__F32_XOSC_REMOVAL_SUPPORT__)
+#define IS_32K_CRYSTAL_REMOVAL_SUPPORT 1
+#else
+#define IS_32K_CRYSTAL_REMOVAL_SUPPORT 0
+#endif
+
+/* IS_CLOAD_CAL_BBLPM_V1_SUPPORT: use BBLPM in FHC and SW LPM in traditional cal */
+#if IS_32K_CRYSTAL_REMOVAL_SUPPORT
+ #if IS_CHIP_MT6755 || IS_CHIP_MT6292
+#define IS_CLOAD_CAL_BBLPM_V1_SUPPORT 1
+ #elif IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 //&& IS_MML1_PMIC_MT6356
+#define IS_CLOAD_CAL_BBLPM_V1_SUPPORT 0
+ #else
+ #error "Please check CHIP and PMIC version"
+ #endif
+#endif
+
+#if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6577 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2
+#define IS_ABB_HW_CALIBRATION_SUPPORT 1
+#else
+#define IS_ABB_HW_CALIBRATION_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_BSI_SX0_SUPPORT 1
+#else
+#define IS_BSI_SX0_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256 || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_BPI_V2_SUPPORT 1
+#else
+#define IS_BPI_V2_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252
+#define IS_BSI_V2_SUPPORT 1
+#else
+#define IS_BSI_V2_SUPPORT 0
+#endif
+
+#define IS_BPI_V1_SUPPORT (!IS_BPI_V2_SUPPORT)
+#define IS_BSI_V1_SUPPORT (!IS_BSI_V2_SUPPORT)
+
+#if IS_BSI_V2_SUPPORT
+ #if IS_CHIP_MT6256 || IS_CHIP_MT6252 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_BSI_V2_ST2_SUPPORT 0
+ #elif IS_CHIP_MT6251 || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6583_MD2
+#define IS_BSI_V2_ST2_SUPPORT 1
+ #elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+#define IS_BSI_V2_ST2_SUPPORT 1
+ #else
+#define IS_BSI_V2_ST2_SUPPORT 0
+ #endif
+#else
+#define IS_BSI_V2_ST2_SUPPORT 0
+#endif
+
+#if IS_BPI_V2_SUPPORT
+ #if defined(__2G_BPI_PT3A_SUPPORT__)
+#define IS_BPI_V2_PT3A_SUPPORT 1
+ #elif defined(L1_SIM)
+#define IS_BPI_V2_PT3A_SUPPORT 1
+ #elif IS_CHIP_MT6582
+#define IS_BPI_V2_PT3A_SUPPORT 1
+ #else
+#define IS_BPI_V2_PT3A_SUPPORT 0
+ #endif
+#else
+#define IS_BPI_V2_PT3A_SUPPORT 0
+#endif
+
+#if defined(L1_SIM) && defined(MT6162_DUAL_RF)
+/* Note: for the combination of MT6280+MT6162_DUAL_RF, we should define IS_BSI_V2_ST2_SUPPORT */
+#undef IS_BSI_V2_ST2_SUPPORT
+#define IS_BSI_V2_ST2_SUPPORT 1
+#endif
+
+#if IS_BSI_V1_SUPPORT || IS_BSI_V2_ST2_SUPPORT
+#define IS_BSI_ST2_SUPPORT 1
+#else
+#define IS_BSI_ST2_SUPPORT 0
+#endif
+
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+#define IS_BSI_ST2B_SUPPORT 1
+#else
+#define IS_BSI_ST2B_SUPPORT 0
+#endif
+
+#if IS_BSI_V1_SUPPORT && IS_EPSK_TX_SUPPORT
+#define IS_BSI_ST2M_SUPPORT 1
+#elif IS_BSI_V2_SUPPORT
+#define IS_BSI_ST2M_SUPPORT 1
+#else
+#define IS_BSI_ST2M_SUPPORT 0
+#endif
+
+#if IS_GPRS || IS_MULTISLOT_TX_SUPPORT
+#define IS_CALCULATE_PM_TABLE_SUPPORT 1
+#else
+#define IS_CALCULATE_PM_TABLE_SUPPORT 0
+#endif
+
+#if IS_RF_MT6162 || IS_RF_MT6163
+#define IS_RF_RX_DCOC_SUPPORT 1
+ #if IS_CHIP_MT6577 || IS_CHIP_MT6583_MD2
+#define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 1
+ #else
+#define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 0
+ #endif
+ #if IS_EPSK_TX_SUPPORT
+#define IS_RF_TX_CALIBRATION_SUPPORT 1
+ #else
+#define IS_RF_TX_CALIBRATION_SUPPORT 0
+ #endif
+#else
+#define IS_RF_RX_DCOC_SUPPORT 0
+#define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 0
+#define IS_RF_TX_CALIBRATION_SUPPORT 0
+#endif
+
+#if defined(L1_SIM) || IS_CHIP_TK6280 /* TK6280 FPGA not support the following feature */
+#undef IS_RF_RX_DCOC_SUPPORT
+#undef IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT
+#undef IS_RF_TX_CALIBRATION_SUPPORT
+#define IS_RF_RX_DCOC_SUPPORT 0
+#define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 0
+#define IS_RF_TX_CALIBRATION_SUPPORT 0
+#endif
+
+#if IS_CACHE_DSP_SUPPORT || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_SIX_IRDMA_MPU_SETTING_CHIP 0
+#elif IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6268A) || IS_CHIP_SER(CHIP_ID_MT6256)
+#define IS_SIX_IRDMA_MPU_SETTING_CHIP 1
+#else
+#define IS_SIX_IRDMA_MPU_SETTING_CHIP 0
+#endif
+
+#if IS_CHIP_MT6251
+#define IS_SINGLE_DSP_TRX_REGION_SUPPORT 1
+#else
+#define IS_SINGLE_DSP_TRX_REGION_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6252
+#define IS_RTX_DATA_MOVED_BY_IRDMA_SUPPORT 0
+#elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+#define IS_RTX_DATA_MOVED_BY_IRDMA_SUPPORT 1
+#else
+#define IS_RTX_DATA_MOVED_BY_IRDMA_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252 || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+#define IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT 1
+#else
+#define IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251_S00
+#undef IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT
+#define IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION
+#define IS_DUAL_MAC_DSP_NEW_EQ_CHECK_SUPPORT 1
+#else
+#define IS_DUAL_MAC_DSP_NEW_EQ_CHECK_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_6R6T_HW_SUPPORT_CHIP 1
+#else
+#define IS_6R6T_HW_SUPPORT_CHIP 0
+#endif
+
+#if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
+#define IS_DSP_COSTDOWN_FB_CHIP 0
+#elif IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6268T) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6223) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6236) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6252H) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6276)
+#define IS_DSP_COSTDOWN_FB_CHIP 0
+#else
+#define IS_DSP_COSTDOWN_FB_CHIP 1
+#endif
+
+#if defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__) || defined(__L1_GPS_REF_TIME_SUPPORT__)
+#define L1D_AGPS_TIMING_SYNC_SUPPORT 1
+#else
+#define L1D_AGPS_TIMING_SYNC_SUPPORT 0
+#endif
+
+#if IS_CENTRALIZED_SMM_CHIP
+ #if IS_CHIP_MT6276_S00 || IS_CHIP_MT6573
+#define L1D_AGPS_OLD_REGISTER 1
+ #else
+#define L1D_AGPS_OLD_REGISTER 0
+ #endif
+#endif
+
+// HW clock gating
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6297)
+#define IS_HWCG_SUPPORT 0
+#elif IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_HWCG_SUPPORT 1
+#else
+#define IS_HWCG_SUPPORT 0
+#endif
+
+// Modem hard real time recovery enhancement
+#ifdef __MD_HRT_RECOVERY__
+#define IS_MD_HRT_RECOVERY_SUPPORT 1
+#else
+#define IS_MD_HRT_RECOVERY_SUPPORT 0
+#endif
+
+// APC Ramping Profiles support
+#define APC_PROFILE_NUM 7
+
+#if IS_CHIP_MT6208
+#undef APC_PROFILE_NUM
+#define APC_PROFILE_NUM 6
+#endif
+
+#if IS_NEW_L1D_ARCH_SUPPORT
+#undef APC_PROFILE_NUM
+#define APC_PROFILE_NUM 5
+#endif
+
+#define IS_5_BANK_RAMP_PROFILES_SUPPORT (APC_PROFILE_NUM==5)
+#define IS_6_BANK_RAMP_PROFILES_SUPPORT (APC_PROFILE_NUM==6)
+#define IS_7_BANK_RAMP_PROFILES_SUPPORT (APC_PROFILE_NUM==7)
+
+#if defined (__2G_TX_POWER_CONTROL_SUPPORT__)
+#define IS_TX_POWER_CONTROL_SUPPORT 1
+ #if IS_CHIP_MT6256
+#define IS_TXPC_CL_AUXADC_SUPPORT 1 /* Closed-loop. Vdet from AUXADC */
+#define IS_TXPC_CL_BSI_SUPPORT 0 /* Closed-loop. Pdet from BSI HW readback */
+#define IS_TXPC_OL_AUXADC_SUPPORT 0 /* Open-loop. Ext. temperature from AUXADC */
+#define IS_TXPC_OL_BSI_SUPPORT 1 /* Open-loop. RF temperature from BSI HW readback */
+ #elif IS_CHIP_MT6575 || IS_CHIP_MT6583_MD2
+#define IS_TXPC_CL_AUXADC_SUPPORT 0
+#define IS_TXPC_CL_BSI_SUPPORT 1
+#define IS_TXPC_OL_AUXADC_SUPPORT 1
+#define IS_TXPC_OL_BSI_SUPPORT 0
+ #elif IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_TXPC_CL_AUXADC_SUPPORT 0
+#define IS_TXPC_CL_BSI_SUPPORT 1
+#define IS_TXPC_OL_AUXADC_SUPPORT 0
+#define IS_TXPC_OL_BSI_SUPPORT 1
+ #elif IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION
+#define IS_TXPC_CL_AUXADC_SUPPORT 1
+#define IS_TXPC_CL_BSI_SUPPORT 1
+#define IS_TXPC_OL_AUXADC_SUPPORT 1
+#define IS_TXPC_OL_BSI_SUPPORT 0
+ #endif
+#else
+#define IS_TX_POWER_CONTROL_SUPPORT 0
+#define IS_TXPC_CL_AUXADC_SUPPORT 0
+#define IS_TXPC_CL_BSI_SUPPORT 0
+#define IS_TXPC_OL_AUXADC_SUPPORT 0
+#define IS_TXPC_OL_BSI_SUPPORT 0
+#endif
+
+#if IS_TX_POWER_CONTROL_SUPPORT && ( IS_RF_MT6177L || IS_RF_MT6177M || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T)
+#define IS_RSSI_TC_SUPPORT 1 /* RSSI Temperature Compensation will reuse TXPC's temperature info */
+#else
+#define IS_RSSI_TC_SUPPORT 0
+#endif
+
+#if IS_RF_MT6162 || IS_RF_MT6256RF || IS_RF_MT6163 || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_RF_TX_POWER_CONTROL_SUPPORT 1
+#else
+#define IS_RF_TX_POWER_CONTROL_SUPPORT 0
+#endif
+
+#if IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_ORION_RF_SERIES 1
+#else
+#define IS_ORION_RF_SERIES 0
+#endif
+
+#if (IS_RF_MT6177L && defined(__IS_2G_DYNAMIC_GAINTABLE_SWITCH_SUPPORT__))
+#define IS_2G_DYNAMIC_GAINTABLE_SWITCH_SUPPORT 1 //Boost LPF2 Gain for Pin=-96~-102dBm
+#else
+#define IS_2G_DYNAMIC_GAINTABLE_SWITCH_SUPPORT 0
+#endif
+
+#if IS_GPRS
+#define IS_DECREASE_RF_TX_MAX_POWER_SUPPORT 1
+#else
+#define IS_DECREASE_RF_TX_MAX_POWER_SUPPORT 0
+#endif
+
+#if defined(__TAS_SUPPORT__)
+#define IS_TAS_MAX_TXPWR_REDUCTION_SUPPORT 1
+#else
+#define IS_TAS_MAX_TXPWR_REDUCTION_SUPPORT 0
+#endif
+
+#if defined (__MULTI_LNA_MODE_CALIBRATION_SUPPORT__)
+ #if IS_CHIP_MT6582
+#define IS_MULTI_LNA_MODE_CALIBRATION_SUPPORT 1
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT 1 /* pathloss cal with one LNA or multi-lna mode are adjustable by tool config */
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT_V2 0 /* pathloss cal with one LNA or multi-lna mode are adjustable by tool config, and LNA Mode can be choose by L1 */
+ #else
+#define IS_MULTI_LNA_MODE_CALIBRATION_SUPPORT 1
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT 0
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT_V2 0
+ #endif
+#else
+#define IS_MULTI_LNA_MODE_CALIBRATION_SUPPORT 0
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT 0
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT_V2 0
+#endif
+
+#if defined (__2G_TX_GAIN_RF_CALIBRATION__)
+#define IS_TX_GAIN_RF_CALIBRATION_SUPPORT 1
+#else
+#define IS_TX_GAIN_RF_CALIBRATION_SUPPORT 0
+#endif
+
+/* for dual talk project, RX LNA > LNA2 which is co-band with 3G need to change to another gain table */
+#define IS_DUAL_TALK_RX_GAIN_TABLE_CO_BAND_SUPPORT 0
+
+#if IS_EPSK_TX_SUPPORT
+ #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6583_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 1 /* Change the GMSK and EPSK TX window positions dynamically by slots. */
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 0 /* Change the GMSK and EPSK TX window positions dynamically by frames */
+ /* according to the modulation type of the whole TX slot in each frame. */
+ #else
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 0
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 1
+ #endif
+#else
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 0
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 0
+#endif
+
+#if defined(L1D_TEST)
+#undef IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT
+#undef IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 0
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 0
+#endif
+
+//#if IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_MT6177M || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T
+#define IS_RF_DUAL_LOOP_AFC_CONTROL_SUPPORT 1
+//#else
+//#define IS_RF_DUAL_LOOP_AFC_CONTROL_SUPPORT 0
+//#endif
+
+#if defined(L1D_TEST)
+#define IS_DUAL_LOOP_AFC_CONTROL_SUPPORT 0
+#else
+ #if IS_VCXO_LC_SUPPORT
+#error "Please implement Dual Loop AFC Control for VCXO"
+ #elif IS_RF_DUAL_LOOP_AFC_CONTROL_SUPPORT
+#define IS_DUAL_LOOP_AFC_CONTROL_SUPPORT 1
+ #else
+#error "This RF Chip is not support Fix AFC and GPS Co-Clock"
+ #endif
+#endif
+
+#if IS_DUAL_LOOP_AFC_CONTROL_SUPPORT
+ #if IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T
+#define IS_FIX_AFC_OFFSET_CW_COMPENSATE_SUPPORT 1
+ #else
+#define IS_FIX_AFC_OFFSET_CW_COMPENSATE_SUPPORT 0
+ #endif
+#endif
+
+#if IS_DUAL_LOOP_AFC_CONTROL_SUPPORT
+ #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DSP_RX_NBIC_SUPPORT 1
+ #else
+#define IS_DSP_RX_NBIC_SUPPORT 0
+ #endif
+ #if defined(L1D_TEST)
+#define IS_DSP_RX_NBIC_SUPPORT 0
+ #endif
+#else
+#define IS_DSP_RX_NBIC_SUPPORT 0
+#endif
+
+#if IS_DUAL_LOOP_AFC_CONTROL_SUPPORT
+#define IS_LOCK_AFCDAC_AT_STARTUP_SUPPORT 1
+#else
+#define IS_LOCK_AFCDAC_AT_STARTUP_SUPPORT 0
+#endif
+
+#if defined(__AUDIO_DSP_LOWPOWER_V2__)
+#define IS_AUDIO_DSP_LOWPOWER_SUPPORT 1
+#else
+#define IS_AUDIO_DSP_LOWPOWER_SUPPORT 0
+#endif
+
+/* IS_AFC_EVENT_SUPPORT_CHIP: decide if the chip supports the AFC event register */
+#if IS_AST_B2S_SUPPORT || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2
+#define IS_AFC_EVENT_SUPPORT_CHIP 1
+#elif IS_SOC_CHIP || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_AFC_EVENT_SUPPORT_CHIP 0
+#else
+#define IS_AFC_EVENT_SUPPORT_CHIP 1
+#endif
+
+/* IS_DCXO_SUPPORT_CHIP: decide if the chip supports the way of sending AFCDAC values by BSI */
+#if IS_SOC_CHIP || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DCXO_SUPPORT_CHIP 1
+#else
+#define IS_DCXO_SUPPORT_CHIP 0
+#endif
+
+/* IS_DFM_RF_TIMING_CHECK_SUPPORT: add RF-BFE timing constraints at RX/TX on/off in l1d_data.c */
+#if IS_RF_MT6252RF || IS_RF_MT6251RF || IS_RF_MT6256RF || IS_RF_MT6255RF || IS_RF_MT6162 || IS_RF_MT6163 || IS_RF_MT6250RF || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_DFM_RF_TIMING_CHECK_SUPPORT 1
+#else
+#define IS_DFM_RF_TIMING_CHECK_SUPPORT 0
+#endif
+
+/*IS_CONTINUOUS_TDMA_EVENT_TIMING_CHECK_SUPPORT: the timing difference of two succeed TDMA events should be larger than 1QB */
+#if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION && (!IS_CHIP_MT6256) && (!IS_CHIP_MT6251) && (!IS_CHIP_MT6255)
+#define IS_CONTINUOUS_TDMA_EVENT_TIMING_CHECK_SUPPORT 1
+#else
+#define IS_CONTINUOUS_TDMA_EVENT_TIMING_CHECK_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_IMM_BSI_SEND_DUMMY_READ_ON 1
+#else
+#define IS_IMM_BSI_SEND_DUMMY_READ_ON 0
+#endif
+
+#if IS_RF_AD6548 || IS_RF_MT6139E || IS_RF_MTKSOC1 || IS_RF_MT6252RF || IS_RF_MT6251RF || IS_RF_MT6255RF
+#define IS_EPSK_TX_NOT_SUPPORT_RF 1
+#else
+#define IS_EPSK_TX_NOT_SUPPORT_RF 0
+#endif
+
+#if defined(L1_SIM)
+#define IS_TDMA_BSI_READBACK_SUPPORT 0
+#elif IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+#define IS_TDMA_BSI_READBACK_SUPPORT 1
+#else
+#define IS_TDMA_BSI_READBACK_SUPPORT 0
+#endif
+
+#if defined(__CLASS_33_34__)
+#define IS_MULTISLOT_CLASS_33_34_SUPPORT 1
+#else
+#define IS_MULTISLOT_CLASS_33_34_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_VAMOS_CAPABILITY 1
+
+#define IS_VAMOS_SUPPORT 1
+
+#define IS_SHIFTSACCH_SUPPORT 1
+
+#else
+#define IS_VAMOS_CAPABILITY 0
+#define IS_VAMOS_SUPPORT 0
+#define IS_SHIFTSACCH_SUPPORT 0
+#endif
+
+#if defined(L1D_TEST) && (IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 )
+#define IS_COSIM_IRDMA_MPU_FULL_TEST_SUPPORT 1
+#else
+#define IS_COSIM_IRDMA_MPU_FULL_TEST_SUPPORT 0
+#endif
+
+#if defined(__UDVT__) && (IS_CHIP_MT6250 || IS_CHIP_MT6280)
+/* move the UDVT FH codes from the meut folder to l1 */
+#define IS_UDVT_FH_SUPPORT 1
+#else
+#define IS_UDVT_FH_SUPPORT 0
+#endif
+
+// Enable TXDFE A-Die Dump
+#define IS_L1D_TXDFE_A_DIE_DUMP_ENABLE 0
+
+// Enable RXDFE dump API
+#define IS_L1D_RXDFE_DUMP_ENABLE 0
+// Debug use; for setup of parameters to L1 through catcher
+#define IS_L1D_INJECT_STRING_DEBUG_ON 1
+
+#if IS_2G_L1D_ROBUST_MODEM_ENABLE
+#define IS_2G_L1D_ROBUST_MODEM_TRACE_ENABLE 1
+#else
+#define IS_2G_L1D_ROBUST_MODEM_TRACE_ENABLE 0
+#endif /* IS_2G_L1D_ROBUST_MODEM_ENABLE */
+/* Enable the patch to compensate DAC when 2g is in stand by , gets
+ * dac from active rat but difference is more than thershold
+ */
+// TDMA debug info
+#define IS_2G_TDMA_DEBUG_INFO_ENABLE 1
+
+#define IS_2G_STANDBY_OWN_DAC_SUPPORT 1
+
+/*Compensate timing erro based on SIM*/
+#define IS_2G_TIMING_CORRECT_SIM_BASE 1
+/*
+ * To handle the false alarm for the patch compensating afc dac in standby mode
+ */
+#if IS_2G_STANDBY_OWN_DAC_SUPPORT
+#define IS_2G_STANDBY_DAC_ENHANCEMENT_ENABLE 1
+#else
+#define IS_2G_STANDBY_DAC_ENHANCEMENT_ENABLE 0
+#endif
+
+
+#if IS_CHIP_MT6280
+ #if IS_CHIP_MT6280_S00
+#define IS_DCM_ISSUE_WORKAROUND_ON 1
+ #else
+#define IS_DCM_ISSUE_WORKAROUND_ON 1
+ #endif
+#define IS_USE_INTERNAL_TEMP_SENSOR 1
+#define IS_LOW_POWER_HQA_PDN_SUPPORT 1
+#elif IS_CHIP_MT6583_MD1
+#define IS_DCM_ISSUE_WORKAROUND_ON 0
+#define IS_USE_INTERNAL_TEMP_SENSOR 1 /* MT6583_MD1 is matched with MT6167 */
+#define IS_LOW_POWER_HQA_PDN_SUPPORT 1
+#elif IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DCM_ISSUE_WORKAROUND_ON 0
+#define IS_USE_INTERNAL_TEMP_SENSOR 1 /* MT6572 is matched with MT6166 */
+#define IS_LOW_POWER_HQA_PDN_SUPPORT 1
+#else
+#define IS_DCM_ISSUE_WORKAROUND_ON 0
+#define IS_USE_INTERNAL_TEMP_SENSOR 0
+#define IS_LOW_POWER_HQA_PDN_SUPPORT 0
+#endif
+
+// There are two methods to solve TC21.1
+// 1. Advance the BFE RX DCOC timing (SW solution)
+// => IS_RX_DCOC_ADVANCED_SUPPORT
+// => This feathure was disable since the side effect of failing FTA in-band block TC.
+// 2. HW adds the NB_ENx field to the RX_TYPE_CONx register (HW solution)
+// to distinguish between NB & SB/FB for RX_TYPEx = 0
+// => IS_BFE_RX_TYPE_NB_EN_SUPPORT (MT6572 BFE HW adds this new function)
+#if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_RX_DCOC_ADVANCED_SUPPORT 0
+#define IS_BFE_RX_TYPE_NB_EN_SUPPORT 1
+#elif IS_CHIP_MT6256_S00 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_RX_DCOC_ADVANCED_SUPPORT 0
+#define IS_BFE_RX_TYPE_NB_EN_SUPPORT 0
+#elif IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255)
+#define IS_RX_DCOC_ADVANCED_SUPPORT 1
+#define IS_BFE_RX_TYPE_NB_EN_SUPPORT 0
+#else
+#define IS_RX_DCOC_ADVANCED_SUPPORT 0
+#define IS_BFE_RX_TYPE_NB_EN_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6280
+#define IS_ANALOG_RXIQ_DEBUG_MODE_ON 0
+#define IS_INJECT_SIGNAL2ADC_DEBUG_MODE_ON 0
+#endif
+
+#ifdef __UE_SIMULATOR__
+#define IS_UESIM_DM_RF_INIT_SUPPORT 1
+#else
+#define IS_UESIM_DM_RF_INIT_SUPPORT 0
+#endif
+
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1)
+/* the ADC/DAC control are moved from RF to BB */
+#define IS_TDMA_AD_DA_WINDOW_SUPPORT 1
+#else
+#define IS_TDMA_AD_DA_WINDOW_SUPPORT 0
+#endif
+
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1)
+/* the TDMA will do the clipping when tq_count+tq_bias is larger than 16383 */
+#define IS_TDMA_CLIPPING_SUPPORT 1
+#else
+#define IS_TDMA_CLIPPING_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_APC_HALF_QB_RESOLUTION_SUPPORT 0
+#elif IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1)
+/* the APC supports 1/2 QB resolution */
+#define IS_APC_HALF_QB_RESOLUTION_SUPPORT 1
+#else
+#define IS_APC_HALF_QB_RESOLUTION_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_DSP_P2X_SUPPORT 1
+#else
+#define IS_DSP_P2X_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_WRITE_DSP_PATCH_BY_L1 1
+#else
+#define IS_WRITE_DSP_PATCH_BY_L1 0
+#endif
+
+#if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572
+ #if defined(__MODEM_CCCI_EXIST__)
+#define IS_REPORT_RF_TEMPERATURE_SUPPORT 1
+ #else
+#define IS_REPORT_RF_TEMPERATURE_SUPPORT 0
+ #endif
+#else
+#define IS_REPORT_RF_TEMPERATURE_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6280
+#define IS_REPORT_RF_TEMPERATURE_BYATCMD_SUPPORT 1
+#else
+#define IS_REPORT_RF_TEMPERATURE_BYATCMD_SUPPORT 0
+#endif
+
+#if defined(__2G_TX_VOLTAGE_COMPENSATION_SUPPORT__)
+ #if defined(__MODEM_CCCI_EXIST__)
+#define IS_TX_VOLTAGE_COMPENSATION_SUPPORT 1
+ #else
+#define IS_TX_VOLTAGE_COMPENSATION_SUPPORT 0
+ #endif
+#else
+#define IS_TX_VOLTAGE_COMPENSATION_SUPPORT 0
+#endif
+
+#if defined(__RF_WIDE_TEMPERATURE_SUPPORT__)
+#define IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT 1
+#else
+#define IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6583_MD2
+#define IS_SW_SECOND_VERSION_NEEDED 1
+#else
+#define IS_SW_SECOND_VERSION_NEEDED 0
+#endif
+
+#if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_TDMA_TDD_TIMER_SYNC_SUPPORT 1
+#else
+#define IS_TDMA_TDD_TIMER_SYNC_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2
+#define IS_GSM_BPI_MASK_NEEDED 1
+#else
+#define IS_GSM_BPI_MASK_NEEDED 0
+#endif
+
+#if IS_COSIM_ON_L1SIM_SUPPORT
+ #if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 ||IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#undef IS_TDMA_BSI_READBACK_SUPPORT
+#define IS_TDMA_BSI_READBACK_SUPPORT 1
+ #endif
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_BSISPI_SEPARATE_SUPPORT 1
+#else
+#define IS_BSISPI_SEPARATE_SUPPORT 0
+#endif
+
+/* If IS_MMRF_CONTROL_BSI_TOP_SUPPORT is supported, it means that BSISPI and BPI_TOP control are moved to MMRF driver. */
+#if IS_BSISPI_SEPARATE_SUPPORT
+ #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MMRF_CONTROL_BSI_TOP_SUPPORT 1
+ #else
+#define IS_MMRF_CONTROL_BSI_TOP_SUPPORT 0
+ #endif
+#else
+#define IS_MMRF_CONTROL_BSI_TOP_SUPPORT 0
+#endif
+
+#define IS_DUAL_TALK_SUPPORT 0
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DMA_REMOVED 1
+#else
+#define IS_DMA_REMOVED 0
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_RF_CENTRAL_CONTROL_SUPPORT 1
+#else
+#define IS_RF_CENTRAL_CONTROL_SUPPORT 0
+#endif
+
+#if IS_RF_CENTRAL_CONTROL_SUPPORT && IS_RF_MT6169
+#define IS_RF_CENTRAL_CONTROL_ENABLE 1
+#define IS_LTE_POWERON_CALIBRATION_ENABLE 1
+#elif IS_RF_CENTRAL_CONTROL_SUPPORT && ( IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M)
+#define IS_RF_CENTRAL_CONTROL_ENABLE 1
+#define IS_LTE_POWERON_CALIBRATION_ENABLE 0
+#else
+#define IS_RF_CENTRAL_CONTROL_ENABLE 0
+#define IS_LTE_POWERON_CALIBRATION_ENABLE 0
+#endif
+
+#if IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_RF_RAMPPROFILE_ROLLBACK_SUPPORT 1 // adjust ramping profile based on TX power rollback
+#else
+#define IS_RF_RAMPPROFILE_ROLLBACK_SUPPORT 0
+#endif
+
+#if IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6177M
+/* This compile option will effect NVRAM/Cross-Core Custom Folder Setting, it's always enable for specific RF */
+#define IS_2G_MMPOC_SUPPORT 1
+#else
+#define IS_2G_MMPOC_SUPPORT 0 // Bypass 2G RFC data Init and copying and under this compile options for Gen97
+#endif
+
+#if defined(__2G_MIPI_SUPPORT__)
+/*Check __2G_MIPI_SUPPORT__ setting at option.mak , if platform has been added*/
+#define IS_MIPI_SUPPORT 1
+#else
+#define IS_MIPI_SUPPORT 0
+#endif
+
+#if IS_MIPI_SUPPORT && ( IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297_AND_LATTER_VERSION )
+#define IS_MIPI_CENTRAL_CONTROL_SUPPORT 1
+#define IS_MIPI_CENTRAL_CONTROL_ENABLE 1
+#else
+#define IS_MIPI_CENTRAL_CONTROL_SUPPORT 0
+#define IS_MIPI_CENTRAL_CONTROL_ENABLE 0
+#endif
+
+#if IS_MIPI_SUPPORT && defined(__2G_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT__)
+/* Macro IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT has been removed from GL1 code after TK6291 */
+#define IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT 1
+#else
+#define IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+/* the frequency hopping is controled by system service */
+#define IS_FH_CONTROL_BY_SS 1
+#else
+#define IS_FH_CONTROL_BY_SS 0
+#endif
+
+#if IS_FH_CONTROL_BY_SS
+#undef IS_MPLL_FH_SUPPORT
+#undef IS_MPLLFH_FREE_RUN_SUPPORT_CHIP
+#undef IS_MPLLFH_FREE_RUN_ON
+#define IS_MPLL_FH_SUPPORT 0
+#define IS_MPLLFH_FREE_RUN_SUPPORT_CHIP 0
+#define IS_MPLLFH_FREE_RUN_ON 0
+#endif
+
+#if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+/* to support the DCS-TD co-existence feature */
+#define IS_DCS_NB_WB_SWITCH_SUPPORT 1
+#else
+#define IS_DCS_NB_WB_SWITCH_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6752_MD2
+#define IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT 1
+#else
+#define IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6752_MD2
+#define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_SUPPORT 1
+#else
+#define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_SUPPORT 0
+#endif
+
+#if IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT
+#define IS_DSDA_DCS_TX_NOTCH_SWITCH_ENABLE 0
+#else
+#define IS_DSDA_DCS_TX_NOTCH_SWITCH_ENABLE 0
+#endif
+
+#if IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_SUPPORT
+ #if defined(__LTE_TX_PATH_SWITCH_SUPPORT__)
+#define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_ENABLE 1
+ #else
+#define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_ENABLE 0
+ #endif
+#else
+#define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_ENABLE 0
+#endif
+
+#if defined(__PS_L1_DC_ARCH__)
+/* to support dual-core modem architecture */
+#define IS_DUAL_CORE_MODEM_SUPPORT 1
+#define IS_CTIRQ3_SUPPORT 0
+#else
+#define IS_DUAL_CORE_MODEM_SUPPORT 0
+#define IS_CTIRQ3_SUPPORT 0
+#endif /* defined(__PS_L1_DC_ARCH__) */
+
+#if IS_DUAL_CORE_MODEM_SUPPORT
+#define IS_DUAL_CORE_MODEM_L1D_UT_DEBUG 0
+ #if IS_CTIRQ3_SUPPORT
+#define IS_TRIGER_U1_AT_CT3 0
+ #else
+#define IS_TRIGER_U1_AT_CT3 0
+ #endif /* IS_CTIRQ3_SUPPORT */
+#define IS_SET_SBUF_AS_GLOBAL_VAR_SUPPORT 1
+#else
+#define IS_DUAL_CORE_MODEM_L1D_UT_DEBUG 0
+#define IS_TRIGER_U1_AT_CT3 0
+#define IS_SET_SBUF_AS_GLOBAL_VAR_SUPPORT 0
+#endif /* IS_DUAL_CORE_MODEM_SUPPORT */
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_OUTPUT_RF_VERSION_SUPPORT 1
+#else
+#define IS_OUTPUT_RF_VERSION_SUPPORT 0
+#endif
+
+#if defined (__ACC_NC_AFC_DB_UPDATE_SUPPORT__)
+#define IS_ACC_NC_AFC_DB_UPDATE_SUPPORT 1 /* Enable Accelerating NC AFC DB updating */
+#else
+#define IS_ACC_NC_AFC_DB_UPDATE_SUPPORT 0
+#endif
+
+
+#define IS_CSFB_WITH_SGLTE_HW_ENABLE 0
+
+#if IS_CSFB_WITH_SGLTE_HW_ENABLE
+ #if IS_RF_MT6165 || IS_RF_MT6166
+// CSFB_WITH_SGLTE_HW can only enable on MT6165/MT6166
+ #else
+#error "This RF Chip is not support CSFB with SGLTE HW."
+ #endif
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 /* Chipset support MML1 and DRDI */
+#define IS_L1_RF_DRDI_CUSTOM_SETTING_FROM_MML1 1
+#else
+#define IS_L1_RF_DRDI_CUSTOM_SETTING_FROM_MML1 0
+#endif
+
+#if defined (__TX_POWER_OFFSET_SUPPORT__)
+#define IS_TX_POWER_OFFSET_SUPPORT 1 /* Enable Tx power offset */
+#else
+#define IS_TX_POWER_OFFSET_SUPPORT 0 /* Disable Tx power offset */
+#endif /*__TX_POWER_OFFSET_SUPPORT__*/
+
+#if defined (__SAR_TX_POWER_BACKOFF_SUPPORT__)
+#define IS_SAR_TX_POWER_BACKOFF_SUPPORT 1 /* Enable Tx power offset for SAR test*/
+#define IS_2G_DYNAMIC_SAR_TABLE_SUPPORT 1
+#else
+#define IS_SAR_TX_POWER_BACKOFF_SUPPORT 0 /* Disable Tx power offset for SAR test*/
+#define IS_2G_DYNAMIC_SAR_TABLE_SUPPORT 0
+#endif /*__SAR_TX_POWER_BACKOFF_SUPPORT__*/
+#if defined(__RX_POWER_OFFSET_SUPPORT__)
+#define IS_RX_POWER_OFFSET_SUPPORT 1
+#else
+#define IS_RX_POWER_OFFSET_SUPPORT 0
+#endif/*__RX_POWER_OFFSET_SUPPORT__*/
+
+#if defined (__GSM_EM_TX_POWER_CONTROL_SUPPORT__)
+#define IS_GSM_EM_TX_POWER_CONTROL_SUPPORT 1 /* Enable EM Tx power control */
+#else
+#define IS_GSM_EM_TX_POWER_CONTROL_SUPPORT 0 /* Disable EM Tx power control */
+#endif
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_GSM_TX_DETECTOR_SUPPORT 1
+#else
+#define IS_GSM_TX_DETECTOR_SUPPORT 0
+#endif /* defined(__GSM_TX_DETECTOR_SUPPORT__) */
+
+#if defined (__NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__)
+
+ #if defined (__EPSK_ADJUST_TPO_SUPPORT__)
+#define IS_EPSK_ADJUST_TPO_SUPPORT 1 /*Enable Adjust TPO feature support on EPSK*/
+ #else
+#define IS_EPSK_ADJUST_TPO_SUPPORT 0 /*Disable Adjust TPO feature support on EPSK*/
+ #endif//__EPSK_ADJUST_TPO_SUPPORT__
+
+#define IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT 1 /* Enable NSFT Adjust Tx Power Offset */
+#else
+#define IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT 0 /* Disable NSFT Adjust Tx Power Offset */
+#endif /*__NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__*/
+
+#if defined (__EM_MAX_TX_POWER_SUPPORT__)
+#define IS_MAX_TX_POWER_CONTROL_SUPPORT 1 /* Enable MAX Tx power control */
+#else
+#define IS_MAX_TX_POWER_CONTROL_SUPPORT 0 /* Disable MAX Tx power control */
+#endif
+
+#if defined (__GSM_INCREASE_RACH_TX_POWER_SUPPORT__)
+#define IS_GSM_INCREASE_RACH_TX_POWER_SUPPORT 1 /* Enable RACH Tx power control */
+#else
+#define IS_GSM_INCREASE_RACH_TX_POWER_SUPPORT 0 /* Disable RACH Tx power control */
+#endif
+
+#if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_CC_NVRAM_CUSTOM_DATA_SUPPORT 1
+#else
+#define IS_CC_NVRAM_CUSTOM_DATA_SUPPORT 0
+#endif
+
+#if IS_CHIP_TK6291
+#define IS_TK6291_HW_BUG_SW_WORKAROUND_SUPPORT 1
+#else
+#define IS_TK6291_HW_BUG_SW_WORKAROUND_SUPPORT 0
+#endif
+
+#if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MD2G_MEM_CONFIG_SUPPORT_CHIP 1
+#else
+#define IS_MD2G_MEM_CONFIG_SUPPORT_CHIP 0
+#endif
+
+#if (IS_MD2G_MEM_CONFIG_SUPPORT_CHIP)
+ #if IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_CENTRALIZED_SW_TYPE_SETTING_SUPPORT 1
+ #else
+#define IS_CENTRALIZED_SW_TYPE_SETTING_SUPPORT 0
+ #endif /* IS_CHIP_MT6295 */
+#else
+#define IS_CENTRALIZED_SW_TYPE_SETTING_SUPPORT 0
+#endif /* IS_MD2G_MEM_CONFIG_SUPPORT_CHIP */
+
+#if defined(__TAS_SUPPORT__)
+ #if defined(__MD93__)
+ #define IS_2G_TAS_SUPPORT 1
+ #define IS_2G_Gen95_UTAS_SUPPORT 0
+ #define IS_2G_Gen97_UTAS_SUPPORT 0
+ #define IS_2G_TAS_INHERIT_4G_ANT 1
+ #elif defined(__MD95__) /*GL1D is not involved from Gen95 onwards since GL1C is taking care of it*/
+ #define IS_2G_TAS_SUPPORT 0
+ #define IS_2G_Gen95_UTAS_SUPPORT 1
+ #define IS_2G_Gen97_UTAS_SUPPORT 0
+ #define IS_2G_TAS_INHERIT_4G_ANT 0
+ #elif (defined(__MD97__) || defined(__MD97P__))
+ #define IS_2G_TAS_SUPPORT 0
+ #define IS_2G_Gen95_UTAS_SUPPORT 0
+ #define IS_2G_Gen97_UTAS_SUPPORT 1
+ #define IS_2G_TAS_INHERIT_4G_ANT 0
+ #else
+ #error "[ERROR] Invalid MD generation"
+ #endif
+ #define IS_2G_TAS_ANT_IDX_FOR_PM_WINDOW_SUPPORT 1
+#else
+#define IS_2G_TAS_SUPPORT 0
+#define IS_2G_TAS_ANT_IDX_FOR_PM_WINDOW_SUPPORT 0
+#define IS_2G_TAS_INHERIT_4G_ANT 0
+#define IS_2G_Gen95_UTAS_SUPPORT 0
+#define IS_2G_Gen97_UTAS_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT 1 /*Gen97 DAT is default enable*/
+#else
+#define IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT defined (__DYNAMIC_ANTENNA_TUNING__)
+#endif
+/*Please review those code usign this feature option*/
+#define IS_L1D_USEC_TRACE_SUPPORT 1
+
+#define IS_2G_UTAS97_DETAIL_FE_TIMING_DEBUG_TRACE_SUPPORT 0 /* Used for UTAS 97 detailed FE timing information*/
+
+
+#if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__)
+ #if defined(__MD93__)
+ #define IS_2G_DAT_SUPPORT 1
+ #define IS_2G_Gen95_UDAT_SUPPORT 0
+ #define IS_2G_Gen97_UDAT_SUPPORT 0
+ #elif defined(__MD95__)
+ #define IS_2G_DAT_SUPPORT 0
+ #define IS_2G_Gen95_UDAT_SUPPORT 1
+ #define IS_2G_Gen97_UDAT_SUPPORT 0
+ #elif (defined(__MD97__) || defined(__MD97P__))
+ #define IS_2G_DAT_SUPPORT 0
+ #define IS_2G_Gen95_UDAT_SUPPORT 0
+ #define IS_2G_Gen97_UDAT_SUPPORT 1
+ #else
+ #error "[ERROR] Invalid MD generation"
+ #endif
+#else
+#define IS_2G_DAT_SUPPORT 0
+#define IS_2G_Gen95_UDAT_SUPPORT 0
+#define IS_2G_Gen97_UDAT_SUPPORT 0
+#endif
+#if defined(__ANT_RXPWR_OFFSET_SUPPORT__)
+#define IS_ANT_RXPWR_OFFSET_SUPPORT 1
+#else
+#define IS_ANT_RXPWR_OFFSET_SUPPORT 0
+#endif
+
+/* Calculate TXRX active timing , default on for Andriod N feature */
+#define IS_TXRX_GET_INFO 1
+
+#define MD97_S2U_TIME 0
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_MM_APC_NEW_RAMP_CONFIGURE 0
+#else
+#define IS_MM_APC_NEW_RAMP_CONFIGURE 1
+#endif
+
+/* DRDI support capability */
+#if defined(__RF_DRDI_CAPABILITY_SUPPORT__)
+#define IS_2G_DRDI_SUPPORT 1
+#else
+#define IS_2G_DRDI_SUPPORT 0
+#endif
+
+/* 2G support PRX1 or DRX1 */
+#if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_2G_ALTERNATIVE_RX_PATH_SUPPORT 1
+#else
+#define IS_2G_ALTERNATIVE_RX_PATH_SUPPORT 0
+#endif
+
+/* 2G support PRX1 or DRX1 */
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) && (IS_2GRXD_CHIP_MT6765_AND_LATTER_VERSION || IS_CHIP_MT6295) || IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT
+
+#define IS_2G_RXD_SUPPORT 1
+#define IS_2G_RXD_ENHANCEMENT_SUPPORT 1
+
+#define IS_GSM_RX_RXD_MODE_FIXED 0 //Force RXD mode before GL1C RAS involve
+
+#else
+
+#define IS_2G_RXD_SUPPORT 0
+#define IS_2G_RXD_ENHANCEMENT_SUPPORT 0
+
+#define IS_GSM_RX_RXD_MODE_FIXED 0
+#endif
+
+#if IS_2G_RXD_SUPPORT
+#define IS_2G_RAS_CROSS_MODE_SUPPORT 1
+#define IS_2G_RAS_DECISION_INCLUDE_DSP_POW_SUPPORT 1
+#if IS_CHIP_MT6853_AND_LATTER_VERSION // Gen97, C-value enable Mouton and latter
+#define IS_2G_C_VALUE_SUPPORT 1
+#endif
+#else
+#define IS_2G_RAS_CROSS_MODE_SUPPORT 0
+#define IS_2G_RAS_DECISION_INCLUDE_DSP_POW_SUPPORT 0
+#define IS_2G_C_VALUE_SUPPORT 0
+#endif
+
+#if defined(__2G_RXD_BLACKLIST_SUPPORT__)
+#define IS_2G_RXD_BLACKLIST_SUPPORT 1
+#else
+#define IS_2G_RXD_BLACKLIST_SUPPORT 0
+#endif
+
+/* For L1C Dummy LISR removal, added debug traces */
+#if (IS_CHIP_MT6292) && (defined __MTK_TARGET__)
+#define IS_2G_DUMMY_LISR_REMOVAL_DEBUG 1
+#else
+#define IS_2G_DUMMY_LISR_REMOVAL_DEBUG 0
+#endif
+
+#if defined(__GSM_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT__)
+#define IS_2G_DYNAMIC_HW_CLOCK_SUPPORT 1 //Adjust HW clock for specific ARFCNs
+#else
+#define IS_2G_DYNAMIC_HW_CLOCK_SUPPORT 0
+#endif
+
+/* Support using external LNA and adjust RX gain table in L1 code flow */
+#if IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_2G_EXTERNAL_LNA_SUPPORT 1
+#else
+#define IS_2G_EXTERNAL_LNA_SUPPORT 0
+#endif
+
+#if IS_RF_MT6186M || IS_RF_MT6190T
+#define IS_2G_WITHOUT_MATCHING_NETWORK_SUPPORT 0
+#else
+#define IS_2G_WITHOUT_MATCHING_NETWORK_SUPPORT 0
+#endif
+
+/* Support using BYPASS and adjust RX gain table in L1 code flow */
+#if IS_2G_EXTERNAL_LNA_SUPPORT
+ #if IS_RF_MT6190T
+#define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0
+ #elif IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M
+#define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 1
+ #elif IS_RF_MT6177L || IS_RF_MT6177M
+#define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0
+ #else
+#define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 0
+#define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 0
+#define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0
+ #endif
+#else
+#define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 0
+#define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 0
+#define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0
+#endif
+
+#if IS_2G_EXTERNAL_LNA_SUPPORT
+#define IS_2G_EXTERNAL_LNA_FSI_SYNC_SUPPORT 1
+#else
+#define IS_2G_EXTERNAL_LNA_FSI_SYNC_SUPPORT 0
+#endif
+#if IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_NEW_FD216_RESTART_FLOW_ENABLE 1
+#define IS_SPEECH_uSIP_SUPPORT 1
+#define IS_MD_TOPSM_API_USING 1
+#define IS_FIXED_DSPCLK 1
+#define IS_DSP_DM_4BYTE_ALIGN_CHIP 1
+#else
+#define IS_NEW_FD216_RESTART_FLOW_ENABLE 0
+#define IS_SPEECH_uSIP_SUPPORT 0
+#define IS_MD_TOPSM_API_USING 0
+#define IS_FIXED_DSPCLK 0
+#define IS_DSP_DM_4BYTE_ALIGN_CHIP 0
+#endif
+
+#if IS_CHIP_MT6295
+#define IS_DYNAMICAL_NOISE_FLOOR_AND_SATURATION_SUPPORT 1
+#else
+#define IS_DYNAMICAL_NOISE_FLOOR_AND_SATURATION_SUPPORT 0
+#endif
+
+#if defined(__A54_ALGORITHM_SUPPORT__)
+#define IS_A54_ALGORITHM_SUPPORT 1
+#else
+#define IS_A54_ALGORITHM_SUPPORT 0
+#endif
+
+#if defined(__MMRF_RF_HAL_SEQ_GEN_SUPPORT__)
+ #if IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M
+#define IS_HAL_SUPPORT 1
+ #else
+#define IS_HAL_SUPPORT 0
+ #endif
+#endif
+
+/*Some check condition for IS_2G_Gen95_UTAS_SUPPORT */
+//#if IS_2G_Gen95_UTAS_SUPPORT && XXXX
+//#error "IS_2G_Gen95_UTAS_SUPPORT not porting for XXXX yet!!!"
+//#endif
+
+#if defined(__MTK_TARGET__)
+ #if (IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT) && (!IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT)
+#error "(IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT) only porting for IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT !!!"
+ #endif
+
+ #if (IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT) && (!IS_2G_RXD_SUPPORT)
+#error "(IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT ) only porting for IS_2G_RXD_SUPPORT !!!"
+ #endif
+#endif
+
+#if IS_CHIP_MT6295
+#define IS_2G_TX_COARSE_DCOC_SUPPORT 1
+#else
+#define IS_2G_TX_COARSE_DCOC_SUPPORT 0
+#endif /* IS_CHIP_MT6295 */
+
+
+/*===================================================================*/
+/* BBTX/BBRX chip design version */
+/*===================================================================*/
+#define BBTXRX_VER_1 1
+#define BBTXRX_VER_2 2
+#define BBTXRX_VER_3 3
+
+#if IS_CHIP_MT6583_MD2
+#define BBTXRX_CHIP_DESIGN_VER BBTXRX_VER_3
+#elif IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575
+#define BBTXRX_CHIP_DESIGN_VER BBTXRX_VER_2
+#else
+#define BBTXRX_CHIP_DESIGN_VER BBTXRX_VER_1
+#endif
+
+#define IS_BBTXRX_CHIP_DESIGN_VER_1 (BBTXRX_CHIP_DESIGN_VER == BBTXRX_VER_1)
+#define IS_BBTXRX_CHIP_DESIGN_VER_2 (BBTXRX_CHIP_DESIGN_VER == BBTXRX_VER_2)
+#define IS_BBTXRX_CHIP_DESIGN_VER_3 (BBTXRX_CHIP_DESIGN_VER == BBTXRX_VER_3)
+
+/*===================================================================*/
+/* CHIP ZIMAGE setting */
+/*===================================================================*/
+#if IS_CHIP_MT6252
+#define IS_PRIMARY_ROCODE 1
+#else
+#define IS_PRIMARY_ROCODE 0
+#endif
+
+/*===================================================================*/
+/* CHIP Partial Internal RAM settings */
+/*===================================================================*/
+#define INTERN_NULL 0
+#define INTERN_FULL 1
+#define INTERN_PARTIAL 2
+#define INTERN_PARTIAL_CRITICAL 3
+
+/*===================================================================*/
+/* WT co-bin feature compile option check */
+/*===================================================================*/
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+ #if defined(__AST2001__) || defined(__AST3001__)
+#error "WT Co-bin feature does not support these phase out feature!"
+ #endif
+ #if IS_3GRF_DETECT
+#error "WT Co-bin feature does not support phase out feature: IS_3GRF_DETECT !"
+ #endif
+ #if IS_DEFAULT_TURNOFF_3GMTCMOS
+#error "WT Co-bin feature does not support phase out feature: IS_DEFAULT_TURNOFF_3GMTCMOS !"
+ #endif
+ #if IS_GCMACHINE_V3_UMTS_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_GCMACHINE_V3_UMTS_SUPPORT !"
+ #endif
+ #if IS_GCMACHINE_V4_HSPA_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_GCMACHINE_V4_HSPA_SUPPORT !"
+ #endif
+ #if IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT !"
+ #endif
+ #if IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT !"
+ #endif
+ #if IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT !"
+ #endif
+ #if IS_SRCLKENA_TRIG_VRF28_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_SRCLKENA_TRIG_VRF28_SUPPORT !"
+ #endif
+ #if IS_AST_B2S_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_AST_B2S_SUPPORT !"
+ #endif
+ #if IS_TDDM_AFC_TRANSFORM_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_TDDM_AFC_TRANSFORM_SUPPORT !"
+ #endif
+ #if IS_CSFB_WITH_SGLTE_HW_ENABLE
+#error "WT Co-bin feature does not support phase out feature: IS_CSFB_WITH_SGLTE_HW_ENABLE !"
+ #endif
+#endif
+/* ------------------------------------------------------------- */
+// Global compiler option for vs1 low power feature of MT6293
+/* ------------------------------------------------------------- */
+#if defined(__PMIC_VS1_LOW_POWER_CTRL_SUPPORT__ )
+ #define IS_2G_PMIC_VS1_LOW_POWER_CTRL_SUPPORT 1
+#else
+ #define IS_2G_PMIC_VS1_LOW_POWER_CTRL_SUPPORT 0
+#endif
+
+/* ------------------------------------------------------------- */
+// default value
+/* ------------------------------------------------------------- */
+#if IS_CHIP_MT6205 || IS_CHIP_MT6225 || IS_CHIP_MT6223 || IS_CHIP_MT6238_SER || IS_CHIP_MT6276 || IS_CHIP_MT6251 || IS_CHIP_MT6573 || IS_CHIP_MT6252 || IS_CHIP_MT6256 || IS_CHIP_MT6575 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define INTERNCODE_DEFAULT INTERN_NULL
+#else
+#define INTERNCODE_DEFAULT INTERN_FULL
+#endif
+/* ------------------------------------------------------------- */
+#if IS_CHIP_MT6205 || IS_CHIP_MT6225 || IS_CHIP_MT6223 || IS_CHIP_MT6238_SER || IS_CHIP_MT6276 || IS_CHIP_MT6253 || IS_CHIP_MT6251 || IS_CHIP_MT6573 || IS_CHIP_MT6256 || IS_CHIP_MT6575 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define INTERNDATA_DEFAULT INTERN_NULL
+#else
+#define INTERNDATA_DEFAULT INTERN_FULL
+#endif
+/* ------------------------------------------------------------- */
+
+/* ------------------------------------------------------------- */
+#define INTERNCODE_M11303 INTERNCODE_DEFAULT
+#define INTERNCODE_M12100 INTERNCODE_DEFAULT
+#define INTERNCODE_M12110 INTERNCODE_DEFAULT
+#define INTERNCODE_M12120 INTERNCODE_DEFAULT
+#define INTERNCODE_M12160 INTERNCODE_DEFAULT
+#define INTERNCODE_M12168 INTERNCODE_DEFAULT
+#define INTERNCODE_M12170 INTERNCODE_DEFAULT
+#define INTERNCODE_M12180 INTERNCODE_DEFAULT
+/* ------------------------------------------------------------- */
+#define INTERNDATA_M11303 INTERNDATA_DEFAULT
+#define INTERNDATA_M12100 INTERNDATA_DEFAULT
+#define INTERNDATA_M12110 INTERNDATA_DEFAULT
+#define INTERNDATA_M12120 INTERNDATA_DEFAULT
+#define INTERNDATA_M12160 INTERNDATA_DEFAULT
+#define INTERNDATA_M12168 INTERNDATA_DEFAULT
+#define INTERNDATA_M12170 INTERNDATA_DEFAULT
+#define INTERNDATA_M12180 INTERNDATA_DEFAULT
+#define INTERNDATA_M12194 INTERNDATA_DEFAULT
+#define INTERNDATA_L1D_DATA INTERNDATA_DEFAULT
+#define INTERNDATA_L1D_INTERNAL_DATA INTERNDATA_DEFAULT
+/* ------------------------------------------------------------- */
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+#define INTERNCODE_M12167 INTERNCODE_DEFAULT
+#define INTERNDATA_M12167 INTERNDATA_DEFAULT
+#else
+#define INTERNCODE_M12167 INTERN_NULL
+#define INTERNDATA_M12167 INTERN_NULL
+#endif
+/* ------------------------------------------------------------- */
+#if IS_CHIP_MT6253 || IS_CHIP_MT6236 /* MPLL FH support chips */
+#define INTERNCODE_M12171 INTERNCODE_DEFAULT
+#define INTERNDATA_M12171 INTERNDATA_DEFAULT
+#else
+#define INTERNCODE_M12171 INTERN_NULL
+#define INTERNDATA_M12171 INTERN_NULL
+#endif
+/* ------------------------------------------------------------- */
+
+#if IS_CHIP_MT6238_SER /* code: all off, data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M12100
+#undef INTERNCODE_M12110
+#undef INTERNCODE_M12120
+#undef INTERNCODE_M12160
+#undef INTERNCODE_M12170
+#define INTERNCODE_M12100 INTERN_FULL
+ #if IS_GEMINI_SUPPORT
+#define INTERNCODE_M12110 INTERN_PARTIAL
+#define INTERNCODE_M12120 INTERN_PARTIAL
+ #else
+#define INTERNCODE_M12110 INTERN_FULL
+#define INTERNCODE_M12120 INTERN_FULL
+ #endif
+#define INTERNCODE_M12160 INTERN_FULL
+#define INTERNCODE_M12170 INTERN_FULL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12100
+#undef INTERNDATA_M12110
+#undef INTERNDATA_M12120
+#undef INTERNDATA_M12160
+#undef INTERNDATA_M12170
+#undef INTERNDATA_L1D_DATA
+#undef INTERNDATA_L1D_INTERNAL_DATA
+#define INTERNDATA_M12100 INTERN_FULL
+#define INTERNDATA_M12110 INTERN_FULL
+#define INTERNDATA_M12120 INTERN_FULL
+#define INTERNDATA_M12160 INTERN_FULL
+#define INTERNDATA_M12170 INTERN_FULL
+#define INTERNDATA_L1D_DATA INTERN_FULL
+#define INTERNDATA_L1D_INTERNAL_DATA INTERN_FULL
+
+#elif IS_CHIP_MT6255 || IS_CHIP_MT6250
+
+#undef INTERNCODE_M11303
+#define INTERNCODE_M11303 INTERN_PARTIAL_CRITICAL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12100
+#undef INTERNDATA_M12168
+#undef INTERNDATA_M12170
+#define INTERNDATA_M12100 INTERN_FULL
+#define INTERNDATA_M12168 INTERN_FULL
+#define INTERNDATA_M12170 INTERN_FULL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6235_SER /* code: all on , data: all on */
+/* ------------------------------------------------------------- */
+ #if IS_GEMINI_SUPPORT
+#undef INTERNCODE_M12110
+#undef INTERNCODE_M12120
+#define INTERNCODE_M12110 INTERN_PARTIAL
+#define INTERNCODE_M12120 INTERN_PARTIAL
+ #endif
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6252 /* code: all off, data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M11303
+#undef INTERNCODE_M12110
+#undef INTERNCODE_M12120
+#undef INTERNCODE_M12168
+#undef INTERNCODE_M12180
+#define INTERNCODE_M11303 INTERN_PARTIAL_CRITICAL
+#define INTERNCODE_M12110 INTERN_PARTIAL_CRITICAL
+#define INTERNCODE_M12120 INTERN_PARTIAL_CRITICAL
+#define INTERNCODE_M12168 INTERN_PARTIAL_CRITICAL
+#define INTERNCODE_M12180 INTERN_PARTIAL_CRITICAL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6253 /* code: all on , data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M11303
+#undef INTERNCODE_M12110
+#undef INTERNCODE_M12120
+#undef INTERNCODE_M12160
+#undef INTERNCODE_M12167
+#undef INTERNCODE_M12168
+#define INTERNCODE_M11303 INTERN_PARTIAL
+#define INTERNCODE_M12110 INTERN_PARTIAL
+#define INTERNCODE_M12120 INTERN_PARTIAL
+#define INTERNCODE_M12160 INTERN_PARTIAL
+#define INTERNCODE_M12167 INTERN_NULL
+#define INTERNCODE_M12168 INTERN_NULL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12100
+#undef INTERNDATA_M12160
+#undef INTERNDATA_M12170
+#undef INTERNDATA_M12171
+#define INTERNDATA_M12100 INTERN_FULL
+#define INTERNDATA_M12160 INTERN_FULL
+#define INTERNDATA_M12170 INTERN_FULL
+#define INTERNDATA_M12171 INTERN_FULL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6223 /* code: all off, data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M11303
+#undef INTERNCODE_M12100
+#undef INTERNCODE_M12110
+#undef INTERNCODE_M12120
+#undef INTERNCODE_M12160
+#undef INTERNCODE_M12170
+#define INTERNCODE_M11303 INTERN_PARTIAL
+#define INTERNCODE_M12100 INTERN_FULL
+#define INTERNCODE_M12110 INTERN_PARTIAL
+#define INTERNCODE_M12120 INTERN_PARTIAL
+#define INTERNCODE_M12160 INTERN_PARTIAL
+#define INTERNCODE_M12170 INTERN_PARTIAL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6225 /* code: all off, data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M12160
+#undef INTERNCODE_M12170
+#define INTERNCODE_M12160 INTERN_FULL
+#define INTERNCODE_M12170 INTERN_FULL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12160
+#undef INTERNDATA_M12170
+#define INTERNDATA_M12160 INTERN_FULL
+#define INTERNDATA_M12170 INTERN_FULL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6218 || IS_CHIP_MT6219 || IS_CHIP_MT6227
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M12100
+#define INTERNCODE_M12100 INTERN_NULL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12100
+#define INTERNDATA_M12100 INTERN_NULL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6205 /* code: all off, data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M12160
+#undef INTERNCODE_M12170
+#define INTERNCODE_M12160 INTERN_FULL
+#define INTERNCODE_M12170 INTERN_FULL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12160
+#undef INTERNDATA_M12170
+#undef INTERNDATA_L1D_DATA
+#define INTERNDATA_M12160 INTERN_FULL
+#define INTERNDATA_M12170 INTERN_FULL
+#define INTERNDATA_L1D_DATA INTERN_FULL
+/* ------------------------------------------------------------- */
+#endif
+
+/*===============================================================================================*/
+#endif
+
diff --git a/mcu/interface/l1/gl1/external/l1d_data_l1core.h b/mcu/interface/l1/gl1/external/l1d_data_l1core.h
new file mode 100644
index 0000000..a7644bc
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_data_l1core.h
@@ -0,0 +1,2381 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_data_l1core.h
+ *
+ * Project:
+ * --------
+ * MT6208
+ *
+ * Description:
+ * ------------
+ * Definition of global data & tables used in L1D
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
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+ *******************************************************************************/
+
+#ifndef _L1D_DATA_L1CORE_H_
+#define _L1D_DATA_L1CORE_H_
+/*---------------------------------------------------------------------------*/
+
+#if IS_RF_TOOL_CUSTOMIZATION_SUPPORT || IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2
+#define CONST
+#else
+#define CONST const
+#endif
+
+#if IS_BPI_DATA_48_BIT_CHIP
+typedef APBADDR32 APBADDR_P; /* a pointer to unsigned 32 bits */
+typedef unsigned long long sint_P; /* unsigned 64 bits */
+#elif IS_BPI_DATA_32_BIT_CHIP
+typedef APBADDR32 APBADDR_P;
+typedef unsigned long sint_P;
+#else
+typedef APBADDR APBADDR_P;
+typedef signed short sint_P;
+#endif
+
+#if IS_BSI_CON_32_BIT_CHIP
+typedef APBADDR32 APBADDR_S;
+typedef signed long sint_S;
+#else
+typedef APBADDR APBADDR_S;
+typedef signed short sint_S;
+#endif
+
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+/*MT6229~*/ #define TQ_CTIRQ12_R23_DELAY 400
+/*MT6229~*/ #if IS_CHIP_MT6251 /*GSM only*/
+/*MT6229~*/ #define TQ_CTIRQ12_DELAY 0
+/*MT6229~*/ #elif IS_CHIP_MT6253 /*Not support EDGE*/
+/*MT6229~*/ #define TQ_CTIRQ12_DELAY 400 // 760
+/*MT6229~*/ #elif IS_CHIP_MT6223 /*Not support EDGE*/
+/*MT6229~*/ #if IS_GPRS
+/*MT6229~*/ #define TQ_CTIRQ12_DELAY 400
+/*MT6229~*/ #else /*GSM only */
+/*MT6229~*/ #define TQ_CTIRQ12_DELAY 0
+/*MT6229~*/ #endif
+/*MT6229~*/ #elif IS_CHIP_MT6236 /*jason: for MPLL down hopping, need to gain 100 more for DSP*/
+/*MT6229~*/ #define TQ_CTIRQ12_DELAY 860
+/*MT6229~*/ #else /*Support EDGE*/
+/*MT6229~*/ #define TQ_CTIRQ12_DELAY 760
+/*MT6229~*/ #endif
+#elif IS_CHIP_MT6218_AND_LATTER_VERSION /*&& !defined(L1D_TEST)*/ //For cosim and loopback, MCU will always run 104MHz
+/*MT6218B~*/ #define TQ_CTIRQ12_R23_DELAY 400
+/*MT6218B~*/ #define TQ_CTIRQ12_DELAY 400
+#else
+/*OTHERS*/ #define TQ_CTIRQ12_R23_DELAY 0
+/*OTHERS*/ #define TQ_CTIRQ12_DELAY 0
+#endif
+
+#if defined(L1_SIM)
+#undef TQ_CTIRQ12_DELAY
+ #if IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT
+#define TQ_CTIRQ12_DELAY 760
+ #else
+#define TQ_CTIRQ12_DELAY 400
+ #endif
+#endif
+
+#if IS_NEW_L1D_ARCH_SUPPORT
+ #if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+#undef TQ_CTIRQ12_DELAY
+#define TQ_CTIRQ12_DELAY 0
+ #endif
+#endif
+
+#if IS_DSP_COSTDOWN_FB_CHIP
+#define TQ_FSWIN_DTIRQ_DELATY_SLOT6 156 /*Set 100Qb before Slot0, for DSP has enough margin to deal FB data*/
+#endif
+
+/*--------------------------------------------------------*/
+/* define TSU event time in QB */
+/*--------------------------------------------------------*/
+#if IS_TDMA_CLIPPING_SUPPORT
+#define TQ_MAXIMUM 16383 /*16383: 0x3FFF*/
+#else
+#define TQ_MAXIMUM (2*TQ_WRAP_COUNT+TQ_SLOT_LEN) /*10624: 2 frames + 1 slot*/
+#endif
+#define TQ_BURST_HEAD_GUARD 16
+#define TQ_SLOT_LEN (156*4)
+#define TQ_SLOT0_BEGIN (TQ_AFC_READY)
+#define TQ_SLOT1_BEGIN (TQ_SLOT0_BEGIN+625)
+#define TQ_SLOT2_BEGIN (TQ_SLOT1_BEGIN+625)
+#define TQ_SLOT3_BEGIN (TQ_SLOT2_BEGIN+625)
+#define TQ_SLOT4_BEGIN (TQ_SLOT3_BEGIN+625)
+#define TQ_SLOT5_BEGIN (TQ_SLOT4_BEGIN+625)
+#define TQ_SLOT6_BEGIN (TQ_SLOT5_BEGIN+625)
+#define TQ_SLOT7_BEGIN (TQ_SLOT6_BEGIN+625)
+#define TQ_TX2RX_LEN (TQ_SLOT3_BEGIN-TQ_SLOT0_BEGIN)
+#define TQ_TX_SLOT0_BEGIN (TQ_SLOT0_BEGIN+TQ_TX2RX_LEN)
+#define TQ_WRAP_COUNT 5000
+#define TQ_VALIDATE_OFFSET 1
+#define TQ_VALIDATE_COUNT (TQ_WRAP_COUNT-60-TQ_VALIDATE_OFFSET) /*4939*/
+#define TQ_VALIDATE (TQ_VALIDATE_COUNT+TQ_VALIDATE_OFFSET) /*4940*/
+#define TQ_CTIRQ1 (TQ_SLOT5_BEGIN+TQ_CTIRQ12_DELAY)
+#if IS_NEW_L1D_ARCH_SUPPORT
+ #if IS_MT6276_ADCMUX_CHECK_CHIP
+#define TQ_CTIRQ2 (TQ_SLOT0_BEGIN-200)
+ #else
+#define TQ_CTIRQ2 (TQ_SLOT0_BEGIN)
+ #endif
+#else
+#define TQ_CTIRQ2 (TQ_SLOT4_BEGIN+TQ_CTIRQ12_DELAY)
+#endif
+#if IS_CTIRQ3_SUPPORT
+#define TQ_CTIRQ3 (TQ_CTIRQ1-300)
+#endif /* IS_CTIRQ3_SUPPORT */
+#define TQ_DTIRQ 2
+#define TQ_CTIRQ1_R23 (TQ_SLOT5_BEGIN+TQ_CTIRQ12_R23_DELAY)
+#define TQ_CTIRQ2_R23 (TQ_SLOT4_BEGIN+TQ_CTIRQ12_R23_DELAY)
+
+#if L1D_PM_ENHANCE
+#define SHORT_PM_LEN 64
+#define TQ_SHORT_PMWIN_LEN_IN_IDLE (SHORT_PM_LEN*4)
+ #if L1D_PM_1R7PM
+#define PM_LEN_1R7PM 32
+#define TQ_1R7PM_PMWIN_LEN_IN_IDLE (PM_LEN_1R7PM*4)
+ #endif
+#endif
+
+#define PM_LEN 64
+#define TQ_SHORT_PMWIN_LEN (PM_LEN*4)
+
+
+#define TQ_AFC_0_DEFAULT 0
+#define TQ_AFC_1_DEFAULT TQ_SLOT4_BEGIN
+#define TQ_AFC_2_DEFAULT TQ_SLOT4_BEGIN
+#define TQ_AFC_CHARGE_IN_IDLE_VCXO (TQ_AFC_IDLE_LEN_VCXO)
+#define TQ_AFC_CHARGE_IN_IDLE_VCTCXO (TQ_AFC_IDLE_LEN_VCTCXO)
+#define TQ_AFC_CHARGE_IN_DEDI (13*(TQ_WRAP_COUNT/8))
+#define TQ_AB_LEN (16+4*88+16)
+#define TQ_AB_END_ADVANCED (TQ_SLOT_LEN-TQ_AB_LEN)
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+ #if IS_FDD_DUAL_MODE_SUPPORT
+#define TQ_FIRST_4PM_ADV_FDD 368 // = 624-256 => make PM0 starting time align 256QB
+ #if IS_GL1D_TW_COEXIST_SUPPORT
+#define TQ_FIRST_4PM_ADV 368 // Allign TDD PM also to 256QB
+ #else
+#define TQ_FIRST_4PM_ADV 0
+ #endif
+ #else
+ #if L1D_WT_CBBIN_UT_T_ONLY_BUILD
+#define TQ_FIRST_4PM_ADV_FDD 368 // = 624-256 => make PM0 starting time align 256QB
+ #endif
+#define TQ_FIRST_4PM_ADV 0
+ #endif
+#else /* L1D_WT_COBIN_ARCHITECTURE_SUPPORT */
+ #if IS_FDD_DUAL_MODE_SUPPORT
+#define TQ_FIRST_4PM_ADV 368 // = 624-256 => make PM0 starting time align 256QB
+ #else
+#define TQ_FIRST_4PM_ADV 0
+ #endif
+#endif /* L1D_WT_COBIN_ARCHITECTURE_SUPPORT */
+
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+ #if IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT && IS_DSP_SHORT_SB_ENABLED
+#define TQ_SBWIN_DSP_EXTEND1 28
+#define TQ_SBWIN_DSP_EXTEND2 28
+#define SB_TIMING_SHIFT_BASE 52
+ #else
+#define TQ_SBWIN_DSP_EXTEND1 52
+#define TQ_SBWIN_DSP_EXTEND2 52
+#define SB_TIMING_SHIFT_BASE 52
+ #endif
+#else
+#define TQ_SBWIN_DSP_EXTEND1 28
+#define TQ_SBWIN_DSP_EXTEND2 28
+#define SB_TIMING_SHIFT_BASE 28
+#endif
+
+#define TQ_SBWIN_LEN (TQ_SBWIN_DSP_EXTEND1+TQ_SLOT_LEN+TQ_SBWIN_DSP_EXTEND2)
+#define TQ_FSWIN_STOP_FSYNC (TQ_VALIDATE+10)
+
+#define TQ_BSI_READ_TIME (TQ_SLOT0_BEGIN+TQ_SLOT_LEN-100)
+
+// for switching FB algorithm on MT6229
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+
+ #ifdef L1D_TEST
+#define MT6229_FB_ON_MT6229 1
+#define MT6229_FB_SCALING 1 //loopback and cosim should 1
+ #else
+#define MT6229_FB_ON_MT6229 1
+#define MT6229_FB_SCALING 1
+ #endif
+
+#define MT6229_FB_VCXO 1
+
+#else
+#define MT6229_FB_ON_MT6229 0
+#define MT6229_FB_SCALING 0
+#define MT6229_FB_VCXO 0
+#endif /*IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION*/
+
+
+/* The 3rd stage FB algorithm of MT6229 sometime finds a FB but with bad QI. */
+/* In the original design, DSP will try to decode SB automatically even if QI is bad. */
+/* In order improve it, L1 will reset DSP to search FB again if FB with bad QI is detected */
+#if MT6229_FB_ON_MT6229
+ #if IS_CHIP_MT6268T || (IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION && !IS_CHIP_MT6253T && !IS_CHIP_MT6516)
+#define RESET_FB_WITH_BAD_QI 1
+ #else
+#define RESET_FB_WITH_BAD_QI 0
+ #endif
+#else
+#define RESET_FB_WITH_BAD_QI 0
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+/* todo : remeber to change the enable flag definition in l1d_reg.h */
+
+#if IS_FPGA_TARGET || IS_CHIP_MT6208
+/*FPGA,MT6208*/ #define AFCEN(n) ((n)<<3)
+/*FPGA,MT6208*/ #define AFCEN3 (0x8000)
+#endif
+
+#if IS_CHIP_MT6205_AND_LATTER_VERSION || IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+/*MT6205~*/#define AFCEN(n) ((n)<<12)
+/*MT6205~*/#define AFCEN3 (0x8000)
+#endif
+
+#if IS_CHIP_MT6205
+/*MT6205*/ #define BSI_EVENT_COUNT 13
+/*MT6205*/ #define BSI_DATA_COUNT 22
+#elif IS_CHIP_MT6208 || IS_CHIP_MT6218 || IS_CHIP_MT6219
+/*MT6218*/ #define BSI_EVENT_COUNT 16
+/*MT6218*/ #define BSI_DATA_COUNT 26
+#elif IS_CHIP_MT6227_AND_LATTER_VERSION
+/*MT6227*/ #define BSI_EVENT_COUNT 16
+/*MT6227*/ #define BSI_DATA_COUNT 27
+#elif IS_CHIP_MT6268T_DMAC
+/*MT6270*/ #define BSI_EVENT_COUNT 20 // DE JC Lin comment: align 68A
+/*MT6270*/ #define BSI_DATA_COUNT 65
+#elif IS_CHIP_MT6268H
+/*MT6270*/ #define BSI_EVENT_COUNT 36
+/*MT6270*/ #define BSI_DATA_COUNT 104
+#elif IS_CHIP_TK6291
+/*MT6291*/ #define BSI_EVENT_COUNT 120
+/*MT6291*/ #define BSI_DATA_COUNT 360
+#elif IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+/*MT6755*/ #define BSI_RFIC_EVENT_COUNT 32
+/*MT6755*/ #define BSI_MIPI_EVENT_COUNT 88
+/*MT6755*/ #define BSI_RFIC_DATA_COUNT 256 //BSI_DATA_COUNT value remains the same for RFIC and MIPI instances hence keeping a common macro define
+/*MT6755*/ #define BSI_MIPI_DATA_COUNT 256
+#elif IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2
+/*MT6290*/ #define BSI_EVENT_COUNT 103
+/*MT6290*/ #define BSI_DATA_COUNT 304
+#elif IS_CHIP_MT6572
+/*MT6572*/ #define BSI_EVENT_COUNT 54
+/*MT6572*/ #define BSI_DATA_COUNT 196
+#elif IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2
+ #if IS_CHIP_MT6270A_E1 || IS_CHIP_MT6276_S00 || IS_CHIP_MT6573
+/*MT6270*/ #define BSI_EVENT_COUNT 36 // for MT6270A E1, MT6276E1, MT6573
+/*MT6270*/ #define BSI_DATA_COUNT 104 // for MT6270A E1, MT6276E1, MT6573
+ #else
+/*MT6270*/ #define BSI_EVENT_COUNT 42 // for MT6270A E2, MT6276E2
+/*MT6270*/ #define BSI_DATA_COUNT 128 // for MT6270A E2, MT6276E2
+ #endif
+#elif IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+ #if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
+/*MT6256*/ #define BSI_EVENT_COUNT 36
+/*MT6256*/ #define BSI_DATA_COUNT 64
+ #else
+/*MT6256*/ #define BSI_EVENT_COUNT 21
+/*MT6256*/ #define BSI_DATA_COUNT 40
+ #endif
+#elif IS_CHIP_MT6252
+/*MT6252*/ #define BSI_EVENT_COUNT 21
+/*MT6252*/ #define BSI_DATA_COUNT 32
+#elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+/*MT6229*/ #define BSI_EVENT_COUNT 20
+/*MT6229*/ #define BSI_DATA_COUNT 44
+#endif
+
+#if IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+/*MT6755*/ #define BSI_DATA_COUNT_SW_LIMIT BSI_RFIC_DATA_COUNT
+#elif IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6268 || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_CHIP_MT6252
+/*MT6252*/ #define BSI_DATA_COUNT_SW_LIMIT BSI_DATA_COUNT
+#elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+/*MT6229*/ #define BSI_DATA_COUNT_SW_LIMIT 40 // the maximum control words length of BSI data 40~43 is 78 bits, which is not support by L1D
+#else
+/*OTHERS*/ #define BSI_DATA_COUNT_SW_LIMIT BSI_DATA_COUNT
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#if IS_GPRS || IS_MULTISLOT_TX_SUPPORT
+ #if IS_5_BANK_RAMP_PROFILES_SUPPORT
+#define S2_S3_APC_IDX 3
+#define S3_S4_APC_IDX 4
+ #elif IS_6_BANK_RAMP_PROFILES_SUPPORT
+#define S2_S3_APC_IDX 3
+#define S3_S4_APC_IDX 5
+ #elif IS_7_BANK_RAMP_PROFILES_SUPPORT
+#define S2_S3_APC_IDX 5
+#define S3_S4_APC_IDX 6
+ #endif
+#endif
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define MM_S2_S3_APC_IDX 5
+#define MM_S3_S4_APC_IDX 6
+#define MM_S2_S3_TXDFE_IDX 4
+#define MM_S3_S4_TXDFE_IDX 5
+#endif
+/* ------------------------------------------------------------------------- */
+
+#if !IS_RTX_5CWIN_SUPPORT // IS_GSM
+ #if IS_BPI_V2_SUPPORT
+/*GSM*/ #define BPIRES1 20
+/*GSM*/ #define BPIRES2 20
+/*GSM*/ #define PT2M_EV(m,n) (21+3*(m)+(n))
+/*GSM*/ #define PR3A_EV(n) BPIDX(n,3)
+/*GSM*/ #define PR2E_EV(n) (BPI_GROUP_COUNT * CWIN_COUNT + \
+ NUM_RESERVED_BPI_EVENTS + \
+ NUM_INTERSLOT_GROUP * NUM_PT2M_EVENTS_PER_GROUP + \
+ NUM_PT3A_EVENTS + \
+ (n))
+ #if IS_BPI_V2_PT3A_SUPPORT
+/*GSM*/ /* PT1/2/2B/3: 0~3, 4~7, 8~11, 12~15, 16~19 */
+/*GSM*/ /* FSI_STOP: 20 */
+/*GSM*/ /* PT2M1/2/3: 21~23, 24~26, 27~29 */
+/*GSM*/ #define PT3A_CWIN1 30
+/*GSM*/ #define PT3A_CWIN2 31
+ #endif
+ #elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+/*GSM*/ #define BPIRES1 40
+/*GSM*/ #define BPIRES2 41
+/*GSM*/ #define PT2M_EV(m,n) (26+3*(m)+(n))
+/*GSM*/ #define PR3A_EV(n) (35+(n))
+ #else
+/*GSM*/ #define BPIRES 12
+ #endif
+/*GSM*/
+/*GSM*/ #define FS_CWIN_IDX 2
+/*GSM*/ #define FS_RXWIN_IDX 2
+/*GSM*/ #define FS_AFC_IDX 3
+/*GSM*/ #define FS_AFC_EN AFCEN3
+/*GSM*/
+/*GSM*/ #define PM7_RXWIN_IDX 3
+/*GSM*/
+/*GSM*/ #define AGCEV0 (CWIN_BSI_EVENT_COUNT*CWIN_COUNT)
+#endif
+
+#if IS_RTX_5CWIN_SUPPORT // IS_GPRS
+ #if IS_BPI_V2_SUPPORT
+/*GPRS*/ #define BPIRES1 20
+/*GPRS*/ #define BPIRES2 20
+/*GPRS*/ #define PT2M_EV(m,n) (21+3*(m)+(n))
+/*GPRS*/ #define PR3A_EV(n) BPIDX(n,3)
+/*GPRS*/ #define PR2E_EV(n) (BPI_GROUP_COUNT * CWIN_COUNT + \
+ NUM_RESERVED_BPI_EVENTS + \
+ NUM_INTERSLOT_GROUP * NUM_PT2M_EVENTS_PER_GROUP + \
+ NUM_PT3A_EVENTS + \
+ (n))
+ #if IS_BPI_V2_PT3A_SUPPORT
+/*GPRS*/ /* PT1/2/2B/3: 0~3, 4~7, 8~11, 12~15, 16~19 */
+/*GPRS*/ /* FSI_STOP: 20 */
+/*GPRS*/ /* PT2M1/2/3: 21~23, 24~26, 27~29 */
+/*GPRS*/ #define PT3A_CWIN1 30
+/*GPRS*/ #define PT3A_CWIN2 31
+ #endif
+ #elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+/*GPRS*/ #define BPIRES1 40
+/*GPRS*/ #define BPIRES2 41
+/*GPRS*/ #define PT2M_EV(m,n) (26+3*(m)+(n))
+/*GPRS*/ #define PR3A_EV(n) (35+(n))
+ #else
+/*GPRS*/ #define BPIRES 15
+ #endif
+/*GPRS*/
+/*GPRS*/ #define FS_CWIN_IDX 3
+/*GPRS*/ #define FS_RXWIN_IDX 4
+/*GPRS*/ #define FS_AFC_IDX 3
+/*GPRS*/ #define FS_AFC_EN AFCEN3
+/*GPRS*/
+/*GPRS*/ #define PM7_RXWIN_IDX 5
+/*GPRS*/
+/*GPRS*/ #define AGCEV0 (CWIN_BSI_EVENT_COUNT*CWIN_COUNT)
+#endif
+
+/* ------------------------------------------------------------------------- */
+
+#define AGCIDX(n) (AGCEV0+(n))
+#if IS_BSI_SX0_SUPPORT
+#define BSI_GROUP_COUNT 3
+#define BSIDX(m,n) ((m)*BSI_GROUP_COUNT+(n)+1)
+#define SR0OFF 0
+#define SR1OFF (SR0OFF+1)
+#define ST0OFF 0
+#define ST1OFF (ST0OFF+1)
+#define SR0TQIDX 0
+#define ST0TQIDX (SR0TQIDX+1)
+#else
+#define BSI_GROUP_COUNT 2
+#define BSIDX(m,n) ((m)*BSI_GROUP_COUNT+(n))
+#define SR1OFF 0
+#define ST1OFF 0
+#endif
+#define TXAFCREADY_TQIDX 0
+#define ST1TQIDX (TXAFCREADY_TQIDX+1)
+#define PT1TQIDX (ST1TQIDX+1)
+#define PT2TQIDX (PT1TQIDX+1)
+#define APCON1TQIDX (PT2TQIDX+1)
+#define APCON2TQIDX (APCON1TQIDX+1)
+#define BULONTQIDX (APCON2TQIDX+1)
+#define SR1TQIDX 0
+#define PR1TQIDX (SR1TQIDX+1)
+#define SR3TQIDX 0
+#define PR3TQIDX (SR3TQIDX+1)
+#define ST3OFF (ST1OFF+1)
+#define SR3OFF (SR1OFF+1)
+#define PT1OFF 0
+#define PT2OFF (PT1OFF+1)
+#define BSIEN(m,n) (1<<BSIDX(m,n))
+#define BSIEN_X(n) (1<<AGCIDX(n))
+#define BSIENALL(m) ((1<<(BSI_GROUP_COUNT*(m)))-1)
+
+#define PR1OFF 0
+#define PT2M1OFF 0
+#define PT2M2OFF (PT2M1OFF+1)
+#define PT2M3OFF (PT2M2OFF+1)
+
+#define REG_FSIWINSB_BDLOFFIDX 0
+#define REG_FSIWINSB_BDLONIDX (REG_FSIWINSB_BDLOFFIDX+1)
+#define REG_FSIWINIM_BDLOFFIDX REG_FSIWINSB_BDLOFFIDX
+
+#define FSISR3TQIDX 0
+#define FSIPR3TQIDX (FSISR3TQIDX+1)
+#define FSIPR3ATQIDX (FSIPR3TQIDX+1)
+#define FSIBDLONTQIDX (FSIPR3ATQIDX+1)
+#define FSIBDLOFFTQIDX (FSIBDLONTQIDX+1)
+
+#define REG_FSI_BDLONIDX 3
+#define REG_FSI_BDLOFFIDX (REG_FSI_BDLONIDX+1)
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+#define BPI_GROUP_COUNT 4
+#define PR2OFF (PR1OFF+1)
+#define PR2BOFF (PR2OFF+1)
+#define PT2BOFF (PT2OFF+1)
+#define PT3OFF (PT2BOFF+1)
+#define PR2TQIDX (PR1TQIDX+1)
+#define PR2BTQIDX (PR2TQIDX+1)
+#define PR3ATQIDX (PR3TQIDX+1)
+#define BDLOFFTQIDX (PR3ATQIDX+1)
+#define PT2BTQIDX 0
+#define ST2BTQIDX 0
+#define ST2M_TQIDX 0
+#define PT2M1_TQIDX (ST2M_TQIDX+1)
+#define PT2M2_TQIDX (PT2M1_TQIDX+1)
+#define PT2M3_TQIDX (PT2M2_TQIDX+1)
+#else
+#define BPI_GROUP_COUNT 3
+#define PR2BOFF (PR1OFF+1)
+#define PT3OFF (PT2OFF+1)
+#define PR2BTQIDX (PR1TQIDX+1)
+#define BDLOFFTQIDX (PR3TQIDX+1)
+#endif
+#define ENDBDLONTQIDX (BDLOFFTQIDX+1)
+#define REG_BULOFFMID_IDX 0
+#define REG_BULONMID_IDX (REG_BULOFFMID_IDX+1)
+#define REG_APCMID1_IDX (REG_BULONMID_IDX+1)
+#define REG_APCMID2_IDX (REG_APCMID1_IDX+1)
+#define BULOFFMID_TQIDX 0
+#define BULONMID_TQIDX (BULOFFMID_TQIDX+1)
+#define APCMID1_TQIDX (BULONMID_TQIDX+1)
+#define APCMID2_TQIDX (APCMID1_TQIDX+1)
+
+#define REG_BULOFF_IDX 0
+#define REG_APC1_IDX (REG_BULOFF_IDX+1)
+#define REG_APC2_IDX (REG_APC1_IDX+1)
+
+#define AFC22BOFF_TQIDX 0
+#define ST3_TQIDX (AFC22BOFF_TQIDX+1)
+#define PT3_TQIDX (ST3_TQIDX+1)
+#define BULOFF_TQIDX (PT3_TQIDX+1)
+#define APC1_TQIDX (BULOFF_TQIDX+1)
+#define APC2_TQIDX (APC1_TQIDX+1)
+#define SR2TQIDX (PR2BTQIDX+1)
+#define BDLONTQIDX (SR2TQIDX+1)
+#define TQMAXTQIDX (BDLONTQIDX+1)
+#if IS_AFC_EVENT_SUPPORT_CHIP
+#define AFCTQIDX (TQMAXTQIDX+1)
+#define REG_AFC2_2_BOFFIDX 0
+#endif
+#define PR3OFF (PR2BOFF+1)
+#define PR3AOFF PR3OFF
+#define RIDX_REG_AGC_IDX 0
+#define RIDX_REG_BDLON_IDX (RIDX_REG_AGC_IDX+1)
+#define RIDX_REG_BDLOFF_IDX (RIDX_REG_BDLON_IDX+1)
+#define RIDX_REG_APC1_IDX 0
+#define RIDX_REG_APC2_IDX (RIDX_REG_APC1_IDX+1)
+#define RIDX_REG_BULON_IDX (RIDX_REG_APC2_IDX+1)
+#define BPIDX(m,n) ((m)*BPI_GROUP_COUNT+(n))
+#define BPIEN(m,n) (1<<BPIDX(m,n))
+#define BPIENALL(m) ((1<<(BPI_GROUP_COUNT*(m)))-1)
+
+#if IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define NUM_RESERVED_BPI_EVENTS 1
+#define NUM_INTERSLOT_GROUP 3
+#define NUM_PT2M_EVENTS_PER_GROUP 3
+#define NUM_PT3A_EVENTS 2
+#define NUM_PR2E_EVENTS 6
+#define MAX_BSI_EVENTS (CWIN_BSI_EVENT_COUNT * CWIN_COUNT + RIDX_COUNT)
+#define MAX_BPI_EVENTS (BPI_GROUP_COUNT * CWIN_COUNT + \
+ NUM_RESERVED_BPI_EVENTS + \
+ NUM_INTERSLOT_GROUP * NUM_PT2M_EVENTS_PER_GROUP + \
+ NUM_PT3A_EVENTS+ \
+ NUM_PR2E_EVENTS)
+#endif /* IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 */
+#define SR1PMTQIDX 0
+#define PR1PMTQIDX (SR1PMTQIDX+1)
+#define PR2PMTQIDX (PR1PMTQIDX+1)
+#define PR2BPMTQIDX (PR2PMTQIDX+1)
+#define SR3PMTQIDX (PR2BPMTQIDX+1)
+#define PR3PMTQIDX (SR3PMTQIDX+1)
+#define PR3APMTQIDX (PR3PMTQIDX+1)
+#define SR2PMTQIDX (PR3APMTQIDX+1)
+#define BDLONPMTQIDX (SR2PMTQIDX+1)
+#define BDLOFFPMTQIDX (BDLONPMTQIDX+1)
+
+#define REG_PMBDLON_IDX 1
+#define REG_PMBDLOFF_IDX (REG_PMBDLON_IDX+1)
+
+#if IS_GL1D_CDF_SUPPORT
+#define CDF_FE_RESERVED_FSI_OFF (CDF_FE_GROUP_COUNT * CWIN_COUNT)
+#define CDF_FE_RX_ON 0
+#define CDF_FE_RX_OFF (CDF_FE_RX_ON+1)
+#define CDF_FE_TX_ON 0
+#define CDF_FE_TX_OFF (CDF_FE_TX_ON+1)
+#define CDF_FE_GROUP_COUNT 2
+#define CDF_FE_CWIN_GROUP_START(n) (n*CDF_FE_GROUP_COUNT)
+
+#define NUM_RESERVED_CDF_FE_FSI_OFF_EVENTS 1
+#define NUM_CDF_FE_XWIM_EVENTS 6
+
+
+#define CDF_FE_XWIM_EV(n) (CDF_FE_GROUP_COUNT * CWIN_COUNT + \
+ NUM_RESERVED_CDF_FE_FSI_OFF_EVENTS + \
+ (n))
+
+#define MAX_CDF_FE_EVENTS (CDF_FE_GROUP_COUNT * CWIN_COUNT + \
+ NUM_RESERVED_CDF_FE_FSI_OFF_EVENTS + \
+ NUM_CDF_FE_XWIM_EVENTS)
+#endif
+
+#ifdef IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT
+#define BSI_CWIN_GROUP_START(n) (n*BSI_GROUP_COUNT)
+#define BPI_CWIN_GROUP_START(n) (n*BPI_GROUP_COUNT)
+
+#define bsiXwinPos(n) AGCIDX(n)
+#define bpiISPos(m,n) PT2M_EV((m-1),n)
+
+
+#endif /* IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT */
+#define BDLOFFMIDTQIDX 0
+#define BDLONMIDTQIDX (BDLOFFMIDTQIDX+1)
+#define SR2MTQIDX (BDLONMIDTQIDX+1)
+#define BDLOFFMID_IDX 0
+#define BDLONMID_IDX (BDLOFFMID_IDX+1)
+/* ------------------------------------------------------------------------- */
+
+#if IS_FPGA_TARGET || IS_CHIP_MT6208
+/*FPGA,MT6208*/ #define PCTRL_INITIAL 0x0001 /* the initial bus status */
+/*FPGA,MT6208*/ #define PCTRL_MAIN 0x0000 /* BPI main control value : ctrl. by TSU */
+/*FPGA,MT6208*/ /* ------------------------------------------------------------------------------------------ */
+#endif
+
+#if IS_CHIP_MT6205_AND_LATTER_VERSION || IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+ #if IS_CHIP_MT6572
+/*MT6572 */ #define DRV_0_6_4mA 0x0 /* Driving level 0 for bus0~ 6 = 4 mA (min) */
+/*MT6572 */ #define DRV_0_6_8mA 0x1 /* Driving level 1 for bus0~ 6 = 8 mA (default) */
+/*MT6572 */ #define DRV_0_6_12mA 0x2 /* Driving level 2 for bus0~ 6 = 12 mA */
+/*MT6572 */ #define DRV_0_6_16mA 0x3 /* Driving level 3 for bus0~ 6 = 16 mA (max) */
+/*MT6572 */ #define DRV_7_15_2mA 0x0 /* Driving level 0 for bus7~15 = 2 mA (min) */
+/*MT6572 */ #define DRV_7_15_4mA 0x1 /* Driving level 1 for bus7~15 = 4 mA (default) */
+/*MT6572 */ #define DRV_7_15_6mA 0x2 /* Driving level 2 for bus7~15 = 6 mA */
+/*MT6572 */ #define DRV_7_15_8mA 0x3 /* Driving level 3 for bus7~15 = 8 mA (max) */
+/*MT6572 */ #define CFG_DRV_MASK 0x000003FC /* Driving capability setting mask (bit[ 9: 2]) */
+/*MT6572 */ #define CFG_DRV_CON (DRV_7_15_4mA<<8)|(DRV_7_15_4mA<<6)|(DRV_0_6_8mA<<4)|(DRV_0_6_8mA<<2)
+ #elif IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2
+/*MT6583~*/ #define DRV_4mA 0x0 /* Driving level 0 = 4 mA (min) */
+/*MT6583~*/ #define DRV_8mA 0x1 /* Driving level 1 = 8 mA */
+/*MT6583~*/ #define DRV_12mA 0x2 /* Driving level 2 = 12 mA (default) */
+/*MT6583~*/ #define DRV_16mA 0x3 /* Driving level 3 = 16 mA (max) */
+/*MT6583~*/ #define CFG_DRV_MASK 0x00006000 /* Driving capability setting mask (bit[14:13]) */
+/*MT6583~*/ #define CFG_DRV_CON (DRV_12mA<<13)
+ #elif IS_CHIP_MT6280
+/*MT6280~*/ #define DRV_4mA 0x0 /* Driving level 0 = 4 mA (min) */
+/*MT6280~*/ #define DRV_8mA 0x1 /* Driving level 1 = 8 mA */
+/*MT6280~*/ #define DRV_12mA 0x2 /* Driving level 2 = 12 mA (default) */
+/*MT6280~*/ #define DRV_16mA 0x3 /* Driving level 3 = 16 mA (max) */
+/*MT6280~*/ #define CFG_DRV13 (DRV_8mA << 8) /* Driving capability setting of BPI0~3 */
+/*MT6280~*/ #define CFG_DRV14 (DRV_8mA <<10) /* Driving capability setting of BPI4 */
+/*MT6280~*/ #define CFG_DRV15 (DRV_12mA<<12) /* Driving capability setting of BPI5 */
+/*MT6280~*/ #define CFG_DRV16 (DRV_12mA<<14) /* Driving capability setting of BPI6 */
+/*MT6280~*/ #define CFG_DRV17 (DRV_12mA<< 0) /* Driving capability setting of BPI7 */
+/*MT6280~*/ #define CFG_DRV18 (DRV_12mA<< 2) /* Driving capability setting of BPI8 */
+/*MT6280~*/ #define CFG_DRV19 (DRV_12mA<< 4) /* Driving capability setting of BPI9 */
+/*MT6280~*/ #define CFG_DRV20 (DRV_12mA<< 6) /* Driving capability setting of BPI10 */
+/*MT6280~*/ #define CFG_DRV21 (DRV_12mA<< 8) /* Driving capability setting of BPI11 */
+/*MT6280~*/ #define CFG_DRV22 (DRV_12mA<<10) /* Driving capability setting of BPI12 */
+/*MT6280~*/ #define CFG_DRV23 (DRV_12mA<<12) /* Driving capability setting of BPI13 */
+/*MT6280~*/ #define CFG_DRV_MASK 0xFF00 /* Driving capability setting mask (bit[15:8]) */
+/*MT6280~*/ #define CFG_DRV_MASK1 0x3FFF /* Driving capability setting mask (bit[13:0]) */
+/*MT6280~*/ #define CFG_DRV_CON (CFG_DRV16|CFG_DRV15|CFG_DRV14|CFG_DRV13)
+/*MT6280~*/ #define CFG_DRV_CON1 (CFG_DRV23|CFG_DRV22|CFG_DRV21|CFG_DRV20|CFG_DRV19|CFG_DRV18|CFG_DRV17)
+/*MT6280~*/ /* ---------------------------------------------------------------------------------------------- */
+ #elif IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6268H || IS_AST_B2S_SUPPORT
+/*MT6270~*/ #define PCTRL_INITIAL 0x03FE /* The output driving capability of BPI0~4 is 8mA */
+/*MT6270~*/ #define PCTRL_MAIN 0x03FE /* The output driving capability of BPI0~4 is 8mA */
+/*MT6270~*/ /* ---------------------------------------------------------------------------------------------- */
+ #elif IS_CHIP_MT6268
+/*MT6268~*/ #define PCTRL_INITIAL 0x003F /* The output driving capability of BPI0~4 is 8mA */
+/*MT6268~*/ #define PCTRL_MAIN 0x003E /* The output driving capability of BPI0~4 is 8mA */
+/*MT6268~*/ /* ---------------------------------------------------------------------------------------------- */
+ #else
+/*MT6229~*/ #define PCTRL_INITIAL 0x000F /* The output driving capability of BPI0~2 is 8mA */
+/*MT6229~*/ #define PCTRL_MAIN 0x000E /* The output driving capability of BPI0~2 is 8mA */
+/*MT6229~*/ /* ---------------------------------------------------------------------------------------------- */
+ #endif
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define L1D_SET_BPI_IMM_MODE_BEGIN()
+#define L1D_SET_BPI_IMM_MODE_END()
+#elif IS_CHIP_MT6572
+#define L1D_SET_BPI_IMM_MODE_BEGIN() { unsigned long d32=HW_READ(GPIO_DRV_CFG0); d32&=~(CFG_DRV_MASK); d32|=CFG_DRV_CON ; HW_WRITE(GPIO_DRV_CFG0, d32); }
+#define L1D_SET_BPI_IMM_MODE_END() { unsigned long d32=HW_READ(GPIO_DRV_CFG0); d32&=~(CFG_DRV_MASK); d32|=CFG_DRV_CON ; HW_WRITE(GPIO_DRV_CFG0, d32); }
+#elif IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2
+#define L1D_SET_BPI_IMM_MODE_BEGIN() { unsigned long d32=HW_READ(GPIO_DRV_CON5); d32&=~(CFG_DRV_MASK); d32|=CFG_DRV_CON ; HW_WRITE(GPIO_DRV_CON5, d32); }
+#define L1D_SET_BPI_IMM_MODE_END() { unsigned long d32=HW_READ(GPIO_DRV_CON5); d32&=~(CFG_DRV_MASK); d32|=CFG_DRV_CON ; HW_WRITE(GPIO_DRV_CON5, d32); }
+#elif IS_CHIP_MT6280
+#define L1D_SET_BPI_IMM_MODE_BEGIN() { unsigned short d16=HW_READ(GPIO_DRV2); d16&=~(CFG_DRV_MASK ); d16|=CFG_DRV_CON ; HW_WRITE(GPIO_DRV2, d16); \
+ d16=HW_READ(GPIO_DRV3); d16&=~(CFG_DRV_MASK1); d16|=CFG_DRV_CON1; HW_WRITE(GPIO_DRV3, d16); }
+#define L1D_SET_BPI_IMM_MODE_END() { unsigned short d16=HW_READ(GPIO_DRV2); d16&=~(CFG_DRV_MASK ); d16|=CFG_DRV_CON ; HW_WRITE(GPIO_DRV2, d16); \
+ d16=HW_READ(GPIO_DRV3); d16&=~(CFG_DRV_MASK1); d16|=CFG_DRV_CON1; HW_WRITE(GPIO_DRV3, d16); }
+#else
+#define L1D_SET_BPI_IMM_MODE_BEGIN() HW_WRITE( BPI_CON, PCTRL_INITIAL )
+#define L1D_SET_BPI_IMM_MODE_END() HW_WRITE( BPI_CON, PCTRL_MAIN )
+#endif
+/* ------------------------------------------------------------------------- */
+
+#if IS_FPGA_TARGET || IS_CHIP_MT6208
+/*FPGA,MT6208*/ #define AFC_EVENT_TRIGGER 0x0000 /* AFC 10 bit *//* AFC power up by DAC_AFC_ENABLEn events */
+/*FPGA,MT6208*/ #define AFC_FORCE_POWER_ON 0x0001 /* AFC 10 bit *//* AFC always power on */
+#endif
+
+#if IS_CHIP_MT6205_AND_LATTER_VERSION || IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+ #if IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT
+ #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6268H || IS_AST_B2S_SUPPORT || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+/*MT6205~*/ #define AFC_EVENT_TRIGGER 0x0000 /* AFC power up by DAC_AFC_ENABLEn events */
+/*MT6205~*/ #define AFC_FORCE_POWER_ON 0x0001 /* AFC immediate mode */
+ #elif IS_CHIP_MT6268A || IS_CHIP_MT6268_S00 || IS_CHIP_MT6268T
+/* chuwei: 0x0020 fixed MT6268A AFC Hold mode issue(Always on) */
+/*MT6205~*/ #define AFC_EVENT_TRIGGER 0x0024 /* AFC power up by DAC_AFC_ENABLEn events */
+/*MT6205~*/ #define AFC_FORCE_POWER_ON 0x0025 /* AFC immediate mode + always power on */
+ #else
+//* chuwei: 0x0020 fixed MT6268A AFC Hold mode issue(Always on), 0x0040 Auto_SRCLKEN_OFF*/
+/*MT6205~*/ #define AFC_EVENT_TRIGGER 0x0064 /* AFC power up by DAC_AFC_ENABLEn events */
+/*MT6205~*/ #define AFC_FORCE_POWER_ON 0x0065 /* AFC immediate mode + always power on */
+ #endif
+ #else
+/*MT6205~*/ #define AFC_EVENT_TRIGGER 0x0000 /* AFC power up by DAC_AFC_ENABLEn events */
+/*MT6205~*/ #define AFC_FORCE_POWER_ON 0x0005 /* AFC immediate mooe + always power on */
+ #endif
+#endif
+/* ------------------------------------------------------------------------- */
+
+#if IS_APC_HALF_QB_RESOLUTION_SUPPORT
+/*MT6583~*/ #define APC_CON_DAC_RATE_SEL 0x1 /* 1: The data rate of APC D/A converter is 2.1666MHz */
+ /* 0: The data rate of APC D/A converter is 1.0833MHz */
+#else
+/*others~*/ #define APC_CON_DAC_RATE_SEL 0x0
+#endif
+/* ------------------------------------------------------------------------- */
+
+#define PWRRES_BIT RSSI_RESOLUTION_BITS
+#define PWRRES RSSI_FACTOR
+
+/* ========================================================================= */
+
+extern const int dsp_power_constance;
+
+extern const short TQ_Afc_ChargeInIdle_VCXO;
+extern const short TQ_Afc_ChargeInIdle_VCTCXO;
+extern CONST short TQ_FBWin_Start_Offset;
+extern CONST short TQ_FSWin_DTIRQ_Delay;
+extern CONST short TxPropagationDelay;
+extern const short FrequencyBias;
+extern short AFC_Dac_TRx_Offset[5];
+#if IS_VCXO_LC_TRXOFFSET_COMPENSATE_SUPPORT
+extern short AFC_TRx_Offset[5];
+extern short AFC_Default_TRx_Offset[5];
+#else
+ #if IS_RF_MT6162 || IS_RF_MT6163
+extern short AFC_TRx_Offset[5];
+extern short AFC_Default_TRx_Offset[5];
+ #endif
+#endif
+#if IS_BBTXRX_CHIP_DESIGN_VER_2 || IS_BBTXRX_CHIP_DESIGN_VER_3
+extern const unsigned char bbrx_iq_swap;
+extern const unsigned char bbtx_iq_swap;
+extern const unsigned char bbtx_common_mode_voltage;
+extern const unsigned char bbtx_offset_i;
+extern const unsigned char bbtx_offset_q;
+extern const unsigned char bbtx_phseli;
+extern const unsigned char bbtx_phselq;
+extern const unsigned char bbtx_rpsel;
+extern const unsigned char bbtx_inten;
+extern const unsigned char bbtx_sw_qbcnt;
+extern const unsigned char bbtx_gain_comp;
+extern const unsigned char bbtx_iqgain_sel;
+extern const unsigned char bbtx_epsk_dtap_sym;
+#else
+extern const unsigned char bbrx_iq_swap;
+extern const unsigned char bbrx_gain_double;
+extern const unsigned char bbtx_iq_swap;
+extern const unsigned char bbtx_calrcsel;
+extern const unsigned char bbtx_calbias;
+extern const unsigned char bbtx_common_mode_voltage;
+extern const unsigned char bbtx_gain;
+extern const unsigned char bbtx_trim_i;
+extern const unsigned char bbtx_trim_q;
+ #if IS_CHIP_MT6225_AND_LATTER_VERSION || IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION
+extern const unsigned char bbtx_dccoarse_i;
+extern const unsigned char bbtx_dccoarse_q;
+ #endif
+extern const unsigned char bbtx_offset_i;
+extern const unsigned char bbtx_offset_q;
+extern const unsigned char bbtx_phsel;
+
+ #if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+extern const unsigned char bbtx_calrcsel_h;
+extern const unsigned char bbtx_common_mode_voltage_h;
+extern const unsigned char bbtx_gain_h;
+extern const unsigned char bbtx_trim_i_h;
+extern const unsigned char bbtx_trim_q_h;
+ #if IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION
+extern const unsigned char bbtx_dccoarse_i_h;
+extern const unsigned char bbtx_dccoarse_q_h;
+ #endif
+extern const unsigned char bbtx_offset_i_h;
+extern const unsigned char bbtx_offset_q_h;
+extern const unsigned char bbtx_phsel_h;
+ #if !IS_CHIP_MT6223 && !IS_CHIP_MT6253 /*MT6223 and MT6253 don't support 8PSK*/
+extern const unsigned char bbtx_rpsel;
+extern const unsigned char bbtx_inten;
+extern const unsigned char bbtx_sw_qbcnt;
+ #endif
+ #endif
+#endif
+
+#if IS_CHIP_MT6227
+extern const unsigned char bbtx_iqswap_onfly;
+#endif
+extern const unsigned short bdlcon_data;
+extern const unsigned short bulcon1_data;
+extern CONST unsigned short bulcon2_data;
+#if IS_TDMA_AD_DA_WINDOW_SUPPORT
+extern const unsigned short bdlcon2_data;
+extern const unsigned short bulcon3_data;
+#endif
+
+extern CONST int apc_bat_voltage_period;
+extern CONST int apc_bat_voltage_count;
+extern CONST int apc_bat_temperature_period;
+extern CONST int apc_bat_temperature_count;
+extern CONST int apc_rf_temperature_period;
+extern CONST int apc_rf_temperature_count;
+
+/*---------------------------------------------------------------------------*/
+
+extern const APBADDR_P PDATA_REG_TABLE[/*4:5*/];
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+extern const APBADDR_P PDATA_REG_TABLE2[/*4:5*/];
+#endif
+#if IS_BPI_V2_PT3A_SUPPORT
+extern const APBADDR_P PDATA_REG_TABLE3[2];
+#endif
+
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+extern CONST signed short RX_END_TQ_TABLE[5];
+#else
+extern CONST signed short RX_END_TQ_TABLE[4];
+#endif
+extern CONST signed short TX_START_TQ_TABLE[8];
+extern CONST signed short TX_END_TQ_TABLE[6];
+#if IS_BPI_V2_PT3A_SUPPORT
+extern CONST signed short TX_END_TQ_TABLE2[1];
+#endif
+extern CONST signed short PM_START_TQ_TABLE[7];
+extern const signed short FWIN_POS_TABLE[8];
+extern CONST sint_P FSWIN_STOP_DATA_BPI_TABLE[2];
+extern const APBADDR_P FSWIN_STOP_REG_BPI_TABLE[2];
+#if IS_RF_MT6179 || IS_RF_MT6176 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+extern const sint_S FSWIN_STOP_DATA_BSI_TABLE[4];
+#else
+extern const sint_S FSWIN_STOP_DATA_BSI_TABLE[2];
+#endif
+extern const APBADDR_S FSWIN_STOP_REG_BSI_TABLE[2];
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+extern CONST signed short FSWIN_STOP_DATA_TABLE[5];
+extern const APBADDR FSWIN_STOP_REG_TABLE[2][5];
+#else
+extern CONST signed short FSWIN_STOP_DATA_TABLE[7];
+extern const APBADDR FSWIN_STOP_REG_TABLE[2][6];
+#endif
+#if IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT
+#else
+#if IS_RF_MT6162 || IS_RF_MT6163
+extern const unsigned long FSWIN_STOP_BSI_DATA_TABLE[2];
+extern const APBADDR FSWIN_STOP_BSI_REG_TABLE[4];
+#else
+extern const unsigned long FSWIN_STOP_BSI_DATA_TABLE[1];
+extern const APBADDR FSWIN_STOP_BSI_REG_TABLE[2];
+ #endif
+#endif
+extern const short FIR_COEF[/*20:17*/];
+extern CONST signed short RX_MIDDLE_TQ_TABLE[3];
+extern CONST signed short TX_MIDDLE_TQ_TABLE[4];
+extern const unsigned char LOWEST_TX_POWER[5];
+extern const signed long bb_tx_opt_swing_dac_sqr;
+extern const unsigned char CONTISLOTMASK[5];
+extern const unsigned char FIRSTSLOTMASK[5];
+
+/*---------------------------------------------------------------------------*/
+#if IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT
+#define NOTCH_CPL 2; // 2nd path notch filter couple loss 2dB
+#endif
+/*---------------------------------------------------------------------------*/
+
+#if IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT
+#define PDATA_TABLE PDATA_TABLE_P
+#else
+#define PDATA_TABLE PDATA_TABLE
+#endif
+
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+ #if IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT
+/*MT6229~*/extern CONST sint_P (*PDATA_TABLE_P)[2][5];
+/*MT6229~*/extern CONST sint_P PDATA_TABLE_DCS_TX_NOTCH[5][2][5];
+/*MT6229~*/extern CONST sint_P PDATA_TABLE_DEFAULT[5][2][5];
+ #else
+/*MT6229~*/extern CONST sint_P PDATA_TABLE[5][2][5];
+ #if IS_2G_RXD_SUPPORT
+/*MT6229~*/extern CONST sint_P PDATA_DIVERSITY_TABLE[5][2][5];
+ #endif
+ #endif
+/*MT6229~*/extern CONST sint_P PDATA_TABLE3[5][3][3];//for PR2M1, PR2M2, PT2M1, PT2M3
+ #if IS_2G_RXD_SUPPORT
+/*MT6229~*/extern CONST sint_P PDATA_DIVERSITY_TABLE3[5][3][3];//for PR2M1, PR2M2, PT2M1, PT2M3
+ #endif
+/*MT6229~*/extern const APBADDR_P PDATA_PT2M_REG_TABLE[4];
+/*MT6229~*/extern const APBADDR_P PDATA_PR2M_REG_TABLE[4];
+/*MT6229~*/
+/*MT6229~*/extern CONST signed short RTX_START_TQ_TABLE[2];
+ #ifdef L1D_TEST
+/*MT6229~*/extern signed short RX_START_TQ_TABLE[8];
+ #else
+/*MT6229~*/extern CONST signed short RX_START_TQ_TABLE[8];
+ #endif
+/*MT6229~*/
+/*MT6229~*/extern CONST signed short PM_TQ_TABLE[10];
+/*MT6229~*/
+ #if L1D_PM_ENHANCE
+/*MT6229~*/extern CONST signed short PM_IN_IDLE_TQ_TABLE[10];
+ #if L1D_PM_1R7PM
+/*MT6229~*/extern CONST signed short PM_1R7PM_TQ_TABLE[10];
+ #endif
+ #endif
+/*MT6229~*/
+/*MT6229~*/extern const short NB_FIR_COEF[];
+/*MT6229~*/extern const short NARROW_FB_FIR_COEF[];
+/*MT6229~*/extern const short WIDE_FB_FIR_COEF[];
+/*MT6229~*/extern const short NB_FIR_COEF_WIDER[];
+/*MT6229~*/
+ #ifdef L1D_TEST
+/*MT6229~*/extern const short VCXO_NARROW_FB_FIR_COEF[];
+/*MT6229~*/extern const short VCXO_WIDE_FB_FIR_COEF[];
+/*MT6229~*/extern const short TCVCXO_NARROW_FB_FIR_COEF[];
+/*MT6229~*/extern const short TCVCXO_WIDE_FB_FIR_COEF[];
+ #endif
+/*MT6229~*/
+/*MT6229~*/extern CONST signed short RX_MIDDLE_TQ_TABLE2[2];
+/*MT6229~*/extern CONST signed short TX_START_TQ_TABLE2[1];
+/*MT6229~*/extern CONST signed short TX_START_TQ_TABLE3[1];//for TQ_ST2B
+/*MT6229~*/
+/*MT6229~*/extern CONST signed short TX_MIDDLE_TQ_TABLE2[2][4];
+/*MT6229~*/
+#else /*!IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION*/
+/*MT6218~*/extern const signed short PDATA_TABLE[/*5*/][2][3];
+/*MT6218~*/
+ #if IS_CHIP_MT6225_AND_LATTER_VERSION
+ #ifdef L1D_TEST
+/*MT6218~*/extern signed short RX_START_TQ_TABLE[7];
+ #else
+/*MT6218~*/extern const signed short RX_START_TQ_TABLE[7];
+ #endif
+ #else
+/*MT6218~*/extern const signed short RX_START_TQ_TABLE[7];
+ #endif /*End of "IS_CHIP_MT6225_AND_LATTER_VERSION"*/
+/*MT6218~*/
+/*MT6218~*/extern const signed short PM_TQ_TABLE[8];
+/*MT6218~*/
+ #if L1D_PM_ENHANCE
+/*MT6218~*/extern const signed short PM_IN_IDLE_TQ_TABLE[8];
+ #if L1D_PM_1R7PM
+/*MT6218~*/extern const signed short PM_1R7PM_TQ_TABLE[8];
+ #endif
+ #endif
+/*MT6218~*/
+ #if IS_CHIP_MT6218_AND_LATTER_VERSION
+/*MT6218~*//*MT6218~*/ extern const signed short PDATA_TABLE2[5][2][2];
+/*MT6218~*//*MT6218~*/ extern const APBADDR PDATA_PT2B_REG_TABLE[2][3];
+/*MT6218~*//*MT6218~*/ extern const APBADDR PDATA_PR2M_REG_TABLE[4];
+/*MT6218~*//*MT6218~*/ extern const signed short RX_MIDDLE_TQ_TABLE2[2];
+/*MT6218~*//*MT6218~*/ extern const signed short TX_START_TQ_TABLE2[1];
+ #endif
+/*MT6218~*/
+ #if IS_CHIP_MT6225_AND_LATTER_VERSION
+/*MT6218~*//*MT6225*/ extern const short NB_FIR_COEF[];
+/*MT6218~*//*MT6225*/ extern const short NB_FIR_COEF_WIDER[];
+ #endif
+/*MT6218~*/
+#endif /* End of "IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION" */
+
+#if IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT
+extern CONST signed short PDATA_SX_TABLE[5][2][2];
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_DUAL_LOOP_AFC_CONTROL_SUPPORT
+extern unsigned char USE_3_SUBSTAGES_FB_STAGE1;
+#elif !IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+extern const unsigned char USE_3_SUBSTAGES_FB_STAGE1;
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_RF_MT6140D
+extern CONST unsigned long TXCW[/*2*/][2][5];
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_MPLL_FH_SUPPORT || IS_MT6276E1_TEMP_MPLL_FH_SUPPORT || IS_MT6276_FREERUN_SUPPORT
+extern unsigned char MPLL_FLT;
+#endif
+
+#if IS_SPLL_FH_SUPPORT
+extern unsigned char SPLL_FLT;
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_32K_CRYSTAL_REMOVAL_SUPPORT
+extern char l1d_ext_32k_exist;
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_32K_CRYSTAL_REMOVAL_SUPPORT || IS_DUAL_LOOP_AFC_CONTROL_SUPPORT
+extern int afc_Phi_est;
+ #if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+extern int locked_DacValue;
+extern int current_DacValue;
+ #if IS_TELEMATICS_HIGH_TEMPERATURE_SUPPORT
+extern int current_DacValueTemperature;
+ #endif
+extern int afc_dac_default_ori;
+ #else
+extern short locked_DacValue;
+extern short current_DacValue;
+extern short afc_dac_default_ori;
+ #endif /* IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT */
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+
+#define TQ_PM0_BEGIN_HF (TQ_AFC_READY+TQ_SLOT_LEN-TQ_SHORT_PMWIN_LEN_IN_IDLE)
+
+#if L1D_PM_ENHANCE
+//#define TQ_PM_WIN_OFF_MARGIN 8 // TQ_PM_WIN_OFF_MARGIN is moved to l1d_public.h
+#define TQ_PM1_BEGIN_HF (TQ_SLOT1_BEGIN+TQ_AFC_READY+TQ_PM_WIN_OFF_MARGIN)
+#define TQ_PM2_BEGIN_HF (TQ_PM1_BEGIN_HF+TQ_SHORT_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+TQ_PM_WIN_OFF_MARGIN)
+#define TQ_PM3_BEGIN_HF (TQ_PM2_BEGIN_HF+TQ_SHORT_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+TQ_PM_WIN_OFF_MARGIN)
+#define TQ_VALIDATE_COUNT_HF (TQ_PM3_BEGIN_HF+TQ_SHORT_PMWIN_LEN_IN_IDLE+TQ_PM_WIN_OFF_MARGIN)
+#define TQ_CTIRQ2_HF (TQ_PM1_BEGIN_HF+TQ_SHORT_PMWIN_LEN_IN_IDLE+100)
+#define TQ_PM_REGBIAS_OFF_HF (((TQ_SHORT_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+TQ_PM_WIN_OFF_MARGIN)*4)+TQ_PM_WIN_OFF_MARGIN)
+ #if IS_FHC_SUPPORT
+#define TQ_PM_REGBIAS_OFF_FHC TQ_SLOT4_BEGIN//(TQ_SLOT4_BEGIN + TQ_AFC_READY)
+ #endif
+
+#define TQ_PM2_END_2ND_HF (TQ_PM_REGBIAS_OFF_HF+TQ_PM2_BEGIN_HF+TQ_SHORT_PMWIN_LEN_IN_IDLE+20)
+ #if IS_NEW_L1D_ARCH_8R_SUPPORT
+#define CTIRQ1_READ_SLOTS_IN_2ND_HF (1)//Read PM2 of 2nd HF in CTIRQ1
+#define IS_CHECK_8PM_DSPPROC 0
+ #elif (TQ_PM2_END_2ND_HF < TQ_CTIRQ1)
+#define CTIRQ1_READ_SLOTS_IN_2ND_HF (3)//Read PM2 of 2nd HF in CTIRQ1
+#define IS_CHECK_8PM_DSPPROC 0
+ #else
+#define CTIRQ1_READ_SLOTS_IN_2ND_HF (2)//Read PM2 of 2nd HF in the following CTIRQ1/CTIRQ2H
+#define IS_CHECK_8PM_DSPPROC 1
+ #endif
+
+ #if IS_NEW_L1D_ARCH_8R_SUPPORT
+#define CTIRQ1_READ_SLOTS (3)
+#define CTIRQ2_READ_SLOTS_IN_1ST_HF (0)
+#define CTIRQ1_READ_SLOTS_IN_2ND_HF_1R7PM (1)
+ #elif IS_NEW_L1D_ARCH_6R_SUPPORT
+#define CTIRQ1_READ_SLOTS (4)
+#define CTIRQ2_READ_SLOTS_IN_1ST_HF (2)
+#define CTIRQ1_READ_SLOTS_IN_2ND_HF_1R7PM (9)
+ #else
+#define CTIRQ1_READ_SLOTS (6)
+#define CTIRQ2_READ_SLOTS_IN_1ST_HF (2)
+#define CTIRQ1_READ_SLOTS_IN_2ND_HF_1R7PM (9)
+ #endif
+
+ #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT && IS_FDD_DUAL_MODE_SUPPORT
+extern const signed short SHORT_PM_START_TQ_TABLE_CT1_FDD[4];
+ #endif
+extern const signed short SHORT_PM_START_TQ_TABLE_CT1[4];
+extern const signed short SHORT_PM_START_TQ_TABLE_CT2H[4];
+ #if IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT
+ #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+extern const signed short SHORT_PM_END_POINT_TABLE_FDD[8];
+ #endif
+extern const signed short SHORT_PM_END_POINT_TABLE[8];
+ #endif
+
+#define TQ_CTIRQ1_HF_MIN (TQ_SLOT5_BEGIN+400) //3781
+ #if IS_NEW_L1D_ARCH_8R_SUPPORT
+#define TQ_CTIRQ1_HF (TQ_CTIRQ1)
+ #elif ( TQ_CTIRQ1_HF_MIN < TQ_CTIRQ1 )
+#define TQ_CTIRQ1_HF (TQ_CTIRQ1)
+ #else
+#define TQ_CTIRQ1_HF (TQ_CTIRQ1_HF_MIN)
+ #endif
+
+ #if L1D_PM_1R7PM
+#define TQ_PM0_BEGIN_1R7PM (TQ_SLOT1_BEGIN-TQ_1R7PM_PMWIN_LEN_IN_IDLE) // 753 (NULL)
+#define TQ_PM1_BEGIN_1R7PM (TQ_SLOT1_BEGIN+TQ_AFC_READY+TQ_PM_WIN_OFF_MARGIN) //1145
+#define TQ_PM2_BEGIN_1R7PM (TQ_PM1_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+TQ_PM_WIN_OFF_MARGIN) //1537
+#define TQ_PM3_BEGIN_1R7PM (TQ_PM2_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+TQ_PM_WIN_OFF_MARGIN) //1929
+#define TQ_PM4_BEGIN_1R7PM (TQ_PM3_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+TQ_PM_WIN_OFF_MARGIN) //2321
+/*
+#define TQ_PM5_BEGIN_1R7PM ((TQ_PM4_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+8)+8)//2721
+#define TQ_PM6_BEGIN_1R7PM (TQ_PM5_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+8) //3113
+#define TQ_PM7_BEGIN_1R7PM (TQ_CTIRQ1-100-TQ_1R7PM_PMWIN_LEN_IN_IDLE) //3553
+ */
+#define TQ_VALIDATE_COUNT_1R7PM (TQ_PM4_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_PM_WIN_OFF_MARGIN) //2457
+#define TQ_CTIRQ2_1R7PM (TQ_PM1_BEGIN_1R7PM+TQ_1R7PM_PMWIN_LEN_IN_IDLE+250) //1523
+#define TQ_PM_REGBIAS_OFF_1R7PM (((TQ_1R7PM_PMWIN_LEN_IN_IDLE+TQ_AFC_READY+TQ_PM_WIN_OFF_MARGIN)*5)+TQ_PM_WIN_OFF_MARGIN) //1968
+
+extern const signed short PM_1R7PM_START_TQ_TABLE[6];
+ #endif
+
+ #if IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT
+/*DM*/ #define TQ_CTIRQ2_FOR_PM_BEFORE_FB (TQ_SLOT0_BEGIN+TQ_SHORT_PMWIN_LEN+100)
+/*DM*/ #define TQ_VALIDATE_COUNT_FOR_PM_BEFORE_FB (TQ_CTIRQ2_FOR_PM_BEFORE_FB+300)
+/*DM*/ #define TQ_DTIRQ_FOR_PM_BEFORE_FB (TQ_VALIDATE_COUNT_FOR_PM_BEFORE_FB+30)
+ #endif
+
+ #if IS_NEW_L1D_ARCH_8R_SUPPORT
+#undef TQ_CTIRQ2_HF
+#undef TQ_CTIRQ2_1R7PM
+#define TQ_CTIRQ2_HF TQ_CTIRQ2
+#define TQ_CTIRQ2_1R7PM TQ_CTIRQ2
+ #endif
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+/* Power offset of WB/NB RX filter depens on WB/NB filter coefficients */
+/* From MT6223~, the WB/NB power offset is not a constant, and the 64-symbol NB power is reported when WB is selected */
+#if IS_CHIP_MT6223
+#define WBNB_RX_FILTER_POWER_OFFSET 0 /* 0.75 *64 */
+#elif IS_CHIP_MT6229 || IS_CHIP_MT6268T
+#define WBNB_RX_FILTER_POWER_OFFSET 88 /* 1.375*64 */
+#elif IS_CHIP_MT6225_AND_LATTER_VERSION
+#define WBNB_RX_FILTER_POWER_OFFSET 80 /* 1.25 *64 */
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_FHC_SUPPORT
+#define FHC_PROC_NONE 0x00
+#define FHC_PROC_DTS_AFC_WB 0x01
+#define FHC_PROC_DTS_AFC_NB_SYNC 0x02
+#define FHC_PROC_DTS_START 0x04
+#define FHC_PROC_DTS_PL 0x10
+#define FHC_PROC_UTS_PCL 0x20
+#define FHC_PROC_UTS_DAC 0x40
+ #if IS_32K_CRYSTAL_REMOVAL_SUPPORT
+#define FHC_PROC_DTS_DCXO_LPM 0x80
+ #endif
+ #if IS_TX_GAIN_RF_CALIBRATION_SUPPORT
+#define FHC_PROC_UTS_GAIN_RF_IDX 0x100
+ #endif
+/*
+ #if IS_GPRS
+#define FHC_PM_SLOT_FOR_PL 6
+ #endif
+ #if IS_GSM
+#define FHC_PM_SLOT_FOR_PL 4
+ #endif
+*/
+#define FHC_PM_SLOT_FOR_PL 4
+
+#define FHC_SB_FAIL_THRESHOLD 255
+#define FHC_PM_SLOT_FOR_FCCH 4
+ #if IS_DSP_ARCHITECTURE_V4_SUPPORT
+#define FHC_SB_SNR_THRESHOLD 10
+ #else
+#define FHC_SB_SNR_THRESHOLD (-1)
+ #endif
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_DLIF_CHIP || IS_DCR_IN_DLIF_CHIP
+#define NB_FIR_4DC_NORMAL_IFSEL0 0x7F7F //( -1, -1)
+ #if (IS_CHIP_MT6256_S00 || IS_CHIP_MT6251_S00) && defined(L1D_TEST)
+#define WB_FIR_4DC_NORMAL_IFSEL0 0x7C7C //( -4, -4)
+ #else
+#define WB_FIR_4DC_NORMAL_IFSEL0 0x7F7F //( -1, -1)
+ #endif
+
+/*
+#define NB_FIR_4DC_NORMAL_IFSEL1 0x7F01 //( -1, 1), no-use, HW do complex-conjugate by itself
+#define WB_FIR_4DC_NORMAL_IFSEL1 0x7C04 //( -4, 4), no-use, HW do complex-conjugate by itself
+ */
+ #if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
+#define NB_FIR_4DC_FB_POWRON_IFSEL0 0x6A16 //(-22, 22)
+#define WB_FIR_4DC_FB_POWRON_IFSEL0 0x2929 //( 41, 41)
+
+#define NB_FIR_4DC_FB_POWRON_IFSEL1 0x1212 //( 18, 18)
+#define WB_FIR_4DC_FB_POWRON_IFSEL1 0x2957 //( 41,-41)
+ #endif
+
+ #if IS_CHIP_MT6256_S00
+ #elif IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+ #if defined(L1D_TEST)
+#define DCOC_QB_RX_FENA_2_FSYNC 32
+ #if IS_BFE_RX_TYPE_NB_EN_SUPPORT
+#define CIC1_DLY_NB 26 // filter CIC1 group delay
+#define MAX_ALLOWED_OFFSET_NB 4 // max value for current data does NOT overlap the previous slot
+#define FIR3_DLY 20 // filter FIR3 group delay
+#define CIC1_DLY 30 // filter CIC1 group delay
+#define MAX_ALLOWED_OFFSET 0 // max value for current data does NOT overlap the previous slot
+ #else
+#define CIC1_DLY 26 // filter CIC1 group delay
+#define MAX_ALLOWED_OFFSET 4 // max value for current data does NOT overlap the previous slot
+#define FIR3_DLY 20 // filter FIR3 group delay
+ #endif
+ #elif IS_BFE_RX_TYPE_NB_EN_SUPPORT
+#define DCOC_QB_RX_FENA_2_FSYNC 48
+#define CIC1_DLY_NB 26 // filter CIC1 group delay
+#define MAX_ALLOWED_OFFSET_NB 15 // max value for current data does NOT overlap the previous slot
+#define FIR3_DLY 20 // filter FIR3 group delay
+#define CIC1_DLY 38 // filter CIC1 group delay
+#define MAX_ALLOWED_OFFSET 10 // max value for current data does NOT overlap the previous slot
+ #elif IS_RX_DCOC_ADVANCED_SUPPORT
+#define DCOC_QB_RX_FENA_2_FSYNC 48
+#define CIC1_DLY 38 // filter CIC1 group delay
+#define MAX_ALLOWED_OFFSET 10 // max value for current data does NOT overlap the previous slot
+#define FIR3_DLY 20 // filter FIR3 group delay
+ #else
+#define DCOC_QB_RX_FENA_2_FSYNC 48
+#define CIC1_DLY 26 // filter CIC1 group delay
+#define MAX_ALLOWED_OFFSET 15 // max value for current data does NOT overlap the previous slot
+#define FIR3_DLY 20 // filter FIR3 group delay
+ #endif
+ #if IS_BFE_RX_TYPE_NB_EN_SUPPORT
+// for RX_TIME_CON0
+#define RX_DCOC_STR_NB (DCOC_QB_RX_FENA_2_FSYNC-CIC1_DLY_NB) // C1 for NB
+#define RX_NULL_STR_NB (RX_DCOC_STR_NB-MAX_ALLOWED_OFFSET_NB) // C3 for NB
+// for RX_TIME_CON1
+#define RX_IRCMPN_SW (DCOC_QB_RX_FENA_2_FSYNC-FIR3_DLY) // C2
+// for RX_TIME_CON2
+#define RX_DCOC_STR (DCOC_QB_RX_FENA_2_FSYNC-CIC1_DLY) // C1 for non-NB
+#define RX_NULL_STR (RX_DCOC_STR-MAX_ALLOWED_OFFSET) // C3 for non-NB
+ #else
+// for RX_TIME_CON0
+#define RX_DCOC_STR (DCOC_QB_RX_FENA_2_FSYNC-CIC1_DLY) // C1
+#define RX_NULL_STR (RX_DCOC_STR-MAX_ALLOWED_OFFSET) // C3
+// for RX_TIME_CON1
+#define RX_IRCMPN_SW (DCOC_QB_RX_FENA_2_FSYNC-FIR3_DLY) // C2
+ #endif
+ #endif
+
+/*...........................................................................*/
+ #if (IS_CHIP_MT6256_S00 || IS_CHIP_MT6251_S00) && defined(L1D_TEST)
+#define THR_ITD_DEFAULT 0x96 //150
+ #else
+#define THR_ITD_DEFAULT 0xA0 //160
+ #endif
+
+ #if defined(L1D_TEST)
+#define TX_CNT_TGT_DEFAULT 158
+ #elif IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define TX_BB_GROUP_DELAY 12
+#else
+#define TX_BB_GROUP_DELAY 10
+#endif
+#define TX_CNT_TGT_DEFAULT (QB_TX_FENA_2_FSYNC-(QB_TON_2_FSYNC-TX_BB_GROUP_DELAY))
+ #elif IS_CHIP_MT6583_MD2
+#define TX_CNT_TGT_DEFAULT QB_BFE_TXCOMP_HYS
+ #else
+#define TX_CNT_TGT_DEFAULT 36 //140
+ #endif
+
+#define PM_DLY_DEFAULT 0
+ #if IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define AM_DLY_DEFAULT 1
+ #elif IS_CHIP_MT6583_MD2
+#define AM_DLY_DEFAULT 0
+ #endif
+#define P2X_SCALE_DEFAULT 0x3A //58
+
+ #if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
+#define TX_CNT_TGT_SW_DEFAULT 0
+ #else
+#define TX_CNT_TGT_SW_DEFAULT TX_CNT_TGT_DEFAULT //For normal mode, TX_CNT_TGT_SW_DEFAULT should be equal to TX_CNT_TGT_DEFAULT
+ #endif //For loopback mode, we set TX_CNT_TGT_SW_DEFAULT=146 in L1DTest_Init2()
+
+#define TX_CON0_DEFAULT 0
+#define TX_CON1_DEFAULT ( ((PM_DLY_DEFAULT&0xF)<<8)|TX_CNT_TGT_DEFAULT )
+
+ #if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
+#define RX_CON3_DEFAULT ( THR_ITD_DEFAULT<<8 )
+#define TX_PWR_DEFAULT ( (TX_CNT_TGT_SW_DEFAULT&0xFF)<<8 )
+ #else
+#define TX_CON2_DEFAULT ( (TX_CNT_TGT_SW_DEFAULT&0xFF)<<8 )
+ #endif
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+// MT6573E1, MD2G sleep ECO for pause abort on preclock_off rising edge
+#if IS_CHIP_MT6573
+#define EVTENA0_SLOW_EN_SEL (0x1<<4)
+#else
+#define EVTENA0_SLOW_EN_SEL (0)
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_TX_POWER_CONTROL_SUPPORT
+ #if IS_TXPC_CL_AUXADC_SUPPORT
+extern short scan_qb;
+extern CONST short TQ_TxSampleOffsetGMSK;
+ #if IS_EPSK_TX_SUPPORT
+extern CONST short TQ_TxSampleOffsetEPSK;
+ #endif
+ #endif
+ #if IS_TXPC_OL_BSI_SUPPORT || IS_TXPC_OL_AUXADC_SUPPORT
+extern CONST short txpc_epsk_tp_slope_lb;
+extern CONST short txpc_epsk_tp_slope_hb;
+ #endif
+extern const char temp_adc_cal_type;
+#endif
+
+/*---------------------------------------------------------------------------*/
+/* RX LNA calbiration */
+#if IS_MULTI_LNA_MODE_CALIBRATION_SUPPORT
+extern const char is_lna_calibration;
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT || IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2
+extern CONST signed short TQ_EPSK_TX_delay;
+#endif
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_RF_TOOL_CUSTOMIZATION_SUPPORT
+#define RFDEF (signed short)0xABCD
+#define URFDEF (unsigned short)0xABCD
+
+typedef struct
+{
+ int start; // the special pattern of start position
+ int version; // Struct Version ID
+ int RF_Type; // RF type
+ char is_data_update; // default is false, and will be changed as true after tool update
+ sint_P xPDATA_TABLE[5][2][5];
+ sint_P xPDATA_TABLE3[5][3][3];
+ signed short xRX_START_TQ_TABLE[8];
+ signed short xRX_END_TQ_TABLE[5];
+ signed short xRX_MIDDLE_TQ_TABLE[3];
+ signed short xRX_MIDDLE_TQ_TABLE2[2];
+ signed short xTX_START_TQ_TABLE[8];
+ signed short xTX_START_TQ_TABLE2[1];
+ signed short xTX_START_TQ_TABLE3[1];
+ signed short xTX_END_TQ_TABLE[6];
+ signed short xTX_MIDDLE_TQ_TABLE[4];
+ signed short xTX_MIDDLE_TQ_TABLE2[2][4];
+ signed short xPM_START_TQ_TABLE[7];
+ signed short xPM_TQ_TABLE[10];
+ signed short xPM_IN_IDLE_TQ_TABLE[10];
+ signed short xPM_1R7PM_TQ_TABLE[10];
+ signed short xFSWIN_STOP_DATA_TABLE[9];
+ unsigned short xtxios_pcl_tab[2][2][5];
+ unsigned short xtxitc_pcl_tab[2][2][5];
+ unsigned short xtxmod_gc_tab[2][2][5];
+ long XO_CapID; // L1 Rf data
+ int end1; // the special pattern of end1 position
+ signed short xPDATA_GMSK;
+ signed short xPDATA_8PSK;
+ signed short xGSM850_GSM900_SWAP;
+ signed short xDCS1800_PCS1900_SWAP;
+ int xBAT_VOLTAGE_SAMPLE_PERIOD;
+ int xBAT_VOLTAGE_AVERAGE_COUNT;
+ int xBAT_TEMPERATURE_SAMPLE_PERIOD;
+ int xBAT_TEMPERATURE_AVERAGE_COUNT;
+ int xBAT_LOW_VOLTAGE;
+ int xBAT_HIGH_VOLTAGE;
+ int xBAT_LOW_TEMPERATURE;
+ int xBAT_HIGH_TEMPERATURE;
+ int end2; // the special pattern of end2 position
+} sRF_TABLE;
+
+extern sRF_TABLE l1_rf_table;
+
+#endif
+
+/*-------------------------------------------------------------------------------------------------------------------*/
+/*----------------------------------------------- TDD Dual Mode Begin -----------------------------------------------*/
+/*-------------------------------------------------------------------------------------------------------------------*/
+#if IS_TDD_DUAL_MODE_SUPPORT
+/*TDD*/ #define TQ_CTIRQ2_HF2_TD_DM TQ_VALIDATE-100 // 4839
+/* The tming margin left for DSP PM decoded is not enough. 5000us-675us*2 = 3954QB.
+ If 2 PM (at max 2PM created in a TD slot gap) created 3954+2*(256+128+8)= 4738QB.
+ 4738QB+100QB = 4838QB ~= 4939-100 to read PM */
+/*TDD*/ extern const signed short TD_DM_PM_BEGIN_POINT_TABLE[8];
+/*TDD*/ extern const signed short TD_DM_PM_END_POINT_TABLE[8];
+/*TDD*/ extern unsigned long TD_AFC_switch_GPIO_pin;
+/*TDD*/ extern signed long TD_AFC_switch_GPIO_status;
+#endif
+extern CONST signed short TD_DM_PM_TQ_TABLE[11];
+
+
+#if IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT
+/*WT */ #define FB_ENHANCE_TQ_LEN_TABLE_SIZE 4
+/*WT */ extern CONST signed short FB_ENHANCE_TQ_LEN_TABLE[FB_ENHANCE_TQ_LEN_TABLE_SIZE];
+/*WT */ extern CONST signed short FB_BURST_SCALOR_TABLE[FB_ENHANCE_TQ_LEN_TABLE_SIZE];
+/*WT */ extern CONST signed short FB_BURST_RESOLUTION_TABLE[FB_ENHANCE_TQ_LEN_TABLE_SIZE];
+/*WT */ #define SB_EXTEND_TQ_LEN_TABLE_SIZE 3
+/*WT */ extern CONST signed short SB_EXTEND_TQ_LEN_TABLE[SB_EXTEND_TQ_LEN_TABLE_SIZE];
+/*WT */ extern CONST signed short SB_BURST_SCALOR_TABLE[SB_EXTEND_TQ_LEN_TABLE_SIZE];
+/*WT */ extern CONST signed short SB_BURST_RESOLUTION_TABLE[SB_EXTEND_TQ_LEN_TABLE_SIZE];
+#endif /* IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT */
+
+/*-------------------------------------------------------------------------------------------------------------------*/
+/*----------------------------------------------- TDD Dual Mode End -------------------------------------------------*/
+/*-------------------------------------------------------------------------------------------------------------------*/
+
+#if IS_MULTI_MODE_AFC_WITH_SHM_SUPPORT
+#define TRUST_LATEST_UPDATE_DURATION 300000000 /* 5min */
+#endif
+
+#endif /*End of "#ifndef _L1D_DATA_H_" */
+
diff --git a/mcu/interface/l1/gl1/external/l1d_data_pcore.h b/mcu/interface/l1/gl1/external/l1d_data_pcore.h
new file mode 100644
index 0000000..42111ff
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_data_pcore.h
@@ -0,0 +1,370 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_data_pcore.h
+ *
+ * Project:
+ * --------
+ * TK6291
+ *
+ * Description:
+ * ------------
+ * Definition of global data & tables used in L1D
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
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+ *
+ *
+ *******************************************************************************/
+
+#ifndef _L1D_DATA_PCORE_H_
+#define _L1D_DATA_PCORE_H_
+/*---------------------------------------------------------------------------*/
+#include "l1d_cid.h"
+#if IS_2G_DRDI_SUPPORT
+#include "mml1_custom_drdi.h"
+#include "l1d_custom_drdi.h"
+#endif
+
+#if IS_2G_DYNAMIC_SAR_TABLE_SUPPORT
+#include "l1d_custom_common.h"
+#endif
+
+#if IS_CHIP_MT6295
+ #ifndef IS_GEN95_L1D_CUSTOM_DYNAMIC_SUPPORT
+ #define IS_GEN95_L1D_CUSTOM_DYNAMIC_SUPPORT 0
+ #endif
+#endif
+
+#if IS_2G_DRDI_SUPPORT
+ #if L1D_CUSTOM_DYNAMIC_INIT_ENABLE && defined (__MTK_TARGET__)
+ #if IS_GEN95_L1D_CUSTOM_DYNAMIC_SUPPORT
+#define L1D_CUSTOM_DYNAMIC_SUPPORT 1
+ #else
+#define L1D_CUSTOM_DYNAMIC_SUPPORT IS_MML1_DRDI_ENABLE
+ #endif
+#define L1D_CUSTOM_TOTAL_SET_NUMS MML1_DRDI_REMAP_GGE_REAL_SET_NUMS
+#define IS_2G_CALIBRATION_DATA_DRDI_ENABLE 1
+ #else
+#define L1D_CUSTOM_DYNAMIC_SUPPORT 0
+#define L1D_CUSTOM_TOTAL_SET_NUMS 1
+#define IS_2G_CALIBRATION_DATA_DRDI_ENABLE 0
+ #endif
+#else
+#define L1D_CUSTOM_DYNAMIC_SUPPORT 0
+#define L1D_CUSTOM_TOTAL_SET_NUMS 1
+#define IS_2G_CALIBRATION_DATA_DRDI_ENABLE 0
+#endif
+
+extern const sL1D_FRONT_END_DATA l1d_front_end_data[L1D_CUSTOM_TOTAL_SET_NUMS];
+
+#if defined(__MD97__)||defined(__MD97__)
+//none
+#elif defined(__2G_MIPI_SUPPORT__)
+extern const sGGE_DRDI_MIPI_CTRL_TABLE l1d_mipi_ctrl_data[L1D_CUSTOM_TOTAL_SET_NUMS];
+#endif
+
+extern sCrystalParameter afc_crystal_data;
+
+#if IS_32K_CRYSTAL_REMOVAL_SUPPORT
+extern sCloadParameter CLoad_FreqOffset_data;
+#endif
+
+extern sTX_POWER_VOLTAGE_COMPENSATION tx_apc_voltage_compensation;
+extern unsigned char l1_2g_drdi_done;
+
+
+extern const sl1CustomBandSupport* L1D_Custom_Band_Support_Data_Array[L1D_CUSTOM_TOTAL_SET_NUMS];
+extern sl1CustomBandSupport l1d_custom_band_support;
+
+extern const sL1D_CAL_DATA L1D_Cal_Data[L1D_CUSTOM_TOTAL_SET_NUMS];
+
+extern const sL1D_CUSTOM_FEATURE_DATA l1d_feature_data[L1D_CUSTOM_TOTAL_SET_NUMS];
+
+#if IS_2G_DYNAMIC_SAR_TABLE_SUPPORT
+extern const L1D_CUSTOM_SAR_TX_BACKOFF_DB_NVRAM_T* l1d_sar_table_type_data[L1D_CUSTOM_TOTAL_SAR_TYPE_NUMS];
+#endif
+/*
+ extern Set0 symbols for L1D_PcoreUpdate2SHM_ByDefaultCustom() to use,
+ When IS_MML1_RF_PCORE_XL1SIM || IS_PCORE_BRINGUP_PHONECALL_TEMPLOAD_ENABLE
+ */
+extern const sAGCGAINOFFSET* AGC_PATHLOSS_TABLE_Set0[];
+
+extern const sRAMPDATA* RampData_Set0[];
+#if defined(__EPSK_TX__)
+extern const sRAMPDATA* RampData_EPSK_Set0[];
+#endif
+#if defined(__EPSK_TX__)
+extern const sMIDRAMPDATA* const* EPSK_InterRampData_Set0[];
+#endif
+extern const sMIDRAMPDATA* InterRampData_Set0[];
+
+#if IS_GPRS
+extern const sTX_POWER_ROLLBACK* tx_power_rollback_gmsk_Set0[];
+#endif
+
+#if IS_EGPRS
+extern const sTX_POWER_ROLLBACK* tx_power_rollback_epsk_Set0[];
+#endif
+#if IS_TX_POWER_CONTROL_SUPPORT
+extern const sTXPC_TEMPDATA TEMP_DAC_Set0;
+extern const sTXPC_TEMPDATA* TXTEMP_Data_Set0[];
+ #if defined(__EPSK_TX__)
+extern const sTXPC_TEMPDATA* TXTEMP_Data_EPSK_Set0[];
+ #endif /* __EPSK_TX__ */
+ #if IS_TXPC_CL_AUXADC_SUPPORT || IS_TXPC_CL_BSI_SUPPORT
+extern const sTXPC_ADCDATA* TXADC_Data_Set0[];
+ #if defined(__EPSK_TX__)
+extern const sTXPC_ADCDATA* TXADC_Data_EPSK_Set0[];
+ #endif
+ #endif
+#endif
+
+extern const sLNAGAINOFFSET* LNA_PATHLOSS_TABLE_Set0[];
+
+#if IS_TX_POWER_OFFSET_SUPPORT
+extern const sTX_POWER_OFFSET* Tx_Power_Offset_GMSK_Set0[];
+ #if defined(__EPSK_TX__)
+extern const sTX_POWER_OFFSET* Tx_Power_Offset_EPSK_Set0[];
+ #endif
+#endif
+
+#if IS_RX_POWER_OFFSET_SUPPORT
+extern s2G_RF_RX_PARAMETER_EXT RX_POWER_OFFSET_SETTING_Set0;
+
+extern const sAGCLNAGAINOFFSET* AGCLNA_PATHLOSS_OFFSET_TABLE_Set0[];
+#endif/*IS_RX_POWER_OFFSET_SUPPORT*/
+
+#if IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT
+extern const sNSFT_ADJUST_TPO* Adjust_TPO_GMSK_Set0[];
+ #if defined(__EPSK_TX__)
+ #if IS_EPSK_ADJUST_TPO_SUPPORT
+extern const sNSFT_ADJUST_TPO* Adjust_TPO_EPSK_Set0[];
+ #endif//IS_EPSK_ADJUST_TPO_SUPPORT
+ #endif//__EPSK_TX__
+#endif//IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT
+
+extern const sCrystalParameter afc_crystal_data_Set0;
+
+#if IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2
+extern const sL1D_RF_CUSTOM_INPUT_DATA l1d_rf_custom_input_data_Set0;
+#endif
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+//none
+#elif IS_MIPI_SUPPORT
+extern const sGGE_MIPI_CTRL_TABLE_BAND* GGE_MIPI_CTRL_TABLE_Set0[];
+#endif
+
+extern const sl1CustomBandSupport l1d_custom_band_support_Set0;
+
+
+#if IS_2G_TAS_SUPPORT || IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT
+ #if IS_2G_TAS_INHERIT_4G_ANT
+extern const L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T L1_TAS_Custom_InheritLteAntTable_Set0;
+ #endif
+extern const L1D_CUSTOM_TAS_NVRAM_T L1_TAS_Custom_NVRAM_Set0;
+ #if IS_2G_TAS_SUPPORT || IS_2G_Gen95_UTAS_SUPPORT /*Not supported for Gen97*/
+extern const L1D_CUSTOM_TAS_FE_NVRAM_T L1_TAS_Custom_FE_NVRAM_Set0;
+extern const L1D_CUSTOM_TAS_TST_T L1_TAS_Custom_TST_Set0;
+ #endif
+#endif
+
+#if IS_2G_DAT_SUPPORT || IS_2G_Gen95_UDAT_SUPPORT || IS_2G_Gen97_UDAT_SUPPORT
+extern const L1D_CUSTOM_DAT_FE_ROUTE_NVRAM_T L1_DAT_Custom_FE_ROUTE_NVRAM_Set0;
+ #if IS_2G_DAT_SUPPORT
+extern const L1D_CUSTOM_DAT_FE_CAT_A_NVRAM_T L1_DAT_Custom_FE_CAT_A_NVRAM_Set0;
+extern const L1D_CUSTOM_DAT_FE_CAT_B_NVRAM_T L1_DAT_Custom_FE_CAT_B_NVRAM_Set0;
+ #endif
+#endif
+
+#if IS_ANT_RXPWR_OFFSET_SUPPORT
+extern const sL1D_ANT_RxPWR_Offset_T L1D_ANT_RxPWR_Offset_NVRAM_Set0;
+#endif
+
+#if IS_2G_DYNAMIC_HW_CLOCK_SUPPORT
+extern const L1D_RF_INTERFERENCE_ARFCN_INDICATION_T L1_HW_Custom_CLK_Set0;
+#endif
+
+extern l1cal_afcData_T afc_crystal_data_dac_slop;
+extern w_coef w_coef_data[ WCTABLE_SIZE ];
+extern orionRFtx_pa_vbias pa_data;
+
+#if IS_2G_RXD_SUPPORT
+ #if IS_RX_POWER_OFFSET_SUPPORT
+extern const sAGCLNAGAINOFFSET* AGCLNA_PATHLOSS_RXD_OFFSET_TABLE_Set0[];
+ #endif
+extern const sAGCGAINOFFSET* AGC_PATHLOSS_RXD_TABLE_Set0[];
+extern const sLNAGAINOFFSET* LNA_PATHLOSS_RXD_TABLE_Set0[];
+extern w_coef w_coef_rxd_data[ WCTABLE_SIZE ];
+extern const L1D_CUSTOM_RAS_NVRAM_T L1_RAS_Custom_NVRAM_Set0;
+#endif
+
+#if IS_SAR_TX_POWER_BACKOFF_SUPPORT
+extern const L1D_CUSTOM_SAR_TX_BACKOFF_DB_NVRAM_T L1_Custom_SAR_TX_BACKOFF_dB_Set0;
+#endif
+
+#endif /* End of _L1D_DATA_PCORE_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1d_gpt_if.h b/mcu/interface/l1/gl1/external/l1d_gpt_if.h
new file mode 100644
index 0000000..7e88f71
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_gpt_if.h
@@ -0,0 +1,9 @@
+#if (defined __MD93__)
+#include "l1d_gpt_if_gen93.h"
+#elif (defined __MD95__)
+#include "l1d_gpt_if_gen95.h"
+#elif (defined __MD97__)||(defined __MD97P__)
+#include "l1d_gpt_if_gen97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1d_gpt_if_gen93.h b/mcu/interface/l1/gl1/external/l1d_gpt_if_gen93.h
new file mode 100644
index 0000000..83d901a
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_gpt_if_gen93.h
@@ -0,0 +1,551 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * File name:
+ * ---------
+ * l1d_gpt_if.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * WCDMA test mode specific definitions for synchronizing with HOST tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 10 09 2018 yungshian.lai
+ * [MOLY00349865] TX POWER OFFSET feature uniform - VMOLY Trunk [ERS00016793].
+ *
+ * 03 30 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE option rename & NSFT swap patch.
+ *
+ * 03 07 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE fix UESIM build err & ContRx PCS1900.
+ *
+ * 03 02 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE Trunk TST part.
+ *
+ * 09 01 2017 yungshian.lai
+ * [MOLY00275140] [Bianco] 93 2G Cal Time Reduction Development - UMOLYA.
+ *
+ ****************************************************************************/
+
+#ifndef __L1D_GPT_IF_H__
+#define __L1D_GPT_IF_H__
+
+/*******************************************************************************
+ * Include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "ft_msg_l1rf.h"
+
+
+/*******************************************************************************
+ * Enumeration
+ ******************************************************************************/
+typedef enum
+{
+ g_sinwave_afc_get_temp_freq = RF_TEST_CMD_SINEWAVE_AFC_GET_TEMP_FREQ, // 106
+ g_set_wcoef = RF_TEST_CMD_SET_WCOEF, // 107
+ g_get_wcoef = RF_TEST_CMD_GET_WCOEF, // 108
+ g_set_txdata = RF_TEST_CMD_SET_TXDATA, // 109
+ g_set_txdata_onemod = RF_TEST_CMD_SET_TXDATA, // 109
+ g_set_txdata_notxpc = RF_TEST_CMD_SET_TXDATA, // 109
+ g_set_txdata_orignal = RF_TEST_CMD_SET_TXDATA, // 109
+
+ g_get_txdata = RF_TEST_CMD_GET_TXDATA, // 110
+ g_get_txdata_onemod = RF_TEST_CMD_GET_TXDATA, // 110
+ g_get_txdata_notxpc = RF_TEST_CMD_GET_TXDATA, // 110
+ g_get_txdata_orignal = RF_TEST_CMD_GET_TXDATA, // 110
+
+#if IS_2G_RXD_SUPPORT
+ g_get_rxd_info_v5 = RF_TEST_CMD_GET_RXD_INFO_V5, // 113
+
+ g_set_rxdata_all = RF_TEST_CMD_SET_RXDATA_V5, // 114
+ g_set_rxdata_partial = RF_TEST_CMD_SET_RXDATA_V5, // 114
+ g_set_rxdata_orignal = RF_TEST_CMD_SET_RXDATA_V5, // 114
+
+ g_get_rxdata_all = RF_TEST_CMD_GET_RXDATA_V5, // 115
+ g_get_rxdata_partial = RF_TEST_CMD_GET_RXDATA_V5, // 115
+ g_get_rxdata_orignal = RF_TEST_CMD_GET_RXDATA_V5, // 115
+
+ g_rx_gain_calculate = RF_TEST_CMD_RX_GAIN_CALCULATE_V5, //126
+#endif
+
+ g_get_tpo_value_v5 = RF_TEST_CMD_GET_TPO_VALUE_V5, // 128
+ g_set_tpo_value_v5 = RF_TEST_CMD_SET_TPO_VALUE_V5, // 129
+
+ g_test_command_1 = RF_TEST_CMD_GP_TOOL_COMMAND_START,
+ g_test_command_2,
+ g_test_command_3,
+ g_test_command_4,
+#if IS_2G_RXD_SUPPORT
+ g_test_rftool_set_path,
+#endif
+ /* --------------- please add new command posterior to this line --------------- */
+
+}ft_rf_test_req_id_cmd_enum_type;
+
+
+/*******************************************************************************
+ * Legacy RF Tool Commands
+ ******************************************************************************/
+
+
+
+/* --------------- please add new command structure posterior to this line --------------- */
+
+/*******************************************************************************
+ * GP RF Tool Commands I (for existing GL1 commands shown on GP tool UI)
+ ******************************************************************************/
+
+/* ---------------------------------------------- *\
+|* RF Test CMD no Req Param *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_uint8 void_param;
+}RfTestCmd_NoParam;
+
+typedef struct
+{
+ kal_uint32 void_result;
+} RfTestCmd_DefaultCnfParam;
+
+
+/* ---------------------------------------------- *\
+|* Use Sinwave AFC Get Freq & Temperature Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdSinewaveAfcGetTempFreq g_sinwave_afc_get_temp_freq_req_param_struct;
+typedef RfTestResultSinewaveAfcGetTempFreq g_sinwave_afc_get_temp_freq_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* SET Wcoef Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_bool is_uplate_to_NVRAM;
+}RfTestCmd_SetWcoef_ReqParam_GpTool;
+
+typedef struct
+{
+ kal_uint8 nvramAccessResult;
+}RfTestCmd_SetGetWcoef_CnfParam_GpTool;
+
+typedef RfTestCmd_SetWcoef_ReqParam_GpTool g_set_wcoef_req_param_struct;
+typedef RfTestCmdSetGetWcoefPdu g_set_wcoef_req_pdu_struct;
+typedef RfTestCmd_SetGetWcoef_CnfParam_GpTool g_set_wcoef_cnf_param_struct;
+//typedef RfTestCmdParam g_set_wcoef_req_param_struct;
+//typedef RfTestResultParam g_set_wcoef_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* GET Wcoef Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmd_NoParam g_get_wcoef_req_param_struct;
+typedef RfTestCmdSetGetWcoefPdu g_get_wcoef_cnf_pdu_struct;
+//typedef RfTestCmd_DefaultCnfParam g_get_wcoef_cnf_param_struct;
+typedef RfTestCmd_SetGetWcoef_CnfParam_GpTool g_get_wcoef_cnf_param_struct;
+
+
+
+
+/* ---------------------------------------------- *\
+|* SET Tx Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ //L1_RFSpecialCoef_Type4_T type4_rfspecialcoef_pdu;
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdSetTxDataReqPdu_GpTool;
+
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_req_param_struct;
+//typedef RfTestCmdSetTxDataReqPdu g_set_txdata_cnf_pdu_struct;
+typedef RfTestCmdSetTxDataReqPdu_GpTool g_set_txdata_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* SET Tx Command One Modulation *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[4];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[2];
+ L1_Txpc_Type3_T type3_txpc_pdu[1];
+ //L1_RFSpecialCoef_Type4_T type4_rfspecialcoef_pdu;
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdSetTxDataReqPdu_onemod_GpTool;
+
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_onemod_req_param_struct;
+typedef RfTestCmdSetTxDataReqPdu_onemod_GpTool g_set_txdata_onemod_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_onemod_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* SET Tx Command No TXPC *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[5];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[3];
+ //L1_Txpc_Type3_T type3_txpc_pdu[1];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdSetTxDataReqPdu_notxpc_GpTool;
+
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_notxpc_req_param_struct;
+typedef RfTestCmdSetTxDataReqPdu_notxpc_GpTool g_set_txdata_notxpc_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_notxpc_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* SET Tx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_orignal_req_param_struct;
+typedef RfTestCmdSetTxDataReqPdu g_set_txdata_orignal_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_orignal_cnf_param_struct;
+
+
+//******************************************************************************************************************//
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdGetTxDataCnfPdu_GpTool; //RfTestCmdGetTxDataCnfPdu
+
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu_GpTool g_get_txdata_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command One Modulation *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[4];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[2];
+ L1_Txpc_Type3_T type3_txpc_pdu[1];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdGetTxDataCnfPdu_onemod_GpTool; //RfTestCmdGetTxDataCnfPdu
+
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_onemod_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu_onemod_GpTool g_get_txdata_onemod_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_onemod_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command No TXPC *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[5];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[3];
+ //L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdGetTxDataCnfPdu_notxpc_GpTool; //RfTestCmdGetTxDataCnfPdu
+
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_notxpc_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu_notxpc_GpTool g_get_txdata_notxpc_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_notxpc_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_orignal_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu g_get_txdata_orignal_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_orignal_cnf_param_struct;
+
+
+
+//******************************************************************************************************************//
+
+
+#if IS_2G_RXD_SUPPORT
+/* ---------------------------------------------- *\
+|* GET RXD Info *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_bool ok; //RfTestResultParam
+}RfTestCmdGetRXDInfoCnfParam_GPTool;
+
+typedef RfTestCmd_NoParam g_get_rxd_info_v5_req_param_struct;
+typedef RfTestCmdCalInfoV5AllBandCnfPdu_T g_get_rxd_info_v5_cnf_pdu_struct;
+typedef RfTestCmdGetRXDInfoCnfParam_GPTool g_get_rxd_info_v5_cnf_param_struct;
+
+//******************************************************************************************************************//
+
+
+/* ---------------------------------------------- *\
+|* SET Rx Command all *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+}RfTestCmdSetRxDataReqPdu_GpTool;
+
+typedef RfTestCmdSetRxDataReqParam g_set_rxdata_all_req_param_struct;
+//typedef RfTestCmdSetRxDataReqPdu g_set_rxdata_cnf_pdu_struct;
+typedef RfTestCmdSetRxDataReqPdu_GpTool g_set_rxdata_all_req_pdu_struct;
+typedef RfTestCmdSetRxDataCnfParam g_set_rxdata_all_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* SET Rx Command RXM or RXD only *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[4];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[1];
+}RfTestCmdSetRxDataReqPdu_partial_GpTool;
+
+typedef RfTestCmdSetRxDataReqParam g_set_rxdata_partial_req_param_struct;
+typedef RfTestCmdSetRxDataReqPdu_partial_GpTool g_set_rxdata_partial_req_pdu_struct;
+typedef RfTestCmdSetRxDataCnfParam g_set_rxdata_partial_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* SET Rx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdSetRxDataReqParam g_set_rxdata_orignal_req_param_struct;
+typedef RfTestCmdSetRxDataReqPdu g_set_rxdata_orignal_req_pdu_struct;
+typedef RfTestCmdSetRxDataCnfParam g_set_rxdata_orignal_cnf_param_struct;
+
+//******************************************************************************************************************//
+
+/* ---------------------------------------------- *\
+|* GET Rx Command All*|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+}RfTestCmdGetRxDataCnfPdu_GpTool; //RfTestCmdGetRxDataCnfPdu
+
+typedef RfTestCmdGetRxDataReqParam g_get_rxdata_all_req_param_struct;
+typedef RfTestCmdGetRxDataCnfPdu_GpTool g_get_rxdata_all_cnf_pdu_struct;
+typedef RfTestCmdGetRxDataCnfParam g_get_rxdata_all_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* GET Rx Command Partial *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[4];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[1];
+}RfTestCmdGetRxDataCnfPdu_partial_GpTool; //RfTestCmdGetRxDataCnfPdu
+
+typedef RfTestCmdGetRxDataReqParam g_get_rxdata_partial_req_param_struct;
+typedef RfTestCmdGetRxDataCnfPdu_partial_GpTool g_get_rxdata_partial_cnf_pdu_struct;
+typedef RfTestCmdGetRxDataCnfParam g_get_rxdata_partial_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* GET Rx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdGetRxDataReqParam g_get_rxdata_orignal_req_param_struct;
+typedef RfTestCmdGetRxDataCnfPdu g_get_rxdata_orignal_cnf_pdu_struct;
+typedef RfTestCmdGetRxDataCnfParam g_get_rxdata_orignal_cnf_param_struct;
+
+//******************************************************************************************************************//
+
+
+/* ---------------------------------------------- *\
+|* GET Rx Gain Calculate value *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdRxGainCalculate_V5 g_rx_gain_calculate_req_param_struct;
+typedef RfTestResultRxGainCalculate_V5 g_rx_gain_calculate_cnf_param_struct;
+//******************************************************************************************************************//
+#endif //#if IS_2G_RXD_SUPPORT
+
+/* ---------------------------------------------- *\
+|* GET/SET TPO Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdGetTPO g_get_tpo_value_v5_req_param_struct;
+typedef RfTestResultGetTPO g_get_tpo_value_v5_cnf_param_struct;
+
+typedef RfTestCmdSetTPO g_set_tpo_value_v5_req_param_struct;
+typedef RfTestCmd_NoParam g_set_tpo_value_v5_cnf_param_struct;
+
+
+/*******************************************************************************
+ * GP RF Tool Commands
+ ******************************************************************************/
+
+/* ------------------ *\
+|* G_TEST_COMMAND_1 *|
+\* ------------------ */
+//PDU: ReqPdu, X
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_1_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} g_test_command_1_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_1_cnf_param_struct;
+
+
+/* ------------------ *\
+|* G_TEST_COMMAND_2 *|
+\* ------------------ */
+//PDU: ReqPdu, CnfPdu
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_2_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} g_test_command_2_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_2_cnf_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_pdu1;
+ kal_uint16 cnf_pdu2;
+ kal_uint16 cnf_pdu3;
+} g_test_command_2_cnf_pdu_struct;
+
+
+/* ------------------ *\
+|* G_TEST_COMMAND_3 *|
+\* ------------------ */
+//PDU: X, CnfPdu
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_3_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_3_cnf_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_pdu1;
+ kal_uint16 cnf_pdu2;
+ kal_uint16 cnf_pdu3;
+} g_test_command_3_cnf_pdu_struct;
+
+
+/* ------------------ *\
+|* G_TEST_COMMAND_4 *|
+\* ------------------ */
+//PDU: X, X
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_4_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_4_cnf_param_struct;
+
+
+#if IS_2G_RXD_SUPPORT
+/* ---------------------- *\
+|* G_TEST_RFTOOL_SET_PATH *|
+\* ---------------------- */
+//PDU: X, X
+typedef struct
+{
+ FrequencyBand req_band;
+ GSM_AntDimension req_path; //GSM_ANT_MASK_RXM
+} g_test_rftool_set_path_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_ok;
+} g_test_rftool_set_path_cnf_param_struct;
+#endif //#if IS_2G_RXD_SUPPORT
+
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1d_gpt_if_gen95.h b/mcu/interface/l1/gl1/external/l1d_gpt_if_gen95.h
new file mode 100644
index 0000000..22a072a
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_gpt_if_gen95.h
@@ -0,0 +1,569 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * File name:
+ * ---------
+ * l1d_gpt_if.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * WCDMA test mode specific definitions for synchronizing with HOST tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 10 09 2018 yungshian.lai
+ * [MOLY00349865] TX POWER OFFSET feature uniform - VMOLY Trunk [ERS00016793].
+ *
+ * 09 18 2018 yungshian.lai
+ * [MOLY00349883] [MT6295][2G] NSFT RxLevel Resolution Enhancement- TST part - VMOLY Trunk.
+ *
+ * 03 30 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE option rename & NSFT swap patch.
+ *
+ * 03 07 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE fix UESIM build err & ContRx PCS1900.
+ *
+ * 03 02 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE Trunk TST part.
+ *
+ * 09 01 2017 yungshian.lai
+ * [MOLY00275140] [Bianco] 93 2G Cal Time Reduction Development - UMOLYA.
+ *
+ ****************************************************************************/
+
+#ifndef __L1D_GPT_IF_H__
+#define __L1D_GPT_IF_H__
+
+/*******************************************************************************
+ * Include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "ft_msg_l1rf.h"
+
+
+/*******************************************************************************
+ * Enumeration
+ ******************************************************************************/
+typedef enum
+{
+ g_sinwave_afc_get_temp_freq = RF_TEST_CMD_SINEWAVE_AFC_GET_TEMP_FREQ, // 106
+ g_set_wcoef = RF_TEST_CMD_SET_WCOEF, // 107
+ g_get_wcoef = RF_TEST_CMD_GET_WCOEF, // 108
+ g_set_txdata = RF_TEST_CMD_SET_TXDATA, // 109
+ g_set_txdata_onemod = RF_TEST_CMD_SET_TXDATA, // 109
+ g_set_txdata_notxpc = RF_TEST_CMD_SET_TXDATA, // 109
+ g_set_txdata_orignal = RF_TEST_CMD_SET_TXDATA, // 109
+
+ g_get_txdata = RF_TEST_CMD_GET_TXDATA, // 110
+ g_get_txdata_onemod = RF_TEST_CMD_GET_TXDATA, // 110
+ g_get_txdata_notxpc = RF_TEST_CMD_GET_TXDATA, // 110
+ g_get_txdata_orignal = RF_TEST_CMD_GET_TXDATA, // 110
+
+#if IS_2G_RXD_SUPPORT
+ g_get_rxd_info_v5 = RF_TEST_CMD_GET_RXD_INFO_V5, // 113
+
+ g_set_rxdata_all = RF_TEST_CMD_SET_RXDATA_V5, // 114
+ g_set_rxdata_partial = RF_TEST_CMD_SET_RXDATA_V5, // 114
+ g_set_rxdata_orignal = RF_TEST_CMD_SET_RXDATA_V5, // 114
+
+ g_get_rxdata_all = RF_TEST_CMD_GET_RXDATA_V5, // 115
+ g_get_rxdata_partial = RF_TEST_CMD_GET_RXDATA_V5, // 115
+ g_get_rxdata_orignal = RF_TEST_CMD_GET_RXDATA_V5, // 115
+
+ g_rx_gain_calculate = RF_TEST_CMD_RX_GAIN_CALCULATE_V5, // 126
+#endif
+ g_set_rxlev_prcsn = RF_TEST_CMD_SET_NSFT_RXLEV_PRECISION, // 127
+ g_get_tpo_value_v5 = RF_TEST_CMD_GET_TPO_VALUE_V5, // 128
+ g_set_tpo_value_v5 = RF_TEST_CMD_SET_TPO_VALUE_V5, // 129
+
+ g_test_command_1 = RF_TEST_CMD_GP_TOOL_COMMAND_START,
+ g_test_command_2,
+ g_test_command_3,
+ g_test_command_4,
+#if IS_2G_RXD_SUPPORT
+ g_test_rftool_set_path,
+#endif
+ /* --------------- please add new command posterior to this line --------------- */
+
+}ft_rf_test_req_id_cmd_enum_type;
+
+
+/*******************************************************************************
+ * Legacy RF Tool Commands
+ ******************************************************************************/
+
+
+
+/* --------------- please add new command structure posterior to this line --------------- */
+
+/*******************************************************************************
+ * GP RF Tool Commands I (for existing GL1 commands shown on GP tool UI)
+ ******************************************************************************/
+
+/* ---------------------------------------------- *\
+|* RF Test CMD no Req Param *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_uint8 void_param;
+}RfTestCmd_NoParam;
+
+typedef struct
+{
+ kal_uint32 void_result;
+} RfTestCmd_DefaultCnfParam;
+
+
+/* ---------------------------------------------- *\
+|* Use Sinwave AFC Get Freq & Temperature Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdSinewaveAfcGetTempFreq g_sinwave_afc_get_temp_freq_req_param_struct;
+typedef RfTestResultSinewaveAfcGetTempFreq g_sinwave_afc_get_temp_freq_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* SET Wcoef Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_bool is_uplate_to_NVRAM;
+}RfTestCmd_SetWcoef_ReqParam_GpTool;
+
+typedef struct
+{
+ kal_uint8 nvramAccessResult;
+}RfTestCmd_SetGetWcoef_CnfParam_GpTool;
+
+typedef RfTestCmd_SetWcoef_ReqParam_GpTool g_set_wcoef_req_param_struct;
+typedef RfTestCmdSetGetWcoefPdu g_set_wcoef_req_pdu_struct;
+typedef RfTestCmd_SetGetWcoef_CnfParam_GpTool g_set_wcoef_cnf_param_struct;
+//typedef RfTestCmdParam g_set_wcoef_req_param_struct;
+//typedef RfTestResultParam g_set_wcoef_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* GET Wcoef Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmd_NoParam g_get_wcoef_req_param_struct;
+typedef RfTestCmdSetGetWcoefPdu g_get_wcoef_cnf_pdu_struct;
+//typedef RfTestCmd_DefaultCnfParam g_get_wcoef_cnf_param_struct;
+typedef RfTestCmd_SetGetWcoef_CnfParam_GpTool g_get_wcoef_cnf_param_struct;
+
+
+
+
+/* ---------------------------------------------- *\
+|* SET Tx Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ //L1_RFSpecialCoef_Type4_T type4_rfspecialcoef_pdu;
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdSetTxDataReqPdu_GpTool;
+
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_req_param_struct;
+//typedef RfTestCmdSetTxDataReqPdu g_set_txdata_cnf_pdu_struct;
+typedef RfTestCmdSetTxDataReqPdu_GpTool g_set_txdata_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* SET Tx Command One Modulation *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[4];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[2];
+ L1_Txpc_Type3_T type3_txpc_pdu[1];
+ //L1_RFSpecialCoef_Type4_T type4_rfspecialcoef_pdu;
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdSetTxDataReqPdu_onemod_GpTool;
+
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_onemod_req_param_struct;
+typedef RfTestCmdSetTxDataReqPdu_onemod_GpTool g_set_txdata_onemod_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_onemod_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* SET Tx Command No TXPC *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[5];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[3];
+ //L1_Txpc_Type3_T type3_txpc_pdu[1];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdSetTxDataReqPdu_notxpc_GpTool;
+
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_notxpc_req_param_struct;
+typedef RfTestCmdSetTxDataReqPdu_notxpc_GpTool g_set_txdata_notxpc_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_notxpc_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* SET Tx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_orignal_req_param_struct;
+typedef RfTestCmdSetTxDataReqPdu g_set_txdata_orignal_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_orignal_cnf_param_struct;
+
+
+//******************************************************************************************************************//
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdGetTxDataCnfPdu_GpTool; //RfTestCmdGetTxDataCnfPdu
+
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu_GpTool g_get_txdata_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command One Modulation *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[4];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[2];
+ L1_Txpc_Type3_T type3_txpc_pdu[1];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdGetTxDataCnfPdu_onemod_GpTool; //RfTestCmdGetTxDataCnfPdu
+
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_onemod_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu_onemod_GpTool g_get_txdata_onemod_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_onemod_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command No TXPC *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[5];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[3];
+ //L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdGetTxDataCnfPdu_notxpc_GpTool; //RfTestCmdGetTxDataCnfPdu
+
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_notxpc_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu_notxpc_GpTool g_get_txdata_notxpc_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_notxpc_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_orignal_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu g_get_txdata_orignal_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_orignal_cnf_param_struct;
+
+
+
+//******************************************************************************************************************//
+
+
+#if IS_2G_RXD_SUPPORT
+/* ---------------------------------------------- *\
+|* GET RXD Info *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_bool ok; //RfTestResultParam
+}RfTestCmdGetRXDInfoCnfParam_GPTool;
+
+typedef RfTestCmd_NoParam g_get_rxd_info_v5_req_param_struct;
+typedef RfTestCmdCalInfoV5AllBandCnfPdu_T g_get_rxd_info_v5_cnf_pdu_struct;
+typedef RfTestCmdGetRXDInfoCnfParam_GPTool g_get_rxd_info_v5_cnf_param_struct;
+
+//******************************************************************************************************************//
+
+
+/* ---------------------------------------------- *\
+|* SET Rx Command all *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+}RfTestCmdSetRxDataReqPdu_GpTool;
+
+typedef RfTestCmdSetRxDataReqParam g_set_rxdata_all_req_param_struct;
+//typedef RfTestCmdSetRxDataReqPdu g_set_rxdata_cnf_pdu_struct;
+typedef RfTestCmdSetRxDataReqPdu_GpTool g_set_rxdata_all_req_pdu_struct;
+typedef RfTestCmdSetRxDataCnfParam g_set_rxdata_all_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* SET Rx Command RXM or RXD only *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[4];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[1];
+}RfTestCmdSetRxDataReqPdu_partial_GpTool;
+
+typedef RfTestCmdSetRxDataReqParam g_set_rxdata_partial_req_param_struct;
+typedef RfTestCmdSetRxDataReqPdu_partial_GpTool g_set_rxdata_partial_req_pdu_struct;
+typedef RfTestCmdSetRxDataCnfParam g_set_rxdata_partial_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* SET Rx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdSetRxDataReqParam g_set_rxdata_orignal_req_param_struct;
+typedef RfTestCmdSetRxDataReqPdu g_set_rxdata_orignal_req_pdu_struct;
+typedef RfTestCmdSetRxDataCnfParam g_set_rxdata_orignal_cnf_param_struct;
+
+//******************************************************************************************************************//
+
+/* ---------------------------------------------- *\
+|* GET Rx Command All*|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+}RfTestCmdGetRxDataCnfPdu_GpTool; //RfTestCmdGetRxDataCnfPdu
+
+typedef RfTestCmdGetRxDataReqParam g_get_rxdata_all_req_param_struct;
+typedef RfTestCmdGetRxDataCnfPdu_GpTool g_get_rxdata_all_cnf_pdu_struct;
+typedef RfTestCmdGetRxDataCnfParam g_get_rxdata_all_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* GET Rx Command Partial *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[4];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[1];
+}RfTestCmdGetRxDataCnfPdu_partial_GpTool; //RfTestCmdGetRxDataCnfPdu
+
+typedef RfTestCmdGetRxDataReqParam g_get_rxdata_partial_req_param_struct;
+typedef RfTestCmdGetRxDataCnfPdu_partial_GpTool g_get_rxdata_partial_cnf_pdu_struct;
+typedef RfTestCmdGetRxDataCnfParam g_get_rxdata_partial_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* GET Rx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdGetRxDataReqParam g_get_rxdata_orignal_req_param_struct;
+typedef RfTestCmdGetRxDataCnfPdu g_get_rxdata_orignal_cnf_pdu_struct;
+typedef RfTestCmdGetRxDataCnfParam g_get_rxdata_orignal_cnf_param_struct;
+
+//******************************************************************************************************************//
+
+
+/* ---------------------------------------------- *\
+|* GET Rx Gain Calculate value *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdRxGainCalculate_V5 g_rx_gain_calculate_req_param_struct;
+typedef RfTestResultRxGainCalculate_V5 g_rx_gain_calculate_cnf_param_struct;
+//******************************************************************************************************************//
+#endif //#if IS_2G_RXD_SUPPORT
+
+
+
+/* ---------------------- *\
+|* SET Rx Level Precision *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_uint8 rxlev_precision;
+}g_set_rxlev_prcsn_req_param_struct;
+
+typedef struct
+{
+ kal_bool ok;
+}g_set_rxlev_prcsn_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* GET/SET TPO Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdGetTPO g_get_tpo_value_v5_req_param_struct;
+typedef RfTestResultGetTPO g_get_tpo_value_v5_cnf_param_struct;
+
+typedef RfTestCmdSetTPO g_set_tpo_value_v5_req_param_struct;
+typedef RfTestCmd_NoParam g_set_tpo_value_v5_cnf_param_struct;
+
+
+/*******************************************************************************
+ * GP RF Tool Commands
+ ******************************************************************************/
+
+/* ------------------ *\
+|* G_TEST_COMMAND_1 *|
+\* ------------------ */
+//PDU: ReqPdu, X
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_1_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} g_test_command_1_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_1_cnf_param_struct;
+
+
+/* ------------------ *\
+|* G_TEST_COMMAND_2 *|
+\* ------------------ */
+//PDU: ReqPdu, CnfPdu
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_2_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} g_test_command_2_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_2_cnf_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_pdu1;
+ kal_uint16 cnf_pdu2;
+ kal_uint16 cnf_pdu3;
+} g_test_command_2_cnf_pdu_struct;
+
+
+/* ------------------ *\
+|* G_TEST_COMMAND_3 *|
+\* ------------------ */
+//PDU: X, CnfPdu
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_3_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_3_cnf_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_pdu1;
+ kal_uint16 cnf_pdu2;
+ kal_uint16 cnf_pdu3;
+} g_test_command_3_cnf_pdu_struct;
+
+
+/* ------------------ *\
+|* G_TEST_COMMAND_4 *|
+\* ------------------ */
+//PDU: X, X
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_4_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_4_cnf_param_struct;
+
+
+#if IS_2G_RXD_SUPPORT
+/* ---------------------- *\
+|* G_TEST_RFTOOL_SET_PATH *|
+\* ---------------------- */
+//PDU: X, X
+typedef struct
+{
+ FrequencyBand req_band;
+ GSM_AntDimension req_path; //GSM_ANT_MASK_RXM
+} g_test_rftool_set_path_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_ok;
+} g_test_rftool_set_path_cnf_param_struct;
+#endif //#if IS_2G_RXD_SUPPORT
+
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1d_gpt_if_gen97.h b/mcu/interface/l1/gl1/external/l1d_gpt_if_gen97.h
new file mode 100644
index 0000000..795f12b
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_gpt_if_gen97.h
@@ -0,0 +1,635 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * File name:
+ * ---------
+ * l1d_gpt_if.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * WCDMA test mode specific definitions for synchronizing with HOST tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 05 21 2021 yungshian.lai
+ * [MOLY00665438] [Colgin][MT2735][New feature][MD] Wide temperature- NR15.R3.MD700.MP(SWRD) - interface/l1[EWSP0000255811].
+ *
+ * 02 01 2021 yungshian.lai
+ * [MOLY00624719] [Gen97][CO-TMS]Support wide temperature range & 2G wide temperature TX compensation- NR15.R3.MD700.MP.MT2735.DEV(SWRD).
+ *
+ * 10 09 2018 yungshian.lai
+ * [MOLY00349865] TX POWER OFFSET feature uniform - VMOLY Trunk [ERS00016793].
+ *
+ * 09 18 2018 yungshian.lai
+ * [MOLY00349883] [MT6295][2G] NSFT RxLevel Resolution Enhancement- TST part - VMOLY Trunk.
+ *
+ * 03 30 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE option rename & NSFT swap patch.
+ *
+ * 03 07 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE fix UESIM build err & ContRx PCS1900.
+ *
+ * 03 02 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE Trunk TST part.
+ *
+ * 09 01 2017 yungshian.lai
+ * [MOLY00275140] [Bianco] 93 2G Cal Time Reduction Development - UMOLYA.
+ *
+ ****************************************************************************/
+
+#ifndef __L1D_GPT_IF_H__
+#define __L1D_GPT_IF_H__
+
+/*******************************************************************************
+ * Include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "ft_msg_l1rf.h"
+
+
+/*******************************************************************************
+ * Enumeration
+ ******************************************************************************/
+typedef enum
+{
+ g_sinwave_afc_get_temp_freq = RF_TEST_CMD_SINEWAVE_AFC_GET_TEMP_FREQ, // 106
+ g_set_wcoef = RF_TEST_CMD_SET_WCOEF, // 107
+ g_get_wcoef = RF_TEST_CMD_GET_WCOEF, // 108
+ g_test_select_pcs = RF_TEST_CMD_BAND_SEL, // 6
+ g_nbtx_test = RF_TEST_CMD_NB_TX, // 2
+ g_stop = RF_TEST_CMD_STOP, // 7
+ g_afc_test = RF_TEST_CMD_AFC, // 1
+
+#if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT
+ g_set_txdata = RF_TEST_CMD_SET_TXDATA_WIDE_TEMP, // 130
+ g_set_txdata_onemod = RF_TEST_CMD_SET_TXDATA_WIDE_TEMP, // 130
+ g_set_txdata_notxpc = RF_TEST_CMD_SET_TXDATA_WIDE_TEMP, // 130
+ g_set_txdata_orignal = RF_TEST_CMD_SET_TXDATA_WIDE_TEMP, // 130
+
+ g_get_txdata = RF_TEST_CMD_GET_TXDATA_WIDE_TEMP, // 131
+ g_get_txdata_onemod = RF_TEST_CMD_GET_TXDATA_WIDE_TEMP, // 131
+ g_get_txdata_notxpc = RF_TEST_CMD_GET_TXDATA_WIDE_TEMP, // 131
+ g_get_txdata_orignal = RF_TEST_CMD_GET_TXDATA_WIDE_TEMP, // 131
+#else
+ g_set_txdata = RF_TEST_CMD_SET_TXDATA, // 109
+ g_set_txdata_onemod = RF_TEST_CMD_SET_TXDATA, // 109
+ g_set_txdata_notxpc = RF_TEST_CMD_SET_TXDATA, // 109
+ g_set_txdata_orignal = RF_TEST_CMD_SET_TXDATA, // 109
+
+ g_get_txdata = RF_TEST_CMD_GET_TXDATA, // 110
+ g_get_txdata_onemod = RF_TEST_CMD_GET_TXDATA, // 110
+ g_get_txdata_notxpc = RF_TEST_CMD_GET_TXDATA, // 110
+ g_get_txdata_orignal = RF_TEST_CMD_GET_TXDATA, // 110
+#endif
+
+#if IS_2G_RXD_SUPPORT
+ g_get_rxd_info_v5 = RF_TEST_CMD_GET_RXD_INFO_V5, // 113
+
+ g_set_rxdata_all = RF_TEST_CMD_SET_RXDATA_V5, // 114
+ g_set_rxdata_partial = RF_TEST_CMD_SET_RXDATA_V5, // 114
+ g_set_rxdata_orignal = RF_TEST_CMD_SET_RXDATA_V5, // 114
+
+ g_get_rxdata_all = RF_TEST_CMD_GET_RXDATA_V5, // 115
+ g_get_rxdata_partial = RF_TEST_CMD_GET_RXDATA_V5, // 115
+ g_get_rxdata_orignal = RF_TEST_CMD_GET_RXDATA_V5, // 115
+
+ g_rx_gain_calculate = RF_TEST_CMD_RX_GAIN_CALCULATE_V5, // 126
+#endif
+ g_set_rxlev_prcsn = RF_TEST_CMD_SET_NSFT_RXLEV_PRECISION, // 127
+ g_get_tpo_value_v5 = RF_TEST_CMD_GET_TPO_VALUE_V5, // 128
+ g_set_tpo_value_v5 = RF_TEST_CMD_SET_TPO_VALUE_V5, // 129
+
+ g_test_command_1 = RF_TEST_CMD_GP_TOOL_COMMAND_START,
+ g_test_command_2,
+ g_test_command_3,
+ g_test_command_4,
+#if IS_2G_RXD_SUPPORT
+ g_test_rftool_set_path,
+#endif
+ /* --------------- please add new command posterior to this line --------------- */
+
+}ft_rf_test_req_id_cmd_enum_type;
+
+
+/*******************************************************************************
+ * Legacy RF Tool Commands
+ ******************************************************************************/
+
+
+
+/* --------------- please add new command structure posterior to this line --------------- */
+
+/*******************************************************************************
+ * GP RF Tool Commands I (for existing GL1 commands shown on GP tool UI)
+ ******************************************************************************/
+
+/* ---------------------------------------------- *\
+|* RF Test CMD no Req Param *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_uint8 void_param;
+}RfTestCmd_NoParam;
+
+typedef struct
+{
+ kal_uint32 void_result;
+} RfTestCmd_DefaultCnfParam;
+
+
+/* ---------------------------------------------- *\
+|* Use Sinwave AFC Get Freq & Temperature Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdSinewaveAfcGetTempFreq g_sinwave_afc_get_temp_freq_req_param_struct;
+typedef RfTestResultSinewaveAfcGetTempFreq g_sinwave_afc_get_temp_freq_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* AFC Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdAfc g_afc_test_req_param_struct;
+typedef RfTestResultAfc g_afc_test_cnf_param_struct;
+
+
+/* ----------------- *\
+|* SET Wcoef Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_bool is_uplate_to_NVRAM;
+}RfTestCmd_SetWcoef_ReqParam_GpTool;
+
+typedef struct
+{
+ kal_uint8 nvramAccessResult;
+}RfTestCmd_SetGetWcoef_CnfParam_GpTool;
+
+typedef RfTestCmd_SetWcoef_ReqParam_GpTool g_set_wcoef_req_param_struct;
+typedef RfTestCmdSetGetWcoefPdu g_set_wcoef_req_pdu_struct;
+typedef RfTestCmd_SetGetWcoef_CnfParam_GpTool g_set_wcoef_cnf_param_struct;
+//typedef RfTestCmdParam g_set_wcoef_req_param_struct;
+//typedef RfTestResultParam g_set_wcoef_cnf_param_struct;
+
+/* ----------------- *\
+|* GET Wcoef Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmd_NoParam g_get_wcoef_req_param_struct;
+typedef RfTestCmdSetGetWcoefPdu g_get_wcoef_cnf_pdu_struct;
+//typedef RfTestCmd_DefaultCnfParam g_get_wcoef_cnf_param_struct;
+typedef RfTestCmd_SetGetWcoef_CnfParam_GpTool g_get_wcoef_cnf_param_struct;
+
+
+/* ------------------- *\
+|* NBTX select PCS1900 *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_bool selectPCS1900;
+}g_test_select_pcs_req_param_struct;
+
+typedef struct
+{
+ kal_bool ok;
+}g_test_select_pcs_cnf_param_struct;
+
+
+/* ----------------- *\
+|* GET Wcoef Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdNbTx g_nbtx_test_req_param_struct;
+typedef struct
+{
+ kal_bool ok;
+}g_nbtx_test_cnf_param_struct;
+
+
+/* ---- *\
+|* Stop *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_int8 dummy;
+}g_stop_req_param_struct;
+
+typedef struct
+{
+ kal_bool ok;
+}g_stop_cnf_param_struct;
+
+
+/* -------------- *\
+|* SET Tx Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ //L1_RFSpecialCoef_Type4_T type4_rfspecialcoef_pdu;
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdSetTxDataReqPdu_GpTool;
+
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_req_param_struct;
+//typedef RfTestCmdSetTxDataReqPdu g_set_txdata_cnf_pdu_struct;
+typedef RfTestCmdSetTxDataReqPdu_GpTool g_set_txdata_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* SET Tx Command One Modulation *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[4];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[2];
+ L1_Txpc_Type3_T type3_txpc_pdu[1];
+ //L1_RFSpecialCoef_Type4_T type4_rfspecialcoef_pdu;
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdSetTxDataReqPdu_onemod_GpTool;
+
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_onemod_req_param_struct;
+typedef RfTestCmdSetTxDataReqPdu_onemod_GpTool g_set_txdata_onemod_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_onemod_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* SET Tx Command No TXPC *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[5];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[3];
+ //L1_Txpc_Type3_T type3_txpc_pdu[1];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdSetTxDataReqPdu_notxpc_GpTool;
+
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_notxpc_req_param_struct;
+typedef RfTestCmdSetTxDataReqPdu_notxpc_GpTool g_set_txdata_notxpc_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_notxpc_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* SET Tx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdSetTxDataReqParam g_set_txdata_orignal_req_param_struct;
+typedef RfTestCmdSetTxDataReqPdu g_set_txdata_orignal_req_pdu_struct;
+typedef RfTestCmdSetTxDataCnfParam g_set_txdata_orignal_cnf_param_struct;
+
+
+//******************************************************************************************************************//
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdGetTxDataCnfPdu_GpTool; //RfTestCmdGetTxDataCnfPdu
+
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu_GpTool g_get_txdata_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_cnf_param_struct;
+
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command One Modulation *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[4];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[2];
+ L1_Txpc_Type3_T type3_txpc_pdu[1];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdGetTxDataCnfPdu_onemod_GpTool; //RfTestCmdGetTxDataCnfPdu
+
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_onemod_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu_onemod_GpTool g_get_txdata_onemod_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_onemod_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command No TXPC *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_Ramptable_Type1_T type1_ramptable_pdu[5];
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[3];
+ //L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+}RfTestCmdGetTxDataCnfPdu_notxpc_GpTool; //RfTestCmdGetTxDataCnfPdu
+
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_notxpc_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu_notxpc_GpTool g_get_txdata_notxpc_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_notxpc_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* GET Tx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdGetTxDataReqParam g_get_txdata_orignal_req_param_struct;
+typedef RfTestCmdGetTxDataCnfPdu g_get_txdata_orignal_cnf_pdu_struct;
+typedef RfTestCmdGetTxDataCnfParam g_get_txdata_orignal_cnf_param_struct;
+
+
+
+//******************************************************************************************************************//
+
+
+#if IS_2G_RXD_SUPPORT
+/* ---------------------------------------------- *\
+|* GET RXD Info *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_bool ok; //RfTestResultParam
+}RfTestCmdGetRXDInfoCnfParam_GPTool;
+
+typedef RfTestCmd_NoParam g_get_rxd_info_v5_req_param_struct;
+typedef RfTestCmdCalInfoV5AllBandCnfPdu_T g_get_rxd_info_v5_cnf_pdu_struct;
+typedef RfTestCmdGetRXDInfoCnfParam_GPTool g_get_rxd_info_v5_cnf_param_struct;
+
+//******************************************************************************************************************//
+
+
+/* ---------------------------------------------- *\
+|* SET Rx Command all *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+}RfTestCmdSetRxDataReqPdu_GpTool;
+
+typedef RfTestCmdSetRxDataReqParam g_set_rxdata_all_req_param_struct;
+//typedef RfTestCmdSetRxDataReqPdu g_set_rxdata_cnf_pdu_struct;
+typedef RfTestCmdSetRxDataReqPdu_GpTool g_set_rxdata_all_req_pdu_struct;
+typedef RfTestCmdSetRxDataCnfParam g_set_rxdata_all_cnf_param_struct;
+
+
+/* ---------------------------------------------- *\
+|* SET Rx Command RXM or RXD only *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[4];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[1];
+}RfTestCmdSetRxDataReqPdu_partial_GpTool;
+
+typedef RfTestCmdSetRxDataReqParam g_set_rxdata_partial_req_param_struct;
+typedef RfTestCmdSetRxDataReqPdu_partial_GpTool g_set_rxdata_partial_req_pdu_struct;
+typedef RfTestCmdSetRxDataCnfParam g_set_rxdata_partial_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* SET Rx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdSetRxDataReqParam g_set_rxdata_orignal_req_param_struct;
+typedef RfTestCmdSetRxDataReqPdu g_set_rxdata_orignal_req_pdu_struct;
+typedef RfTestCmdSetRxDataCnfParam g_set_rxdata_orignal_cnf_param_struct;
+
+//******************************************************************************************************************//
+
+/* ---------------------------------------------- *\
+|* GET Rx Command All*|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+}RfTestCmdGetRxDataCnfPdu_GpTool; //RfTestCmdGetRxDataCnfPdu
+
+typedef RfTestCmdGetRxDataReqParam g_get_rxdata_all_req_param_struct;
+typedef RfTestCmdGetRxDataCnfPdu_GpTool g_get_rxdata_all_cnf_pdu_struct;
+typedef RfTestCmdGetRxDataCnfParam g_get_rxdata_all_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* GET Rx Command Partial *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ L1_SetGetRxPathLossEntry_Type1_T type1_rxpathloss_pdu[4];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[1];
+}RfTestCmdGetRxDataCnfPdu_partial_GpTool; //RfTestCmdGetRxDataCnfPdu
+
+typedef RfTestCmdGetRxDataReqParam g_get_rxdata_partial_req_param_struct;
+typedef RfTestCmdGetRxDataCnfPdu_partial_GpTool g_get_rxdata_partial_cnf_pdu_struct;
+typedef RfTestCmdGetRxDataCnfParam g_get_rxdata_partial_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* GET Rx Command Orignal *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdGetRxDataReqParam g_get_rxdata_orignal_req_param_struct;
+typedef RfTestCmdGetRxDataCnfPdu g_get_rxdata_orignal_cnf_pdu_struct;
+typedef RfTestCmdGetRxDataCnfParam g_get_rxdata_orignal_cnf_param_struct;
+
+//******************************************************************************************************************//
+
+
+/* ---------------------------------------------- *\
+|* GET Rx Gain Calculate value *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdRxGainCalculate_V5 g_rx_gain_calculate_req_param_struct;
+typedef RfTestResultRxGainCalculate_V5 g_rx_gain_calculate_cnf_param_struct;
+//******************************************************************************************************************//
+#endif //#if IS_2G_RXD_SUPPORT
+
+
+
+/* ---------------------- *\
+|* SET Rx Level Precision *|
+\* ------------------------------------------------------------------------------------ */
+typedef struct
+{
+ kal_uint8 rxlev_precision;
+}g_set_rxlev_prcsn_req_param_struct;
+
+typedef struct
+{
+ kal_bool ok;
+}g_set_rxlev_prcsn_cnf_param_struct;
+
+/* ---------------------------------------------- *\
+|* GET/SET TPO Command *|
+\* ------------------------------------------------------------------------------------ */
+typedef RfTestCmdGetTPO g_get_tpo_value_v5_req_param_struct;
+typedef RfTestResultGetTPO g_get_tpo_value_v5_cnf_param_struct;
+
+typedef RfTestCmdSetTPO g_set_tpo_value_v5_req_param_struct;
+typedef RfTestCmd_NoParam g_set_tpo_value_v5_cnf_param_struct;
+
+
+/*******************************************************************************
+ * GP RF Tool Commands
+ ******************************************************************************/
+
+/* ------------------ *\
+|* G_TEST_COMMAND_1 *|
+\* ------------------ */
+//PDU: ReqPdu, X
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_1_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} g_test_command_1_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_1_cnf_param_struct;
+
+
+/* ------------------ *\
+|* G_TEST_COMMAND_2 *|
+\* ------------------ */
+//PDU: ReqPdu, CnfPdu
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_2_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} g_test_command_2_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_2_cnf_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_pdu1;
+ kal_uint16 cnf_pdu2;
+ kal_uint16 cnf_pdu3;
+} g_test_command_2_cnf_pdu_struct;
+
+
+/* ------------------ *\
+|* G_TEST_COMMAND_3 *|
+\* ------------------ */
+//PDU: X, CnfPdu
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_3_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_3_cnf_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_pdu1;
+ kal_uint16 cnf_pdu2;
+ kal_uint16 cnf_pdu3;
+} g_test_command_3_cnf_pdu_struct;
+
+
+/* ------------------ *\
+|* G_TEST_COMMAND_4 *|
+\* ------------------ */
+//PDU: X, X
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} g_test_command_4_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} g_test_command_4_cnf_param_struct;
+
+
+#if IS_2G_RXD_SUPPORT
+/* ---------------------- *\
+|* G_TEST_RFTOOL_SET_PATH *|
+\* ---------------------- */
+//PDU: X, X
+typedef struct
+{
+ FrequencyBand req_band;
+ GSM_AntDimension req_path; //GSM_ANT_MASK_RXM
+} g_test_rftool_set_path_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_ok;
+} g_test_rftool_set_path_cnf_param_struct;
+#endif //#if IS_2G_RXD_SUPPORT
+
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1d_mipi_data_common.h b/mcu/interface/l1/gl1/external/l1d_mipi_data_common.h
new file mode 100644
index 0000000..0aa2dac
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_mipi_data_common.h
@@ -0,0 +1,150 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_mipi_data_common.h
+ *
+ * Project:
+ * --------
+ * TK6291
+ *
+ * Description:
+ * ------------
+ * Definition of global data & tables used in L1D
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision:
+ * $Modtime:
+ * $Log:
+ *
+ *******************************************************************************/
+
+#ifndef _L1D_MIPI_DATA_COMMON_H_
+#define _L1D_MIPI_DATA_COMMON_H_
+
+#include "l1d_cid.h"
+/*---------------------------------------------------------------------------*/
+
+#if IS_MIPI_SUPPORT
+/* --------------------------------------- */
+/* For 1st MIPI Architecture REsource Plan */
+/* Should not modify this field */
+/* --------------------------------------- */
+/* moved from l1d_mipi_data.h */
+
+#define GGE_MIPI_RTX_EVENT_NUM 13
+#define GGE_MIPI_RTX_DATA_NUM 30
+#define GGE_MIPI_TXMID_EVENT_NUM 2
+#define GGE_MIPI_TXMID_DATA_NUM 3
+#define GGE_MIPI_RTX_EVENT_COUNT 5
+#define GGE_MIPI_TXMID_EVENT_COUNT 4
+#define GGE_MIPI_R2E_EVENT_COUNT 6
+
+#define GGE_MIPI_SUBBAND_NUM 5
+#define GGE_MIPI_SUBBAND_PA_DATA_NUM 3
+#define GGE_MIPI_TXMID_TYPE_NUM 4
+
+/* MIPI Event Type */
+#define GGE_MIPI_EVENT_NULL 0x00
+#define GGE_MIPI_TRX_ON 0x01
+#define GGE_MIPI_TRX_OFF 0x02
+#define GGE_MIPI_TXMID 0x03
+/* MIPI Port Select */
+#if IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define GGE_MIPI_PORT0 0x00
+#define GGE_MIPI_PORT1 0x01
+#define GGE_MIPI_PORT2 0x02
+#define GGE_MIPI_PORT3 0x03
+#define GGE_MIPI_PORT4 0x04
+ #if IS_CHIP_MT6295
+#define GGE_MIPI_PORT5 0x05
+#define GGE_MIPI_DATA_NULL 0x06
+ #else
+#define GGE_MIPI_DATA_NULL 0x05
+ #endif
+#elif IS_CHIP_MT6755 || IS_CHIP_MT6292
+#define GGE_MIPI_PORT0 0x00
+#define GGE_MIPI_PORT1 0x01
+#define GGE_MIPI_PORT2 0x02
+#define GGE_MIPI_PORT3 0x03
+#define GGE_MIPI_DATA_NULL 0x04
+#elif IS_CHIP_TK6291
+/* 0x00 : Device 0 for RFIC */
+/* 0x01 : Device 1 for PMIC */
+#define GGE_MIPI_PORT0 0x02
+#define GGE_MIPI_PORT1 0x03
+#define GGE_MIPI_DATA_NULL 0x04
+#else
+#error "please define the mipi port"
+#endif
+
+/* MIPI Data Sequence Format */
+#define GGE_MIPI_REG_W_NULL 0x00
+#define GGE_MIPI_REG_0_W 0x01
+#define GGE_MIPI_REG_W 0x02
+#define GGE_MIPI_REG_W_EXT_1ST 0x03
+#define GGE_MIPI_REG_W_EXT_BYTE 0x04
+#define GGE_MIPI_WAIT 0x05
+
+/* MIPI Component Type */
+#define GGE_MIPI_NULL 0x00
+#define GGE_MIPI_ASM 0x01
+#define GGE_MIPI_ANT 0x02
+#define GGE_MIPI_PA 0x03
+#define GGE_MIPI_ET 0x04
+#if IS_2G_RXD_SUPPORT
+#define GGE_MIPI_ASM_RXD 0x05
+#endif
+/* MIPI PA G/8 Data */
+#define GGE_MIPI_PA_G8 0x30000000
+
+#define GGE_NULL_ARFCN (-1)
+#define GGE_NULL_PA_DATA (-1)
+//max +ve value of signed short to make it valid for all the ARFCN
+#define GGE_TAS_NO_SPLIT_BAND (32767)
+
+
+#endif /* IS_MIPI_SUPPORT */
+
+/*---------------------------------------------------------------------------*/
+#endif /*End of "#ifndef _L1D_MIPI_DATA_H_" */
+
diff --git a/mcu/interface/l1/gl1/external/l1d_mipi_data_pcore.h b/mcu/interface/l1/gl1/external/l1d_mipi_data_pcore.h
new file mode 100644
index 0000000..2d9039b
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_mipi_data_pcore.h
@@ -0,0 +1,72 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_mipi_data_pcore.h
+ *
+ * Project:
+ * --------
+ * TK6291
+ *
+ * Description:
+ * ------------
+ * Definition of global data & tables used in L1D
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision:
+ * $Modtime:
+ * $Log:
+ *
+ *******************************************************************************/
+
+#ifndef _L1D_MIPI_DATA_PCORE_H_
+#define _L1D_MIPI_DATA_PCORE_H_
+
+/*---------------------------------------------------------------------------*/
+
+#if IS_MIPI_SUPPORT
+
+
+#endif /* IS_MIPI_SUPPORT */
+/*---------------------------------------------------------------------------*/
+#endif /*End of "#ifndef _L1D_MIPI_DATA_H_" */
+
diff --git a/mcu/interface/l1/gl1/external/l1d_mipi_pcore.h b/mcu/interface/l1/gl1/external/l1d_mipi_pcore.h
new file mode 100644
index 0000000..1e47dc6
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_mipi_pcore.h
@@ -0,0 +1,261 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_mipi_pcore.h
+ *
+ * Project:
+ * --------
+ * TK6291
+ *
+ * Description:
+ * ------------
+ * MIPI constance defintion
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision:
+ * $Modtime:
+ * $Log:
+ *
+ *******************************************************************************/
+
+#ifndef _L1D_MIPI_PCORE_H_
+#define _L1D_MIPI_PCORE_H_
+/*============================================================================== */
+
+ #if IS_MIPI_SUPPORT
+
+#ifndef QB_MIPI_RX_ON0
+#define QB_MIPI_RX_ON0 (-10000)
+#endif
+#ifndef QB_MIPI_RX_ON1
+#define QB_MIPI_RX_ON1 (-10000)
+#endif
+#ifndef QB_MIPI_RX_ON2
+#define QB_MIPI_RX_ON2 (-10000)
+#endif
+#ifndef QB_MIPI_RX_ON3
+#define QB_MIPI_RX_ON3 (-10000)
+#endif
+#ifndef QB_MIPI_RX_ON4
+#define QB_MIPI_RX_ON4 (-10000)
+#endif
+#ifndef QB_MIPI_RX_ON5
+#define QB_MIPI_RX_ON5 (-10000)
+#endif
+#ifndef QB_MIPI_RX_ON6
+#define QB_MIPI_RX_ON6 (-10000)
+#endif
+#ifndef QB_MIPI_RX_ON7
+#define QB_MIPI_RX_ON7 (-10000)
+#endif
+#ifndef QB_MIPI_RX_OFF0
+#define QB_MIPI_RX_OFF0 (10000)
+#endif
+#ifndef QB_MIPI_RX_OFF1
+#define QB_MIPI_RX_OFF1 (10000)
+#endif
+#ifndef QB_MIPI_RX_OFF2
+#define QB_MIPI_RX_OFF2 (10000)
+#endif
+#ifndef QB_MIPI_RX_OFF3
+#define QB_MIPI_RX_OFF3 (10000)
+#endif
+#ifndef QB_MIPI_RX_OFF4
+#define QB_MIPI_RX_OFF4 (10000)
+#endif
+
+#ifndef QB_MIPI_TX_ON0
+#define QB_MIPI_TX_ON0 (-10000)
+#endif
+#ifndef QB_MIPI_TX_ON1
+#define QB_MIPI_TX_ON1 (-10000)
+#endif
+#ifndef QB_MIPI_TX_ON2
+#define QB_MIPI_TX_ON2 (-10000)
+#endif
+#ifndef QB_MIPI_TX_ON3
+#define QB_MIPI_TX_ON3 (-10000)
+#endif
+#ifndef QB_MIPI_TX_ON4
+#define QB_MIPI_TX_ON4 (-10000)
+#endif
+#ifndef QB_MIPI_TX_ON5
+#define QB_MIPI_TX_ON5 (-10000)
+#endif
+#ifndef QB_MIPI_TX_ON6
+#define QB_MIPI_TX_ON6 (-10000)
+#endif
+#ifndef QB_MIPI_TX_ON7
+#define QB_MIPI_TX_ON7 (-10000)
+#endif
+#ifndef QB_MIPI_TX_OFF0
+#define QB_MIPI_TX_OFF0 (10000)
+#endif
+#ifndef QB_MIPI_TX_OFF1
+#define QB_MIPI_TX_OFF1 (10000)
+#endif
+#ifndef QB_MIPI_TX_OFF2
+#define QB_MIPI_TX_OFF2 (10000)
+#endif
+#ifndef QB_MIPI_TX_OFF3
+#define QB_MIPI_TX_OFF3 (10000)
+#endif
+#ifndef QB_MIPI_TX_OFF4
+#define QB_MIPI_TX_OFF4 (10000)
+#endif
+
+#ifndef QB_MIPI_TXMID0
+#define QB_MIPI_TXMID0 (-10000)
+#endif
+#ifndef QB_MIPI_TXMID1
+#define QB_MIPI_TXMID1 (-10000)
+#endif
+
+#define TQ_MIPI_RX_ON0 (QB_MIPI_RX_ON0-QB_RON_2_FSYNC)
+#define TQ_MIPI_RX_ON1 (QB_MIPI_RX_ON1-QB_RON_2_FSYNC)
+#define TQ_MIPI_RX_ON2 (QB_MIPI_RX_ON2-QB_RON_2_FSYNC)
+#define TQ_MIPI_RX_ON3 (QB_MIPI_RX_ON3-QB_RON_2_FSYNC)
+#define TQ_MIPI_RX_ON4 (QB_MIPI_RX_ON4-QB_RON_2_FSYNC)
+#define TQ_MIPI_RX_ON5 (QB_MIPI_RX_ON5-QB_RON_2_FSYNC)
+#define TQ_MIPI_RX_ON6 (QB_MIPI_RX_ON6-QB_RON_2_FSYNC)
+#define TQ_MIPI_RX_ON7 (QB_MIPI_RX_ON7-QB_RON_2_FSYNC)
+
+#define TQ_MIPI_RX_OFF0 (QB_MIPI_RX_OFF0-QB_FSYNC_2_ROFF)
+#define TQ_MIPI_RX_OFF1 (QB_MIPI_RX_OFF1-QB_FSYNC_2_ROFF)
+#define TQ_MIPI_RX_OFF2 (QB_MIPI_RX_OFF2-QB_FSYNC_2_ROFF)
+#define TQ_MIPI_RX_OFF3 (QB_MIPI_RX_OFF3-QB_FSYNC_2_ROFF)
+#define TQ_MIPI_RX_OFF4 (QB_MIPI_RX_OFF4-QB_FSYNC_2_ROFF)
+
+#define TQ_MIPI_TX_ON0 (QB_MIPI_TX_ON0-QB_TON_2_FSYNC)
+#define TQ_MIPI_TX_ON1 (QB_MIPI_TX_ON1-QB_TON_2_FSYNC)
+#define TQ_MIPI_TX_ON2 (QB_MIPI_TX_ON2-QB_TON_2_FSYNC)
+#define TQ_MIPI_TX_ON3 (QB_MIPI_TX_ON3-QB_TON_2_FSYNC)
+#define TQ_MIPI_TX_ON4 (QB_MIPI_TX_ON4-QB_TON_2_FSYNC)
+#define TQ_MIPI_TX_ON5 (QB_MIPI_TX_ON5-QB_TON_2_FSYNC)
+#define TQ_MIPI_TX_ON6 (QB_MIPI_TX_ON6-QB_TON_2_FSYNC)
+#define TQ_MIPI_TX_ON7 (QB_MIPI_TX_ON7-QB_TON_2_FSYNC)
+
+#define TQ_MIPI_TX_OFF0 (QB_MIPI_TX_OFF0-QB_FSYNC_2_TOFF)
+#define TQ_MIPI_TX_OFF1 (QB_MIPI_TX_OFF1-QB_FSYNC_2_TOFF)
+#define TQ_MIPI_TX_OFF2 (QB_MIPI_TX_OFF2-QB_FSYNC_2_TOFF)
+#define TQ_MIPI_TX_OFF3 (QB_MIPI_TX_OFF3-QB_FSYNC_2_TOFF)
+#define TQ_MIPI_TX_OFF4 (QB_MIPI_TX_OFF4-QB_FSYNC_2_TOFF)
+
+#if 0
+ #if !defined(QB_PR3) || !defined(QB_SR3)
+/* under construction !*/
+ #elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+ #if TQ_PR3A>TQ_SR3 && TQ_PR3A>TQ_PR3 && TQ_PR3A>TQ_MIPI_RX_OFF0 && TQ_PR3A>TQ_MIPI_RX_OFF1 && \
+ TQ_PR3A>TQ_MIPI_RX_OFF2 && TQ_PR3A>TQ_MIPI_RX_OFF3 && TQ_PR3A>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #elif TQ_PR3 >TQ_SR3 && TQ_PR3>TQ_PR3A && TQ_PR3>TQ_MIPI_RX_OFF0 && TQ_PR3>TQ_MIPI_RX_OFF1 && \
+ TQ_PR3>TQ_MIPI_RX_OFF2 && TQ_PR3>TQ_MIPI_RX_OFF3 && TQ_PR3>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #elif TQ_SR3 >TQ_PR3 && TQ_SR3>TQ_PR3A && TQ_SR3>TQ_MIPI_RX_OFF0 && TQ_SR3>TQ_MIPI_RX_OFF1 && \
+ TQ_SR3>TQ_MIPI_RX_OFF2 && TQ_SR3>TQ_MIPI_RX_OFF3 && TQ_SR3>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #elif TQ_MIPI_RX_OFF0>TQ_PR3 && TQ_MIPI_RX_OFF0>TQ_PR3A && TQ_MIPI_RX_OFF0>TQ_SR3 && TQ_MIPI_RX_OFF0>TQ_MIPI_RX_OFF1 && \
+ TQ_MIPI_RX_OFF0>TQ_MIPI_RX_OFF2 && TQ_MIPI_RX_OFF0>TQ_MIPI_RX_OFF3 && TQ_MIPI_RX_OFF0>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #elif TQ_MIPI_RX_OFF1>TQ_PR3 && TQ_MIPI_RX_OFF1>TQ_PR3A && TQ_MIPI_RX_OFF1>TQ_SR3 && TQ_MIPI_RX_OFF1>TQ_MIPI_RX_OFF0 && \
+ TQ_MIPI_RX_OFF1>TQ_MIPI_RX_OFF2 && TQ_MIPI_RX_OFF1>TQ_MIPI_RX_OFF3 && TQ_MIPI_RX_OFF1>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #elif TQ_MIPI_RX_OFF2>TQ_PR3 && TQ_MIPI_RX_OFF2>TQ_PR3A && TQ_MIPI_RX_OFF2>TQ_SR3 && TQ_MIPI_RX_OFF2>TQ_MIPI_RX_OFF0 && \
+ TQ_MIPI_RX_OFF2>TQ_MIPI_RX_OFF1 && TQ_MIPI_RX_OFF2>TQ_MIPI_RX_OFF3 && TQ_MIPI_RX_OFF2>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #elif TQ_MIPI_RX_OFF3>TQ_PR3 && TQ_MIPI_RX_OFF3>TQ_PR3A && TQ_MIPI_RX_OFF3>TQ_SR3 && TQ_MIPI_RX_OFF3>TQ_MIPI_RX_OFF0 && \
+ TQ_MIPI_RX_OFF3>TQ_MIPI_RX_OFF1 && TQ_MIPI_RX_OFF3>TQ_MIPI_RX_OFF2 && TQ_MIPI_RX_OFF3>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #else
+/* under construction !*/
+/* under construction !*/
+ #endif
+ #else
+ #if TQ_PR3 >TQ_SR3 && TQ_PR3>TQ_MIPI_RX_OFF0 && TQ_PR3>TQ_MIPI_RX_OFF1 && \
+ TQ_PR3>TQ_MIPI_RX_OFF2 && TQ_PR3>TQ_MIPI_RX_OFF3 && TQ_PR3>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #elif TQ_SR3 >TQ_PR3 && TQ_SR3>TQ_MIPI_RX_OFF0 && TQ_SR3>TQ_MIPI_RX_OFF1 && \
+ TQ_SR3>TQ_MIPI_RX_OFF2 && TQ_SR3>TQ_MIPI_RX_OFF3 && TQ_SR3>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #elif TQ_MIPI_RX_OFF0>TQ_PR3 && TQ_MIPI_RX_OFF0>TQ_SR3 && TQ_MIPI_RX_OFF0>TQ_MIPI_RX_OFF1 && \
+ TQ_MIPI_RX_OFF0>TQ_MIPI_RX_OFF2 && TQ_MIPI_RX_OFF0>TQ_MIPI_RX_OFF3 && TQ_MIPI_RX_OFF0>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #elif TQ_MIPI_RX_OFF1>TQ_PR3 && TQ_MIPI_RX_OFF1>TQ_SR3 && TQ_MIPI_RX_OFF1>TQ_MIPI_RX_OFF0 && \
+ TQ_MIPI_RX_OFF1>TQ_MIPI_RX_OFF2 && TQ_MIPI_RX_OFF1>TQ_MIPI_RX_OFF3 && TQ_MIPI_RX_OFF1>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #elif TQ_MIPI_RX_OFF2>TQ_PR3 && TQ_MIPI_RX_OFF2>TQ_SR3 && TQ_MIPI_RX_OFF2>TQ_MIPI_RX_OFF0 && \
+ TQ_MIPI_RX_OFF2>TQ_MIPI_RX_OFF1 && TQ_MIPI_RX_OFF2>TQ_MIPI_RX_OFF3 && TQ_MIPI_RX_OFF2>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #elif TQ_MIPI_RX_OFF3>TQ_PR3 && TQ_MIPI_RX_OFF3>TQ_SR3 && TQ_MIPI_RX_OFF3>TQ_MIPI_RX_OFF0 && \
+ TQ_MIPI_RX_OFF3>TQ_MIPI_RX_OFF1 && TQ_MIPI_RX_OFF3>TQ_MIPI_RX_OFF2 && TQ_MIPI_RX_OFF3>TQ_MIPI_RX_OFF4
+/* under construction !*/
+/* under construction !*/
+ #else
+/* under construction !*/
+/* under construction !*/
+ #endif
+ #endif
+#endif
+/*============================================================================== */
+
+#ifdef L1_SIM
+#undef QB_MIPI_RX_OFF0
+#define QB_MIPI_RX_OFF0 6 /* MIPI OFF timing reduncing timing in Simulation only */
+#endif
+
+#endif /*IS_MIPI_SUPPORT*/
+
+#endif /*End of "#ifndef _L1D_MIPI_PCORE_H_" */
+
diff --git a/mcu/interface/l1/gl1/external/l1d_public.h b/mcu/interface/l1/gl1/external/l1d_public.h
new file mode 100644
index 0000000..a3d3084
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_public.h
@@ -0,0 +1,382 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_public.h
+ *
+ * Project:
+ * --------
+ * TK6291 Project
+ *
+ * Description:
+ * ------------
+ * The structure definition of L1 calibration data
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef L1D_PUBLIC_H
+#define L1D_PUBLIC_H
+
+#include "l1d_cid.h"
+#include "l1cal.h"
+#include "l1d_rf_common.h"
+#include "l1_types_public.h"
+
+
+/* ------------------------------------------------------------------------- */
+
+/* moved from l1d_data_l1core.h */
+#if IS_AST_B2S_SUPPORT
+#define TQ_AFC_READY 245
+#define TQ_AFC_READY_RX 213
+#else
+#define TQ_AFC_READY 256
+#define TQ_AFC_READY_RX TQ_AFC_READY
+#endif
+
+#if L1D_PM_ENHANCE
+#define TQ_PM_WIN_OFF_MARGIN 8
+#endif
+
+/* ------------------------------------------------------------------------- */
+/* moved from l1d_custom_rf.h */
+#define SECONDS2FRAME(n) ((int)((n)*1000000/4615))
+#define VOLT2UVOLT(n) ((int)((n)*1000000))
+#define TEMP2MTEMP(n) ((int)((n)*1000))
+
+/* ------------------------------------------------------------------------- */
+ /* !!important: please align the setting in L1_const.h */
+#define RSSI_RESOLUTION_BITS 3 /* 0.125 dB resolution */
+#define RSSI_FACTOR (1<<RSSI_RESOLUTION_BITS)
+
+// moved from m12190_l1core.h
+#ifndef _L1D_DATA_L1CORE_H_
+#define PWRRES_BIT RSSI_RESOLUTION_BITS
+#define PWRRES RSSI_FACTOR
+#endif
+
+#define PWROFFSET(n) ((signed char)((n)*(1<<2))) /* rx power offset resolution = 0.25 dB */
+#define GAINLOSS( n ) ((signed char)((n)*PWRRES))
+#define WEIGHT(n) ((unsigned short)((n)*(1<<14)))
+#define TABLE_END (unsigned short)0xFFFF
+/* ------------------------------------------------------------------------- */
+/* moved from m12197_l1core.h */
+#define RFDEF 0xABCD
+#define RFDEF_short 0xAB
+
+/* ------------------------------------------------------------------------- */
+
+extern intx afc_inv_slope;
+
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+extern int32 afc_dac_default;
+extern const int32 afc_dac_initial;
+#else
+extern int16 afc_dac_default;
+
+extern const int16 afc_dac_initial;
+#endif /* IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT */
+
+extern long XO_CapID;
+
+extern sAGCGAINOFFSET* AGC_PATHLOSS_TABLE[FrequencyBandCount];
+
+extern sLNAGAINOFFSET* LNA_PATHLOSS_TABLE[FrequencyBandCount];
+
+#if IS_2G_RXD_SUPPORT
+extern sAGCGAINOFFSET* AGC_PATHLOSS_RXD_TABLE[FrequencyBandCount];
+
+extern sLNAGAINOFFSET* LNA_PATHLOSS_RXD_TABLE[FrequencyBandCount];
+extern L1D_CUSTOM_RAS_NVRAM_T L1_RAS_Custom_NVRAM;
+#endif
+
+extern sRAMPDATA* RampData[FrequencyBandCount];
+
+#if IS_EPSK_TX_SUPPORT
+extern sRAMPDATA* RampData_EPSK[FrequencyBandCount];
+#endif
+
+extern sMIDRAMPDATA* InterRampData[FrequencyBandCount];
+
+#if IS_EPSK_TX_SUPPORT
+extern sMIDRAMPDATA** EPSK_InterRampData[5];
+#endif
+
+extern sBBTXParameters BBTXParameters;
+
+#if IS_GPRS
+extern sTX_POWER_ROLLBACK* tx_power_rollback_gmsk[FrequencyBandCount];
+ #if IS_EGPRS
+extern sTX_POWER_ROLLBACK* tx_power_rollback_epsk[FrequencyBandCount];
+ #endif
+#endif
+
+#if IS_TX_POWER_CONTROL_SUPPORT
+extern char is_txpc_calibrated;
+ #if IS_TXPC_CL_AUXADC_SUPPORT || IS_TXPC_CL_BSI_SUPPORT
+extern sTXPC_ADCDATA* TXADC_Data[FrequencyBandCount];
+extern sTXPC_TEMPDATA* TXTEMP_Data[FrequencyBandCount];
+ #if IS_EPSK_TX_SUPPORT
+extern sTXPC_ADCDATA* TXADC_Data_EPSK[FrequencyBandCount];
+extern sTXPC_TEMPDATA* TXTEMP_Data_EPSK[FrequencyBandCount];
+ #endif
+ #endif /* IS_TXPC_CL_AUXADC_SUPPORT || IS_TXPC_CL_BSI_SUPPORT */
+ #if IS_TXPC_OL_BSI_SUPPORT || IS_TXPC_OL_AUXADC_SUPPORT
+extern short ref_temperature;
+ #endif
+#endif /* IS_TX_POWER_CONTROL_SUPPORT */
+
+extern sTXPC_TEMPDATA TEMP_DAC;
+
+#if IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2
+extern sL1D_RF_CUSTOM_INPUT_DATA l1d_rf_custom_input_data;
+#endif
+
+extern sTXGAIN_RFDATA* GAIN_RF_TABLE[FrequencyBandCount];
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+//none
+#elif IS_MIPI_SUPPORT
+ #if IS_2G_TAS_SUPPORT
+extern sGGE_TAS_MIPI_RTXCTRL_TABLE* GGE_TAS_MIPI_CTRL_TABLE[FrequencyBandCount][L1D_TAS_STATE_NUM];
+ #endif
+
+ #if IS_2G_DAT_SUPPORT
+extern sGGE_DAT_MIPI_RTXCTRL_TABLE* GGE_DAT_MIPI_CTRL_TABLE[FrequencyBandCount][L1D_DAT_STATE_NUM];
+ #endif
+
+extern sGGE_MIPI_CTRL_TABLE_BAND* GGE_MIPI_CTRL_TABLE[FrequencyBandCount];
+extern sGGE_MIPIEVENT* GGE_MIPI_CTRL_TABLE_RX_EVENT[FrequencyBandCount];
+extern sGGE_MIPIEVENT* GGE_MIPI_CTRL_TABLE_TX_EVENT[FrequencyBandCount];
+extern sGGE_MIPIEVENT* GGE_MIPI_CTRL_TABLE_TXMID_EVENT[FrequencyBandCount];
+extern sGGE_MIPIDATA_SUBBAND* GGE_MIPI_CTRL_TABLE_RX_DATA[FrequencyBandCount];
+extern sGGE_MIPIDATA_SUBBAND* GGE_MIPI_CTRL_TABLE_TX_DATA[FrequencyBandCount];
+extern sGGE_MIPIPADATA* GGE_MIPI_CTRL_TABLE_PA_DATA[FrequencyBandCount];
+extern sGGE_MIPIDATA_SUBBAND* GGE_MIPI_CTRL_TABLE_TXMID_DATA[FrequencyBandCount];
+#endif
+
+#if IS_TX_POWER_OFFSET_SUPPORT
+
+extern sTX_POWER_OFFSET* Tx_Power_Offset_GMSK[FrequencyBandCount];
+extern sTX_POWER_OFFSET* Tx_Power_Offset_EPSK[FrequencyBandCount];
+#endif
+
+#if IS_RX_POWER_OFFSET_SUPPORT
+extern s2G_RF_RX_PARAMETER_EXT* AGCLNA_PL_OFFSET_SETTING;
+extern sAGCLNAGAINOFFSET* AGCLNA_PATHLOSS_OFFSET[FrequencyBandCount];
+ #if IS_2G_RXD_SUPPORT
+extern sAGCLNAGAINOFFSET* AGCLNA_PATHLOSS_RXD_OFFSET[FrequencyBandCount];
+ #endif
+#endif/*IS_RX_POWER_OFFSET_SUPPORT*/
+
+#if IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT
+extern sNSFT_ADJUST_TPO* Adjust_TPO_GMSK[FrequencyBandCount];
+ #if IS_EPSK_ADJUST_TPO_SUPPORT
+extern sNSFT_ADJUST_TPO* Adjust_TPO_EPSK[FrequencyBandCount];
+ #endif//IS_EPSK_ADJUST_TPO_SUPPORT
+#endif//IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT
+
+#if (IS_2G_TAS_SUPPORT || IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT)
+extern L1D_CUSTOM_TAS_NVRAM_T L1_TAS_Custom_NVRAM;
+ #if IS_2G_TAS_SUPPORT || IS_2G_Gen95_UTAS_SUPPORT /*Not supported for Gen97*/
+extern L1D_CUSTOM_TAS_FE_NVRAM_T L1_TAS_Custom_FE_NVRAM;
+ #endif
+ #if (IS_2G_TAS_INHERIT_4G_ANT)
+extern L1D_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T L1_TAS_Custom_InheritLteAntTable;
+ #endif
+#endif
+
+#if IS_2G_DAT_SUPPORT || IS_2G_Gen95_UDAT_SUPPORT || IS_2G_Gen97_UDAT_SUPPORT
+extern L1D_CUSTOM_DAT_FE_ROUTE_NVRAM_T L1_DAT_Custom_FE_ROUTE_NVRAM;
+ #if IS_2G_DAT_SUPPORT
+extern L1D_CUSTOM_DAT_FE_CAT_A_NVRAM_T L1_DAT_Custom_FE_CAT_A_NVRAM;
+extern L1D_CUSTOM_DAT_FE_CAT_B_NVRAM_T L1_DAT_Custom_FE_CAT_B_NVRAM;
+ #endif
+#endif
+
+#if IS_ANT_RXPWR_OFFSET_SUPPORT
+extern sL1D_ANT_RxPWR_Offset_T L1D_ANT_RxPWR_Offset_NVRAM;
+#endif
+
+#if IS_2G_DYNAMIC_HW_CLOCK_SUPPORT
+extern L1D_RF_INTERFERENCE_ARFCN_INDICATION_T L1_Custom_HW_CLK_NVRAM;
+#endif
+
+extern sl1CustomBandSupport l1d_custom_band_support;
+
+#if IS_SAR_TX_POWER_BACKOFF_SUPPORT
+extern L1D_CUSTOM_SAR_TX_BACKOFF_DB_NVRAM_T L1_Custom_SAR_TX_BACKOFF_DB_NVRAM;
+#endif
+
+/* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
+#endif /* End of L1D_PUBLIC_H */
diff --git a/mcu/interface/l1/gl1/external/l1d_rf_common.h b/mcu/interface/l1/gl1/external/l1d_rf_common.h
new file mode 100644
index 0000000..bd7ba6c
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_rf_common.h
@@ -0,0 +1,1031 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_rf_common.h
+ *
+ * Project:
+ * --------
+ * TK6291
+ *
+ * Description:
+ * ------------
+ * CC RF constance defintion
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
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+ * removed!
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+ *
+ * removed!
+ * removed!
+ * removed!
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+ *
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+ * removed!
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+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _L1D_RF_COMMON_H_
+#define _L1D_RF_COMMON_H_
+#include "l1d_cid.h"
+#include "l1cal.h"
+#include "l1d_public.h"
+/* ------------------------------------------------------------------------- */
+#if IS_TXPC_CL_AUXADC_SUPPORT || IS_TXPC_CL_BSI_SUPPORT
+void L1D_RF_TXPC_CL_GetAllADC( sTXPC_L1CAL *buff, char is_EPSK );
+void L1D_RF_TXPC_CL_GetAllTEMP( sTXPC_L1CAL *buff, char is_EPSK );
+#endif
+
+
+/* To prevent abnormal BAND_SUPPORT upgrade in project make file for partial-source load */
+#ifdef __GSM450__
+#define l1d_support_band400 FrequencyBand400
+#endif
+
+#ifdef __GSM850__
+#define l1d_support_band850 FrequencyBand850
+#endif
+
+#if defined(__PGSM900__)||defined(__EGSM900__)||defined(__RGSM900__)
+#define l1d_support_band900 FrequencyBand900
+#endif
+
+#ifdef __DCS1800__
+#define l1d_support_band1800 FrequencyBand1800
+#endif
+
+#ifdef __PCS1900__
+#define l1d_support_band1900 FrequencyBand1900
+#endif
+/* To prevent abnormal BAND_SUPPORT upgrade in project make file for partial-source load */
+
+
+/* ------------------------------------------------------------------------- */
+/*==========================*/ /*========================*/
+/* BBRX_GAIN_DOUBLE */ /* BBTX_CALBIAS */
+/*--------------------------*/ /*------------------------*/
+/* 0: mapping range = 2.24V */ /* N= 0..+15 : 1.038^N */
+/* 1: mapping range = 1.12V */ /* N=-1..-16 : 0.918^(-N) */
+/*==========================*/ /*========================*/
+/*==========================*/ /*========================*/
+/* BBTX_COMMON_MODE_VOLTAGE */ /* BBTX_CALRCSEL */
+/*--------------------------*/ /*------------------------*/
+/* Set | Volt || Set | Volt */ /* Set | BW || Set | BW */
+/*-----+------||-----+------*/ /*-----+-----||-----+-----*/
+/* 3 | 1.75 || -1 | 1.29 */ /* 3 | 213 || -1 | 394 */
+/* 2 | 1.62 || -2 | 1.18 */ /* 2 | 245 || -2 | 450 */
+/* 1 | 1.51 || -3 | 1.06 */ /* 1 | 289 || -3 | 520 */
+/* 0 | 1.40 || -4 | 0.95 */ /* 0 | 350 || -4 | 620 */
+/*==========================*/ /*========================*/
+/*==========================*/ /*========================*/
+/* BBTX_TRIM_I */ /* BBTX_OFFSET_I */
+/* BBTX_TRIM_Q */ /* BBTX_OFFSET_Q */
+/*--------------------------*/ /*------------------------*/
+/* N= -8...+7 : 0.16N dB */ /* N=-32...+31: 2.737N mV */
+/*==========================*/ /*========================*/
+/*========================================================*/
+/* BBTX_GAIN */
+/* --+---------+---------------+------------+-------------*/
+/* S | FPGA | | | */
+/* e | MT6208 | MT6205B | MT6218B_EN | MT6218B_FN~ */
+/* t | MT6205A | MT6218B_AN~DN | MT6219AV | MT6219_BV */
+/* | MT6218A | | | */
+/*---+---------+---------------+------------+-------------*/
+/* 3 | 2.52V | 1.48V | 0.93V | 1.50V */
+/* 2 | 2.01V | 1.37V | 0.87V | 1.42V */
+/* 1 | 1.62V | 1.29V | 0.81V | 1.36V */
+/* 0 | 1.26V | 1.15V | 0.76V | 1.19V */
+/*-1 | 1.00V | 1.06V | 0.71V | 1.12V */
+/*-2 | 0.81V | 1.00V | 0.66V | 1.05V */
+/*-3 | 0.64V | 0.92V | 0.62V | 1.00V */
+/*-4 | 0.50V | 0.87V | 0.58V | 0.93V */
+/*========================================================*/
+/* ------------------------------------------------------------------------- */
+//#define CLK32K_MICRO_SECOND(n) ((int)(n*32.0/1000))
+/* ------------------------------------------------------------------------- */
+
+#if IS_RF_MT6280RF
+/*MT6280RF*/ /*--------------------------------------------------------*/
+/*MT6280RF*/ /* BFE Legacy Setting (no use) */
+/*MT6280RF*/ /*--------------------------------------------------------*/
+/*MT6280RF*/ #define BBRX_GAIN_DOUBLE 0
+/*MT6280RF*/ #define BBTX_IQ_SWAP 0
+/*MT6280RF*/ #define BBTX_CALBIAS 0
+/*MT6280RF*/ #define BBTX_CALRCSEL 0
+/*MT6280RF*/ #define BBTX_CALRCSEL_H 0
+/*MT6280RF*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6280RF*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6280RF*/ #define BBTX_TRIM_I 0 // wait calibration
+/*MT6280RF*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*MT6280RF*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*MT6280RF*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*MT6280RF*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*MT6280RF*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*MT6280RF*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*MT6280RF*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*MT6280RF*/ #define BBTX_PHSEL 0 // wait calibration
+/*MT6280RF*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*MT6280RF*/ #define BBTX_COARSGAIN 0
+/*MT6280RF*/ #define BBTX_GAIN 0 // get from experiment
+/*MT6280RF*/ #define BBTX_GAIN_H 0 // get from experiment
+/*MT6280RF*/ #define BBTX_GAIN_SWING 900 /* mV */
+/*MT6280RF*/
+/*MT6280RF*/ /*--------------------------------------------------------*/
+/*MT6280RF*/ /* Define band mode mapped receiver type */
+/*MT6280RF*/ /* DO NOT MODIFY the definitions here. */
+/*MT6280RF*/ /*--------------------------------------------------------*/
+/*MT6280RF*/ #define RX_MAIN_PATH_OFF 0x0
+/*MT6280RF*/ #define LNA_1 0x1
+/*MT6280RF*/ #define LNA_2 0x2
+/*MT6280RF*/ #define LNA_3 0x3
+/*MT6280RF*/ #define LNA_4 0x4
+/*MT6280RF*/ #define LNA_5 0x5
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_MT6169
+/*MT6169*/ /*--------------------------------------------------------*/
+/*MT6169*/ /* BFE Legacy Setting (no use) */
+/*MT6169*/ /*--------------------------------------------------------*/
+/*MT6169*/ #define BBRX_GAIN_DOUBLE 0
+/*MT6169*/ #define BBTX_IQ_SWAP 0
+/*MT6169*/ #define BBTX_CALBIAS 0
+/*MT6169*/ #define BBTX_CALRCSEL 0
+/*MT6169*/ #define BBTX_CALRCSEL_H 0
+/*MT6169*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6169*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6169*/ #define BBTX_TRIM_I 0 // wait calibration
+/*MT6169*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*MT6169*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*MT6169*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*MT6169*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*MT6169*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*MT6169*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*MT6169*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*MT6169*/ #define BBTX_PHSEL 0 // wait calibration
+/*MT6169*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*MT6169*/ #define BBTX_COARSGAIN 0
+/*MT6169*/ #define BBTX_GAIN 0 // get from experiment
+/*MT6169*/ #define BBTX_GAIN_H 0 // get from experiment
+/*MT6169*/ #define BBTX_GAIN_SWING 900 /* mV */
+/*MT6169*/
+/*MT6169*/ /*--------------------------------------------------------*/
+/*MT6169*/ /* Define band mode mapped receiver type */
+/*MT6169*/ /* DO NOT MODIFY the definitions here. */
+/*MT6169*/ /*--------------------------------------------------------*/
+/*MT6169*/ #define IORX_HB1 0x0
+/*MT6169*/ #define IORX_HB2 0x1
+/*MT6169*/ #define IORX_HB3 0x2
+/*MT6169*/ #define IORX_MB1 0x3
+/*MT6169*/ #define IORX_MB2 0x4
+/*MT6169*/ #define IORX_LB1 0x5
+/*MT6169*/ #define IORX_LB2 0x6
+/*MT6169*/ #define IORX_LB3 0x7
+/*MT6169*/
+/*MT6169*/ /*--------------------------------------------------------*/
+/*MT6169*/ /* Define band mode mapped receiver type */
+/*MT6169*/ /* DO NOT MODIFY the definitions here. */
+/*MT6169*/ /*--------------------------------------------------------*/
+/*MT6169*/ #define IOTX_HB1 0x0
+/*MT6169*/ #define IOTX_HB2 0x1
+/*MT6169*/ #define IOTX_MB1 0x2
+/*MT6169*/ #define IOTX_MB2 0x3
+/*MT6169*/ #define IOTX_LB1 0x4
+/*MT6169*/ #define IOTX_LB2 0x5
+/*MT6169*/ #define IOTX_LB3 0x6
+/*MT6169*/ #define IOTX_LB4 0x7
+/*MT6169*/
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_MT6166
+/*MT6166*/ /*--------------------------------------------------------*/
+/*MT6166*/ /* BFE Legacy Setting (no use) */
+/*MT6166*/ /*--------------------------------------------------------*/
+/*MT6166*/ #define BBRX_GAIN_DOUBLE 0
+/*MT6166*/ #define BBTX_IQ_SWAP 0
+/*MT6166*/ #define BBTX_CALBIAS 0
+/*MT6166*/ #define BBTX_CALRCSEL 0
+/*MT6166*/ #define BBTX_CALRCSEL_H 0
+/*MT6166*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6166*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6166*/ #define BBTX_TRIM_I 0 // wait calibration
+/*MT6166*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*MT6166*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*MT6166*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*MT6166*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*MT6166*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*MT6166*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*MT6166*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*MT6166*/ #define BBTX_PHSEL 0 // wait calibration
+/*MT6166*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*MT6166*/ #define BBTX_COARSGAIN 0
+/*MT6166*/ #define BBTX_GAIN 0 // get from experiment
+/*MT6166*/ #define BBTX_GAIN_H 0 // get from experiment
+/*MT6166*/ #define BBTX_GAIN_SWING 900 /* mV */
+/*MT6166*/
+/*MT6166*/ /*--------------------------------------------------------*/
+/*MT6166*/ /* Define band mode mapped receiver type */
+/*MT6166*/ /* DO NOT MODIFY the definitions here. */
+/*MT6166*/ /*--------------------------------------------------------*/
+/*MT6166*/ #define RX_MAIN_PATH_OFF 0x0
+/*MT6166*/ #define LNA_1 0x1
+/*MT6166*/ #define LNA_2 0x2
+/*MT6166*/ #define LNA_3 0x3
+/*MT6166*/ #define LNA_4 0x4
+/*MT6166*/ #define LNA_5 0x5
+/*MT6166*/ #define LNA_6 0x6
+/*MT6166*/ #define LNA_7 0x7
+/*MT6166*/
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_MT6165
+/*MT6165*/ /*--------------------------------------------------------*/
+/*MT6165*/ /* BFE Legacy Setting (no use) */
+/*MT6165*/ /*--------------------------------------------------------*/
+/*MT6165*/ #define BBRX_GAIN_DOUBLE 0
+/*MT6165*/ #define BBTX_IQ_SWAP 0
+/*MT6165*/ #define BBTX_CALBIAS 0
+/*MT6165*/ #define BBTX_CALRCSEL 0
+/*MT6165*/ #define BBTX_CALRCSEL_H 0
+/*MT6165*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6165*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6165*/ #define BBTX_TRIM_I 0 // wait calibration
+/*MT6165*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*MT6165*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*MT6165*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*MT6165*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*MT6165*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*MT6165*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*MT6165*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*MT6165*/ #define BBTX_PHSEL 0 // wait calibration
+/*MT6165*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*MT6165*/ #define BBTX_COARSGAIN 0
+/*MT6165*/ #define BBTX_GAIN 0 // get from experiment
+/*MT6165*/ #define BBTX_GAIN_H 0 // get from experiment
+/*MT6165*/ #define BBTX_GAIN_SWING 900 /* mV */
+/*MT6165*/
+/*MT6165*/ /*--------------------------------------------------------*/
+/*MT6165*/ /* Define band mode mapped receiver type */
+/*MT6165*/ /* DO NOT MODIFY the definitions here. */
+/*MT6165*/ /*--------------------------------------------------------*/
+/*MT6165*/ #define LNA_0 0x0
+/*MT6165*/ #define LNA_1 0x1
+/*MT6165*/ #define LNA_2 0x2
+/*MT6165*/ #define LNA_3 0x3
+/*MT6165*/ #define LNA_4 0x4
+/*MT6165*/ #define LNA_5 0x5
+/*MT6165*/ #define LNA_6 0x6
+/*MT6165*/
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_MT6176
+/*MT6176*/ /*--------------------------------------------------------*/
+/*MT6176*/ /* BFE Legacy Setting (no use) */
+/*MT6176*/ /*--------------------------------------------------------*/
+/*MT6176*/ #define BBRX_GAIN_DOUBLE 0
+/*MT6176*/ #define BBTX_IQ_SWAP 0
+/*MT6176*/ #define BBTX_CALBIAS 0
+/*MT6176*/ #define BBTX_CALRCSEL 0
+/*MT6176*/ #define BBTX_CALRCSEL_H 0
+/*MT6176*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6176*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6176*/ #define BBTX_TRIM_I 0 // wait calibration
+/*MT6176*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*MT6176*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*MT6176*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*MT6176*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*MT6176*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*MT6176*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*MT6176*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*MT6176*/ #define BBTX_PHSEL 0 // wait calibration
+/*MT6176*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*MT6176*/ #define BBTX_COARSGAIN 0
+/*MT6176*/ #define BBTX_GAIN 0 // get from experiment
+/*MT6176*/ #define BBTX_GAIN_H 0 // get from experiment
+/*MT6176*/ #define BBTX_GAIN_SWING 900 /* mV */
+/*MT6176*/
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_MT6179
+/*MT6179*/ /*--------------------------------------------------------*/
+/*MT6179*/ /* BFE Legacy Setting (no use) */
+/*MT6179*/ /*--------------------------------------------------------*/
+/*MT6179*/ #define BBRX_GAIN_DOUBLE 0
+/*MT6179*/ #define BBTX_IQ_SWAP 0
+/*MT6179*/ #define BBTX_CALBIAS 0
+/*MT6179*/ #define BBTX_CALRCSEL 0
+/*MT6179*/ #define BBTX_CALRCSEL_H 0
+/*MT6179*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6179*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6179*/ #define BBTX_TRIM_I 0 // wait calibration
+/*MT6179*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*MT6179*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*MT6179*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*MT6179*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*MT6179*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*MT6179*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*MT6179*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*MT6179*/ #define BBTX_PHSEL 0 // wait calibration
+/*MT6179*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*MT6179*/ #define BBTX_COARSGAIN 0
+/*MT6179*/ #define BBTX_GAIN 0 // get from experiment
+/*MT6179*/ #define BBTX_GAIN_H 0 // get from experiment
+/*MT6179*/ #define BBTX_GAIN_SWING 900 /* mV */
+/*MT6179*/
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_MT6177L
+/*MT6177L*/ /*--------------------------------------------------------*/
+/*MT6177L*/ /* BFE Legacy Setting (no use) */
+/*MT6177L*/ /*--------------------------------------------------------*/
+/*MT6177L*/ #define BBRX_GAIN_DOUBLE 0
+/*MT6177L*/ #define BBTX_IQ_SWAP 0
+/*MT6177L*/ #define BBTX_CALBIAS 0
+/*MT6177L*/ #define BBTX_CALRCSEL 0
+/*MT6177L*/ #define BBTX_CALRCSEL_H 0
+/*MT6177L*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6177L*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6177L*/ #define BBTX_TRIM_I 0 // wait calibration
+/*MT6177L*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*MT6177L*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*MT6177L*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*MT6177L*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*MT6177L*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*MT6177L*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*MT6177L*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*MT6177L*/ #define BBTX_PHSEL 0 // wait calibration
+/*MT6177L*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*MT6177L*/ #define BBTX_COARSGAIN 0
+/*MT6177L*/ #define BBTX_GAIN 0 // get from experiment
+/*MT6177L*/ #define BBTX_GAIN_H 0 // get from experiment
+/*MT6177L*/ #define BBTX_GAIN_SWING 900 /* mV */
+/*MT6177L*/
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_MT6177M
+/*MT6173*/ /*--------------------------------------------------------*/
+/*MT6173*/ /* BFE Legacy Setting (no use) */
+/*MT6173*/ /*--------------------------------------------------------*/
+/*MT6173*/ #define BBRX_GAIN_DOUBLE 0
+/*MT6173*/ #define BBTX_IQ_SWAP 0
+/*MT6173*/ #define BBTX_CALBIAS 0
+/*MT6173*/ #define BBTX_CALRCSEL 0
+/*MT6173*/ #define BBTX_CALRCSEL_H 0
+/*MT6173*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6173*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6173*/ #define BBTX_TRIM_I 0 // wait calibration
+/*MT6173*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*MT6173*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*MT6173*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*MT6173*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*MT6173*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*MT6173*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*MT6173*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*MT6173*/ #define BBTX_PHSEL 0 // wait calibration
+/*MT6173*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*MT6173*/ #define BBTX_COARSGAIN 0
+/*MT6173*/ #define BBTX_GAIN 0 // get from experiment
+/*MT6173*/ #define BBTX_GAIN_H 0 // get from experiment
+/*MT6173*/ #define BBTX_GAIN_SWING 900 /* mV */
+/*MT6173*/
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_TRINITYE1
+/*TRINITYE1*/ /*--------------------------------------------------------*/
+/*TRINITYE1*/ /* BFE Legacy Setting (no use) */
+/*TRINITYE1*/ /*--------------------------------------------------------*/
+/*TRINITYE1*/ #define BBRX_GAIN_DOUBLE 0
+/*TRINITYE1*/ #define BBTX_IQ_SWAP 0
+/*TRINITYE1*/ #define BBTX_CALBIAS 0
+/*TRINITYE1*/ #define BBTX_CALRCSEL 0
+/*TRINITYE1*/ #define BBTX_CALRCSEL_H 0
+/*TRINITYE1*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*TRINITYE1*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*TRINITYE1*/ #define BBTX_TRIM_I 0 // wait calibration
+/*TRINITYE1*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*TRINITYE1*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*TRINITYE1*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*TRINITYE1*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*TRINITYE1*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*TRINITYE1*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*TRINITYE1*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*TRINITYE1*/ #define BBTX_PHSEL 0 // wait calibration
+/*TRINITYE1*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*TRINITYE1*/ #define BBTX_COARSGAIN 0
+/*TRINITYE1*/ #define BBTX_GAIN 0 // get from experiment
+/*TRINITYE1*/ #define BBTX_GAIN_H 0 // get from experiment
+/*TRINITYE1*/ #define BBTX_GAIN_SWING 900 /* mV */
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_TRINITYL
+/*TRINITYL*/ /*--------------------------------------------------------*/
+/*TRINITYL*/ /* BFE Legacy Setting (no use) */
+/*TRINITYL*/ /*--------------------------------------------------------*/
+/*TRINITYL*/ #define BBRX_GAIN_DOUBLE 0
+/*TRINITYL*/ #define BBTX_IQ_SWAP 0
+/*TRINITYL*/ #define BBTX_CALBIAS 0
+/*TRINITYL*/ #define BBTX_CALRCSEL 0
+/*TRINITYL*/ #define BBTX_CALRCSEL_H 0
+/*TRINITYL*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*TRINITYL*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*TRINITYL*/ #define BBTX_TRIM_I 0 // wait calibration
+/*TRINITYL*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*TRINITYL*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*TRINITYL*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*TRINITYL*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*TRINITYL*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*TRINITYL*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*TRINITYL*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*TRINITYL*/ #define BBTX_PHSEL 0 // wait calibration
+/*TRINITYL*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*TRINITYL*/ #define BBTX_COARSGAIN 0
+/*TRINITYL*/ #define BBTX_GAIN 0 // get from experiment
+/*TRINITYL*/ #define BBTX_GAIN_H 0 // get from experiment
+/*TRINITYL*/ #define BBTX_GAIN_SWING 900 /* mV */
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_MT6186
+/*MT6186*/ /*--------------------------------------------------------*/
+/*MT6186*/ /* BFE Legacy Setting (no use) */
+/*MT6186*/ /*--------------------------------------------------------*/
+/*MT6186*/ #define BBRX_GAIN_DOUBLE 0
+/*MT6186*/ #define BBTX_IQ_SWAP 0
+/*MT6186*/ #define BBTX_CALBIAS 0
+/*MT6186*/ #define BBTX_CALRCSEL 0
+/*MT6186*/ #define BBTX_CALRCSEL_H 0
+/*MT6186*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6186*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6186*/ #define BBTX_TRIM_I 0 // wait calibration
+/*MT6186*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*MT6186*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*MT6186*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*MT6186*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*MT6186*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*MT6186*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*MT6186*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*MT6186*/ #define BBTX_PHSEL 0 // wait calibration
+/*MT6186*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*MT6186*/ #define BBTX_COARSGAIN 0
+/*MT6186*/ #define BBTX_GAIN 0 // get from experiment
+/*MT6186*/ #define BBTX_GAIN_H 0 // get from experiment
+/*MT6186*/ #define BBTX_GAIN_SWING 900 /* mV */
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_MT6186M
+/*MT6186M*/ /*--------------------------------------------------------*/
+/*MT6186M*/ /* BFE Legacy Setting (no use) */
+/*MT6186M*/ /*--------------------------------------------------------*/
+/*MT6186M*/ #define BBRX_GAIN_DOUBLE 0
+/*MT6186M*/ #define BBTX_IQ_SWAP 0
+/*MT6186M*/ #define BBTX_CALBIAS 0
+/*MT6186M*/ #define BBTX_CALRCSEL 0
+/*MT6186M*/ #define BBTX_CALRCSEL_H 0
+/*MT6186M*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6186M*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6186M*/ #define BBTX_TRIM_I 0 // wait calibration
+/*MT6186M*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*MT6186M*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*MT6186M*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*MT6186M*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*MT6186M*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*MT6186M*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*MT6186M*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*MT6186M*/ #define BBTX_PHSEL 0 // wait calibration
+/*MT6186M*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*MT6186M*/ #define BBTX_COARSGAIN 0
+/*MT6186M*/ #define BBTX_GAIN 0 // get from experiment
+/*MT6186M*/ #define BBTX_GAIN_H 0 // get from experiment
+/*MT6186M*/ #define BBTX_GAIN_SWING 900 /* mV */
+#endif
+
+/*============================================================================== */
+
+#if IS_RF_MT6190T
+/*MT6190T*/ /*--------------------------------------------------------*/
+/*MT6190T*/ /* BFE Legacy Setting (no use) */
+/*MT6190T*/ /*--------------------------------------------------------*/
+/*MT6190T*/ #define BBRX_GAIN_DOUBLE 0
+/*MT6190T*/ #define BBTX_IQ_SWAP 0
+/*MT6190T*/ #define BBTX_CALBIAS 0
+/*MT6190T*/ #define BBTX_CALRCSEL 0
+/*MT6190T*/ #define BBTX_CALRCSEL_H 0
+/*MT6190T*/ #define BBTX_COMMON_MODE_VOLTAGE 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6190T*/ #define BBTX_COMMON_MODE_VOLTAGE_H 0 //COMMON MODE VOLTAGE: 1.5v
+/*MT6190T*/ #define BBTX_TRIM_I 0 // wait calibration
+/*MT6190T*/ #define BBTX_TRIM_I_H 0 // wait calibration
+/*MT6190T*/ #define BBTX_TRIM_Q 0 // wait calibration
+/*MT6190T*/ #define BBTX_TRIM_Q_H 0 // wait calibration
+/*MT6190T*/ #define BBTX_OFFSET_I 0 // wait calibration
+/*MT6190T*/ #define BBTX_OFFSET_I_H 0 // wait calibration
+/*MT6190T*/ #define BBTX_OFFSET_Q 0 // wait calibration
+/*MT6190T*/ #define BBTX_OFFSET_Q_H 0 // wait calibration
+/*MT6190T*/ #define BBTX_PHSEL 0 // wait calibration
+/*MT6190T*/ #define BBTX_PHSEL_H 0 // wait calibration
+/*MT6190T*/ #define BBTX_COARSGAIN 0
+/*MT6190T*/ #define BBTX_GAIN 0 // get from experiment
+/*MT6190T*/ #define BBTX_GAIN_H 0 // get from experiment
+/*MT6190T*/ #define BBTX_GAIN_SWING 900 /* mV */
+#endif
+
+/*============================================================================== */
+
+
+
+
+#ifndef BBTX_IQSWAP_ONFLY
+#define BBTX_IQSWAP_ONFLY 0
+#endif
+
+//BBTX_PHSEL
+#ifndef BBTX_PHSEL
+#define BBTX_PHSEL 0
+#endif
+//BBTX_RPSEL
+#ifndef BBTX_RPSEL
+#define BBTX_RPSEL 0
+#endif
+//BBTX_INTEN
+#ifndef BBTX_INTEN
+#define BBTX_INTEN 0
+#endif
+//BBTX_SW_QBCNT
+#ifndef BBTX_SW_QBCNT
+#define BBTX_SW_QBCNT 0
+#endif
+//BBTX_RPSEL
+#ifndef BBTX_RPSEL
+#define BBTX_RPSEL 0
+#endif
+//BBTX_INTEN
+#ifndef BBTX_INTEN
+#define BBTX_INTEN 0
+#endif
+//BBTX_SW_QBCNT
+#ifndef BBTX_SW_QBCNT
+#define BBTX_SW_QBCNT 0
+#endif
+//BBTX_PHSEL
+#ifndef BBTX_PHSEL
+#define BBTX_PHSEL 0
+#endif
+
+#ifndef BBTX_CALRCSEL_H
+#define BBTX_CALRCSEL_H 0
+#endif
+#ifndef BBTX_COMMON_MODE_VOLTAGE_H
+#define BBTX_COMMON_MODE_VOLTAGE_H 0
+#endif
+#ifndef BBTX_TRIM_I_H
+#define BBTX_TRIM_I_H 0
+#endif
+#ifndef BBTX_TRIM_Q_H
+#define BBTX_TRIM_Q_H 0
+#endif
+#ifndef BBTX_DCCOARSE_I
+#define BBTX_DCCOARSE_I 0
+#endif
+#ifndef BBTX_DCCOARSE_Q
+#define BBTX_DCCOARSE_Q 0
+#endif
+#ifndef BBTX_DCCOARSE_I_H
+#define BBTX_DCCOARSE_I_H 0
+#endif
+#ifndef BBTX_DCCOARSE_Q_H
+#define BBTX_DCCOARSE_Q_H 0
+#endif
+#ifndef BBTX_OFFSET_I_H
+#define BBTX_OFFSET_I_H 0
+#endif
+#ifndef BBTX_OFFSET_Q_H
+#define BBTX_OFFSET_Q_H 0
+#endif
+#ifndef BBTX_GAIN_H
+#define BBTX_GAIN_H 0
+#endif
+#ifndef BBTX_PHSEL_H
+#define BBTX_PHSEL_H 0
+#endif
+#ifndef BBTX_GAIN_COMP
+#define BBTX_GAIN_COMP 0
+#endif
+#ifndef BBTX_IQGAIN_SEL
+#define BBTX_IQGAIN_SEL 0
+#endif
+#ifndef BBTX_GAIN_COMP_H
+#define BBTX_GAIN_COMP_H 0
+#endif
+#ifndef BBTX_IQGAIN_SEL_H
+#define BBTX_IQGAIN_SEL_H 0
+#endif
+#ifndef BBTX_PHSEL_I
+#define BBTX_PHSEL_I 0
+#endif
+#ifndef BBTX_PHSEL_Q
+#define BBTX_PHSEL_Q 0
+#endif
+#ifndef BBTX_PHSEL_I_H
+#define BBTX_PHSEL_I_H 0
+#endif
+#ifndef BBTX_PHSEL_Q_H
+#define BBTX_PHSEL_Q_H 0
+#endif
+#ifndef BBTX_EPSK_DTAP_SYM
+#define BBTX_EPSK_DTAP_SYM 0
+#endif
+/* ------------------------------------------------------------------------- */
+
+#if IS_CHIP_MT6583_MD1
+/* for MT6167 */
+#define QB_RX_FENA_2_FSYNC 48 /* this value shall be 4N+0 */
+#define QB_RX_FSYNC_2_FENA 0
+#define QB_TX_FENA_2_FSYNC 20
+#define QB_TX_FSYNC_2_FENA 30
+#endif
+
+#if IS_CHIP_MT6583_MD2
+/* for MT6168 */
+#undef QB_RX_FENA_2_FSYNC
+#undef QB_RX_FSYNC_2_FENA
+#undef QB_TX_FENA_2_FSYNC
+#undef QB_TX_FSYNC_2_FENA
+#define QB_RX_FENA_2_FSYNC 48 /* this value shall be 4N+0 */
+#define QB_RX_FSYNC_2_FENA 0
+#define QB_TX_FENA_2_FSYNC 20
+#define QB_TX_FSYNC_2_FENA 26
+#endif
+
+#if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define QB_RX_FENA_2_FSYNC 48 /* this value shall be 4N+0 */ /* the same as MT6291 */
+#define QB_RX_FSYNC_2_FENA 0 /* the same as MT6291 */
+#define QB_TX_FENA_2_FSYNC 20 /* the same as MT6291 */
+#define QB_TX_FSYNC_2_FENA 36 /* change for more ramp down profile usage */
+#elif IS_CHIP_TK6291 || IS_CHIP_MT6755
+#define QB_RX_FENA_2_FSYNC 48 /* this value shall be 4N+0 */ /* the same as MT6290 */
+#define QB_RX_FSYNC_2_FENA 0 /* the same as MT6290 */
+#define QB_TX_FENA_2_FSYNC 20 /* the same as MT6589 MD2 */
+#define QB_TX_FSYNC_2_FENA 26 /* the same as MT6589 MD2 */
+#elif IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2
+/* for MT6166 and MT6169 */
+#define QB_RX_FENA_2_FSYNC 48 /* this value shall be 4N+0 */
+#define QB_RX_FSYNC_2_FENA 0
+#define QB_TX_FENA_2_FSYNC 20
+#define QB_TX_FSYNC_2_FENA 30
+#endif
+
+#define QB_RON_2_FSYNC 0
+#define QB_FSYNC_2_ROFF 0
+#define QB_TON_2_FSYNC 16
+#define QB_FSYNC_2_TOFF 16
+
+#if IS_TDMA_AD_DA_WINDOW_SUPPORT
+ #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define QB_RX_ADEN_2_FENA 115 /* the same as MT6290 */
+#define QB_RX_FENA_2_ADEN 0 /* the same as MT6290 */
+#define QB_TX_DAEN_2_FENA 25 /* the same as MT6589 MD2 */
+#define QB_TX_FENA_2_DAEN 0 /* the same as MT6589 MD2 */
+ #elif IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2
+#define QB_RX_ADEN_2_FENA 115 /* >100us for MT6290 */
+#define QB_RX_FENA_2_ADEN 0
+#define QB_TX_DAEN_2_FENA 25 /* > 20us for MT6290 */
+#define QB_TX_FENA_2_DAEN 0
+ #elif IS_CHIP_MT6572
+#define QB_RX_ADEN_2_FENA 72 /* > 66us for MT6572 */
+#define QB_RX_FENA_2_ADEN 0
+#define QB_TX_DAEN_2_FENA 13 /* > 12us for MT6572 */
+#define QB_TX_FENA_2_DAEN 0
+ #elif IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2
+#define QB_RX_ADEN_2_FENA 135 /* >120us for MT6583 */
+#define QB_RX_FENA_2_ADEN 0
+#define QB_TX_DAEN_2_FENA 25 /* > 20us for MT6583 */
+#define QB_TX_FENA_2_DAEN 0
+ #else
+#error "please check the AD/DA window settings"
+ #endif
+#else
+#define QB_RX_ADEN_2_FENA 0
+#define QB_RX_FENA_2_ADEN 0
+#define QB_TX_DAEN_2_FENA 0
+#define QB_TX_FENA_2_DAEN 0
+#endif
+/* ------------------------------------------------------------------------- */
+#if IS_COSIM_ON_L1SIM_SUPPORT
+#undef QB_RX_ADEN_2_FENA
+#undef QB_RX_FENA_2_ADEN
+#undef QB_TX_DAEN_2_FENA
+#undef QB_TX_FENA_2_DAEN
+#define QB_RX_ADEN_2_FENA 1
+#define QB_RX_FENA_2_ADEN 0
+#define QB_TX_DAEN_2_FENA 1
+#define QB_TX_FENA_2_DAEN 0
+
+#undef QB_RX_FSYNC_2_FENA
+#define QB_RX_FSYNC_2_FENA 3
+#endif
+
+#ifdef L1D_TEST
+#undef QB_RX_FENA_2_FSYNC
+ #if IS_CHIP_MT6225_AND_LATTER_VERSION || IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+#define QB_RX_FENA_2_FSYNC 32
+#undef QB_TX_FENA_2_FSYNC
+#define QB_TX_FENA_2_FSYNC 152
+ #else
+#define QB_RX_FENA_2_FSYNC 33 /* this value shall be 4N+1 */
+ #endif
+ #if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+#undef QB_TX_FSYNC_2_FENA
+#define QB_TX_FSYNC_2_FENA 38 /* BFE additional loopback reset delay, tx_off only */
+ #endif
+
+#undef BBTX_IQ_SWAP
+#undef BBRX_IQ_SWAP
+#define BBTX_IQ_SWAP 0
+#define BBRX_IQ_SWAP 0
+#endif
+/* ------------------------------------------------------------------------- */
+#if IS_BBTXRX_CHIP_DESIGN_VER_2 || IS_BBTXRX_CHIP_DESIGN_VER_3
+#define QB_BFE_TXCOMP_HYS 1 // BFE TX compensation hysteresis
+#else
+#define QB_BFE_TXCOMP_HYS 0
+#endif
+/* ------------------------------------------------------------------------- */
+#if IS_TX_POWER_CONTROL_SUPPORT
+#define TEMP_VALUE_DEFAULT 20 /* Default temperature: 20 oC */
+#endif
+/* ------------------------------------------------------------------------- */
+/* For Gain Setting */
+#if IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define GAIN_PA 800 /* 25(dB) * 32, S10.5 */
+#endif
+/* ------------------------------------------------------------------------- */
+
+/* Parameter read from Flash or EEPROM */
+
+/* Bit width of AFC DAC: */
+/* Default Option */
+/* 1)MT6208,FPGA 10-bit 13-bit */
+/* 2)MT6205 13-bit X */
+
+//#define AFC_13bit /* used to turn on 13-bit AFC DAC for MT6208 or FPGA */
+//#define RX_ADC_14bit
+#ifdef __MTK_TARGET__
+ #if (!defined(FPGA))&&(!defined(MT6208))
+/*MT6205~*/ #ifndef AFC_13bit
+/*MT6205~*/ #define AFC_13bit
+/*MT6205~*/ #endif
+ #endif
+#endif
+
+#ifdef AFC_13bit
+/* Due to 13bits DAC */
+ #if IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+ #if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+#define PSI_EE (20250)
+ #else
+#define PSI_EE (4096) /* DAC initial value, sync with all RAT for Fix AFC */
+ #endif /* IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT */
+ #else
+#define PSI_EE (4100) /* DAC initial value */
+ #endif
+#else
+/* Due to 10bits DAC */
+#define PSI_EE (517) /* DAC initial value */
+#endif
+/* ------------------------------------------------------------------------- */
+
+#if IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+/*MT6176*/ #ifdef AFC_13bit
+ #if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ #define C_PSI_STA (1266) /* 3.24^(-1) *2^15*/
+ #else
+/*MT6176*/ #define C_PSI_STA (1266) /* C_PSI_STA= sta^(-1) * (2^12), sta=8.64 */
+ #endif /* IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT */
+/*MT6176*/ #else
+/*MT6176*/ #define C_PSI_STA (146) /* C_PSI_STA= sta^(-1) * (2^12), sta=28.05 */
+/*MT6176*/ #endif
+#endif
+
+/* ------------------------------------------------------------------------- */
+#if IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT
+
+ #define BAT_VOLTAGE_TRHESHOLD1_Default_Value VOLT2UVOLT(3.2)
+ #define BAT_VOLTAGE_TRHESHOLD2_Default_Value VOLT2UVOLT(3.5)
+ #define BAT_VOLTAGE_TRHESHOLD3_Default_Value VOLT2UVOLT(4.0)
+ #define BAT_VOLTAGE_TRHESHOLD4_Default_Value VOLT2UVOLT(4.2)
+
+ #define BAT_TEMPERATURE_TRHESHOLD1_Default_Value TEMP2MTEMP(-20)
+ #define BAT_TEMPERATURE_TRHESHOLD2_Default_Value TEMP2MTEMP(0)
+ #define BAT_TEMPERATURE_TRHESHOLD3_Default_Value TEMP2MTEMP(50)
+ #define BAT_TEMPERATURE_TRHESHOLD4_Default_Value TEMP2MTEMP(65)
+
+#else
+
+ #ifndef BAT_LOW_VOLTAGE_Set0
+ #define BAT_LOW_VOLTAGE_Default_Value VOLT2UVOLT(3.5)
+ #else
+ #define BAT_LOW_VOLTAGE_Default_Value BAT_LOW_VOLTAGE_Set0
+ #endif
+
+ #ifndef BAT_HIGH_VOLTAGE_Set0
+ #define BAT_HIGH_VOLTAGE_Default_Value VOLT2UVOLT(4.0)
+ #else
+ #define BAT_HIGH_VOLTAGE_Default_Value BAT_HIGH_VOLTAGE_Set0
+ #endif
+
+ #ifndef BAT_LOW_TEMPERATURE_Set0
+ #define BAT_LOW_TEMPERATURE_Default_Value TEMP2MTEMP(0)
+ #else
+ #define BAT_LOW_TEMPERATURE_Default_Value BAT_LOW_TEMPERATURE_Set0
+ #endif
+
+ #ifndef BAT_HIGH_TEMPERATURE_Set0
+ #define BAT_HIGH_TEMPERATURE_Default_Value TEMP2MTEMP(50)
+ #else
+ #define BAT_HIGH_TEMPERATURE_Default_Value BAT_HIGH_TEMPERATURE_Set0
+ #endif
+
+#endif
+
+ #ifndef AP_UPDATE_VOLTINFO_PERIOD_Set0
+ #define AP_UPDATE_VOLTINFO_PERIOD_Default_Value SECONDS2FRAME(1)
+ #else
+ #define AP_UPDATE_VOLTINFO_PERIOD_Default_Value AP_UPDATE_VOLTINFO_PERIOD_Set0
+ #endif
+
+/* ------------------------------------------------------------------------- */
+#endif
+
diff --git a/mcu/interface/l1/gl1/external/l1d_rf_dat_typedef.h b/mcu/interface/l1/gl1/external/l1d_rf_dat_typedef.h
new file mode 100644
index 0000000..9f0af8c
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_rf_dat_typedef.h
@@ -0,0 +1,185 @@
+/*******************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_rf_dat_typedef.h
+ *
+ * Project:
+ * --------
+ * MT6176
+ *
+ * Description:
+ * ------------
+ * MT6176 2G L1D DAT
+ *
+ * Author:
+ * -------
+ *
+ *
+ *******************************************************************************/
+
+#ifndef _L1D_RF_DAT_TYPEDEF_H_
+#define _L1D_RF_DAT_TYPEDEF_H_
+/* ------------------------------------------------------------------------- */
+#include "l1_public_defs.h"
+
+#define L1D_DAT_MAX_STATE_NUM 8
+#define L1D_DAT_FE_CAT_MAX_NUM 2
+#define L1D_DAT_MAX_CAT_A_CONFIG_NUM 8
+#define L1D_DAT_MAX_CAT_B_CONFIG_NUM 32
+#define L1D_DAT_MAX_MIPI_EVNET_NUM 8
+#define L1D_DAT_MAX_MIPI_DATA_NUM 20
+
+typedef enum
+{ L1D_DAT_FE_CAT_A_CONFIG0,
+ L1D_DAT_FE_CAT_A_CONFIG1,
+ L1D_DAT_FE_CAT_A_CONFIG2,
+ L1D_DAT_FE_CAT_A_CONFIG3,
+ L1D_DAT_FE_CAT_A_CONFIG4,
+ L1D_DAT_FE_CAT_A_CONFIG5,
+ L1D_DAT_FE_CAT_A_CONFIG6,
+ L1D_DAT_FE_CAT_A_CONFIG7,
+ L1D_DAT_FE_CAT_A_NULL,
+}L1D_CUSTOM_DAT_FE_CAT_A_CONFIG_IDX_E;
+
+typedef enum
+{ L1D_DAT_FE_CAT_B_CONFIG0,
+ L1D_DAT_FE_CAT_B_CONFIG1,
+ L1D_DAT_FE_CAT_B_CONFIG2,
+ L1D_DAT_FE_CAT_B_CONFIG3,
+ L1D_DAT_FE_CAT_B_CONFIG4,
+ L1D_DAT_FE_CAT_B_CONFIG5,
+ L1D_DAT_FE_CAT_B_CONFIG6,
+ L1D_DAT_FE_CAT_B_CONFIG7,
+ L1D_DAT_FE_CAT_B_CONFIG8,
+ L1D_DAT_FE_CAT_B_CONFIG9,
+ L1D_DAT_FE_CAT_B_CONFIG10,
+ L1D_DAT_FE_CAT_B_CONFIG11,
+ L1D_DAT_FE_CAT_B_CONFIG12,
+ L1D_DAT_FE_CAT_B_CONFIG13,
+ L1D_DAT_FE_CAT_B_CONFIG14,
+ L1D_DAT_FE_CAT_B_CONFIG15,
+ L1D_DAT_FE_CAT_B_CONFIG16,
+ L1D_DAT_FE_CAT_B_CONFIG17,
+ L1D_DAT_FE_CAT_B_CONFIG18,
+ L1D_DAT_FE_CAT_B_CONFIG19,
+ L1D_DAT_FE_CAT_B_CONFIG20,
+ L1D_DAT_FE_CAT_B_CONFIG21,
+ L1D_DAT_FE_CAT_B_CONFIG22,
+ L1D_DAT_FE_CAT_B_CONFIG23,
+ L1D_DAT_FE_CAT_B_CONFIG24,
+ L1D_DAT_FE_CAT_B_CONFIG25,
+ L1D_DAT_FE_CAT_B_CONFIG26,
+ L1D_DAT_FE_CAT_B_CONFIG27,
+ L1D_DAT_FE_CAT_B_CONFIG28,
+ L1D_DAT_FE_CAT_B_CONFIG29,
+ L1D_DAT_FE_CAT_B_CONFIG30,
+ L1D_DAT_FE_CAT_B_CONFIG31,
+ L1D_DAT_FE_CAT_B_NULL,
+}L1D_CUSTOM_DAT_FE_CAT_B_CONFIG_IDX_E;
+
+
+typedef enum
+{
+ L1D_DAT_MIPI_TABLE_CONFIG0,
+ L1D_DAT_MIPI_TABLE_CONFIG1,
+ L1D_DAT_MIPI_TABLE_CONFIG2,
+ L1D_DAT_MIPI_TABLE_CONFIG3,
+ L1D_DAT_MIPI_TABLE_CONFIG4,
+ L1D_DAT_MIPI_TABLE_CONFIG5,
+ L1D_DAT_MIPI_TABLE_CONFIG6,
+ L1D_DAT_MIPI_TABLE_CONFIG7,
+ L1D_DAT_MIPI_TABLE_CONFIG8,
+ L1D_DAT_MIPI_TABLE_CONFIG9,
+ L1D_DAT_MIPI_TABLE_CONFIG10,
+ L1D_DAT_MIPI_TABLE_CONFIG11,
+ L1D_DAT_MIPI_TABLE_CONFIG12,
+ L1D_DAT_MIPI_TABLE_CONFIG13,
+ L1D_DAT_MIPI_TABLE_CONFIG14,
+ L1D_DAT_MIPI_TABLE_CONFIG15,
+ L1D_DAT_MIPI_TABLE_CONFIG16,
+ L1D_DAT_MIPI_TABLE_CONFIG17,
+ L1D_DAT_MIPI_TABLE_CONFIG18,
+ L1D_DAT_MIPI_TABLE_CONFIG19,
+ L1D_DAT_MIPI_TABLE_CONFIG20,
+ L1D_DAT_MIPI_TABLE_CONFIG21,
+ L1D_DAT_MIPI_TABLE_CONFIG22,
+ L1D_DAT_MIPI_TABLE_CONFIG23,
+ L1D_DAT_MIPI_TABLE_CONFIG24,
+ L1D_DAT_MIPI_TABLE_CONFIG25,
+ L1D_DAT_MIPI_TABLE_CONFIG26,
+ L1D_DAT_MIPI_TABLE_CONFIG27,
+ L1D_DAT_MIPI_TABLE_CONFIG28,
+ L1D_DAT_MIPI_TABLE_CONFIG29,
+ L1D_DAT_MIPI_TABLE_CONFIG30,
+ L1D_DAT_MIPI_TABLE_CONFIG31,
+ L1D_DAT_MIPI_TABLE_NULL,
+}L1D_CUSTOM_DAT_MIPI_TBL_IDX_E;
+
+
+/*** Customer need to review and fill in correct setting ***/
+
+#define L1D_MIPI_DAT_ON_Set0 100 /*QB time*/
+
+/*--------------------------------------------------------------------*/
+/* User Notification
+ DAT single band indicator defintion:
+ We provide the max 35 single band indicator for DAT setting
+ Customer only need to fill in the specified bands which you want to enable DAT functionality.
+ There is no need to copy all band indocator from BAND_INDICATORX_Set0 at lte_custom_rf.h
+
+ If you don't want to enable DAT for LTE_Band1, you can delete it and fill it as LTE_BandNone.
+*/
+
+
+
+#define L1D_MIPI_DAT_EVENT(rt,s) L1D_##rt##_MIPI_EVENT_##s
+#define L1D_MIPI_DAT_DATA(rt,s) L1D_##rt##_MIPI_DATA_##s
+
+typedef struct
+{
+ L1D_CUSTOM_DAT_FE_CAT_A_CONFIG_IDX_E cat_a_route_num;
+ L1D_CUSTOM_DAT_FE_CAT_B_CONFIG_IDX_E cat_b_route_num;
+}L1D_CUSTOM_DAT_FE_ROUTE_MAP_T;
+
+typedef struct
+{
+ kal_uint32 bpi_mask;
+ kal_uint32 bpi_value;
+ L1D_CUSTOM_DAT_MIPI_TBL_IDX_E dat_mipi_table_index;
+}L1D_CUSTOM_DAT_FE_CAT_A_SETTING_T;
+
+typedef struct
+{
+ kal_uint32 bpi_mask;
+ kal_uint32 bpi_value;
+ L1D_CUSTOM_DAT_MIPI_TBL_IDX_E dat_mipi_table_index;
+}L1D_CUSTOM_DAT_FE_CAT_B_SETTING_T;
+
+typedef struct
+{
+ L1D_CUSTOM_DAT_FE_CAT_A_SETTING_T dat_cat_a_fe_route[L1D_DAT_MAX_CAT_A_CONFIG_NUM];
+}L1D_CUSTOM_DAT_FE_CAT_A_T;
+
+typedef struct
+{
+ L1D_CUSTOM_DAT_FE_CAT_B_SETTING_T dat_cat_b_fe_route[L1D_DAT_MAX_CAT_B_CONFIG_NUM];
+}L1D_CUSTOM_DAT_FE_CAT_B_T;
+
+
+typedef struct
+{
+ L1D_CUSTOM_DAT_FE_ROUTE_MAP_T l1d_dat_route_map[L1D_DAT_MAX_STATE_NUM];
+}L1D_CUSTOM_SB_DAT_FE_DATABASE_T;
+
+#endif /* _L1D_RF_DAT_TYPEDEF_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1d_rf_data_common.h b/mcu/interface/l1/gl1/external/l1d_rf_data_common.h
new file mode 100644
index 0000000..0149c30
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_rf_data_common.h
@@ -0,0 +1,1645 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_rf_data_common.h
+ *
+ * Project:
+ * --------
+ * MT6292
+ *
+ * Description:
+ * ------------
+ * Definition of RF global data & tables used in L1D
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision:
+ * $Modtime:
+ * $Log:
+ *
+ *******************************************************************************/
+
+#ifndef _L1D_RF_DATA_COMMON_H_
+#define _L1D_RF_DATA_COMMON_H_
+
+#include "l1_option.h"
+#include "mml1_fe_public.h"
+#if MD_DRV_IS_RF_TRINITYE1
+/*===============================================================================*/
+/* RF Calibration Result Structure */
+/*===============================================================================*/
+// Since MMRFC is module cross multi-module, add L1_SIM to avoid xL1Sim build error
+#define MMRFC_GSM_DET_FE_GAIN_STEPS 2
+#define MMRFC_GSM_TX_PGA_A_SLICE_NUM 2 //Slice for PGA-A = 4,2
+#define MMRFC_GSM_TX_PGA_B_SLICE_NUM 1 //Slice for PGA-B = 1
+#define MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS 14 ///< G0~G13
+#define MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS 8 ///< G14~G21 Note : Please fill in "0" if there is no PGA B !!!
+#define MMRFC_GSM_TX_AUX_SLICE_NUM 1 //Slice for AUX = 1
+#define MMRFC_GSM_TX_PGA_SLICE_NUM (MMRFC_GSM_TX_PGA_A_SLICE_NUM + MMRFC_GSM_TX_PGA_B_SLICE_NUM + MMRFC_GSM_TX_AUX_SLICE_NUM)
+#define MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS 5 ///< G22~G26
+#define MMRFC_GSM_TX_DNL_PGA_TOTAL_GAIN_STEPS (MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS + MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS + MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS) // G0 ~ G26
+#define MMRFC_GSM_TX_DNL_PGA_A_SEQ_NUM (MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS-1) //20, Calibration sequence for PGA-A, 21 for MT6177L
+#define MMRFC_GSM_TX_DNL_PGA_B_SEQ_NUM (MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS+MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS-1) //16, Calibration sequence for PGA-B and PGA-AUX
+#define MMRFC_GSM_TX_PGA_TYPE_NUM 3 //PGA-A, PGA-B, PGA-AUX
+#define MMRFC_GSM_TX_PGA_GAIN_STEP_SUBBAND_NUM 12 //12 subband for PGA gain step cal
+#define MMRFC_GSM_TX_PGA_GAIN_STEP_NUM 10 ///< G11a-G12b, G12a-G13b, G13a-G14b, G14a-G15b, G15a-G16b, G16a-G17b, G17a-G18b, G18a-G19b, G19a-G20b, G20a-G21b
+#define MMRFC_GSM_TX_PGA_GAIN_START 11 //PGA-A&B Switch Start Point, use for POC value init, in view of PGA-A.
+#define MMRFC_GSM_TX_PGA_GAIN_SWITCH 14 //Switch Point for PGA-A -> PGA-B, use for L1D_RF_Gainrf_Init(), in view of PGA-A.
+#define MMRFC_GSM_TX_CBW_NUM 1
+#define MMRFC_GSM_DET_GAIN_STEPS_DET_CAL 17
+#define MMRFC_GSM_FILT_TAPS_NUM 7 ///< maximum numbers of compensation filter taps
+#define MMRFC_GSM_DET_EQLPF_TAP_NUM 11
+#define MMRFC_GSM_DET_FE_GAIN_STEPS 2
+#define MMRFC_GSM_DET_CDCOC_GAIN_STEPS_NUM 4
+#define MMRFC_GSM_TX_PGA_BIAS_STEP_NUM (3) // for TrinityL
+
+
+#elif MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M
+/*===============================================================================*/
+/* RF Calibration Result Structure */
+/*===============================================================================*/
+// Since MMRFC is module cross multi-module, add L1_SIM to avoid xL1Sim build error
+#define MMRFC_GSM_DET_FE_GAIN_STEPS 2
+#define MMRFC_GSM_TX_PGA_A_SLICE_NUM 3 //Slice for PGA-A = 4,2,1
+#define MMRFC_GSM_TX_PGA_B_SLICE_NUM 0 //Slice for PGA-B = 1
+#define MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS 22 ///< G0~G21
+#define MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS 0 // Note : Please fill in "0" if there is no PGA B !!!
+#define MMRFC_GSM_TX_AUX_SLICE_NUM 1 //Slice for AUX = 1
+#define MMRFC_GSM_TX_PGA_SLICE_NUM (MMRFC_GSM_TX_PGA_A_SLICE_NUM + MMRFC_GSM_TX_PGA_B_SLICE_NUM + MMRFC_GSM_TX_AUX_SLICE_NUM)
+#define MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS 5 ///< G22~G26
+#define MMRFC_GSM_TX_DNL_PGA_TOTAL_GAIN_STEPS (MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS + MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS + MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS) // G0 ~ G26
+#define MMRFC_GSM_TX_DNL_PGA_A_SEQ_NUM (MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS-1) //20, Calibration sequence for PGA-A, 21 for MT6177L
+#define MMRFC_GSM_TX_DNL_PGA_B_SEQ_NUM (MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS+MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS-1) //16, Calibration sequence for PGA-B and PGA-AUX
+#define MMRFC_GSM_TX_PGA_TYPE_NUM 2 //PGA-A, PGA-AUX
+#define MMRFC_GSM_TX_PGA_GAIN_STEP_SUBBAND_NUM 12 //12 subband for PGA gain step cal
+#define MMRFC_GSM_TX_PGA_GAIN_STEP_NUM 10 ///< G11a-G12b, G12a-G13b, G13a-G14b, G14a-G15b, G15a-G16b, G16a-G17b, G17a-G18b, G18a-G19b, G19a-G20b, G20a-G21b
+#define MMRFC_GSM_TX_PGA_GAIN_START 11 //PGA-A&B Switch Start Point, use for POC value init, in view of PGA-A.
+#define MMRFC_GSM_TX_PGA_GAIN_SWITCH 14 //Switch Point for PGA-A -> PGA-B, use for L1D_RF_Gainrf_Init(), in view of PGA-A.
+#define MMRFC_GSM_TX_CBW_NUM 1
+#define MMRFC_GSM_DET_GAIN_STEPS_DET_CAL 17
+#define MMRFC_GSM_FILT_TAPS_NUM 7 ///< maximum numbers of compensation filter taps
+#define MMRFC_GSM_DET_EQLPF_TAP_NUM 13
+#define MMRFC_GSM_DET_FE_GAIN_STEPS 2
+#define MMRFC_GSM_DET_CDCOC_GAIN_STEPS_NUM 4
+#define MMRFC_GSM_TX_PGA_BIAS_STEP_NUM (3) // for TrinityL
+
+#elif MD_DRV_IS_RF_MT6190T
+/*===============================================================================*/
+/* RF Calibration Result Structure */
+/*===============================================================================*/
+// Since MMRFC is module cross multi-module, add L1_SIM to avoid xL1Sim build error
+#define MMRFC_GSM_DET_FE_GAIN_STEPS 2
+#define MMRFC_GSM_TX_PGA_A_SLICE_NUM 3 //Slice for PGA-A = 4,2,1
+#define MMRFC_GSM_TX_PGA_B_SLICE_NUM 0 //Slice for PGA-B = 1
+#define MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS 27 ///< G0~G26
+#define MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS 0 // Note : Please fill in "0" if there is no PGA B !!!
+#define MMRFC_GSM_TX_AUX_SLICE_NUM 1 //Slice for AUX = 1
+#define MMRFC_GSM_TX_PGA_SLICE_NUM (MMRFC_GSM_TX_PGA_A_SLICE_NUM + MMRFC_GSM_TX_PGA_B_SLICE_NUM + MMRFC_GSM_TX_AUX_SLICE_NUM)
+#define MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS 1 ///< G27
+#define MMRFC_GSM_TX_DNL_PGA_TOTAL_GAIN_STEPS (MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS + MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS + MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS) // G0 ~ G26
+#define MMRFC_GSM_TX_DNL_PGA_A_SEQ_NUM (MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS) //Calibration sequence for PGA-A
+#define MMRFC_GSM_TX_DNL_PGA_B_SEQ_NUM (MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS+MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS) //Calibration sequence for PGA-B and PGA-AUX
+#define MMRFC_GSM_TX_PGA_TYPE_NUM 2 //PGA-A, PGA-AUX
+#define MMRFC_GSM_TX_PGA_GAIN_STEP_SUBBAND_NUM 12 //12 subband for PGA gain step cal
+#define MMRFC_GSM_TX_PGA_GAIN_STEP_NUM 10 ///< G11a-G12b, G12a-G13b, G13a-G14b, G14a-G15b, G15a-G16b, G16a-G17b, G17a-G18b, G18a-G19b, G19a-G20b, G20a-G21b
+#define MMRFC_GSM_TX_PGA_GAIN_START 11 //PGA-A&B Switch Start Point, use for POC value init, in view of PGA-A.
+#define MMRFC_GSM_TX_PGA_GAIN_SWITCH 14 //Switch Point for PGA-A -> PGA-B, use for L1D_RF_Gainrf_Init(), in view of PGA-A.
+#define MMRFC_GSM_TX_CBW_NUM 1
+#define MMRFC_GSM_DET_GAIN_STEPS_DET_CAL 17
+#define MMRFC_GSM_FILT_TAPS_NUM 7 ///< maximum numbers of compensation filter taps
+#define MMRFC_GSM_DET_EQLPF_TAP_NUM 11
+#define MMRFC_GSM_DET_FE_GAIN_STEPS 2
+#define MMRFC_GSM_DET_CDCOC_GAIN_STEPS_NUM 4
+#define MMRFC_GSM_TX_PGA_BIAS_STEP_NUM (3) // for TrinityL
+
+
+#if 0//MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+ #if 0
+#if( MMRFC_GSM_DET_FE_GAIN_STEPS != MMRFC_DET_FE_GAIN_STEPS )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_PGA_A_SLICE_NUM != MMRFC_TX_PGA_A_SLICE_NUM )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_PGA_B_SLICE_NUM != MMRFC_TX_PGA_B_SLICE_NUM )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_PGA_SLICE_NUM != MMRFC_TX_PGA_SLICE_NUM )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS != MMRFC_TX_DNL_PGA_A_GAIN_STEPS )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS != MMRFC_TX_DNL_PGA_B_GAIN_STEPS )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS != MMRFC_TX_DNL_PGA_AUX_GAIN_STEPS )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_DNL_PGA_TOTAL_GAIN_STEPS != MMRFC_TX_DNL_PGA_TOTAL_GAIN_STEPS )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_DNL_PGA_A_SEQ_NUM != MMRFC_TX_DNL_PGA_A_SEQ_NUM )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_DNL_PGA_B_SEQ_NUM != MMRFC_TX_DNL_PGA_B_SEQ_NUM )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_PGA_TYPE_NUM != MMRFC_TX_PGA_TYPE_NUM )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_PGA_GAIN_STEP_SUBBAND_NUM != MMRFC_TX_PGA_GAIN_STEP_SUBBAND_NUM )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_PGA_GAIN_STEP_NUM != MMRFC_TX_PGA_GAIN_STEP_NUM )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_PGA_GAIN_START != MMRFC_TX_PGA_GAIN_START )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_PGA_GAIN_SWITCH != MMRFC_TX_PGA_GAIN_SWITCH )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_TX_CBW_NUM != MMRFC_TX_CBW_NUM )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_DET_GAIN_STEPS_DET_CAL != MMRFC_DET_GAIN_STEPS_DET_CAL )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_FILT_TAPS_NUM != MMRFC_FILT_TAPS_NUM )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_DET_EQLPF_TAP_NUM != MMRFC_DET_EQLPF_TAP_NUM )
+/* under construction !*/
+#endif
+#if( MMRFC_GSM_DET_FE_GAIN_STEPS != MMRFC_DET_FE_GAIN_STEPS )
+/* under construction !*/
+#endif
+ #endif
+#elif MD_DRV_IS_RF_MT6177M
+/*===============================================================================*/
+/* RF Calibration Result Structure */
+/*===============================================================================*/
+// Since MMRFC is module cross multi-module, add L1_SIM to avoid xL1Sim build error
+#define MMRFC_GSM_DET_FE_GAIN_STEPS 2
+#define MMRFC_GSM_TX_PGA_A_SLICE_NUM 4 //Slice for PGA-A = 8, 4, 2, 1
+#define MMRFC_GSM_TX_PGA_B_SLICE_NUM 0 //MT6177M don't have PGA B
+#define MMRFC_GSM_TX_PGA_SLICE_NUM (MMRFC_GSM_TX_PGA_A_SLICE_NUM + MMRFC_GSM_TX_PGA_B_SLICE_NUM)
+#define MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS 22 ///< G0~G21
+#define MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS 0
+#define MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS 8 ///< G22~G29
+#define MMRFC_GSM_TX_DNL_PGA_A_SEQ_NUM (MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS+MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS-1) // Calibration sequence for PGA-A
+#define MMRFC_GSM_TX_DNL_PGA_B_SEQ_NUM (MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS) // Calibration sequence for PGA-B and PGA-AUX
+#define MMRFC_GSM_TX_PGA_TYPE_NUM 2 //PGA-A, PGA-AUX
+#define MMRFC_GSM_TX_PGA_GAIN_STEP_SUBBAND_NUM 12 //12 subband for PGA gain step cal
+#define MMRFC_GSM_TX_PGA_GAIN_STEP_NUM 10 ///< G11a-G12b, G12a-G13b, G13a-G14b, G14a-G15b, G15a-G16b, G16a-G17b, G17a-G18b, G18a-G19b, G19a-G20b, G20a-G21b
+#define MMRFC_GSM_TX_PGA_GAIN_START 11 //PGA-A&B Switch Start Point, use for POC value init, in view of PGA-A.
+#define MMRFC_GSM_TX_PGA_GAIN_SWITCH 14 //Switch Point for PGA-A -> PGA-B, use for L1D_RF_Gainrf_Init(), in view of PGA-A.
+#define MMRFC_GSM_TX_CBW_NUM 1
+#define MMRFC_GSM_DET_GAIN_STEPS_DET_CAL 17
+#define MMRFC_GSM_FILT_TAPS_NUM 7 ///< maximum numbers of compensation filter taps
+#define MMRFC_GSM_DET_EQLPF_TAP_NUM 11
+#define MMRFC_GSM_DET_FE_GAIN_STEPS 2
+
+#elif MD_DRV_IS_RF_MT6176 || MD_DRV_IS_RF_MT6179 || MD_DRV_IS_RF_MT6177L
+/*===============================================================================*/
+/* RF Calibration Result Structure */
+/*===============================================================================*/
+// Since MMRFC is module cross multi-module, add L1_SIM to avoid xL1Sim build error
+#define MMRFC_GSM_DET_FE_GAIN_STEPS 2
+#define MMRFC_GSM_TX_PGA_A_SLICE_NUM 5 //Slice for PGA-A = 8, 7, 4, 2, 1
+#define MMRFC_GSM_TX_PGA_B_SLICE_NUM 2 //Slice for PGA-B = 2, 1
+#define MMRFC_GSM_TX_PGA_SLICE_NUM (MMRFC_GSM_TX_PGA_A_SLICE_NUM + MMRFC_GSM_TX_PGA_B_SLICE_NUM)
+ #if MD_DRV_IS_RF_MT6177L
+#define MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS 22 ///< G0~G21
+ #else
+#define MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS 21 ///< G0~G20
+ #endif
+#define MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS 10 ///< G12~G21
+#define MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS 7 ///< G22~G28
+#define MMRFC_GSM_TX_DNL_PGA_A_SEQ_NUM (MMRFC_GSM_TX_DNL_PGA_A_GAIN_STEPS-1) //20, Calibration sequence for PGA-A, 21 for MT6177L
+#define MMRFC_GSM_TX_DNL_PGA_B_SEQ_NUM (MMRFC_GSM_TX_DNL_PGA_B_GAIN_STEPS+MMRFC_GSM_TX_DNL_PGA_AUX_GAIN_STEPS-1) //16, Calibration sequence for PGA-B and PGA-AUX
+#define MMRFC_GSM_TX_PGA_TYPE_NUM 3 //PGA-A, PGA-B, PGA-AUX
+#define MMRFC_GSM_TX_PGA_GAIN_STEP_SUBBAND_NUM 12 //12 subband for PGA gain step cal
+#define MMRFC_GSM_TX_PGA_GAIN_STEP_NUM 10 ///< G11a-G12b, G12a-G13b, G13a-G14b, G14a-G15b, G15a-G16b, G16a-G17b, G17a-G18b, G18a-G19b, G19a-G20b, G20a-G21b
+#define MMRFC_GSM_TX_PGA_GAIN_START 11 //PGA-A&B Switch Start Point, use for POC value init, in view of PGA-A.
+#define MMRFC_GSM_TX_PGA_GAIN_SWITCH 14 //Switch Point for PGA-A -> PGA-B, use for L1D_RF_Gainrf_Init(), in view of PGA-A.
+#define MMRFC_GSM_TX_CBW_NUM 1
+#define MMRFC_GSM_DET_GAIN_STEPS_DET_CAL 17
+#define MMRFC_GSM_FILT_TAPS_NUM 7 ///< maximum numbers of compensation filter taps
+#define MMRFC_GSM_DET_EQLPF_TAP_NUM 11
+#define MMRFC_GSM_DET_FE_GAIN_STEPS 2
+#endif
+#if MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T
+typedef struct{
+ kal_int32 dc_est_i;
+ kal_int32 dc_est_q;
+} MMRFC_GSM_TX_DC_RESULT_T;
+typedef struct{
+ kal_uint32 det_cdcoc_i; /* MRX coarse DC offset I channel */
+ kal_uint32 det_cdcoc_q; /* MRX coarse DC offset I channel */
+ kal_uint32 det_cdcoci_mag;
+ kal_uint32 det_cdcoci_sign;
+ kal_uint32 det_cdcocq_mag;
+ kal_uint32 det_cdcocq_sign;
+} MMRFC_GSM_DET_CDCOC_RESULT_T;
+typedef struct
+{
+ kal_int32 pga_bias[MMRFC_GSM_TX_PGA_BIAS_STEP_NUM /* Slice : 0:4A, 1:2A, 2:1A */];
+}MMRFC_GSM_POC_PGA_BIAS_T;
+#endif
+#if MD_DRV_IS_RF_MT6176 || MD_DRV_IS_RF_MT6179 || MD_DRV_IS_RF_MT6177L || MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T || MD_DRV_IS_RF_MT6177M
+
+typedef struct{
+ kal_int32 gain_est;
+ kal_int32 phase_est;
+ kal_int32 dc_est_i;
+ kal_int32 dc_est_q;
+ kal_int16 freq_dep_phase_tx;
+} MMRFC_GSM_TX_IQDC_RESULT_T;
+
+typedef struct{
+ kal_int32 gain_est_hw;
+ kal_int32 phase_est_hw;
+ kal_int16 freq_dep_filt[MMRFC_GSM_FILT_TAPS_NUM];
+ kal_int32 dnl;
+} MMRFC_GSM_DET_IQDNL_RESULT_T;
+
+typedef struct{
+ kal_int32 dc_est_i;
+ kal_int32 dc_est_q;
+} MMRFC_GSM_DET_DC_RESULT_T;
+
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+
+} MMRFC_DET_GSM_EQLPF_COMP_T;
+
+
+typedef struct
+{
+ MMRFC_DET_GSM_EQLPF_COMP_T coef[MMRFC_GSM_DET_EQLPF_TAP_NUM]; //< maximum numbers of filter taps for DET EQLPF comp.
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+} MMRFC_GSM_DET_EQLPF_CFG_T;
+
+typedef struct
+{
+#if MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T
+ MMRFC_GSM_DET_CDCOC_RESULT_T det_cdcoc_result[MMRFC_GSM_DET_CDCOC_GAIN_STEPS_NUM];
+ #if MD_DRV_IS_RF_MT6186
+ MMRFC_GSM_DET_CDCOC_RESULT_T det_ant_cdcoc_result[MMRFC_GSM_DET_CDCOC_GAIN_STEPS_NUM];
+ #endif
+#else
+ kal_uint32 det_coarse_dcoc_cw807;
+ kal_uint32 det_coarse_dcoc_cw808;
+#endif
+ MMRFC_GSM_DET_IQDNL_RESULT_T det_iqdnl_fwd[MMRFC_GSM_DET_FE_GAIN_STEPS][MMRFC_GSM_TX_CBW_NUM];
+ MMRFC_GSM_DET_DC_RESULT_T det_dc_fwd[MMRFC_GSM_DET_GAIN_STEPS_DET_CAL];
+ #if MD_DRV_IS_RF_MT6186
+ MMRFC_GSM_DET_DC_RESULT_T det_ant_dc_fwd[MMRFC_GSM_DET_GAIN_STEPS_DET_CAL];
+ #endif
+ MMRFC_GSM_DET_IQDNL_RESULT_T det_iqdnl_rev[MMRFC_GSM_DET_FE_GAIN_STEPS][MMRFC_GSM_TX_CBW_NUM];
+ MMRFC_GSM_DET_DC_RESULT_T det_dc_rev[MMRFC_GSM_DET_GAIN_STEPS_DET_CAL];
+ MMRFC_GSM_DET_EQLPF_CFG_T det_fdadpcb_filter[MMRFC_GSM_DET_FE_GAIN_STEPS];
+#if MD_DRV_IS_RF_MT6176 || MD_DRV_IS_RF_MT6179 || MD_DRV_IS_RF_MT6177L || MD_DRV_IS_RF_MT6177M
+ kal_int16 tx_rc_lpf;
+ kal_int16 tx_rc_rcf;
+ /*MD_DRV_IS_RF_TRINITYE1:TX_LO cal. not done in TRININTY*/
+ kal_uint32 tx_lo;
+ kal_uint8 tx_lo_ind;
+ kal_uint8 tx_lo_capcal_peak_cap;
+ kal_uint8 tx_lo_in_bias_hpm;
+ kal_uint8 tx_lo_in_bias_lpm;
+ kal_int16 pga_gain_subband[MMRFC_GSM_TX_PGA_GAIN_STEP_SUBBAND_NUM];
+ kal_int16 pga_gain_step[MMRFC_GSM_TX_PGA_GAIN_STEP_SUBBAND_NUM][MMRFC_GSM_TX_PGA_GAIN_STEP_NUM];
+#endif
+ MMRFC_GSM_TX_IQDC_RESULT_T tx_iqdc_lin[MMRFC_GSM_TX_PGA_SLICE_NUM+1]; //+1 only for PGA-AUX
+
+ kal_int16 tx_dnl_lin_pga_a[MMRFC_GSM_TX_DNL_PGA_A_SEQ_NUM];
+#if MD_DRV_IS_RF_MT6177M
+ //Don't have PGA B
+#else
+ kal_int16 tx_dnl_lin_pga_b[MMRFC_GSM_TX_DNL_PGA_B_SEQ_NUM];
+#endif
+
+ kal_uint16 cap_tuning_pga_a;
+ kal_uint16 cap_tuning_pga_b;
+#if MD_DRV_IS_RF_TRINITYE1 || MD_DRV_IS_RF_TRINITYL || MD_DRV_IS_RF_MT6186 || MD_DRV_IS_RF_MT6186M || MD_DRV_IS_RF_MT6190T
+ kal_uint16 cap_tuning_mod;
+ #if IS_CHIP_MT6295 || IS_CHIP_MT6297
+ MMRFC_GSM_TX_DC_RESULT_T tx_cdcoc_lin[MMRFC_GSM_TX_PGA_SLICE_NUM+1]; //+1 only for PGA-AUX, only used in MT6295
+ #endif
+ kal_uint16 tx_rc_lpf_rsel;
+ kal_uint16 tx_rc_lpf_csel1;//first part of LPF C value after LPF calibration in Manual mode
+ kal_uint16 tx_rc_lpf_csel2;//second part of LPF C value after LPF calibration in Manual mode, use this as TXn_ABB_CSEL
+ kal_uint16 tx_rc_rcf_rsel;
+ kal_uint16 tx_rc_rcf_csel;
+ kal_uint16 tx_rc_rcf_csel_1b;
+ kal_uint16 tx_rc_rcf_csel_2a;
+ kal_uint16 tx_rc_rcf_csel_4a;
+ kal_uint16 mrx_tza_ctune;
+ kal_uint16 mrx_pga_ctune;
+#endif
+
+} MMRFC_GSM_RESULT_PER_BAND_T;
+/* ------------------------------------------------------------------------- */
+
+ #if MD_DRV_IS_RF_MT6176
+/*---------------------------------------------------------------*/
+/* Primary RX Path (bit[20]=0: Primarary) */
+/* Primary RX Path (bit[21]=Reserved for future extension) */
+/* Primary RX Path (bit[22]=Reserved for future extension) */
+/* Primary RX Path (bit[23]=Reserved for future extension) */
+/* Primary RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+/*---------------------------------------------------------------*/
+/* Diversity RX Path (bit[20]=1: Diversity) */
+/* Diversity RX Path (bit[21]=Reserved for future extension) */
+/* Diversity RX Path (bit[22]=Reserved for future extension) */
+/* Diversity RX Path (bit[23]=Reserved for future extension) */
+/* Diversity RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+/*---------------------------------------------------------------*/
+typedef enum
+{
+ IORX_PRX1 = 0x000048,
+ IORX_PRX2 = 0x000088,
+ IORX_PRX3 = 0x000108,
+ IORX_PRX4 = 0x000044,
+ IORX_PRX5 = 0x000084,
+ IORX_PRX6 = 0x000104,
+ IORX_PRX7 = 0x000204,
+ IORX_PRX8 = 0x000042,
+ IORX_PRX9 = 0x000082,
+ IORX_PRX10 = 0x000102,
+ IORX_PRX11 = 0x000202,
+ IORX_PRX12 = 0x000041,
+ IORX_PRX13 = 0x000081,
+ IORX_PRX14 = 0x000101,
+ //IORX_DRX1 = 0x100048,
+ //IORX_DRX2 = 0x100088,
+ //IORX_DRX3 = 0x100108,
+ //IORX_DRX4 = 0x100044,
+ //IORX_DRX5 = 0x100084,
+ //IORX_DRX6 = 0x100104,
+ //IORX_DRX7 = 0x100204,
+ //IORX_DRX8 = 0x100042,
+ //IORX_DRX9 = 0x100082,
+ //IORX_DRX10 = 0x100102,
+ //IORX_DRX11 = 0x100202,
+ //IORX_DRX12 = 0x100041,
+ //IORX_DRX13 = 0x100081,
+ //IORX_DRX14 = 0x100101,
+}GGE_IORX_E;
+
+ #elif MD_DRV_IS_RF_MT6179
+/*---------------------------------------------------------------*/
+/* Primary RX Path (bit[20]=0: Primarary) */
+/* Primary RX Path (bit[21]=Reserved for future extension) */
+/* Primary RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+/* Primary RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+/* Primary RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+/*---------------------------------------------------------------*/
+/* Diversity RX Path (bit[20]=1: Diversity) */
+/* Diversity RX Path (bit[21]=Reserved for future extension) */
+/* Diversity RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+/* Diversity RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+/* Diversity RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+/*---------------------------------------------------------------*/
+#define IORX_PATH_LSB 20
+#define IORX_RFIC_LSB 22
+#define IORX_LNA_GROUP_LSB 23
+#define IORX_ELNA_LSB 24
+
+
+#define IORX_PRIMARY (0<<IORX_PATH_LSB)
+#define IORX_DIVERSITY (1<<IORX_PATH_LSB)
+
+#define IORX_RFIC0 (0<<IORX_RFIC_LSB)
+#define IORX_RFIC1 (1<<IORX_RFIC_LSB)
+
+#define IORX_LNA_LMB (0<<IORX_LNA_GROUP_LSB)
+#define IORX_LNA_MHB (1<<IORX_LNA_GROUP_LSB)
+
+#define IORX_ELNA_USAGE (1<<IORX_ELNA_LSB)
+
+
+typedef enum
+{
+ IORX_PRX1 = ( 0x000021 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX2 = ( 0x000041 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX3 = ( 0x000061 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX4 = ( 0x0000A1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX5 = ( 0x000101 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX6 = ( 0x0000C1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX7 = ( 0x000022 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PRX8 = ( 0x000042 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PRX9 = ( 0x0000C2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PRX10 = ( 0x0000E2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PRX11 = ( 0x0000A2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PRX12 = ( 0x000021 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ IORX_PRX13 = ( 0x000041 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ IORX_PRX14 = ( 0x000061 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ IORX_PRX15 = ( 0x000081 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ IORX_PRX16 = ( 0x0000A1 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ IORX_PRX17 = ( 0x000101 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ IORX_PRX18 = ( 0x000022 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_MHB) ),
+ IORX_PRX19 = ( 0x000042 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_MHB) ),
+ IORX_PRX20 = ( 0x0000A2 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_MHB) ),
+ IORX_PRX21 = ( 0x0000E2 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_MHB) ),
+ IORX_PRX22 = ( 0x0000C2 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_MHB) ),
+ #if MD_DRV_IS_2G_EXTERNAL_LNA_SUPPORT
+ IORX_PRX1_ELNA = ( 0x000021 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX2_ELNA = ( 0x000041 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX3_ELNA = ( 0x000061 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX4_ELNA = ( 0x0000A1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX5_ELNA = ( 0x000101 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX6_ELNA = ( 0x0000C1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX7_ELNA = ( 0x000022 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX8_ELNA = ( 0x000042 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX9_ELNA = ( 0x0000C2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX10_ELNA = ( 0x0000E2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX11_ELNA = ( 0x0000A2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX12_ELNA = ( 0x000021 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX13_ELNA = ( 0x000041 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX14_ELNA = ( 0x000061 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX15_ELNA = ( 0x000081 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX16_ELNA = ( 0x0000A1 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX17_ELNA = ( 0x000101 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX18_ELNA = ( 0x000022 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX19_ELNA = ( 0x000042 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX20_ELNA = ( 0x0000A2 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX21_ELNA = ( 0x0000E2 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ IORX_PRX22_ELNA = ( 0x0000C2 | (IORX_PRIMARY) | (IORX_RFIC1) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ #endif
+ //IORX_DRX1 = ( 0x000021 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ //IORX_DRX2 = ( 0x000041 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ //IORX_DRX3 = ( 0x000061 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ //IORX_DRX4 = ( 0x0000A1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ //IORX_DRX5 = ( 0x0000C1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ //IORX_DRX6 = ( 0x0000E1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ //IORX_DRX7 = ( 0x000042 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ //IORX_DRX8 = ( 0x000022 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ //IORX_DRX9 = ( 0x0000E2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ //IORX_DRX10 = ( 0x0000C2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ //IORX_DRX11 = ( 0x0000A2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ //IORX_DRX12 = ( 0x000021 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ //IORX_DRX13 = ( 0x000041 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ //IORX_DRX14 = ( 0x000061 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ //IORX_DRX15 = ( 0x000081 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ //IORX_DRX16 = ( 0x0000A1 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ //IORX_DRX17 = ( 0x0000C1 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) ),
+ //IORX_DRX18 = ( 0x000042 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_MHB) ),
+ //IORX_DRX19 = ( 0x000022 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_MHB) ),
+ //IORX_DRX20 = ( 0x0000A2 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_MHB) ),
+ //IORX_DRX21 = ( 0x0000C2 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_MHB) ),
+ //IORX_DRX22 = ( 0x0000E2 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_MHB) ),
+ // #if MD_DRV_IS_2G_EXTERNAL_LNA_SUPPORT
+ //IORX_DRX1_ELNA = ( 0x000021 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX2_ELNA = ( 0x000041 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX3_ELNA = ( 0x000061 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX4_ELNA = ( 0x0000A1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX5_ELNA = ( 0x0000C1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX6_ELNA = ( 0x0000E1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX7_ELNA = ( 0x000042 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX8_ELNA = ( 0x000022 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX9_ELNA = ( 0x0000E2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX10_ELNA = ( 0x0000C2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX11_ELNA = ( 0x0000A2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX12_ELNA = ( 0x000021 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX13_ELNA = ( 0x000041 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX14_ELNA = ( 0x000061 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX15_ELNA = ( 0x000081 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX16_ELNA = ( 0x0000A1 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX17_ELNA = ( 0x0000C1 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_LMB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX18_ELNA = ( 0x000042 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX19_ELNA = ( 0x000022 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX20_ELNA = ( 0x0000A2 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX21_ELNA = ( 0x0000C2 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ //IORX_DRX22_ELNA = ( 0x0000E2 | (IORX_DIVERSITY) | (IORX_RFIC1) | (IORX_LNA_MHB) | (IORX_ELNA_USAGE) ),
+ // #endif
+}GGE_IORX_E;
+ #elif MD_DRV_IS_RF_MT6177L
+/*---------------------------------------------------------------*/
+/* Primary RX Path (bit[20]=0: Primarary) */
+/* Primary RX Path (bit[21]=Reserved for future extension) */
+/* Primary RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+/* Primary RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+/* Primary RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+/* Diversity RX Path (bit[20]=1: Diversity) */
+/* Diversity RX Path (bit[21]=Reserved for future extension) */
+/* Diversity RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+/* Diversity RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+/* Diversity RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+/*---------------------------------------------------------------*/
+#define IORX_PATH_LSB 20
+#define IORX_RFIC_LSB 22
+#define IORX_LNA_GROUP_LSB 23
+#define IORX_ELNA_ROUTE 24 // keep index for MML1_FE_ELNA_ROUTE_E from bit[24] to bit[28]
+
+#define IORX_PRIMARY (0<<IORX_PATH_LSB)
+#define IORX_DIVERSITY (1<<IORX_PATH_LSB)
+
+#define IORX_RFIC0 (0<<IORX_RFIC_LSB)
+#define IORX_RFIC1 (1<<IORX_RFIC_LSB)
+
+#define IORX_LNA_LMB (0<<IORX_LNA_GROUP_LSB)
+#define IORX_LNA_MHB (1<<IORX_LNA_GROUP_LSB)
+
+#define IORX_LNASEL_LNA0 0
+#define IORX_LNASEL_LNA1 1
+#define IORX_LNASEL_LNA2 2
+#define IORX_LNASEL_LNA3 3
+#define IORX_LNASEL_LNA4 4
+#define IORX_LNASEL_LNA5 5
+#define IORX_LNASEL_LNA6 6
+#define IORX_LNASEL_LNA7 7
+
+
+#define L1D_RF_ELNA_PDATABASE_SETTING(b,s)\
+ b##_##s=(b | (s<<IORX_ELNA_ROUTE) )
+
+#define L1D_RF_ELNA_PDATABASE_LIST(b)\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA_NONE),\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA1), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA2), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA3), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA4), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA5), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA6), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA7), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA8), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA9), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA10), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA11), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA12)
+
+typedef enum
+{
+/* PRX */
+ IORX_PRX1 = ( IORX_LNASEL_LNA0 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX2 = ( IORX_LNASEL_LNA1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX3 = ( IORX_LNASEL_LNA2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX4 = ( IORX_LNASEL_LNA3 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX5 = ( IORX_LNASEL_LNA5 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX6 = ( IORX_LNASEL_LNA4 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX7 = ( IORX_LNASEL_LNA7 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX8 = ( IORX_LNASEL_LNA6 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX9 = ( IORX_LNASEL_LNA0 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PRX10 = ( IORX_LNASEL_LNA1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PRX11 = ( IORX_LNASEL_LNA2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PRX12 = ( IORX_LNASEL_LNA3 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PRX13 = ( IORX_LNASEL_LNA5 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PRX14 = ( IORX_LNASEL_LNA4 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+
+ /* DRX */
+ IORX_DRX1 = ( IORX_LNASEL_LNA0 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX2 = ( IORX_LNASEL_LNA1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX3 = ( IORX_LNASEL_LNA2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX4 = ( IORX_LNASEL_LNA3 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX5 = ( IORX_LNASEL_LNA5 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX6 = ( IORX_LNASEL_LNA4 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX7 = ( IORX_LNASEL_LNA6 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX8 = ( IORX_LNASEL_LNA7 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX9 = ( IORX_LNASEL_LNA1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DRX10 = ( IORX_LNASEL_LNA0 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DRX11 = ( IORX_LNASEL_LNA2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DRX12 = ( IORX_LNASEL_LNA3 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DRX13 = ( IORX_LNASEL_LNA4 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DRX14 = ( IORX_LNASEL_LNA5 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+
+#if MD_DRV_IS_2G_EXTERNAL_LNA_SUPPORT
+ /* PRX */
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX10),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX11),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX12),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX13),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX14),
+
+ /* DRX */
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX10),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX11),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX12),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX13),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX14),
+#endif
+ //#if MD_DRV_IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT
+ //#endif
+}GGE_IORX_E;
+ #elif MD_DRV_IS_RF_MT6177M
+ /*---------------------------------------------------------------*/
+ /* Primary RX Path (bit[20]=0: Primarary) */
+ /* Primary RX Path (bit[21]=Reserved for future extension) */
+ /* Primary RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+ /* Primary RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+ /* Primary RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+ /* Diversity RX Path (bit[20]=1: Diversity) */
+ /* Diversity RX Path (bit[21]=Reserved for future extension) */
+ /* Diversity RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+ /* Diversity RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+ /* Diversity RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+ /*---------------------------------------------------------------*/
+#define IORX_PATH_LSB 20
+#define IORX_RFIC_LSB 22
+#define IORX_LNA_GROUP_LSB 23
+#define IORX_ELNA_ROUTE 24
+
+#define IORX_PRIMARY (0<<IORX_PATH_LSB)
+#define IORX_DIVERSITY (1<<IORX_PATH_LSB)
+
+#define IORX_RFIC0 (0<<IORX_RFIC_LSB)
+#define IORX_RFIC1 (1<<IORX_RFIC_LSB)
+
+#define IORX_LNA_LMB (0<<IORX_LNA_GROUP_LSB)
+#define IORX_LNA_MHB (1<<IORX_LNA_GROUP_LSB)
+
+#define IORX_LNASEL_LNA0 0
+#define IORX_LNASEL_LNA1 1
+#define IORX_LNASEL_LNA2 3
+#define IORX_LNASEL_LNA3 4
+#define IORX_LNASEL_LNA4 5
+#define IORX_LNASEL_LNA5 6
+#define IORX_LNASEL_LNA6 7
+#define IORX_LNASEL_LNA7 8
+#define IORX_LNASEL_LNA8 9
+#define IORX_LNASEL_LNA9 10
+#define IORX_LNASEL_LNA10 2
+
+#define L1D_RF_ELNA_PDATABASE_SETTING(b,s)\
+ b##_##s=(b | (s<<IORX_ELNA_ROUTE) )
+
+#define L1D_RF_ELNA_PDATABASE_LIST(b)\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA_NONE),\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA1), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA2), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA3), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA4), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA5), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA6), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA7), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA8), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA9), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA10), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA11), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA12)
+
+typedef enum
+{
+ /* PRX */
+ IORX_PRX1 = ( IORX_LNASEL_LNA1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX2 = ( IORX_LNASEL_LNA2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX3 = ( IORX_LNASEL_LNA3 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX4 = ( IORX_LNASEL_LNA4 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX5 = ( IORX_LNASEL_LNA5 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX6 = ( IORX_LNASEL_LNA6 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX7 = ( IORX_LNASEL_LNA7 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX8 = ( IORX_LNASEL_LNA8 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_PRX9 = ( IORX_LNASEL_LNA9 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PRX10 = ( IORX_LNASEL_LNA10 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+
+ /* DRX */
+ IORX_DRX1 = ( IORX_LNASEL_LNA1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX2 = ( IORX_LNASEL_LNA2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX3 = ( IORX_LNASEL_LNA3 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX4 = ( IORX_LNASEL_LNA4 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX5 = ( IORX_LNASEL_LNA5 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX6 = ( IORX_LNASEL_LNA6 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX7 = ( IORX_LNASEL_LNA7 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX8 = ( IORX_LNASEL_LNA8 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LMB) ),
+ IORX_DRX9 = ( IORX_LNASEL_LNA9 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DRX10 = ( IORX_LNASEL_LNA10 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+#if MD_DRV_IS_2G_EXTERNAL_LNA_SUPPORT
+ /* PRX */
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PRX10),
+
+ /* DRX */
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DRX10),
+
+#endif
+
+}GGE_IORX_E;
+ #elif MD_DRV_IS_RF_TRINITYE1
+ /*---------------------------------------------------------------*/
+ /* Primary RX Path (bit[20]=0: Primarary) */
+ /* Primary RX Path (bit[21]=Reserved for future extension) */
+ /* Primary RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+ /* Primary RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+ /* Primary RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+ /* Diversity RX Path (bit[20]=1: Diversity) */
+ /* Diversity RX Path (bit[21]=Reserved for future extension) */
+ /* Diversity RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+ /* Diversity RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+ /* Diversity RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+ /*---------------------------------------------------------------*/
+#define IORX_PATH_LSB 20
+#define IORX_RFIC_LSB 22
+#define IORX_LNA_GROUP_LSB 23
+#define IORX_ELNA_ROUTE 24 // keep index for MML1_FE_ELNA_ROUTE_E from bit[24] to bit[28]
+
+#define IORX_PRIMARY (0<<IORX_PATH_LSB)
+#define IORX_DIVERSITY (1<<IORX_PATH_LSB)
+
+#define IORX_RFIC0 (0<<IORX_RFIC_LSB)
+#define IORX_RFIC1 (1<<IORX_RFIC_LSB)
+
+#define IORX_LNA_LB (0<<IORX_LNA_GROUP_LSB)
+#define IORX_LNA_MHB (1<<IORX_LNA_GROUP_LSB)
+
+/*---------------------------------------------------------*/
+/* Copy from MMRF HAL file (mml1_rf_hal_general_def.h) */
+/*---------------------------------------------------------*/
+/* primary RX port enum */
+typedef enum
+{
+ HAL_RX_PMHB1,
+ HAL_RX_PMHB2,
+ HAL_RX_PMHB3,
+ HAL_RX_PMHB4,
+ HAL_RX_PMHB5,
+ HAL_RX_PMHB6,
+ HAL_RX_PMHB7,
+ HAL_RX_PMHB8,
+ HAL_RX_PMHB9,
+ HAL_RX_PMHB10,
+ HAL_RX_PUHBLAA1,
+ HAL_RX_PUHBLAA2,
+ HAL_RX_PLB1,
+ HAL_RX_PLB2,
+ HAL_RX_PLB3,
+ HAL_RX_PLB4,
+ HAL_RX_PLB5,
+ HAL_RX_PLB6,
+} L1D_RXP_PORT_E;
+
+/* divisity RX port enum */
+typedef enum
+{
+ HAL_RX_DMHB1,
+ HAL_RX_DMHB2,
+ HAL_RX_DMHB3,
+ HAL_RX_DMHB4,
+ HAL_RX_DMHB5,
+ HAL_RX_DMHB6,
+ HAL_RX_DMHB7,
+ HAL_RX_DMHB8,
+ HAL_RX_DMHB9,
+ HAL_RX_DMHB10,
+ HAL_RX_DUHBLAA1,
+ HAL_RX_DUHBLAA2,
+ HAL_RX_DLB1,
+ HAL_RX_DLB2,
+ HAL_RX_DLB3,
+ HAL_RX_DLB4,
+} L1D_RXD_PORT_E;
+/*---------------------------------------------------------*/
+
+
+#define L1D_RF_ELNA_PDATABASE_SETTING(b,s)\
+ b##_##s=(b | (s<<IORX_ELNA_ROUTE) )
+
+#define L1D_RF_ELNA_PDATABASE_LIST(b)\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA_NONE),\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA1), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA2), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA3), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA4), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA5), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA6), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA7), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA8), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA9), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA10), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA11), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA12), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA13), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA14), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA15), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA16), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA17), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA18), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA19), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA20), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA21), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA22), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA23), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA24), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA25), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA26), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA27), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA28), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA29), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA30), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA31), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA32)
+
+/*---------------------------------------------------------*/
+/* PRX LNA port mapping */
+/*---------------------------------------------------------*/
+
+
+
+ typedef enum
+ { //PRX LNA port mapping
+ IORX_PMHB1 = ( HAL_RX_PMHB1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB2 = ( HAL_RX_PMHB2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB3 = ( HAL_RX_PMHB3 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB4 = ( HAL_RX_PMHB4 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB5 = ( HAL_RX_PMHB5 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB6 = ( HAL_RX_PMHB6 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB7 = ( HAL_RX_PMHB7 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB8 = ( HAL_RX_PMHB8 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB9 = ( HAL_RX_PMHB9 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB10 = ( HAL_RX_PMHB10 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PUHBLAA1 = ( HAL_RX_PUHBLAA1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PUHBLAA2 = ( HAL_RX_PUHBLAA2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PLB1 = ( HAL_RX_PLB1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB2 = ( HAL_RX_PLB2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB3 = ( HAL_RX_PLB3 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB4 = ( HAL_RX_PLB4 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB5 = ( HAL_RX_PLB5 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB6 = ( HAL_RX_PLB6 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+
+ //DRX LNA port mapping
+ IORX_DMHB1 = ( HAL_RX_DMHB1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB2 = ( HAL_RX_DMHB2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB3 = ( HAL_RX_DMHB3 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB4 = ( HAL_RX_DMHB4 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB5 = ( HAL_RX_DMHB5 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB6 = ( HAL_RX_DMHB6 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB7 = ( HAL_RX_DMHB7 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB8 = ( HAL_RX_DMHB8 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB9 = ( HAL_RX_DMHB9 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB10 = ( HAL_RX_DMHB10 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DUHBLAA1 = ( HAL_RX_DUHBLAA1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DUHBLAA2 = ( HAL_RX_DUHBLAA2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DLB1 = ( HAL_RX_DLB1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB2 = ( HAL_RX_DLB2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB3 = ( HAL_RX_DLB3 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB4 = ( HAL_RX_DLB4 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+
+ #if MD_DRV_IS_2G_EXTERNAL_LNA_SUPPORT
+ //PRX part ELNA
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB10),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PUHBLAA1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PUHBLAA2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB6),
+
+
+ //DRX part ELNA
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB10),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DUHBLAA1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DUHBLAA2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB4),
+
+ #endif
+ //#if MD_DRV_IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT
+ //#endif
+ }GGE_IORX_E;
+ #elif MD_DRV_IS_RF_TRINITYL
+ /*---------------------------------------------------------------*/
+ /* Primary RX Path (bit[20]=0: Primarary) */
+ /* Primary RX Path (bit[21]=Reserved for future extension) */
+ /* Primary RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+ /* Primary RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+ /* Primary RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+ /* Diversity RX Path (bit[20]=1: Diversity) */
+ /* Diversity RX Path (bit[21]=Reserved for future extension) */
+ /* Diversity RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+ /* Diversity RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+ /* Diversity RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+ /*---------------------------------------------------------------*/
+#define IORX_PATH_LSB 20
+#define IORX_RFIC_LSB 22
+#define IORX_LNA_GROUP_LSB 23
+#define IORX_ELNA_ROUTE 24 // keep index for MML1_FE_ELNA_ROUTE_E from bit[24] to bit[28]
+
+#define IORX_PRIMARY (0<<IORX_PATH_LSB)
+#define IORX_DIVERSITY (1<<IORX_PATH_LSB)
+
+#define IORX_RFIC0 (0<<IORX_RFIC_LSB)
+#define IORX_RFIC1 (1<<IORX_RFIC_LSB)
+
+#define IORX_LNA_LB (0<<IORX_LNA_GROUP_LSB)
+#define IORX_LNA_MHB (1<<IORX_LNA_GROUP_LSB)
+
+/*---------------------------------------------------------*/
+/* Copy from MMRF HAL file (mml1_rf_hal_general_def.h) */
+/*---------------------------------------------------------*/
+/* primary RX port enum */
+typedef enum
+{
+ HAL_RX_PMHB1,
+ HAL_RX_PMHB2,
+ HAL_RX_PMHB3,
+ HAL_RX_PMHB4,
+ HAL_RX_PMHB5,
+ HAL_RX_PMHB6,
+ HAL_RX_PMHB7,
+ HAL_RX_PMHB8,
+ HAL_RX_PMHB9,
+ HAL_RX_PMHB10,
+ HAL_RX_PUHBLAA1,
+ HAL_RX_PUHBLAA2,
+ HAL_RX_PLB1,
+ HAL_RX_PLB2,
+ HAL_RX_PLB3,
+ HAL_RX_PLB4,
+ HAL_RX_PLB5,
+ HAL_RX_PLB6,
+} L1D_RXP_PORT_E;
+
+/* divisity RX port enum */
+typedef enum
+{
+ HAL_RX_DMHB1,
+ HAL_RX_DMHB2,
+ HAL_RX_DMHB3,
+ HAL_RX_DMHB4,
+ HAL_RX_DMHB5,
+ HAL_RX_DMHB6,
+ HAL_RX_DMHB7,
+ HAL_RX_DMHB8,
+ HAL_RX_DMHB9,
+ HAL_RX_DMHB10,
+ HAL_RX_DUHBLAA1,
+ HAL_RX_DUHBLAA2,
+ HAL_RX_DLB1,
+ HAL_RX_DLB2,
+ HAL_RX_DLB3,
+ HAL_RX_DLB4,
+ HAL_RX_DLB5, // new add for TrinityL
+} L1D_RXD_PORT_E;
+/*---------------------------------------------------------*/
+
+
+#define L1D_RF_ELNA_PDATABASE_SETTING(b,s)\
+ b##_##s=(b | (s<<IORX_ELNA_ROUTE) )
+
+#define L1D_RF_ELNA_PDATABASE_LIST(b)\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA_NONE),\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA1), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA2), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA3), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA4), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA5), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA6), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA7), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA8), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA9), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA10), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA11), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA12), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA13), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA14), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA15), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA16), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA17), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA18), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA19), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA20), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA21), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA22), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA23), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA24), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA25), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA26), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA27), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA28), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA29), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA30), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA31), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA32)
+
+/*---------------------------------------------------------*/
+/* PRX LNA port mapping */
+/*---------------------------------------------------------*/
+
+
+
+ typedef enum
+ { //PRX LNA port mapping
+ IORX_PMHB1 = ( HAL_RX_PMHB1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB2 = ( HAL_RX_PMHB2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB3 = ( HAL_RX_PMHB3 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB4 = ( HAL_RX_PMHB4 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB5 = ( HAL_RX_PMHB5 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB6 = ( HAL_RX_PMHB6 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB7 = ( HAL_RX_PMHB7 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB8 = ( HAL_RX_PMHB8 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB9 = ( HAL_RX_PMHB9 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB10 = ( HAL_RX_PMHB10 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PUHBLAA1 = ( HAL_RX_PUHBLAA1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PUHBLAA2 = ( HAL_RX_PUHBLAA2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PLB1 = ( HAL_RX_PLB1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB2 = ( HAL_RX_PLB2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB3 = ( HAL_RX_PLB3 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB4 = ( HAL_RX_PLB4 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB5 = ( HAL_RX_PLB5 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB6 = ( HAL_RX_PLB6 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+
+ //DRX LNA port mapping
+ IORX_DMHB1 = ( HAL_RX_DMHB1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB2 = ( HAL_RX_DMHB2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB3 = ( HAL_RX_DMHB3 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB4 = ( HAL_RX_DMHB4 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB5 = ( HAL_RX_DMHB5 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB6 = ( HAL_RX_DMHB6 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB7 = ( HAL_RX_DMHB7 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB8 = ( HAL_RX_DMHB8 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB9 = ( HAL_RX_DMHB9 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB10 = ( HAL_RX_DMHB10 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DUHBLAA1 = ( HAL_RX_DUHBLAA1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DUHBLAA2 = ( HAL_RX_DUHBLAA2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DLB1 = ( HAL_RX_DLB1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB2 = ( HAL_RX_DLB2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB3 = ( HAL_RX_DLB3 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB4 = ( HAL_RX_DLB4 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB5 = ( HAL_RX_DLB5 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+
+ #if MD_DRV_IS_2G_EXTERNAL_LNA_SUPPORT
+ //PRX part ELNA
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB10),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PUHBLAA1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PUHBLAA2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB6),
+
+ //DRX part ELNA
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB10),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DUHBLAA1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DUHBLAA2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB5),
+ #endif
+ //#if MD_DRV_IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT
+ //#endif
+ }GGE_IORX_E;
+
+#elif MD_DRV_IS_RF_MT6186
+ /*---------------------------------------------------------------*/
+ /* Primary RX Path (bit[20]=0: Primarary) */
+ /* Primary RX Path (bit[21]=Reserved for future extension) */
+ /* Primary RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+ /* Primary RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+ /* Primary RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+ /* Diversity RX Path (bit[20]=1: Diversity) */
+ /* Diversity RX Path (bit[21]=Reserved for future extension) */
+ /* Diversity RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+ /* Diversity RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+ /* Diversity RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+ /*---------------------------------------------------------------*/
+#define IORX_PATH_LSB 20
+#define IORX_RFIC_LSB 22
+#define IORX_LNA_GROUP_LSB 23
+#define IORX_ELNA_ROUTE 24 // keep index for MML1_FE_ELNA_ROUTE_E from bit[24] to bit[28]
+
+#define IORX_PRIMARY (0<<IORX_PATH_LSB)
+#define IORX_DIVERSITY (1<<IORX_PATH_LSB)
+
+#define IORX_RFIC0 (0<<IORX_RFIC_LSB)
+#define IORX_RFIC1 (1<<IORX_RFIC_LSB)
+
+#define IORX_LNA_LB (0<<IORX_LNA_GROUP_LSB)
+#define IORX_LNA_MHB (1<<IORX_LNA_GROUP_LSB)
+
+/*---------------------------------------------------------*/
+/* Copy from MMRF HAL file (mml1_rf_hal_general_def.h) */
+/*---------------------------------------------------------*/
+/* primary RX port enum */
+typedef enum
+{
+ HAL_RX_PMHB1,
+ HAL_RX_PMHB2,
+ HAL_RX_PMHB3,
+ HAL_RX_PMHB4,
+ HAL_RX_PMHB5,
+ HAL_RX_PMHB6,
+ HAL_RX_PMHB7,
+ HAL_RX_PMHB8,
+ HAL_RX_PMHB9,
+ HAL_RX_PMHB10,
+ HAL_RX_PUHBLAA1,
+ HAL_RX_PUHBLAA2,
+ HAL_RX_PLB1,
+ HAL_RX_PLB2,
+ HAL_RX_PLB3,
+ HAL_RX_PLB4,
+ HAL_RX_PLB5,
+ HAL_RX_PLB6,
+} L1D_RXP_PORT_E;
+
+/* divisity RX port enum */
+typedef enum
+{
+ HAL_RX_DMHB1,
+ HAL_RX_DMHB2,
+ HAL_RX_DMHB3,
+ HAL_RX_DMHB4,
+ HAL_RX_DMHB5,
+ HAL_RX_DMHB6,
+ HAL_RX_DMHB7,
+ HAL_RX_DMHB8,
+ HAL_RX_DMHB9,
+ HAL_RX_DMHB10,
+ HAL_RX_DUHBLAA1,
+ HAL_RX_DUHBLAA2,
+ HAL_RX_DLB1,
+ HAL_RX_DLB2,
+ HAL_RX_DLB3,
+ HAL_RX_DLB4,
+ HAL_RX_DLB5, // new add for TrinityL
+} L1D_RXD_PORT_E;
+/*---------------------------------------------------------*/
+
+
+#define L1D_RF_ELNA_PDATABASE_SETTING(b,s)\
+ b##_##s=(b | (s<<IORX_ELNA_ROUTE) )
+
+#define L1D_RF_ELNA_PDATABASE_LIST(b)\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA_NONE),\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA1), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA2), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA3), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA4), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA5), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA6), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA7), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA8), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA9), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA10), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA11), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA12), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA13), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA14), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA15), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA16), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA17), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA18), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA19), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA20), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA21), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA22), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA23), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA24), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA25), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA26), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA27), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA28), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA29), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA30), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA31), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA32)
+
+/*---------------------------------------------------------*/
+/* PRX LNA port mapping */
+/*---------------------------------------------------------*/
+
+
+
+ typedef enum
+ { //PRX LNA port mapping
+ IORX_PMHB1 = ( HAL_RX_PMHB1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB2 = ( HAL_RX_PMHB2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB3 = ( HAL_RX_PMHB3 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB4 = ( HAL_RX_PMHB4 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB5 = ( HAL_RX_PMHB5 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB6 = ( HAL_RX_PMHB6 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB7 = ( HAL_RX_PMHB7 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB8 = ( HAL_RX_PMHB8 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB9 = ( HAL_RX_PMHB9 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB10 = ( HAL_RX_PMHB10 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PUHBLAA1 = ( HAL_RX_PUHBLAA1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PUHBLAA2 = ( HAL_RX_PUHBLAA2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PLB1 = ( HAL_RX_PLB1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB2 = ( HAL_RX_PLB2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB3 = ( HAL_RX_PLB3 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB4 = ( HAL_RX_PLB4 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB5 = ( HAL_RX_PLB5 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB6 = ( HAL_RX_PLB6 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+
+ //DRX LNA port mapping
+ IORX_DMHB1 = ( HAL_RX_DMHB1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB2 = ( HAL_RX_DMHB2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB3 = ( HAL_RX_DMHB3 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB4 = ( HAL_RX_DMHB4 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB5 = ( HAL_RX_DMHB5 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB6 = ( HAL_RX_DMHB6 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB7 = ( HAL_RX_DMHB7 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB8 = ( HAL_RX_DMHB8 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB9 = ( HAL_RX_DMHB9 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB10 = ( HAL_RX_DMHB10 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DUHBLAA1 = ( HAL_RX_DUHBLAA1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DUHBLAA2 = ( HAL_RX_DUHBLAA2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DLB1 = ( HAL_RX_DLB1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB2 = ( HAL_RX_DLB2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB3 = ( HAL_RX_DLB3 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB4 = ( HAL_RX_DLB4 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB5 = ( HAL_RX_DLB5 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+
+ #if MD_DRV_IS_2G_EXTERNAL_LNA_SUPPORT
+ //PRX part ELNA
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB10),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PUHBLAA1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PUHBLAA2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB6),
+
+ //DRX part ELNA
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB10),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DUHBLAA1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DUHBLAA2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB5),
+ #endif
+ //#if MD_DRV_IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT
+ //#endif
+ }GGE_IORX_E;
+
+
+
+#elif MD_DRV_IS_RF_MT6186M
+ /*---------------------------------------------------------------*/
+ /* Primary RX Path (bit[20]=0: Primarary) */
+ /* Primary RX Path (bit[21]=Reserved for future extension) */
+ /* Primary RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+ /* Primary RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+ /* Primary RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+ /* Diversity RX Path (bit[20]=1: Diversity) */
+ /* Diversity RX Path (bit[21]=Reserved for future extension) */
+ /* Diversity RX Path (bit[22]=0: RFIC1, bit[22]=1: RFIC2) */
+ /* Diversity RX Path (bit[23]=0: LNA LMB, bit[23]=1: LNA MHB) */
+ /* Diversity RX Path (bit[24]=0: w/o eLNA, bit[24]=1: w/ eLNA) */
+ /*---------------------------------------------------------------*/
+#define IORX_PATH_LSB 20
+#define IORX_RFIC_LSB 22
+#define IORX_LNA_GROUP_LSB 23
+#define IORX_ELNA_ROUTE 24 // keep index for MML1_FE_ELNA_ROUTE_E from bit[24] to bit[28]
+
+#define IORX_PRIMARY (0<<IORX_PATH_LSB)
+#define IORX_DIVERSITY (1<<IORX_PATH_LSB)
+
+#define IORX_RFIC0 (0<<IORX_RFIC_LSB)
+#define IORX_RFIC1 (1<<IORX_RFIC_LSB)
+
+#define IORX_LNA_LB (0<<IORX_LNA_GROUP_LSB)
+#define IORX_LNA_MHB (1<<IORX_LNA_GROUP_LSB)
+
+ /*---------------------------------------------------------*/
+ /* Copy from MMRF HAL file (mml1_rf_hal_general_def.h) */
+ /*---------------------------------------------------------*/
+ /* primary RX port enum */
+ typedef enum
+ {
+ HAL_RX_PMHB1,
+ HAL_RX_PMHB2,
+ HAL_RX_PMHB3,
+ HAL_RX_PMHB4,
+ HAL_RX_PMHB5,
+ HAL_RX_PMHB6,
+ HAL_RX_PMHB7,
+ HAL_RX_PMHB8,
+ HAL_RX_PMHB9,
+ HAL_RX_PMHB10,
+ HAL_RX_PUHBLAA1,
+ HAL_RX_PUHBLAA2,
+ HAL_RX_PLB1,
+ HAL_RX_PLB2,
+ HAL_RX_PLB3,
+ HAL_RX_PLB4,
+ HAL_RX_PLB5,
+ HAL_RX_PLB6,
+ } L1D_RXP_PORT_E;
+
+ /* divisity RX port enum */
+ typedef enum
+ {
+ HAL_RX_DMHB1,
+ HAL_RX_DMHB2,
+ HAL_RX_DMHB3,
+ HAL_RX_DMHB4,
+ HAL_RX_DMHB5,
+ HAL_RX_DMHB6,
+ HAL_RX_DMHB7,
+ HAL_RX_DMHB8,
+ HAL_RX_DMHB9,
+ HAL_RX_DMHB10,
+ HAL_RX_DUHBLAA1,
+ HAL_RX_DUHBLAA2,
+ HAL_RX_DLB1,
+ HAL_RX_DLB2,
+ HAL_RX_DLB3,
+ HAL_RX_DLB4,
+ HAL_RX_DLB5, // new add for TrinityL
+ } L1D_RXD_PORT_E;
+ /*---------------------------------------------------------*/
+
+
+#define L1D_RF_ELNA_PDATABASE_SETTING(b,s)\
+ b##_##s=(b | (s<<IORX_ELNA_ROUTE) )
+
+#define L1D_RF_ELNA_PDATABASE_LIST(b)\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA_NONE),\
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA1), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA2), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA3), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA4), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA5), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA6), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA7), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA8), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA9), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA10), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA11), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA12), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA13), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA14), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA15), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA16), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA17), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA18), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA19), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA20), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA21), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA22), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA23), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA24), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA25), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA26), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA27), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA28), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA29), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA30), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA31), \
+ L1D_RF_ELNA_PDATABASE_SETTING(b,MML1_FE_ELNA32)
+
+ /*---------------------------------------------------------*/
+ /* PRX LNA port mapping */
+ /*---------------------------------------------------------*/
+
+
+
+ typedef enum
+ { //PRX LNA port mapping
+ IORX_PMHB1 = ( HAL_RX_PMHB1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB2 = ( HAL_RX_PMHB2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB3 = ( HAL_RX_PMHB3 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB4 = ( HAL_RX_PMHB4 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB5 = ( HAL_RX_PMHB5 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB6 = ( HAL_RX_PMHB6 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB7 = ( HAL_RX_PMHB7 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB8 = ( HAL_RX_PMHB8 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB9 = ( HAL_RX_PMHB9 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PMHB10 = ( HAL_RX_PMHB10 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PUHBLAA1 = ( HAL_RX_PUHBLAA1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PUHBLAA2 = ( HAL_RX_PUHBLAA2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_PLB1 = ( HAL_RX_PLB1 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB2 = ( HAL_RX_PLB2 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB3 = ( HAL_RX_PLB3 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB4 = ( HAL_RX_PLB4 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB5 = ( HAL_RX_PLB5 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_PLB6 = ( HAL_RX_PLB6 | (IORX_PRIMARY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+
+ //DRX LNA port mapping
+ IORX_DMHB1 = ( HAL_RX_DMHB1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB2 = ( HAL_RX_DMHB2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB3 = ( HAL_RX_DMHB3 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB4 = ( HAL_RX_DMHB4 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB5 = ( HAL_RX_DMHB5 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB6 = ( HAL_RX_DMHB6 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB7 = ( HAL_RX_DMHB7 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB8 = ( HAL_RX_DMHB8 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB9 = ( HAL_RX_DMHB9 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DMHB10 = ( HAL_RX_DMHB10 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DUHBLAA1 = ( HAL_RX_DUHBLAA1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DUHBLAA2 = ( HAL_RX_DUHBLAA2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_MHB) ),
+ IORX_DLB1 = ( HAL_RX_DLB1 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB2 = ( HAL_RX_DLB2 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB3 = ( HAL_RX_DLB3 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB4 = ( HAL_RX_DLB4 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+ IORX_DLB5 = ( HAL_RX_DLB5 | (IORX_DIVERSITY) | (IORX_RFIC0) | (IORX_LNA_LB) ),
+
+ #if MD_DRV_IS_2G_EXTERNAL_LNA_SUPPORT
+ //PRX part ELNA
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PMHB10),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PUHBLAA1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PUHBLAA2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_PLB6),
+
+ //DRX part ELNA
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB5),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB6),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB7),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB8),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB9),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DMHB10),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DUHBLAA1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DUHBLAA2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB1),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB2),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB3),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB4),
+ L1D_RF_ELNA_PDATABASE_LIST(IORX_DLB5),
+ #endif
+ //#if MD_DRV_IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT
+ //#endif
+ }GGE_IORX_E;
+
+ #endif
+
+#endif /*End of #if MD_DRV_IS_RF_MT6176 || MD_DRV_IS_RF_MT6179 || MD_DRV_IS_RF_MT6177L || MD_DRV_IS_RF_TRINITYE1|| MD_DRV_IS_RF_MT6177M */
+
+
+/*---------------------------------------------------------------------------*/
+#endif /*End of "#ifndef _L1D_RF_DATA_COMMON_H_" */
+
diff --git a/mcu/interface/l1/gl1/external/l1d_rf_pcore.h b/mcu/interface/l1/gl1/external/l1d_rf_pcore.h
new file mode 100644
index 0000000..5eba177
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_rf_pcore.h
@@ -0,0 +1,164 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_rf_pcore.h
+ *
+ * Project:
+ * --------
+ * TK6291
+ *
+ * Description:
+ * ------------
+ * RF constance defintion
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ * 10 01 2018 tim.tsai
+ * [MOLY00356374] [Gen97][GL1D] 2G RFD porting
+ * .[Vmoly] Or RF option MT6190T
+ *
+ * 09 20 2018 rick.lee
+ * [MOLY00346462] [GL1D][RF]merge UMOLYE patch back to VMOLY
+ *
+ * 09 10 2018 rick.lee
+ * [MOLY00346462] [GL1D][RF][Gen95] Trinity2L 2G porting
+ * .Trinity2L patch back to UMOLYE
+ *
+ * 08 06 2018 rick.lee
+ * [MOLY00340337] [GL1D][RFD][Gen95] TrinityL-E2 2G porting
+ * .TrinityLE2 Dev patch back to UMOLYE
+ * 08 02 2018 rick.lee
+ * [MOLY00340337][GL1D][RF] TrinityLE2 Dev patch back to UMOLYE
+ *
+ * 07 20 2018 rick.lee
+ * [MOLY00340337] [GL1D][RFD][Gen95] TrinityL-E2 2G porting
+ * [GL1D][RFD][Gen95] TrinityL-E2 2G RF porting
+ *
+ * 12 26 2017 tim.tsai
+ * [MOLY00296149] [MT6295][GL1D] 2G Trinity L porting
+ * .
+ *
+ * 11 10 2017 tim.tsai
+ * [MOLY00288931] [MT6295][L1D] 2G TRINITY E1 RFD
+ * .
+ *
+ * 06 12 2017 tim.tsai
+ * [MOLY00256723] [UMOLYA][ZION][L1D] MT6177M 2G RF Driver
+ * .
+ *
+ * 01 06 2017 silvers.peng
+ * [MOLY00223254] [L1D]Bianco BB RF Driver check in 1st wave
+ * .
+ *
+ * 03 15 2016 yw.chen
+ * [MOLY00169087] [L1D] MT6179 2G RF Driver Modification
+ * .
+ *
+ * 03 10 2016 dou.ju
+ * [MOLY00168285] [GL1D RF]DRDI feature
+ *
+ * .
+ *
+ * 06 18 2015 prakash.chaudhary
+ * [MOLY00122406] [L1D][modify]Check in BB driver for Jade BB porting
+ * .
+ *
+ * 05 29 2015 sherman.chung
+ * [MOLY00116464] [UMOLY] 2G L1 TAS Check in
+ * .
+ *
+ * 04 24 2015 ola.lee
+ * [MOLY00091988] [L1D] Update MT6176 2G RF Driver
+ * .
+ *
+ * 04 24 2015 ola.lee
+ * [MOLY00091988] [L1D] Update MT6176 2G RF Driver-Update TX Propagation Dely.
+ *
+ * 04 24 2015 ola.lee
+ * [MOLY00091988] [L1D] Update MT6176 2G RF Driver
+ * Update TQ_EPSK_TX_DELAY for MT6176.
+ *
+ * 04 15 2015 ola.lee
+ * [MOLY00091988] [L1D] Update MT6176 2G RF Driver
+ * Fix G->8 EDGE TX PVT.
+ *
+ * 02 12 2015 yi-ying.lin
+ * [MOLY00095975] [L1D][Modify] TK6291 CC NVRAM and custom data modification L1D mipi part
+ * .
+ *
+ *
+ *******************************************************************************/
+
+#ifndef _L1D_RF_PCORE_H_
+#define _L1D_RF_PCORE_H_
+/* ------------------------------------------------------------------------- */
+
+#if IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+/*--------------------------------------------------------*/
+/* BFE Setting */
+/*--------------------------------------------------------*/
+ #if IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT
+#define TQ_EPSK_TX_DELAY 8
+ #endif
+#endif
+
+
+#ifndef QB_TX_SAMPLE_OFFSET_GMSK
+#define QB_TX_SAMPLE_OFFSET_GMSK 0
+#endif
+
+#ifndef QB_TX_SAMPLE_OFFSET_EPSK
+#define QB_TX_SAMPLE_OFFSET_EPSK 0
+#endif
+
+
+#ifndef IS_EGSM900_DISABLE
+#define IS_EGSM900_DISABLE 0
+#endif
+
+#endif
+
diff --git a/mcu/interface/l1/gl1/external/l1d_rf_utas_typedef.h b/mcu/interface/l1/gl1/external/l1d_rf_utas_typedef.h
new file mode 100644
index 0000000..ce31008
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_rf_utas_typedef.h
@@ -0,0 +1,170 @@
+/*******************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_rf_utas_typedef.h
+ *
+ * Project:
+ * --------
+ * MT3967
+ *
+ * Description:
+ * ------------
+ * 2G L1D UTAS
+ *
+ * Author:
+ * -------
+ *
+ *
+ *******************************************************************************/
+
+#ifndef _L1D_RF_UTAS_TYPEDEF_H_
+#define _L1D_RF_UTAS_TYPEDEF_H_
+/* ------------------------------------------------------------------------- */
+#include "l1_public_defs.h"
+#include "mml1_fe_public.h"
+#include "l1d_cid.h"
+#if IS_2G_TAS_INHERIT_4G_ANT
+ #ifdef L1_SIM
+ #else
+#include "el1d_rf_band.h"
+ #if defined(__FPGA__) || defined(__MAUI_BASIC__)
+ #else
+#include "el1d_rf_def.h"
+ #endif
+ #endif
+#endif
+
+#if IS_2G_TAS_INHERIT_4G_ANT
+ #if defined(L1_SIM)
+typedef enum{dummy=0xffff} LTE_Band;
+#define L1D_TAS_INHERIT_LTE_BAND_END 0
+#define L1D_TAS_INHERIT_LTE_BAND_MAX_NUM 255
+#define L1D_TAS_INHERIT_LTE_BAND_BITMAP_NUM ((255+1)/32)/* (255+1)/32 = 8 words */
+#define L1D_TAS_INHERIT_LTE_BAND_MAX_UL_CC_NUM 2
+ #else
+#define L1D_TAS_INHERIT_LTE_BAND_END LTE_BandNone
+#define L1D_TAS_INHERIT_LTE_BAND_MAX_NUM LTE_Band_Supported_Max
+#define L1D_TAS_INHERIT_LTE_BAND_BITMAP_NUM ((L1D_TAS_INHERIT_LTE_BAND_MAX_NUM/32)+1)/* ((254/32)+1) = 8 words */
+ #if defined(__FPGA__) || defined(__MAUI_BASIC__)/*LTE says to use own define for FPGA/BASIC build for now*/
+#define L1D_TAS_INHERIT_LTE_BAND_MAX_UL_CC_NUM (2)
+ #else
+#define L1D_TAS_INHERIT_LTE_BAND_MAX_UL_CC_NUM LTE_CA_MAX_UL_CC_NUM
+ #endif
+ #endif
+#define L1D_TAS_INHERIT_LTE_ANT(b,s) L1D_TAS_INHERIT_LTE_ANT_##b##_##s
+#endif
+
+
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#endif /* _L1D_RF_UTAS_TYPEDEF_H_ */
+
diff --git a/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct.h b/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct.h
new file mode 100644
index 0000000..bcde490
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct.h
@@ -0,0 +1,9 @@
+#if (defined __MD93__)
+#include "l1tst_ft_msg_struct_gen93.h"
+#elif (defined __MD95__)
+#include "l1tst_ft_msg_struct_gen95.h"
+#elif (defined __MD97__)||(defined __MD97P__)
+#include "l1tst_ft_msg_struct_gen97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct_gen93.h b/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct_gen93.h
new file mode 100644
index 0000000..65c9657
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct_gen93.h
@@ -0,0 +1,2001 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_ft_msg_struct.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Struct definition of L1TST - FT interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ * 10 09 2018 yungshian.lai
+ * [MOLY00349865] TX POWER OFFSET feature uniform - VMOLY Trunk [ERS00016793].
+ *
+ * 03 30 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE option rename & NSFT swap patch.
+ *
+ * 03 02 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE Trunk TST part.
+ *
+ * 09 08 2017 yungshian.lai
+ * [MOLY00275140] [Bianco] 93 2G Cal Time Reduction Development - UMOLYA - CNF bitmap.
+ *
+ * 09 01 2017 yungshian.lai
+ * [MOLY00275140] [Bianco] 93 2G Cal Time Reduction Development - UMOLYA.
+ *
+ * 07 21 2017 yungshian.lai
+ * [MOLY00266063] [EL1TST] GPS coclock v2.0 Development - 4G Read AuxADC /2G add capability and modify DHL PSTrace - UMOLYA.
+ *
+ * 01 11 2017 yungshian.lai
+ * [MOLY00223923] [Bianco Bring-up][GSM] MT6293 eLNA Development & GPScoclock V2.0.
+ *
+ * 05 03 2016 yungshian.lai
+ * [MOLY00163211] [L1TST] Sawless Development & DTS_STEP_CNT=512
+ * - modify LID VER & Struct naming & uint16 &SetRxNVRAM.
+ *
+ * 01 29 2016 yungshian.lai
+ * [MOLY00163211] [L1TST] Sawless Development & DTS_STEP_CNT=512.
+ *
+ * 06 12 2015 yungshian.lai
+ * [MOLY00121036] [TK6291][L1TST] NSFT list mode send pdu modify
+ * .
+ *
+ * 04 24 2015 yungshian.lai
+ * [MOLY00109190] [TK6291][L1TST] Add lack CMD,trace and modify TADC bitmap.
+ *
+ * 01 03 2014 th.yeh
+ * [MOLY00052308] [L1D][Modify] FT/L1D dual-core modem interface development
+ * .
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_FT_MSG_STRUCT_H_
+#define _L1TST_FT_MSG_STRUCT_H_
+#include "l1_types_public.h"
+//#if IS_2G_RXD_SUPPORT
+#include "ft_msg_common.h" //For L1D read RXD Info struct
+//#endif
+
+/*************************************************************************
+* Include Statements for PLTABLE_SIZE
+ *************************************************************************/
+#include "l1cal.h"
+
+
+/*******************************************************************************
+*
+* Data structures used in Message Definition
+*
+*******************************************************************************/
+
+typedef enum
+{
+ FT_RF_PWR_STATE_UNKNOWN = -1,
+ FT_RF_PWR_STATE_ON,
+ FT_RF_PWR_STATE_OFF,
+}ft_rf_power_state_enum;
+
+typedef enum
+{
+ RF_TEST_CMD_PM = 0
+ ,RF_TEST_CMD_AFC = 1
+ ,RF_TEST_CMD_NB_TX = 2
+ ,RF_TEST_CMD_CONTINUOUS_RX = 3
+ ,RF_TEST_CMD_CONTINUOUS_TX = 4
+ ,RF_TEST_CMD_SET_BB_TX_CFG = 5 //phase out
+ ,RF_TEST_CMD_BAND_SEL = 6
+ ,RF_TEST_CMD_STOP = 7
+ ,RF_TEST_CMD_MULTISLOT_TX = 8
+ ,RF_TEST_CMD_SET_RAMPAPCLVL = 9
+ ,RF_TEST_CMD_SET_AFCDACVALUE = 10 //phase out
+ ,RF_TEST_CMD_SET_BBTXCFG2 = 11 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG2 = 12 //phase out
+ ,RF_TEST_CMD_SET_CRYSTAL_CFG = 13
+ ,RF_TEST_CMD_BBTX_AUTOCAL = 14 //phase out
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY = 15
+ ,RF_TEST_CMD_SET_RAMPTABLE = 16
+ ,RF_TEST_CMD_SET_AFC_SINWAVE_DETECTION = 17
+ ,RF_TEST_CMD_MULTISLOT_TX_EX = 18
+ ,RF_TEST_CMD_EPSK_SET_RAMPAPCLVL = 19
+ ,RF_TEST_CMD_GET_RFID = 20
+ ,RF_TEST_CMD_SET_IMMEDIATE_BSI = 21
+ ,RF_TEST_CMD_GET_IMMEDIATE_BSI = 22
+ ,RF_TEST_CMD_SET_SPECIALCOEF = 23 //phase out
+ ,RF_TEST_CMD_CONTINUOUS_TX_EX = 24
+ ,RF_TEST_CMD_SET_BBTXCFG3 = 25 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG3 = 26 //phase out
+ ,RF_TEST_CMD_IF_TWO_APC_DC_OFFSET_SUPPORT = 27
+ ,RF_TEST_CMD_CONTINUOUS_TX_EX2 = 28
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY_EX = 29
+ ,RF_TEST_CMD_GET_AFCDACVALUE_AT_RTX_OFFSET_CAL = 30
+ ,RF_TEST_CMD_SET_BBTXCFG4 = 31 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG4 = 32 //phase out
+ ,RF_TEST_CMD_SET_BBTXCFG5 = 33 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG5 = 34 //phase out
+ ,RF_TEST_CMD_CALIBRATE_32K = 35
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY_EX2 = 36
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_50P = 37 // including AFC and RX pathloss: downlink //RF_TEST_CMD_START_FDT_DL
+ ,RF_TEST_CMD_START_FDT_UL_50P = 38 // APC calibration :uplink //RF_TEST_CMD_START_FDT_UL
+ ,RF_TEST_CMD_EPSK_SET_RAMPTABLE = 39 //phase out
+ ,RF_TEST_CMD_GET_AFC_DAC_OFFSET = 40 //phase out
+ ,RF_TEST_CMD_SET_AFC_DAC_OFFSET = 41 //phase out
+ ,RF_TEST_CMD_SET_BBTXCFG6 = 42 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG6 = 43 //phase out
+ ,RF_TEST_CMD_GET_FDT_RESULT_50P = 44 //RF_TEST_CMD_GET_FDT_RESULT
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_50P = 45
+ ,RF_TEST_CMD_NSFT_CHANGE_SETTING = 46
+ ,RF_TEST_CMD_NSFT_START = 47
+ ,RF_TEST_CMD_NSFT_STOP = 48
+ ,RF_TEST_CMD_NSFT_CHANGE_POWER = 49 //phase out?
+ ,RF_TEST_CMD_NSFT_START_EPSK_TX = 50
+ ,RF_TEST_CMD_OE_PATTERN_READY = 51
+ ,RF_TEST_CMD_POWER_ON = 52
+ ,RF_TEST_CMD_POWER_OFF = 53
+ ,RF_TEST_CMD_QUERY_POWER_STATE_IN_FT = 54 //phase out?
+ ,RF_TEST_CMD_AFC_TYPE_QUERY_READY = 55
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_GMSK = 56
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_EPSK = 57
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_TABLE_GMSK = 58 //phase out
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_TABLE_EPSK = 59 //phase out
+ ,RF_TEST_CMD_GET_SPECIALCOEF = 60
+ ,RF_TEST_CMD_NSFT_CONFIG_SBER = 61
+ ,RF_TEST_CMD_NSFT_GET_SBER = 62
+ ,RF_TEST_CMD_NSFT_START_RXLEV = 63
+ ,RF_TEST_CMD_NSFT_GET_RXLEV = 64
+ ,RF_TEST_CMD_NSFT_GET_RXQUAL = 65
+ ,RF_TEST_CMD_IF_PM = 66
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_BY_PCL_GMSK = 67 //phase out
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_BY_PCL_EPSK = 68 //phase out
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_GMSK = 69 //phase out
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_EPSK = 70 //phase out
+ ,RF_TEST_CMD_GET_TXPC_SUBBAND_GMSK = 71 //phase out
+ ,RF_TEST_CMD_GET_TXPC_SUBBAND_EPSK = 72 //phase out
+ ,RF_TEST_CMD_GET_TXPC_TEMPERATURE = 73
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY_EX3 = 74
+ /* [LPM CAL] */
+ ,RF_TEST_CMD_SET_DCXO_POWER_MODE = 75 //32k Less
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_50P = 76 //32k Less, Check func is False, open if need //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_EX
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_50P = 77 //32k Less, Check func is False, open if need //RF_TEST_CMD_GET_FDT_RESULT_EX
+ ,RF_TEST_CMD_SET_EDGE_TX_OCT_PA_SPECIAL_COEF = 78
+ ,RF_TEST_CMD_TXPC_CL_RESET_PD_DATA = 79 /**< \brief reset TX power control close loop pd value */
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_100P = 80 //RF_TEST_CMD_START_FDT_DL_BIG
+ ,RF_TEST_CMD_START_FDT_UL_100P = 81 //RF_TEST_CMD_START_FDT_UL_BIG
+ ,RF_TEST_CMD_GET_FDT_RESULT_100P = 82 //RF_TEST_CMD_GET_FDT_RESULT_BIG
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_100P = 83 //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_BIG
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_100P = 84 //32k Less, //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_EX_BIG
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_100P = 85 //32k Less, Check func is False, open if need //RF_TEST_CMD_GET_FDT_RESULT_EX_BIG
+ ,RF_TEST_CMD_MULTISLOT_TX_WITH_AUXADC_READ = 86 /**< \brief TX RF on and read AuxADC at same time for CoTsx */
+ ,RF_TEST_CMD_GAIN_RF_TX = 87 //Marked, open if need /**< \brief EDGE TX gain rf cal */
+ ,RF_TEST_CMD_QUERY_GAIN_RF_NUM = 88 //Marked, open if need /**< \brief Query gain rf target support number (max: 20)*/
+ ,RF_TEST_CMD_GET_BB_POWER_LIST = 89 //Marked, open if need /**< \brief Get BB power list from target */
+ ,RF_TEST_CMD_CHECK_IF_FUNC_EXIST = 90 /**< \brief Reserved. META DLL not send directly */
+ ,RF_TEST_CMD_GET_TEMPERATURE_INFO = 91
+ ,RF_TEST_CMD_SET_DT_PATH_FLAG = 92 /**< \brief Set L1 flag to use second path */
+ ,RF_TEST_CMD_LIST_MODE_NSFT_START = 93 /**< \brief 2G list mode nsft*/
+ ,RF_TEST_CMD_START_FDT_UL_512P = 94 /** reduce UL CMD round trip number*/ //RF_TEST_CMD_START_FDT_UL_BIG_V2
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P = 95 /** For sawless lna mode and reduce DL CMD round trip number*/
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P = 96 /** For sawless lna mode and reduce DL CMD round trip number*/ //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_EX_BIG_V2
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_512P = 97 /** For sawless lna mode and reduce DL CMD round trip number*/
+ ,RF_TEST_CMD_SAWLESS_PM = 98 /** Force LTF on - for sawless lna mode in trad calibration*/
+ ,RF_TEST_CMD_SET_RX_PATH_LOSS = 99 /** FT Set data to runtime var, use flag to decide whether to update NVRAM or not*/
+ ,RF_TEST_CMD_GET_RX_PATH_LOSS = 100 /** FT Get data from runtime var (because runtime var==NVRAM)*/
+ ,RF_TEST_CMD_SET_RX_PATH_LOSS_V3 = 101 //For 93 SET_RX_PATH_LOSS elna+g6, elna bypass+g1 /** FT Set data to runtime var, use flag to decide whether to update NVRAM or not*/
+ ,RF_TEST_CMD_GET_RX_PATH_LOSS_V3 = 102 //For 93 GET_RX_PATH_LOSS elna+g6, elna bypass+g1 /** FT Get data from runtime var (because runtime var==NVRAM)*/
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P_V3 = 103 //Add New CMD, For 6293 compatible with 92 tool procedure - RFTestCmdDTS_Lpm_512P_V3
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P_V3 = 104 //Add New CMD, For 6293 compatible with 92 tool procedure (previous CMD)
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_512P_V3 = 105 //Add New CMD, For 6293 compatible with 92 tool procedure (previous CMD)
+ ,RF_TEST_CMD_SINEWAVE_AFC_GET_TEMP_FREQ = 106 /*For GPS co-clock V2.0, use this CMD to get temperature and freq offset*/
+ ,RF_TEST_CMD_SET_WCOEF = 107 //Cal time reduction development - Wcoef part
+ ,RF_TEST_CMD_GET_WCOEF = 108 //Cal time reduction development - Wcoef part
+ ,RF_TEST_CMD_SET_TXDATA = 109 //Cal time reduction development - Tx part
+ ,RF_TEST_CMD_GET_TXDATA = 110 //Cal time reduction development - Tx part
+ ,RF_TEST_CMD_GET_TPO_VALUE = 111 // For NSFT Adjust TPO support - Phase Out
+ ,RF_TEST_CMD_SET_TPO_VALUE = 112 // For NSFT Adjust TPO support - Phase Out
+ ,RF_TEST_CMD_GET_RXD_INFO_V5 = 113 //Gen95: Get Rx DL Power or ELNA Type info
+ ,RF_TEST_CMD_SET_RXDATA_V5 = 114 //RF_TEST_CMD_SET_RX_PATH_LOSS_V5
+ ,RF_TEST_CMD_GET_RXDATA_V5 = 115 //RF_TEST_CMD_SET_RX_PATH_LOSS_V5
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P_V5 = 116 //Gen95: RFTestCmdDTS_Lpm_512P_V5
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P_V5 = 117 //Gen95: RFTestCmdDTS_Lpm_512P_V5
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_512P_V5 = 118
+ ,RF_TEST_CMD_PM_V5 = 119 // Gen95: Trad Cal
+ ,RF_TEST_CMD_IF_PM_V5 = 120 // Gen95: RF Tool & Trad Cal
+ ,RF_TEST_CMD_CONTINUOUS_RX_V5 = 121 // Gen95: RF Tool & Trad Cal
+ ,RF_TEST_CMD_NSFT_START_V5 = 122 // Gen95
+ ,RF_TEST_CMD_NSFT_GET_RXLEV_V5 =123 // Gen95
+ ,RF_TEST_CMD_NSFT_CHANGE_SETTING_V5 = 124 // Gen95
+ ,RF_TEST_CMD_LIST_MODE_NSFT_START_V5 = 125 // Gen95
+ ,RF_TEST_CMD_RX_GAIN_CALCULATE_V5 = 126 // Gen95
+ ,RF_TEST_CMD_GET_TPO_VALUE_V5 = 128 // For NSFT Adjust TPO support - Gen95
+ ,RF_TEST_CMD_SET_TPO_VALUE_V5 = 129 // For NSFT Adjust TPO support - Gen95
+ //Remember to add req/result param to FT_GL1TST_UnionTag.txt & add CMD to CheckFunction
+ /*----------------------------------------------------------------------------------------------------*/
+ ,RF_TEST_CMD_GP_TOOL_COMMAND_START
+ ,RF_TEST_CMD_END
+ ,RF_TEST_CMD_MAX = 0x7FFFFFFF
+} RfTestCmdType;
+
+typedef enum {
+ MS_GSM = 0
+ ,MS_GPRS
+ ,MS_EGPRS_RX_ONLY
+ ,MS_EGPRS_FULL_FUNCTION
+} MS_CAPABILITY_E;
+
+typedef struct
+{
+ ARFCN arfcn;
+ kal_int8 sampleNoPerFrame;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain;
+ kal_int16 frames;
+} RfTestCmdPm;
+
+typedef struct
+{
+ ARFCN arfcn;
+ kal_int16 dacValue;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain;
+ kal_int16 testNumber;
+} RfTestCmdAfc;
+
+typedef struct
+{
+ ARFCN arfcn;
+ BSIC bsic;
+ kal_int8 bitmask;
+ Power txPowerLev;
+ kal_int16 frames;
+ kal_int16 dacValue;
+ APCTxPattern burstTypeNB;
+} RfTestCmdNbTx;
+
+typedef struct
+{
+ ARFCN arfcn;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain;
+ kal_bool onOff;
+} RfTestCmdContRx;
+
+typedef struct
+{
+ ARFCN arfcn;
+ ContTxPattern pattern;
+ kal_bool onOff;
+} RfTestCmdContTx;
+
+typedef struct {
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+} RfTestCmdSetBBTXCfg;
+
+typedef struct {
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+ kal_int8 TxCalbias;
+ kal_int8 TxIQSwap;
+ kal_int8 TxCMV;
+ kal_int8 TxGain;
+ kal_int8 TxCalrcsel;
+} RfTestCmdSetBBTXCfg2;
+
+typedef struct {
+ ARFCN arfcn;
+ BSIC bsic;
+ kal_int8 timeSlotmask;
+ Power powerLev[4];
+ CodingScheme cs[4];
+ TimingAdvance ta;
+ kal_int32 frames;
+ kal_int16 dacValue;
+} RfTestCmdMultiSlotTX;
+
+typedef struct {
+ kal_int32 rf_band;
+ kal_int32 power_level;
+ kal_int32 apc_dac;
+} RfTestCmdSetRampApcLevel;
+
+typedef struct {
+ kal_int16 dacValue;
+} RfTestCmdSetAfcDacValue;
+
+typedef struct {
+ kal_int32 cap_id;
+} RfTestCmdSetCrystalCfg;
+
+typedef struct {
+ kal_int32 rf_band;
+} RfTestCmdSetRampTable;
+
+typedef struct {
+ kal_bool is_sinwave;
+} RfTestCmdSetAfcSinWave;
+
+typedef struct {
+ kal_uint32 bsi_data;
+} RfTestCmdSetBSI;
+
+typedef struct {
+ kal_uint32 bsi_addr;
+} RfTestCmdGetBSI;
+
+typedef struct {
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+ kal_int8 TxCalbias;
+ kal_int8 TxIQSwap;
+ kal_int8 TxCMV;
+ kal_int8 TxGain;
+ kal_int8 TxCalrcsel;
+ kal_int8 TxPhasesel;
+} RfTestCmdSetBBTXCfg3;
+
+typedef struct
+{
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+ kal_int8 TxCalbias;
+ kal_int8 TxIQSwap;
+ kal_int8 TxCMV;
+ kal_int8 TxGain;
+ kal_int8 TxCalrcsel;
+ kal_int8 TxPhasesel;
+ kal_int8 TxCoarseI;
+ kal_int8 TxCoarseQ;
+
+}RfTestCmdSetBBTXCfg4;
+
+typedef struct {
+ ARFCN arfcn;
+ BSIC bsic;
+ kal_int8 timeSlotmask;
+ Power powerLev[4];
+ CodingScheme cs[4];
+ TimingAdvance ta;
+ kal_int32 frames;
+ kal_int16 dacValue;
+ APCTxPattern pattern;
+ kal_uint16 pattern_data;
+} RfTestCmdMultiSlotTXEx;
+
+typedef struct {
+ ARFCN arfcn;
+ ContTxPattern pattern;
+ kal_uint16 pattern_data;
+ kal_bool onOff;
+ kal_uint16 modtype;
+} RfTestCmdContTxEx;
+
+typedef struct {
+ ARFCN arfcn;
+ ContTxPattern pattern;
+ kal_uint16 pattern_data;
+ kal_bool onOff;
+ kal_uint16 modtype;
+ Power powerLev;
+} RfTestCmdContTxEx2;
+
+typedef struct{
+ FrequencyBand band;
+ ARFCN BCH_ARFCN;
+ ARFCN TCH_ARFCN;
+ Gain BCH_gain;
+ Gain TCH_gain;
+ TSC tsc;
+ TimeSlot TCH_slot;
+ Power tx_power_level;
+ kal_bool is_EPSK_tx;
+ CodingScheme epsk_cs;
+}RfTestCmdNSFTParam;
+
+/** ----- 2G nsft V5 -----*/
+#if IS_2G_RXD_SUPPORT
+typedef struct{
+ FrequencyBand band;
+ ARFCN BCH_ARFCN;
+ ARFCN TCH_ARFCN;
+ Power BCH_DL_Power;
+ Power TCH_DL_Power;
+ TSC tsc;
+ TimeSlot TCH_slot;
+ Power tx_power_level;
+ kal_bool is_EPSK_tx;
+ CodingScheme epsk_cs;
+ kal_uint8 Antenna; //GSM_AntDimension
+}RfTestCmdNSFTParam_V5;
+#endif
+/** ----------------------*/
+
+
+typedef struct{
+ Power tx_power_level;
+}RfTestCmdNSFTPowerChangeParam;
+
+/** ----- 2G list mode nsft -----*/
+typedef struct
+{
+ kal_uint8 cmd_count;
+} RfTestCmdListModeNSFTParam;
+
+typedef struct
+{
+ kal_uint8 cmd_type;
+} RfTestCmdListModeNSFTCommonParam;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_int16 sync_power;
+ kal_uint8 sync_slot_offset;
+} RfTestCmdListModeNSFT_Sync_REQ;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 tsc;
+ kal_uint8 trx_type;
+ kal_int16 tx_power;
+} RfTestCmdListModeNSFT_Trigger_REQ;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 tsc;
+ kal_uint8 trx_type;
+ kal_int8 tx_pcl[8];
+ kal_int16 rx_power;
+ kal_int8 repeat_count[8];
+} RfTestCmdListModeNSFT_CHMeas_REQ;
+
+typedef union
+{
+ RfTestCmdListModeNSFT_Sync_REQ sync;
+ RfTestCmdListModeNSFT_Trigger_REQ trigger;
+ RfTestCmdListModeNSFT_CHMeas_REQ test;
+} RfTestCmdListModeNSFTCmdParam;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCmdParam param[60];
+} RfTestCmdListModeNSFT;
+// --------------------------------- //
+
+
+
+/** ----- 2G list mode nsft V5 -----*/
+#if IS_2G_RXD_SUPPORT
+//Req Param
+typedef struct
+{
+ kal_uint8 cmd_count;
+ kal_uint8 Antenna; // GSM_AntDimension
+} RfTestCmdListModeNSFTParam_V5;
+
+
+//Req Pdu
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 trx_type; //new param
+ kal_int16 sync_power;
+ kal_uint8 sync_slot_offset;
+} RfTestCmdListModeNSFT_Sync_REQ_V5;
+
+typedef RfTestCmdListModeNSFT_Trigger_REQ RfTestCmdListModeNSFT_Trigger_REQ_V5;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 tsc;
+ kal_uint8 trx_type;
+ kal_int8 tx_pcl[8];
+ kal_int16 rx_power;
+ kal_int8 repeat_count[8];
+} RfTestCmdListModeNSFT_CHMeas_REQ_V5;
+//typedef RfTestCmdListModeNSFT_CHMeas_REQ RfTestCmdListModeNSFT_CHMeas_REQ_V5;
+
+typedef union
+{
+ RfTestCmdListModeNSFT_Sync_REQ_V5 sync;
+ RfTestCmdListModeNSFT_Trigger_REQ_V5 trigger;
+ RfTestCmdListModeNSFT_CHMeas_REQ_V5 test;
+} RfTestCmdListModeNSFTCmdParam_V5;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCmdParam_V5 param[60];
+} RfTestCmdListModeNSFT_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+// --------------------------------- //
+
+
+
+// ***************************************** //
+// FDT Calibration
+// ***************************************** //
+#define FT_MAX_STEP_CNT_50P 50
+#define FT_MAX_STEP_CNT_100P 100
+#define FT_MAX_STEP_CNT_512P 512
+
+typedef struct
+{
+ FrequencyBand band;
+ ARFCN arfcn;
+ kal_int16 dac_value[33];
+ Gain gain;
+ kal_int16 repeat_cnt; // repetitive test counts (frames) for each AFC DAC value
+ kal_bool capid_cal; // capid calibration ctrl
+ kal_bool linear_cal; // 33 stages calibration ctrl
+ //kal_int8 capid_min; // min value for capid range when capid_cal is True; capid when capid_cal is False
+ //kal_int8 capid_max; // max value for capid range
+ kal_int32 capid_min; // min value for capid range when capid_cal is True; capid when capid_cal is False
+ kal_int32 capid_max; // max value for capid range
+} RFTestCmdDSSAfc;
+
+#define RF_TEST_CMD_DSSPL_HDR \
+ FrequencyBand band; \
+ ARFCN arfcn; \
+ Gain gain[6]; \
+ kal_int16 repeat_cnt; \
+
+typedef struct
+{
+ //FrequencyBand band;
+ //ARFCN arfcn;
+ //Gain gain[6]; // gain for rx slot 0/1/2/3/4/5
+ //kal_int16 repeat_cnt; // repetitive test counts (frames) for each ARFCN value
+ RF_TEST_CMD_DSSPL_HDR
+ //kal_int16 dac_value; // Use InitDacValue from AFC calibration when dacValue = 0 (or -1)
+} RFTestCmdDSSPL;
+
+typedef enum
+{
+ LNA_NULL, //For old CMD, tool will not set gsm_lna_mode
+ LNA_HIGH,
+ LNA_MID,
+ LNA_LOW,
+ LNA_W_COEF,
+ LNA_SAWLESS_MID
+}RFTestCmdLNACalType;
+
+typedef struct
+{
+ RF_TEST_CMD_DSSPL_HDR
+ RFTestCmdLNACalType gsm_lna_mode; //0(Null) 1(high) 2(mid) 3(low) 4(w-coef) 5(sawless mid) 6(elna+G6) 7(elna bypass+G1)
+} RFTestCmdDSSPL_V2;
+
+typedef enum
+{
+ LNA_NULL_V3, //For old CMD, tool will not set gsm_lna_mode
+ LNA_HIGH_V3,
+ LNA_MID_V3,
+ LNA_LOW_V3,
+ LNA_W_COEF_V3,
+ LNA_SAWLESS_MID_V3,
+ ELNA_HIGH_SENSITIVITY,
+ ELNA_BYPASS_LOW_MAXPIN
+}RFTestCmdLNACalType_V3;
+
+typedef struct
+{
+ RF_TEST_CMD_DSSPL_HDR
+ RFTestCmdLNACalType_V3 gsm_lna_mode; //0(Null) 1(high) 2(mid) 3(low) 4(w-coef) 5(sawless mid) 6(elna+G6) 7(elna bypass+G1)
+} RFTestCmdDSSPL_V3;
+
+#define RF_TEST_CMD_DTS_HDR \
+ kal_bool afc_cal; \
+ kal_bool pl_cal; \
+ kal_int8 sync_sb_num; \
+ kal_int16 power; \
+ RFTestCmdDSSAfc AfcDSS;
+
+typedef struct
+{
+ //kal_bool afc_cal;
+ //kal_bool pl_cal; // Control whether Path loss calibration is needed or not
+ //kal_int8 sync_sb_num; // the SB frame numbers needed for sync process before path loss calibration
+ //kal_int16 power; // the power level expected to measure from test set
+ //RFTestCmdDSSAfc AfcDSS;
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_50P-2];
+} RFTestCmdDTS_50P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_100P-2];
+} RFTestCmdDTS_100P;
+
+/* [LPM CAL] */
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_50P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_50P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_100P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_100P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ RFTestCmdDSSPL_V2 PathLossDSS[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_512P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ RFTestCmdDSSPL_V3 PathLossDSS[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_512P_V3;
+
+
+/* ----RF_TEST_CMD_GET_CALIBRATION_INFO_FOR_RXD_V5 ---- */
+#if IS_2G_RXD_SUPPORT
+typedef enum
+{
+ NON_ELNA,
+ ELNA_BYPASS_NB_MATCH,
+ ELNA_BYPASS_WB_MATCH,
+ ELNA_ALWAYS_ON
+} RfTestRx_Elna_Type_E;
+
+typedef enum
+{
+ RX_LNA_NONE = 0,
+ RX_LNA_UTRA_HIGH = 1,
+ RX_LNA_HIGH = 2,
+ RX_LNA_MID = 3,
+ RX_LNA_MID_SAWLESS = 4,
+ RX_LNA_LOW = 5,
+ RX_LNA_BYPASS_LOW = 6, //the same as GSM_RF_MAX_RX_GAIN_NUM_V5
+} RfTestRx_Lna_Mode_E;
+
+typedef enum
+{
+ SUPPORT_BAND_GSM400,
+ SUPPORT_BAND_GSM850,
+ SUPPORT_BAND_GSM900,
+ SUPPORT_BAND_DCS1800,
+ SUPPORT_BAND_PCS1900,
+ SUPPORT_BAND_NUM
+} RfTestSupportBand; //FrequencyBand
+
+typedef struct
+{
+ //FHC
+ kal_uint8 seq_num;
+ kal_int16 dlpow_default[GSM_RF_MAX_RX_GAIN_NUM_V5]; //0.125 dBm
+ kal_int16 dlpow_lbound[GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_int16 dlpow_hbound[GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_uint8 lna_enum_type[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5]; //RfTestRx_Lna_Mode_E
+ kal_uint8 antenna_enable[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_int16 dlpow_wcoef_default; //0.125 dBm
+ kal_int16 dlpow_wcoef_lbound;
+ kal_int16 dlpow_wcoef_hbound;
+ kal_int16 wcoef_arfcn[8]; //each band woef arfcn, [850][900][DCS][PCS]=[1][2][8][6]
+
+ //for trad cal
+ kal_int16 gain_default[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5]; // 0.125 dB
+ kal_int16 wcoef_gain_default[GSM_RF_MAX_RX_ANT_NUM]; // 0.125 dB
+ //RF Tool
+ kal_uint8 elna_type[GSM_RF_MAX_RX_ANT_NUM]; // RfTestRx_Elna_Type_E
+ kal_int16 gain_hbound[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_int16 gain_lbound[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5];
+} RfTestCmdCalInfoV5_T; // RfTestElnaInfoV5_T
+
+typedef struct
+{
+ RfTestCmdCalInfoV5_T GSM_Band_Info[SUPPORT_BAND_NUM-1]; //No GSM400
+} RfTestCmdCalInfoV5AllBandCnfPdu_T;
+
+
+/* ----RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P_V5 ---- */
+typedef enum
+{
+ RX_CAL_SEQ_V5_NULL = RX_LNA_NONE ,
+ RX_CAL_SEQ_V5_UTRA_HIGH = RX_LNA_UTRA_HIGH ,
+ RX_CAL_SEQ_V5_HIGH = RX_LNA_HIGH ,
+ RX_CAL_SEQ_V5_MID = RX_LNA_MID ,
+ RX_CAL_SEQ_V5_MID_SAWLESS = RX_LNA_MID_SAWLESS,
+ RX_CAL_SEQ_V5_LOW = RX_LNA_LOW ,
+ RX_CAL_SEQ_V5_BYPASS_LOW = RX_LNA_BYPASS_LOW ,
+ RX_CAL_SEQ_V5_WCOEF
+} RfTestRxCalSeqV5_E; //the same as LNACalSeqV5_E //reference to RfTestRx_Lna_Mode_E
+
+typedef struct
+{
+ FrequencyBand band;
+ ARFCN arfcn;
+ kal_int16 repeat_cnt;
+ kal_int16 dl_power; //it is DL Power for each frame
+ RfTestRxCalSeqV5_E gsm_lna_mode[GSM_RF_MAX_RX_ANT_NUM];
+} RFTestCmdDSSPL_V5;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ RFTestCmdDSSPL_V5 PathLossDSS[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 lpm_sb_num;
+ kal_uint8 Antenna; //GSM_AntDimension
+} RFTestCmdDTS_Lpm_512P_V5;
+
+
+/* ----RF_TEST_CMD_PM_V5 & RF_TEST_CMD_IF_PM_V5---- */
+//REQ Param
+typedef struct
+{
+ RfTestSupportBand band;
+ ARFCN arfcn;
+ kal_int8 sampleNoPerFrame;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int16 frames;
+ GSM_AntDimension Antenna;
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+} RfTestCmdPm_V5;
+
+//CNF Param
+typedef struct
+{
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ kal_int32 power[GSM_RF_MAX_RX_ANT_NUM];
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS*2 bits*/
+ kal_int32 deviation[GSM_RF_MAX_RX_ANT_NUM];
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain usedGain[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 iOffset[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 qOffset[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 validSamples[GSM_RF_MAX_RX_ANT_NUM];
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 ok;
+} RfTestResultPm_V5;
+
+
+/* ----RF_TEST_CMD_CONTINUOUS_RX_V5---- */
+//REQ Param
+typedef struct
+{
+ RfTestSupportBand band;
+ ARFCN arfcn;
+ Gain gain[GSM_RF_MAX_RX_ANT_NUM];
+ GSM_AntDimension Antenna;
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+ kal_bool onOff;
+} RfTestCmdContRx_V5;
+//CNF Param
+//kal_bool ok;
+
+
+/* ----RF_TEST_CMD_RX_GAIN_CALCULATE_V5---- */
+//REQ Param
+typedef struct
+{
+ RfTestSupportBand band;
+ GSM_AntDimension Antenna;
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+} RfTestCmdRxGainCalculate_V5;
+
+//CNF Param
+typedef enum
+{
+ GSM_CALCULATE_NULL = 0,
+ GSM_CALCULATE_SUCCESS,
+ GSM_CALCULATE_FAIL
+} GSM_RxGain_Caculator;
+
+typedef struct
+{
+ kal_int16 recommend_dlpow;
+ kal_uint16 request_gain [GSM_RF_MAX_RX_ANT_NUM]; // 1/8 dB
+ GSM_RxGain_Caculator calculate_status;
+} RfTestResultRxGainCalculate_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+/* ---------------------------------------------------------------------------- */
+
+
+typedef struct
+{
+ FrequencyBand band;
+ ARFCN arfcn;
+ kal_int8 timeslot_per_frame;
+ kal_int8 apc_dac_pcl_sel; // 1: apc_dac, 0: apc_pcl
+ kal_int16 apc_dac_pcl_value[4];
+ //kal_uint8 pa_vbias_val;
+ kal_uint8 pa_vbias_val[4];
+ kal_uint8 is_low_pcl[4];
+
+ CodingScheme cs[4];
+ kal_int32 repeat_cnt;
+ kal_int16 afc_dac_value;
+ kal_int8 tsc;
+ APCTxPattern pattern;
+ kal_uint16 pattern_data;
+} RfTestCmdUSSApc;
+
+typedef struct
+{
+ //kal_bool pa_vbias_cal; // Control whether PA need to calibrate different Vbias value when APC DAC is used
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ kal_int16 high_apc_dcoffset[FrequencyBandCount];
+ // kal_int32 lowest_power[FrequencyBandCount];
+ RfTestCmdUSSApc ApcUSS[FT_MAX_STEP_CNT_50P];
+}RfTestCmdUTS_50P;
+
+typedef struct
+{
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ kal_int16 high_apc_dcoffset[FrequencyBandCount];
+ RfTestCmdUSSApc ApcUSS[FT_MAX_STEP_CNT_100P];
+}RfTestCmdUTS_100P;
+
+typedef struct
+{
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ kal_int16 high_apc_dcoffset[FrequencyBandCount];
+ RfTestCmdUSSApc ApcUSS[FT_MAX_STEP_CNT_512P];
+}RfTestCmdUTS_512P;
+
+typedef struct
+{
+ //kal_int32 rf_band;
+ kal_int16 afc_offset[FrequencyBandCount];
+
+}RF_SET_AFC_DAC_OFFSET_REQ_T;
+
+typedef struct
+{
+ signed char rollback_2t; /* Rollback (2t/F2I_Resolution) dB when 2 TX slots */
+ signed char rollback_3t; /* Rollback (3t/F2I_Resolution) dB when 3 TX slots */
+ signed char rollback_4t; /* Rollback (4t/F2I_Resolution) dB when 4 TX slots */
+ signed char rollback_5t; /* Rollback (5t/F2I_Resolution) dB when 5 TX slots */
+} FT_Rf_sTX_POWER_ROLLBACK;
+
+typedef struct
+{
+ kal_int32 band;
+ FT_Rf_sTX_POWER_ROLLBACK PowerRollbackTable;
+}RfTestCmdSetPowerRollbackTable;
+
+/**
+ * The RfTestCmdIrPm is used for IRR w coeffiecient calibration
+ * The command is analogous to RfTestCmdPm, except the m_IfFlag
+ */
+typedef struct
+{
+ /// power scan input parameter
+ RfTestCmdPm m_Pm;
+ /// if_flag for the power scan (to override the if setting in power scan, the original interface is not changed)
+ kal_int8 m_IfFlag;
+}RfTestCmdIrPm;
+
+#if IS_2G_RXD_SUPPORT
+typedef struct
+{
+ /// power scan input parameter
+ RfTestCmdPm_V5 m_Pm;
+ /// if_flag for the power scan (to override the if setting in power scan, the original interface is not changed)
+ kal_int8 m_IfFlag;
+}
+RfTestCmdIrPm_V5;
+#endif
+
+typedef struct
+{
+ FrequencyBand band;
+ Power pcl;
+}RfTestCmdTXPC;
+// ***************************************** //
+
+// R8 edge new feature
+typedef struct
+{
+ unsigned char rf_band;
+ unsigned short pa_gain[16];
+}RfTestCmdSetEdgeTxOctPACoef;
+
+typedef struct
+{
+ kal_uint8 rf_band;
+ kal_int8 cTxAdc_State;
+ kal_int8 is_EPSK;
+}RfTestCmdResetPdData;
+
+typedef struct{
+ ARFCN arfcn; // absolute radio frequency channel number
+ BSIC bsic; // training sequence
+ CodingScheme cs; // coding scheme for each time slot, MCS1~9 is only valid for EPSK function
+ TimingAdvance ta; // time advance
+ kal_int32 frames; // the number of frames should transmit
+ kal_int16 dacValue; // AFC DAC value
+ APCTxPattern pattern; // Tx pattern is only valid for EPSK function
+ kal_uint16 pattern_data; // if NB_TX_PATTERN_WITHOUT_TSC==pattern, user can input any 16bits value as pattern.
+ kal_uint16 pa_gain; // pa gain from ini file
+ kal_uint16 pa_vbias; // pa vbias from ini file
+ kal_uint8 rf_gain_index; // gain rf index
+}Rf_GainRfTx_Req;
+
+typedef struct
+{
+ kal_uint16 max_arfcn;
+ kal_int8 path_loss_H;
+ kal_int8 path_loss_M;
+ kal_int8 path_loss_M_sawless;
+ kal_int8 path_loss_L;
+}RfPathLossOffset;
+
+typedef struct
+{
+ RfPathLossOffset rx_pathloss[FrequencyBandCount][PLTABLE_SIZE];
+}RfTestCmdSetGetRxPathLoss;
+
+typedef struct
+{
+ kal_uint16 max_arfcn;
+ kal_int8 path_loss_H;
+ kal_int8 path_loss_M;
+ kal_int8 path_loss_M_sawless;
+ kal_int8 path_loss_L;
+ kal_int8 path_loss_H_sensitivity; //elna+g6
+ kal_int8 path_loss_L_maxpin; //elna_bypass+g1 ,sLNAGAINOFFSET
+}RfPathLossOffset_V3;
+
+typedef struct
+{
+ RfPathLossOffset_V3 rx_pathloss[FrequencyBandCount][PLTABLE_SIZE];
+}RfTestCmdSetGetRxPathLoss_V3;
+
+typedef struct
+{
+ RfTestCmdAfc afc;
+ FrequencyBand band;
+ RfTestCmdSetAfcSinWave setAfcSinWave;
+}RfTestCmdSinewaveAfcGetTempFreq;
+
+typedef struct
+{
+ //sRFSpecialCoef rfspecialcoef;
+ //RFSpecialCoef.rx.mt6256_51rf.w_data
+ w_coef w_data[WCTABLE_SIZE];
+}RfTestCmdSetGetWcoefPdu;
+
+
+
+
+/* -------------------- *\
+|* SET TX CMD REQ Struct *|
+ \* -------------------- */
+#define RF_MAX_PEER_BUF_CNF_BYTE_SIZE 51200 //50*1024
+#define RF_MAX_PEER_BUF_CNF_WORD_SIZE RF_MAX_PEER_BUF_CNF_BYTE_SIZE >> 2
+
+typedef enum
+{
+ GMSK_Band850 =1, //0x00 01
+ GMSK_Band900 =2, //0x00 02
+ GMSK_Band1800 =4, //0x00 04
+ GMSK_Band1900 =8, //0x00 08
+ EPSK_Band850 =256, //0x01 00
+ EPSK_Band900 =512, //0x02 00
+ EPSK_Band1800 =1024, //0x04 00
+ EPSK_Band1900 =2048, //0x08 00
+}RfTestTxData_ModBand_Bitmap_E;
+
+typedef struct
+{
+ kal_uint16 count;
+ kal_uint16 offset;
+ //kal_uint16 mod_band_bitmap; //modulation+band bitmap
+ //// EPSK(4bit) | GMSK(4bit) -> 0000 0101 | 0000 0011 -> PCS|DCS|900|850 ex.Set Data for GSM850/GSM900 GMSK + GSM850/DCS EPSK Ramping
+ //kal_uint16 mod_bitmap; //modulation bitmap
+ //// EPSK(1bit) | GMSK(1bit) -> 00000001 | 00000001 ex.Set Data for GMSK & EPSK Txpc
+ //kal_uint16 band_bitmap; //band bitmap
+ // EPSK(4bit) -> PCS|DCS|900|850-> 0000 1111 | 0000 0000 ex.Set Data for EPSK interslotramp GSM850/GSM900/DCS/PCS
+ //kal_uint16 not_used_bitmap; //0000 0000 | 0000 0001, only need one bit, data did not separate from diff band and mod type
+ kal_uint16 bitmap; //for general purpose //RfTestTxData_ModBand_Bitmap_E //RfTestRxData_ModBand_Bitmap_E
+ kal_uint16 zero_padding;
+}RfTestParamDynamicEntryElm_T;
+
+typedef struct
+{
+ kal_uint16 is_uplate_to_NVRAM;
+ RfTestParamDynamicEntryElm_T type1_ramptable_param;
+ RfTestParamDynamicEntryElm_T type2_epsk_interramptable_param;
+ RfTestParamDynamicEntryElm_T type3_txpc_param;
+ RfTestParamDynamicEntryElm_T type4_epskpa_param;
+}RfTestCmdSetTxDataReqParam;
+
+typedef l1cal_rampTable_T L1_Ramptable_Type1_T;
+
+#if MD_DRV_IS_EPSK_TX_SUPPORT
+typedef l1cal_EPSK_interRampData_T L1_EPSK_InterRamptable_Type2_T;
+#endif
+
+typedef struct
+{
+ char is_calibrated;
+ short temperature;
+}L1_Txpc_Type3_T; //l1cal_txpc_T
+
+typedef orionRFtx_pa_vbias L1_EpskPA_Type4_T; //l1cal_rfspecialcoef_T
+
+typedef struct
+{
+ union
+ {
+ kal_int32 set_txdata_req_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ #if MD_DRV_IS_EPSK_TX_SUPPORT
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ #endif
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+ } request;
+}RfTestCmdSetTxDataReqPdu;
+/* -------------------------------------- */
+
+
+
+/* -------------------- *\
+|* GET TX CMD REQ Struct *|
+ \* -------------------- */
+typedef struct
+{
+ kal_uint16 type1_ramptable_count;
+ kal_uint16 type2_epsk_interramptable_count;
+ kal_uint16 type3_txpc_count;
+ kal_uint16 type4_epskpa_count;
+
+ //point out which kind of this type should be got
+ kal_uint16 type1_ramptable_bitmap;
+ kal_uint16 type2_epsk_interramptable_bitmap;
+ kal_uint16 type3_txpc_bitmap;
+ kal_uint16 type4_epskpa_bitmap;
+}RfTestCmdGetTxDataReqParam;
+/* -------------------------------------- */
+
+
+#if IS_2G_RXD_SUPPORT
+/* -------------------- *\
+|* SET RX CMD REQ Struct *|
+ \* -------------------- */
+typedef enum
+{
+ GSM_RXM_Band850 =1, //0x00 01
+ GSM_RXM_Band900 =2, //0x00 02
+ GSM_RXM_Band1800 =4, //0x00 04
+ GSM_RXM_Band1900 =8, //0x00 08
+ GSM_RXD_Band850 =256, //0x01 00
+ GSM_RXD_Band900 =512, //0x02 00
+ GSM_RXD_Band1800 =1024, //0x04 00
+ GSM_RXD_Band1900 =2048, //0x08 00
+}RfTestRxData_ModBand_Bitmap_E;
+
+//typedef struct
+//{
+// kal_uint16 count;
+// kal_uint16 offset;
+// kal_uint16 bitmap; //for general purpose //RfTestTxData_ModBand_Bitmap_E, RfTestRxData_ModBand_Bitmap_E
+// kal_uint16 zero_padding;
+//}RfTestParamDynamicEntryElm_T;
+
+typedef struct
+{
+ kal_uint16 is_uplate_to_NVRAM;
+ RfTestParamDynamicEntryElm_T type1_rxpathloss_param;
+ RfTestParamDynamicEntryElm_T type2_wcoef_param;
+}RfTestCmdSetRxDataReqParam;
+
+typedef struct
+{
+ RfPathLossOffset_V3 rx_pathloss_entry[PLTABLE_SIZE];
+} L1_SetGetRxPathLossEntry_Type1_T;
+
+typedef l1cal_wcoef_T L1_Wcoef_Type2_T;
+
+typedef struct
+{
+ union
+ {
+ kal_int32 set_rxdata_req_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_SetGetRxPathLossEntry_Type1_T type1_pathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+ } request;
+}RfTestCmdSetRxDataReqPdu;
+/* -------------------------------------- */
+
+
+/* -------------------- *\
+|* GET RX CMD REQ Struct *|
+ \* -------------------- */
+typedef struct
+{
+ kal_uint16 type1_rxpathloss_count;
+ kal_uint16 type2_wcoef_count;
+
+ //point out which kind of this type should be got
+ kal_uint16 type1_rxpathloss_bitmap;
+ kal_uint16 type2_wcoef_bitmap;
+}RfTestCmdGetRxDataReqParam;
+/* -------------------------------------- */
+#endif //#if IS_2G_RXD_SUPPORT
+
+/*GET TPO CMD REQ struct*/
+typedef struct
+{
+ FrequencyBand band;
+ kal_bool is_epsk;
+}RfTestCmdGetTPO;
+
+/*SET TPO CMD REQ struct*/
+typedef struct
+{
+ FrequencyBand band;
+ kal_bool is_epsk;
+ kal_int16 power_apcdac_offset; // unit:DAC
+ kal_int16 power_dB_offset; // 0.125 dB
+}RfTestCmdSetTPO;
+
+typedef union
+{
+ RfTestCmdPm pm;
+ RfTestCmdAfc afc;
+ RfTestCmdNbTx nbTx;
+ RfTestCmdContRx contRx;
+ RfTestCmdContTx contTx;
+ RfTestCmdSetBBTXCfg setBBTXCfg;
+ kal_bool selectPCS1900;
+ kal_int8 dummy;
+ RfTestCmdMultiSlotTX msTx;
+ RfTestCmdSetRampApcLevel setRampApcLevel;
+ RfTestCmdSetAfcDacValue setAfcDacValue;
+ RfTestCmdSetBBTXCfg2 BBTxCfg2;
+ RfTestCmdSetCrystalCfg setCrystalCfg;
+ RfTestCmdSetRampTable setRampTable;
+ RfTestCmdSetAfcSinWave setAfcSinWave;
+ RfTestCmdSetBSI SetBSI;
+ RfTestCmdGetBSI GetBSI;
+ RfTestCmdSetBBTXCfg3 BBTxCfg3;
+ RfTestCmdMultiSlotTXEx msTxEx;
+ RfTestCmdContTxEx contTxEx;
+ RfTestCmdContTxEx2 contTxEx2;
+ RfTestCmdSetBBTXCfg4 BBTxCfg4;
+ RF_SET_AFC_DAC_OFFSET_REQ_T set_afc_offset_req;
+ RfTestCmdNSFTParam NSFT_start;
+ RfTestCmdNSFTPowerChangeParam NSFT_change_power;
+ RfTestCmdSetPowerRollbackTable PowerRollbackTable;
+ kal_uint32 m_u4NSFTSBERTestCount;
+ /// for L1TST_ReportRXQual input
+ kal_uint16 m_u2NSFTRxQualBerDecile;
+ /// for SOC2 IRR W PM
+ RfTestCmdIrPm m_IrPm;
+ RfTestCmdTXPC txpc_req;
+ /// for L1TST_TXPC_CL_GetSubband input
+ kal_uint8 band;
+ /* [LPM CAL] */
+ /// for DCXO FPM/LPM control (1 FPM, 0 LPM)
+ kal_uint8 dcxoMode;
+ /// R8 edge new feature
+ RfTestCmdSetEdgeTxOctPACoef setTxOctPaCoef;
+ RfTestCmdResetPdData resetTxPcPdData;
+ /// gain rf tx
+ Rf_GainRfTx_Req gainRfTx;
+ kal_uint8 path_flag;
+ RfTestCmdType query_op_code;
+ RfTestCmdListModeNSFTParam List_Mode_NSFT_start;
+ kal_bool is_uplate_to_NVRAM;
+ RfTestCmdSinewaveAfcGetTempFreq afc_gpscoclockv2;
+ RfTestCmdSetTxDataReqParam set_txdata_req;
+ RfTestCmdGetTxDataReqParam get_txdata_req;
+ #if IS_2G_RXD_SUPPORT
+ RfTestCmdPm_V5 pm_v5;
+ RfTestCmdIrPm_V5 m_IrPm_v5;
+ RfTestCmdContRx_V5 contRx_v5;
+ RfTestCmdNSFTParam_V5 NSFT_start_v5;
+ RfTestCmdListModeNSFTParam_V5 List_Mode_NSFT_start_v5;
+ RfTestCmdSetRxDataReqParam set_rxdata_req;
+ RfTestCmdGetRxDataReqParam get_rxdata_req;
+ RfTestCmdRxGainCalculate_V5 rx_gain_calculate_req;
+ #endif
+ RfTestCmdGetTPO getTPOVlaue;
+ RfTestCmdSetTPO setTPOVlaue;
+} RfTestCmdParam;
+
+
+
+
+/* ---------------------------------- */
+typedef struct
+{
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ kal_int32 power;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS*2 bits*/
+ kal_int32 deviation;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain usedGain;
+ kal_int32 ok;
+ kal_int32 iOffset;
+ kal_int32 qOffset;
+ kal_int32 validSamples;
+} RfTestResultPm;
+
+typedef struct
+{
+ kal_int16 fcb_ok_number;
+ kal_int32 freqOffset;
+ kal_int32 deviation;
+ kal_int32 ok;
+} RfTestResultAfc;
+
+typedef struct
+{
+ kal_int16 fcb_ok_number;
+ kal_int32 freqOffset;
+ kal_int32 deviation;
+ kal_int32 ok;
+ kal_int32 temperature;
+} RfTestResultSinewaveAfcGetTempFreq;
+
+typedef struct {
+ kal_bool ok;
+ RfTestCmdSetBBTXCfg2 bbtx_cfg;
+} RfTestResultGetBBTXCfg2;
+
+typedef struct {
+ kal_uint32 GSM400;
+ kal_uint32 GSM850;
+ kal_uint32 GSM900;
+ kal_uint32 DCS1800;
+ kal_uint32 PCS1900;
+} RfTestResultBandSupport;
+
+typedef struct {
+ kal_bool ok;
+ MS_CAPABILITY_E capability;
+ RfTestResultBandSupport band_support;
+} RfTestResultMsCapability;
+/*
+#define MS_CAPABILITY_GSM 0x00000001
+#define MS_CAPABILITY_GPRS 0x00000002
+#define MS_CAPABILITY_EDGE_RX 0x00000004
+#define MS_CAPABILITY_EDGE_8PSK_TX 0x00000008
+#define MS_CAPABILITY_8PM 0x00000010
+
+#define MS_BAND_SUPPORT_GSM400 0x00000001
+#define MS_BAND_SUPPORT_GSM850 0x00000002
+#define MS_BAND_SUPPORT_GSM900 0x00000004
+#define MS_BAND_SUPPORT_DCS1800 0x00000008
+#define MS_BAND_SUPPORT_PCS1900 0x00000010
+*/
+
+typedef struct
+{
+ kal_uint32 capability;
+ kal_uint32 band_support;
+}RfResultMsCapabilityEx;
+
+typedef struct {
+ kal_bool ok;
+ kal_uint32 capability;
+ kal_uint32 band_support;
+} RfTestResultMsCapabilityEx;
+
+typedef struct {
+ kal_bool ok;
+ kal_uint32 id;
+} RfTestResultGetRFID;
+
+typedef struct {
+ kal_bool ok;
+ kal_uint32 bsi_data;
+} RfTestResultGetBSI;
+
+typedef struct {
+ kal_bool ok;
+ RfTestCmdSetBBTXCfg3 bbtx_cfg;
+} RfTestResultGetBBTXCfg3;
+
+typedef struct
+{
+ kal_bool ok;
+ RfTestCmdSetBBTXCfg4 bbtx_cfg;
+}RfTestResultGetBBTXCfg4;
+
+typedef struct {
+ kal_bool ok;
+ kal_int16 dacValue;
+} RfGetAfcDacValueAtRTXOffsetCal;
+
+typedef struct
+{
+ kal_bool ok;
+ kal_int32 calibra_result_32k;
+}RfTestResult32kCalibration;
+
+// ****************************** //
+// FDT Calibration
+// ****************************** //
+typedef struct
+{
+ kal_int32 power[FT_MAX_STEP_CNT_50P-2];
+ kal_int16 valid_sample[FT_MAX_STEP_CNT_50P-2];
+ kal_bool ok;
+} RfTestResultDSSPL_50P;
+
+typedef struct
+{
+ kal_int32 power[FT_MAX_STEP_CNT_100P-2];
+ kal_int16 valid_sample[FT_MAX_STEP_CNT_100P-2];
+ kal_bool ok;
+} RfTestResultDSSPL_100P;
+
+typedef struct
+{
+ kal_int32 power[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 valid_sample[FT_MAX_STEP_CNT_512P-2];
+ kal_bool ok;
+ //kal_bool is_se_sawless; // remove this item, otherwise memory copy from ResultDSSPL will be not match
+} RfTestResultDSSPL_512P; /** For sawless lna mode and enlarge size=512 to reduce CMD round trip number*/
+
+typedef struct
+{
+ kal_int32 freq_offset[33]; // only valid when 33 stage calibration is ON
+ kal_int32 deviation[33]; // only valid when 33 stage calibration is ON
+ kal_int16 fcb_ok_number[33];
+ //kal_int8 capid; // only valid when capid calibration is ON
+ kal_int32 capid; // only valid when capid calibration is ON
+ kal_int16 init_dac_value; // only valid when 33 stage calibration is OFF
+ kal_int32 slope; // only valid when 33 stage calibration is OFF
+ kal_bool ok;
+} RfTestResultDSSAfc;
+/* [LPM CAL] */
+typedef struct
+{
+ kal_int32 cload_freq_offset;
+ kal_bool ok;
+ kal_bool is_perform_cal;
+} RfTestResultDSSLpm;
+
+#if IS_FHC_SUPPORT == 1
+typedef struct
+{
+ kal_int32 path_loss_cnt;
+ kal_int32 freq_offset;
+ kal_int32 capid_freq_offset_min;
+ kal_int32 capid_freq_offset[FHC_MAX_CAPID_SEARCH_NUM]; // 16
+ kal_int32 capid_search_order[FHC_MAX_CAPID_SEARCH_NUM]; // 16
+ kal_int32 capid;
+ kal_int32 capid_high;
+ kal_int32 capid_low;
+ kal_int32 capid_best;
+ kal_int16 afc_dac;
+ kal_int16 arfcn;
+ kal_int16 capid_cnt;
+ kal_int16 repeat_index;
+ kal_int8 state;
+ kal_int8 capid_index;
+ kal_int8 capid_okay_cnt;
+ kal_int8 afc_dac_index;
+ kal_int8 sb_okay_cnt;
+ kal_uint8 sb_fail_cnt;
+ kal_uint8 fb_fail_cnt;
+ kal_bool pl_started;
+ kal_bool pre_capid_cal_ok[FHC_PRE_CAPID_SEARCH_NUM]; // FHC_PRE_CAPID_SEARCH_NUM
+}RfTestResultDtsmInfo;
+#else
+typedef struct
+{
+ kal_int32 path_loss_cnt;
+ kal_int32 freq_offset;
+ kal_int32 capid_freq_offset_min;
+ kal_int32 capid_freq_offset[16]; //FHC_MAX_CAPID_SEARCH_NUM
+ kal_int32 capid_search_order[16]; //FHC_MAX_CAPID_SEARCH_NUM
+ kal_int32 capid;
+ kal_int32 capid_high;
+ kal_int32 capid_low;
+ kal_int32 capid_best;
+ kal_int16 afc_dac;
+ kal_int16 arfcn;
+ kal_int16 capid_cnt;
+ kal_int16 repeat_index;
+ kal_int8 state;
+ kal_int8 capid_index;
+ kal_int8 capid_okay_cnt;
+ kal_int8 afc_dac_index;
+ kal_int8 sb_okay_cnt;
+ kal_uint8 sb_fail_cnt;
+ kal_uint8 fb_fail_cnt;
+ kal_bool pl_started;
+ kal_bool pre_capid_cal_ok[9]; // FHC_PRE_CAPID_SEARCH_NUM
+}RfTestResultDtsmInfo;
+#endif
+
+typedef enum {
+ DTS_RESULT_READY = 0, // DTS results is ready to get back
+ DTS_RESULT_NOT_READY, // DTS result is still in progress and not ready to get back
+ DTS_RESULT_NOT_REQUESTED, // Haven't called the META_Rf_StartFdtDL() in advance.
+ DTS_FATAL_ERROR
+}RF_DTS_GET_RESULT_STATUS;
+typedef struct
+{
+ RfTestResultDSSPL_50P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo; // for L1 debug use, will print in META Tool's test report.
+} RfTestResultDTS_50P;
+
+typedef struct
+{
+ RfTestResultDSSPL_100P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo; // for L1 debug use, will print in META Tool's test report.
+} RfTestResultDTS_100P;
+
+
+/* [LPM CAL] */
+typedef struct
+{
+ RfTestResultDSSPL_50P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_50P;
+
+typedef struct
+{
+ RfTestResultDSSPL_100P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_100P;
+
+typedef struct
+{
+ RfTestResultDSSPL_512P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_512P; /** For sawless lna mode and reduce CMD round trip number*/
+
+typedef struct
+{
+ RfTestResultDSSPL_512P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_512P_V3; /** For sawless lna mode and reduce CMD round trip number*/
+
+/*------RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P_V5, RF_TEST_CMD_GET_FDT_RESULT_LPM_512P_V5------*/
+#if IS_2G_RXD_SUPPORT
+typedef struct
+{
+ kal_int32 power[GSM_RF_MAX_RX_ANT_NUM][FT_MAX_STEP_CNT_512P-2];
+ kal_int16 valid_sample[GSM_RF_MAX_RX_ANT_NUM][FT_MAX_STEP_CNT_512P-2];
+ kal_bool ok;
+} RfTestResultDSSPL_512P_V5; //ResultDSSPL
+
+typedef struct
+{
+ RfTestResultDSSPL_512P_V5 PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_512P_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+/*---------------------------------------------------------------*/
+
+typedef struct
+{
+ kal_int16 afc_offset[FrequencyBandCount];
+ kal_bool ok;
+}RfGetAfcOffsetResult;
+
+typedef struct
+{
+ kal_uint32 m_u4NSFTSBER;
+ kal_uint32 m_u4NSFTSBERCurrentCount;
+}RfNSFTSBERResult;
+// local
+typedef struct
+{
+ kal_bool ok;
+ kal_uint16 m_u2PDValue;
+}RfTestResultPDValue;
+
+// peer
+typedef struct
+{
+ kal_uint16 data[16];
+} RfTestResultTXPCPD;
+
+typedef struct
+{
+ kal_uint16 data[8];
+} RfTestResultTXPCPDTemp;
+
+typedef struct
+{
+ /// calibrated flag
+ kal_int8 is_calibrated;
+ /// closed-loop target value by PCL
+ RfTestResultTXPCPD adc[FrequencyBandCount];
+ /// temperature compensation interval
+ kal_int16 temperature;
+ /// closed-loop target value by temperature compensation
+ RfTestResultTXPCPDTemp temp[FrequencyBandCount];
+}RfTestResultTXPCAllPD;
+
+typedef struct
+{
+ kal_int16 status;
+ kal_int16 tadc_dac;
+ kal_int16 temperature;
+ kal_int16 temp_idx;
+} RfTestResultRfTemperatureInfo;
+
+// ****************************** //
+
+typedef struct
+{
+ kal_uint32 result; // 1: support 0: not support
+ kal_uint32 query_op_code; // query op code
+}RfCheckIfFuncExist;
+
+/** ----- 2G list mode nsft -----*/
+typedef struct
+{
+ kal_uint8 report_count;
+}RfTestResultListModeNSFT;
+
+typedef struct
+{
+ kal_uint16 status; //NsftListCmdStatus //NsftListRpt_Com_t
+}RfTestResultListModeNSFTCommon;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+ kal_uint16 retry_count;
+ kal_int16 new_afc_dac;
+ kal_int32 detected_foe;
+}RfTestResultListModeNSFTSync;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+}RfTestResultListModeNSFTTrigger;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+ kal_uint16 RX_level;
+ kal_uint32 BER_sum;
+ kal_uint32 BER_frame_count;
+}RfTestResultListModeNSFTMeasure;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+}RfTestResultListModeNSFTStop;
+
+typedef union
+{
+ RfTestResultListModeNSFTSync sync;
+ RfTestResultListModeNSFTTrigger trigger;
+ RfTestResultListModeNSFTMeasure test;
+ RfTestResultListModeNSFTStop stop;
+}RfTestResultListModeNSFTReport;
+
+typedef struct
+{
+ unsigned char cmd_type[60];
+ RfTestResultListModeNSFTReport report[60];
+}RfTestResultListModeNSFTParam;
+// --------------------------------- //
+
+
+/** ----- 2G list mode nsft V5 -----*/
+#if IS_2G_RXD_SUPPORT
+//CNF Local Param
+typedef RfTestResultListModeNSFT RfTestResultListModeNSFT_V5;
+
+//CNF Pdu
+typedef RfTestResultListModeNSFTSync RfTestResultListModeNSFTSync_V5;
+typedef RfTestResultListModeNSFTTrigger RfTestResultListModeNSFTTrigger_V5;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+ kal_uint16 RX_level[GSM_RF_MAX_RX_ANT_NUM];
+ kal_uint32 BER_sum;
+ kal_uint32 BER_frame_count;
+}RfTestResultListModeNSFTMeasure_V5;
+
+typedef RfTestResultListModeNSFTStop RfTestResultListModeNSFTStop_V5;
+
+typedef union
+{
+ RfTestResultListModeNSFTSync_V5 sync;
+ RfTestResultListModeNSFTTrigger_V5 trigger;
+ RfTestResultListModeNSFTMeasure_V5 test;
+ RfTestResultListModeNSFTStop_V5 stop;
+}RfTestResultListModeNSFTReport_V5;
+
+typedef struct
+{
+ unsigned char cmd_type[60];
+ RfTestResultListModeNSFTReport_V5 report[60];
+}RfTestResultListModeNSFTParam_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+// --------------------------------- //
+
+typedef enum
+{
+ RF_CNF_SUCCESS = 0, /**< access NVRAM successfully? */
+ RF_CNF_RECORD_STATUS_FAIL = 1, /**< access NVRAM general error? */
+ RF_CNF_NVRAM_GET_FAIL = 2, /**< GET NVRAM, NVRAM return failed */
+ RF_CNF_FREQ_INVALID = 3, /**< Error arfcn parameter for band*/
+ RF_CNF_CMD_INVALID = 4, /**< Error, SET CMD peer buffer is NULL*/
+ RF_CNF_NVRAM_SET_FAIL = 5, /**< SET NVRAM, NVRAM return failed */
+ RF_CNF_ALLOC_BUFFER_FAIL = 6 /**< Allocate peer buffer FAIL */
+}RF_NVRAM_ACCESS_CAl_DATA_RESULT;
+
+
+/* -------------------- *\
+|* SET TX CMD CNF Struct *|
+ \* -------------------- */
+typedef enum
+{
+ RF_TEST_SET_TX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_SET_TX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_SET_TX_DATA_TYPE2_OFFSET_ERROR = 2, // Type-2 count/offset mismatch
+ RF_TEST_SET_TX_DATA_TYPE3_OFFSET_ERROR = 3, // Type-3 count/offset mismatch
+ RF_TEST_SET_TX_DATA_TYPE4_OFFSET_ERROR = 4, // Type-4 count/offset mismatch
+ RF_TEST_SET_TX_DATA_EXCESS_REQ_PDU_LENGTH = 5,
+ RF_TEST_SET_TX_DATA_CNF_CHECK_OFFSET_PASS = 6,
+ RF_TEST_SET_TX_DATA_BITMAP_COUNT_MISMATCH = 7,
+ RF_TEST_SET_TX_DATA_NULL_PEER_BUF = 8,
+ RF_TEST_SET_TX_DATA_RECORD_SET_FAIL = 9,
+ RF_TEST_SET_TX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestSetTxData_Cnf_Status_E;
+
+typedef enum
+{
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_MAX,
+}RfTestSetTxData_RunTime_Status_E;
+
+typedef struct
+{
+ kal_uint16 count;
+ kal_uint16 bitmap; //add bitmap for tool team debug
+}RfTestSetTxDataCnfParamEntry_T; // Similar with RfTestParamDynamicEntryElm_T
+
+typedef struct
+{
+ RfTestSetTxData_Cnf_Status_E set_txdata_cnf_status;
+ RfTestSetTxDataCnfParamEntry_T type1_result;
+ RfTestSetTxDataCnfParamEntry_T type2_result;
+ RfTestSetTxDataCnfParamEntry_T type3_result;
+ RfTestSetTxDataCnfParamEntry_T type4_result;
+ RfTestSetTxData_RunTime_Status_E type1_ramptable_result[8];
+ RfTestSetTxData_RunTime_Status_E type2_epsk_interramptable_result[4];
+ RfTestSetTxData_RunTime_Status_E type3_txpc_result[2];
+ RfTestSetTxData_RunTime_Status_E type4_epskpa_result; //RFSpecialCoef.tx.orionRFtx.data...
+}RfTestCmdSetTxDataCnfParam;
+/* -------------------------------------- */
+
+
+/* -------------------- *\
+|* GET TX CMD CNF Struct *|
+ \* -------------------- */
+typedef enum
+{
+ RF_TEST_GET_TX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_GET_TX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_GET_TX_DATA_BITMAP_COUNT_MISMATCH = 2,
+ RF_TEST_GET_TX_DATA_OFFSET_MISMATCH = 3,
+ RF_TEST_GET_TX_DATA_NULL_PEER_BUF = 4,
+ RF_TEST_GET_TX_DATA_PEER_BUF_SIZE_OVERFLOW = 5,
+ RF_TEST_GET_TX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestGetTxData_Cnf_Status_E;
+
+//typedef struct
+//{
+// kal_uint16 count;
+// kal_uint16 offset;
+//}RfTestGetParamDynamicEntryElm_T;
+
+typedef enum
+{
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_MAX,
+}RfTestGetTxData_RunTime_Status_E;
+
+typedef struct
+{
+ RfTestGetTxData_Cnf_Status_E get_txdata_cnf_status;
+ RfTestParamDynamicEntryElm_T type1_ramptable_data;
+ RfTestParamDynamicEntryElm_T type2_epsk_interramptable_data;
+ RfTestParamDynamicEntryElm_T type3_txpc_data;
+ RfTestParamDynamicEntryElm_T type4_epskpa_data;
+ RfTestGetTxData_RunTime_Status_E type1_ramptable_result[8];
+ RfTestGetTxData_RunTime_Status_E type2_epsk_interramptable_result[4];
+ RfTestGetTxData_RunTime_Status_E type3_txpc_result[2];
+ RfTestGetTxData_RunTime_Status_E type4_epskpa_result; //RFSpecialCoef.tx.orionRFtx.data...
+}RfTestCmdGetTxDataCnfParam;
+
+typedef struct
+{
+ union
+ {
+ kal_int32 get_txdata_cnf_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ #if MD_DRV_IS_EPSK_TX_SUPPORT
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ #endif
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+ } confirm;
+}RfTestCmdGetTxDataCnfPdu;
+/* -------------------------------------- */
+
+
+
+/* -------------------- *\
+|* SET RX CMD CNF Struct *|
+ \* -------------------- */
+#if IS_2G_RXD_SUPPORT
+typedef enum
+{
+ RF_TEST_SET_RX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_SET_RX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_SET_RX_DATA_TYPE2_OFFSET_ERROR = 2, // Type-2 count/offset mismatch
+ RF_TEST_SET_RX_DATA_TYPE3_OFFSET_ERROR = 3, // Type-3 count/offset mismatch
+ RF_TEST_SET_RX_DATA_TYPE4_OFFSET_ERROR = 4, // Type-4 count/offset mismatch
+ RF_TEST_SET_RX_DATA_EXCESS_REQ_PDU_LENGTH = 5,
+ RF_TEST_SET_RX_DATA_CNF_CHECK_OFFSET_PASS = 6,
+ RF_TEST_SET_RX_DATA_BITMAP_COUNT_MISMATCH = 7,
+ RF_TEST_SET_RX_DATA_NULL_PEER_BUF = 8,
+ RF_TEST_SET_RX_DATA_RECORD_SET_FAIL = 9,
+ RF_TEST_SET_RX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestSetRxData_Cnf_Status_E;
+
+typedef enum
+{
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_MAX,
+}RfTestSetRxData_RunTime_Status_E;
+
+typedef struct
+{
+ kal_uint16 count;
+ kal_uint16 bitmap; //add bitmap for tool team debug
+}RfTestSetRxDataCnfParamEntry_T; // Similar with RfTestParamDynamicEntryElm_T
+
+typedef struct
+{
+ RfTestSetRxData_Cnf_Status_E set_rxdata_cnf_status;
+ RfTestSetRxDataCnfParamEntry_T type1_result;
+ RfTestSetRxDataCnfParamEntry_T type2_result;
+ RfTestSetRxData_RunTime_Status_E type1_rxpathloss_result[8];
+ RfTestSetRxData_RunTime_Status_E type2_wcoef_result[2];
+}RfTestCmdSetRxDataCnfParam;
+/* -------------------------------------- */
+
+
+/* -------------------- *\
+|* GET RX CMD CNF Struct *|
+ \* -------------------- */
+typedef enum
+{
+ RF_TEST_GET_RX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_GET_RX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_GET_RX_DATA_BITMAP_COUNT_MISMATCH = 2,
+ RF_TEST_GET_RX_DATA_OFFSET_MISMATCH = 3,
+ RF_TEST_GET_RX_DATA_NULL_PEER_BUF = 4,
+ RF_TEST_GET_RX_DATA_PEER_BUF_SIZE_OVERFLOW = 5,
+ RF_TEST_GET_RX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestGetRxData_Cnf_Status_E;
+
+//typedef struct
+//{
+// kal_uint16 count;
+// kal_uint16 offset;
+//}RfTestGetParamDynamicEntryElm_T;
+
+typedef enum
+{
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_MAX,
+}RfTestGetRxData_RunTime_Status_E;
+
+typedef struct
+{
+ RfTestGetRxData_Cnf_Status_E get_rxdata_cnf_status;
+ RfTestParamDynamicEntryElm_T type1_rxpathloss_data;
+ RfTestParamDynamicEntryElm_T type2_wcoef_data;
+ RfTestGetRxData_RunTime_Status_E type1_rxpathloss_result[8];
+ RfTestGetRxData_RunTime_Status_E type2_wcoef_result[2];
+}RfTestCmdGetRxDataCnfParam;
+
+typedef struct
+{
+ union
+ {
+ kal_int32 get_rxdata_req_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_SetGetRxPathLossEntry_Type1_T type1_pathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+ } confirm;
+}RfTestCmdGetRxDataCnfPdu;
+#endif //#if IS_2G_RXD_SUPPORT
+/* -------------------------------------- */
+
+/*GET TPO CMD CNF struct*/
+typedef struct
+{
+ kal_bool ok;
+ kal_int16 power_apcdac_offset; // unit:DAC
+ kal_int16 power_dB_offset; // 0.125 dB
+} RfTestResultGetTPO;
+
+typedef union
+{
+ kal_bool ok;
+ kal_int8 m_i1RfPwrState_FT;
+ kal_int16 m_sBBPowerArrary[20]; /// META_Rf_QueryBBPowerList_r output
+ kal_uint8 nvramAccessResult; //RF_NVRAM_ACCESS_CAl_DATA_RESULT
+ kal_uint8 m_u1NSFTRxQual; /// L1TST_ReportRXQual output
+ kal_uint8 m_ucNumOfGainRf; /// META_Rf_QueryNumOfGainRf_r output
+ kal_uint16 m_u2NSFTRxLevel; /// L1TST_ReportRXLEV output
+ kal_uint16 temperature; /// L1TST_TXPC_GetTemperature output: RF_TEST_CMD_GET_TXPC_TEMPERATURE
+ kal_uint16 m_txpc_subband_compensation[11]; /// L1TST_TXPC_CL_GetSubband output
+ RF_DTS_GET_RESULT_STATUS dts_get_result_status;
+ RfGetAfcOffsetResult afc_result;
+ RfGetAfcDacValueAtRTXOffsetCal GetAfcDacValueAtRTXOffsetCal;
+ RfNSFTSBERResult m_rNSFTSBER;
+ RfTestResultPm pm;
+ RfTestResultAfc afc;
+ RfTestResultSinewaveAfcGetTempFreq afc_gpscoclockv2_result;
+ RfTestResultGetBSI GetBSI;
+ RfTestResultGetRFID rfid;
+ RfTestResultPDValue txpc_cnf;
+ RfTestResultGetBBTXCfg2 BBTxCfg2;
+ RfTestResultGetBBTXCfg3 BBTxCfg3;
+ RfTestResultGetBBTXCfg4 BBTxCfg4;
+ RfTestResultListModeNSFT List_Mode_NSFT_result;
+ RfTestResultMsCapability ms_capability;
+ RfTestResultMsCapabilityEx ms_capability_ex;
+ RfTestResult32kCalibration calibration_32k;
+ RfTestResultRfTemperatureInfo rfTemperatureInfo;
+ RfCheckIfFuncExist CheckIfFuncExist;
+ RfTestCmdSetTxDataCnfParam set_txdata_cnf;
+ RfTestCmdGetTxDataCnfParam get_txdata_cnf;
+ #if IS_2G_RXD_SUPPORT
+ kal_uint16 m_u2NSFTRxLevel_v5[GSM_RF_MAX_RX_ANT_NUM]; /// L1TST_ReportRXLEV output
+ RfTestResultPm_V5 pm_v5;
+ RfTestCmdSetRxDataCnfParam set_rxdata_cnf;
+ RfTestCmdGetRxDataCnfParam get_rxdata_cnf;
+ RfTestResultRxGainCalculate_V5 rx_gain_calculate_cnf;
+ #endif
+ RfTestResultGetTPO tpo_result;
+} RfTestResultParam;
+
+/*******************************************************************************
+*
+* Message structures defined for L1TST Interface
+*
+*******************************************************************************/
+typedef struct
+{
+ FT_HDR
+ RfTestCmdType type;
+ RfTestCmdParam param;
+} ft_rf_test_req_T;
+
+typedef struct
+{
+ FT_HDR
+ RfTestCmdType type;
+ RfTestResultParam param;
+} ft_rf_test_cnf_T;
+
+typedef ft_rf_test_req_T ft_to_gl1tst_struct;
+typedef ft_rf_test_cnf_T gl1tst_to_ft_struct;
+
+typedef ft_rf_test_req_T ft_rf_test_req_id_struct;
+typedef ft_rf_test_cnf_T ft_rf_test_cnf_id_struct;
+
+#endif /* _L1TST_FT_MSG_STRUCT_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct_gen95.h b/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct_gen95.h
new file mode 100644
index 0000000..1821f40
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct_gen95.h
@@ -0,0 +1,2006 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_ft_msg_struct.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Struct definition of L1TST - FT interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ * 10 09 2018 yungshian.lai
+ * [MOLY00349865] TX POWER OFFSET feature uniform - VMOLY Trunk [ERS00016793].
+ *
+ * 09 18 2018 yungshian.lai
+ * [MOLY00349883] [MT6295][2G] NSFT RxLevel Resolution Enhancement- TST part - VMOLY Trunk.
+ *
+ * 03 30 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE option rename & NSFT swap patch.
+ *
+ * 03 02 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE Trunk TST part.
+ *
+ * 09 08 2017 yungshian.lai
+ * [MOLY00275140] [Bianco] 93 2G Cal Time Reduction Development - UMOLYA - CNF bitmap.
+ *
+ * 09 01 2017 yungshian.lai
+ * [MOLY00275140] [Bianco] 93 2G Cal Time Reduction Development - UMOLYA.
+ *
+ * 07 21 2017 yungshian.lai
+ * [MOLY00266063] [EL1TST] GPS coclock v2.0 Development - 4G Read AuxADC /2G add capability and modify DHL PSTrace - UMOLYA.
+ *
+ * 01 11 2017 yungshian.lai
+ * [MOLY00223923] [Bianco Bring-up][GSM] MT6293 eLNA Development & GPScoclock V2.0.
+ *
+ * 05 03 2016 yungshian.lai
+ * [MOLY00163211] [L1TST] Sawless Development & DTS_STEP_CNT=512
+ * - modify LID VER & Struct naming & uint16 &SetRxNVRAM.
+ *
+ * 01 29 2016 yungshian.lai
+ * [MOLY00163211] [L1TST] Sawless Development & DTS_STEP_CNT=512.
+ *
+ * 06 12 2015 yungshian.lai
+ * [MOLY00121036] [TK6291][L1TST] NSFT list mode send pdu modify
+ * .
+ *
+ * 04 24 2015 yungshian.lai
+ * [MOLY00109190] [TK6291][L1TST] Add lack CMD,trace and modify TADC bitmap.
+ *
+ * 01 03 2014 th.yeh
+ * [MOLY00052308] [L1D][Modify] FT/L1D dual-core modem interface development
+ * .
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_FT_MSG_STRUCT_H_
+#define _L1TST_FT_MSG_STRUCT_H_
+#include "l1_types_public.h"
+//#if IS_2G_RXD_SUPPORT
+#include "ft_msg_common.h" //For L1D read RXD Info struct
+//#endif
+
+/*************************************************************************
+* Include Statements for PLTABLE_SIZE
+ *************************************************************************/
+#include "l1cal.h"
+
+
+/*******************************************************************************
+*
+* Data structures used in Message Definition
+*
+*******************************************************************************/
+
+typedef enum
+{
+ FT_RF_PWR_STATE_UNKNOWN = -1,
+ FT_RF_PWR_STATE_ON,
+ FT_RF_PWR_STATE_OFF,
+}ft_rf_power_state_enum;
+
+typedef enum
+{
+ RF_TEST_CMD_PM = 0
+ ,RF_TEST_CMD_AFC = 1
+ ,RF_TEST_CMD_NB_TX = 2
+ ,RF_TEST_CMD_CONTINUOUS_RX = 3
+ ,RF_TEST_CMD_CONTINUOUS_TX = 4
+ ,RF_TEST_CMD_SET_BB_TX_CFG = 5 //phase out
+ ,RF_TEST_CMD_BAND_SEL = 6
+ ,RF_TEST_CMD_STOP = 7
+ ,RF_TEST_CMD_MULTISLOT_TX = 8
+ ,RF_TEST_CMD_SET_RAMPAPCLVL = 9
+ ,RF_TEST_CMD_SET_AFCDACVALUE = 10 //phase out
+ ,RF_TEST_CMD_SET_BBTXCFG2 = 11 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG2 = 12 //phase out
+ ,RF_TEST_CMD_SET_CRYSTAL_CFG = 13
+ ,RF_TEST_CMD_BBTX_AUTOCAL = 14 //phase out
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY = 15
+ ,RF_TEST_CMD_SET_RAMPTABLE = 16
+ ,RF_TEST_CMD_SET_AFC_SINWAVE_DETECTION = 17
+ ,RF_TEST_CMD_MULTISLOT_TX_EX = 18
+ ,RF_TEST_CMD_EPSK_SET_RAMPAPCLVL = 19
+ ,RF_TEST_CMD_GET_RFID = 20
+ ,RF_TEST_CMD_SET_IMMEDIATE_BSI = 21
+ ,RF_TEST_CMD_GET_IMMEDIATE_BSI = 22
+ ,RF_TEST_CMD_SET_SPECIALCOEF = 23 //phase out
+ ,RF_TEST_CMD_CONTINUOUS_TX_EX = 24
+ ,RF_TEST_CMD_SET_BBTXCFG3 = 25 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG3 = 26 //phase out
+ ,RF_TEST_CMD_IF_TWO_APC_DC_OFFSET_SUPPORT = 27
+ ,RF_TEST_CMD_CONTINUOUS_TX_EX2 = 28
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY_EX = 29
+ ,RF_TEST_CMD_GET_AFCDACVALUE_AT_RTX_OFFSET_CAL = 30
+ ,RF_TEST_CMD_SET_BBTXCFG4 = 31 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG4 = 32 //phase out
+ ,RF_TEST_CMD_SET_BBTXCFG5 = 33 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG5 = 34 //phase out
+ ,RF_TEST_CMD_CALIBRATE_32K = 35
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY_EX2 = 36
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_50P = 37 // including AFC and RX pathloss: downlink //RF_TEST_CMD_START_FDT_DL
+ ,RF_TEST_CMD_START_FDT_UL_50P = 38 // APC calibration :uplink //RF_TEST_CMD_START_FDT_UL
+ ,RF_TEST_CMD_EPSK_SET_RAMPTABLE = 39 //phase out
+ ,RF_TEST_CMD_GET_AFC_DAC_OFFSET = 40 //phase out
+ ,RF_TEST_CMD_SET_AFC_DAC_OFFSET = 41 //phase out
+ ,RF_TEST_CMD_SET_BBTXCFG6 = 42 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG6 = 43 //phase out
+ ,RF_TEST_CMD_GET_FDT_RESULT_50P = 44 //RF_TEST_CMD_GET_FDT_RESULT
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_50P = 45
+ ,RF_TEST_CMD_NSFT_CHANGE_SETTING = 46
+ ,RF_TEST_CMD_NSFT_START = 47
+ ,RF_TEST_CMD_NSFT_STOP = 48
+ ,RF_TEST_CMD_NSFT_CHANGE_POWER = 49 //phase out?
+ ,RF_TEST_CMD_NSFT_START_EPSK_TX = 50
+ ,RF_TEST_CMD_OE_PATTERN_READY = 51
+ ,RF_TEST_CMD_POWER_ON = 52
+ ,RF_TEST_CMD_POWER_OFF = 53
+ ,RF_TEST_CMD_QUERY_POWER_STATE_IN_FT = 54 //phase out?
+ ,RF_TEST_CMD_AFC_TYPE_QUERY_READY = 55
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_GMSK = 56
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_EPSK = 57
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_TABLE_GMSK = 58 //phase out
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_TABLE_EPSK = 59 //phase out
+ ,RF_TEST_CMD_GET_SPECIALCOEF = 60
+ ,RF_TEST_CMD_NSFT_CONFIG_SBER = 61
+ ,RF_TEST_CMD_NSFT_GET_SBER = 62
+ ,RF_TEST_CMD_NSFT_START_RXLEV = 63
+ ,RF_TEST_CMD_NSFT_GET_RXLEV = 64
+ ,RF_TEST_CMD_NSFT_GET_RXQUAL = 65
+ ,RF_TEST_CMD_IF_PM = 66
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_BY_PCL_GMSK = 67 //phase out
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_BY_PCL_EPSK = 68 //phase out
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_GMSK = 69 //phase out
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_EPSK = 70 //phase out
+ ,RF_TEST_CMD_GET_TXPC_SUBBAND_GMSK = 71 //phase out
+ ,RF_TEST_CMD_GET_TXPC_SUBBAND_EPSK = 72 //phase out
+ ,RF_TEST_CMD_GET_TXPC_TEMPERATURE = 73
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY_EX3 = 74
+ /* [LPM CAL] */
+ ,RF_TEST_CMD_SET_DCXO_POWER_MODE = 75 //32k Less
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_50P = 76 //32k Less, Check func is False, open if need //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_EX
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_50P = 77 //32k Less, Check func is False, open if need //RF_TEST_CMD_GET_FDT_RESULT_EX
+ ,RF_TEST_CMD_SET_EDGE_TX_OCT_PA_SPECIAL_COEF = 78
+ ,RF_TEST_CMD_TXPC_CL_RESET_PD_DATA = 79 /**< \brief reset TX power control close loop pd value */
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_100P = 80 //RF_TEST_CMD_START_FDT_DL_BIG
+ ,RF_TEST_CMD_START_FDT_UL_100P = 81 //RF_TEST_CMD_START_FDT_UL_BIG
+ ,RF_TEST_CMD_GET_FDT_RESULT_100P = 82 //RF_TEST_CMD_GET_FDT_RESULT_BIG
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_100P = 83 //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_BIG
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_100P = 84 //32k Less, //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_EX_BIG
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_100P = 85 //32k Less, Check func is False, open if need //RF_TEST_CMD_GET_FDT_RESULT_EX_BIG
+ ,RF_TEST_CMD_MULTISLOT_TX_WITH_AUXADC_READ = 86 /**< \brief TX RF on and read AuxADC at same time for CoTsx */
+ ,RF_TEST_CMD_GAIN_RF_TX = 87 //Marked, open if need /**< \brief EDGE TX gain rf cal */
+ ,RF_TEST_CMD_QUERY_GAIN_RF_NUM = 88 //Marked, open if need /**< \brief Query gain rf target support number (max: 20)*/
+ ,RF_TEST_CMD_GET_BB_POWER_LIST = 89 //Marked, open if need /**< \brief Get BB power list from target */
+ ,RF_TEST_CMD_CHECK_IF_FUNC_EXIST = 90 /**< \brief Reserved. META DLL not send directly */
+ ,RF_TEST_CMD_GET_TEMPERATURE_INFO = 91
+ ,RF_TEST_CMD_SET_DT_PATH_FLAG = 92 /**< \brief Set L1 flag to use second path */
+ ,RF_TEST_CMD_LIST_MODE_NSFT_START = 93 /**< \brief 2G list mode nsft*/
+ ,RF_TEST_CMD_START_FDT_UL_512P = 94 /** reduce UL CMD round trip number*/ //RF_TEST_CMD_START_FDT_UL_BIG_V2
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P = 95 /** For sawless lna mode and reduce DL CMD round trip number*/
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P = 96 /** For sawless lna mode and reduce DL CMD round trip number*/ //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_EX_BIG_V2
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_512P = 97 /** For sawless lna mode and reduce DL CMD round trip number*/
+ ,RF_TEST_CMD_SAWLESS_PM = 98 /** Force LTF on - for sawless lna mode in trad calibration*/
+ ,RF_TEST_CMD_SET_RX_PATH_LOSS = 99 /** FT Set data to runtime var, use flag to decide whether to update NVRAM or not*/
+ ,RF_TEST_CMD_GET_RX_PATH_LOSS = 100 /** FT Get data from runtime var (because runtime var==NVRAM)*/
+ ,RF_TEST_CMD_SET_RX_PATH_LOSS_V3 = 101 //For 93 SET_RX_PATH_LOSS elna+g6, elna bypass+g1 /** FT Set data to runtime var, use flag to decide whether to update NVRAM or not*/
+ ,RF_TEST_CMD_GET_RX_PATH_LOSS_V3 = 102 //For 93 GET_RX_PATH_LOSS elna+g6, elna bypass+g1 /** FT Get data from runtime var (because runtime var==NVRAM)*/
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P_V3 = 103 //Add New CMD, For 6293 compatible with 92 tool procedure - RFTestCmdDTS_Lpm_512P_V3
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P_V3 = 104 //Add New CMD, For 6293 compatible with 92 tool procedure (previous CMD)
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_512P_V3 = 105 //Add New CMD, For 6293 compatible with 92 tool procedure (previous CMD)
+ ,RF_TEST_CMD_SINEWAVE_AFC_GET_TEMP_FREQ = 106 /*For GPS co-clock V2.0, use this CMD to get temperature and freq offset*/
+ ,RF_TEST_CMD_SET_WCOEF = 107 //Cal time reduction development - Wcoef part
+ ,RF_TEST_CMD_GET_WCOEF = 108 //Cal time reduction development - Wcoef part
+ ,RF_TEST_CMD_SET_TXDATA = 109 //Cal time reduction development - Tx part
+ ,RF_TEST_CMD_GET_TXDATA = 110 //Cal time reduction development - Tx part
+ ,RF_TEST_CMD_GET_TPO_VALUE = 111 // For NSFT Adjust TPO support - Phase Out
+ ,RF_TEST_CMD_SET_TPO_VALUE = 112 // For NSFT Adjust TPO support - Phase Out
+ ,RF_TEST_CMD_GET_RXD_INFO_V5 = 113 //Gen95: Get Rx DL Power or ELNA Type info
+ ,RF_TEST_CMD_SET_RXDATA_V5 = 114 //RF_TEST_CMD_SET_RX_PATH_LOSS_V5
+ ,RF_TEST_CMD_GET_RXDATA_V5 = 115 //RF_TEST_CMD_SET_RX_PATH_LOSS_V5
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P_V5 = 116 //Gen95: RFTestCmdDTS_Lpm_512P_V5
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P_V5 = 117 //Gen95: RFTestCmdDTS_Lpm_512P_V5
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_512P_V5 = 118
+ ,RF_TEST_CMD_PM_V5 = 119 // Gen95: Trad Cal
+ ,RF_TEST_CMD_IF_PM_V5 = 120 // Gen95: RF Tool & Trad Cal
+ ,RF_TEST_CMD_CONTINUOUS_RX_V5 = 121 // Gen95: RF Tool & Trad Cal
+ ,RF_TEST_CMD_NSFT_START_V5 = 122 // Gen95
+ ,RF_TEST_CMD_NSFT_GET_RXLEV_V5 =123 // Gen95
+ ,RF_TEST_CMD_NSFT_CHANGE_SETTING_V5 = 124 // Gen95
+ ,RF_TEST_CMD_LIST_MODE_NSFT_START_V5 = 125 // Gen95
+ ,RF_TEST_CMD_RX_GAIN_CALCULATE_V5 = 126 // Gen95
+ ,RF_TEST_CMD_SET_NSFT_RXLEV_PRECISION = 127 // Gen95
+ ,RF_TEST_CMD_GET_TPO_VALUE_V5 = 128 // For NSFT Adjust TPO support - Gen95
+ ,RF_TEST_CMD_SET_TPO_VALUE_V5 = 129 // For NSFT Adjust TPO support - Gen95
+ //Remember to add req/result param to FT_GL1TST_UnionTag.txt & add CMD to CheckFunction
+ /*----------------------------------------------------------------------------------------------------*/
+ ,RF_TEST_CMD_GP_TOOL_COMMAND_START
+ ,RF_TEST_CMD_END
+ ,RF_TEST_CMD_MAX = 0x7FFFFFFF
+} RfTestCmdType;
+
+typedef enum {
+ MS_GSM = 0
+ ,MS_GPRS
+ ,MS_EGPRS_RX_ONLY
+ ,MS_EGPRS_FULL_FUNCTION
+} MS_CAPABILITY_E;
+
+typedef struct
+{
+ ARFCN arfcn;
+ kal_int8 sampleNoPerFrame;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain;
+ kal_int16 frames;
+} RfTestCmdPm;
+
+typedef struct
+{
+ ARFCN arfcn;
+ kal_int16 dacValue;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain;
+ kal_int16 testNumber;
+} RfTestCmdAfc;
+
+typedef struct
+{
+ ARFCN arfcn;
+ BSIC bsic;
+ kal_int8 bitmask;
+ Power txPowerLev;
+ kal_int16 frames;
+ kal_int16 dacValue;
+ APCTxPattern burstTypeNB;
+} RfTestCmdNbTx;
+
+typedef struct
+{
+ ARFCN arfcn;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain;
+ kal_bool onOff;
+} RfTestCmdContRx;
+
+typedef struct
+{
+ ARFCN arfcn;
+ ContTxPattern pattern;
+ kal_bool onOff;
+} RfTestCmdContTx;
+
+typedef struct {
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+} RfTestCmdSetBBTXCfg;
+
+typedef struct {
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+ kal_int8 TxCalbias;
+ kal_int8 TxIQSwap;
+ kal_int8 TxCMV;
+ kal_int8 TxGain;
+ kal_int8 TxCalrcsel;
+} RfTestCmdSetBBTXCfg2;
+
+typedef struct {
+ ARFCN arfcn;
+ BSIC bsic;
+ kal_int8 timeSlotmask;
+ Power powerLev[4];
+ CodingScheme cs[4];
+ TimingAdvance ta;
+ kal_int32 frames;
+ kal_int16 dacValue;
+} RfTestCmdMultiSlotTX;
+
+typedef struct {
+ kal_int32 rf_band;
+ kal_int32 power_level;
+ kal_int32 apc_dac;
+} RfTestCmdSetRampApcLevel;
+
+typedef struct {
+ kal_int16 dacValue;
+} RfTestCmdSetAfcDacValue;
+
+typedef struct {
+ kal_int32 cap_id;
+} RfTestCmdSetCrystalCfg;
+
+typedef struct {
+ kal_int32 rf_band;
+} RfTestCmdSetRampTable;
+
+typedef struct {
+ kal_bool is_sinwave;
+} RfTestCmdSetAfcSinWave;
+
+typedef struct {
+ kal_uint32 bsi_data;
+} RfTestCmdSetBSI;
+
+typedef struct {
+ kal_uint32 bsi_addr;
+} RfTestCmdGetBSI;
+
+typedef struct {
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+ kal_int8 TxCalbias;
+ kal_int8 TxIQSwap;
+ kal_int8 TxCMV;
+ kal_int8 TxGain;
+ kal_int8 TxCalrcsel;
+ kal_int8 TxPhasesel;
+} RfTestCmdSetBBTXCfg3;
+
+typedef struct
+{
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+ kal_int8 TxCalbias;
+ kal_int8 TxIQSwap;
+ kal_int8 TxCMV;
+ kal_int8 TxGain;
+ kal_int8 TxCalrcsel;
+ kal_int8 TxPhasesel;
+ kal_int8 TxCoarseI;
+ kal_int8 TxCoarseQ;
+
+}RfTestCmdSetBBTXCfg4;
+
+typedef struct {
+ ARFCN arfcn;
+ BSIC bsic;
+ kal_int8 timeSlotmask;
+ Power powerLev[4];
+ CodingScheme cs[4];
+ TimingAdvance ta;
+ kal_int32 frames;
+ kal_int16 dacValue;
+ APCTxPattern pattern;
+ kal_uint16 pattern_data;
+} RfTestCmdMultiSlotTXEx;
+
+typedef struct {
+ ARFCN arfcn;
+ ContTxPattern pattern;
+ kal_uint16 pattern_data;
+ kal_bool onOff;
+ kal_uint16 modtype;
+} RfTestCmdContTxEx;
+
+typedef struct {
+ ARFCN arfcn;
+ ContTxPattern pattern;
+ kal_uint16 pattern_data;
+ kal_bool onOff;
+ kal_uint16 modtype;
+ Power powerLev;
+} RfTestCmdContTxEx2;
+
+typedef struct{
+ FrequencyBand band;
+ ARFCN BCH_ARFCN;
+ ARFCN TCH_ARFCN;
+ Gain BCH_gain;
+ Gain TCH_gain;
+ TSC tsc;
+ TimeSlot TCH_slot;
+ Power tx_power_level;
+ kal_bool is_EPSK_tx;
+ CodingScheme epsk_cs;
+}RfTestCmdNSFTParam;
+
+/** ----- 2G nsft V5 -----*/
+#if IS_2G_RXD_SUPPORT
+typedef struct{
+ FrequencyBand band;
+ ARFCN BCH_ARFCN;
+ ARFCN TCH_ARFCN;
+ Power BCH_DL_Power;
+ Power TCH_DL_Power;
+ TSC tsc;
+ TimeSlot TCH_slot;
+ Power tx_power_level;
+ kal_bool is_EPSK_tx;
+ CodingScheme epsk_cs;
+ kal_uint8 Antenna; //GSM_AntDimension
+}RfTestCmdNSFTParam_V5;
+#endif
+/** ----------------------*/
+
+
+typedef struct{
+ Power tx_power_level;
+}RfTestCmdNSFTPowerChangeParam;
+
+/** ----- 2G list mode nsft -----*/
+typedef struct
+{
+ kal_uint8 cmd_count;
+} RfTestCmdListModeNSFTParam;
+
+typedef struct
+{
+ kal_uint8 cmd_type;
+} RfTestCmdListModeNSFTCommonParam;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_int16 sync_power;
+ kal_uint8 sync_slot_offset;
+} RfTestCmdListModeNSFT_Sync_REQ;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 tsc;
+ kal_uint8 trx_type;
+ kal_int16 tx_power;
+} RfTestCmdListModeNSFT_Trigger_REQ;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 tsc;
+ kal_uint8 trx_type;
+ kal_int8 tx_pcl[8];
+ kal_int16 rx_power;
+ kal_int8 repeat_count[8];
+} RfTestCmdListModeNSFT_CHMeas_REQ;
+
+typedef union
+{
+ RfTestCmdListModeNSFT_Sync_REQ sync;
+ RfTestCmdListModeNSFT_Trigger_REQ trigger;
+ RfTestCmdListModeNSFT_CHMeas_REQ test;
+} RfTestCmdListModeNSFTCmdParam;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCmdParam param[60];
+} RfTestCmdListModeNSFT;
+// --------------------------------- //
+
+
+
+/** ----- 2G list mode nsft V5 -----*/
+#if IS_2G_RXD_SUPPORT
+//Req Param
+typedef struct
+{
+ kal_uint8 cmd_count;
+ kal_uint8 Antenna; // GSM_AntDimension
+} RfTestCmdListModeNSFTParam_V5;
+
+
+//Req Pdu
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 trx_type; //new param
+ kal_int16 sync_power;
+ kal_uint8 sync_slot_offset;
+} RfTestCmdListModeNSFT_Sync_REQ_V5;
+
+typedef RfTestCmdListModeNSFT_Trigger_REQ RfTestCmdListModeNSFT_Trigger_REQ_V5;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 tsc;
+ kal_uint8 trx_type;
+ kal_int8 tx_pcl[8];
+ kal_int16 rx_power;
+ kal_int8 repeat_count[8];
+} RfTestCmdListModeNSFT_CHMeas_REQ_V5;
+//typedef RfTestCmdListModeNSFT_CHMeas_REQ RfTestCmdListModeNSFT_CHMeas_REQ_V5;
+
+typedef union
+{
+ RfTestCmdListModeNSFT_Sync_REQ_V5 sync;
+ RfTestCmdListModeNSFT_Trigger_REQ_V5 trigger;
+ RfTestCmdListModeNSFT_CHMeas_REQ_V5 test;
+} RfTestCmdListModeNSFTCmdParam_V5;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCmdParam_V5 param[60];
+} RfTestCmdListModeNSFT_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+// --------------------------------- //
+
+
+
+// ***************************************** //
+// FDT Calibration
+// ***************************************** //
+#define FT_MAX_STEP_CNT_50P 50
+#define FT_MAX_STEP_CNT_100P 100
+#define FT_MAX_STEP_CNT_512P 512
+
+typedef struct
+{
+ FrequencyBand band;
+ ARFCN arfcn;
+ kal_int16 dac_value[33];
+ Gain gain;
+ kal_int16 repeat_cnt; // repetitive test counts (frames) for each AFC DAC value
+ kal_bool capid_cal; // capid calibration ctrl
+ kal_bool linear_cal; // 33 stages calibration ctrl
+ //kal_int8 capid_min; // min value for capid range when capid_cal is True; capid when capid_cal is False
+ //kal_int8 capid_max; // max value for capid range
+ kal_int32 capid_min; // min value for capid range when capid_cal is True; capid when capid_cal is False
+ kal_int32 capid_max; // max value for capid range
+} RFTestCmdDSSAfc;
+
+#define RF_TEST_CMD_DSSPL_HDR \
+ FrequencyBand band; \
+ ARFCN arfcn; \
+ Gain gain[6]; \
+ kal_int16 repeat_cnt; \
+
+typedef struct
+{
+ //FrequencyBand band;
+ //ARFCN arfcn;
+ //Gain gain[6]; // gain for rx slot 0/1/2/3/4/5
+ //kal_int16 repeat_cnt; // repetitive test counts (frames) for each ARFCN value
+ RF_TEST_CMD_DSSPL_HDR
+ //kal_int16 dac_value; // Use InitDacValue from AFC calibration when dacValue = 0 (or -1)
+} RFTestCmdDSSPL;
+
+typedef enum
+{
+ LNA_NULL, //For old CMD, tool will not set gsm_lna_mode
+ LNA_HIGH,
+ LNA_MID,
+ LNA_LOW,
+ LNA_W_COEF,
+ LNA_SAWLESS_MID
+}RFTestCmdLNACalType;
+
+typedef struct
+{
+ RF_TEST_CMD_DSSPL_HDR
+ RFTestCmdLNACalType gsm_lna_mode; //0(Null) 1(high) 2(mid) 3(low) 4(w-coef) 5(sawless mid) 6(elna+G6) 7(elna bypass+G1)
+} RFTestCmdDSSPL_V2;
+
+typedef enum
+{
+ LNA_NULL_V3, //For old CMD, tool will not set gsm_lna_mode
+ LNA_HIGH_V3,
+ LNA_MID_V3,
+ LNA_LOW_V3,
+ LNA_W_COEF_V3,
+ LNA_SAWLESS_MID_V3,
+ ELNA_HIGH_SENSITIVITY,
+ ELNA_BYPASS_LOW_MAXPIN
+}RFTestCmdLNACalType_V3;
+
+typedef struct
+{
+ RF_TEST_CMD_DSSPL_HDR
+ RFTestCmdLNACalType_V3 gsm_lna_mode; //0(Null) 1(high) 2(mid) 3(low) 4(w-coef) 5(sawless mid) 6(elna+G6) 7(elna bypass+G1)
+} RFTestCmdDSSPL_V3;
+
+#define RF_TEST_CMD_DTS_HDR \
+ kal_bool afc_cal; \
+ kal_bool pl_cal; \
+ kal_int8 sync_sb_num; \
+ kal_int16 power; \
+ RFTestCmdDSSAfc AfcDSS;
+
+typedef struct
+{
+ //kal_bool afc_cal;
+ //kal_bool pl_cal; // Control whether Path loss calibration is needed or not
+ //kal_int8 sync_sb_num; // the SB frame numbers needed for sync process before path loss calibration
+ //kal_int16 power; // the power level expected to measure from test set
+ //RFTestCmdDSSAfc AfcDSS;
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_50P-2];
+} RFTestCmdDTS_50P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_100P-2];
+} RFTestCmdDTS_100P;
+
+/* [LPM CAL] */
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_50P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_50P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_100P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_100P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ RFTestCmdDSSPL_V2 PathLossDSS[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_512P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ RFTestCmdDSSPL_V3 PathLossDSS[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_512P_V3;
+
+
+/* ----RF_TEST_CMD_GET_CALIBRATION_INFO_FOR_RXD_V5 ---- */
+#if IS_2G_RXD_SUPPORT
+typedef enum
+{
+ NON_ELNA,
+ ELNA_BYPASS_NB_MATCH,
+ ELNA_BYPASS_WB_MATCH,
+ ELNA_ALWAYS_ON
+} RfTestRx_Elna_Type_E;
+
+typedef enum
+{
+ RX_LNA_NONE = 0,
+ RX_LNA_UTRA_HIGH = 1,
+ RX_LNA_HIGH = 2,
+ RX_LNA_MID = 3,
+ RX_LNA_MID_SAWLESS = 4,
+ RX_LNA_LOW = 5,
+ RX_LNA_BYPASS_LOW = 6, //the same as GSM_RF_MAX_RX_GAIN_NUM_V5
+} RfTestRx_Lna_Mode_E;
+
+typedef enum
+{
+ SUPPORT_BAND_GSM400,
+ SUPPORT_BAND_GSM850,
+ SUPPORT_BAND_GSM900,
+ SUPPORT_BAND_DCS1800,
+ SUPPORT_BAND_PCS1900,
+ SUPPORT_BAND_NUM
+} RfTestSupportBand; //FrequencyBand
+
+typedef struct
+{
+ //FHC
+ kal_uint8 seq_num;
+ kal_int16 dlpow_default[GSM_RF_MAX_RX_GAIN_NUM_V5]; //0.125 dBm
+ kal_int16 dlpow_lbound[GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_int16 dlpow_hbound[GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_uint8 lna_enum_type[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5]; //RfTestRx_Lna_Mode_E
+ kal_uint8 antenna_enable[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_int16 dlpow_wcoef_default; //0.125 dBm
+ kal_int16 dlpow_wcoef_lbound;
+ kal_int16 dlpow_wcoef_hbound;
+ kal_int16 wcoef_arfcn[8]; //each band woef arfcn, [850][900][DCS][PCS]=[1][2][8][6]
+
+ //for trad cal
+ kal_int16 gain_default[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5]; // 0.125 dB
+ kal_int16 wcoef_gain_default[GSM_RF_MAX_RX_ANT_NUM]; // 0.125 dB
+ //RF Tool
+ kal_uint8 elna_type[GSM_RF_MAX_RX_ANT_NUM]; // RfTestRx_Elna_Type_E
+ kal_int16 gain_hbound[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_int16 gain_lbound[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5];
+} RfTestCmdCalInfoV5_T; // RfTestElnaInfoV5_T
+
+typedef struct
+{
+ RfTestCmdCalInfoV5_T GSM_Band_Info[SUPPORT_BAND_NUM-1]; //No GSM400
+} RfTestCmdCalInfoV5AllBandCnfPdu_T;
+
+
+/* ----RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P_V5 ---- */
+typedef enum
+{
+ RX_CAL_SEQ_V5_NULL = RX_LNA_NONE ,
+ RX_CAL_SEQ_V5_UTRA_HIGH = RX_LNA_UTRA_HIGH ,
+ RX_CAL_SEQ_V5_HIGH = RX_LNA_HIGH ,
+ RX_CAL_SEQ_V5_MID = RX_LNA_MID ,
+ RX_CAL_SEQ_V5_MID_SAWLESS = RX_LNA_MID_SAWLESS,
+ RX_CAL_SEQ_V5_LOW = RX_LNA_LOW ,
+ RX_CAL_SEQ_V5_BYPASS_LOW = RX_LNA_BYPASS_LOW ,
+ RX_CAL_SEQ_V5_WCOEF
+} RfTestRxCalSeqV5_E; //the same as LNACalSeqV5_E //reference to RfTestRx_Lna_Mode_E
+
+typedef struct
+{
+ FrequencyBand band;
+ ARFCN arfcn;
+ kal_int16 repeat_cnt;
+ kal_int16 dl_power; //it is DL Power for each frame
+ RfTestRxCalSeqV5_E gsm_lna_mode[GSM_RF_MAX_RX_ANT_NUM];
+} RFTestCmdDSSPL_V5;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ RFTestCmdDSSPL_V5 PathLossDSS[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 lpm_sb_num;
+ kal_uint8 Antenna; //GSM_AntDimension
+} RFTestCmdDTS_Lpm_512P_V5;
+
+
+/* ----RF_TEST_CMD_PM_V5 & RF_TEST_CMD_IF_PM_V5---- */
+//REQ Param
+typedef struct
+{
+ RfTestSupportBand band;
+ ARFCN arfcn;
+ kal_int8 sampleNoPerFrame;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int16 frames;
+ GSM_AntDimension Antenna;
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+} RfTestCmdPm_V5;
+
+//CNF Param
+typedef struct
+{
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ kal_int32 power[GSM_RF_MAX_RX_ANT_NUM];
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS*2 bits*/
+ kal_int32 deviation[GSM_RF_MAX_RX_ANT_NUM];
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain usedGain[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 iOffset[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 qOffset[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 validSamples[GSM_RF_MAX_RX_ANT_NUM];
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 ok;
+} RfTestResultPm_V5;
+
+
+/* ----RF_TEST_CMD_CONTINUOUS_RX_V5---- */
+//REQ Param
+typedef struct
+{
+ RfTestSupportBand band;
+ ARFCN arfcn;
+ Gain gain[GSM_RF_MAX_RX_ANT_NUM];
+ GSM_AntDimension Antenna;
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+ kal_bool onOff;
+} RfTestCmdContRx_V5;
+//CNF Param
+//kal_bool ok;
+
+
+/* ----RF_TEST_CMD_RX_GAIN_CALCULATE_V5---- */
+//REQ Param
+typedef struct
+{
+ RfTestSupportBand band;
+ GSM_AntDimension Antenna;
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+} RfTestCmdRxGainCalculate_V5;
+
+//CNF Param
+typedef enum
+{
+ GSM_CALCULATE_NULL = 0,
+ GSM_CALCULATE_SUCCESS,
+ GSM_CALCULATE_FAIL
+} GSM_RxGain_Caculator;
+
+typedef struct
+{
+ kal_int16 recommend_dlpow;
+ kal_uint16 request_gain [GSM_RF_MAX_RX_ANT_NUM]; // 1/8 dB
+ GSM_RxGain_Caculator calculate_status;
+} RfTestResultRxGainCalculate_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+/* ---------------------------------------------------------------------------- */
+
+
+typedef struct
+{
+ FrequencyBand band;
+ ARFCN arfcn;
+ kal_int8 timeslot_per_frame;
+ kal_int8 apc_dac_pcl_sel; // 1: apc_dac, 0: apc_pcl
+ kal_int16 apc_dac_pcl_value[4];
+ //kal_uint8 pa_vbias_val;
+ kal_uint8 pa_vbias_val[4];
+ kal_uint8 is_low_pcl[4];
+
+ CodingScheme cs[4];
+ kal_int32 repeat_cnt;
+ kal_int16 afc_dac_value;
+ kal_int8 tsc;
+ APCTxPattern pattern;
+ kal_uint16 pattern_data;
+} RfTestCmdUSSApc;
+
+typedef struct
+{
+ //kal_bool pa_vbias_cal; // Control whether PA need to calibrate different Vbias value when APC DAC is used
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ kal_int16 high_apc_dcoffset[FrequencyBandCount];
+ // kal_int32 lowest_power[FrequencyBandCount];
+ RfTestCmdUSSApc ApcUSS[FT_MAX_STEP_CNT_50P];
+}RfTestCmdUTS_50P;
+
+typedef struct
+{
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ kal_int16 high_apc_dcoffset[FrequencyBandCount];
+ RfTestCmdUSSApc ApcUSS[FT_MAX_STEP_CNT_100P];
+}RfTestCmdUTS_100P;
+
+typedef struct
+{
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ kal_int16 high_apc_dcoffset[FrequencyBandCount];
+ RfTestCmdUSSApc ApcUSS[FT_MAX_STEP_CNT_512P];
+}RfTestCmdUTS_512P;
+
+typedef struct
+{
+ //kal_int32 rf_band;
+ kal_int16 afc_offset[FrequencyBandCount];
+
+}RF_SET_AFC_DAC_OFFSET_REQ_T;
+
+typedef struct
+{
+ signed char rollback_2t; /* Rollback (2t/F2I_Resolution) dB when 2 TX slots */
+ signed char rollback_3t; /* Rollback (3t/F2I_Resolution) dB when 3 TX slots */
+ signed char rollback_4t; /* Rollback (4t/F2I_Resolution) dB when 4 TX slots */
+ signed char rollback_5t; /* Rollback (5t/F2I_Resolution) dB when 5 TX slots */
+} FT_Rf_sTX_POWER_ROLLBACK;
+
+typedef struct
+{
+ kal_int32 band;
+ FT_Rf_sTX_POWER_ROLLBACK PowerRollbackTable;
+}RfTestCmdSetPowerRollbackTable;
+
+/**
+ * The RfTestCmdIrPm is used for IRR w coeffiecient calibration
+ * The command is analogous to RfTestCmdPm, except the m_IfFlag
+ */
+typedef struct
+{
+ /// power scan input parameter
+ RfTestCmdPm m_Pm;
+ /// if_flag for the power scan (to override the if setting in power scan, the original interface is not changed)
+ kal_int8 m_IfFlag;
+}RfTestCmdIrPm;
+
+#if IS_2G_RXD_SUPPORT
+typedef struct
+{
+ /// power scan input parameter
+ RfTestCmdPm_V5 m_Pm;
+ /// if_flag for the power scan (to override the if setting in power scan, the original interface is not changed)
+ kal_int8 m_IfFlag;
+}
+RfTestCmdIrPm_V5;
+#endif
+
+typedef struct
+{
+ FrequencyBand band;
+ Power pcl;
+}RfTestCmdTXPC;
+// ***************************************** //
+
+// R8 edge new feature
+typedef struct
+{
+ unsigned char rf_band;
+ unsigned short pa_gain[16];
+}RfTestCmdSetEdgeTxOctPACoef;
+
+typedef struct
+{
+ kal_uint8 rf_band;
+ kal_int8 cTxAdc_State;
+ kal_int8 is_EPSK;
+}RfTestCmdResetPdData;
+
+typedef struct{
+ ARFCN arfcn; // absolute radio frequency channel number
+ BSIC bsic; // training sequence
+ CodingScheme cs; // coding scheme for each time slot, MCS1~9 is only valid for EPSK function
+ TimingAdvance ta; // time advance
+ kal_int32 frames; // the number of frames should transmit
+ kal_int16 dacValue; // AFC DAC value
+ APCTxPattern pattern; // Tx pattern is only valid for EPSK function
+ kal_uint16 pattern_data; // if NB_TX_PATTERN_WITHOUT_TSC==pattern, user can input any 16bits value as pattern.
+ kal_uint16 pa_gain; // pa gain from ini file
+ kal_uint16 pa_vbias; // pa vbias from ini file
+ kal_uint8 rf_gain_index; // gain rf index
+}Rf_GainRfTx_Req;
+
+typedef struct
+{
+ kal_uint16 max_arfcn;
+ kal_int8 path_loss_H;
+ kal_int8 path_loss_M;
+ kal_int8 path_loss_M_sawless;
+ kal_int8 path_loss_L;
+}RfPathLossOffset;
+
+typedef struct
+{
+ RfPathLossOffset rx_pathloss[FrequencyBandCount][PLTABLE_SIZE];
+}RfTestCmdSetGetRxPathLoss;
+
+typedef struct
+{
+ kal_uint16 max_arfcn;
+ kal_int8 path_loss_H;
+ kal_int8 path_loss_M;
+ kal_int8 path_loss_M_sawless;
+ kal_int8 path_loss_L;
+ kal_int8 path_loss_H_sensitivity; //elna+g6
+ kal_int8 path_loss_L_maxpin; //elna_bypass+g1 ,sLNAGAINOFFSET
+}RfPathLossOffset_V3;
+
+typedef struct
+{
+ RfPathLossOffset_V3 rx_pathloss[FrequencyBandCount][PLTABLE_SIZE];
+}RfTestCmdSetGetRxPathLoss_V3;
+
+typedef struct
+{
+ RfTestCmdAfc afc;
+ FrequencyBand band;
+ RfTestCmdSetAfcSinWave setAfcSinWave;
+}RfTestCmdSinewaveAfcGetTempFreq;
+
+typedef struct
+{
+ //sRFSpecialCoef rfspecialcoef;
+ //RFSpecialCoef.rx.mt6256_51rf.w_data
+ w_coef w_data[WCTABLE_SIZE];
+}RfTestCmdSetGetWcoefPdu;
+
+
+
+
+/* -------------------- *\
+|* SET TX CMD REQ Struct *|
+ \* -------------------- */
+#define RF_MAX_PEER_BUF_CNF_BYTE_SIZE 51200 //50*1024
+#define RF_MAX_PEER_BUF_CNF_WORD_SIZE RF_MAX_PEER_BUF_CNF_BYTE_SIZE >> 2
+
+typedef enum
+{
+ GMSK_Band850 =1, //0x00 01
+ GMSK_Band900 =2, //0x00 02
+ GMSK_Band1800 =4, //0x00 04
+ GMSK_Band1900 =8, //0x00 08
+ EPSK_Band850 =256, //0x01 00
+ EPSK_Band900 =512, //0x02 00
+ EPSK_Band1800 =1024, //0x04 00
+ EPSK_Band1900 =2048, //0x08 00
+}RfTestTxData_ModBand_Bitmap_E;
+
+typedef struct
+{
+ kal_uint16 count;
+ kal_uint16 offset;
+ //kal_uint16 mod_band_bitmap; //modulation+band bitmap
+ //// EPSK(4bit) | GMSK(4bit) -> 0000 0101 | 0000 0011 -> PCS|DCS|900|850 ex.Set Data for GSM850/GSM900 GMSK + GSM850/DCS EPSK Ramping
+ //kal_uint16 mod_bitmap; //modulation bitmap
+ //// EPSK(1bit) | GMSK(1bit) -> 00000001 | 00000001 ex.Set Data for GMSK & EPSK Txpc
+ //kal_uint16 band_bitmap; //band bitmap
+ // EPSK(4bit) -> PCS|DCS|900|850-> 0000 1111 | 0000 0000 ex.Set Data for EPSK interslotramp GSM850/GSM900/DCS/PCS
+ //kal_uint16 not_used_bitmap; //0000 0000 | 0000 0001, only need one bit, data did not separate from diff band and mod type
+ kal_uint16 bitmap; //for general purpose //RfTestTxData_ModBand_Bitmap_E //RfTestRxData_ModBand_Bitmap_E
+ kal_uint16 zero_padding;
+}RfTestParamDynamicEntryElm_T;
+
+typedef struct
+{
+ kal_uint16 is_uplate_to_NVRAM;
+ RfTestParamDynamicEntryElm_T type1_ramptable_param;
+ RfTestParamDynamicEntryElm_T type2_epsk_interramptable_param;
+ RfTestParamDynamicEntryElm_T type3_txpc_param;
+ RfTestParamDynamicEntryElm_T type4_epskpa_param;
+}RfTestCmdSetTxDataReqParam;
+
+typedef l1cal_rampTable_T L1_Ramptable_Type1_T;
+
+#if MD_DRV_IS_EPSK_TX_SUPPORT
+typedef l1cal_EPSK_interRampData_T L1_EPSK_InterRamptable_Type2_T;
+#endif
+
+typedef struct
+{
+ char is_calibrated;
+ short temperature;
+}L1_Txpc_Type3_T; //l1cal_txpc_T
+
+typedef orionRFtx_pa_vbias L1_EpskPA_Type4_T; //l1cal_rfspecialcoef_T
+
+typedef struct
+{
+ union
+ {
+ kal_int32 set_txdata_req_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ #if MD_DRV_IS_EPSK_TX_SUPPORT
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ #endif
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+ } request;
+}RfTestCmdSetTxDataReqPdu;
+/* -------------------------------------- */
+
+
+
+/* -------------------- *\
+|* GET TX CMD REQ Struct *|
+ \* -------------------- */
+typedef struct
+{
+ kal_uint16 type1_ramptable_count;
+ kal_uint16 type2_epsk_interramptable_count;
+ kal_uint16 type3_txpc_count;
+ kal_uint16 type4_epskpa_count;
+
+ //point out which kind of this type should be got
+ kal_uint16 type1_ramptable_bitmap;
+ kal_uint16 type2_epsk_interramptable_bitmap;
+ kal_uint16 type3_txpc_bitmap;
+ kal_uint16 type4_epskpa_bitmap;
+}RfTestCmdGetTxDataReqParam;
+/* -------------------------------------- */
+
+
+#if IS_2G_RXD_SUPPORT
+/* -------------------- *\
+|* SET RX CMD REQ Struct *|
+ \* -------------------- */
+typedef enum
+{
+ GSM_RXM_Band850 =1, //0x00 01
+ GSM_RXM_Band900 =2, //0x00 02
+ GSM_RXM_Band1800 =4, //0x00 04
+ GSM_RXM_Band1900 =8, //0x00 08
+ GSM_RXD_Band850 =256, //0x01 00
+ GSM_RXD_Band900 =512, //0x02 00
+ GSM_RXD_Band1800 =1024, //0x04 00
+ GSM_RXD_Band1900 =2048, //0x08 00
+}RfTestRxData_ModBand_Bitmap_E;
+
+//typedef struct
+//{
+// kal_uint16 count;
+// kal_uint16 offset;
+// kal_uint16 bitmap; //for general purpose //RfTestTxData_ModBand_Bitmap_E, RfTestRxData_ModBand_Bitmap_E
+// kal_uint16 zero_padding;
+//}RfTestParamDynamicEntryElm_T;
+
+typedef struct
+{
+ kal_uint16 is_uplate_to_NVRAM;
+ RfTestParamDynamicEntryElm_T type1_rxpathloss_param;
+ RfTestParamDynamicEntryElm_T type2_wcoef_param;
+}RfTestCmdSetRxDataReqParam;
+
+typedef struct
+{
+ RfPathLossOffset_V3 rx_pathloss_entry[PLTABLE_SIZE];
+} L1_SetGetRxPathLossEntry_Type1_T;
+
+typedef l1cal_wcoef_T L1_Wcoef_Type2_T;
+
+typedef struct
+{
+ union
+ {
+ kal_int32 set_rxdata_req_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_SetGetRxPathLossEntry_Type1_T type1_pathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+ } request;
+}RfTestCmdSetRxDataReqPdu;
+/* -------------------------------------- */
+
+
+/* -------------------- *\
+|* GET RX CMD REQ Struct *|
+ \* -------------------- */
+typedef struct
+{
+ kal_uint16 type1_rxpathloss_count;
+ kal_uint16 type2_wcoef_count;
+
+ //point out which kind of this type should be got
+ kal_uint16 type1_rxpathloss_bitmap;
+ kal_uint16 type2_wcoef_bitmap;
+}RfTestCmdGetRxDataReqParam;
+/* -------------------------------------- */
+#endif //#if IS_2G_RXD_SUPPORT
+
+/*GET TPO CMD REQ struct*/
+typedef struct
+{
+ FrequencyBand band;
+ kal_bool is_epsk;
+}RfTestCmdGetTPO;
+
+/*SET TPO CMD REQ struct*/
+typedef struct
+{
+ FrequencyBand band;
+ kal_bool is_epsk;
+ kal_int16 power_apcdac_offset; // unit:DAC
+ kal_int16 power_dB_offset; // 0.125 dB
+}RfTestCmdSetTPO;
+
+typedef union
+{
+ RfTestCmdPm pm;
+ RfTestCmdAfc afc;
+ RfTestCmdNbTx nbTx;
+ RfTestCmdContRx contRx;
+ RfTestCmdContTx contTx;
+ RfTestCmdSetBBTXCfg setBBTXCfg;
+ kal_bool selectPCS1900;
+ kal_int8 dummy;
+ RfTestCmdMultiSlotTX msTx;
+ RfTestCmdSetRampApcLevel setRampApcLevel;
+ RfTestCmdSetAfcDacValue setAfcDacValue;
+ RfTestCmdSetBBTXCfg2 BBTxCfg2;
+ RfTestCmdSetCrystalCfg setCrystalCfg;
+ RfTestCmdSetRampTable setRampTable;
+ RfTestCmdSetAfcSinWave setAfcSinWave;
+ RfTestCmdSetBSI SetBSI;
+ RfTestCmdGetBSI GetBSI;
+ RfTestCmdSetBBTXCfg3 BBTxCfg3;
+ RfTestCmdMultiSlotTXEx msTxEx;
+ RfTestCmdContTxEx contTxEx;
+ RfTestCmdContTxEx2 contTxEx2;
+ RfTestCmdSetBBTXCfg4 BBTxCfg4;
+ RF_SET_AFC_DAC_OFFSET_REQ_T set_afc_offset_req;
+ RfTestCmdNSFTParam NSFT_start;
+ RfTestCmdNSFTPowerChangeParam NSFT_change_power;
+ RfTestCmdSetPowerRollbackTable PowerRollbackTable;
+ kal_uint32 m_u4NSFTSBERTestCount;
+ /// for L1TST_ReportRXQual input
+ kal_uint16 m_u2NSFTRxQualBerDecile;
+ /// for SOC2 IRR W PM
+ RfTestCmdIrPm m_IrPm;
+ RfTestCmdTXPC txpc_req;
+ /// for L1TST_TXPC_CL_GetSubband input
+ kal_uint8 band;
+ /* [LPM CAL] */
+ /// for DCXO FPM/LPM control (1 FPM, 0 LPM)
+ kal_uint8 dcxoMode;
+ /// R8 edge new feature
+ RfTestCmdSetEdgeTxOctPACoef setTxOctPaCoef;
+ RfTestCmdResetPdData resetTxPcPdData;
+ /// gain rf tx
+ Rf_GainRfTx_Req gainRfTx;
+ kal_uint8 path_flag;
+ RfTestCmdType query_op_code;
+ RfTestCmdListModeNSFTParam List_Mode_NSFT_start;
+ kal_bool is_uplate_to_NVRAM;
+ RfTestCmdSinewaveAfcGetTempFreq afc_gpscoclockv2;
+ RfTestCmdSetTxDataReqParam set_txdata_req;
+ RfTestCmdGetTxDataReqParam get_txdata_req;
+ #if IS_2G_RXD_SUPPORT
+ RfTestCmdPm_V5 pm_v5;
+ RfTestCmdIrPm_V5 m_IrPm_v5;
+ RfTestCmdContRx_V5 contRx_v5;
+ RfTestCmdNSFTParam_V5 NSFT_start_v5;
+ RfTestCmdListModeNSFTParam_V5 List_Mode_NSFT_start_v5;
+ RfTestCmdSetRxDataReqParam set_rxdata_req;
+ RfTestCmdGetRxDataReqParam get_rxdata_req;
+ RfTestCmdRxGainCalculate_V5 rx_gain_calculate_req;
+ #endif
+ kal_uint8 rxlev_precision;
+ RfTestCmdGetTPO getTPOVlaue;
+ RfTestCmdSetTPO setTPOVlaue;
+} RfTestCmdParam;
+
+
+
+
+/* ---------------------------------- */
+typedef struct
+{
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ kal_int32 power;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS*2 bits*/
+ kal_int32 deviation;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain usedGain;
+ kal_int32 ok;
+ kal_int32 iOffset;
+ kal_int32 qOffset;
+ kal_int32 validSamples;
+} RfTestResultPm;
+
+typedef struct
+{
+ kal_int16 fcb_ok_number;
+ kal_int32 freqOffset;
+ kal_int32 deviation;
+ kal_int32 ok;
+} RfTestResultAfc;
+
+typedef struct
+{
+ kal_int16 fcb_ok_number;
+ kal_int32 freqOffset;
+ kal_int32 deviation;
+ kal_int32 ok;
+ kal_int32 temperature;
+} RfTestResultSinewaveAfcGetTempFreq;
+
+typedef struct {
+ kal_bool ok;
+ RfTestCmdSetBBTXCfg2 bbtx_cfg;
+} RfTestResultGetBBTXCfg2;
+
+typedef struct {
+ kal_uint32 GSM400;
+ kal_uint32 GSM850;
+ kal_uint32 GSM900;
+ kal_uint32 DCS1800;
+ kal_uint32 PCS1900;
+} RfTestResultBandSupport;
+
+typedef struct {
+ kal_bool ok;
+ MS_CAPABILITY_E capability;
+ RfTestResultBandSupport band_support;
+} RfTestResultMsCapability;
+/*
+#define MS_CAPABILITY_GSM 0x00000001
+#define MS_CAPABILITY_GPRS 0x00000002
+#define MS_CAPABILITY_EDGE_RX 0x00000004
+#define MS_CAPABILITY_EDGE_8PSK_TX 0x00000008
+#define MS_CAPABILITY_8PM 0x00000010
+
+#define MS_BAND_SUPPORT_GSM400 0x00000001
+#define MS_BAND_SUPPORT_GSM850 0x00000002
+#define MS_BAND_SUPPORT_GSM900 0x00000004
+#define MS_BAND_SUPPORT_DCS1800 0x00000008
+#define MS_BAND_SUPPORT_PCS1900 0x00000010
+*/
+
+typedef struct
+{
+ kal_uint32 capability;
+ kal_uint32 band_support;
+}RfResultMsCapabilityEx;
+
+typedef struct {
+ kal_bool ok;
+ kal_uint32 capability;
+ kal_uint32 band_support;
+} RfTestResultMsCapabilityEx;
+
+typedef struct {
+ kal_bool ok;
+ kal_uint32 id;
+} RfTestResultGetRFID;
+
+typedef struct {
+ kal_bool ok;
+ kal_uint32 bsi_data;
+} RfTestResultGetBSI;
+
+typedef struct {
+ kal_bool ok;
+ RfTestCmdSetBBTXCfg3 bbtx_cfg;
+} RfTestResultGetBBTXCfg3;
+
+typedef struct
+{
+ kal_bool ok;
+ RfTestCmdSetBBTXCfg4 bbtx_cfg;
+}RfTestResultGetBBTXCfg4;
+
+typedef struct {
+ kal_bool ok;
+ kal_int16 dacValue;
+} RfGetAfcDacValueAtRTXOffsetCal;
+
+typedef struct
+{
+ kal_bool ok;
+ kal_int32 calibra_result_32k;
+}RfTestResult32kCalibration;
+
+// ****************************** //
+// FDT Calibration
+// ****************************** //
+typedef struct
+{
+ kal_int32 power[FT_MAX_STEP_CNT_50P-2];
+ kal_int16 valid_sample[FT_MAX_STEP_CNT_50P-2];
+ kal_bool ok;
+} RfTestResultDSSPL_50P;
+
+typedef struct
+{
+ kal_int32 power[FT_MAX_STEP_CNT_100P-2];
+ kal_int16 valid_sample[FT_MAX_STEP_CNT_100P-2];
+ kal_bool ok;
+} RfTestResultDSSPL_100P;
+
+typedef struct
+{
+ kal_int32 power[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 valid_sample[FT_MAX_STEP_CNT_512P-2];
+ kal_bool ok;
+ //kal_bool is_se_sawless; // remove this item, otherwise memory copy from ResultDSSPL will be not match
+} RfTestResultDSSPL_512P; /** For sawless lna mode and enlarge size=512 to reduce CMD round trip number*/
+
+typedef struct
+{
+ kal_int32 freq_offset[33]; // only valid when 33 stage calibration is ON
+ kal_int32 deviation[33]; // only valid when 33 stage calibration is ON
+ kal_int16 fcb_ok_number[33];
+ //kal_int8 capid; // only valid when capid calibration is ON
+ kal_int32 capid; // only valid when capid calibration is ON
+ kal_int16 init_dac_value; // only valid when 33 stage calibration is OFF
+ kal_int32 slope; // only valid when 33 stage calibration is OFF
+ kal_bool ok;
+} RfTestResultDSSAfc;
+/* [LPM CAL] */
+typedef struct
+{
+ kal_int32 cload_freq_offset;
+ kal_bool ok;
+ kal_bool is_perform_cal;
+} RfTestResultDSSLpm;
+
+#if IS_FHC_SUPPORT == 1
+typedef struct
+{
+ kal_int32 path_loss_cnt;
+ kal_int32 freq_offset;
+ kal_int32 capid_freq_offset_min;
+ kal_int32 capid_freq_offset[FHC_MAX_CAPID_SEARCH_NUM]; // 16
+ kal_int32 capid_search_order[FHC_MAX_CAPID_SEARCH_NUM]; // 16
+ kal_int32 capid;
+ kal_int32 capid_high;
+ kal_int32 capid_low;
+ kal_int32 capid_best;
+ kal_int16 afc_dac;
+ kal_int16 arfcn;
+ kal_int16 capid_cnt;
+ kal_int16 repeat_index;
+ kal_int8 state;
+ kal_int8 capid_index;
+ kal_int8 capid_okay_cnt;
+ kal_int8 afc_dac_index;
+ kal_int8 sb_okay_cnt;
+ kal_uint8 sb_fail_cnt;
+ kal_uint8 fb_fail_cnt;
+ kal_bool pl_started;
+ kal_bool pre_capid_cal_ok[FHC_PRE_CAPID_SEARCH_NUM]; // FHC_PRE_CAPID_SEARCH_NUM
+}RfTestResultDtsmInfo;
+#else
+typedef struct
+{
+ kal_int32 path_loss_cnt;
+ kal_int32 freq_offset;
+ kal_int32 capid_freq_offset_min;
+ kal_int32 capid_freq_offset[16]; //FHC_MAX_CAPID_SEARCH_NUM
+ kal_int32 capid_search_order[16]; //FHC_MAX_CAPID_SEARCH_NUM
+ kal_int32 capid;
+ kal_int32 capid_high;
+ kal_int32 capid_low;
+ kal_int32 capid_best;
+ kal_int16 afc_dac;
+ kal_int16 arfcn;
+ kal_int16 capid_cnt;
+ kal_int16 repeat_index;
+ kal_int8 state;
+ kal_int8 capid_index;
+ kal_int8 capid_okay_cnt;
+ kal_int8 afc_dac_index;
+ kal_int8 sb_okay_cnt;
+ kal_uint8 sb_fail_cnt;
+ kal_uint8 fb_fail_cnt;
+ kal_bool pl_started;
+ kal_bool pre_capid_cal_ok[9]; // FHC_PRE_CAPID_SEARCH_NUM
+}RfTestResultDtsmInfo;
+#endif
+
+typedef enum {
+ DTS_RESULT_READY = 0, // DTS results is ready to get back
+ DTS_RESULT_NOT_READY, // DTS result is still in progress and not ready to get back
+ DTS_RESULT_NOT_REQUESTED, // Haven't called the META_Rf_StartFdtDL() in advance.
+ DTS_FATAL_ERROR
+}RF_DTS_GET_RESULT_STATUS;
+typedef struct
+{
+ RfTestResultDSSPL_50P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo; // for L1 debug use, will print in META Tool's test report.
+} RfTestResultDTS_50P;
+
+typedef struct
+{
+ RfTestResultDSSPL_100P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo; // for L1 debug use, will print in META Tool's test report.
+} RfTestResultDTS_100P;
+
+
+/* [LPM CAL] */
+typedef struct
+{
+ RfTestResultDSSPL_50P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_50P;
+
+typedef struct
+{
+ RfTestResultDSSPL_100P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_100P;
+
+typedef struct
+{
+ RfTestResultDSSPL_512P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_512P; /** For sawless lna mode and reduce CMD round trip number*/
+
+typedef struct
+{
+ RfTestResultDSSPL_512P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_512P_V3; /** For sawless lna mode and reduce CMD round trip number*/
+
+/*------RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P_V5, RF_TEST_CMD_GET_FDT_RESULT_LPM_512P_V5------*/
+#if IS_2G_RXD_SUPPORT
+typedef struct
+{
+ kal_int32 power[GSM_RF_MAX_RX_ANT_NUM][FT_MAX_STEP_CNT_512P-2];
+ kal_int16 valid_sample[GSM_RF_MAX_RX_ANT_NUM][FT_MAX_STEP_CNT_512P-2];
+ kal_bool ok;
+} RfTestResultDSSPL_512P_V5; //ResultDSSPL
+
+typedef struct
+{
+ RfTestResultDSSPL_512P_V5 PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_512P_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+/*---------------------------------------------------------------*/
+
+typedef struct
+{
+ kal_int16 afc_offset[FrequencyBandCount];
+ kal_bool ok;
+}RfGetAfcOffsetResult;
+
+typedef struct
+{
+ kal_uint32 m_u4NSFTSBER;
+ kal_uint32 m_u4NSFTSBERCurrentCount;
+}RfNSFTSBERResult;
+// local
+typedef struct
+{
+ kal_bool ok;
+ kal_uint16 m_u2PDValue;
+}RfTestResultPDValue;
+
+// peer
+typedef struct
+{
+ kal_uint16 data[16];
+} RfTestResultTXPCPD;
+
+typedef struct
+{
+ kal_uint16 data[8];
+} RfTestResultTXPCPDTemp;
+
+typedef struct
+{
+ /// calibrated flag
+ kal_int8 is_calibrated;
+ /// closed-loop target value by PCL
+ RfTestResultTXPCPD adc[FrequencyBandCount];
+ /// temperature compensation interval
+ kal_int16 temperature;
+ /// closed-loop target value by temperature compensation
+ RfTestResultTXPCPDTemp temp[FrequencyBandCount];
+}RfTestResultTXPCAllPD;
+
+typedef struct
+{
+ kal_int16 status;
+ kal_int16 tadc_dac;
+ kal_int16 temperature;
+ kal_int16 temp_idx;
+} RfTestResultRfTemperatureInfo;
+
+// ****************************** //
+
+typedef struct
+{
+ kal_uint32 result; // 1: support 0: not support
+ kal_uint32 query_op_code; // query op code
+}RfCheckIfFuncExist;
+
+/** ----- 2G list mode nsft -----*/
+typedef struct
+{
+ kal_uint8 report_count;
+}RfTestResultListModeNSFT;
+
+typedef struct
+{
+ kal_uint16 status; //NsftListCmdStatus //NsftListRpt_Com_t
+}RfTestResultListModeNSFTCommon;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+ kal_uint16 retry_count;
+ kal_int16 new_afc_dac;
+ kal_int32 detected_foe;
+}RfTestResultListModeNSFTSync;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+}RfTestResultListModeNSFTTrigger;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+ kal_uint16 RX_level;
+ kal_uint32 BER_sum;
+ kal_uint32 BER_frame_count;
+}RfTestResultListModeNSFTMeasure;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+}RfTestResultListModeNSFTStop;
+
+typedef union
+{
+ RfTestResultListModeNSFTSync sync;
+ RfTestResultListModeNSFTTrigger trigger;
+ RfTestResultListModeNSFTMeasure test;
+ RfTestResultListModeNSFTStop stop;
+}RfTestResultListModeNSFTReport;
+
+typedef struct
+{
+ unsigned char cmd_type[60];
+ RfTestResultListModeNSFTReport report[60];
+}RfTestResultListModeNSFTParam;
+// --------------------------------- //
+
+
+/** ----- 2G list mode nsft V5 -----*/
+#if IS_2G_RXD_SUPPORT
+//CNF Local Param
+typedef RfTestResultListModeNSFT RfTestResultListModeNSFT_V5;
+
+//CNF Pdu
+typedef RfTestResultListModeNSFTSync RfTestResultListModeNSFTSync_V5;
+typedef RfTestResultListModeNSFTTrigger RfTestResultListModeNSFTTrigger_V5;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+ kal_uint16 RX_level[GSM_RF_MAX_RX_ANT_NUM];
+ kal_uint32 BER_sum;
+ kal_uint32 BER_frame_count;
+}RfTestResultListModeNSFTMeasure_V5;
+
+typedef RfTestResultListModeNSFTStop RfTestResultListModeNSFTStop_V5;
+
+typedef union
+{
+ RfTestResultListModeNSFTSync_V5 sync;
+ RfTestResultListModeNSFTTrigger_V5 trigger;
+ RfTestResultListModeNSFTMeasure_V5 test;
+ RfTestResultListModeNSFTStop_V5 stop;
+}RfTestResultListModeNSFTReport_V5;
+
+typedef struct
+{
+ unsigned char cmd_type[60];
+ RfTestResultListModeNSFTReport_V5 report[60];
+}RfTestResultListModeNSFTParam_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+// --------------------------------- //
+
+typedef enum
+{
+ RF_CNF_SUCCESS = 0, /**< access NVRAM successfully? */
+ RF_CNF_RECORD_STATUS_FAIL = 1, /**< access NVRAM general error? */
+ RF_CNF_NVRAM_GET_FAIL = 2, /**< GET NVRAM, NVRAM return failed */
+ RF_CNF_FREQ_INVALID = 3, /**< Error arfcn parameter for band*/
+ RF_CNF_CMD_INVALID = 4, /**< Error, SET CMD peer buffer is NULL*/
+ RF_CNF_NVRAM_SET_FAIL = 5, /**< SET NVRAM, NVRAM return failed */
+ RF_CNF_ALLOC_BUFFER_FAIL = 6 /**< Allocate peer buffer FAIL */
+}RF_NVRAM_ACCESS_CAl_DATA_RESULT;
+
+
+/* -------------------- *\
+|* SET TX CMD CNF Struct *|
+ \* -------------------- */
+typedef enum
+{
+ RF_TEST_SET_TX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_SET_TX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_SET_TX_DATA_TYPE2_OFFSET_ERROR = 2, // Type-2 count/offset mismatch
+ RF_TEST_SET_TX_DATA_TYPE3_OFFSET_ERROR = 3, // Type-3 count/offset mismatch
+ RF_TEST_SET_TX_DATA_TYPE4_OFFSET_ERROR = 4, // Type-4 count/offset mismatch
+ RF_TEST_SET_TX_DATA_EXCESS_REQ_PDU_LENGTH = 5,
+ RF_TEST_SET_TX_DATA_CNF_CHECK_OFFSET_PASS = 6,
+ RF_TEST_SET_TX_DATA_BITMAP_COUNT_MISMATCH = 7,
+ RF_TEST_SET_TX_DATA_NULL_PEER_BUF = 8,
+ RF_TEST_SET_TX_DATA_RECORD_SET_FAIL = 9,
+ RF_TEST_SET_TX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestSetTxData_Cnf_Status_E;
+
+typedef enum
+{
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_MAX,
+}RfTestSetTxData_RunTime_Status_E;
+
+typedef struct
+{
+ kal_uint16 count;
+ kal_uint16 bitmap; //add bitmap for tool team debug
+}RfTestSetTxDataCnfParamEntry_T; // Similar with RfTestParamDynamicEntryElm_T
+
+typedef struct
+{
+ RfTestSetTxData_Cnf_Status_E set_txdata_cnf_status;
+ RfTestSetTxDataCnfParamEntry_T type1_result;
+ RfTestSetTxDataCnfParamEntry_T type2_result;
+ RfTestSetTxDataCnfParamEntry_T type3_result;
+ RfTestSetTxDataCnfParamEntry_T type4_result;
+ RfTestSetTxData_RunTime_Status_E type1_ramptable_result[8];
+ RfTestSetTxData_RunTime_Status_E type2_epsk_interramptable_result[4];
+ RfTestSetTxData_RunTime_Status_E type3_txpc_result[2];
+ RfTestSetTxData_RunTime_Status_E type4_epskpa_result; //RFSpecialCoef.tx.orionRFtx.data...
+}RfTestCmdSetTxDataCnfParam;
+/* -------------------------------------- */
+
+
+/* -------------------- *\
+|* GET TX CMD CNF Struct *|
+ \* -------------------- */
+typedef enum
+{
+ RF_TEST_GET_TX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_GET_TX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_GET_TX_DATA_BITMAP_COUNT_MISMATCH = 2,
+ RF_TEST_GET_TX_DATA_OFFSET_MISMATCH = 3,
+ RF_TEST_GET_TX_DATA_NULL_PEER_BUF = 4,
+ RF_TEST_GET_TX_DATA_PEER_BUF_SIZE_OVERFLOW = 5,
+ RF_TEST_GET_TX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestGetTxData_Cnf_Status_E;
+
+//typedef struct
+//{
+// kal_uint16 count;
+// kal_uint16 offset;
+//}RfTestGetParamDynamicEntryElm_T;
+
+typedef enum
+{
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_MAX,
+}RfTestGetTxData_RunTime_Status_E;
+
+typedef struct
+{
+ RfTestGetTxData_Cnf_Status_E get_txdata_cnf_status;
+ RfTestParamDynamicEntryElm_T type1_ramptable_data;
+ RfTestParamDynamicEntryElm_T type2_epsk_interramptable_data;
+ RfTestParamDynamicEntryElm_T type3_txpc_data;
+ RfTestParamDynamicEntryElm_T type4_epskpa_data;
+ RfTestGetTxData_RunTime_Status_E type1_ramptable_result[8];
+ RfTestGetTxData_RunTime_Status_E type2_epsk_interramptable_result[4];
+ RfTestGetTxData_RunTime_Status_E type3_txpc_result[2];
+ RfTestGetTxData_RunTime_Status_E type4_epskpa_result; //RFSpecialCoef.tx.orionRFtx.data...
+}RfTestCmdGetTxDataCnfParam;
+
+typedef struct
+{
+ union
+ {
+ kal_int32 get_txdata_cnf_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ #if MD_DRV_IS_EPSK_TX_SUPPORT
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ #endif
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+ } confirm;
+}RfTestCmdGetTxDataCnfPdu;
+/* -------------------------------------- */
+
+
+
+/* -------------------- *\
+|* SET RX CMD CNF Struct *|
+ \* -------------------- */
+#if IS_2G_RXD_SUPPORT
+typedef enum
+{
+ RF_TEST_SET_RX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_SET_RX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_SET_RX_DATA_TYPE2_OFFSET_ERROR = 2, // Type-2 count/offset mismatch
+ RF_TEST_SET_RX_DATA_TYPE3_OFFSET_ERROR = 3, // Type-3 count/offset mismatch
+ RF_TEST_SET_RX_DATA_TYPE4_OFFSET_ERROR = 4, // Type-4 count/offset mismatch
+ RF_TEST_SET_RX_DATA_EXCESS_REQ_PDU_LENGTH = 5,
+ RF_TEST_SET_RX_DATA_CNF_CHECK_OFFSET_PASS = 6,
+ RF_TEST_SET_RX_DATA_BITMAP_COUNT_MISMATCH = 7,
+ RF_TEST_SET_RX_DATA_NULL_PEER_BUF = 8,
+ RF_TEST_SET_RX_DATA_RECORD_SET_FAIL = 9,
+ RF_TEST_SET_RX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestSetRxData_Cnf_Status_E;
+
+typedef enum
+{
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_MAX,
+}RfTestSetRxData_RunTime_Status_E;
+
+typedef struct
+{
+ kal_uint16 count;
+ kal_uint16 bitmap; //add bitmap for tool team debug
+}RfTestSetRxDataCnfParamEntry_T; // Similar with RfTestParamDynamicEntryElm_T
+
+typedef struct
+{
+ RfTestSetRxData_Cnf_Status_E set_rxdata_cnf_status;
+ RfTestSetRxDataCnfParamEntry_T type1_result;
+ RfTestSetRxDataCnfParamEntry_T type2_result;
+ RfTestSetRxData_RunTime_Status_E type1_rxpathloss_result[8];
+ RfTestSetRxData_RunTime_Status_E type2_wcoef_result[2];
+}RfTestCmdSetRxDataCnfParam;
+/* -------------------------------------- */
+
+
+/* -------------------- *\
+|* GET RX CMD CNF Struct *|
+ \* -------------------- */
+typedef enum
+{
+ RF_TEST_GET_RX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_GET_RX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_GET_RX_DATA_BITMAP_COUNT_MISMATCH = 2,
+ RF_TEST_GET_RX_DATA_OFFSET_MISMATCH = 3,
+ RF_TEST_GET_RX_DATA_NULL_PEER_BUF = 4,
+ RF_TEST_GET_RX_DATA_PEER_BUF_SIZE_OVERFLOW = 5,
+ RF_TEST_GET_RX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestGetRxData_Cnf_Status_E;
+
+//typedef struct
+//{
+// kal_uint16 count;
+// kal_uint16 offset;
+//}RfTestGetParamDynamicEntryElm_T;
+
+typedef enum
+{
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_MAX,
+}RfTestGetRxData_RunTime_Status_E;
+
+typedef struct
+{
+ RfTestGetRxData_Cnf_Status_E get_rxdata_cnf_status;
+ RfTestParamDynamicEntryElm_T type1_rxpathloss_data;
+ RfTestParamDynamicEntryElm_T type2_wcoef_data;
+ RfTestGetRxData_RunTime_Status_E type1_rxpathloss_result[8];
+ RfTestGetRxData_RunTime_Status_E type2_wcoef_result[2];
+}RfTestCmdGetRxDataCnfParam;
+
+typedef struct
+{
+ union
+ {
+ kal_int32 get_rxdata_req_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_SetGetRxPathLossEntry_Type1_T type1_pathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+ } confirm;
+}RfTestCmdGetRxDataCnfPdu;
+#endif //#if IS_2G_RXD_SUPPORT
+/* -------------------------------------- */
+
+/*GET TPO CMD CNF struct*/
+typedef struct
+{
+ kal_bool ok;
+ kal_int16 power_apcdac_offset; // unit:DAC
+ kal_int16 power_dB_offset; // 0.125 dB
+} RfTestResultGetTPO;
+
+typedef union
+{
+ kal_bool ok;
+ kal_int8 m_i1RfPwrState_FT;
+ kal_int16 m_sBBPowerArrary[20]; /// META_Rf_QueryBBPowerList_r output
+ kal_uint8 nvramAccessResult; //RF_NVRAM_ACCESS_CAl_DATA_RESULT
+ kal_uint8 m_u1NSFTRxQual; /// L1TST_ReportRXQual output
+ kal_uint8 m_ucNumOfGainRf; /// META_Rf_QueryNumOfGainRf_r output
+ kal_uint16 m_u2NSFTRxLevel; /// L1TST_ReportRXLEV output
+ kal_uint16 temperature; /// L1TST_TXPC_GetTemperature output: RF_TEST_CMD_GET_TXPC_TEMPERATURE
+ kal_uint16 m_txpc_subband_compensation[11]; /// L1TST_TXPC_CL_GetSubband output
+ RF_DTS_GET_RESULT_STATUS dts_get_result_status;
+ RfGetAfcOffsetResult afc_result;
+ RfGetAfcDacValueAtRTXOffsetCal GetAfcDacValueAtRTXOffsetCal;
+ RfNSFTSBERResult m_rNSFTSBER;
+ RfTestResultPm pm;
+ RfTestResultAfc afc;
+ RfTestResultSinewaveAfcGetTempFreq afc_gpscoclockv2_result;
+ RfTestResultGetBSI GetBSI;
+ RfTestResultGetRFID rfid;
+ RfTestResultPDValue txpc_cnf;
+ RfTestResultGetBBTXCfg2 BBTxCfg2;
+ RfTestResultGetBBTXCfg3 BBTxCfg3;
+ RfTestResultGetBBTXCfg4 BBTxCfg4;
+ RfTestResultListModeNSFT List_Mode_NSFT_result;
+ RfTestResultMsCapability ms_capability;
+ RfTestResultMsCapabilityEx ms_capability_ex;
+ RfTestResult32kCalibration calibration_32k;
+ RfTestResultRfTemperatureInfo rfTemperatureInfo;
+ RfCheckIfFuncExist CheckIfFuncExist;
+ RfTestCmdSetTxDataCnfParam set_txdata_cnf;
+ RfTestCmdGetTxDataCnfParam get_txdata_cnf;
+ #if IS_2G_RXD_SUPPORT
+ kal_uint16 m_u2NSFTRxLevel_v5[GSM_RF_MAX_RX_ANT_NUM]; /// L1TST_ReportRXLEV output
+ RfTestResultPm_V5 pm_v5;
+ RfTestCmdSetRxDataCnfParam set_rxdata_cnf;
+ RfTestCmdGetRxDataCnfParam get_rxdata_cnf;
+ RfTestResultRxGainCalculate_V5 rx_gain_calculate_cnf;
+ #endif
+ RfTestResultGetTPO tpo_result;
+} RfTestResultParam;
+
+/*******************************************************************************
+*
+* Message structures defined for L1TST Interface
+*
+*******************************************************************************/
+typedef struct
+{
+ FT_HDR
+ RfTestCmdType type;
+ RfTestCmdParam param;
+} ft_rf_test_req_T;
+
+typedef struct
+{
+ FT_HDR
+ RfTestCmdType type;
+ RfTestResultParam param;
+} ft_rf_test_cnf_T;
+
+typedef ft_rf_test_req_T ft_to_gl1tst_struct;
+typedef ft_rf_test_cnf_T gl1tst_to_ft_struct;
+
+typedef ft_rf_test_req_T ft_rf_test_req_id_struct;
+typedef ft_rf_test_cnf_T ft_rf_test_cnf_id_struct;
+
+#endif /* _L1TST_FT_MSG_STRUCT_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct_gen97.h b/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct_gen97.h
new file mode 100644
index 0000000..d0162c4
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_ft_msg_struct_gen97.h
@@ -0,0 +1,2063 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_ft_msg_struct.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Struct definition of L1TST - FT interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ * 05 21 2021 yungshian.lai
+ * [MOLY00665438] [Colgin][MT2735][New feature][MD] Wide temperature- NR15.R3.MD700.MP(SWRD) - interface/l1[EWSP0000255811].
+ *
+ * 02 01 2021 yungshian.lai
+ * [MOLY00624719] [Gen97][CO-TMS]Support wide temperature range & 2G wide temperature TX compensation- NR15.R3.MD700.MP.MT2735.DEV(SWRD).
+ *
+ * 10 09 2018 yungshian.lai
+ * [MOLY00349865] TX POWER OFFSET feature uniform - VMOLY Trunk [ERS00016793].
+ *
+ * 09 18 2018 yungshian.lai
+ * [MOLY00349883] [MT6295][2G] NSFT RxLevel Resolution Enhancement- TST part - VMOLY Trunk.
+ *
+ * 03 30 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE option rename & NSFT swap patch.
+ *
+ * 03 02 2018 yungshian.lai
+ * [MOLY00310374] [MT6293][MT6295] GSM RXD Development - UMOLYE Trunk TST part.
+ *
+ * 09 08 2017 yungshian.lai
+ * [MOLY00275140] [Bianco] 93 2G Cal Time Reduction Development - UMOLYA - CNF bitmap.
+ *
+ * 09 01 2017 yungshian.lai
+ * [MOLY00275140] [Bianco] 93 2G Cal Time Reduction Development - UMOLYA.
+ *
+ * 07 21 2017 yungshian.lai
+ * [MOLY00266063] [EL1TST] GPS coclock v2.0 Development - 4G Read AuxADC /2G add capability and modify DHL PSTrace - UMOLYA.
+ *
+ * 01 11 2017 yungshian.lai
+ * [MOLY00223923] [Bianco Bring-up][GSM] MT6293 eLNA Development & GPScoclock V2.0.
+ *
+ * 05 03 2016 yungshian.lai
+ * [MOLY00163211] [L1TST] Sawless Development & DTS_STEP_CNT=512
+ * - modify LID VER & Struct naming & uint16 &SetRxNVRAM.
+ *
+ * 01 29 2016 yungshian.lai
+ * [MOLY00163211] [L1TST] Sawless Development & DTS_STEP_CNT=512.
+ *
+ * 06 12 2015 yungshian.lai
+ * [MOLY00121036] [TK6291][L1TST] NSFT list mode send pdu modify
+ * .
+ *
+ * 04 24 2015 yungshian.lai
+ * [MOLY00109190] [TK6291][L1TST] Add lack CMD,trace and modify TADC bitmap.
+ *
+ * 01 03 2014 th.yeh
+ * [MOLY00052308] [L1D][Modify] FT/L1D dual-core modem interface development
+ * .
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_FT_MSG_STRUCT_H_
+#define _L1TST_FT_MSG_STRUCT_H_
+#include "l1_types_public.h"
+//#if IS_2G_RXD_SUPPORT
+#include "ft_msg_common.h" //For L1D read RXD Info struct
+//#endif
+
+/*************************************************************************
+* Include Statements for PLTABLE_SIZE
+ *************************************************************************/
+#include "l1cal.h"
+
+
+/*******************************************************************************
+*
+* Data structures used in Message Definition
+*
+*******************************************************************************/
+
+typedef enum
+{
+ FT_RF_PWR_STATE_UNKNOWN = -1,
+ FT_RF_PWR_STATE_ON,
+ FT_RF_PWR_STATE_OFF,
+}ft_rf_power_state_enum;
+
+typedef enum
+{
+ RF_TEST_CMD_PM = 0
+ ,RF_TEST_CMD_AFC = 1
+ ,RF_TEST_CMD_NB_TX = 2
+ ,RF_TEST_CMD_CONTINUOUS_RX = 3
+ ,RF_TEST_CMD_CONTINUOUS_TX = 4
+ ,RF_TEST_CMD_SET_BB_TX_CFG = 5 //phase out
+ ,RF_TEST_CMD_BAND_SEL = 6
+ ,RF_TEST_CMD_STOP = 7
+ ,RF_TEST_CMD_MULTISLOT_TX = 8
+ ,RF_TEST_CMD_SET_RAMPAPCLVL = 9
+ ,RF_TEST_CMD_SET_AFCDACVALUE = 10 //phase out
+ ,RF_TEST_CMD_SET_BBTXCFG2 = 11 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG2 = 12 //phase out
+ ,RF_TEST_CMD_SET_CRYSTAL_CFG = 13
+ ,RF_TEST_CMD_BBTX_AUTOCAL = 14 //phase out
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY = 15
+ ,RF_TEST_CMD_SET_RAMPTABLE = 16
+ ,RF_TEST_CMD_SET_AFC_SINWAVE_DETECTION = 17
+ ,RF_TEST_CMD_MULTISLOT_TX_EX = 18
+ ,RF_TEST_CMD_EPSK_SET_RAMPAPCLVL = 19
+ ,RF_TEST_CMD_GET_RFID = 20
+ ,RF_TEST_CMD_SET_IMMEDIATE_BSI = 21
+ ,RF_TEST_CMD_GET_IMMEDIATE_BSI = 22
+ ,RF_TEST_CMD_SET_SPECIALCOEF = 23 //phase out
+ ,RF_TEST_CMD_CONTINUOUS_TX_EX = 24
+ ,RF_TEST_CMD_SET_BBTXCFG3 = 25 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG3 = 26 //phase out
+ ,RF_TEST_CMD_IF_TWO_APC_DC_OFFSET_SUPPORT = 27
+ ,RF_TEST_CMD_CONTINUOUS_TX_EX2 = 28
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY_EX = 29
+ ,RF_TEST_CMD_GET_AFCDACVALUE_AT_RTX_OFFSET_CAL = 30
+ ,RF_TEST_CMD_SET_BBTXCFG4 = 31 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG4 = 32 //phase out
+ ,RF_TEST_CMD_SET_BBTXCFG5 = 33 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG5 = 34 //phase out
+ ,RF_TEST_CMD_CALIBRATE_32K = 35
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY_EX2 = 36
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_50P = 37 // including AFC and RX pathloss: downlink //RF_TEST_CMD_START_FDT_DL
+ ,RF_TEST_CMD_START_FDT_UL_50P = 38 // APC calibration :uplink //RF_TEST_CMD_START_FDT_UL
+ ,RF_TEST_CMD_EPSK_SET_RAMPTABLE = 39 //phase out
+ ,RF_TEST_CMD_GET_AFC_DAC_OFFSET = 40 //phase out
+ ,RF_TEST_CMD_SET_AFC_DAC_OFFSET = 41 //phase out
+ ,RF_TEST_CMD_SET_BBTXCFG6 = 42 //phase out
+ ,RF_TEST_CMD_GET_BBTXCFG6 = 43 //phase out
+ ,RF_TEST_CMD_GET_FDT_RESULT_50P = 44 //RF_TEST_CMD_GET_FDT_RESULT
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_50P = 45
+ ,RF_TEST_CMD_NSFT_CHANGE_SETTING = 46
+ ,RF_TEST_CMD_NSFT_START = 47
+ ,RF_TEST_CMD_NSFT_STOP = 48
+ ,RF_TEST_CMD_NSFT_CHANGE_POWER = 49 //phase out?
+ ,RF_TEST_CMD_NSFT_START_EPSK_TX = 50
+ ,RF_TEST_CMD_OE_PATTERN_READY = 51
+ ,RF_TEST_CMD_POWER_ON = 52
+ ,RF_TEST_CMD_POWER_OFF = 53
+ ,RF_TEST_CMD_QUERY_POWER_STATE_IN_FT = 54 //phase out?
+ ,RF_TEST_CMD_AFC_TYPE_QUERY_READY = 55
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_GMSK = 56
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_EPSK = 57
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_TABLE_GMSK = 58 //phase out
+ ,RF_TEST_CMD_SET_TX_POWER_ROLLBACK_TABLE_EPSK = 59 //phase out
+ ,RF_TEST_CMD_GET_SPECIALCOEF = 60
+ ,RF_TEST_CMD_NSFT_CONFIG_SBER = 61
+ ,RF_TEST_CMD_NSFT_GET_SBER = 62
+ ,RF_TEST_CMD_NSFT_START_RXLEV = 63
+ ,RF_TEST_CMD_NSFT_GET_RXLEV = 64
+ ,RF_TEST_CMD_NSFT_GET_RXQUAL = 65
+ ,RF_TEST_CMD_IF_PM = 66
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_BY_PCL_GMSK = 67 //phase out
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_BY_PCL_EPSK = 68 //phase out
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_GMSK = 69 //phase out
+ ,RF_TEST_CMD_GET_TXPC_PD_VALUE_EPSK = 70 //phase out
+ ,RF_TEST_CMD_GET_TXPC_SUBBAND_GMSK = 71 //phase out
+ ,RF_TEST_CMD_GET_TXPC_SUBBAND_EPSK = 72 //phase out
+ ,RF_TEST_CMD_GET_TXPC_TEMPERATURE = 73
+ ,RF_TEST_CMD_QUERY_MS_CAPABILITY_EX3 = 74
+ /* [LPM CAL] */
+ ,RF_TEST_CMD_SET_DCXO_POWER_MODE = 75 //32k Less
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_50P = 76 //32k Less, Check func is False, open if need //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_EX
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_50P = 77 //32k Less, Check func is False, open if need //RF_TEST_CMD_GET_FDT_RESULT_EX
+ ,RF_TEST_CMD_SET_EDGE_TX_OCT_PA_SPECIAL_COEF = 78
+ ,RF_TEST_CMD_TXPC_CL_RESET_PD_DATA = 79 /**< \brief reset TX power control close loop pd value */
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_100P = 80 //RF_TEST_CMD_START_FDT_DL_BIG
+ ,RF_TEST_CMD_START_FDT_UL_100P = 81 //RF_TEST_CMD_START_FDT_UL_BIG
+ ,RF_TEST_CMD_GET_FDT_RESULT_100P = 82 //RF_TEST_CMD_GET_FDT_RESULT_BIG
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_100P = 83 //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_BIG
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_100P = 84 //32k Less, //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_EX_BIG
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_100P = 85 //32k Less, Check func is False, open if need //RF_TEST_CMD_GET_FDT_RESULT_EX_BIG
+ ,RF_TEST_CMD_MULTISLOT_TX_WITH_AUXADC_READ = 86 /**< \brief TX RF on and read AuxADC at same time for CoTsx */
+ ,RF_TEST_CMD_GAIN_RF_TX = 87 //Marked, open if need /**< \brief EDGE TX gain rf cal */
+ ,RF_TEST_CMD_QUERY_GAIN_RF_NUM = 88 //Marked, open if need /**< \brief Query gain rf target support number (max: 20)*/
+ ,RF_TEST_CMD_GET_BB_POWER_LIST = 89 //Marked, open if need /**< \brief Get BB power list from target */
+ ,RF_TEST_CMD_CHECK_IF_FUNC_EXIST = 90 /**< \brief Reserved. META DLL not send directly */
+ ,RF_TEST_CMD_GET_TEMPERATURE_INFO = 91
+ ,RF_TEST_CMD_SET_DT_PATH_FLAG = 92 /**< \brief Set L1 flag to use second path */
+ ,RF_TEST_CMD_LIST_MODE_NSFT_START = 93 /**< \brief 2G list mode nsft*/
+ ,RF_TEST_CMD_START_FDT_UL_512P = 94 /** reduce UL CMD round trip number*/ //RF_TEST_CMD_START_FDT_UL_BIG_V2
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P = 95 /** For sawless lna mode and reduce DL CMD round trip number*/
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P = 96 /** For sawless lna mode and reduce DL CMD round trip number*/ //RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_EX_BIG_V2
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_512P = 97 /** For sawless lna mode and reduce DL CMD round trip number*/
+ ,RF_TEST_CMD_SAWLESS_PM = 98 /** Force LTF on - for sawless lna mode in trad calibration*/
+ ,RF_TEST_CMD_SET_RX_PATH_LOSS = 99 /** FT Set data to runtime var, use flag to decide whether to update NVRAM or not*/
+ ,RF_TEST_CMD_GET_RX_PATH_LOSS = 100 /** FT Get data from runtime var (because runtime var==NVRAM)*/
+ ,RF_TEST_CMD_SET_RX_PATH_LOSS_V3 = 101 //For 93 SET_RX_PATH_LOSS elna+g6, elna bypass+g1 /** FT Set data to runtime var, use flag to decide whether to update NVRAM or not*/
+ ,RF_TEST_CMD_GET_RX_PATH_LOSS_V3 = 102 //For 93 GET_RX_PATH_LOSS elna+g6, elna bypass+g1 /** FT Get data from runtime var (because runtime var==NVRAM)*/
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P_V3 = 103 //Add New CMD, For 6293 compatible with 92 tool procedure - RFTestCmdDTS_Lpm_512P_V3
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P_V3 = 104 //Add New CMD, For 6293 compatible with 92 tool procedure (previous CMD)
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_512P_V3 = 105 //Add New CMD, For 6293 compatible with 92 tool procedure (previous CMD)
+ ,RF_TEST_CMD_SINEWAVE_AFC_GET_TEMP_FREQ = 106 /*For GPS co-clock V2.0, use this CMD to get temperature and freq offset*/
+ ,RF_TEST_CMD_SET_WCOEF = 107 //Cal time reduction development - Wcoef part
+ ,RF_TEST_CMD_GET_WCOEF = 108 //Cal time reduction development - Wcoef part
+ ,RF_TEST_CMD_SET_TXDATA = 109 //Cal time reduction development - Tx part
+ ,RF_TEST_CMD_GET_TXDATA = 110 //Cal time reduction development - Tx part
+ ,RF_TEST_CMD_GET_TPO_VALUE = 111 // For NSFT Adjust TPO support - Phase Out
+ ,RF_TEST_CMD_SET_TPO_VALUE = 112 // For NSFT Adjust TPO support - Phase Out
+ ,RF_TEST_CMD_GET_RXD_INFO_V5 = 113 //Gen95: Get Rx DL Power or ELNA Type info
+ ,RF_TEST_CMD_SET_RXDATA_V5 = 114 //RF_TEST_CMD_SET_RX_PATH_LOSS_V5
+ ,RF_TEST_CMD_GET_RXDATA_V5 = 115 //RF_TEST_CMD_SET_RX_PATH_LOSS_V5
+ ,RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P_V5 = 116 //Gen95: RFTestCmdDTS_Lpm_512P_V5
+ ,RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P_V5 = 117 //Gen95: RFTestCmdDTS_Lpm_512P_V5
+ ,RF_TEST_CMD_GET_FDT_RESULT_LPM_512P_V5 = 118
+ ,RF_TEST_CMD_PM_V5 = 119 // Gen95: Trad Cal
+ ,RF_TEST_CMD_IF_PM_V5 = 120 // Gen95: RF Tool & Trad Cal
+ ,RF_TEST_CMD_CONTINUOUS_RX_V5 = 121 // Gen95: RF Tool & Trad Cal
+ ,RF_TEST_CMD_NSFT_START_V5 = 122 // Gen95
+ ,RF_TEST_CMD_NSFT_GET_RXLEV_V5 =123 // Gen95
+ ,RF_TEST_CMD_NSFT_CHANGE_SETTING_V5 = 124 // Gen95
+ ,RF_TEST_CMD_LIST_MODE_NSFT_START_V5 = 125 // Gen95
+ ,RF_TEST_CMD_RX_GAIN_CALCULATE_V5 = 126 // Gen95
+ ,RF_TEST_CMD_SET_NSFT_RXLEV_PRECISION = 127 // Gen95
+ ,RF_TEST_CMD_GET_TPO_VALUE_V5 = 128 // For NSFT Adjust TPO support - Gen95
+ ,RF_TEST_CMD_SET_TPO_VALUE_V5 = 129 // For NSFT Adjust TPO support - Gen95
+ ,RF_TEST_CMD_SET_TXDATA_WIDE_TEMP = 130 //For IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT
+ ,RF_TEST_CMD_GET_TXDATA_WIDE_TEMP = 131 //For IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT
+
+ //Remember to add req/result param to FT_GL1TST_UnionTag.txt & add CMD to CheckFunction
+ /*----------------------------------------------------------------------------------------------------*/
+ ,RF_TEST_CMD_GP_TOOL_COMMAND_START
+ ,RF_TEST_CMD_END
+ ,RF_TEST_CMD_MAX = 0x7FFFFFFF
+} RfTestCmdType;
+
+typedef enum {
+ MS_GSM = 0
+ ,MS_GPRS
+ ,MS_EGPRS_RX_ONLY
+ ,MS_EGPRS_FULL_FUNCTION
+} MS_CAPABILITY_E;
+
+typedef struct
+{
+ ARFCN arfcn;
+ kal_int8 sampleNoPerFrame;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain;
+ kal_int16 frames;
+} RfTestCmdPm;
+
+typedef struct
+{
+ ARFCN arfcn;
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 dacValue;
+#else
+ kal_int16 dacValue;
+#endif
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain;
+ kal_int16 testNumber;
+} RfTestCmdAfc;
+
+typedef struct
+{
+ ARFCN arfcn;
+ BSIC bsic;
+ kal_int8 bitmask;
+ Power txPowerLev;
+ kal_int16 frames;
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 dacValue;
+#else
+ kal_int16 dacValue;
+#endif
+ APCTxPattern burstTypeNB;
+} RfTestCmdNbTx;
+
+typedef struct
+{
+ ARFCN arfcn;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain;
+ kal_bool onOff;
+} RfTestCmdContRx;
+
+typedef struct
+{
+ ARFCN arfcn;
+ ContTxPattern pattern;
+ kal_bool onOff;
+} RfTestCmdContTx;
+
+typedef struct {
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+} RfTestCmdSetBBTXCfg;
+
+typedef struct {
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+ kal_int8 TxCalbias;
+ kal_int8 TxIQSwap;
+ kal_int8 TxCMV;
+ kal_int8 TxGain;
+ kal_int8 TxCalrcsel;
+} RfTestCmdSetBBTXCfg2;
+
+typedef struct {
+ ARFCN arfcn;
+ BSIC bsic;
+ kal_int8 timeSlotmask;
+ Power powerLev[4];
+ CodingScheme cs[4];
+ TimingAdvance ta;
+ kal_int32 frames;
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 dacValue;
+#else
+ kal_int16 dacValue;
+#endif
+} RfTestCmdMultiSlotTX;
+
+typedef struct {
+ kal_int32 rf_band;
+ kal_int32 power_level;
+ kal_int32 apc_dac;
+} RfTestCmdSetRampApcLevel;
+
+typedef struct {
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 dacValue;
+#else
+ kal_int16 dacValue;
+#endif
+} RfTestCmdSetAfcDacValue;
+
+typedef struct {
+ kal_int32 cap_id;
+} RfTestCmdSetCrystalCfg;
+
+typedef struct {
+ kal_int32 rf_band;
+} RfTestCmdSetRampTable;
+
+typedef struct {
+ kal_bool is_sinwave;
+} RfTestCmdSetAfcSinWave;
+
+typedef struct {
+ kal_uint32 bsi_data;
+} RfTestCmdSetBSI;
+
+typedef struct {
+ kal_uint32 bsi_addr;
+} RfTestCmdGetBSI;
+
+typedef struct {
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+ kal_int8 TxCalbias;
+ kal_int8 TxIQSwap;
+ kal_int8 TxCMV;
+ kal_int8 TxGain;
+ kal_int8 TxCalrcsel;
+ kal_int8 TxPhasesel;
+} RfTestCmdSetBBTXCfg3;
+
+typedef struct
+{
+ kal_int8 TxTrimI;
+ kal_int8 TxTrimQ;
+ kal_int8 TxOffsetI;
+ kal_int8 TxOffsetQ;
+ kal_int8 TxCalbias;
+ kal_int8 TxIQSwap;
+ kal_int8 TxCMV;
+ kal_int8 TxGain;
+ kal_int8 TxCalrcsel;
+ kal_int8 TxPhasesel;
+ kal_int8 TxCoarseI;
+ kal_int8 TxCoarseQ;
+
+}RfTestCmdSetBBTXCfg4;
+
+typedef struct {
+ ARFCN arfcn;
+ BSIC bsic;
+ kal_int8 timeSlotmask;
+ Power powerLev[4];
+ CodingScheme cs[4];
+ TimingAdvance ta;
+ kal_int32 frames;
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 dacValue;
+#else
+ kal_int16 dacValue;
+#endif
+ APCTxPattern pattern;
+ kal_uint16 pattern_data;
+} RfTestCmdMultiSlotTXEx;
+
+typedef struct {
+ ARFCN arfcn;
+ ContTxPattern pattern;
+ kal_uint16 pattern_data;
+ kal_bool onOff;
+ kal_uint16 modtype;
+} RfTestCmdContTxEx;
+
+typedef struct {
+ ARFCN arfcn;
+ ContTxPattern pattern;
+ kal_uint16 pattern_data;
+ kal_bool onOff;
+ kal_uint16 modtype;
+ Power powerLev;
+} RfTestCmdContTxEx2;
+
+typedef struct{
+ FrequencyBand band;
+ ARFCN BCH_ARFCN;
+ ARFCN TCH_ARFCN;
+ Gain BCH_gain;
+ Gain TCH_gain;
+ TSC tsc;
+ TimeSlot TCH_slot;
+ Power tx_power_level;
+ kal_bool is_EPSK_tx;
+ CodingScheme epsk_cs;
+}RfTestCmdNSFTParam;
+
+/** ----- 2G nsft V5 -----*/
+#if IS_2G_RXD_SUPPORT
+typedef struct{
+ FrequencyBand band;
+ ARFCN BCH_ARFCN;
+ ARFCN TCH_ARFCN;
+ Power BCH_DL_Power;
+ Power TCH_DL_Power;
+ TSC tsc;
+ TimeSlot TCH_slot;
+ Power tx_power_level;
+ kal_bool is_EPSK_tx;
+ CodingScheme epsk_cs;
+ kal_uint8 Antenna; //GSM_AntDimension
+}RfTestCmdNSFTParam_V5;
+#endif
+/** ----------------------*/
+
+
+typedef struct{
+ Power tx_power_level;
+}RfTestCmdNSFTPowerChangeParam;
+
+/** ----- 2G list mode nsft -----*/
+typedef struct
+{
+ kal_uint8 cmd_count;
+} RfTestCmdListModeNSFTParam;
+
+typedef struct
+{
+ kal_uint8 cmd_type;
+} RfTestCmdListModeNSFTCommonParam;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_int16 sync_power;
+ kal_uint8 sync_slot_offset;
+} RfTestCmdListModeNSFT_Sync_REQ;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 tsc;
+ kal_uint8 trx_type;
+ kal_int16 tx_power;
+} RfTestCmdListModeNSFT_Trigger_REQ;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 tsc;
+ kal_uint8 trx_type;
+ kal_int8 tx_pcl[8];
+ kal_int16 rx_power;
+ kal_int8 repeat_count[8];
+} RfTestCmdListModeNSFT_CHMeas_REQ;
+
+typedef union
+{
+ RfTestCmdListModeNSFT_Sync_REQ sync;
+ RfTestCmdListModeNSFT_Trigger_REQ trigger;
+ RfTestCmdListModeNSFT_CHMeas_REQ test;
+} RfTestCmdListModeNSFTCmdParam;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCmdParam param[60];
+} RfTestCmdListModeNSFT;
+// --------------------------------- //
+
+
+
+/** ----- 2G list mode nsft V5 -----*/
+#if IS_2G_RXD_SUPPORT
+//Req Param
+typedef struct
+{
+ kal_uint8 cmd_count;
+ kal_uint8 Antenna; // GSM_AntDimension
+} RfTestCmdListModeNSFTParam_V5;
+
+
+//Req Pdu
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 trx_type; //new param
+ kal_int16 sync_power;
+ kal_uint8 sync_slot_offset;
+} RfTestCmdListModeNSFT_Sync_REQ_V5;
+
+typedef RfTestCmdListModeNSFT_Trigger_REQ RfTestCmdListModeNSFT_Trigger_REQ_V5;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCommonParam common;
+ kal_uint8 band;
+ kal_uint16 arfcn;
+ kal_uint8 tsc;
+ kal_uint8 trx_type;
+ kal_int8 tx_pcl[8];
+ kal_int16 rx_power;
+ kal_int8 repeat_count[8];
+} RfTestCmdListModeNSFT_CHMeas_REQ_V5;
+//typedef RfTestCmdListModeNSFT_CHMeas_REQ RfTestCmdListModeNSFT_CHMeas_REQ_V5;
+
+typedef union
+{
+ RfTestCmdListModeNSFT_Sync_REQ_V5 sync;
+ RfTestCmdListModeNSFT_Trigger_REQ_V5 trigger;
+ RfTestCmdListModeNSFT_CHMeas_REQ_V5 test;
+} RfTestCmdListModeNSFTCmdParam_V5;
+
+typedef struct
+{
+ RfTestCmdListModeNSFTCmdParam_V5 param[60];
+} RfTestCmdListModeNSFT_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+// --------------------------------- //
+
+
+
+// ***************************************** //
+// FDT Calibration
+// ***************************************** //
+#define FT_MAX_STEP_CNT_50P 50
+#define FT_MAX_STEP_CNT_100P 100
+#define FT_MAX_STEP_CNT_512P 512
+
+typedef struct
+{
+ FrequencyBand band;
+ ARFCN arfcn;
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 dac_value[33];
+#else
+ kal_int16 dac_value[33];
+#endif
+ Gain gain;
+ kal_int16 repeat_cnt; // repetitive test counts (frames) for each AFC DAC value
+ kal_bool capid_cal; // capid calibration ctrl
+ kal_bool linear_cal; // 33 stages calibration ctrl
+ //kal_int8 capid_min; // min value for capid range when capid_cal is True; capid when capid_cal is False
+ //kal_int8 capid_max; // max value for capid range
+ kal_int32 capid_min; // min value for capid range when capid_cal is True; capid when capid_cal is False
+ kal_int32 capid_max; // max value for capid range
+} RFTestCmdDSSAfc;
+
+#define RF_TEST_CMD_DSSPL_HDR \
+ FrequencyBand band; \
+ ARFCN arfcn; \
+ Gain gain[6]; \
+ kal_int16 repeat_cnt; \
+
+typedef struct
+{
+ //FrequencyBand band;
+ //ARFCN arfcn;
+ //Gain gain[6]; // gain for rx slot 0/1/2/3/4/5
+ //kal_int16 repeat_cnt; // repetitive test counts (frames) for each ARFCN value
+ RF_TEST_CMD_DSSPL_HDR
+ //kal_uint16 dac_value; // Use InitDacValue from AFC calibration when dacValue = 0 (or -1)
+} RFTestCmdDSSPL;
+
+typedef enum
+{
+ LNA_NULL, //For old CMD, tool will not set gsm_lna_mode
+ LNA_HIGH,
+ LNA_MID,
+ LNA_LOW,
+ LNA_W_COEF,
+ LNA_SAWLESS_MID
+}RFTestCmdLNACalType;
+
+typedef struct
+{
+ RF_TEST_CMD_DSSPL_HDR
+ RFTestCmdLNACalType gsm_lna_mode; //0(Null) 1(high) 2(mid) 3(low) 4(w-coef) 5(sawless mid) 6(elna+G6) 7(elna bypass+G1)
+} RFTestCmdDSSPL_V2;
+
+typedef enum
+{
+ LNA_NULL_V3, //For old CMD, tool will not set gsm_lna_mode
+ LNA_HIGH_V3,
+ LNA_MID_V3,
+ LNA_LOW_V3,
+ LNA_W_COEF_V3,
+ LNA_SAWLESS_MID_V3,
+ ELNA_HIGH_SENSITIVITY,
+ ELNA_BYPASS_LOW_MAXPIN
+}RFTestCmdLNACalType_V3;
+
+typedef struct
+{
+ RF_TEST_CMD_DSSPL_HDR
+ RFTestCmdLNACalType_V3 gsm_lna_mode; //0(Null) 1(high) 2(mid) 3(low) 4(w-coef) 5(sawless mid) 6(elna+G6) 7(elna bypass+G1)
+} RFTestCmdDSSPL_V3;
+
+#define RF_TEST_CMD_DTS_HDR \
+ kal_bool afc_cal; \
+ kal_bool pl_cal; \
+ kal_int8 sync_sb_num; \
+ kal_int16 power; \
+ RFTestCmdDSSAfc AfcDSS;
+
+typedef struct
+{
+ //kal_bool afc_cal;
+ //kal_bool pl_cal; // Control whether Path loss calibration is needed or not
+ //kal_int8 sync_sb_num; // the SB frame numbers needed for sync process before path loss calibration
+ //kal_int16 power; // the power level expected to measure from test set
+ //RFTestCmdDSSAfc AfcDSS;
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_50P-2];
+} RFTestCmdDTS_50P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_100P-2];
+} RFTestCmdDTS_100P;
+
+/* [LPM CAL] */
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_50P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_50P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ RFTestCmdDSSPL PathLossDSS[FT_MAX_STEP_CNT_100P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_100P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ RFTestCmdDSSPL_V2 PathLossDSS[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_512P;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ RFTestCmdDSSPL_V3 PathLossDSS[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 lpm_sb_num;
+} RFTestCmdDTS_Lpm_512P_V3;
+
+
+/* ----RF_TEST_CMD_GET_CALIBRATION_INFO_FOR_RXD_V5 ---- */
+#if IS_2G_RXD_SUPPORT
+typedef enum
+{
+ NON_ELNA,
+ ELNA_BYPASS_NB_MATCH,
+ ELNA_BYPASS_WB_MATCH,
+ ELNA_ALWAYS_ON
+} RfTestRx_Elna_Type_E;
+
+typedef enum
+{
+ RX_LNA_NONE = 0,
+ RX_LNA_UTRA_HIGH = 1,
+ RX_LNA_HIGH = 2,
+ RX_LNA_MID = 3,
+ RX_LNA_MID_SAWLESS = 4,
+ RX_LNA_LOW = 5,
+ RX_LNA_BYPASS_LOW = 6, //the same as GSM_RF_MAX_RX_GAIN_NUM_V5
+} RfTestRx_Lna_Mode_E;
+
+typedef enum
+{
+ SUPPORT_BAND_GSM400,
+ SUPPORT_BAND_GSM850,
+ SUPPORT_BAND_GSM900,
+ SUPPORT_BAND_DCS1800,
+ SUPPORT_BAND_PCS1900,
+ SUPPORT_BAND_NUM
+} RfTestSupportBand; //FrequencyBand
+
+typedef struct
+{
+ //FHC
+ kal_uint8 seq_num;
+ kal_int16 dlpow_default[GSM_RF_MAX_RX_GAIN_NUM_V5]; //0.125 dBm
+ kal_int16 dlpow_lbound[GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_int16 dlpow_hbound[GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_uint8 lna_enum_type[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5]; //RfTestRx_Lna_Mode_E
+ kal_uint8 antenna_enable[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_int16 dlpow_wcoef_default; //0.125 dBm
+ kal_int16 dlpow_wcoef_lbound;
+ kal_int16 dlpow_wcoef_hbound;
+ kal_int16 wcoef_arfcn[8]; //each band woef arfcn, [850][900][DCS][PCS]=[1][2][8][6]
+
+ //for trad cal
+ kal_int16 gain_default[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5]; // 0.125 dB
+ kal_int16 wcoef_gain_default[GSM_RF_MAX_RX_ANT_NUM]; // 0.125 dB
+ //RF Tool
+ kal_uint8 elna_type[GSM_RF_MAX_RX_ANT_NUM]; // RfTestRx_Elna_Type_E
+ kal_int16 gain_hbound[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5];
+ kal_int16 gain_lbound[GSM_RF_MAX_RX_ANT_NUM][GSM_RF_MAX_RX_GAIN_NUM_V5];
+} RfTestCmdCalInfoV5_T; // RfTestElnaInfoV5_T
+
+typedef struct
+{
+ RfTestCmdCalInfoV5_T GSM_Band_Info[SUPPORT_BAND_NUM-1]; //No GSM400
+} RfTestCmdCalInfoV5AllBandCnfPdu_T;
+
+
+/* ----RF_TEST_CMD_START_FDT_DL_NOT_WAIT_RESULT_LPM_512P_V5 ---- */
+typedef enum
+{
+ RX_CAL_SEQ_V5_NULL = RX_LNA_NONE ,
+ RX_CAL_SEQ_V5_UTRA_HIGH = RX_LNA_UTRA_HIGH ,
+ RX_CAL_SEQ_V5_HIGH = RX_LNA_HIGH ,
+ RX_CAL_SEQ_V5_MID = RX_LNA_MID ,
+ RX_CAL_SEQ_V5_MID_SAWLESS = RX_LNA_MID_SAWLESS,
+ RX_CAL_SEQ_V5_LOW = RX_LNA_LOW ,
+ RX_CAL_SEQ_V5_BYPASS_LOW = RX_LNA_BYPASS_LOW ,
+ RX_CAL_SEQ_V5_WCOEF
+} RfTestRxCalSeqV5_E; //the same as LNACalSeqV5_E //reference to RfTestRx_Lna_Mode_E
+
+typedef struct
+{
+ FrequencyBand band;
+ ARFCN arfcn;
+ kal_int16 repeat_cnt;
+ kal_int16 dl_power; //it is DL Power for each frame
+ RfTestRxCalSeqV5_E gsm_lna_mode[GSM_RF_MAX_RX_ANT_NUM];
+} RFTestCmdDSSPL_V5;
+
+typedef struct
+{
+ RF_TEST_CMD_DTS_HDR
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ RFTestCmdDSSPL_V5 PathLossDSS[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 lpm_sb_num;
+ kal_uint8 Antenna; //GSM_AntDimension
+} RFTestCmdDTS_Lpm_512P_V5;
+
+
+/* ----RF_TEST_CMD_PM_V5 & RF_TEST_CMD_IF_PM_V5---- */
+//REQ Param
+typedef struct
+{
+ RfTestSupportBand band;
+ ARFCN arfcn;
+ kal_int8 sampleNoPerFrame;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain gain[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int16 frames;
+ GSM_AntDimension Antenna;
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+} RfTestCmdPm_V5;
+
+//CNF Param
+typedef struct
+{
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ kal_int32 power[GSM_RF_MAX_RX_ANT_NUM];
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS*2 bits*/
+ kal_int32 deviation[GSM_RF_MAX_RX_ANT_NUM];
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain usedGain[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 iOffset[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 qOffset[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 validSamples[GSM_RF_MAX_RX_ANT_NUM];
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+ kal_int32 ok;
+} RfTestResultPm_V5;
+
+
+/* ----RF_TEST_CMD_CONTINUOUS_RX_V5---- */
+//REQ Param
+typedef struct
+{
+ RfTestSupportBand band;
+ ARFCN arfcn;
+ Gain gain[GSM_RF_MAX_RX_ANT_NUM];
+ GSM_AntDimension Antenna;
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+ kal_bool onOff;
+} RfTestCmdContRx_V5;
+//CNF Param
+//kal_bool ok;
+
+
+/* ----RF_TEST_CMD_RX_GAIN_CALCULATE_V5---- */
+//REQ Param
+typedef struct
+{
+ RfTestSupportBand band;
+ GSM_AntDimension Antenna;
+ RfTestRx_Lna_Mode_E elna_mode[GSM_RF_MAX_RX_ANT_NUM];
+} RfTestCmdRxGainCalculate_V5;
+
+//CNF Param
+typedef enum
+{
+ GSM_CALCULATE_NULL = 0,
+ GSM_CALCULATE_SUCCESS,
+ GSM_CALCULATE_FAIL
+} GSM_RxGain_Caculator;
+
+typedef struct
+{
+ kal_int16 recommend_dlpow;
+ kal_uint16 request_gain [GSM_RF_MAX_RX_ANT_NUM]; // 1/8 dB
+ GSM_RxGain_Caculator calculate_status;
+} RfTestResultRxGainCalculate_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+/* ---------------------------------------------------------------------------- */
+
+
+typedef struct
+{
+ FrequencyBand band;
+ ARFCN arfcn;
+ kal_int8 timeslot_per_frame;
+ kal_int8 apc_dac_pcl_sel; // 1: apc_dac, 0: apc_pcl
+ kal_int16 apc_dac_pcl_value[4];
+ //kal_uint8 pa_vbias_val;
+ kal_uint8 pa_vbias_val[4];
+ kal_uint8 is_low_pcl[4];
+
+ CodingScheme cs[4];
+ kal_int32 repeat_cnt;
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 afc_dac_value;
+#else
+ kal_int16 afc_dac_value;
+#endif
+ kal_int8 tsc;
+ APCTxPattern pattern;
+ kal_uint16 pattern_data;
+} RfTestCmdUSSApc;
+
+typedef struct
+{
+ //kal_bool pa_vbias_cal; // Control whether PA need to calibrate different Vbias value when APC DAC is used
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ kal_int16 high_apc_dcoffset[FrequencyBandCount];
+ // kal_int32 lowest_power[FrequencyBandCount];
+ RfTestCmdUSSApc ApcUSS[FT_MAX_STEP_CNT_50P];
+}RfTestCmdUTS_50P;
+
+typedef struct
+{
+ kal_int8 step_cnt; //Still use int8, old CMD struct must the same as before
+ kal_int16 high_apc_dcoffset[FrequencyBandCount];
+ RfTestCmdUSSApc ApcUSS[FT_MAX_STEP_CNT_100P];
+}RfTestCmdUTS_100P;
+
+typedef struct
+{
+ kal_uint16 step_cnt; //int8 -> uint16 to match size 512
+ kal_int16 high_apc_dcoffset[FrequencyBandCount];
+ RfTestCmdUSSApc ApcUSS[FT_MAX_STEP_CNT_512P];
+}RfTestCmdUTS_512P;
+
+typedef struct
+{
+ //kal_int32 rf_band;
+ kal_int16 afc_offset[FrequencyBandCount];
+
+}RF_SET_AFC_DAC_OFFSET_REQ_T;
+
+typedef struct
+{
+ signed char rollback_2t; /* Rollback (2t/F2I_Resolution) dB when 2 TX slots */
+ signed char rollback_3t; /* Rollback (3t/F2I_Resolution) dB when 3 TX slots */
+ signed char rollback_4t; /* Rollback (4t/F2I_Resolution) dB when 4 TX slots */
+ signed char rollback_5t; /* Rollback (5t/F2I_Resolution) dB when 5 TX slots */
+} FT_Rf_sTX_POWER_ROLLBACK;
+
+typedef struct
+{
+ kal_int32 band;
+ FT_Rf_sTX_POWER_ROLLBACK PowerRollbackTable;
+}RfTestCmdSetPowerRollbackTable;
+
+/**
+ * The RfTestCmdIrPm is used for IRR w coeffiecient calibration
+ * The command is analogous to RfTestCmdPm, except the m_IfFlag
+ */
+typedef struct
+{
+ /// power scan input parameter
+ RfTestCmdPm m_Pm;
+ /// if_flag for the power scan (to override the if setting in power scan, the original interface is not changed)
+ kal_int8 m_IfFlag;
+}RfTestCmdIrPm;
+
+#if IS_2G_RXD_SUPPORT
+typedef struct
+{
+ /// power scan input parameter
+ RfTestCmdPm_V5 m_Pm;
+ /// if_flag for the power scan (to override the if setting in power scan, the original interface is not changed)
+ kal_int8 m_IfFlag;
+}
+RfTestCmdIrPm_V5;
+#endif
+
+typedef struct
+{
+ FrequencyBand band;
+ Power pcl;
+}RfTestCmdTXPC;
+// ***************************************** //
+
+// R8 edge new feature
+typedef struct
+{
+ unsigned char rf_band;
+ unsigned short pa_gain[16];
+}RfTestCmdSetEdgeTxOctPACoef;
+
+typedef struct
+{
+ kal_uint8 rf_band;
+ kal_int8 cTxAdc_State;
+ kal_int8 is_EPSK;
+}RfTestCmdResetPdData;
+
+typedef struct{
+ ARFCN arfcn; // absolute radio frequency channel number
+ BSIC bsic; // training sequence
+ CodingScheme cs; // coding scheme for each time slot, MCS1~9 is only valid for EPSK function
+ TimingAdvance ta; // time advance
+ kal_int32 frames; // the number of frames should transmit
+ kal_int16 dacValue; // AFC DAC value
+ APCTxPattern pattern; // Tx pattern is only valid for EPSK function
+ kal_uint16 pattern_data; // if NB_TX_PATTERN_WITHOUT_TSC==pattern, user can input any 16bits value as pattern.
+ kal_uint16 pa_gain; // pa gain from ini file
+ kal_uint16 pa_vbias; // pa vbias from ini file
+ kal_uint8 rf_gain_index; // gain rf index
+}Rf_GainRfTx_Req;
+
+typedef struct
+{
+ kal_uint16 max_arfcn;
+ kal_int8 path_loss_H;
+ kal_int8 path_loss_M;
+ kal_int8 path_loss_M_sawless;
+ kal_int8 path_loss_L;
+}RfPathLossOffset;
+
+typedef struct
+{
+ RfPathLossOffset rx_pathloss[FrequencyBandCount][PLTABLE_SIZE];
+}RfTestCmdSetGetRxPathLoss;
+
+typedef struct
+{
+ kal_uint16 max_arfcn;
+ kal_int8 path_loss_H;
+ kal_int8 path_loss_M;
+ kal_int8 path_loss_M_sawless;
+ kal_int8 path_loss_L;
+ kal_int8 path_loss_H_sensitivity; //elna+g6
+ kal_int8 path_loss_L_maxpin; //elna_bypass+g1 ,sLNAGAINOFFSET
+}RfPathLossOffset_V3;
+
+typedef struct
+{
+ RfPathLossOffset_V3 rx_pathloss[FrequencyBandCount][PLTABLE_SIZE];
+}RfTestCmdSetGetRxPathLoss_V3;
+
+typedef struct
+{
+ RfTestCmdAfc afc;
+ FrequencyBand band;
+ RfTestCmdSetAfcSinWave setAfcSinWave;
+}RfTestCmdSinewaveAfcGetTempFreq;
+
+typedef struct
+{
+ //sRFSpecialCoef rfspecialcoef;
+ //RFSpecialCoef.rx.mt6256_51rf.w_data
+ w_coef w_data[WCTABLE_SIZE];
+}RfTestCmdSetGetWcoefPdu;
+
+
+
+
+/* -------------------- *\
+|* SET TX CMD REQ Struct *|
+ \* -------------------- */
+#define RF_MAX_PEER_BUF_CNF_BYTE_SIZE 51200 //50*1024
+#define RF_MAX_PEER_BUF_CNF_WORD_SIZE RF_MAX_PEER_BUF_CNF_BYTE_SIZE >> 2
+
+typedef enum
+{
+ GMSK_Band850 =1, //0x00 01
+ GMSK_Band900 =2, //0x00 02
+ GMSK_Band1800 =4, //0x00 04
+ GMSK_Band1900 =8, //0x00 08
+ EPSK_Band850 =256, //0x01 00
+ EPSK_Band900 =512, //0x02 00
+ EPSK_Band1800 =1024, //0x04 00
+ EPSK_Band1900 =2048, //0x08 00
+}RfTestTxData_ModBand_Bitmap_E;
+
+typedef struct
+{
+ kal_uint16 count;
+ kal_uint16 offset;
+ //kal_uint16 mod_band_bitmap; //modulation+band bitmap
+ //// EPSK(4bit) | GMSK(4bit) -> 0000 0101 | 0000 0011 -> PCS|DCS|900|850 ex.Set Data for GSM850/GSM900 GMSK + GSM850/DCS EPSK Ramping
+ //kal_uint16 mod_bitmap; //modulation bitmap
+ //// EPSK(1bit) | GMSK(1bit) -> 00000001 | 00000001 ex.Set Data for GMSK & EPSK Txpc
+ //kal_uint16 band_bitmap; //band bitmap
+ // EPSK(4bit) -> PCS|DCS|900|850-> 0000 1111 | 0000 0000 ex.Set Data for EPSK interslotramp GSM850/GSM900/DCS/PCS
+ //kal_uint16 not_used_bitmap; //0000 0000 | 0000 0001, only need one bit, data did not separate from diff band and mod type
+ kal_uint16 bitmap; //for general purpose //RfTestTxData_ModBand_Bitmap_E //RfTestRxData_ModBand_Bitmap_E
+ kal_uint16 zero_padding;
+}RfTestParamDynamicEntryElm_T;
+
+typedef struct
+{
+ kal_uint16 is_uplate_to_NVRAM;
+ RfTestParamDynamicEntryElm_T type1_ramptable_param;
+ RfTestParamDynamicEntryElm_T type2_epsk_interramptable_param;
+ RfTestParamDynamicEntryElm_T type3_txpc_param;
+ RfTestParamDynamicEntryElm_T type4_epskpa_param;
+}RfTestCmdSetTxDataReqParam;
+
+typedef l1cal_rampTable_T L1_Ramptable_Type1_T;
+
+#if MD_DRV_IS_EPSK_TX_SUPPORT
+typedef l1cal_EPSK_interRampData_T L1_EPSK_InterRamptable_Type2_T;
+#endif
+
+typedef struct
+{
+ char is_calibrated;
+ short temperature;
+}L1_Txpc_Type3_T; //l1cal_txpc_T
+
+typedef orionRFtx_pa_vbias L1_EpskPA_Type4_T; //l1cal_rfspecialcoef_T
+
+typedef struct
+{
+ union
+ {
+ kal_int32 set_txdata_req_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ #if MD_DRV_IS_EPSK_TX_SUPPORT
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ #endif
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+ } request;
+}RfTestCmdSetTxDataReqPdu;
+/* -------------------------------------- */
+
+
+
+/* -------------------- *\
+|* GET TX CMD REQ Struct *|
+ \* -------------------- */
+typedef struct
+{
+ kal_uint16 type1_ramptable_count;
+ kal_uint16 type2_epsk_interramptable_count;
+ kal_uint16 type3_txpc_count;
+ kal_uint16 type4_epskpa_count;
+
+ //point out which kind of this type should be got
+ kal_uint16 type1_ramptable_bitmap;
+ kal_uint16 type2_epsk_interramptable_bitmap;
+ kal_uint16 type3_txpc_bitmap;
+ kal_uint16 type4_epskpa_bitmap;
+}RfTestCmdGetTxDataReqParam;
+/* -------------------------------------- */
+
+
+#if IS_2G_RXD_SUPPORT
+/* -------------------- *\
+|* SET RX CMD REQ Struct *|
+ \* -------------------- */
+typedef enum
+{
+ GSM_RXM_Band850 =1, //0x00 01
+ GSM_RXM_Band900 =2, //0x00 02
+ GSM_RXM_Band1800 =4, //0x00 04
+ GSM_RXM_Band1900 =8, //0x00 08
+ GSM_RXD_Band850 =256, //0x01 00
+ GSM_RXD_Band900 =512, //0x02 00
+ GSM_RXD_Band1800 =1024, //0x04 00
+ GSM_RXD_Band1900 =2048, //0x08 00
+}RfTestRxData_ModBand_Bitmap_E;
+
+//typedef struct
+//{
+// kal_uint16 count;
+// kal_uint16 offset;
+// kal_uint16 bitmap; //for general purpose //RfTestTxData_ModBand_Bitmap_E, RfTestRxData_ModBand_Bitmap_E
+// kal_uint16 zero_padding;
+//}RfTestParamDynamicEntryElm_T;
+
+typedef struct
+{
+ kal_uint16 is_uplate_to_NVRAM;
+ RfTestParamDynamicEntryElm_T type1_rxpathloss_param;
+ RfTestParamDynamicEntryElm_T type2_wcoef_param;
+}RfTestCmdSetRxDataReqParam;
+
+typedef struct
+{
+ RfPathLossOffset_V3 rx_pathloss_entry[PLTABLE_SIZE];
+} L1_SetGetRxPathLossEntry_Type1_T;
+
+typedef l1cal_wcoef_T L1_Wcoef_Type2_T;
+
+typedef struct
+{
+ union
+ {
+ kal_int32 set_rxdata_req_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_SetGetRxPathLossEntry_Type1_T type1_pathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+ } request;
+}RfTestCmdSetRxDataReqPdu;
+/* -------------------------------------- */
+
+
+/* -------------------- *\
+|* GET RX CMD REQ Struct *|
+ \* -------------------- */
+typedef struct
+{
+ kal_uint16 type1_rxpathloss_count;
+ kal_uint16 type2_wcoef_count;
+
+ //point out which kind of this type should be got
+ kal_uint16 type1_rxpathloss_bitmap;
+ kal_uint16 type2_wcoef_bitmap;
+}RfTestCmdGetRxDataReqParam;
+/* -------------------------------------- */
+#endif //#if IS_2G_RXD_SUPPORT
+
+/*GET TPO CMD REQ struct*/
+typedef struct
+{
+ FrequencyBand band;
+ kal_bool is_epsk;
+}RfTestCmdGetTPO;
+
+/*SET TPO CMD REQ struct*/
+typedef struct
+{
+ FrequencyBand band;
+ kal_bool is_epsk;
+ kal_int16 power_apcdac_offset; // unit:DAC
+ kal_int16 power_dB_offset; // 0.125 dB
+}RfTestCmdSetTPO;
+
+typedef union
+{
+ RfTestCmdPm pm;
+ RfTestCmdAfc afc;
+ RfTestCmdNbTx nbTx;
+ RfTestCmdContRx contRx;
+ RfTestCmdContTx contTx;
+ RfTestCmdSetBBTXCfg setBBTXCfg;
+ kal_bool selectPCS1900;
+ kal_int8 dummy;
+ RfTestCmdMultiSlotTX msTx;
+ RfTestCmdSetRampApcLevel setRampApcLevel;
+ RfTestCmdSetAfcDacValue setAfcDacValue;
+ RfTestCmdSetBBTXCfg2 BBTxCfg2;
+ RfTestCmdSetCrystalCfg setCrystalCfg;
+ RfTestCmdSetRampTable setRampTable;
+ RfTestCmdSetAfcSinWave setAfcSinWave;
+ RfTestCmdSetBSI SetBSI;
+ RfTestCmdGetBSI GetBSI;
+ RfTestCmdSetBBTXCfg3 BBTxCfg3;
+ RfTestCmdMultiSlotTXEx msTxEx;
+ RfTestCmdContTxEx contTxEx;
+ RfTestCmdContTxEx2 contTxEx2;
+ RfTestCmdSetBBTXCfg4 BBTxCfg4;
+ RF_SET_AFC_DAC_OFFSET_REQ_T set_afc_offset_req;
+ RfTestCmdNSFTParam NSFT_start;
+ RfTestCmdNSFTPowerChangeParam NSFT_change_power;
+ RfTestCmdSetPowerRollbackTable PowerRollbackTable;
+ kal_uint32 m_u4NSFTSBERTestCount;
+ /// for L1TST_ReportRXQual input
+ kal_uint16 m_u2NSFTRxQualBerDecile;
+ /// for SOC2 IRR W PM
+ RfTestCmdIrPm m_IrPm;
+ RfTestCmdTXPC txpc_req;
+ /// for L1TST_TXPC_CL_GetSubband input
+ kal_uint8 band;
+ /* [LPM CAL] */
+ /// for DCXO FPM/LPM control (1 FPM, 0 LPM)
+ kal_uint8 dcxoMode;
+ /// R8 edge new feature
+ RfTestCmdSetEdgeTxOctPACoef setTxOctPaCoef;
+ RfTestCmdResetPdData resetTxPcPdData;
+ /// gain rf tx
+ Rf_GainRfTx_Req gainRfTx;
+ kal_uint8 path_flag;
+ RfTestCmdType query_op_code;
+ RfTestCmdListModeNSFTParam List_Mode_NSFT_start;
+ kal_bool is_uplate_to_NVRAM;
+ RfTestCmdSinewaveAfcGetTempFreq afc_gpscoclockv2;
+ RfTestCmdSetTxDataReqParam set_txdata_req;
+ RfTestCmdGetTxDataReqParam get_txdata_req;
+ #if IS_2G_RXD_SUPPORT
+ RfTestCmdPm_V5 pm_v5;
+ RfTestCmdIrPm_V5 m_IrPm_v5;
+ RfTestCmdContRx_V5 contRx_v5;
+ RfTestCmdNSFTParam_V5 NSFT_start_v5;
+ RfTestCmdListModeNSFTParam_V5 List_Mode_NSFT_start_v5;
+ RfTestCmdSetRxDataReqParam set_rxdata_req;
+ RfTestCmdGetRxDataReqParam get_rxdata_req;
+ RfTestCmdRxGainCalculate_V5 rx_gain_calculate_req;
+ #endif
+ kal_uint8 rxlev_precision;
+ RfTestCmdGetTPO getTPOVlaue;
+ RfTestCmdSetTPO setTPOVlaue;
+} RfTestCmdParam;
+
+
+
+
+/* ---------------------------------- */
+typedef struct
+{
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ kal_int32 power;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS*2 bits*/
+ kal_int32 deviation;
+ /* Resoultion can be up to RSSI_RESOLUTION_BITS bits*/
+ Gain usedGain;
+ kal_int32 ok;
+ kal_int32 iOffset;
+ kal_int32 qOffset;
+ kal_int32 validSamples;
+} RfTestResultPm;
+
+typedef struct
+{
+ kal_int16 fcb_ok_number;
+ kal_int32 freqOffset;
+ kal_int32 deviation;
+ kal_int32 ok;
+} RfTestResultAfc;
+
+typedef struct
+{
+ kal_int16 fcb_ok_number;
+ kal_int32 freqOffset;
+ kal_int32 deviation;
+ kal_int32 ok;
+ kal_int32 temperature;
+} RfTestResultSinewaveAfcGetTempFreq;
+
+typedef struct {
+ kal_bool ok;
+ RfTestCmdSetBBTXCfg2 bbtx_cfg;
+} RfTestResultGetBBTXCfg2;
+
+typedef struct {
+ kal_uint32 GSM400;
+ kal_uint32 GSM850;
+ kal_uint32 GSM900;
+ kal_uint32 DCS1800;
+ kal_uint32 PCS1900;
+} RfTestResultBandSupport;
+
+typedef struct {
+ kal_bool ok;
+ MS_CAPABILITY_E capability;
+ RfTestResultBandSupport band_support;
+} RfTestResultMsCapability;
+/*
+#define MS_CAPABILITY_GSM 0x00000001
+#define MS_CAPABILITY_GPRS 0x00000002
+#define MS_CAPABILITY_EDGE_RX 0x00000004
+#define MS_CAPABILITY_EDGE_8PSK_TX 0x00000008
+#define MS_CAPABILITY_8PM 0x00000010
+
+#define MS_BAND_SUPPORT_GSM400 0x00000001
+#define MS_BAND_SUPPORT_GSM850 0x00000002
+#define MS_BAND_SUPPORT_GSM900 0x00000004
+#define MS_BAND_SUPPORT_DCS1800 0x00000008
+#define MS_BAND_SUPPORT_PCS1900 0x00000010
+*/
+
+typedef struct
+{
+ kal_uint32 capability;
+ kal_uint32 band_support;
+}RfResultMsCapabilityEx;
+
+typedef struct {
+ kal_bool ok;
+ kal_uint32 capability;
+ kal_uint32 band_support;
+} RfTestResultMsCapabilityEx;
+
+typedef struct {
+ kal_bool ok;
+ kal_uint32 id;
+} RfTestResultGetRFID;
+
+typedef struct {
+ kal_bool ok;
+ kal_uint32 bsi_data;
+} RfTestResultGetBSI;
+
+typedef struct {
+ kal_bool ok;
+ RfTestCmdSetBBTXCfg3 bbtx_cfg;
+} RfTestResultGetBBTXCfg3;
+
+typedef struct
+{
+ kal_bool ok;
+ RfTestCmdSetBBTXCfg4 bbtx_cfg;
+}RfTestResultGetBBTXCfg4;
+
+typedef struct {
+ kal_bool ok;
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 dacValue;
+#else
+ kal_int16 dacValue;
+#endif
+} RfGetAfcDacValueAtRTXOffsetCal;
+
+typedef struct
+{
+ kal_bool ok;
+ kal_int32 calibra_result_32k;
+}RfTestResult32kCalibration;
+
+// ****************************** //
+// FDT Calibration
+// ****************************** //
+typedef struct
+{
+ kal_int32 power[FT_MAX_STEP_CNT_50P-2];
+ kal_int16 valid_sample[FT_MAX_STEP_CNT_50P-2];
+ kal_bool ok;
+} RfTestResultDSSPL_50P;
+
+typedef struct
+{
+ kal_int32 power[FT_MAX_STEP_CNT_100P-2];
+ kal_int16 valid_sample[FT_MAX_STEP_CNT_100P-2];
+ kal_bool ok;
+} RfTestResultDSSPL_100P;
+
+typedef struct
+{
+ kal_int32 power[FT_MAX_STEP_CNT_512P-2];
+ kal_int16 valid_sample[FT_MAX_STEP_CNT_512P-2];
+ kal_bool ok;
+ //kal_bool is_se_sawless; // remove this item, otherwise memory copy from ResultDSSPL will be not match
+} RfTestResultDSSPL_512P; /** For sawless lna mode and enlarge size=512 to reduce CMD round trip number*/
+
+typedef struct
+{
+ kal_int32 freq_offset[33]; // only valid when 33 stage calibration is ON
+ kal_int32 deviation[33]; // only valid when 33 stage calibration is ON
+ kal_int16 fcb_ok_number[33];
+ //kal_int8 capid; // only valid when capid calibration is ON
+ kal_int32 capid; // only valid when capid calibration is ON
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 init_dac_value; // only valid when 33 stage calibration is OFF
+#else
+ kal_int16 init_dac_value; // only valid when 33 stage calibration is OFF
+#endif
+ kal_int32 slope; // only valid when 33 stage calibration is OFF
+ kal_bool ok;
+} RfTestResultDSSAfc;
+/* [LPM CAL] */
+typedef struct
+{
+ kal_int32 cload_freq_offset;
+ kal_bool ok;
+ kal_bool is_perform_cal;
+} RfTestResultDSSLpm;
+
+#if IS_FHC_SUPPORT == 1
+typedef struct
+{
+ kal_int32 path_loss_cnt;
+ kal_int32 freq_offset;
+ kal_int32 capid_freq_offset_min;
+ kal_int32 capid_freq_offset[FHC_MAX_CAPID_SEARCH_NUM]; // 16
+ kal_int32 capid_search_order[FHC_MAX_CAPID_SEARCH_NUM]; // 16
+ kal_int32 capid;
+ kal_int32 capid_high;
+ kal_int32 capid_low;
+ kal_int32 capid_best;
+ #if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 afc_dac;
+ #else
+ kal_int16 afc_dac;
+ #endif
+ kal_int16 arfcn;
+ kal_int16 capid_cnt;
+ kal_int16 repeat_index;
+ kal_int8 state;
+ kal_int8 capid_index;
+ kal_int8 capid_okay_cnt;
+ kal_int8 afc_dac_index;
+ kal_int8 sb_okay_cnt;
+ kal_uint8 sb_fail_cnt;
+ kal_uint8 fb_fail_cnt;
+ kal_bool pl_started;
+ kal_bool pre_capid_cal_ok[FHC_PRE_CAPID_SEARCH_NUM]; // FHC_PRE_CAPID_SEARCH_NUM
+}RfTestResultDtsmInfo;
+#else
+typedef struct
+{
+ kal_int32 path_loss_cnt;
+ kal_int32 freq_offset;
+ kal_int32 capid_freq_offset_min;
+ kal_int32 capid_freq_offset[16]; //FHC_MAX_CAPID_SEARCH_NUM
+ kal_int32 capid_search_order[16]; //FHC_MAX_CAPID_SEARCH_NUM
+ kal_int32 capid;
+ kal_int32 capid_high;
+ kal_int32 capid_low;
+ kal_int32 capid_best;
+ #if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 afc_dac;
+ #else
+ kal_int16 afc_dac;
+ #endif
+ kal_int16 arfcn;
+ kal_int16 capid_cnt;
+ kal_int16 repeat_index;
+ kal_int8 state;
+ kal_int8 capid_index;
+ kal_int8 capid_okay_cnt;
+ kal_int8 afc_dac_index;
+ kal_int8 sb_okay_cnt;
+ kal_uint8 sb_fail_cnt;
+ kal_uint8 fb_fail_cnt;
+ kal_bool pl_started;
+ kal_bool pre_capid_cal_ok[9]; // FHC_PRE_CAPID_SEARCH_NUM
+}RfTestResultDtsmInfo;
+#endif
+
+typedef enum {
+ DTS_RESULT_READY = 0, // DTS results is ready to get back
+ DTS_RESULT_NOT_READY, // DTS result is still in progress and not ready to get back
+ DTS_RESULT_NOT_REQUESTED, // Haven't called the META_Rf_StartFdtDL() in advance.
+ DTS_FATAL_ERROR
+}RF_DTS_GET_RESULT_STATUS;
+typedef struct
+{
+ RfTestResultDSSPL_50P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo; // for L1 debug use, will print in META Tool's test report.
+} RfTestResultDTS_50P;
+
+typedef struct
+{
+ RfTestResultDSSPL_100P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo; // for L1 debug use, will print in META Tool's test report.
+} RfTestResultDTS_100P;
+
+
+/* [LPM CAL] */
+typedef struct
+{
+ RfTestResultDSSPL_50P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_50P;
+
+typedef struct
+{
+ RfTestResultDSSPL_100P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_100P;
+
+typedef struct
+{
+ RfTestResultDSSPL_512P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_512P; /** For sawless lna mode and reduce CMD round trip number*/
+
+typedef struct
+{
+ RfTestResultDSSPL_512P PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_512P_V3; /** For sawless lna mode and reduce CMD round trip number*/
+
+/*------RF_TEST_CMD_START_FDT_DL_WAIT_RESULT_LPM_512P_V5, RF_TEST_CMD_GET_FDT_RESULT_LPM_512P_V5------*/
+#if IS_2G_RXD_SUPPORT
+typedef struct
+{
+ kal_int32 power[GSM_RF_MAX_RX_ANT_NUM][FT_MAX_STEP_CNT_512P-2];
+ kal_int16 valid_sample[GSM_RF_MAX_RX_ANT_NUM][FT_MAX_STEP_CNT_512P-2];
+ kal_bool ok;
+} RfTestResultDSSPL_512P_V5; //ResultDSSPL
+
+typedef struct
+{
+ RfTestResultDSSPL_512P_V5 PLResult;
+ RfTestResultDSSAfc AfcResult;
+ RfTestResultDtsmInfo m_rDtsmInfo;
+ /* crystal low power mode calibration result (for 32k removal) */
+ RfTestResultDSSLpm LpmResult;
+} RfTestResultDTS_Lpm_512P_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+/*---------------------------------------------------------------*/
+
+typedef struct
+{
+ kal_int16 afc_offset[FrequencyBandCount];
+ kal_bool ok;
+}RfGetAfcOffsetResult;
+
+typedef struct
+{
+ kal_uint32 m_u4NSFTSBER;
+ kal_uint32 m_u4NSFTSBERCurrentCount;
+}RfNSFTSBERResult;
+// local
+typedef struct
+{
+ kal_bool ok;
+ kal_uint16 m_u2PDValue;
+}RfTestResultPDValue;
+
+// peer
+typedef struct
+{
+ kal_uint16 data[16];
+} RfTestResultTXPCPD;
+
+typedef struct
+{
+ kal_uint16 data[8];
+} RfTestResultTXPCPDTemp;
+
+typedef struct
+{
+ /// calibrated flag
+ kal_int8 is_calibrated;
+ /// closed-loop target value by PCL
+ RfTestResultTXPCPD adc[FrequencyBandCount];
+ /// temperature compensation interval
+ kal_int16 temperature;
+ /// closed-loop target value by temperature compensation
+ RfTestResultTXPCPDTemp temp[FrequencyBandCount];
+}RfTestResultTXPCAllPD;
+
+typedef struct
+{
+ kal_int16 status;
+ kal_int16 tadc_dac;
+ kal_int16 temperature;
+ kal_int16 temp_idx;
+} RfTestResultRfTemperatureInfo;
+
+// ****************************** //
+
+typedef struct
+{
+ kal_uint32 result; // 1: support 0: not support
+ kal_uint32 query_op_code; // query op code
+}RfCheckIfFuncExist;
+
+/** ----- 2G list mode nsft -----*/
+typedef struct
+{
+ kal_uint8 report_count;
+}RfTestResultListModeNSFT;
+
+typedef struct
+{
+ kal_uint16 status; //NsftListCmdStatus //NsftListRpt_Com_t
+}RfTestResultListModeNSFTCommon;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+ kal_uint16 retry_count;
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ kal_uint16 new_afc_dac;
+#else
+ kal_int16 new_afc_dac;
+#endif
+ kal_int32 detected_foe;
+}RfTestResultListModeNSFTSync;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+}RfTestResultListModeNSFTTrigger;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+ kal_uint16 RX_level;
+ kal_uint32 BER_sum;
+ kal_uint32 BER_frame_count;
+}RfTestResultListModeNSFTMeasure;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+}RfTestResultListModeNSFTStop;
+
+typedef union
+{
+ RfTestResultListModeNSFTSync sync;
+ RfTestResultListModeNSFTTrigger trigger;
+ RfTestResultListModeNSFTMeasure test;
+ RfTestResultListModeNSFTStop stop;
+}RfTestResultListModeNSFTReport;
+
+typedef struct
+{
+ unsigned char cmd_type[60];
+ RfTestResultListModeNSFTReport report[60];
+}RfTestResultListModeNSFTParam;
+// --------------------------------- //
+
+
+/** ----- 2G list mode nsft V5 -----*/
+#if IS_2G_RXD_SUPPORT
+//CNF Local Param
+typedef RfTestResultListModeNSFT RfTestResultListModeNSFT_V5;
+
+//CNF Pdu
+typedef RfTestResultListModeNSFTSync RfTestResultListModeNSFTSync_V5;
+typedef RfTestResultListModeNSFTTrigger RfTestResultListModeNSFTTrigger_V5;
+
+typedef struct
+{
+ RfTestResultListModeNSFTCommon common;
+ kal_uint16 RX_level[GSM_RF_MAX_RX_ANT_NUM];
+ kal_uint32 BER_sum;
+ kal_uint32 BER_frame_count;
+}RfTestResultListModeNSFTMeasure_V5;
+
+typedef RfTestResultListModeNSFTStop RfTestResultListModeNSFTStop_V5;
+
+typedef union
+{
+ RfTestResultListModeNSFTSync_V5 sync;
+ RfTestResultListModeNSFTTrigger_V5 trigger;
+ RfTestResultListModeNSFTMeasure_V5 test;
+ RfTestResultListModeNSFTStop_V5 stop;
+}RfTestResultListModeNSFTReport_V5;
+
+typedef struct
+{
+ unsigned char cmd_type[60];
+ RfTestResultListModeNSFTReport_V5 report[60];
+}RfTestResultListModeNSFTParam_V5;
+#endif //#if IS_2G_RXD_SUPPORT
+// --------------------------------- //
+
+typedef enum
+{
+ RF_CNF_SUCCESS = 0, /**< access NVRAM successfully? */
+ RF_CNF_RECORD_STATUS_FAIL = 1, /**< access NVRAM general error? */
+ RF_CNF_NVRAM_GET_FAIL = 2, /**< GET NVRAM, NVRAM return failed */
+ RF_CNF_FREQ_INVALID = 3, /**< Error arfcn parameter for band*/
+ RF_CNF_CMD_INVALID = 4, /**< Error, SET CMD peer buffer is NULL*/
+ RF_CNF_NVRAM_SET_FAIL = 5, /**< SET NVRAM, NVRAM return failed */
+ RF_CNF_ALLOC_BUFFER_FAIL = 6 /**< Allocate peer buffer FAIL */
+}RF_NVRAM_ACCESS_CAl_DATA_RESULT;
+
+
+/* -------------------- *\
+|* SET TX CMD CNF Struct *|
+ \* -------------------- */
+typedef enum
+{
+ RF_TEST_SET_TX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_SET_TX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_SET_TX_DATA_TYPE2_OFFSET_ERROR = 2, // Type-2 count/offset mismatch
+ RF_TEST_SET_TX_DATA_TYPE3_OFFSET_ERROR = 3, // Type-3 count/offset mismatch
+ RF_TEST_SET_TX_DATA_TYPE4_OFFSET_ERROR = 4, // Type-4 count/offset mismatch
+ RF_TEST_SET_TX_DATA_EXCESS_REQ_PDU_LENGTH = 5,
+ RF_TEST_SET_TX_DATA_CNF_CHECK_OFFSET_PASS = 6,
+ RF_TEST_SET_TX_DATA_BITMAP_COUNT_MISMATCH = 7,
+ RF_TEST_SET_TX_DATA_NULL_PEER_BUF = 8,
+ RF_TEST_SET_TX_DATA_RECORD_SET_FAIL = 9,
+ RF_TEST_SET_TX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestSetTxData_Cnf_Status_E;
+
+typedef enum
+{
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_SET_TX_RUNTIME_DATA_STATUS_MAX,
+}RfTestSetTxData_RunTime_Status_E;
+
+typedef struct
+{
+ kal_uint16 count;
+ kal_uint16 bitmap; //add bitmap for tool team debug
+}RfTestSetTxDataCnfParamEntry_T; // Similar with RfTestParamDynamicEntryElm_T
+
+typedef struct
+{
+ RfTestSetTxData_Cnf_Status_E set_txdata_cnf_status;
+ RfTestSetTxDataCnfParamEntry_T type1_result;
+ RfTestSetTxDataCnfParamEntry_T type2_result;
+ RfTestSetTxDataCnfParamEntry_T type3_result;
+ RfTestSetTxDataCnfParamEntry_T type4_result;
+ RfTestSetTxData_RunTime_Status_E type1_ramptable_result[8];
+ RfTestSetTxData_RunTime_Status_E type2_epsk_interramptable_result[4];
+ RfTestSetTxData_RunTime_Status_E type3_txpc_result[2];
+ RfTestSetTxData_RunTime_Status_E type4_epskpa_result; //RFSpecialCoef.tx.orionRFtx.data...
+}RfTestCmdSetTxDataCnfParam;
+/* -------------------------------------- */
+
+
+/* -------------------- *\
+|* GET TX CMD CNF Struct *|
+ \* -------------------- */
+typedef enum
+{
+ RF_TEST_GET_TX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_GET_TX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_GET_TX_DATA_BITMAP_COUNT_MISMATCH = 2,
+ RF_TEST_GET_TX_DATA_OFFSET_MISMATCH = 3,
+ RF_TEST_GET_TX_DATA_NULL_PEER_BUF = 4,
+ RF_TEST_GET_TX_DATA_PEER_BUF_SIZE_OVERFLOW = 5,
+ RF_TEST_GET_TX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestGetTxData_Cnf_Status_E;
+
+//typedef struct
+//{
+// kal_uint16 count;
+// kal_uint16 offset;
+//}RfTestGetParamDynamicEntryElm_T;
+
+typedef enum
+{
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_GET_TX_RUNTIME_DATA_STATUS_MAX,
+}RfTestGetTxData_RunTime_Status_E;
+
+typedef struct
+{
+ RfTestGetTxData_Cnf_Status_E get_txdata_cnf_status;
+ RfTestParamDynamicEntryElm_T type1_ramptable_data;
+ RfTestParamDynamicEntryElm_T type2_epsk_interramptable_data;
+ RfTestParamDynamicEntryElm_T type3_txpc_data;
+ RfTestParamDynamicEntryElm_T type4_epskpa_data;
+ RfTestGetTxData_RunTime_Status_E type1_ramptable_result[8];
+ RfTestGetTxData_RunTime_Status_E type2_epsk_interramptable_result[4];
+ RfTestGetTxData_RunTime_Status_E type3_txpc_result[2];
+ RfTestGetTxData_RunTime_Status_E type4_epskpa_result; //RFSpecialCoef.tx.orionRFtx.data...
+}RfTestCmdGetTxDataCnfParam;
+
+typedef struct
+{
+ union
+ {
+ kal_int32 get_txdata_cnf_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_Ramptable_Type1_T type1_ramptable_pdu[8];
+ #if MD_DRV_IS_EPSK_TX_SUPPORT
+ L1_EPSK_InterRamptable_Type2_T type2_epsk_interramptable_pdu[4];
+ #endif
+ L1_Txpc_Type3_T type3_txpc_pdu[2];
+ L1_EpskPA_Type4_T type4_epskpa_pdu;
+ } confirm;
+}RfTestCmdGetTxDataCnfPdu;
+/* -------------------------------------- */
+
+
+
+/* -------------------- *\
+|* SET RX CMD CNF Struct *|
+ \* -------------------- */
+#if IS_2G_RXD_SUPPORT
+typedef enum
+{
+ RF_TEST_SET_RX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_SET_RX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_SET_RX_DATA_TYPE2_OFFSET_ERROR = 2, // Type-2 count/offset mismatch
+ RF_TEST_SET_RX_DATA_TYPE3_OFFSET_ERROR = 3, // Type-3 count/offset mismatch
+ RF_TEST_SET_RX_DATA_TYPE4_OFFSET_ERROR = 4, // Type-4 count/offset mismatch
+ RF_TEST_SET_RX_DATA_EXCESS_REQ_PDU_LENGTH = 5,
+ RF_TEST_SET_RX_DATA_CNF_CHECK_OFFSET_PASS = 6,
+ RF_TEST_SET_RX_DATA_BITMAP_COUNT_MISMATCH = 7,
+ RF_TEST_SET_RX_DATA_NULL_PEER_BUF = 8,
+ RF_TEST_SET_RX_DATA_RECORD_SET_FAIL = 9,
+ RF_TEST_SET_RX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestSetRxData_Cnf_Status_E;
+
+typedef enum
+{
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_SET_RX_RUNTIME_DATA_STATUS_MAX,
+}RfTestSetRxData_RunTime_Status_E;
+
+typedef struct
+{
+ kal_uint16 count;
+ kal_uint16 bitmap; //add bitmap for tool team debug
+}RfTestSetRxDataCnfParamEntry_T; // Similar with RfTestParamDynamicEntryElm_T
+
+typedef struct
+{
+ RfTestSetRxData_Cnf_Status_E set_rxdata_cnf_status;
+ RfTestSetRxDataCnfParamEntry_T type1_result;
+ RfTestSetRxDataCnfParamEntry_T type2_result;
+ RfTestSetRxData_RunTime_Status_E type1_rxpathloss_result[8];
+ RfTestSetRxData_RunTime_Status_E type2_wcoef_result[2];
+}RfTestCmdSetRxDataCnfParam;
+/* -------------------------------------- */
+
+
+/* -------------------- *\
+|* GET RX CMD CNF Struct *|
+ \* -------------------- */
+typedef enum
+{
+ RF_TEST_GET_RX_DATA_CNF_STATUS_INVALID = 0,
+ RF_TEST_GET_RX_DATA_CNF_STATUS_OK = 1,
+ RF_TEST_GET_RX_DATA_BITMAP_COUNT_MISMATCH = 2,
+ RF_TEST_GET_RX_DATA_OFFSET_MISMATCH = 3,
+ RF_TEST_GET_RX_DATA_NULL_PEER_BUF = 4,
+ RF_TEST_GET_RX_DATA_PEER_BUF_SIZE_OVERFLOW = 5,
+ RF_TEST_GET_RX_DATA_CNF_STATUS_MAX = 0xFFFF
+}RfTestGetRxData_Cnf_Status_E;
+
+//typedef struct
+//{
+// kal_uint16 count;
+// kal_uint16 offset;
+//}RfTestGetParamDynamicEntryElm_T;
+
+typedef enum
+{
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_INVALID = 0,
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_OK = 1, // set runtime success
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_BAND_NOT_SUPPORT = 2, // band mismatch with route
+ RF_TEST_GET_RX_RUNTIME_DATA_STATUS_MAX,
+}RfTestGetRxData_RunTime_Status_E;
+
+typedef struct
+{
+ RfTestGetRxData_Cnf_Status_E get_rxdata_cnf_status;
+ RfTestParamDynamicEntryElm_T type1_rxpathloss_data;
+ RfTestParamDynamicEntryElm_T type2_wcoef_data;
+ RfTestGetRxData_RunTime_Status_E type1_rxpathloss_result[8];
+ RfTestGetRxData_RunTime_Status_E type2_wcoef_result[2];
+}RfTestCmdGetRxDataCnfParam;
+
+typedef struct
+{
+ union
+ {
+ kal_int32 get_rxdata_req_pdu_raw_data[RF_MAX_PEER_BUF_CNF_WORD_SIZE];
+ L1_SetGetRxPathLossEntry_Type1_T type1_pathloss_pdu[8];
+ L1_Wcoef_Type2_T type2_wcoef_pdu[2];
+ } confirm;
+}RfTestCmdGetRxDataCnfPdu;
+#endif //#if IS_2G_RXD_SUPPORT
+/* -------------------------------------- */
+
+/*GET TPO CMD CNF struct*/
+typedef struct
+{
+ kal_bool ok;
+ kal_int16 power_apcdac_offset; // unit:DAC
+ kal_int16 power_dB_offset; // 0.125 dB
+} RfTestResultGetTPO;
+
+typedef union
+{
+ kal_bool ok;
+ kal_int8 m_i1RfPwrState_FT;
+ kal_int16 m_sBBPowerArrary[20]; /// META_Rf_QueryBBPowerList_r output
+ kal_uint8 nvramAccessResult; //RF_NVRAM_ACCESS_CAl_DATA_RESULT
+ kal_uint8 m_u1NSFTRxQual; /// L1TST_ReportRXQual output
+ kal_uint8 m_ucNumOfGainRf; /// META_Rf_QueryNumOfGainRf_r output
+ kal_uint16 m_u2NSFTRxLevel; /// L1TST_ReportRXLEV output
+ kal_uint16 temperature; /// L1TST_TXPC_GetTemperature output: RF_TEST_CMD_GET_TXPC_TEMPERATURE
+ kal_uint16 m_txpc_subband_compensation[11]; /// L1TST_TXPC_CL_GetSubband output
+ RF_DTS_GET_RESULT_STATUS dts_get_result_status;
+ RfGetAfcOffsetResult afc_result;
+ RfGetAfcDacValueAtRTXOffsetCal GetAfcDacValueAtRTXOffsetCal;
+ RfNSFTSBERResult m_rNSFTSBER;
+ RfTestResultPm pm;
+ RfTestResultAfc afc;
+ RfTestResultSinewaveAfcGetTempFreq afc_gpscoclockv2_result;
+ RfTestResultGetBSI GetBSI;
+ RfTestResultGetRFID rfid;
+ RfTestResultPDValue txpc_cnf;
+ RfTestResultGetBBTXCfg2 BBTxCfg2;
+ RfTestResultGetBBTXCfg3 BBTxCfg3;
+ RfTestResultGetBBTXCfg4 BBTxCfg4;
+ RfTestResultListModeNSFT List_Mode_NSFT_result;
+ RfTestResultMsCapability ms_capability;
+ RfTestResultMsCapabilityEx ms_capability_ex;
+ RfTestResult32kCalibration calibration_32k;
+ RfTestResultRfTemperatureInfo rfTemperatureInfo;
+ RfCheckIfFuncExist CheckIfFuncExist;
+ RfTestCmdSetTxDataCnfParam set_txdata_cnf;
+ RfTestCmdGetTxDataCnfParam get_txdata_cnf;
+ #if IS_2G_RXD_SUPPORT
+ kal_uint16 m_u2NSFTRxLevel_v5[GSM_RF_MAX_RX_ANT_NUM]; /// L1TST_ReportRXLEV output
+ RfTestResultPm_V5 pm_v5;
+ RfTestCmdSetRxDataCnfParam set_rxdata_cnf;
+ RfTestCmdGetRxDataCnfParam get_rxdata_cnf;
+ RfTestResultRxGainCalculate_V5 rx_gain_calculate_cnf;
+ #endif
+ RfTestResultGetTPO tpo_result;
+} RfTestResultParam;
+
+/*******************************************************************************
+*
+* Message structures defined for L1TST Interface
+*
+*******************************************************************************/
+typedef struct
+{
+ FT_HDR
+ RfTestCmdType type;
+ RfTestCmdParam param;
+} ft_rf_test_req_T;
+
+typedef struct
+{
+ FT_HDR
+ RfTestCmdType type;
+ RfTestResultParam param;
+} ft_rf_test_cnf_T;
+
+typedef ft_rf_test_req_T ft_to_gl1tst_struct;
+typedef ft_rf_test_cnf_T gl1tst_to_ft_struct;
+
+typedef ft_rf_test_req_T ft_rf_test_req_id_struct;
+typedef ft_rf_test_cnf_T ft_rf_test_cnf_id_struct;
+
+#endif /* _L1TST_FT_MSG_STRUCT_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg.h b/mcu/interface/l1/gl1/external/l1tst_msg.h
new file mode 100644
index 0000000..9cfbbd0
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg.h
@@ -0,0 +1,9 @@
+#if (defined __MD93__)
+#include "l1tst_msg_gen93.h"
+#elif (defined __MD95__)
+#include "l1tst_msg_gen95.h"
+#elif (defined __MD97__)||(defined __MD97P__)
+#include "l1tst_msg_gen97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg_common.h b/mcu/interface/l1/gl1/external/l1tst_msg_common.h
new file mode 100644
index 0000000..b07c73d
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg_common.h
@@ -0,0 +1,9 @@
+#if (defined __MD93__)
+#include "l1tst_msg_common_gen93.h"
+#elif (defined __MD95__)
+#include "l1tst_msg_common_gen95.h"
+#elif (defined __MD97__)||(defined __MD97P__)
+#include "l1tst_msg_common_gen97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg_common_gen93.h b/mcu/interface/l1/gl1/external/l1tst_msg_common_gen93.h
new file mode 100644
index 0000000..9763cf1
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg_common_gen93.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_msg_common.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Common definition of GL1TST task
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ * 01 29 2016 yungshian.lai
+ * [MOLY00163211] [L1TST] Sawless Development & DTS_STEP_CNT=512.
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_MSG_COMMON_H_
+#define _L1TST_MSG_COMMON_H_
+
+/*************************************************************************
+ * Include Statements for KAL
+ *************************************************************************/
+#include "kal_public_api.h"
+
+/*************************************************************************
+* Include Statements for FT
+ *************************************************************************/
+#include "ft_msg_common.h"
+
+/*************************************************************************
+* Global constant and data definition
+ *************************************************************************/
+#define GL1TST_CNF_OK 1
+#define GL1TST_CNF_FAIL 0
+
+/*************************************************************************
+ * Function declaration
+ *************************************************************************/
+void _GL1TST_ALLOC_MSG(ilm_struct* ptr_ilm, kal_uint16 size, kal_bool IsFtMsg);
+void _GL1TST_SendFtMsgByToken(module_type src_mod, module_type dest_mod, sap_type sap, msg_type msg, ilm_struct *ilm_ptr, kal_uint16 token);
+void _GL1TST_SendFtMsgToFtByToken(ilm_struct *ilm_ptr, kal_uint16 token);
+void _GL1TST_SendFtMsgToAddRecord(ilm_struct *ilm_ptr, kal_uint16 token);
+
+kal_uint16 GL1TST_GetGolbalToken( void );
+
+/*************************************************************************
+* Utility Functions
+ *************************************************************************/
+#define GL1TST_ALLOC_MSG(ptr_ilm,size) _GL1TST_ALLOC_MSG(ptr_ilm, size, KAL_TRUE)
+#define GL1TST_ALLOC_OTHER_MSG(ptr_ilm,size) _GL1TST_ALLOC_MSG(ptr_ilm, size, KAL_FALSE)
+
+//#define GL1TST_SEND_MSG(src_mod, dest_mod, sap, msg, ilm_ptr) _GL1TST_SendFtMsgByToken(src_mod, dest_mod, sap, msg, ilm_ptr, GL1TST_GetGolbalToken())
+#define GL1TST_SEND_MSG_TO_FT(ilm_ptr) _GL1TST_SendFtMsgToFtByToken(ilm_ptr, GL1TST_GetGolbalToken())
+
+#endif /* _L1TST_MSG_COMMON_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg_common_gen95.h b/mcu/interface/l1/gl1/external/l1tst_msg_common_gen95.h
new file mode 100644
index 0000000..9763cf1
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg_common_gen95.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_msg_common.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Common definition of GL1TST task
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ * 01 29 2016 yungshian.lai
+ * [MOLY00163211] [L1TST] Sawless Development & DTS_STEP_CNT=512.
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_MSG_COMMON_H_
+#define _L1TST_MSG_COMMON_H_
+
+/*************************************************************************
+ * Include Statements for KAL
+ *************************************************************************/
+#include "kal_public_api.h"
+
+/*************************************************************************
+* Include Statements for FT
+ *************************************************************************/
+#include "ft_msg_common.h"
+
+/*************************************************************************
+* Global constant and data definition
+ *************************************************************************/
+#define GL1TST_CNF_OK 1
+#define GL1TST_CNF_FAIL 0
+
+/*************************************************************************
+ * Function declaration
+ *************************************************************************/
+void _GL1TST_ALLOC_MSG(ilm_struct* ptr_ilm, kal_uint16 size, kal_bool IsFtMsg);
+void _GL1TST_SendFtMsgByToken(module_type src_mod, module_type dest_mod, sap_type sap, msg_type msg, ilm_struct *ilm_ptr, kal_uint16 token);
+void _GL1TST_SendFtMsgToFtByToken(ilm_struct *ilm_ptr, kal_uint16 token);
+void _GL1TST_SendFtMsgToAddRecord(ilm_struct *ilm_ptr, kal_uint16 token);
+
+kal_uint16 GL1TST_GetGolbalToken( void );
+
+/*************************************************************************
+* Utility Functions
+ *************************************************************************/
+#define GL1TST_ALLOC_MSG(ptr_ilm,size) _GL1TST_ALLOC_MSG(ptr_ilm, size, KAL_TRUE)
+#define GL1TST_ALLOC_OTHER_MSG(ptr_ilm,size) _GL1TST_ALLOC_MSG(ptr_ilm, size, KAL_FALSE)
+
+//#define GL1TST_SEND_MSG(src_mod, dest_mod, sap, msg, ilm_ptr) _GL1TST_SendFtMsgByToken(src_mod, dest_mod, sap, msg, ilm_ptr, GL1TST_GetGolbalToken())
+#define GL1TST_SEND_MSG_TO_FT(ilm_ptr) _GL1TST_SendFtMsgToFtByToken(ilm_ptr, GL1TST_GetGolbalToken())
+
+#endif /* _L1TST_MSG_COMMON_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg_common_gen97.h b/mcu/interface/l1/gl1/external/l1tst_msg_common_gen97.h
new file mode 100644
index 0000000..9763cf1
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg_common_gen97.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_msg_common.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Common definition of GL1TST task
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ * 01 29 2016 yungshian.lai
+ * [MOLY00163211] [L1TST] Sawless Development & DTS_STEP_CNT=512.
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_MSG_COMMON_H_
+#define _L1TST_MSG_COMMON_H_
+
+/*************************************************************************
+ * Include Statements for KAL
+ *************************************************************************/
+#include "kal_public_api.h"
+
+/*************************************************************************
+* Include Statements for FT
+ *************************************************************************/
+#include "ft_msg_common.h"
+
+/*************************************************************************
+* Global constant and data definition
+ *************************************************************************/
+#define GL1TST_CNF_OK 1
+#define GL1TST_CNF_FAIL 0
+
+/*************************************************************************
+ * Function declaration
+ *************************************************************************/
+void _GL1TST_ALLOC_MSG(ilm_struct* ptr_ilm, kal_uint16 size, kal_bool IsFtMsg);
+void _GL1TST_SendFtMsgByToken(module_type src_mod, module_type dest_mod, sap_type sap, msg_type msg, ilm_struct *ilm_ptr, kal_uint16 token);
+void _GL1TST_SendFtMsgToFtByToken(ilm_struct *ilm_ptr, kal_uint16 token);
+void _GL1TST_SendFtMsgToAddRecord(ilm_struct *ilm_ptr, kal_uint16 token);
+
+kal_uint16 GL1TST_GetGolbalToken( void );
+
+/*************************************************************************
+* Utility Functions
+ *************************************************************************/
+#define GL1TST_ALLOC_MSG(ptr_ilm,size) _GL1TST_ALLOC_MSG(ptr_ilm, size, KAL_TRUE)
+#define GL1TST_ALLOC_OTHER_MSG(ptr_ilm,size) _GL1TST_ALLOC_MSG(ptr_ilm, size, KAL_FALSE)
+
+//#define GL1TST_SEND_MSG(src_mod, dest_mod, sap, msg, ilm_ptr) _GL1TST_SendFtMsgByToken(src_mod, dest_mod, sap, msg, ilm_ptr, GL1TST_GetGolbalToken())
+#define GL1TST_SEND_MSG_TO_FT(ilm_ptr) _GL1TST_SendFtMsgToFtByToken(ilm_ptr, GL1TST_GetGolbalToken())
+
+#endif /* _L1TST_MSG_COMMON_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg_gen93.h b/mcu/interface/l1/gl1/external/l1tst_msg_gen93.h
new file mode 100644
index 0000000..4325ab2
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg_gen93.h
@@ -0,0 +1,70 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_msg.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Messages definition of GL1TST task
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_MSG_H_
+#define _L1TST_MSG_H_
+
+/*************************************************************************
+* Include Statements for GL1TST
+ *************************************************************************/
+#include "l1tst_msg_common.h"
+#include "l1tst_msg_l1rf.h"
+
+#endif /* _L1TST_MSG_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg_gen95.h b/mcu/interface/l1/gl1/external/l1tst_msg_gen95.h
new file mode 100644
index 0000000..4325ab2
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg_gen95.h
@@ -0,0 +1,70 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_msg.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Messages definition of GL1TST task
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_MSG_H_
+#define _L1TST_MSG_H_
+
+/*************************************************************************
+* Include Statements for GL1TST
+ *************************************************************************/
+#include "l1tst_msg_common.h"
+#include "l1tst_msg_l1rf.h"
+
+#endif /* _L1TST_MSG_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg_gen97.h b/mcu/interface/l1/gl1/external/l1tst_msg_gen97.h
new file mode 100644
index 0000000..4325ab2
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg_gen97.h
@@ -0,0 +1,70 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_msg.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Messages definition of GL1TST task
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_MSG_H_
+#define _L1TST_MSG_H_
+
+/*************************************************************************
+* Include Statements for GL1TST
+ *************************************************************************/
+#include "l1tst_msg_common.h"
+#include "l1tst_msg_l1rf.h"
+
+#endif /* _L1TST_MSG_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg_l1rf.h b/mcu/interface/l1/gl1/external/l1tst_msg_l1rf.h
new file mode 100644
index 0000000..76dabaf
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg_l1rf.h
@@ -0,0 +1,9 @@
+#if (defined __MD93__)
+#include "l1tst_msg_l1rf_gen93.h"
+#elif (defined __MD95__)
+#include "l1tst_msg_l1rf_gen95.h"
+#elif (defined __MD97__)||(defined __MD97P__)
+#include "l1tst_msg_l1rf_gen97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg_l1rf_gen93.h b/mcu/interface/l1/gl1/external/l1tst_msg_l1rf_gen93.h
new file mode 100644
index 0000000..10a8cba
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg_l1rf_gen93.h
@@ -0,0 +1,85 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_msg_l1rf.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Messages definition of L1RF category of GL1TST task
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ * 04 20 2015 samuel.yang
+ * [MOLY00108029] [TK6291] META mode related modifications
+ * .
+ *
+ * 01 03 2014 th.yeh
+ * [MOLY00052308] [L1D][Modify] FT/L1D dual-core modem interface development
+ * .
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_MSG_L1RF_H_
+#define _L1TST_MSG_L1RF_H_
+
+/*************************************************************************
+* Include Statements for GL1TST
+ *************************************************************************/
+#include "l1tst_msg_common.h"
+
+/*************************************************************************
+* Include Statements for GL1
+ *************************************************************************/
+#include "mph_types.h"
+#include "l1tst_public.h"
+#include "l1cal.h"
+#include "l1_option.h" // L1 compile option header
+#include "l1tst_ft_msg_struct.h"
+#endif /* _L1TST_MSG_L1RF_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg_l1rf_gen95.h b/mcu/interface/l1/gl1/external/l1tst_msg_l1rf_gen95.h
new file mode 100644
index 0000000..10a8cba
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg_l1rf_gen95.h
@@ -0,0 +1,85 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_msg_l1rf.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Messages definition of L1RF category of GL1TST task
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ * 04 20 2015 samuel.yang
+ * [MOLY00108029] [TK6291] META mode related modifications
+ * .
+ *
+ * 01 03 2014 th.yeh
+ * [MOLY00052308] [L1D][Modify] FT/L1D dual-core modem interface development
+ * .
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_MSG_L1RF_H_
+#define _L1TST_MSG_L1RF_H_
+
+/*************************************************************************
+* Include Statements for GL1TST
+ *************************************************************************/
+#include "l1tst_msg_common.h"
+
+/*************************************************************************
+* Include Statements for GL1
+ *************************************************************************/
+#include "mph_types.h"
+#include "l1tst_public.h"
+#include "l1cal.h"
+#include "l1_option.h" // L1 compile option header
+#include "l1tst_ft_msg_struct.h"
+#endif /* _L1TST_MSG_L1RF_H_ */
diff --git a/mcu/interface/l1/gl1/external/l1tst_msg_l1rf_gen97.h b/mcu/interface/l1/gl1/external/l1tst_msg_l1rf_gen97.h
new file mode 100644
index 0000000..10a8cba
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1tst_msg_l1rf_gen97.h
@@ -0,0 +1,85 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1tst_msg_l1rf.h
+ *
+ * Project:
+ * --------
+ * MT6291
+ *
+ * Description:
+ * ------------
+ * Messages definition of L1RF category of GL1TST task
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ * $Revision: $
+ * $Modtime: $
+ * $Log: $
+ *
+ * 04 20 2015 samuel.yang
+ * [MOLY00108029] [TK6291] META mode related modifications
+ * .
+ *
+ * 01 03 2014 th.yeh
+ * [MOLY00052308] [L1D][Modify] FT/L1D dual-core modem interface development
+ * .
+ *
+ *******************************************************************************/
+
+#ifndef _L1TST_MSG_L1RF_H_
+#define _L1TST_MSG_L1RF_H_
+
+/*************************************************************************
+* Include Statements for GL1TST
+ *************************************************************************/
+#include "l1tst_msg_common.h"
+
+/*************************************************************************
+* Include Statements for GL1
+ *************************************************************************/
+#include "mph_types.h"
+#include "l1tst_public.h"
+#include "l1cal.h"
+#include "l1_option.h" // L1 compile option header
+#include "l1tst_ft_msg_struct.h"
+#endif /* _L1TST_MSG_L1RF_H_ */
diff --git a/mcu/interface/l1/gl1/external/m12190_pcore.h b/mcu/interface/l1/gl1/external/m12190_pcore.h
new file mode 100644
index 0000000..002e73a
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/m12190_pcore.h
@@ -0,0 +1,146 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * m12190_pcore.h
+ *
+ * Project:
+ * --------
+ * TK6291
+ *
+ * Description:
+ * ------------
+ * Setup RF
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *******************************************************************************/
+
+
+#ifndef _M12190_PCORE_H_
+#define _M12190_PCORE_H_
+/*---------------------------------------------------------------------------*/
+#include "l1_types_public.h"
+#include "l1cal.h"
+#include "l1d_rf_common.h"
+#include "l1d_public.h"
+#include "l1d_custom_drdi.h"
+#if IS_GEN95_L1D_CUSTOM_DYNAMIC_SUPPORT
+#else
+#include "l1d_custom_rf.h"
+#endif
+
+typedef enum
+{
+ BandSupportFromDefaultCustom,
+ BandSupportFromPcoreNvram,
+ BandSupportFromNull
+} BandSupportSource;
+
+void L1D_RF_GetAFCData( void *data_buffer );
+
+#if IS_TXPC_CL_AUXADC_SUPPORT || IS_TXPC_CL_BSI_SUPPORT
+#define L1D_RF_TXPC_CL_GET_ALL_ADC( buff, is_EPSK ) \
+{ L1D_RF_TXPC_CL_GetAllADC( buff, is_EPSK ); \
+}
+
+#define L1D_RF_TXPC_CL_GET_ALL_TEMP( buff, is_EPSK ) \
+{ L1D_RF_TXPC_CL_GetAllTEMP( buff, is_EPSK ); \
+}
+#else
+#define L1D_RF_TXPC_CL_GET_ALL_ADC( buff, is_EPSK ) {;}
+#define L1D_RF_TXPC_CL_GET_ALL_TEMP( buff, is_EPSK ) {;}
+#endif
+
+#if IS_TXPC_OL_BSI_SUPPORT || IS_TXPC_OL_AUXADC_SUPPORT
+#define L1D_RF_TXPC_OL_GET_TEMPERATURE( buff ) \
+{ (buff)->temperature = ref_temperature; \
+}
+#else
+#define L1D_RF_TXPC_OL_GET_TEMPERATURE( buff ) {;}
+#endif
+
+#if IS_TX_POWER_CONTROL_SUPPORT
+#define L1D_RF_TXPC_GET_FLAG( buff ) \
+{ (buff)->is_calibrated = is_txpc_calibrated; \
+}
+#else
+#define L1D_RF_TXPC_GET_FLAG( buff ) {;}
+#endif
+
+#if IS_TX_GAIN_RF_CALIBRATION_SUPPORT
+void L1D_RF_GetGainRF( l1cal_gainrf_T *buff );
+#endif
+
+void L1D_PcoreNvramUpdate2SHM( kal_uint32 );
+
+#if IS_RX_POWER_OFFSET_SUPPORT
+void L1D_RF_SetPathLoss_Offset_Table_Pcore( int rf_band, void *table );
+#endif/*IS_RX_POWER_OFFSET_SUPPORT*/
+#endif /*End of _M12190_PCORE_H_ */
diff --git a/mcu/interface/l1/gl1/external/mph_types.h b/mcu/interface/l1/gl1/external/mph_types.h
new file mode 100644
index 0000000..b162848
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/mph_types.h
@@ -0,0 +1,503 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mph_types.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Common constant and enum definitions for MediaTek GSM/GPRS software
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _MPH_TYPES_H
+#define _MPH_TYPES_H
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+#include "l1_gemini_def.h"
+
+/* define multi mode option for GL1 only */
+#if defined(__UMTS_RAT__) || defined(__LTE_RAT__)
+#define __GL1_MULTI_MODE__
+#endif /* __UMTS_RAT__ || __LTE_RAT__ */
+#if defined(__PS_L1_DC_ARCH__)
+/* to support dual-core modem architecture */
+#define IS_DUAL_CORE_GL1AC_MODEM_SUPPORT 1
+#else
+#define IS_DUAL_CORE_GL1AC_MODEM_SUPPORT 0
+#endif /* defined(__PS_L1_DC_ARCH__) */
+
+#if defined (__CSFB_WITH_SGLTE_HW__) && defined (__UMTS_TDD128_MODE__)
+#define __SGTDS_STANDBY_AFC_TRACKING__
+#endif
+#define GSM_DATA_LEN_PER_BLK 23
+#if IS_FANR_EDGE_SUPPORT
+#define PACKET_DATA_LEN_PER_BLK 164
+#else
+#define PACKET_DATA_LEN_PER_BLK 160
+#endif
+// CSD non-transparent mode may use up to 72 - 3 bytes
+#define MAX_CSD_DATA_LEN_PER_BLK 69
+#define __GL1_QUICK_MCC_SEARCH__
+
+#if defined( __MTK_TARGET__ ) && !defined( __FPGA__ )
+#define GL1C_PROFILE_ENABLE 1
+#else
+#define GL1C_PROFILE_ENABLE 0
+#endif
+
+/*
+ * Definitions for GSM related types
+ */
+typedef kal_int16 ARFCN;
+typedef kal_int8 BSIC;
+typedef kal_int8 TSC;
+typedef kal_int8 TimeSlot; /* Timeslot Number */
+typedef kal_uint8 TimeSlotMask; /* Timeslot Mask */
+typedef kal_int8 SubChannel;
+typedef kal_int16 Power; /* in dBm */
+typedef kal_uint8 RxlevPower; /* in Rxlev */
+typedef kal_uint8 TimingAdvance;
+typedef kal_int32 FrameNumber;
+typedef kal_uint16 RAChData;
+
+typedef kal_int8 TFI;
+typedef kal_int8 PowerControlLevel;
+typedef kal_int16 PowerSum;
+typedef kal_uint8 BlockData;
+typedef kal_int8 LoopMode;
+typedef kal_int8 USF;
+
+typedef enum
+{
+ BTSPowerControlModeNoPowerControl,
+ BTSPowerControlModeA,
+ BTSPowerControlModeB
+} BTSPowerControlMode;
+
+typedef enum
+{
+ CodingSchemeNone,
+ CodingSchemeCS1,
+ CodingSchemeCS2,
+ CodingSchemeCS3,
+ CodingSchemeCS4,
+ #ifdef __EGPRS_MODE__
+ #ifdef __GERAN_RTTI__
+ CodingSchemeMCS0,
+ #endif /* end of __GERAN_RTTI__ */
+ CodingSchemeMCS1,
+ CodingSchemeMCS2,
+ CodingSchemeMCS3,
+ CodingSchemeMCS4,
+ CodingSchemeMCS5,
+ CodingSchemeMCS6,
+ CodingSchemeMCS7,
+ CodingSchemeMCS8,
+ CodingSchemeMCS9,
+ #endif
+ CodingSchemePRACh8,
+ CodingSchemePRACh11
+} CodingScheme;
+
+typedef enum
+{
+ PuncturingSchemeNone,
+ PuncturingScheme1,
+ PuncturingScheme2,
+ PuncturingScheme3
+} PuncturingScheme;
+
+
+typedef enum
+{
+ PBCChModeNone,
+ PBCChModeAll,
+ PBCChModePSI1Only,
+ PBCChModeHROnly,
+ PBCChModeLROnly,
+ PBCChModePSI1HR,
+ PBCChModePSI1LR,
+ PBCChModeHRLR,
+ PBCChModeB0OnTC0Only
+} PBCChMode;
+
+/*
+@enum LogChannel | DCh channel type.
+*/
+typedef enum
+{
+ LogTChF, /* @emem Full rate trafic channel */
+ LogTChH, /* @emem Half rate trafic channel*/
+ LogSDCCh4, /* @emem Standalone dedicated control channel combined */
+ LogSDCCh8 /* @emem Standalone dedicated control channel uncombined */
+} LogChannel;
+
+/*
+@enum TChMode | TCh channel mode.
+*/
+typedef enum
+{
+ TChModeNone, /* @emem Undefined channel mode */
+ TChModeFSig, /* @emem Full rate singnalling only */
+ TChModeFS, /* @emem Full rate speech */
+ TChModeF144, /* @emem Full rate data 14400 */
+ TChModeF96, /* @emem Full rate data 9600 */
+ TChModeF48, /* @emem Full rate data 4800 */
+ TChModeF24, /* @emem Full rate data 2400 */
+
+/* TODO maybe get rid of these because they are redundant */
+ TChModeHSig, /* @emem Half rate singnalling only */
+ TChModeHS, /* @emem Half rate speech */
+ TChModeH48, /* @emem Half rate data 4800 */
+ TChModeH24, /* @emem Half rate data 2400 */
+ TChModeEFS, /* Enhanced full rate speech */
+
+/* AMR speech modes used by RR, L1A and L1C. */
+ TChModeAFS, /* @emem AMR Full rate speech */
+ TChModeAHS, /* @emem AMR Half rate speech */
+ TChModeAFS_WB, /* @emem AMR-WB Full rate speech */
+
+/* VAMOS tch modes */
+ TChModeFS_VAMOS,
+ TChModeHS_VAMOS,
+ TChModeEFS_VAMOS,
+ TChModeAFS_VAMOS,
+ TChModeAHS_VAMOS,
+ TChModeAFS_WB_VAMOS,
+
+/* AMR speech modes used by L1D. */
+ TChModeAFS1220, /* @emem AMR Full rate speech 12.2k */
+ TChModeAFS1020, /* @emem AMR Full rate speech 10.2k */
+ TChModeAFS795, /* @emem AMR Full rate speech 7.95k */
+ TChModeAFS740, /* @emem AMR Full rate speech 7.4k */
+ TChModeAFS670, /* @emem AMR Full rate speech 6.7k */
+ TChModeAFS590, /* @emem AMR Full rate speech 5.9k */
+ TChModeAFS515, /* @emem AMR Full rate speech 5.15k */
+ TChModeAFS475, /* @emem AMR Full rate speech 4.75k */
+
+ TChModeAHS795, /* @emem AMR Half rate speech 7.95k */
+ TChModeAHS740, /* @emem AMR Half rate speech 7.4k */
+ TChModeAHS670, /* @emem AMR Half rate speech 6.7k */
+ TChModeAHS590, /* @emem AMR Half rate speech 5.9k */
+ TChModeAHS515, /* @emem AMR Half rate speech 5.15k */
+ TChModeAHS475, /* @emem AMR Half rate speech 4.75k */
+
+ TChModeAFS_WB1265, /* @emem AMR-WB Full rate speech 12.65k */
+ TChModeAFS_WB885, /* @emem AMR-WB Full rate speech 8.85k */
+ TChModeAFS_WB660 /* @emem AMR-WB Full rate speech 6.6k */
+} TChMode;
+
+
+/*Shihyao 20090601, add for callback function to indicate the module id*/
+/*Rick 20111028 Modify for smart paging in idle mode*/
+typedef enum
+{
+ RR_L1A_1
+#if defined(__GL1_GEMINI__)
+ ,RR_L1A_2
+#if (GL1_GEMINI_NUM >= 3)
+ ,RR_L1A_3
+#endif
+#if (GL1_GEMINI_NUM >= 4)
+ ,RR_L1A_4
+#endif
+#endif /* __GL1_GEMINI__ */
+} module_id_enum;
+
+/* For 3G Gemini2.0+ */
+typedef enum
+{
+ MPAL_GL1_QUERY_RRBP,
+ MPAL_GL1_QUERY_RRBP_AND_PROTECT_PDTCH
+} mpal_gl1_query_priority_enum;
+
+#ifdef __EGPRS_MODE__
+typedef struct
+{
+ CodingScheme codingScheme;
+ BlockData* header;
+ BlockData* blockData;
+ BlockData* blockData2;
+ PuncturingScheme puncturingScheme_1; // for the 1st RLC block in the radio block, no use in CS1~4
+ PuncturingScheme puncturingScheme_2; // for the 2nd RLC block in the radio block, no use in CS1~4
+} PrePacketBlockSpec;
+#else
+typedef struct
+{
+ CodingScheme codingScheme;
+ BlockData* blockData;
+} PrePacketBlockSpec;
+#endif
+
+typedef struct
+{
+ PrePacketBlockSpec block[4];
+} PrePacketUplinkSpec;
+
+/* elly20070709, Add a structure for INJECT message */
+typedef struct
+{
+ kal_bool l1_no_service_test;
+ kal_bool l1_standby_gsm_meas_test;
+ kal_bool l1_standby_gsm_bsic_req_test;
+ kal_bool standby_gsm_report_cgi_pwrscan_test;
+ kal_bool standby_gsm_report_cgi_bsic_test;
+ kal_bool standby_gsm_report_cgi_sys_info_test;
+ kal_bool l1_auto_gap_test;
+ kal_bool auto_gap_start_cnf;
+ kal_bool auto_gap_stop_cnf;
+
+ // for store cgi info.
+ kal_bool cgi_bsic_known;
+ BSIC cgi_bsic;
+ FrameNumber cgi_frame_offset;
+ kal_int32 cgi_ebit_offset;
+} L1InjectMessage;
+
+typedef enum
+{
+ Normal = 0,
+ IgnoreUSF, /* The last PDTCh for G to G handover */
+ NoUplinkCB, /* The last PDTCh for G to W handover */
+ Conflict
+} ReportPDTChType;
+#if IS_DUAL_CORE_GL1AC_MODEM_SUPPORT
+
+#define MOBILE_IDENTITY_IEI 0x17
+
+typedef enum
+{
+ L1_PAGING_REQ_1_MSG_TYPE = 0x21, /* 0x21 */
+ L1_PAGING_REQ_2_MSG_TYPE, /* 0x22 */
+ L1_PDCH_ASSGN_MSG_TYPE, /* 0x23 */
+ L1_PAGING_REQ_3_MSG_TYPE, /* 0x24 */
+ L1_IMM_ASSGN_MSG_TYPE = 0x3f, /* 0x3f */
+} l1_peer_msg_type;
+
+
+typedef enum
+{
+ L1_MSG_DECODE_SUCCESS,
+ L1_NO_ERROR,
+ L1_IGNORE_MSG,
+ L1_UNKNOWN_MSG_IN_ACK,
+ L1_MSG_IN_INCOMPATIBLE_STATE,
+ L1_SYNT_INCORRECT_MSG
+} l1_gsm_ret_code;
+
+typedef enum
+{
+ S_L1_IMSI_TYPE = 1,
+ S_L1_PTMSI_TYPE = 4,
+ S_L1_TMSI_TYPE = 5,
+ S_L1_INVALID_ID_TYPE = 0xFF
+} l1_mob_id_enum;
+
+typedef struct {
+ kal_uint8 length; /* LENGTH*/
+ kal_uint8 digit0; /* DIGIT 0*/
+ kal_uint8 odd_or_even; /* ODD OR EVEN*/
+ kal_uint8 identity_type; /* IDENTITY TYPE*/
+ kal_uint8 digit_byte[7];
+} l1_imsi_struct;
+
+typedef struct{
+kal_bool is_imsi_present;
+l1_imsi_struct imsi; // L3_inc_struct.h
+kal_bool is_tmsi_present;
+kal_uint8 tmsi[4];
+kal_bool is_ptmsi_present;
+kal_uint8 ptmsi[4];
+} l1_ms_identity_struct;
+
+#endif /* IS_DUAL_CORE_GL1AC_MODEM_SUPPORT */
+#endif
+