[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/gl1/external/l1d_cid.h b/mcu/interface/l1/gl1/external/l1d_cid.h
new file mode 100644
index 0000000..975258c
--- /dev/null
+++ b/mcu/interface/l1/gl1/external/l1d_cid.h
@@ -0,0 +1,7059 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * l1d_cid.h
+ *
+ * Project:
+ * --------
+ * MT6208
+ *
+ * Description:
+ * ------------
+ * Compile option definitoin
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
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+ *******************************************************************************/
+
+#ifndef _L1D_CID_H_
+#define _L1D_CID_H_
+
+/*===================================================================*/
+/* UMOLY Build Error Bypass before New Feature Ready. */
+/*===================================================================*/
+
+#define IS_TK6291_BYPASS_BUILD_ERR_DRDI 1
+
+
+/*===============================================================================================*/
+
+/*------------------------------------------*/
+/* Compile Option : */
+/* (1) MODE_GSM */
+/* (2) MODE_GPRS */
+/* (3) MODE_EGPRS */
+/* ------------- */
+/* (*) MTK_EGPRS_ENABLE */
+/* (*) __EGPRS_MODE__ */
+/* (*) MTK_GPRS_ENABLE */
+/* (*) __PS_SERVICE__ */
+/* (*) GPRS==1 */
+/*------------------------------------------*/
+/* Use in L1D : */
+/* (1) IS_GSM */
+/* (2) IS_GPRS */
+/* (3) IS_EGPRS */
+/*------------------------------------------*/
+
+#define MODE_ID_GSM 0x0001
+#define MODE_ID_GPRS 0x0002
+#define MODE_ID_EGPRS 0x0004
+
+#ifdef MODE_GSM
+#define MODE_ID MODE_ID_GSM
+#endif
+#ifdef MODE_GPRS
+#define MODE_ID MODE_ID_GPRS
+#endif
+#ifdef MODE_EGPRS
+#define MODE_ID MODE_ID_EGPRS
+#endif
+
+#define IS_GSM (MODE_ID==MODE_ID_GSM )
+#define IS_GPRS ((MODE_ID==MODE_ID_GPRS) || (MODE_ID==MODE_ID_EGPRS))
+#define IS_EGPRS (MODE_ID==MODE_ID_EGPRS)
+/*.......................................................*/
+
+#ifndef MODE_ID
+ #ifdef __EGPRS_MODE__
+/*EGPRS*/ #define MODE_ID MODE_ID_EGPRS
+ #endif
+#endif
+
+#ifndef MODE_ID
+ #ifdef MTK_EGPRS_ENABLE
+/*EGPRS*/ #define MODE_ID MODE_ID_EGPRS
+ #endif
+#endif
+
+#ifndef MODE_ID
+ #ifdef __PS_SERVICE__
+/*GPRS*/ #define MODE_ID MODE_ID_GPRS
+ #endif
+#endif
+
+#ifndef MODE_ID
+ #ifdef MTK_GPRS_ENABLE
+/*GPRS*/ #define MODE_ID MODE_ID_GPRS
+ #endif
+#endif
+
+#ifndef MODE_ID
+ #ifdef GPRS
+ #if GPRS==1
+/*GPRS*/ #define MODE_ID MODE_ID_GPRS
+ #else
+/*GSM*/ #define MODE_ID MODE_ID_GSM
+ #endif
+ #endif
+#endif
+
+/* default setting */
+#ifndef MODE_ID
+/*GSM*/ #define MODE_ID MODE_ID_GSM
+#endif
+/*===============================================================================================*/
+
+/*---------------------------------------------------*/
+/* Compile Option : */
+/* (1) FPGA */
+/* (2) CHIP_MT6208 */
+/* (3) CHIP_MT6205 (A) */
+/* (4) CHIP_MT6205B (B) */
+/* (5) CHIP_MT6218 (A) */
+/* (6) CHIP_MT6218B (B) */
+/* (7) CHIP_MT6219 */
+/* (8) CHIP_MT6217 */
+/* (9) CHIP_MT6227 */
+/* (10)CHIP_MT6228 */
+/* (11)CHIP_MT6229 */
+/* (12)CHIP_MT6225 */
+/* (13)CHIP_MT6223 */
+/* (14)CHIP_MT6238 */
+/* --------------- */
+/* (*) CHIP_TARGET */
+/*---------------------------------------------------*/
+/* Use in L1D : */
+/* (1) IS_FPGA_TARGET */
+/* (2) IS_CHIP_TARGET */
+/* (3) IS_CHIP_MT6208 */
+/* (4) IS_CHIP_MT6205A */
+/* (5) IS_CHIP_MT6205B */
+/* (6) IS_CHIP_MT6205 (A/B) */
+/* (7) IS_CHIP_MT6218A */
+/* (8) IS_CHIP_MT6218B */
+/* (9) IS_CHIP_MT6218 */
+/* (10)IS_CHIP_MT6219 */
+/* (11)IS_CHIP_MT6228 */
+/* (12)IS_CHIP_MT6229 */
+/* (13)IS_CHIP_MT6227 */
+/* (14)IS_CHIP_MT6208_AND_LATTER_VERSION */
+/* (15)IS_CHIP_MT6205_AND_LATTER_VERSION (A/B) */
+/* (16)IS_CHIP_MT6205A_AND_LATTER_VERSION (A/B) */
+/* (17)IS_CHIP_MT6205B_AND_LATTER_VERSION */
+/* (18)IS_CHIP_MT6218_AND_LATTER_VERSION (A/B) */
+/* (19)IS_CHIP_MT6218A_AND_LATTER_VERSION (A/B) */
+/* (20)IS_CHIP_MT6218B_AND_LATTER_VERSION */
+/* (21)IS_CHIP_MT6219_AND_LATTER_VERSION */
+/* (22)IS_CHIP_MT6228_AND_LATTER_VERSION */
+/* (23)IS_CHIP_MT6227_AND_LATTER_VERSION */
+/* (24)IS_CHIP_MT6218B_AN2DN */
+/* (25)IS_CHIP_MT6218B_EN */
+/* (26)IS_CHIP_MT6218B_FN */
+/* (27)IS_CHIP_MT6219_AV */
+/* (28)IS_CHIP_MT6219_BV */
+/* (29)IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION */
+/* (30)IS_CHIP_MT6225 */
+/* (31)IS_CHIP_MT6225_AND_LATTER_VERSION */
+/* (32)IS_CHIP_MT6223 */
+/* (33)IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION */
+/* (34)IS_CHIP_MT6238 */
+/* (35)IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION */
+/*---------------------------------------------------*/
+
+#define CHIP_ID_FPGA 0x00000000
+
+/* Divide chips into Series+Number */
+
+#define CHIP_SER(ID) (0xFFFFFF00&ID)
+#define CHIP_NUM(ID) (0x000000FF&ID)
+
+/*---------------------*/
+/* For GSM/GPRS Group */
+/*---------------------*/
+/* GSM */ /* 0x00000100+number */
+#define CHIP_ID_MT6208 0x00000101 //0x00000001
+#define CHIP_ID_MT6205A 0x00000102 //0x00000002
+#define CHIP_ID_MT6205B 0x00000103 //0x00000004
+/* GPRS */ /* 0x00000200+number */
+#define CHIP_ID_MT6218A 0x00000201 //0x00000008
+#define CHIP_ID_MT6218B 0x00000202 //0x00000010
+#define CHIP_ID_MT6219 0x00000203 //0x00000020
+/* AMR */ /* 0x00000400+number */
+#define CHIP_ID_MT6227 0x00000401 //0x00000100
+#define CHIP_ID_MT6228 0x00000402 //0x00000040
+#define CHIP_ID_MT6225 0x00000403 //0x00000200
+
+/*----------------------------------*/
+/* For Dual DSP Group (EGPRS Group) */
+/*----------------------------------*/
+/* EDGE */ /* 0x00000800+number */
+#define CHIP_ID_MT6229 0x00000801 //0x00000080
+#define CHIP_ID_MT6268T 0x00000802 //0x00000400
+/* GPRS SAIC */ /* 0x00001000+number */
+#define CHIP_ID_MT6223 0x00001001 //0x00000800
+/* EDGE SAIC */ /* 0x00002000+number */
+#define CHIP_ID_MT6235 0x00002001 //0x00001000
+#define CHIP_ID_MT6238 0x00002002 //0x00002000
+#define CHIP_ID_TK6516 0x00002003 //0x00004000
+#define CHIP_ID_MT6268A 0x00002004 //0x00008000
+#define CHIP_ID_MT6516 0x00002005 //0x00010000
+#define CHIP_ID_MT6268 0x00002006 //0x00040000
+#define CHIP_ID_MT6236 0x00002007 //0x00100000
+/* SOC */ /* 0x00004000+number */
+#define CHIP_ID_MT6253T 0x00004001 //0x00020000
+#define CHIP_ID_MT6253 0x00004002 //0x00080000
+#define CHIP_ID_MT6252L 0x00004003
+#define CHIP_ID_MT6252H 0x00004004
+/* Dual MAC DSP */ /* 0x00008000+number */
+#define CHIP_ID_MT6268T_DMAC 0x00008001 //0x00200000
+#define CHIP_ID_MT6270A 0x00008002 //0x00400000
+#define CHIP_ID_MT6276 0x00008003 //0x00800000
+#define CHIP_ID_MT6573 0x00008004 //0x00000000
+#define CHIP_ID_MT6575 0x00008005 //0x00000000
+#define CHIP_ID_MT6577 0x00008006 //0x00000000
+/* DLIF */ /* 0x00010000+number */
+#define CHIP_ID_MT6256 0x00010001 //0x01000000
+#define CHIP_ID_MT6251 0x00010002 //0x02000000
+#define CHIP_ID_MT6255 0x00010003
+#define CHIP_ID_MT6250 0x00010004
+#define CHIP_ID_MT6260 0x00010005
+#define CHIP_ID_MT6261 0x00010006
+#define CHIP_ID_MT6280 0x00010080
+#define CHIP_ID_MT6583_MD1 0x00010081
+#define CHIP_ID_MT6583_MD2 0x00010082
+#define CHIP_ID_MT6572 0x00010083
+#define CHIP_ID_MT6582 0x00010084
+#define CHIP_ID_MT6290 0x00010085
+#define CHIP_ID_MT6595 0x00010088
+#define CHIP_ID_MT6752_MD1 0x00010089
+#define CHIP_ID_MT6752_MD2 0x00010090
+#define CHIP_ID_TK6291 0x00010091
+#define CHIP_ID_MT6755 0x00010092
+#define CHIP_ID_MT6292 0x000100A0
+#define CHIP_ID_MT6799 0x000100A1
+#define CHIP_ID_MT6293 0x000100B0
+#define CHIP_ID_MT6763 0X000100B1
+#define CHIP_ID_MT6739 0X000100B2
+#define CHIP_ID_TRINITYE1 0X000100B3
+#define CHIP_ID_TRINITYL 0X000100B4
+#define CHIP_ID_MT6771 0x000100B5
+#define CHIP_ID_MT6765 0x000100B6
+#define CHIP_ID_MT6295M 0X000100C0
+#define CHIP_ID_MT3967 0X000100C1
+#define CHIP_ID_MT6779 0X000100C2
+#define CHIP_ID_MT6297 0X000100D0
+#define CHIP_ID_MT6885 0X000100D1
+#define CHIP_ID_MERCURY 0X000100D2
+#define CHIP_ID_MT6873 0X000100D3
+#define CHIP_ID_MT6853 0X000100D4
+#define CHIP_ID_MT6833 0X000100D5
+#define CHIP_ID_MT6880 0X000100D6
+#define CHIP_ID_MT6890 0X000100D7
+#define CHIP_ID_MT2735 0X000100D8
+#define CHIP_ID_MT6893 0X000100D9/*D6, D7, D8 is used for Colgin*/
+#define CHIP_ID_MT6877 0X000100DA
+#define CHIP_ID_MT6855 0X000100DB
+#ifdef FPGA
+#define CHIP_ID CHIP_ID_FPGA
+#endif
+#ifdef CHIP_MT6208
+#define CHIP_ID CHIP_ID_MT6208
+#endif
+#ifdef CHIP_MT6205
+#define CHIP_ID CHIP_ID_MT6205A
+#endif
+#ifdef CHIP_MT6205B
+#define CHIP_ID CHIP_ID_MT6205B
+#endif
+#ifdef CHIP_MT6218
+#define CHIP_ID CHIP_ID_MT6218A
+#endif
+#ifdef CHIP_MT6218B
+#define CHIP_ID CHIP_ID_MT6218B
+#endif
+#ifdef CHIP_MT6217
+#define CHIP_ID CHIP_ID_MT6218B
+#endif
+#ifdef CHIP_MT6219
+#define CHIP_ID CHIP_ID_MT6219
+#endif
+#ifdef CHIP_MT6228
+#define CHIP_ID CHIP_ID_MT6228
+#endif
+#ifdef CHIP_MT6229
+#define CHIP_ID CHIP_ID_MT6229
+#endif
+#ifdef CHIP_MT6230
+#define CHIP_ID CHIP_ID_MT6229 /* For L1 MT6230==MT6229 */
+#endif
+#ifdef CHIP_MT6226
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226==MT6227 */
+#endif
+#ifdef CHIP_MT6227
+#define CHIP_ID CHIP_ID_MT6227
+#endif
+#ifdef CHIP_MT6226M
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226M==MT6227 */
+#endif
+#ifdef CHIP_MT6226D
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226D==MT6227 */
+#endif
+#ifdef CHIP_MT6227D
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6227D==MT6227 */
+#endif
+#ifdef CHIP_MT6226DS
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6226DS==MT6227 */
+#endif
+#ifdef CHIP_MT6227DS
+#define CHIP_ID CHIP_ID_MT6227 /* For L1 MT6227DS==MT6227 */
+#endif
+#ifdef CHIP_MT6225
+#define CHIP_ID CHIP_ID_MT6225
+#endif
+#ifdef CHIP_MT6268T
+ #ifdef __DSP_FCORE4__
+#define CHIP_ID CHIP_ID_MT6268T_DMAC
+ #else
+#define CHIP_ID CHIP_ID_MT6268T
+ #endif
+#endif
+#ifdef CHIP_MT6268H
+#define CHIP_ID CHIP_ID_MT6268T/* For L1 MT6268H==MT6268T*/
+#endif
+#ifdef CHIP_MT6223
+#define CHIP_ID CHIP_ID_MT6223
+#endif
+#ifdef CHIP_MT6223P
+#define CHIP_ID CHIP_ID_MT6223 /* For L1 MT6223P==MT6223 */
+#endif
+#ifdef CHIP_MT6235
+#define CHIP_ID CHIP_ID_MT6238 /* For L1 MT6235==MT6238 */
+#endif
+#ifdef CHIP_MT6238
+#define CHIP_ID CHIP_ID_MT6238
+#endif
+#ifdef CHIP_MT6235B
+#define CHIP_ID CHIP_ID_MT6238 /* For L1 MT6235B==MT6238 */
+#endif
+#ifdef CHIP_MT6239
+#define CHIP_ID CHIP_ID_MT6238
+#endif
+#ifdef CHIP_TK6516
+#define CHIP_ID CHIP_ID_TK6516
+#endif
+#ifdef CHIP_MT6268A
+#define CHIP_ID CHIP_ID_MT6268A
+#endif
+#ifdef CHIP_MT6268
+#define CHIP_ID CHIP_ID_MT6268
+#endif
+#ifdef CHIP_MT6516
+#define CHIP_ID CHIP_ID_MT6516
+#endif
+#ifdef CHIP_MT6253T
+#define CHIP_ID CHIP_ID_MT6253T
+#endif
+#ifdef CHIP_MT6253
+#define CHIP_ID CHIP_ID_MT6253
+#endif
+#ifdef CHIP_MT6253E
+#define CHIP_ID CHIP_ID_MT6252H
+#endif
+#ifdef CHIP_MT6253L
+#define CHIP_ID CHIP_ID_MT6252L
+#endif
+#ifdef CHIP_MT6252
+#define CHIP_ID CHIP_ID_MT6252L
+#endif
+#ifdef CHIP_MT6252H
+#define CHIP_ID CHIP_ID_MT6252H
+#endif
+#ifdef CHIP_MT6236
+#define CHIP_ID CHIP_ID_MT6236
+#endif
+#ifdef CHIP_MT6236B
+#define CHIP_ID CHIP_ID_MT6236 /* For L1 MT6236B==MT6236 */
+#endif
+#ifdef CHIP_MT6270A
+#define CHIP_ID CHIP_ID_MT6270A
+#endif
+#ifdef CHIP_MT6276
+#define CHIP_ID CHIP_ID_MT6276
+#endif
+#ifdef CHIP_MT6256
+#define CHIP_ID CHIP_ID_MT6256
+#endif
+#ifdef CHIP_MT6255
+#define CHIP_ID CHIP_ID_MT6255
+#endif
+#ifdef CHIP_MT6251
+#define CHIP_ID CHIP_ID_MT6251
+#endif
+#ifdef CHIP_MT6573
+#define CHIP_ID CHIP_ID_MT6573
+#endif
+#ifdef CHIP_MT6575
+#define CHIP_ID CHIP_ID_MT6575
+#endif
+#ifdef CHIP_MT6577
+#define CHIP_ID CHIP_ID_MT6577
+#endif
+#ifdef CHIP_MT6250
+#define CHIP_ID CHIP_ID_MT6250
+#endif
+#ifdef CHIP_MT6280
+#define CHIP_ID CHIP_ID_MT6280
+#endif
+#ifdef CHIP_TK6280
+#define CHIP_ID CHIP_ID_MT6270A /* For TK6280 FPGA development, The 2G part is similar to MT6270A FPGA */
+#endif
+#ifdef CHIP_MT6583
+ #if defined(__MD1__)
+#define CHIP_ID CHIP_ID_MT6583_MD1
+ #elif defined(__MD2__)
+#define CHIP_ID CHIP_ID_MT6583_MD2
+ #else
+#error
+ #endif
+#endif
+#ifdef CHIP_MT6752
+ #if defined(__MD1__)
+#define CHIP_ID CHIP_ID_MT6752_MD1
+ #elif defined(__MD2__)
+#define CHIP_ID CHIP_ID_MT6752_MD2
+ #else
+#error
+ #endif
+#endif
+#ifdef CHIP_MT6572
+#define CHIP_ID CHIP_ID_MT6572
+#endif
+#ifdef CHIP_MT6582
+#define CHIP_ID CHIP_ID_MT6582
+#endif
+#ifdef CHIP_MT6290
+#define CHIP_ID CHIP_ID_MT6290
+#endif
+#ifdef CHIP_MT6595
+#define CHIP_ID CHIP_ID_MT6595
+#endif
+#ifdef MT6293
+#define CHIP_ID CHIP_ID_MT6293
+#endif
+#ifdef MT6763
+#define CHIP_ID CHIP_ID_MT6763
+#endif
+#ifdef MT6739
+#define CHIP_ID CHIP_ID_MT6739
+#endif
+#ifdef MT6771
+#define CHIP_ID CHIP_ID_MT6771
+#endif
+#ifdef MT6765
+#define CHIP_ID CHIP_ID_MT6765
+#endif
+#ifdef MT6295M
+#define CHIP_ID CHIP_ID_MT6295M
+#endif
+#ifdef MT3967
+#define CHIP_ID CHIP_ID_MT3967
+#endif
+#ifdef MT6779
+#define CHIP_ID CHIP_ID_MT6779
+#endif
+#ifdef MT6297
+#define CHIP_ID CHIP_ID_MT6297
+#endif
+#ifdef MT6885
+#define CHIP_ID CHIP_ID_MT6885
+#endif
+#ifdef MERCURY
+#define CHIP_ID CHIP_ID_MERCURY
+#endif
+#ifdef MT6873
+#define CHIP_ID CHIP_ID_MT6873
+#endif
+#ifdef MT6853
+#define CHIP_ID CHIP_ID_MT6853
+#endif
+#ifdef MT6833
+#define CHIP_ID CHIP_ID_MT6833
+#endif
+#if (defined(MT6880) || ((defined(MT6880) && defined(CHIP10992))))
+#define CHIP_ID CHIP_ID_MT6880
+#endif
+#if (defined(MT6890) || ((defined(MT6890) && defined(CHIP10992))))
+#define CHIP_ID CHIP_ID_MT6890
+#endif
+#if (defined(MT2735) || ((defined(MT2735) && defined(CHIP10992))))
+#define CHIP_ID CHIP_ID_MT2735
+#endif
+#ifdef MT6893
+#undef CHIP_ID /* we are undefining the chip id since MT6885 is also enabled for MT6893 project*/
+#define CHIP_ID CHIP_ID_MT6893
+#endif
+#ifdef MT6877
+#define CHIP_ID CHIP_ID_MT6877
+#endif
+#ifdef MT6855
+#define CHIP_ID CHIP_ID_MT6855
+#endif
+
+#if defined(L1_SIM) || (defined(ESIM_BUILD_CONFIG) && (ESIM_BUILD_CONFIG == ESIM_MULTI_MODE_ON_FIBERS))
+ #ifdef L1D_TEST
+#undef CHIP_ID
+#define CHIP_ID CHIP_ID_MT6293
+
+ #else
+
+ #if (defined __MD93__)
+#undef CHIP_ID
+#define CHIP_ID CHIP_ID_MT6292
+ #endif
+ #endif
+#endif
+
+
+#define IS_CHIP_SER(ID) ( CHIP_SER(CHIP_ID)==CHIP_SER(ID) )
+#define IS_CHIP_SER_AND_LATTER(ID) ( CHIP_NUM(CHIP_ID)>=CHIP_NUM(ID) && IS_CHIP_SER(ID) )
+#define IS_CHIP_SER_AND_BEFORE(ID) ( CHIP_NUM(CHIP_ID)<=CHIP_NUM(ID) && IS_CHIP_SER(ID) )
+
+#define IS_FPGA_TARGET ( CHIP_ID==CHIP_ID_FPGA )
+#define IS_CHIP_TARGET ( CHIP_ID!=CHIP_ID_FPGA )
+
+#define IS_CHIP_MT6208 ( CHIP_ID==CHIP_ID_MT6208 )
+#define IS_CHIP_MT6205A ( CHIP_ID==CHIP_ID_MT6205A)
+#define IS_CHIP_MT6205B ( CHIP_ID==CHIP_ID_MT6205B)
+#define IS_CHIP_MT6205 ((CHIP_ID==CHIP_ID_MT6205A) || (CHIP_ID==CHIP_ID_MT6205B))
+#define IS_CHIP_MT6218A ( CHIP_ID==CHIP_ID_MT6218A)
+#define IS_CHIP_MT6218B ( CHIP_ID==CHIP_ID_MT6218B)
+#define IS_CHIP_MT6218 ((CHIP_ID==CHIP_ID_MT6218A) || (CHIP_ID==CHIP_ID_MT6218B))
+#define IS_CHIP_MT6219 ( CHIP_ID==CHIP_ID_MT6219 )
+#define IS_CHIP_MT6228 ( CHIP_ID==CHIP_ID_MT6228 )
+#define IS_CHIP_MT6229 ( CHIP_ID==CHIP_ID_MT6229 )
+#define IS_CHIP_MT6227 ( CHIP_ID==CHIP_ID_MT6227 )
+#define IS_CHIP_MT6225 ( CHIP_ID==CHIP_ID_MT6225 )
+#define IS_CHIP_MT6268T ( CHIP_ID==CHIP_ID_MT6268T)
+#define IS_CHIP_MT6268T_DMAC ( CHIP_ID==CHIP_ID_MT6268T_DMAC )
+#define IS_CHIP_MT6268H ((CHIP_ID==CHIP_ID_MT6268T) && (defined MT6268H) )
+#define IS_CHIP_MT6223 ( CHIP_ID==CHIP_ID_MT6223 )
+#define IS_CHIP_MT6238 ( CHIP_ID==CHIP_ID_MT6238 )
+#define IS_CHIP_TK6516 ( CHIP_ID==CHIP_ID_TK6516 )
+#define IS_CHIP_MT6268A ( CHIP_ID==CHIP_ID_MT6268A)
+#define IS_CHIP_MT6268B ( CHIP_ID==CHIP_ID_MT6268 )
+#define IS_CHIP_MT6268 ((CHIP_ID==CHIP_ID_MT6268A) || (CHIP_ID==CHIP_ID_MT6268)) /* MT6268 includes MT6268A and MT6268 */
+#define IS_CHIP_MT6516 ( CHIP_ID==CHIP_ID_MT6516 )
+#define IS_CHIP_MT6253T ( CHIP_ID==CHIP_ID_MT6253T)
+#define IS_CHIP_MT6253 ((CHIP_ID==CHIP_ID_MT6253T) || (CHIP_ID==CHIP_ID_MT6253) || (CHIP_ID==CHIP_ID_MT6252L) || (CHIP_ID==CHIP_ID_MT6252H)) /* MT6253 includes MT6253T,MT6253,MT6252L,MT6252H */
+#define IS_CHIP_MT6252L ( CHIP_ID==CHIP_ID_MT6252L)
+#define IS_CHIP_MT6252H ( CHIP_ID==CHIP_ID_MT6252H)
+#define IS_CHIP_MT6252 ((CHIP_ID==CHIP_ID_MT6252L) || (CHIP_ID==CHIP_ID_MT6252H))
+#define IS_CHIP_MT6253EL ( IS_CHIP_MT6252 )
+#define IS_CHIP_MT6236 ( CHIP_ID==CHIP_ID_MT6236 )
+#define IS_CHIP_MT6270A ( CHIP_ID==CHIP_ID_MT6270A)
+#define IS_CHIP_MT6276 ( CHIP_ID==CHIP_ID_MT6276 )
+#define IS_CHIP_MT6256 ( CHIP_ID==CHIP_ID_MT6256 )
+#define IS_CHIP_MT6251 ( CHIP_ID==CHIP_ID_MT6251 )
+#define IS_CHIP_MT6573 ( CHIP_ID==CHIP_ID_MT6573 )
+#define IS_CHIP_MT6575 ((CHIP_ID==CHIP_ID_MT6575) || (CHIP_ID==CHIP_ID_MT6577))
+#define IS_CHIP_MT6577 ( CHIP_ID==CHIP_ID_MT6577 )
+#define IS_CHIP_MT6250 ( CHIP_ID==CHIP_ID_MT6250 )
+#define IS_CHIP_MT6280 ( CHIP_ID==CHIP_ID_MT6280 )
+#define IS_CHIP_MT6925 ( CHIP_ID==CHIP_ID_MT6229 ) /* Temp add for MT6925 simulation */
+#define IS_CHIP_TK6280 ( CHIP_ID==CHIP_ID_MT6270A) /* For TK6280 FPGA */
+#define IS_CHIP_MT6583_MD1 ( CHIP_ID==CHIP_ID_MT6583_MD1 )
+#define IS_CHIP_MT6583_MD2 ( CHIP_ID==CHIP_ID_MT6583_MD2 )
+#define IS_CHIP_MT6572 ((CHIP_ID==CHIP_ID_MT6572) || (CHIP_ID==CHIP_ID_MT6582))
+#define IS_CHIP_MT6582 ( CHIP_ID==CHIP_ID_MT6582 )
+#define IS_CHIP_MT6290 ( CHIP_ID==CHIP_ID_MT6290 )
+#define IS_CHIP_MT6595 ( CHIP_ID==CHIP_ID_MT6595 )
+#define IS_CHIP_MT6752_MD1 ( CHIP_ID==CHIP_ID_MT6752_MD1 )
+#define IS_CHIP_MT6752_MD2 ( CHIP_ID==CHIP_ID_MT6752_MD2 )
+#define IS_CHIP_TK6291 ( CHIP_ID==CHIP_ID_TK6291 )
+#define IS_CHIP_MT6755 ( CHIP_ID==CHIP_ID_MT6755 )
+#define IS_CHIP_MT6292 (( CHIP_ID==CHIP_ID_MT6292 ) || (CHIP_ID==CHIP_ID_MT6799))
+#define IS_CHIP_MT6799 ( CHIP_ID==CHIP_ID_MT6799 )
+#define IS_CHIP_MT6293 ((CHIP_ID==CHIP_ID_MT6293) || (CHIP_ID==CHIP_ID_MT6763) || (CHIP_ID==CHIP_ID_MT6739) || (CHIP_ID==CHIP_ID_MT6771) || (CHIP_ID==CHIP_ID_MT6765) || (CHIP_ID==CHIP_ID_TRINITYE1) || (CHIP_ID==CHIP_ID_TRINITYL))
+#define IS_CHIP_MT6763 (CHIP_ID==CHIP_ID_MT6763)
+#define IS_CHIP_MT6739 (CHIP_ID==CHIP_ID_MT6739)
+#define IS_CHIP_MT6771 (CHIP_ID==CHIP_ID_MT6771)
+#define IS_CHIP_MT6765 (CHIP_ID==CHIP_ID_MT6765)
+#define IS_CHIP_MT6295 ((CHIP_ID==CHIP_ID_MT6295M) || (CHIP_ID==CHIP_ID_MT3967) || (CHIP_ID==CHIP_ID_MT6779))
+#define IS_CHIP_MT3967 (CHIP_ID==CHIP_ID_MT3967)
+#define IS_CHIP_MT6779 (CHIP_ID==CHIP_ID_MT6779)
+#define IS_CHIP_MT6297 ((CHIP_ID==CHIP_ID_MT6297) || (CHIP_ID==CHIP_ID_MT6885) || (CHIP_ID==CHIP_ID_MERCURY) || (CHIP_ID==CHIP_ID_MT6873) || (CHIP_ID==CHIP_ID_MT6853) || (CHIP_ID==CHIP_ID_MT6833) || (CHIP_ID==CHIP_ID_MT6880) || (CHIP_ID==CHIP_ID_MT6890) || (CHIP_ID==CHIP_ID_MT2735) || (CHIP_ID==CHIP_ID_MT6893) || (CHIP_ID==CHIP_ID_MT6877) || (CHIP_ID==CHIP_ID_MT6855))
+#define IS_CHIP_MT6885 ((CHIP_ID==CHIP_ID_MT6885) || (CHIP_ID==CHIP_ID_MERCURY) || (CHIP_ID==CHIP_ID_MT6873) || (CHIP_ID==CHIP_ID_MT6853) || (CHIP_ID==CHIP_ID_MT6833) || (CHIP_ID==CHIP_ID_MT6880) || (CHIP_ID==CHIP_ID_MT6890) || (CHIP_ID==CHIP_ID_MT2735) || (CHIP_ID==CHIP_ID_MT6893) || (CHIP_ID==CHIP_ID_MT6877) || (CHIP_ID==CHIP_ID_MT6855))
+#define IS_CHIP_MERCURY (CHIP_ID==CHIP_ID_MERCURY)
+#define IS_CHIP_MT6873 (CHIP_ID==CHIP_ID_MT6873)
+#define IS_CHIP_MT6853 (CHIP_ID==CHIP_ID_MT6853)
+#define IS_CHIP_MT6833 (CHIP_ID==CHIP_ID_MT6833)
+#define IS_CHIP_MT6880 (CHIP_ID==CHIP_ID_MT6880)
+#define IS_CHIP_MT6890 (CHIP_ID==CHIP_ID_MT6890)
+#define IS_CHIP_MT2735 (CHIP_ID==CHIP_ID_MT2735)
+#define IS_CHIP_MT6893 (CHIP_ID==CHIP_ID_MT6893)
+#define IS_CHIP_MT6877 (CHIP_ID==CHIP_ID_MT6877)
+#define IS_CHIP_MT6855 (CHIP_ID==CHIP_ID_MT6855)
+
+/* For L1C usage */
+/* CS3 requirement, CS3 would request us to update them */
+#define IS_CHIP_MT623538 IS_CHIP_MT6238
+#define IS_CHIP_MT6235_SER defined(MT6235B)
+#define IS_CHIP_MT6238_SER ( IS_CHIP_MT623538 && !IS_CHIP_MT6235_SER )
+#define IS_HYPER_SLEEP_MODE_CHIP ((IS_CHIP_MT6238_SER || IS_CHIP_MT6516 || IS_CHIP_MT6268B || IS_CHIP_MT6253 || IS_CHIP_MT6236 || IS_CHIP_MT6256 || IS_CHIP_MT6251 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297) && !defined(MT6516_S00) )
+// SM_EINT_ABORT_DEFECT: 27, 28, 25, 29, 23, (35,38), 6516
+#define IS_SM_EINT_ABORT_DEFECT ( IS_CHIP_MT6227 || IS_CHIP_MT6228 || IS_CHIP_MT6225 || IS_CHIP_MT6229 || IS_CHIP_MT6223 || IS_CHIP_MT6238 )
+// Total settling time = 26M settling time + PLL settling time
+#define IS_SEPARATE_PLL_SETTLING_CHIP ( IS_CHIP_MT6256 || IS_CHIP_MT6251 || IS_CHIP_MT6255 )
+
+#ifdef __HYPER_SLEEP_MODE_CHIP__
+#undef IS_HYPER_SLEEP_MODE_CHIP
+#define IS_HYPER_SLEEP_MODE_CHIP 1
+#endif
+
+/*--------------------*/
+/* For Dual MAC Group */
+/*--------------------*/
+#define IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6270A) )
+
+/*------------------*/
+/* For New 2G Modem */
+/*------------------*/
+#define IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6256) )
+
+/*---------------------*/
+/* For GSM/GPRS Group */
+/*---------------------*/
+#define IS_CHIP_MT6208_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6208) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6205_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6205A) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6205A_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6205A) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6205B_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6205B) || IS_CHIP_SER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6218_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6218A_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6218A) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6218B_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6218B) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6219_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6219) || IS_CHIP_SER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6227_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6227) )
+#define IS_CHIP_MT6228_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6228) )
+#define IS_CHIP_MT6225_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6225) )
+#define IS_CHIP_MT6295_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6295M) )
+#define IS_CHIP_MT6297_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6297) )
+#define IS_CHIP_MT6885_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6885) )
+#define IS_CHIP_MT6853_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6853) )
+
+
+/*----------------------------------*/
+/* For Dual DSP Group (EGPRS Group) */
+/*----------------------------------*/
+#define IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6229) || IS_CHIP_SER(CHIP_ID_MT6223) || IS_CHIP_SER(CHIP_ID_MT6238) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+/* For SAIC group */
+/* Be careful!! MT6223 is a special chip without EDGE */
+#define IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6223) || IS_CHIP_SER(CHIP_ID_MT6238) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+#define IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION ( IS_CHIP_SER(CHIP_ID_MT6238) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+#define IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6268A) || IS_CHIP_SER(CHIP_ID_MT6253) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+/* Be careful!! MT6253(T) is a special chip without EDGE */
+#define IS_SAIC_CHIP_MT6253T_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6253T) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6236) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+#define IS_SAIC_CHIP_MT6253_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6253) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6236) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+#define IS_EDGE_SAIC_CHIP_MT6236_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6236) || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+
+/*-------------------*/
+/* For 2G RxD Group */
+/*-------------------*/
+#define IS_2GRXD_CHIP_MT6765_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6765) )
+
+/*----------------------*/
+/* For 2G MMDFE Group */
+/*----------------------*/
+#define IS_MMDFE_CHIP_MT6297_AND_LATTER_VERSION ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6297) )
+
+/*--------------------*/
+/* For Specific Group */
+/*--------------------*/
+/* For SmartPhone Group */
+#define IS_SMARTPHONE_CHIP_TK6516_AND_LATTER_VERSION ( IS_CHIP_TK6516 || IS_CHIP_MT6516 )
+/* For 65NM chip Group */
+#define IS_65NM_CHIP ( IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6268A) || IS_CHIP_SER(CHIP_ID_MT6256) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6276) )
+/* For 65NM with BSI/BPI power down group*/
+#define IS_65NM_CHIP_BSI_BPI_PWN ( IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_SER(CHIP_ID_MT6256) )
+/* For Support us counter chip Group */
+#define IS_USC_CHIP ( IS_CHIP_MT6268B || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6270A) || IS_CHIP_MT6268H || IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) )
+/* For TDMA 8R/(6T), AuxADC chip */
+#define IS_NEW_TDMA_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) || IS_CHIP_MT6252 )
+/* For chip with 32-bit of BSI_ENA */
+#define IS_BSI_REG_32_BIT_CHIP ( IS_CHIP_MT6268T || IS_CHIP_MT6268 || IS_CHIP_MT6268H || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) )
+/* For chip with 32-bit of BPI_ENA */
+#define IS_BPI_REG_32_BIT_CHIP ( IS_CHIP_MT6268T || IS_CHIP_MT6268 || IS_CHIP_MT6268H || IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280) )
+/* For chip with 48-bit of BPI_DATA */
+#define IS_BPI_DATA_48_BIT_CHIP ( IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 )
+/* For chip with 32-bit of BPI_DATA */
+#define IS_BPI_DATA_32_BIT_CHIP ( !IS_BPI_DATA_48_BIT_CHIP )
+/* For chip with 32-bit of BSI_CON */
+#define IS_BSI_CON_32_BIT_CHIP ( IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293)
+/* For HW 8RWIN PM chip */
+#define IS_HW_8RXWIN_PM_SUPPORT_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) || IS_CHIP_MT6252 )
+/* For SOC chip Group */
+#define IS_SOC_CHIP ( IS_CHIP_SER(CHIP_ID_MT6253) || (IS_CHIP_SER(CHIP_ID_MT6256)&&(!IS_CHIP_MT6583_MD1)&&(!IS_CHIP_MT6583_MD2)&&(!IS_CHIP_MT6572)&&(!IS_CHIP_MT6290)&&(!IS_CHIP_MT6595)&&(!IS_CHIP_MT6752_MD1)&&(!IS_CHIP_MT6752_MD2)&&(!IS_CHIP_TK6291)&&(!IS_CHIP_MT6755)&&(!IS_CHIP_MT6292)&&(!IS_CHIP_MT6293)) )
+/* For 3G group */
+#define IS_3G_CHIP ( IS_CHIP_MT6268 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6276) )
+/* For EDGE MTBF PSHO group */
+#define IS_EDGE_MTBF_PSHO_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) )
+/* For EDGE RTTI FANR group */
+#define IS_EDGE_RTTI_FANR_CHIP ( 0 ) // temp, RTTI and FANR is still under development
+
+#define IS_FM_ON_26M_CHIP ( IS_CHIP_MT6268 || IS_CHIP_MT6236 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6270A) || IS_CHIP_SER(CHIP_ID_MT6256) )
+#define IS_DUAL_DSP_CHIP ( IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION && !(IS_CACHE_DSP_SUPPORT || IS_DSP_ARCHITECTURE_V4_SUPPORT) )
+#define IS_DUAL_MAC_DSP_CHIP ( IS_CHIP_SER(CHIP_ID_MT6270A) )
+#define IS_FD216_DSP_CHIP ( !IS_DUAL_MAC_DSP_CHIP )
+/*IS_CHIP_EQ34311 (DSP central weighting window) is defined for L1C to adjust the upper bound to recalibrate 32k Xtal : 1=> upper bound 24; 0=> upper bound 32*/
+#define IS_CHIP_EQ34311 ( IS_CHIP_MT6225 || IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION )
+/* Modified By James, to avoid VC++ bug of that defined(MT6217) is always false */
+#define IS_CHIP_MT6218B_AN2DN ( (defined MT6218B_AN) || (defined MT6218B_BN) || (defined MT6218B_CN) || (defined MT6218B_DN) )
+#define IS_CHIP_MT6218B_EN ( (defined MT6218B_EN) )
+#define IS_CHIP_MT6218B_FN ( (defined MT6218B_FN) )
+#define IS_CHIP_MT6219_AV ( (defined MT6219_AV) )
+#define IS_CHIP_MT6219_BV ( (defined MT6219_BV) )
+#define IS_CHIP_MT6219_EV ( (defined MT6219_EV) )
+#define IS_CHIP_MT6217 ( (defined CHIP_MT6217) || (defined MT6217) )
+#define IS_CHIP_MT6227_S00 ( (defined MT6227_S00) || (defined MT6226_S00) || (defined MT6226M_S00) )
+#define IS_CHIP_MT6227_S01 ( (defined MT6227_S01) || (defined MT6226_S01) || (defined MT6226M_S01) ) // !Caution:Plz also take care of chip MT6226 & MT6226M as using this compile option
+#define IS_CHIP_MT6227_S02 ( (defined MT6227_S02) || (defined MT6226_S02) || (defined MT6226M_S02) ) // !Caution:Plz also take care of chip MT6226 & MT6226M as using this compile option
+#define IS_CHIP_MT6227_D00 ( (defined MT6227D_S00) || (defined MT6226D_S00) || (defined MT6227DS_S00) || (defined MT6226DS_S00) )
+#define IS_CHIP_MT6228_S00 ( (defined MT6228_S00) )
+#define IS_CHIP_MT6228_S01 ( (defined MT6228_S01) )
+#define IS_CHIP_MT6228_S02 ( (defined MT6228_S02) )
+#define IS_CHIP_MT6225_S00 ( (defined MT6225_S00) )
+#define IS_CHIP_MT6229_FPGA1 ( defined MT6229_FPGA1 )
+#define IS_CHIP_MT6229_FPGA2 ( defined MT6229_FPGA2 )
+#define IS_CHIP_MT6229_FPGA3 ( defined MT6229_FPGA3 )
+#define IS_CHIP_MT6229_S00 ( (defined MT6229_S00) || (defined MT6230_S00) )
+#define IS_CHIP_MT6229_S01 ( (defined MT6229_S01) || (defined MT6230_S01) )
+#define IS_CHIP_MT6229_S02 ( (defined MT6229_S02) || (defined MT6230_S02) )
+#define IS_CHIP_MT6223_S00 ( (defined MT6223_S00) || (defined MT6223P_S00) )
+#define IS_CHIP_MT6268_S00 ( (defined MT6268_S00) )
+#define IS_CHIP_MT6256_S00 ( (defined MT6256_S00) )
+#define IS_CHIP_MT6256_S01 ( (defined MT6256_S01) )
+#define IS_CHIP_MT6256_S02 ( (defined MT6256_S02) )
+#define IS_CHIP_MT6251_S00 ( (defined MT6251_S00) )
+#define IS_CHIP_MT6252_S00 ( (defined MT6253E_S00) || (defined MT6253L_S00) || (defined MT6252_S00) || (defined MT6252H_S00) )
+#define IS_CHIP_MT6252_S01 ( (defined MT6253E_S01) || (defined MT6253L_S01) || (defined MT6252_S01) || (defined MT6252H_S01) )
+#define IS_CHIP_MT6270A_E1 ( (defined MT6270A_S00) && !(defined __MT6270A_FPGA_HW_VER_E2__) )
+#define IS_CHIP_MT6270A_E2 ( (defined MT6270A_S00) && (defined __MT6270A_FPGA_HW_VER_E2__) )
+#define IS_CHIP_MT6276_S00 ( (defined MT6276_S00) )
+#define IS_CHIP_MT6276_S01 ( (defined MT6276_S01) )
+#define IS_CHIP_MT6573_S00 ( (defined MT6573_S00) )
+#define IS_CHIP_MT6573_S01 ( (defined MT6573_S01) )
+#define IS_CHIP_MT6575_S00 ( (defined MT6575_S00) )
+#define IS_CHIP_MT6280_S00 ( (defined MT6280_S00) )
+#define IS_CHIP_MT6280_S01 ( (defined MT6280_S01) )
+#define IS_CHIP_MT6290_S00 ( (defined MT6290_S00) )
+#define IS_CHIP_MT6290_S01 ( (defined MT6290_S01) )
+
+/* For temparially modification */
+/* Remove the compile option once MT6229 has been verified */
+/* For FPGA old architecture without IR and Exchange Buffer on External SRAM */
+/* 1: Full Function 6229 0: For FPGA old architecture */
+#define IS_DSP_FULLFUNCTION_OF_6229 0
+#define IS_EPSK_TX_SUPPORT (defined __EPSK_TX__)
+#define IS_PS_EPSK_TX_DISABLE (defined __EPSK_TX_SW_SWITCH_OFF__)
+/*.......................................................*/
+
+#ifndef CHIP_ID
+ #ifdef FPGA
+/*FPGA*/ #define CHIP_ID CHIP_ID_FPGA
+ #endif
+ #ifdef MT6208
+/*MT6208*/ #define CHIP_ID CHIP_ID_MT6208
+ #endif
+ #ifdef MT6205
+/*MT6205*/ #define CHIP_ID CHIP_ID_MT6205A
+ #endif
+ #ifdef MT6205A
+/*MT6205A*/ #define CHIP_ID CHIP_ID_MT6205A
+ #endif
+ #ifdef MT6205B
+/*MT6205B*/ #define CHIP_ID CHIP_ID_MT6205B
+ #endif
+ #ifdef MT6218
+/*MT6218*/ #define CHIP_ID CHIP_ID_MT6218A
+ #endif
+ #ifdef MT6218A
+/*MT6218A*/ #define CHIP_ID CHIP_ID_MT6218A
+ #endif
+ #ifdef MT6218B
+/*MT6218B*/ #define CHIP_ID CHIP_ID_MT6218B
+ #endif
+ #ifdef MT6219
+/*MT6219*/ #define CHIP_ID CHIP_ID_MT6219
+ #endif
+ #ifdef MT6217
+/*MT6217*/ #define CHIP_ID CHIP_ID_MT6218B
+ #endif
+ #ifdef MT6228
+/*MT6228*/ #define CHIP_ID CHIP_ID_MT6228
+ #endif
+ #ifdef MT6229
+/*MT6229*/ #define CHIP_ID CHIP_ID_MT6229
+ #endif
+ #ifdef MT6230
+/*MT6229*/ #define CHIP_ID CHIP_ID_MT6229
+ #endif
+ #ifdef MT6226 /* For L1 MT6226==MT6227 */
+/*MT6226*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6227
+/*MT6227*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6226M /* For L1 MT6226M==MT6227 */
+/*MT6226M*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6226D /* For L1 MT6226D==MT6227 */
+/*MT6226*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6227D /* For L1 MT6227D==MT6227 */
+/*MT6227*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6226DS /* For L1 MT6226DS==MT6227 */
+/*MT6226*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6227DS /* For L1 MT6227DS==MT6227 */
+/*MT6227*/ #define CHIP_ID CHIP_ID_MT6227
+ #endif
+ #ifdef MT6225
+/*MT6225*/ #define CHIP_ID CHIP_ID_MT6225
+ #endif
+ #ifdef MT6268T
+ #ifdef __DSP_FCORE4__
+/*MT6268T*/ #define CHIP_ID CHIP_ID_MT6268T_DMAC
+ #else
+/*MT6268T*/ #define CHIP_ID CHIP_ID_MT6268T
+ #endif
+ #endif
+ #ifdef MT6268H /* For L1 MT6268H==MT6268T*/
+/*MT6268H*/ #define CHIP_ID CHIP_ID_MT6268T
+ #endif
+ #ifdef MT6223
+/*MT6223*/ #define CHIP_ID CHIP_ID_MT6223
+ #endif
+ #ifdef MT6223P /* For L1 MT6223P==MT6223 */
+/*MT6223*/ #define CHIP_ID CHIP_ID_MT6223
+ #endif
+ #ifdef MT6238
+/*MT6238*/ #define CHIP_ID CHIP_ID_MT6238
+ #endif
+ #ifdef MT6235B /* For L1 MT6235B==MT6238 */
+/*MT6235B*/ #define CHIP_ID CHIP_ID_MT6238
+ #endif
+ #ifdef MT6239 /* For L1 MT6239==MT6238 */
+/*MT6239*/ #define CHIP_ID CHIP_ID_MT6238
+ #endif
+ #ifdef TK6516
+/*TK6516*/ #define CHIP_ID CHIP_ID_TK6516
+ #endif
+ #ifdef MT6268A
+/*MT6268A*/ #define CHIP_ID CHIP_ID_MT6268A
+ #endif
+ #ifdef MT6268
+/*MT6268*/ #define CHIP_ID CHIP_ID_MT6268
+ #endif
+ #ifdef MT6516
+/*MT6516*/ #define CHIP_ID CHIP_ID_MT6516
+ #endif
+ #ifdef MT6253T
+/*MT6253T*/ #define CHIP_ID CHIP_ID_MT6253T
+ #endif
+ #ifdef MT6253L
+/*MT6253*/ #define CHIP_ID CHIP_ID_MT6252L
+ #endif
+ #ifdef MT6270A
+/*MT6270A*/ #define CHIP_ID CHIP_ID_MT6270A
+ #endif
+ #ifdef TK6280
+/*TK6280*/ #define CHIP_ID CHIP_ID_MT6270A /* For TK6280 FPGA development, The 2G part is similar to MT6270A FPGA */
+ #endif
+ #ifdef MT6583
+ #if defined(__MD1__)
+/*MT6583*/ #define CHIP_ID CHIP_ID_MT6583_MD1
+ #elif defined(__MD2__)
+/*MT6583*/ #define CHIP_ID CHIP_ID_MT6583_MD2
+ #else
+#error
+ #endif
+ #endif
+ #ifdef MT6752
+ #if defined(__MD1__)
+/*MT6583*/ #define CHIP_ID CHIP_ID_MT6752_MD1
+ #elif defined(__MD2__)
+/*MT6583*/ #define CHIP_ID CHIP_ID_MT6752_MD2
+ #else
+#error
+ #endif
+ #endif
+
+ /* UESIM-MOLY */
+ #if defined(__UE_SIMULATOR__)
+ #ifdef L1D_TEST
+/*MT6290*/ #undef CHIP_ID
+/*MT6290*/ #define CHIP_ID CHIP_ID_MT6290
+ #else
+/*MT6280*/ #undef CHIP_ID
+/*MT6280*/ #define CHIP_ID CHIP_ID_MT6280
+ #endif
+ #endif
+#endif
+
+/* default setting */
+#ifndef CHIP_ID
+ #ifdef CHIP_TARGET
+/*CHIP*/ #define CHIP_ID CHIP_ID_MT6208
+ #else
+/*FPGA*/ #define CHIP_ID CHIP_ID_FPGA
+ #endif
+#endif
+
+//CH modify for simulation environment
+#ifdef L1_SIM
+ #if defined(MT6205)
+#define SIM_MT6205 MT6205
+ #elif defined(MT6208)
+#define SIM_MT6208 MT6208
+ #elif defined(MT6218)
+#define SIM_MT6218 MT6218
+ #elif defined(MT6229)
+#define SIM_MT6229 MT6229
+ #elif defined(MT6268T)
+#define SIM_MT6229 MT6268T
+ #elif defined(MT6268)
+#define SIM_MT6229 MT6268
+ #elif defined(MT6268H)
+#define SIM_MT6229 MT6268T
+ #elif defined(MT6583)
+#define SIM_MT6229 MT6583
+ #elif defined(MT6752)
+#define SIM_MT6229 MT6752
+ #elif defined(MT6291)
+#define SIM_MT6229 TK6291
+ #elif defined(MT6293)
+#define SIM_MT6229 MT6293
+ #elif defined(MT6763)
+#define SIM_MT6229 MT6763
+ #elif defined(MT6739)
+#define SIM_MT6229 MT6739
+ #elif defined(MT6771)
+#define SIM_MT6229 MT6771
+ #elif defined(MT6765)
+#define SIM_MT6229 MT6765
+ #elif defined(MT6295M)
+#define SIM_MT6229 MT6295M
+ #elif defined(MT3967)
+#define SIM_MT6229 MT3967
+ #elif defined(MT6779)
+#define SIM_MT6229 MT6779
+ #elif ((defined(MT6297)) || (defined MT6885) || (defined MERCURY) || (defined MT6873) || (defined MT6853) || (defined MT6833) || (defined MT6880) || (defined MT6890) || (defined MT2735) || (defined MT6893) || (defined MT6877) || (defined MT6855))
+#define SIM_MT6229 MT3967
+// #else
+//#error
+ #endif
+#endif
+
+/*===============================================================================================*/
+
+/*------------------------------------------*/
+/* Compile Option : */
+/* ( 1) RF_BRIGHT2 */
+/* ( 2) RF_BRIGHT4 */
+/* ( 3) RF_AERO */
+/* ( 4) RF_AERO1PLUS */
+/* ( 5) RF_MT6116 */
+/* ( 6) RF_MT6119 */
+/* ( 7) RF_MT6119C */
+/* ( 8) RF_MT6129A */
+/* ( 9) RF_MT6129B */
+/* (10) RF_MT6129C */
+/* (11) RF_MT6129D */
+/* (12) RF_MT6139B */
+/* (13) RF_MT6139C */
+/* (14) RF_MT6140A */
+/* (16) RF_MT6139E */
+/* ------------- */
+/* (*) BRIGHT2_RF */
+/*------------------------------------------*/
+/* Use in L1D : */
+/* ( 1) IS_RF_BRIGHT2 */
+/* ( 2) IS_RF_BRIGHT4 */
+/* ( 3) IS_RF_AERO */
+/* ( 4) IS_RF_AERO1PLUS */
+/* ( 5) IS_RF_MT6116 */
+/* ( 6) IS_RF_MT6119 */
+/* ( 7) IS_RF_MT6119C */
+/* ( 8) IS_RF_MT6129A */
+/* ( 9) IS_RF_MT6129B */
+/* (10) IS_RF_MT6129C */
+/* (11) IS_RF_MT6129D */
+/*------------------------------------------*/
+
+#define RF_ID_BRIGHT2 0x00000001
+#define RF_ID_BRIGHT4 0x00000002
+#define RF_ID_AERO 0x00000004
+#define RF_ID_AERO1PLUS 0x00000008
+#define RF_ID_POLARIS1 0x00000010
+#define RF_ID_POLARIS2 0x00000020
+#define RF_ID_SKY74045 0x00000040
+#define RF_ID_BRIGHT5P 0x00000080
+#define RF_ID_MT6116 0x00000100
+#define RF_ID_MT6119 0x00000200
+#define RF_ID_MT6119C 0x00000400
+#define RF_ID_MT6129A 0x00000800
+#define RF_ID_MT6129B 0x00001000
+#define RF_ID_MT6129C 0x00002000
+#define RF_ID_MT6129D 0x00004000
+#define RF_ID_MT6139B 0x00008000
+#define RF_ID_MT6139C 0x00010000
+#define RF_ID_MT6140A 0x00020000
+#define RF_ID_SKY74117 0x00040000
+#define RF_ID_SKY74400 0x00080000
+#define RF_ID_AERO2 0x00100000
+#define RF_ID_MT6140B 0x00200000
+#define RF_ID_MT6139E 0x00800000
+#define RF_ID_SKY74137 0x01000000
+#define RF_ID_MT6140C 0x02000000
+#define RF_ID_GRF6201 0x04000000
+#define RF_ID_IRFS3001 0x08000000
+#define RF_ID_MT6140D 0x10000000
+#define RF_ID_AG2550 0x10000001
+#define RF_ID_AERO2E 0x10000002
+#define RF_ID_QS1000 0x10000003
+#define RF_ID_QS1001 0x10000004
+#define RF_ID_AD6548 0x10000005
+#define RF_ID_AD6546 0x10000006
+#define RF_ID_CMOSEDGE 0x10000007
+#define RF_ID_MTKSOC1 0x10000008
+#define RF_ID_MT6256RF 0x10000009
+#define RF_ID_MT6251RF 0x1000000a
+#define RF_ID_MT6253ELRF 0x1000000b // the same as MT6252RF
+#define RF_ID_MT6252RF 0x1000000c
+#define RF_ID_MT6162 0x1000000d
+#define RF_ID_MT6163 0x1000000e
+#define RF_ID_MT6255RF 0x1000000f
+#define RF_ID_MT6250RF 0x10000010
+#define RF_ID_MT6280RF 0x10000011
+#define RF_ID_MT6167 0x10000012
+#define RF_ID_MT6160 0x10000013
+#define RF_ID_MT6166 0x10000014
+#define RF_ID_MT6169 0x10000015
+#define RF_ID_MT6165 0x10000016
+#define RF_ID_MT6261RF 0x10000017
+#define RF_ID_MT6580RF 0x10000018
+#define RF_ID_MT6176 0x10000019
+#define RF_ID_MT6179 0x1000001a
+#define RF_ID_MT6570RF 0x1000001b
+#define RF_ID_MT6177L 0x1000001c
+#define RF_ID_MT6177M 0x1000001d
+#define RF_ID_TRINITYE1 0x1000001e
+#define RF_ID_TRINITYL 0x1000001f
+#define RF_ID_MT6186 0x10000020
+#define RF_ID_MT6186M 0x10000021
+#define RF_ID_MT6190T 0x10000022
+#define RF_ID_MT6190 0x10000023
+#define RF_ID_MT6190M 0x10000024
+#define RF_ID_MT6195 0x10000025
+
+
+
+
+
+/* ------------------------------------------- */
+/* Note that the RF ID should be named */
+/* as a variable rather than BITMask */
+/* from 0x10000000, */
+/* the next RF ID should be 0x10000007...etc */
+/* ------------------------------------------- */
+
+#ifdef L1_SIM
+ #ifdef BRIGHT2_EVB
+/*BRIGHT2*/ #define RF_ID RF_ID_BRIGHT2
+ #endif
+ #ifdef BRIGHT4_EVB
+/*BRIGHT4*/ #define RF_ID RF_ID_BRIGHT4
+ #endif
+ #ifdef BRIGHT5P_EVB
+/*BRIGHT5P*/#define RF_ID RF_ID_BRIGHT5P
+ #endif
+ #ifdef AERO_EVB
+/*AERO*/ #define RF_ID RF_ID_AERO
+ #endif
+ #ifdef SPRING_EVB
+/*AERO*/ #define RF_ID RF_ID_AERO
+ #endif
+ #ifdef POLARIS1_EVB
+/*RFMD*/ #define RF_ID RF_ID_POLARIS1
+ #endif
+ #ifdef MT6119_EVB
+/*MT6119*/ #define RF_ID RF_ID_MT6119
+ #endif
+ #ifdef FOUNTAIN_EVB
+/*MT6119*/ #define RF_ID RF_ID_MT6119
+ #endif
+ #ifdef FOUNTAIN2_EVB
+/*MT6119*/ #define RF_ID RF_ID_MT6119C
+ #endif
+ #ifdef MT6129A_EVB
+/*MT6129A*/ #define RF_ID RF_ID_MT6129A
+ #endif
+ #ifdef OCEAN_EVB
+/*MT6129C*/ #define RF_ID RF_ID_MT6129C
+ #endif
+ #ifdef MT6139B_EVB
+/*MT6139B*/ #define RF_ID RF_ID_MT6139B
+ #endif
+ #ifdef MT6139C_EVB
+/*MT6139C*/ #define RF_ID RF_ID_MT6139C
+ #endif
+ #ifdef MT6139E_EVB
+/*MT6139E*/ #define RF_ID RF_ID_MT6139E
+ #endif
+ #ifdef MT6140A_EVB
+/*MT6140A*/ #define RF_ID RF_ID_MT6140A
+ #endif
+ #ifdef SKY74045_EVB
+/*SKY74045*/#define RF_ID RF_ID_SKY74045
+ #endif
+ #ifdef SKY74117_EVB
+/*SKY74117*/#define RF_ID RF_ID_SKY74117
+ #endif
+ #ifdef SKY74137_EVB
+/*SKY74137*/#define RF_ID RF_ID_SKY74137
+ #endif
+ #ifdef GRF6201_EVB
+/*GRF6201*/ #define RF_ID RF_ID_GRF6201
+ #endif
+ #ifdef IRFS3001_EVB
+/*IRFS3001*/#define RF_ID RF_ID_IRFS3001
+ #endif
+ #ifdef AD6546_EVB
+/*AD6546*/ #define RF_ID RF_ID_AD6546
+ #endif
+#endif
+
+#define IS_RF_BRIGHT2 ( RF_ID==RF_ID_BRIGHT2 )
+#define IS_RF_BRIGHT4 ( RF_ID==RF_ID_BRIGHT4 )
+#define IS_RF_BRIGHT5P ( RF_ID==RF_ID_BRIGHT5P )
+#define IS_RF_AERO ( RF_ID==RF_ID_AERO )
+#define IS_RF_AERO1PLUS ( RF_ID==RF_ID_AERO1PLUS )
+#define IS_RF_POLARIS1 ( RF_ID==RF_ID_POLARIS1 )
+#define IS_RF_MT6116 ( RF_ID==RF_ID_MT6116 )
+#define IS_RF_MT6119 ( RF_ID==RF_ID_MT6119 )
+#define IS_RF_MT6119C ( RF_ID==RF_ID_MT6119C )
+#define IS_RF_MT6129A ( RF_ID==RF_ID_MT6129A )
+#define IS_RF_MT6129B ( RF_ID==RF_ID_MT6129B )
+#define IS_RF_MT6129C ( RF_ID==RF_ID_MT6129C )
+#define IS_RF_MT6129D ( RF_ID==RF_ID_MT6129D )
+#define IS_RF_MT6139B ( RF_ID==RF_ID_MT6139B )
+#define IS_RF_MT6139C ( RF_ID==RF_ID_MT6139C )
+#define IS_RF_MT6139E ( RF_ID==RF_ID_MT6139E )
+#define IS_RF_MT6140A ( RF_ID==RF_ID_MT6140A )
+#define IS_RF_MT6140B ( RF_ID==RF_ID_MT6140B )
+#define IS_RF_MT6140C ( RF_ID==RF_ID_MT6140C )
+#define IS_RF_MT6140D ( RF_ID==RF_ID_MT6140D )
+#define IS_RF_CMOSEDGE ( RF_ID==RF_ID_CMOSEDGE )
+#define IS_RF_MTKSOC1 ( RF_ID==RF_ID_MTKSOC1 && CHIP_ID==CHIP_ID_MT6253 )
+#define IS_RF_MTKSOC1T ( RF_ID==RF_ID_MTKSOC1 && CHIP_ID==CHIP_ID_MT6253T )
+#define IS_RF_MT6253ELRF ( RF_ID==RF_ID_MT6252RF )
+#define IS_RF_MT6252RF ( RF_ID==RF_ID_MT6252RF )
+#define IS_RF_SKY74045 ( RF_ID==RF_ID_SKY74045 )
+#define IS_RF_SKY74117 ( RF_ID==RF_ID_SKY74117 )
+#define IS_RF_SKY74400 ( RF_ID==RF_ID_SKY74400 )
+#define IS_RF_AERO2 ( RF_ID==RF_ID_AERO2 )
+#define IS_RF_SKY74137 ( RF_ID==RF_ID_SKY74137 )
+#define IS_RF_GRF6201 ( RF_ID==RF_ID_GRF6201 )
+#define IS_RF_IRFS3001 ( RF_ID==RF_ID_IRFS3001 )
+#define IS_RF_AD6548 ( RF_ID==RF_ID_AD6548 )
+#define IS_RF_AD6546 ( RF_ID==RF_ID_AD6546 )
+#define IS_RF_MT6256RF ( RF_ID==RF_ID_MT6256RF )
+#define IS_RF_MT6255RF ( RF_ID==RF_ID_MT6255RF )
+#define IS_RF_MT6251RF ( RF_ID==RF_ID_MT6251RF )
+#define IS_RF_MT6162 ( ((defined RF_ID) && RF_ID==RF_ID_MT6162) || ((defined UL1D_RF_ID) && UL1D_RF_ID==UL1D_RF_ID_MT6162) )
+#define IS_RF_MT6163 ( RF_ID==RF_ID_MT6163 )
+#define IS_RF_MT6250RF ( RF_ID==RF_ID_MT6250RF )
+#define IS_RF_MT6280RF ( RF_ID==RF_ID_MT6280RF )
+#define IS_RF_MT6167 ( RF_ID==RF_ID_MT6167 )
+#define IS_RF_MT6166 ( RF_ID==RF_ID_MT6166 )
+#define IS_RF_MT6169 ( RF_ID==RF_ID_MT6169 )
+#define IS_RF_MT6165 ( RF_ID==RF_ID_MT6165 )
+#define IS_RF_MT6176 ( RF_ID==RF_ID_MT6176 )
+#define IS_RF_MT6179 ( RF_ID==RF_ID_MT6179 )
+#define IS_RF_MT6177L ( RF_ID==RF_ID_MT6177L )
+#define IS_RF_MT6177M ( RF_ID==RF_ID_MT6177M )
+#define IS_RF_TRINITYE1 ( RF_ID==RF_ID_TRINITYE1 )
+#define IS_RF_TRINITYL ( RF_ID==RF_ID_TRINITYL )
+#define IS_RF_MT6186 ( RF_ID==RF_ID_MT6186 )
+#define IS_RF_MT6186M ( RF_ID==RF_ID_MT6186M )
+#define IS_RF_MT6190T (( RF_ID==RF_ID_MT6190T )||( RF_ID==RF_ID_MT6190 )||( RF_ID==RF_ID_MT6190M )) || ( RF_ID == RF_ID_MT6195 )
+#define IS_RF_MT6190 (( RF_ID==RF_ID_MT6190 )||( RF_ID==RF_ID_MT6190M )) || ( RF_ID == RF_ID_MT6195 )
+#define IS_RF_MT6190M ( RF_ID==RF_ID_MT6190M )
+#define IS_RF_MT6195 ( RF_ID==RF_ID_MT6195 )
+
+/*.......................................................*/
+
+#ifndef RF_ID
+ #ifdef BRIGHT2_RF
+/*BRIGHT2*/ #define RF_ID RF_ID_BRIGHT2
+ #endif
+ #ifdef BRIGHT4_RF
+/*BRIGHT4*/ #define RF_ID RF_ID_BRIGHT4
+ #endif
+ #ifdef BRIGHT5P_RF
+/*BRIGHT5P*/#define RF_ID RF_ID_BRIGHT5P
+ #endif
+ #ifdef AERO_RF
+/*AERO*/ #define RF_ID RF_ID_AERO
+ #endif
+ #ifdef AERO1PLUS_RF
+/*AERO*/ #define RF_ID RF_ID_AERO1PLUS
+ #endif
+ #ifdef POLARIS1_RF
+/*RFMD*/ #define RF_ID RF_ID_POLARIS1
+ #endif
+ #ifdef MT6116_RF
+/*MT6116*/ #define RF_ID RF_ID_MT6116
+ #endif
+ #ifdef MT6119_RF
+/*MT6119*/ #define RF_ID RF_ID_MT6119
+ #endif
+ #ifdef MT6119C_RF
+/*MT6119*/ #define RF_ID RF_ID_MT6119C
+ #endif
+ #ifdef MT6129A_RF
+/*MT6129A*/ #define RF_ID RF_ID_MT6129A
+ #endif
+ #ifdef MT6129B_RF
+/*MT6129B*/ #define RF_ID RF_ID_MT6129B
+ #endif
+ #ifdef MT6129C_RF
+/*MT6129C*/ #define RF_ID RF_ID_MT6129C
+ #endif
+ #ifdef MT6129D_RF
+/*MT6129D*/ #define RF_ID RF_ID_MT6129D
+ #endif
+ #ifdef MT6139B_RF
+/*MT6139B*/ #define RF_ID RF_ID_MT6139B
+ #endif
+ #ifdef MT6139C_RF
+/*MT6139C*/ #define RF_ID RF_ID_MT6139C
+ #endif
+ #ifdef MT6139E_RF
+/*MT6139E*/ #define RF_ID RF_ID_MT6139E
+ #endif
+ #ifdef MT6140A_RF
+/*MT6140A*/ #define RF_ID RF_ID_MT6140A
+ #endif
+ #ifdef MT6140B_RF
+/*MT6140B*/ #define RF_ID RF_ID_MT6140B
+ #endif
+ #ifdef MT6140C_RF
+/*MT6140C*/ #define RF_ID RF_ID_MT6140C
+ #endif
+ #ifdef MT6140D_RF
+/*MT6140D*/ #define RF_ID RF_ID_MT6140D
+ #endif
+ #ifdef CMOSEDGE_RF
+/*CMOSEDGE*/#define RF_ID RF_ID_CMOSEDGE
+ #endif
+ #ifdef MTKSOC1_RF
+/*MTKSOC1*/ #define RF_ID RF_ID_MTKSOC1
+ #endif
+ #ifdef MT6256RF_RF
+/*MT6256RF*/#define RF_ID RF_ID_MT6256RF
+ #endif
+ #ifdef MT6255RF_RF
+/*MT6255RF*/#define RF_ID RF_ID_MT6255RF
+ #endif
+ #ifdef MT6250RF_RF
+/*MT6250RF*/#define RF_ID RF_ID_MT6250RF
+ #endif
+ #ifdef MT6280RF_2G_RF
+/*MT6280RF*/#define RF_ID RF_ID_MT6280RF
+ #endif
+ #ifdef MT6169_2G_RF
+/*MT6169*/ #define RF_ID RF_ID_MT6169
+ #endif
+ #ifdef MT6166_2G_RF
+/*MT6166*/ #define RF_ID RF_ID_MT6166
+ #endif
+ #ifdef MT6165_2G_RF
+/*MT6165*/ #define RF_ID RF_ID_MT6165
+ #endif
+ #ifdef MT6176_2G_RF
+/*MT6176*/ #define RF_ID RF_ID_MT6176
+ #endif
+ #ifdef MT6179_2G_RF
+/*MT6179*/ #define RF_ID RF_ID_MT6179
+ #endif
+ #ifdef MT6177L_2G_RF
+/*MT6177L*/ #define RF_ID RF_ID_MT6177L
+ #endif
+ #ifdef MT6177M_2G_RF
+/*MT6177M*/ #define RF_ID RF_ID_MT6177M
+ #endif
+ #ifdef TRINITYE1_2G_RF
+/*Trinity*/ #define RF_ID RF_ID_TRINITYE1
+ #endif
+ #ifdef TRINITYL_2G_RF
+/*Trinity*/ #define RF_ID RF_ID_TRINITYL
+ #endif
+ #ifdef MT6185M_2G_RF
+/*Trinity*/ #define RF_ID RF_ID_TRINITYL
+ #endif
+ #ifdef MT6186_2G_RF
+/*Trinity*/ #define RF_ID RF_ID_MT6186
+ #endif
+ #ifdef MT6186M_2G_RF
+/*Trinity*/ #define RF_ID RF_ID_MT6186M
+ #endif
+ #ifdef TRINITYE1_RF
+// #define RF_ID RF_ID_TRINITYE1
+ #endif
+ #ifdef MT6190T_2G_RF
+/*MT6190T*/ #define RF_ID RF_ID_MT6190T
+ #endif
+ #ifdef MT6190_2G_RF
+/*MT6190*/ #define RF_ID RF_ID_MT6190
+ #endif
+ #ifdef MT6190M_2G_RF
+/*MT6190M*/ #define RF_ID RF_ID_MT6190M
+ #endif
+ #ifdef MT6195_2G_RF
+/*COLUMBUSP*/ #define RF_ID RF_ID_MT6195
+ #endif
+ #ifdef MT6251RF_RF
+/*MT6251RF*/#define RF_ID RF_ID_MT6251RF
+ #endif
+ #ifdef MT6253ELRF_RF
+/*MT6253EL*/#define RF_ID RF_ID_MT6252RF
+ #endif
+ #ifdef MT6252RF_RF
+/*MT6252RF*/#define RF_ID RF_ID_MT6252RF
+ #endif
+ #ifdef SKY74045_RF
+/*SKY74045*/#define RF_ID RF_ID_SKY74045
+ #endif
+ #ifdef SKY74117_RF
+/*SKY74117*/#define RF_ID RF_ID_SKY74117
+ #endif
+ #ifdef SKY74400_RF
+/*SKY74400*/#define RF_ID RF_ID_SKY74400
+ #endif
+ #ifdef AERO2_RF
+/*AERO2*/ #define RF_ID RF_ID_AERO2
+ #endif
+ #ifdef SKY74137_RF
+/*SKY74137*/#define RF_ID RF_ID_SKY74137
+ #endif
+ #ifdef GRF6201_RF
+/*GRF6201*/ #define RF_ID RF_ID_GRF6201
+ #endif
+ #ifdef IRFS3001_RF
+/*IRFS3001*/#define RF_ID RF_ID_IRFS3001
+ #endif
+ #ifdef AD6548_RF
+/*AD6548*/ #define RF_ID RF_ID_AD6548
+ #endif
+ #ifdef AD6546_RF
+/*AD6546*/ #define RF_ID RF_ID_AD6546
+ #endif
+ #ifdef MT6162_RF
+/*MT6162*/ #define RF_ID RF_ID_MT6162
+ #endif
+ #ifdef MT6163_2G_RF
+/*MT6163*/ #define RF_ID RF_ID_MT6163
+ #endif
+ #ifdef MT6168_2G_RF
+/*MT6163*/ #define RF_ID RF_ID_MT6163
+ #endif
+ #ifdef MT6162_DUAL_RF /* This is used just for TK6280 FPGA from Jay's request */
+/*MT6162*/ #define RF_ID RF_ID_MT6162
+ #endif
+#endif
+
+/* default setting */
+#ifndef RF_ID
+/*BRIGHT2*/ #define RF_ID RF_ID_BRIGHT2
+#endif
+/*...........................................................................................................*/
+
+#define IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT 1
+
+#if defined(L1_SIM) && IS_CHIP_MT6292
+#undef IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT
+#define IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT 0
+#endif
+
+#if IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT
+ #if IS_BPI_DATA_48_BIT_CHIP
+ #error "dynamic allocation does not support 48 bits BPI"
+ #endif
+#endif
+
+#if IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT && IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_GL1D_CDF_SUPPORT 1
+#else
+#define IS_GL1D_CDF_SUPPORT 0
+#endif
+
+
+#define TURN_ON_PHONE_CALL_TRACE 0 //mtk13381
+#define l1D_RXDFE_RCC_SYN_REG_SW_CNTRL 0
+#define L1D_BASEBAND_MT6297_CHANGES 0 //mtk10455
+#define TURN_ON_PHONE_CALL_TRACE_97 1 //debug trace for 97
+
+//Usip restart process same as fd 216 flow
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_L1D_MML1_LPWR_DSP_ENABLE 1
+#else
+#define IS_L1D_MML1_LPWR_DSP_ENABLE 0
+#endif
+
+#if defined(L1D_SIM)
+#define IS_GSIM_PATTERN_CHECK_ENABLE 0
+#else
+#define IS_GSIM_PATTERN_CHECK_ENABLE 0
+#endif
+
+/*===================================================================*/
+/* CHIP Feature settings */
+/*===================================================================*/
+#if defined(__UMTS_NEW_ARCH__)
+#define L1D_WT_COBIN_ARCHITECTURE_SUPPORT 1
+#define L1D_WT_COBIN_RUNTIME_SWITCH_SUPPORT 1
+#else
+#define L1D_WT_COBIN_ARCHITECTURE_SUPPORT 0
+#define L1D_WT_COBIN_RUNTIME_SWITCH_SUPPORT 0
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+ #if defined(L1_SIM) || (IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297)
+#define IS_GL1D_TW_COEXIST_SUPPORT 1 /* This feature can support W and T in SIM1. SIM2 is always W */
+ #else
+#define IS_GL1D_TW_COEXIST_SUPPORT 0
+ #endif /* IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 */
+#else
+#define IS_GL1D_TW_COEXIST_SUPPORT 0
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT || L1D_WT_COBIN_RUNTIME_SWITCH_SUPPORT
+#define L1D_WT_COBIN_UT_BEBUG 0
+ #if defined(__UMTS_FDD_MODE__) && !defined(__UMTS_TDD128_MODE__)
+#define L1D_WT_COBIN_UT_W_ONLY_BUILD 1
+ #else
+#define L1D_WT_COBIN_UT_W_ONLY_BUILD 0
+ #endif
+ #if !defined(__UMTS_FDD_MODE__) && defined(__UMTS_TDD128_MODE__)
+#define L1D_WT_CBBIN_UT_T_ONLY_BUILD 1
+ #else
+#define L1D_WT_CBBIN_UT_T_ONLY_BUILD 0
+ #endif
+#else
+#define L1D_WT_COBIN_UT_BEBUG 0
+#define L1D_WT_COBIN_UT_W_ONLY_BUILD 0
+#define L1D_WT_CBBIN_UT_T_ONLY_BUILD 0
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT && L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD
+ #if !defined(__UMTS_FDD_MODE__)
+#define __UMTS_FDD_MODE__ 1
+ #endif
+ #if !defined(__MTK_UL1_FDD__)
+#define __MTK_UL1_FDD__ 1
+ #endif
+ #if !defined(__AST_TL1_TDD__)
+#define __AST_TL1_TDD__ 1
+ #endif
+ #if !defined(__UMTS_TDD128_MODE__)
+#define __UMTS_TDD128_MODE__ 1
+ #endif
+#endif
+
+#if defined(L1D_SIM) && defined(L1D_TEST) && (IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6260)||IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1))
+#define IS_COSIM_ON_L1SIM_SUPPORT 1
+#define IS_COSIM_ON_L1SIM_BYPASS_RF 1
+#else
+#define IS_COSIM_ON_L1SIM_SUPPORT 0
+#define IS_COSIM_ON_L1SIM_BYPASS_RF 0
+#endif
+
+#if (IS_CHIP_MT6227_AND_LATTER_VERSION && !IS_CHIP_MT6227_S00 && !IS_CHIP_MT6228_S00 && !IS_CHIP_MT6228_S01) || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01)
+#define L1D_PCH_2BURST_DECODE 1
+#else
+#define L1D_PCH_2BURST_DECODE 0
+#endif
+
+#if IS_CHIP_MT6227_D00 || IS_CHIP_MT6225_AND_LATTER_VERSION || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01)
+ #if defined(__MA_L1__) // MONZA29 and VENUS do not suppport PCH_1BURST_DECODE
+#define L1D_PCH_1BURST_DECODE 0
+ #else
+ #if IS_CHIP_MT6223 && defined(L1D_TEST)
+#define L1D_PCH_1BURST_DECODE 0
+ #else
+#define L1D_PCH_1BURST_DECODE 1
+ #endif
+ #endif
+ #if IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION
+#define L1D_PCH_EMPTY_PATTERN 1
+ #else
+#define L1D_PCH_EMPTY_PATTERN 0
+ #endif
+#else
+#define L1D_PCH_1BURST_DECODE 0
+#define L1D_PCH_EMPTY_PATTERN 0
+#endif
+
+#if L1D_PCH_1BURST_DECODE
+ #ifdef __MONITOR_PAGE_DURING_TRANSFER__
+ #if IS_NEW_L1D_ARCH_SUPPORT
+ #if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 1
+ #elif defined(__UMTS_TDD128_MODE__)
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 0
+ #else
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 1
+ #endif
+ #else
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 1
+ #endif
+ #else
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 0
+ #endif
+#else
+#define L1D_MONITOR_PAGE_DURING_TRANSFER_SUPPORT 0
+#endif
+
+#if defined (__COTMS_TELEMATICS_SUPPORT__)
+#define IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT 1
+#define IS_TELEMATICS_HIGH_TEMPERATURE_SUPPORT 1
+#else
+#define IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT 0
+#define IS_TELEMATICS_HIGH_TEMPERATURE_SUPPORT 0
+#endif /* __COTMS_TELEMATICS_SUPPORT__ */
+
+#if IS_AFC_CAPABILITY_ENHANCEMENT_SUPPORT
+ #if IS_TELEMATICS_HIGH_TEMPERATURE_SUPPORT
+#define TURN_ON_TELEMATICS_TRACE 1
+ #endif
+#endif
+
+/* Add for short PM */
+#if IS_GPRS
+#define L1D_PM_ENHANCE 1
+ #if IS_CHIP_MT6227_D00 || IS_CHIP_MT6225_AND_LATTER_VERSION || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01)
+ #if defined(__MA_L1__) // MONZA29 and VENUS do not suppport 1R7PM
+#define L1D_PM_1R7PM 0
+ #else
+ #if IS_CHIP_MT6223 && defined(L1D_TEST)
+#define L1D_PM_1R7PM 0
+ #else
+#define L1D_PM_1R7PM 1
+ #endif
+ #endif
+ #else
+#define L1D_PM_1R7PM 0
+ #endif
+#else // IS_GSM
+ #if IS_HW_8RXWIN_PM_SUPPORT_CHIP
+#define L1D_PM_ENHANCE 1
+#define L1D_PM_1R7PM 1
+ #else
+#define L1D_PM_ENHANCE 0
+#define L1D_PM_1R7PM 0
+ #endif
+#endif
+
+#if IS_GPRS || L1D_PM_ENHANCE
+#define IS_RTX_5CWIN_SUPPORT 1
+#else
+#define IS_RTX_5CWIN_SUPPORT 0
+#endif
+
+/*Repeated ACCH*/
+#if IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION
+#define IS_REPEATED_ACCH_SUPPORT 1
+#else
+#define IS_REPEATED_ACCH_SUPPORT 0
+#endif
+
+#if defined(FOUNTAIN2_EVB) || defined(MT6129A_EVB)
+#define RFVCO_SW_CONTROL
+#endif
+
+#if IS_SAIC_CHIP_MT6223_AND_LATTER_VERSION
+#define FILLING_BYTES_2ND_DECODE
+#endif
+
+#ifdef __HO_IMPROVE__
+#define NONSYNC_HO_IMPROVEMENT
+#endif
+
+#if IS_FD216_DSP_CHIP
+ #if IS_CHIP_MT6268T || IS_CHIP_MT6268 || IS_EDGE_SAIC_CHIP_MT6236_AND_LATTER_VERSION
+#define IS_UPDATE_TIMESTAMP_FOR_DSP_CHIP 1
+ #else
+#define IS_UPDATE_TIMESTAMP_FOR_DSP_CHIP 0
+ #endif
+#else
+#define IS_UPDATE_TIMESTAMP_FOR_DSP_CHIP 1
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION
+#define IS_PM_DONE_CHECK_SUPPORT 1
+#elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+ #if defined(L1_SIM)
+#define IS_PM_DONE_CHECK_SUPPORT 1
+ #else
+#define IS_PM_DONE_CHECK_SUPPORT 0
+ #endif
+#else
+#define IS_PM_DONE_CHECK_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6238_AND_LATTER_VERSION && !IS_CHIP_TK6516
+#define IS_HYBRID_SAIC_SUPPORT 1
+#else
+#define IS_HYBRID_SAIC_SUPPORT 0
+#endif
+
+#if defined(__GEMINI__)
+
+#if defined(L1_SIM)
+ #ifdef IS_GEMINI_SUPPORT
+ #undef IS_GEMINI_SUPPORT
+ #endif
+#endif
+
+#define IS_GEMINI_SUPPORT 1
+#else
+#define IS_GEMINI_SUPPORT 0
+#endif
+
+#if IS_GEMINI_SUPPORT
+ #ifdef GEMINI_PLUS_GSM
+#define NUM_OF_SIM GEMINI_PLUS_GSM
+ #else
+#define NUM_OF_SIM 2
+ #endif
+#else
+#define NUM_OF_SIM 1
+#endif
+
+#define IS_GEMINI_1_2_SUPPORT 1 /*Gemini 1.2*/
+
+#if defined(__GEMINI__) && defined(__UMTS_FDD_MODE__)
+#define IS_GEMINI_WGG_SUPPORT 1 /*WG+G*/
+#else
+#define IS_GEMINI_WGG_SUPPORT 0
+#endif
+
+#if defined(__GEMINI__) && defined(__UMTS_TDD128_MODE__)
+#define IS_GEMINI_TGG_SUPPORT 1 /*TG+G*/
+#else
+#define IS_GEMINI_TGG_SUPPORT 0
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+
+ #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_GEMINI_WGG_SUPPORT
+#undef IS_GEMINI_TGG_SUPPORT
+#define IS_GEMINI_TGG_SUPPORT 1
+ #endif
+ #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_GEMINI_TGG_SUPPORT
+#undef IS_GEMINI_WGG_SUPPORT
+#define IS_GEMINI_WGG_SUPPORT 1
+ #endif
+
+ #if (IS_GEMINI_WGG_SUPPORT && !IS_GEMINI_TGG_SUPPORT) || (!IS_GEMINI_WGG_SUPPORT && IS_GEMINI_TGG_SUPPORT)
+ #if L1D_WT_COBIN_UT_W_ONLY_BUILD || L1D_WT_CBBIN_UT_T_ONLY_BUILD
+ #else
+#error "IS_GEMINI_WGG_SUPPORT and IS_GEMINI_TGG_SUPPORT should be aligned with WT Co-bin feature!"
+ #endif
+ #endif
+#endif
+
+#if defined(__GEMINI_WCDMA__)
+#define IS_GEMINI_WCDMA_SUPPORT 1
+#else
+#define IS_GEMINI_WCDMA_SUPPORT 0
+#endif
+
+#if IS_GEMINI_SUPPORT
+ #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_FORCE_ENHENCE_PM_SUPPORT 1
+ #else
+#define IS_FORCE_ENHENCE_PM_SUPPORT 0
+ #endif
+#else
+#define IS_FORCE_ENHENCE_PM_SUPPORT 0
+#endif
+#if defined(__MTK_TARGET__)
+ #if IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_SB_ENHANCE_TRACE_SUPPORT 1
+ #else
+#define IS_SB_ENHANCE_TRACE_SUPPORT 0
+ #endif
+#else
+#define IS_SB_ENHANCE_TRACE_SUPPORT 0
+#endif
+
+// workaround for APC HW bug, APC cannot work when DCM with 13M. In RFTOOL mode, L1D need to disable DCM by itself
+#if IS_CHIP_MT6227 || IS_CHIP_MT6228
+#define IS_RFTOOL_MODE_DCM_DISABLE 1
+#define IS_IDLE_MODE_TX_DCM_26M 1
+#else
+#define IS_RFTOOL_MODE_DCM_DISABLE 0
+#define IS_IDLE_MODE_TX_DCM_26M 0
+#endif
+
+#if IS_CHIP_MT6268
+#define IS_HANDLE_TX_DCM_SUPPORT 1
+#else
+#define IS_HANDLE_TX_DCM_SUPPORT 0
+#endif
+
+#if defined(L1D_TEST) // loopback no APC/BSI issue
+#undef IS_RFTOOL_MODE_DCM_DISABLE
+#undef IS_IDLE_MODE_TX_DCM_26M
+#undef IS_HANDLE_TX_DCM_SUPPORT
+#define IS_RFTOOL_MODE_DCM_DISABLE 0
+#define IS_IDLE_MODE_TX_DCM_26M 0
+#define IS_HANDLE_TX_DCM_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_CHIP_MT6252
+#define __NEW_L1D_ARCH__
+#endif
+
+#if IS_COSIM_ON_L1SIM_SUPPORT
+#elif defined(L1D_TEST) // loopback not ready for NEW L1D ARCH
+#undef __NEW_L1D_ARCH__
+#endif
+
+// new AGC/AFC update scheme
+#if defined(__NEW_L1D_ARCH__)
+#define IS_NEW_L1D_ARCH_SUPPORT 1
+ #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_CHIP_MT6252
+#define IS_NEW_L1D_ARCH_6R_SUPPORT 0
+#define IS_NEW_L1D_ARCH_8R_SUPPORT 1
+ #else
+#define IS_NEW_L1D_ARCH_6R_SUPPORT 1
+#define IS_NEW_L1D_ARCH_8R_SUPPORT 0
+ #endif
+ #if IS_CHIP_MT6256_S00
+#define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0
+ #elif IS_CHIP_MT6256
+#define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0
+ #else
+#define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0
+ #endif
+#else
+#define IS_NEW_L1D_ARCH_SUPPORT 0
+#define IS_NEW_L1D_ARCH_6R_SUPPORT 0
+#define IS_NEW_L1D_ARCH_8R_SUPPORT 0
+#define IS_NEW_L1D_ARCH_3R_USF_SUPPORT 0
+#endif
+
+#define IS_OLD_L1D_ARCH_SUPPORT !IS_NEW_L1D_ARCH_SUPPORT
+
+#if defined(L1_SIM) && IS_NEW_L1D_ARCH_8R_SUPPORT
+#undef IS_NEW_TDMA_CHIP
+#undef IS_HW_8RXWIN_PM_SUPPORT_CHIP
+#define IS_NEW_TDMA_CHIP 1
+#define IS_HW_8RXWIN_PM_SUPPORT_CHIP 1
+#endif
+
+#if IS_OLD_L1D_ARCH_SUPPORT && IS_HYPER_SLEEP_MODE_CHIP
+#define IS_OLD_L1D_ARCH_NEW_SLEEP_SUPPORT 1
+#else
+#define IS_OLD_L1D_ARCH_NEW_SLEEP_SUPPORT 0
+#endif
+
+// GSM mode slot2, slot3 CCCH handling
+#if IS_GPRS
+#define IS_GSM_ONLY_HANDLE_R23_SUPPORT 0
+#else
+ #if IS_NEW_L1D_ARCH_SUPPORT
+#define IS_GSM_ONLY_HANDLE_R23_SUPPORT 0
+ #else
+#define IS_GSM_ONLY_HANDLE_R23_SUPPORT 1
+ #endif
+#endif
+
+/* 3G RF chip preotection */
+#if defined(__MTK_UL1_FDD__) && !defined(L1_SIM) && !defined(L1D_TEST) && !defined(UL1D_TEST)
+ #ifdef MT6160_RF
+#define IS_3GRF_DETECT 1
+ #else
+#define IS_3GRF_DETECT 0
+ #endif
+#else
+#define IS_3GRF_DETECT 0
+#endif
+
+/* Align ul1d_cid.h*/
+#ifdef MT6160_RF
+#define RF_3G_ID_Rev2p1 0x000000F9
+#define RF_3G_ID_Rev3p0 0x000000EF
+#endif
+
+#if IS_CHIP_MT6276_S00 && defined(__UMTS_RAT__) && !defined(L1D_TEST) // only for MT6276E1
+#define IS_MT6276_ADCMUX_CHECK_CHIP 1
+#else
+#define IS_MT6276_ADCMUX_CHECK_CHIP 0
+#endif
+
+#if IS_CHIP_MT6276_S00 && IS_RF_MT6162
+#undef IS_MT6276_ADCMUX_CHECK_CHIP
+#define IS_MT6276_ADCMUX_CHECK_CHIP 0
+#endif
+
+#if IS_CHIP_MT6276_S01 && defined(__UMTS_RAT__) && !defined(L1D_TEST) // only for MT6276E2
+#define IS_MT6276_DACMODE_CHECK_CHIP 1
+#else
+#define IS_MT6276_DACMODE_CHECK_CHIP 0
+#endif
+
+#if IS_CHIP_MT6276 || IS_CHIP_MT6573
+#define IS_MD2G_LOGGER_SUPPORT_CHIP 1
+#else
+#define IS_MD2G_LOGGER_SUPPORT_CHIP 0
+#endif
+
+#if defined(__CACHED_BASE_DSP__)
+#define IS_CACHE_DSP_SUPPORT 1
+#else
+#define IS_CACHE_DSP_SUPPORT 0
+#endif
+
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define DSP_ARCHITECTURE_VERSION 4
+#elif IS_CACHE_DSP_SUPPORT
+#define DSP_ARCHITECTURE_VERSION 3
+#elif IS_DUAL_MAC_DSP_CHIP
+#define DSP_ARCHITECTURE_VERSION 2
+#else
+#define DSP_ARCHITECTURE_VERSION 1
+#endif
+
+#define IS_DSP_ARCHITECTURE_V1_SUPPORT (DSP_ARCHITECTURE_VERSION==1)
+#define IS_DSP_ARCHITECTURE_V2_SUPPORT (DSP_ARCHITECTURE_VERSION==2)
+#define IS_DSP_ARCHITECTURE_V3_SUPPORT (DSP_ARCHITECTURE_VERSION==3)
+#define IS_DSP_ARCHITECTURE_V4_SUPPORT (DSP_ARCHITECTURE_VERSION==4)
+
+// DSP Watchdog configuration
+#if IS_CHIP_MT6225_AND_LATTER_VERSION || (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION && !IS_CHIP_MT6229_S00 && !IS_CHIP_MT6229_S01)
+#define IS_DSP_WATCHDOG 1
+ #if IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION
+#define IS_DSP2_WATCHDOG 1
+ #else
+#define IS_DSP2_WATCHDOG 0
+ #endif
+#else
+#define IS_DSP_WATCHDOG 0
+#define IS_DSP2_WATCHDOG 0
+#endif
+
+#if !IS_DUAL_DSP_CHIP
+#undef IS_DSP2_WATCHDOG
+#define IS_DSP2_WATCHDOG 0
+#endif
+
+/* For 65NM IRDBG bug group*/ /* MT6268A, MT6516E0 has this bug */
+#if IS_CHIP_MT6268A // only for MT6268A FT Test, CM is not protected so we have this solution
+#define IS_IRDBG_SW_WORKAROUND 1
+#else
+#define IS_IRDBG_SW_WORKAROUND 0
+#endif
+
+/* Disable 65NM in L1Sim */
+#if IS_COSIM_ON_L1SIM_SUPPORT
+#elif defined(L1_SIM)
+#undef IS_65NM_CHIP
+#define IS_65NM_CHIP 0
+#endif
+
+/* For Support Centralized Sleep Mode Manager Group */
+/* We used to define IS_CENTRALIZED_SMM_CHIP as chip option */
+/* It's better to align with feature option */
+#if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_CENTRALIZED_SMM_CHIP 1
+#else
+#define IS_CENTRALIZED_SMM_CHIP 0
+#endif
+
+#if defined(ESIM_BUILD_CONFIG) && (ESIM_BUILD_CONFIG == ESIM_MULTI_MODE_ON_FIBERS) && defined(MTK_SLEEP_ENABLE)
+#define IS_TDMAIRQ_TIMING_CHECK_BYPASS_SUPPORT 1
+#elif ( IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6582 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 ) && defined(MTK_SLEEP_ENABLE)
+#define IS_TDMAIRQ_TIMING_CHECK_BYPASS_SUPPORT 1
+#else
+#define IS_TDMAIRQ_TIMING_CHECK_BYPASS_SUPPORT 0
+#endif
+
+/* Dual Mode Chip should always use SW_MODE, MT6516 has problem with HW_MODE */
+#if IS_65NM_CHIP
+ #if IS_CHIP_MT6268 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6251 || IS_CHIP_MT6575 || IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+ #if defined(MT6516_S00) || IS_CHIP_MT6251_S00 || IS_CHIP_MT6256_S00
+#define IS_MD2G_PWD_SUPPORT 0
+ #else
+#define IS_MD2G_PWD_SUPPORT 1
+ #endif
+ #if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_MD2G_PWD_DEFAULT_SW_MODE 0
+ #else
+#define IS_MD2G_PWD_DEFAULT_SW_MODE 1
+ #endif
+#define IS_IRDBG_LOG_STATUS 1
+ #else
+#define IS_MD2G_PWD_SUPPORT 0
+#define IS_MD2G_PWD_DEFAULT_SW_MODE 0
+#define IS_IRDBG_LOG_STATUS 1
+ #endif
+
+ #if IS_CHIP_MT6268 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6251 || IS_CHIP_MT6575 || IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250 //Later chip should apply new control flow
+#define IS_NEW_MD2G_PWD_CONTROL_SUPPORT 0
+ #else //For MT6280 and later chip
+#define IS_NEW_MD2G_PWD_CONTROL_SUPPORT 1
+ #endif
+
+ #if IS_CHIP_MT6268 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6256_S00
+#define IS_BACKUP_DPRAM_CHIP 1
+#define IS_RESTORE_PATCH_RAM_CHIP 1
+ #else
+#define IS_BACKUP_DPRAM_CHIP 0
+#define IS_RESTORE_PATCH_RAM_CHIP 0
+ #endif
+
+ #if IS_CHIP_MT6251_S00 && defined(L1D_TEST)
+#undef IS_BACKUP_DPRAM_CHIP
+#undef IS_RESTORE_PATCH_RAM_CHIP
+#define IS_BACKUP_DPRAM_CHIP 1
+#define IS_RESTORE_PATCH_RAM_CHIP 1
+ #endif
+
+ #if IS_CENTRALIZED_SMM_CHIP
+#define IS_MD2G_STANDALONE_MTCMOS_CHIP 1
+ #elif defined(__UMTS_RAT__) // 68 MD2G MTCMOS
+#define IS_MD2G_STANDALONE_MTCMOS_CHIP 0
+ #else
+#define IS_MD2G_STANDALONE_MTCMOS_CHIP 1
+ #endif
+
+ #if IS_CHIP_MT6575
+ #if defined(__UMTS_RAT__) && defined(__MTK_UL1_FDD__)
+#define IS_DEFAULT_TURNOFF_3GMTCMOS 0
+ #else
+#define IS_DEFAULT_TURNOFF_3GMTCMOS 1
+ #endif
+ #else
+#define IS_DEFAULT_TURNOFF_3GMTCMOS 0
+ #endif
+#endif
+
+#if defined(MTK_SLEEP_ENABLE) && IS_65NM_CHIP && IS_DSP_ARCHITECTURE_V4_SUPPORT
+ #if IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DSP_INIT_FLOW_V2_SUPPORT 1
+ #else
+#define IS_DSP_INIT_FLOW_V2_SUPPORT 0
+ #endif
+#else
+#define IS_DSP_INIT_FLOW_V2_SUPPORT 0
+#endif
+#if (L1D_TEST)
+#undef IS_DSP_INIT_FLOW_V2_SUPPORT
+#define IS_DSP_INIT_FLOW_V2_SUPPORT 0
+#endif
+#if IS_DSP_INIT_FLOW_V2_SUPPORT
+ #if IS_BACKUP_DPRAM_CHIP || IS_RESTORE_PATCH_RAM_CHIP || IS_COMPARE_DPRAM_CHIP
+#error "IS_DSP_INIT_FLOW_V2_SUPPORT does not support these feature."
+ #endif
+#else
+ #if IS_CHIP_MT6280
+#define IS_AFE_PRESENT 0
+ #else
+#define IS_AFE_PRESENT 1
+ #endif
+#endif
+
+#if defined(__2G_FAST_TIMING_ADJUST_SUPPORT__)
+#define IS_FAST_TIMING_ADJUST_SUPPORT 1
+#else
+#define IS_FAST_TIMING_ADJUST_SUPPORT 0
+#endif
+
+#if defined(__2G_FAST_TIMING_ADJUST_ENABLE__)
+#define IS_FAST_TIMING_ADJUST_ENABLE 1
+#else
+#define IS_FAST_TIMING_ADJUST_ENABLE 0
+#endif
+
+// For SOC chip MPLL FH Feature
+#if (IS_SOC_CHIP && !defined(__L1D_SOC_NO_MPLLFH__)) || IS_CHIP_MT6236 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MPLL_FH_SUPPORT 1
+ #if IS_CHIP_MT6252_S00
+#define IS_MPLL_FH_V2 0
+#define IS_MPLL_TX_RULE_CHECKED 0
+#define IS_SPLL_FH_SUPPORT 0
+#define IS_SPLL_FH_V2 0
+ #elif IS_CHIP_MT6252
+#define IS_MPLL_FH_V2 1
+#define IS_MPLL_TX_RULE_CHECKED 1
+#define IS_SPLL_FH_SUPPORT 1
+#define IS_SPLL_FH_V2 1
+ #else
+#define IS_MPLL_FH_V2 0
+#define IS_MPLL_TX_RULE_CHECKED 0
+#define IS_SPLL_FH_SUPPORT 0
+#define IS_SPLL_FH_V2 0
+ #endif
+#else
+#define IS_MPLL_FH_SUPPORT 0
+#define IS_MPLL_FH_V2 0
+#define IS_MPLL_TX_RULE_CHECKED 0
+#define IS_SPLL_FH_SUPPORT 0
+#define IS_SPLL_FH_V2 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+#define IS_MPLLFH_FREE_RUN_SUPPORT_CHIP 1
+#else
+#define IS_MPLLFH_FREE_RUN_SUPPORT_CHIP 0
+#endif
+
+#if IS_MPLLFH_FREE_RUN_SUPPORT_CHIP
+ #if IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_MPLLFH_FREE_RUN_ON 1
+ #elif IS_CHIP_MT6251
+#define IS_MPLLFH_FREE_RUN_ON 0
+ #else
+#define IS_MPLLFH_FREE_RUN_ON 0
+ #endif
+#else
+#define IS_MPLLFH_FREE_RUN_ON 0
+#endif
+
+#if defined(L1_SIM)
+#undef IS_MPLL_FH_SUPPORT
+#define IS_MPLL_FH_SUPPORT 0
+#endif
+
+#ifdef __CYCLIC_MPLLFH__
+#define IS_MPLL_CYCLIC_FH_SUPPORT 1
+#else
+#define IS_MPLL_CYCLIC_FH_SUPPORT 0
+#endif
+
+#ifdef __FIXED_MPLLFH__
+#define IS_MPLL_FIXED_LOWEST_SUPPORT 1
+#define IS_SPLL_FIXED_LOWEST_SUPPORT 1
+#else
+#define IS_MPLL_FIXED_LOWEST_SUPPORT 0
+#define IS_SPLL_FIXED_LOWEST_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6276_S00 // For MT6276E1 MPLL FH, MT6276E1 has only partial FH
+#define IS_MT6276E1_TEMP_MPLL_FH_SUPPORT 1
+#else
+#define IS_MT6276E1_TEMP_MPLL_FH_SUPPORT 0
+#endif
+
+#if defined(L1_SIM)
+#undef IS_MT6276E1_TEMP_MPLL_FH_SUPPORT
+#define IS_MT6276E1_TEMP_MPLL_FH_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6276_S01
+#define IS_MT6276_FREERUN_SUPPORT 1
+#else
+#define IS_MT6276_FREERUN_SUPPORT 0
+#endif
+
+#if defined(L1_SIM)
+#undef IS_MT6276_FREERUN_SUPPORT
+#define IS_MT6276_FREERUN_SUPPORT 0
+#endif
+
+#if IS_MPLL_FH_SUPPORT
+ #if IS_CHIP_MT6251
+#define IS_MPLL_DYNAMIC_FH_SUPPORT 1
+ #else
+#define IS_MPLL_DYNAMIC_FH_SUPPORT 0
+ #endif
+#endif
+
+#if IS_SOC_CHIP
+#define TX_DCOC_RF_LOOPBACK 1
+#else
+#define TX_DCOC_RF_LOOPBACK 0
+#endif
+
+// if need 33 sections calibration
+#if IS_CHIP_MT6253
+#define IS_VCXO_LC_NEED 1
+#else
+#define IS_VCXO_LC_NEED 0
+#endif
+
+// AFC linear compensation support
+#if IS_VCXO_LC_NEED
+#define IS_VCXO_LC_SUPPORT 1
+ #if IS_CHIP_MT6252
+#define IS_VCXO_LC_TRXOFFSET_COMPENSATE_SUPPORT 1
+ #else
+#define IS_VCXO_LC_TRXOFFSET_COMPENSATE_SUPPORT 0
+ #endif
+#else
+#define IS_VCXO_LC_SUPPORT 0
+#define IS_VCXO_LC_TRXOFFSET_COMPENSATE_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6251 || IS_CHIP_MT6252 || IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_TWO_STEP_AFC_TRACKING_SUPPORT 1
+#else
+#define IS_TWO_STEP_AFC_TRACKING_SUPPORT 0
+#endif
+
+// PM with DSP2MCU Interrupt
+#if IS_EDGE_SAIC_CHIP_MT6268_AND_LATTER_VERSION
+#define IS_PM_DSP2MCU_SUPPORT 1
+#else
+#define IS_PM_DSP2MCU_SUPPORT 0
+#endif
+
+// For feature of split binary: MAUI/FACTORY bin
+#if defined(__FACTORY_BIN__) || !defined(__SPLIT_BINARY__)
+#define IS_FOR_FACTORY_MODE_ONLY 1
+#else
+// This case means only __SPLIT_BINARY__ is defined, which is used for generating MAUI bin.
+#define IS_FOR_FACTORY_MODE_ONLY 0
+#endif
+
+// Fast Handset Calibration (FHC) Support
+#if IS_FOR_FACTORY_MODE_ONLY && (IS_CHIP_MT6229 || IS_CHIP_MT6238 || IS_CHIP_MT6223 || IS_CHIP_MT6253 || IS_CHIP_MT6225 || IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_CHIP_MT6268 || IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION)
+#define IS_FHC_SUPPORT 1
+#else
+#define IS_FHC_SUPPORT 0
+#endif
+
+// Non-Signaling Final Test (NSFT) Support
+#if IS_FOR_FACTORY_MODE_ONLY
+#define IS_NSFT_SUPPORT 1
+#else
+#define IS_NSFT_SUPPORT 0
+#endif
+
+// Single-End BER Support
+#if IS_NSFT_SUPPORT
+#define IS_SINGLE_END_BER_SUPPORT 1
+#define IS_NSFT_SACCH_TEST_ITEM_SUPPORT 1
+#else
+#define IS_SINGLE_END_BER_SUPPORT 0
+#define IS_NSFT_SACCH_TEST_ITEM_SUPPORT 0
+#endif
+
+//add __UMTS_RAT__, because for 2G Only target, control buffer size = 2K/4K, L1_ALLOC_BUF(sizeof(NsftList_CMD_Q_ENTRY_T)*NsftList_MAX_CMD_QUEUE_SIZE) will overflow
+// size define can reference to "interface/service/config/kal_user_mem.h" 2G only case: RPS_CREATED_CTRL_BUFF_POOLS=8, custom_ctrl_num_buff_pool_size=4096
+// Note: even if MAX support size=4KB, it may only 2K buffer can use, the supported buffer number of every size pool are decided by project
+#if IS_NSFT_SUPPORT && IS_EPSK_TX_SUPPORT && (defined(__UMTS_RAT__))
+#define IS_NSFT_LIST_MODE_SUPPORT 1
+#else
+#define IS_NSFT_LIST_MODE_SUPPORT 0
+#endif
+
+// MS Capability v2.0
+#if 1 // use v2.0 by default
+#define IS_MS_CAPABILITY_V2_SUPPORT 1
+#else
+/* under construction !*/
+#endif
+
+// Multi-slot TX Support in GSM only
+#if IS_FHC_SUPPORT && IS_GSM
+ #if 0 // TBD
+/* under construction !*/
+ #else
+#define IS_MULTISLOT_TX_SUPPORT 0
+ #endif
+#else
+#define IS_MULTISLOT_TX_SUPPORT 0
+#endif
+
+// FWBW-DCOC support: including DSP FWBW DCOC support and L1 alpha filtering enhance FWBW DCOC feature
+#if (IS_SAIC_CHIP_MT6253_AND_LATTER_VERSION && !IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION) || IS_CHIP_MT6583_MD2
+// MT6583 modem 2 is the DCR architecture
+ #if defined(L1D_TEST)
+#define IS_FWBW_DCOC_SUPPORT 0
+#define IS_AM_SUPPRESSION_ALPHA_FILTERING_SUPPORT 0
+ #else
+#define IS_FWBW_DCOC_SUPPORT 1
+#define IS_AM_SUPPRESSION_ALPHA_FILTERING_SUPPORT 1
+ #endif
+#else
+#define IS_FWBW_DCOC_SUPPORT 0
+#define IS_AM_SUPPRESSION_ALPHA_FILTERING_SUPPORT 0
+#endif
+
+// Force 2G TDMA and/or RF NO Sleep
+#if IS_CHIP_MT6268A
+#define IS_2G_TDMA_RF_NO_SLEEP 0 // 1
+#else
+#define IS_2G_TDMA_RF_NO_SLEEP 0
+#endif
+
+// Define TDMA/RF no Sleep default setting
+#if IS_2G_TDMA_RF_NO_SLEEP
+ #if IS_CHIP_MT6268A
+#define IS_2G_TDMA_NO_SLEEP 1
+#define IS_2G_RF_NO_SLEEP 0
+ #else
+#define IS_2G_TDMA_NO_SLEEP 0
+#define IS_2G_RF_NO_SLEEP 0
+ #endif
+#else
+#define IS_2G_TDMA_NO_SLEEP 0
+#define IS_2G_RF_NO_SLEEP 0
+#endif
+
+#if IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_SLEEP_DSPCLK_GATE 0
+#elif IS_CHIP_MT6516 || IS_CHIP_MT6236 || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+#define IS_SLEEP_DSPCLK_GATE 1
+#else
+#define IS_SLEEP_DSPCLK_GATE 0
+#endif
+
+#if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2
+#define IS_SLEEP_HW_DIVIDER_INIT 1
+#else
+// For MT6280, MT6572/82, and later chips, the divider will be turned on or off by DIVIDE() and MODULO() defined in Divider_Public.h
+#define IS_SLEEP_HW_DIVIDER_INIT 0
+#endif
+
+// For 36 latter chips, slave DSP crash is moved to IO(0x7)
+#if IS_EDGE_SAIC_CHIP_MT6236_AND_LATTER_VERSION && !(IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280))
+#define IS_DSP2_CRASH_ON_IO7_CHIP 1
+#else
+#define IS_DSP2_CRASH_ON_IO7_CHIP 0
+#endif
+
+#if IS_DUAL_MAC_DSP_CHIP
+#define IS_DSP_CRASH_WORKAROUND 1
+#else
+#define IS_DSP_CRASH_WORKAROUND 0
+#endif
+
+#if (IS_CHIP_MT6295_AND_LATTER_VERSION && defined(__MTK_TARGET__))
+#define IS_GL1D_CAL_DATA_DOWNLOAD_CHECK_SUPPORT 1
+#else
+#define IS_GL1D_CAL_DATA_DOWNLOAD_CHECK_SUPPORT 0
+#endif
+#if IS_CHIP_MT6295_AND_LATTER_VERSION
+#define IS_GL1D_DSP_V2_FLOW_SINGLE_USER_SUPPORT 1
+#else
+#define IS_GL1D_DSP_V2_FLOW_SINGLE_USER_SUPPORT 0
+#endif
+// IRDMA power control
+#if IS_FD216_DSP_CHIP && (IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION || IS_CHIP_MT6225_AND_LATTER_VERSION)
+#define IS_IRDMA_POWER_CTRL_CHIP 1
+#else
+#define IS_IRDMA_POWER_CTRL_CHIP 0
+#endif
+
+/* The De-interleaving buffer was moved to external memory */
+/* So, IRDMA would be used when wake-up, and the IR memory size should be increased */
+#if IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_DEINTERLEAVING_BUFFER_MOVED_CHIP 1
+#else
+#define IS_DEINTERLEAVING_BUFFER_MOVED_CHIP 0
+#endif
+
+#if defined(__MTK_MODEM_REMOVED__)
+#define IS_MTK_MODEM_REMOVED 1
+#else
+#define IS_MTK_MODEM_REMOVED 0
+#endif
+
+#if defined(__2G_RF_CUSTOM_TOOL_SUPPORT__)
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT 0
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 1
+#elif IS_CHIP_MT6516
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT 1
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 0
+#else
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT 0
+#define IS_RF_TOOL_CUSTOMIZATION_SUPPORT_V2 0
+#endif
+
+#if IS_CHIP_MT6236
+#define IS_BT_CO_CLOCK_SW_SUPPORT 0
+#define IS_BT_CO_CLOCK_HW_SUPPORT 1
+#else
+#define IS_BT_CO_CLOCK_SW_SUPPORT 0
+#define IS_BT_CO_CLOCK_HW_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_SMP_ARCHITECTURE 1
+#else
+#define IS_SMP_ARCHITECTURE 0
+#endif
+
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6292) || defined(__UE_SIMULATOR__)
+#define IS_SIMULTANEOUS_L1CD_ENABLE 1
+#else
+#error "Remove dummy LISR is mandatory feature since LR12"
+#endif
+
+#if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MD2G_BUS_LOW_POWER_MODE 1
+#else
+#define IS_MD2G_BUS_LOW_POWER_MODE 0
+#endif
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_2G_L1D_ROBUST_MODEM_ENABLE 1
+#else
+#define IS_2G_L1D_ROBUST_MODEM_ENABLE 0
+#endif
+
+#if IS_CHIP_MT6293
+#define IS_2G_BANK_B_ENABLE 1
+#else
+#define IS_2G_BANK_B_ENABLE 0
+#endif
+
+#if (IS_CHIP_MT6761) && (defined __MTK_TARGET__)
+#define IS_L1D_DELSEL_MEMORY_DUMP_ENABLE 1
+#else
+#define IS_L1D_DELSEL_MEMORY_DUMP_ENABLE 0
+#endif
+//FDD Dual Mode Feature Option
+#if defined(__UMTS_FDD_MODE__)
+#define IS_FDD_DUAL_MODE_SUPPORT 1
+#else
+#define IS_FDD_DUAL_MODE_SUPPORT 0
+#endif
+
+//TDD Dual Mode Feature Option
+#if defined(__UMTS_TDD128_MODE__)
+#define IS_TDD_DUAL_MODE_SUPPORT 1
+#else
+#define IS_TDD_DUAL_MODE_SUPPORT 0 //To do TDD dual mode L1S and loopback test, this feature should be opened
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+
+ #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_FDD_DUAL_MODE_SUPPORT
+#undef IS_TDD_DUAL_MODE_SUPPORT
+#define IS_TDD_DUAL_MODE_SUPPORT 1
+ #endif
+ #if L1D_WT_COBIN_UT_BEBUG && !L1D_WT_COBIN_UT_W_ONLY_BUILD && !L1D_WT_CBBIN_UT_T_ONLY_BUILD && IS_TDD_DUAL_MODE_SUPPORT
+#undef IS_FDD_DUAL_MODE_SUPPORT
+#define IS_FDD_DUAL_MODE_SUPPORT 1
+ #endif
+
+ #if (IS_FDD_DUAL_MODE_SUPPORT && !IS_TDD_DUAL_MODE_SUPPORT) || (!IS_FDD_DUAL_MODE_SUPPORT && IS_TDD_DUAL_MODE_SUPPORT)
+ #if L1D_WT_COBIN_UT_W_ONLY_BUILD || L1D_WT_CBBIN_UT_T_ONLY_BUILD
+ #else
+#error "IS_FDD_DUAL_MODE_SUPPORT and IS_TDD_DUAL_MODE_SUPPORT should be aligned with WT Co-bin feature!"
+ #endif
+ #endif
+
+ #if (IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT) && !defined(__MULTI_RAT_AFC_TADC_SHARE_SUPPORT__)
+ #if L1D_WT_COBIN_UT_W_ONLY_BUILD || L1D_WT_CBBIN_UT_T_ONLY_BUILD
+ #else
+#error "WT Co-bin feature needs multi-mode AFC Temp ADC sharing feature when dual-mode or multi-mode!"
+ #endif
+ #endif
+
+#endif
+
+//Multi Mode Feature Option
+#if defined(__UMTS_RAT__) || defined(__LTE_RAT__)
+#define IS_GL1_MULTI_MODE_SUPPORT 1
+#else
+#define IS_GL1_MULTI_MODE_SUPPORT 0
+#endif
+
+#if ( IS_GL1_MULTI_MODE_SUPPORT && IS_TDD_DUAL_MODE_SUPPORT ) || IS_GEMINI_TGG_SUPPORT
+#define IS_TDD_5PM_NORMAL_CTIRQ2_SUPPORT 1
+#else
+#define IS_TDD_5PM_NORMAL_CTIRQ2_SUPPORT 0
+#endif
+#if defined(L1_SIM)//Here we are undefining the macro IS_MULTI_MODE_AFC_SUPPORT since while running on XL1sim
+#undef IS_MULTI_MODE_AFC_SUPPORT //we are facing the warning as macro is redefined since 3G is also using same macro definition
+#endif
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+ #if IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT
+#define IS_MULTI_MODE_AFC_SUPPORT 1
+ #else
+#define IS_MULTI_MODE_AFC_SUPPORT 0
+ #endif
+#else
+#define IS_MULTI_MODE_AFC_SUPPORT 0
+#endif
+
+#if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MULTI_MODE_AFC_WITH_SHM_SUPPORT 1
+#else
+#define IS_MULTI_MODE_AFC_WITH_SHM_SUPPORT 0
+#endif
+
+#if defined(__COTMS_TELEMATICS_SUPPORT__)
+#define IS_MULTI_MODE_AFC_IN_32BITS 1
+#else
+#define IS_MULTI_MODE_AFC_IN_32BITS 0
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+ #if (IS_FDD_DUAL_MODE_SUPPORT || IS_TDD_DUAL_MODE_SUPPORT) && !IS_MULTI_MODE_AFC_SUPPORT
+#error "WT Co-bin feature needs multi-mode AFC feature when dual-mode or multi-mode!"
+ #endif
+#endif
+
+#if IS_TDD_DUAL_MODE_SUPPORT && (IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297)
+#define IS_AST3002_SUPPORT 1
+#else
+#define IS_AST3002_SUPPORT 0
+#endif
+
+#if IS_TDD_DUAL_MODE_SUPPORT
+ #if ( IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #elif IS_CHIP_MT6575 && defined(__AST3001__)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 1 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 1 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 1 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 1 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 1 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #elif (IS_CHIP_MT6583_MD2 || IS_CHIP_MT6280) && defined(__AST3001__)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 1 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 1 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 1 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 1 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #elif IS_AST3002_SUPPORT && (IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 1 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #elif ( IS_CHIP_MT6255 || IS_CHIP_MT6256 ) && defined(__AST3001__)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #elif IS_GEMINI_TGG_SUPPORT && defined(__AST2001__)
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 1 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #else
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0
+ #endif
+#else
+ #if IS_CHIP_MT6583_MD2
+/* For MT6583_MD2 2G Only Project, VRF28 is trigger by SRCLKENA */
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0 /* Trigger off-chip BPI pins by sending BSI data */
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0 /* Trigger off-chip BSI switch before sending BSI data to RF */
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0 /* Trigger off-chip Vrf18 */
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 1 /* Trigger Vrf28 by SRCLKENA instead of SW config */
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0 /* Handle init flow of single RF controlled by separate TD/2G BB chips */
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0 /* Handle power-on/off sync of single RF controlled by separate TD/2G BB chips */
+ #else
+#define IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT 0
+#define IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT 0
+#define IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT 0
+#define IS_SRCLKENA_TRIG_VRF28_SUPPORT 0
+#define IS_TDD_DM_RF_INIT_HANDSHAKE_SUPPORT 0
+#define IS_TDD_DM_RF_POWER_CHECK_SUPPORT 0
+ #endif
+#endif
+
+//TDD Dual Mode Feature Option
+#if IS_TDD_DUAL_MODE_SUPPORT
+ #if IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250
+#define IS_AST_B2S_SUPPORT 1
+ #else
+#define IS_AST_B2S_SUPPORT 0
+ #endif
+#else
+#define IS_AST_B2S_SUPPORT 0
+#endif
+
+//TDD Dual Mode Feature Option
+#if IS_TDD_DUAL_MODE_SUPPORT
+ #if IS_CHIP_MT6256 || IS_CHIP_MT6255 || ((IS_CHIP_MT6575||IS_CHIP_MT6280||IS_CHIP_MT6583_MD2) && defined(__AST3001__))
+#define IS_CO_CRYSTAL_SUPPORT 1
+#define IS_CO_TEMPADC_SUPPORT 0
+ #elif IS_CHIP_MT6572
+#define IS_CO_CRYSTAL_SUPPORT 1
+#define IS_CO_TEMPADC_SUPPORT 1
+ #else
+#define IS_CO_CRYSTAL_SUPPORT 0
+#define IS_CO_TEMPADC_SUPPORT 0
+ #endif
+#else
+#define IS_CO_CRYSTAL_SUPPORT 0
+#define IS_CO_TEMPADC_SUPPORT 0
+#endif
+
+#if defined(__MULTI_RAT_AFC_TADC_SHARE_SUPPORT__)
+ #if IS_CHIP_MT6290_S00
+#define IS_MULTI_RAT_AFC_SHARE_SUPPORT 0
+#define IS_MULTI_RAT_TADC_SHARE_SUPPORT 0
+ #else
+#define IS_MULTI_RAT_AFC_SHARE_SUPPORT 1
+#define IS_MULTI_RAT_TADC_SHARE_SUPPORT 1
+ #endif
+#else
+#define IS_MULTI_RAT_AFC_SHARE_SUPPORT 0
+#define IS_MULTI_RAT_TADC_SHARE_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6752_MD2
+#define IS_2G_ONLY_MODEM_SUPPORT 1
+#else
+#define IS_2G_ONLY_MODEM_SUPPORT 0
+#endif
+
+//TDD Dual Mode Short FBSB Feature
+#if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
+#define IS_DSP_ENHANCE_SHORT_FBSB_PATCH 0
+#elif IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6268T) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6223) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6268) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6253) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6276)
+#define IS_DSP_ENHANCE_SHORT_FBSB_PATCH 0
+#else
+#define IS_DSP_ENHANCE_SHORT_FBSB_PATCH 1
+#endif
+
+#if IS_TDD_DUAL_MODE_SUPPORT && !IS_DSP_ENHANCE_SHORT_FBSB_PATCH
+#error "DSP enhanced short FB/SB patch is mandatory for TDD dual mode"
+#endif
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+#define IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT 1
+#else
+ #if IS_TDD_DUAL_MODE_SUPPORT
+#define IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT 1
+ #else
+#define IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT 0
+ #endif
+#endif
+
+#if IS_DSP_ENHANCE_SHORT_FBSB_SUPPORT
+ #if defined(L1_SIM)
+#define IS_DSP_SHORT_FBSB_V1 0
+#define IS_DSP_SHORT_FBSB_V2 1
+ #endif
+#define IS_DSP_SHORT_SB_ENABLED 1
+#endif
+
+#if IS_TDD_DUAL_MODE_SUPPORT
+ #ifdef L1_SIM
+#define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 0
+ #else
+ #if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 1
+ #else
+#define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 0
+ #endif
+ #endif
+#else
+#define IS_RRM_TD_GAP_SHORT_FB_WORKAROUND 0
+#endif
+//TDD Dual Mode AFC Control Rule
+#if IS_TDD_DUAL_MODE_SUPPORT
+ #if defined(__AST2001__)
+#define IS_TDDM_AFC_TRANSFORM_SUPPORT 1 /* TD AFC HW has different DAC/slope from 2G */
+ #else
+#define IS_TDDM_AFC_TRANSFORM_SUPPORT 0
+ #endif
+#else
+#define IS_TDDM_AFC_TRANSFORM_SUPPORT 0
+#endif
+
+// Define L1D full pm test mode setting
+/*
+#define __L1D_FULL_PM_TEST__
+#define __L1D_FULL_PM_TEST_DEFAULT_OFF__
+ */
+#if defined(__L1D_FULL_PM_TEST__)
+#define IS_L1D_FULL_PM_TEST_SUPPORT 1
+#else
+#define IS_L1D_FULL_PM_TEST_SUPPORT 0
+#endif
+
+#if IS_L1D_FULL_PM_TEST_SUPPORT
+ #if !defined(__L1D_FULL_PM_TEST_DEFAULT_OFF__)
+#define IS_L1D_FULL_PM_TEST_DEFAULT_ON 1
+ #else
+#define IS_L1D_FULL_PM_TEST_DEFAULT_ON 0
+ #endif
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_WB_AMR_SUPPORT 1
+#define IS_FB_SNIFFER_SUPPORT 1
+#else
+#define IS_WB_AMR_SUPPORT 0
+#define IS_FB_SNIFFER_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6583_MD2
+#define IS_DLIF_CHIP 0
+#define IS_DCR_IN_DLIF_CHIP 1 /* MT6583_MD2 is DCR but re-uses the DLIF architecture */
+#define IS_DYNAMIC_SETPOINT_SUPPORT 0
+#define IS_HEADROOM_DETECTION_SUPPORT 0
+#define IS_SET_TX_BSI_CW_NEEDED 0
+#elif IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+#define IS_DLIF_CHIP 1
+#define IS_DCR_IN_DLIF_CHIP 0
+#define IS_DYNAMIC_SETPOINT_SUPPORT 1
+#define IS_HEADROOM_DETECTION_SUPPORT 1
+ #if IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_SET_TX_BSI_CW_NEEDED 0
+ #else
+#define IS_SET_TX_BSI_CW_NEEDED 1
+ #endif
+#else
+#define IS_DLIF_CHIP 0
+#define IS_DCR_IN_DLIF_CHIP 0
+#define IS_DYNAMIC_SETPOINT_SUPPORT 0
+#define IS_HEADROOM_DETECTION_SUPPORT 0
+#define IS_SET_TX_BSI_CW_NEEDED 0
+#endif
+
+#if IS_HEADROOM_DETECTION_SUPPORT
+ #if IS_CHIP_MT6256 || IS_CHIP_MT6251 || IS_CHIP_MT6255 || IS_CHIP_MT6250
+#define IS_IM_HEADROOM_DETECTION_SUPPORT 1
+ #else
+#define IS_IM_HEADROOM_DETECTION_SUPPORT 0
+ #endif
+#else
+#define IS_IM_HEADROOM_DETECTION_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_INBAND_BLOCKER_DETECTION_SUPPORT 1
+#else
+#define IS_INBAND_BLOCKER_DETECTION_SUPPORT 0
+#endif
+
+#if defined(L1_SIM)
+#define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 0
+#elif IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 1
+#else
+#define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 0
+#endif
+
+#if IS_OUTBAND_BLOCKER_DETECTION_SUPPORT
+#define IS_DSP_RX_DCOC_SUPPORT 1
+#else
+#define IS_DSP_RX_DCOC_SUPPORT 0
+#endif
+
+#if IS_RF_MT6179
+#define IS_DUAL_RF_SIP_CHIP_SUPPORT 1
+#else
+#define IS_DUAL_RF_SIP_CHIP_SUPPORT 0
+#endif
+
+#if IS_INBAND_BLOCKER_DETECTION_SUPPORT
+ #if IS_CHIP_MT6250
+#define IS_IM_INBAND_BLOCKER_DETECTION_SUPPORT 1
+ #else
+#define IS_IM_INBAND_BLOCKER_DETECTION_SUPPORT 0
+ #endif
+#else
+#define IS_IM_INBAND_BLOCKER_DETECTION_SUPPORT 0
+#endif
+
+#if IS_RF_MT6256RF || IS_RF_MT6251RF || IS_RF_MT6252RF || IS_RF_MT6255RF || IS_RF_MT6162 || IS_RF_MT6163 || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_DYNAMIC_MACRO_SUPPORT 1
+#else
+#define IS_DYNAMIC_MACRO_SUPPORT 0
+#endif
+
+#if IS_RF_MT6256RF
+#define IS_DYNAMIC_TC_GAIN_SUPPORT 1
+#define IS_TEMP_COMP_TC_GAIN_SUPPORT 1
+#elif IS_RF_MT6255RF
+#define IS_DYNAMIC_TC_GAIN_SUPPORT 0
+#define IS_TEMP_COMP_TC_GAIN_SUPPORT 0
+#else
+#define IS_DYNAMIC_TC_GAIN_SUPPORT 0
+#define IS_TEMP_COMP_TC_GAIN_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6583_MD2
+#define IS_GCMACHINE_SUPPORT 1
+#elif IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_CHIP_MT6252
+#define IS_GCMACHINE_SUPPORT 0
+#else
+#define IS_GCMACHINE_SUPPORT 1
+#endif
+
+#if IS_CHIP_MT6256
+#define IS_MT6251_DCR_MODE 0
+#define IS_MT6256_DCR_MODE 0
+#define IS_MT6251_E1_FT 0
+ #if IS_MT6256_DCR_MODE
+#define IS_W_CANCELLATION_SUPPORT 0
+ #else
+#define IS_W_CANCELLATION_SUPPORT 1
+ #endif
+#elif IS_CHIP_MT6251
+#define IS_MT6251_DCR_MODE 0
+#define IS_MT6256_DCR_MODE 0
+#define IS_MT6251_E1_FT 0
+ #if IS_MT6251_DCR_MODE
+#define IS_W_CANCELLATION_SUPPORT 0
+ #else
+#define IS_W_CANCELLATION_SUPPORT 1
+ #endif
+#elif IS_CHIP_MT6255 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MT6251_DCR_MODE 0
+#define IS_MT6256_DCR_MODE 0
+#define IS_W_CANCELLATION_SUPPORT 1
+#define IS_MT6251_E1_FT 0
+#else
+#define IS_MT6251_DCR_MODE 0
+#define IS_MT6256_DCR_MODE 0
+#define IS_W_CANCELLATION_SUPPORT 0
+#define IS_MT6251_E1_FT 0
+#endif
+
+#if IS_CHIP_MT6256
+ #if defined(__BT_SUPPORT__)
+#define IS_BT_R_CAL_SUPPORT 1
+ #else
+#define IS_BT_R_CAL_SUPPORT 0
+ #endif
+#else
+#define IS_BT_R_CAL_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256_S00
+#define IS_SWITD_SUPPORT 0
+#elif IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_SWITD_SUPPORT 1
+#else
+#define IS_SWITD_SUPPORT 0
+#endif
+
+#if IS_SWITD_SUPPORT
+ #if IS_CHIP_MT6256 || IS_CHIP_MT6255 || IS_CHIP_MT6250
+#define IS_IM_SWITD_SUPPORT 1
+ #else
+#define IS_IM_SWITD_SUPPORT 0
+ #endif
+#else
+#define IS_IM_SWITD_SUPPORT 0
+#endif
+
+#if IS_DSP_INIT_FLOW_V2_SUPPORT
+#define IS_POLLING_SHERIF_AFTER_DSP_RESET_NEEDED 1
+#else
+#define IS_POLLING_SHERIF_AFTER_DSP_RESET_NEEDED 0
+#endif
+
+/* IS_SPEECH_RESYNC_SUPPORT :L1D inform Audio to trigger VBI-Reset(DSP-Speech reset) */
+/* IS_SPEECH_RESYNC_SUPPORT_V2:L1D provide API to Audio, Audio query these API to trigger speech resync */
+/* MT6582 or latter version use IS_SPEECH_RESYNC_SUPPORT_V2*/
+#if IS_DSP_ARCHITECTURE_V1_SUPPORT || IS_DSP_ARCHITECTURE_V2_SUPPORT || IS_DSP_ARCHITECTURE_V3_SUPPORT
+#define IS_SPEECH_RESYNC_SUPPORT 0
+#define IS_SPEECH_RESYNC_SUPPORT_V2 0
+#elif IS_CHIP_MT6582 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_SPEECH_RESYNC_SUPPORT 0
+#define IS_SPEECH_RESYNC_SUPPORT_V2 1
+#elif IS_LOCK_AFCDAC_AT_STARTUP_SUPPORT
+#define IS_SPEECH_RESYNC_SUPPORT 0
+#define IS_SPEECH_RESYNC_SUPPORT_V2 1
+#else
+#define IS_SPEECH_RESYNC_SUPPORT 1
+#define IS_SPEECH_RESYNC_SUPPORT_V2 0
+#endif
+
+#if defined(L1D_TEST)
+#undef IS_HEADROOM_DETECTION_SUPPORT
+#undef IS_INBAND_BLOCKER_DETECTION_SUPPORT
+#undef IS_OUTBAND_BLOCKER_DETECTION_SUPPORT
+#undef IS_DYNAMIC_SETPOINT_SUPPORT
+#undef IS_W_CANCELLATION_SUPPORT
+#undef IS_SWITD_SUPPORT
+#define IS_HEADROOM_DETECTION_SUPPORT 0
+#define IS_INBAND_BLOCKER_DETECTION_SUPPORT 0
+#define IS_OUTBAND_BLOCKER_DETECTION_SUPPORT 0
+#define IS_DYNAMIC_SETPOINT_SUPPORT 0
+#define IS_W_CANCELLATION_SUPPORT 0
+#define IS_SWITD_SUPPORT 0
+#endif
+
+#if defined(L1_SIM)
+#undef IS_W_CANCELLATION_SUPPORT
+#undef IS_SPEECH_RESYNC_SUPPORT
+#define IS_W_CANCELLATION_SUPPORT 0
+#define IS_SPEECH_RESYNC_SUPPORT 0
+#endif
+
+#if IS_W_CANCELLATION_SUPPORT
+#define IS_WC_SLOW_TRACKING_SUPPORT 1
+ #if IS_WC_SLOW_TRACKING_SUPPORT
+#define IS_WC_SUB_KEEP_GAIN_DIM 0
+ #else
+#define IS_WC_SUB_KEEP_GAIN_DIM 1
+ #endif
+ #if IS_CHIP_MT6251_S00 || IS_CHIP_MT6256_S00
+#define IS_WC_IMM_MODE_ENABLE 0
+ #else
+#define IS_WC_IMM_MODE_ENABLE 1
+ #endif
+#else
+#define IS_WC_SLOW_TRACKING_SUPPORT 0
+#define IS_WC_SUB_KEEP_GAIN_DIM 0
+#define IS_WC_IMM_MODE_ENABLE 0
+#endif
+
+#if IS_EPSK_TX_SUPPORT
+ #if IS_RF_MT6256RF || IS_RF_MT6162 || IS_RF_MT6163 || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_EPSK_TX_GAIN_CONTROL_SUPPORT 1
+ #else
+#define IS_EPSK_TX_GAIN_CONTROL_SUPPORT 0
+ #endif
+#else
+#define IS_EPSK_TX_GAIN_CONTROL_SUPPORT 0
+#endif
+
+#if IS_RF_MT6252RF
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 1
+#elif IS_RF_MT6162
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 1
+#elif IS_RF_MT6251RF
+ #if IS_MT6251_E1_FT
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 0
+ #else
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 1
+ #endif
+#elif IS_RF_MT6255RF
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 1
+#else
+#define IS_RF_VCO_DOO_OFF 0
+#define IS_RF_VCO_PARTIAL_DOO_ON 0
+#endif
+
+#if IS_CHIP_MT6252_S00
+#define IS_RF_TX_SLEEP_MODE_SUPPORT 0
+#elif IS_CHIP_MT6252
+#define IS_RF_TX_SLEEP_MODE_SUPPORT 1
+#elif IS_CHIP_MT6251_S00
+#define IS_RF_TX_SLEEP_MODE_SUPPORT 0
+#elif IS_CHIP_MT6251
+#define IS_RF_TX_SLEEP_MODE_SUPPORT 1
+#else
+#define IS_RF_TX_SLEEP_MODE_SUPPORT 0
+#endif
+
+#if IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_OBB_DETECTION_SUPPORT 1
+#else
+#define IS_OBB_DETECTION_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6251_S00 || IS_CHIP_MT6252_S00
+#define IS_DSP_PIO_GLITCH_FIXED_NEEDED 0
+#elif IS_CHIP_MT6251 || IS_CHIP_MT6252
+#define IS_DSP_PIO_GLITCH_FIXED_NEEDED 1
+#else
+#define IS_DSP_PIO_GLITCH_FIXED_NEEDED 0
+#endif
+
+#if IS_CHIP_MT6251_S00 || IS_CHIP_MT6256_S00
+#define IS_FB_LONG_WINDOW_RXWIN_MULTIPLY_SUPPORT 1
+#else
+#define IS_FB_LONG_WINDOW_RXWIN_MULTIPLY_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256_S00
+#define IS_RTX_BUFFER_POWER_CTRL_SUPPORT 0
+#define IS_IDMA_SHORT_PORT_MODE_V2_SUPPORT 0
+#define IS_ACCESS_SHERIF_BY_IDMA_SUPPORT 0
+#elif IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_RTX_BUFFER_POWER_CTRL_SUPPORT 1
+#define IS_IDMA_SHORT_PORT_MODE_V2_SUPPORT 1
+#define IS_ACCESS_SHERIF_BY_IDMA_SUPPORT 1
+#else
+#define IS_RTX_BUFFER_POWER_CTRL_SUPPORT 0
+#define IS_IDMA_SHORT_PORT_MODE_V2_SUPPORT 0
+#define IS_ACCESS_SHERIF_BY_IDMA_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256_S00
+#define IS_DYNAMIC_SWITCH_DDS_SUPPORT 0
+#elif IS_CHIP_MT6256
+#define IS_DYNAMIC_SWITCH_DDS_SUPPORT 1
+#else
+#define IS_DYNAMIC_SWITCH_DDS_SUPPORT 0
+#endif
+
+#if defined(__F32_XOSC_REMOVAL_SUPPORT__)
+#define IS_32K_CRYSTAL_REMOVAL_SUPPORT 1
+#else
+#define IS_32K_CRYSTAL_REMOVAL_SUPPORT 0
+#endif
+
+/* IS_CLOAD_CAL_BBLPM_V1_SUPPORT: use BBLPM in FHC and SW LPM in traditional cal */
+#if IS_32K_CRYSTAL_REMOVAL_SUPPORT
+ #if IS_CHIP_MT6755 || IS_CHIP_MT6292
+#define IS_CLOAD_CAL_BBLPM_V1_SUPPORT 1
+ #elif IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 //&& IS_MML1_PMIC_MT6356
+#define IS_CLOAD_CAL_BBLPM_V1_SUPPORT 0
+ #else
+ #error "Please check CHIP and PMIC version"
+ #endif
+#endif
+
+#if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6577 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2
+#define IS_ABB_HW_CALIBRATION_SUPPORT 1
+#else
+#define IS_ABB_HW_CALIBRATION_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_BSI_SX0_SUPPORT 1
+#else
+#define IS_BSI_SX0_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256 || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_BPI_V2_SUPPORT 1
+#else
+#define IS_BPI_V2_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252
+#define IS_BSI_V2_SUPPORT 1
+#else
+#define IS_BSI_V2_SUPPORT 0
+#endif
+
+#define IS_BPI_V1_SUPPORT (!IS_BPI_V2_SUPPORT)
+#define IS_BSI_V1_SUPPORT (!IS_BSI_V2_SUPPORT)
+
+#if IS_BSI_V2_SUPPORT
+ #if IS_CHIP_MT6256 || IS_CHIP_MT6252 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_BSI_V2_ST2_SUPPORT 0
+ #elif IS_CHIP_MT6251 || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6583_MD2
+#define IS_BSI_V2_ST2_SUPPORT 1
+ #elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+#define IS_BSI_V2_ST2_SUPPORT 1
+ #else
+#define IS_BSI_V2_ST2_SUPPORT 0
+ #endif
+#else
+#define IS_BSI_V2_ST2_SUPPORT 0
+#endif
+
+#if IS_BPI_V2_SUPPORT
+ #if defined(__2G_BPI_PT3A_SUPPORT__)
+#define IS_BPI_V2_PT3A_SUPPORT 1
+ #elif defined(L1_SIM)
+#define IS_BPI_V2_PT3A_SUPPORT 1
+ #elif IS_CHIP_MT6582
+#define IS_BPI_V2_PT3A_SUPPORT 1
+ #else
+#define IS_BPI_V2_PT3A_SUPPORT 0
+ #endif
+#else
+#define IS_BPI_V2_PT3A_SUPPORT 0
+#endif
+
+#if defined(L1_SIM) && defined(MT6162_DUAL_RF)
+/* Note: for the combination of MT6280+MT6162_DUAL_RF, we should define IS_BSI_V2_ST2_SUPPORT */
+#undef IS_BSI_V2_ST2_SUPPORT
+#define IS_BSI_V2_ST2_SUPPORT 1
+#endif
+
+#if IS_BSI_V1_SUPPORT || IS_BSI_V2_ST2_SUPPORT
+#define IS_BSI_ST2_SUPPORT 1
+#else
+#define IS_BSI_ST2_SUPPORT 0
+#endif
+
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+#define IS_BSI_ST2B_SUPPORT 1
+#else
+#define IS_BSI_ST2B_SUPPORT 0
+#endif
+
+#if IS_BSI_V1_SUPPORT && IS_EPSK_TX_SUPPORT
+#define IS_BSI_ST2M_SUPPORT 1
+#elif IS_BSI_V2_SUPPORT
+#define IS_BSI_ST2M_SUPPORT 1
+#else
+#define IS_BSI_ST2M_SUPPORT 0
+#endif
+
+#if IS_GPRS || IS_MULTISLOT_TX_SUPPORT
+#define IS_CALCULATE_PM_TABLE_SUPPORT 1
+#else
+#define IS_CALCULATE_PM_TABLE_SUPPORT 0
+#endif
+
+#if IS_RF_MT6162 || IS_RF_MT6163
+#define IS_RF_RX_DCOC_SUPPORT 1
+ #if IS_CHIP_MT6577 || IS_CHIP_MT6583_MD2
+#define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 1
+ #else
+#define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 0
+ #endif
+ #if IS_EPSK_TX_SUPPORT
+#define IS_RF_TX_CALIBRATION_SUPPORT 1
+ #else
+#define IS_RF_TX_CALIBRATION_SUPPORT 0
+ #endif
+#else
+#define IS_RF_RX_DCOC_SUPPORT 0
+#define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 0
+#define IS_RF_TX_CALIBRATION_SUPPORT 0
+#endif
+
+#if defined(L1_SIM) || IS_CHIP_TK6280 /* TK6280 FPGA not support the following feature */
+#undef IS_RF_RX_DCOC_SUPPORT
+#undef IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT
+#undef IS_RF_TX_CALIBRATION_SUPPORT
+#define IS_RF_RX_DCOC_SUPPORT 0
+#define IS_RF_RX_DCOC_WITH_PRECISION_IMPROVEMENT 0
+#define IS_RF_TX_CALIBRATION_SUPPORT 0
+#endif
+
+#if IS_CACHE_DSP_SUPPORT || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_SIX_IRDMA_MPU_SETTING_CHIP 0
+#elif IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6268A) || IS_CHIP_SER(CHIP_ID_MT6256)
+#define IS_SIX_IRDMA_MPU_SETTING_CHIP 1
+#else
+#define IS_SIX_IRDMA_MPU_SETTING_CHIP 0
+#endif
+
+#if IS_CHIP_MT6251
+#define IS_SINGLE_DSP_TRX_REGION_SUPPORT 1
+#else
+#define IS_SINGLE_DSP_TRX_REGION_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6252
+#define IS_RTX_DATA_MOVED_BY_IRDMA_SUPPORT 0
+#elif IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+#define IS_RTX_DATA_MOVED_BY_IRDMA_SUPPORT 1
+#else
+#define IS_RTX_DATA_MOVED_BY_IRDMA_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6252 || IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+#define IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT 1
+#else
+#define IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251_S00
+#undef IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT
+#define IS_DSP_FCCH_LENGTH_DYNAMIC_SET_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION
+#define IS_DUAL_MAC_DSP_NEW_EQ_CHECK_SUPPORT 1
+#else
+#define IS_DUAL_MAC_DSP_NEW_EQ_CHECK_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_6R6T_HW_SUPPORT_CHIP 1
+#else
+#define IS_6R6T_HW_SUPPORT_CHIP 0
+#endif
+
+#if IS_CHIP_MT6256_S00 || IS_CHIP_MT6251
+#define IS_DSP_COSTDOWN_FB_CHIP 0
+#elif IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6268T) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6223) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6236) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6252H) || IS_CHIP_SER_AND_BEFORE(CHIP_ID_MT6276)
+#define IS_DSP_COSTDOWN_FB_CHIP 0
+#else
+#define IS_DSP_COSTDOWN_FB_CHIP 1
+#endif
+
+#if defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__) || defined(__L1_GPS_REF_TIME_SUPPORT__)
+#define L1D_AGPS_TIMING_SYNC_SUPPORT 1
+#else
+#define L1D_AGPS_TIMING_SYNC_SUPPORT 0
+#endif
+
+#if IS_CENTRALIZED_SMM_CHIP
+ #if IS_CHIP_MT6276_S00 || IS_CHIP_MT6573
+#define L1D_AGPS_OLD_REGISTER 1
+ #else
+#define L1D_AGPS_OLD_REGISTER 0
+ #endif
+#endif
+
+// HW clock gating
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6297)
+#define IS_HWCG_SUPPORT 0
+#elif IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_HWCG_SUPPORT 1
+#else
+#define IS_HWCG_SUPPORT 0
+#endif
+
+// Modem hard real time recovery enhancement
+#ifdef __MD_HRT_RECOVERY__
+#define IS_MD_HRT_RECOVERY_SUPPORT 1
+#else
+#define IS_MD_HRT_RECOVERY_SUPPORT 0
+#endif
+
+// APC Ramping Profiles support
+#define APC_PROFILE_NUM 7
+
+#if IS_CHIP_MT6208
+#undef APC_PROFILE_NUM
+#define APC_PROFILE_NUM 6
+#endif
+
+#if IS_NEW_L1D_ARCH_SUPPORT
+#undef APC_PROFILE_NUM
+#define APC_PROFILE_NUM 5
+#endif
+
+#define IS_5_BANK_RAMP_PROFILES_SUPPORT (APC_PROFILE_NUM==5)
+#define IS_6_BANK_RAMP_PROFILES_SUPPORT (APC_PROFILE_NUM==6)
+#define IS_7_BANK_RAMP_PROFILES_SUPPORT (APC_PROFILE_NUM==7)
+
+#if defined (__2G_TX_POWER_CONTROL_SUPPORT__)
+#define IS_TX_POWER_CONTROL_SUPPORT 1
+ #if IS_CHIP_MT6256
+#define IS_TXPC_CL_AUXADC_SUPPORT 1 /* Closed-loop. Vdet from AUXADC */
+#define IS_TXPC_CL_BSI_SUPPORT 0 /* Closed-loop. Pdet from BSI HW readback */
+#define IS_TXPC_OL_AUXADC_SUPPORT 0 /* Open-loop. Ext. temperature from AUXADC */
+#define IS_TXPC_OL_BSI_SUPPORT 1 /* Open-loop. RF temperature from BSI HW readback */
+ #elif IS_CHIP_MT6575 || IS_CHIP_MT6583_MD2
+#define IS_TXPC_CL_AUXADC_SUPPORT 0
+#define IS_TXPC_CL_BSI_SUPPORT 1
+#define IS_TXPC_OL_AUXADC_SUPPORT 1
+#define IS_TXPC_OL_BSI_SUPPORT 0
+ #elif IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_TXPC_CL_AUXADC_SUPPORT 0
+#define IS_TXPC_CL_BSI_SUPPORT 1
+#define IS_TXPC_OL_AUXADC_SUPPORT 0
+#define IS_TXPC_OL_BSI_SUPPORT 1
+ #elif IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION
+#define IS_TXPC_CL_AUXADC_SUPPORT 1
+#define IS_TXPC_CL_BSI_SUPPORT 1
+#define IS_TXPC_OL_AUXADC_SUPPORT 1
+#define IS_TXPC_OL_BSI_SUPPORT 0
+ #endif
+#else
+#define IS_TX_POWER_CONTROL_SUPPORT 0
+#define IS_TXPC_CL_AUXADC_SUPPORT 0
+#define IS_TXPC_CL_BSI_SUPPORT 0
+#define IS_TXPC_OL_AUXADC_SUPPORT 0
+#define IS_TXPC_OL_BSI_SUPPORT 0
+#endif
+
+#if IS_TX_POWER_CONTROL_SUPPORT && ( IS_RF_MT6177L || IS_RF_MT6177M || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T)
+#define IS_RSSI_TC_SUPPORT 1 /* RSSI Temperature Compensation will reuse TXPC's temperature info */
+#else
+#define IS_RSSI_TC_SUPPORT 0
+#endif
+
+#if IS_RF_MT6162 || IS_RF_MT6256RF || IS_RF_MT6163 || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_RF_TX_POWER_CONTROL_SUPPORT 1
+#else
+#define IS_RF_TX_POWER_CONTROL_SUPPORT 0
+#endif
+
+#if IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_ORION_RF_SERIES 1
+#else
+#define IS_ORION_RF_SERIES 0
+#endif
+
+#if (IS_RF_MT6177L && defined(__IS_2G_DYNAMIC_GAINTABLE_SWITCH_SUPPORT__))
+#define IS_2G_DYNAMIC_GAINTABLE_SWITCH_SUPPORT 1 //Boost LPF2 Gain for Pin=-96~-102dBm
+#else
+#define IS_2G_DYNAMIC_GAINTABLE_SWITCH_SUPPORT 0
+#endif
+
+#if IS_GPRS
+#define IS_DECREASE_RF_TX_MAX_POWER_SUPPORT 1
+#else
+#define IS_DECREASE_RF_TX_MAX_POWER_SUPPORT 0
+#endif
+
+#if defined(__TAS_SUPPORT__)
+#define IS_TAS_MAX_TXPWR_REDUCTION_SUPPORT 1
+#else
+#define IS_TAS_MAX_TXPWR_REDUCTION_SUPPORT 0
+#endif
+
+#if defined (__MULTI_LNA_MODE_CALIBRATION_SUPPORT__)
+ #if IS_CHIP_MT6582
+#define IS_MULTI_LNA_MODE_CALIBRATION_SUPPORT 1
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT 1 /* pathloss cal with one LNA or multi-lna mode are adjustable by tool config */
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT_V2 0 /* pathloss cal with one LNA or multi-lna mode are adjustable by tool config, and LNA Mode can be choose by L1 */
+ #else
+#define IS_MULTI_LNA_MODE_CALIBRATION_SUPPORT 1
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT 0
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT_V2 0
+ #endif
+#else
+#define IS_MULTI_LNA_MODE_CALIBRATION_SUPPORT 0
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT 0
+#define IS_ADJUSTABLE_LNA_MODE_CALIBRATION_SUPPORT_V2 0
+#endif
+
+#if defined (__2G_TX_GAIN_RF_CALIBRATION__)
+#define IS_TX_GAIN_RF_CALIBRATION_SUPPORT 1
+#else
+#define IS_TX_GAIN_RF_CALIBRATION_SUPPORT 0
+#endif
+
+/* for dual talk project, RX LNA > LNA2 which is co-band with 3G need to change to another gain table */
+#define IS_DUAL_TALK_RX_GAIN_TABLE_CO_BAND_SUPPORT 0
+
+#if IS_EPSK_TX_SUPPORT
+ #if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6583_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 1 /* Change the GMSK and EPSK TX window positions dynamically by slots. */
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 0 /* Change the GMSK and EPSK TX window positions dynamically by frames */
+ /* according to the modulation type of the whole TX slot in each frame. */
+ #else
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 0
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 1
+ #endif
+#else
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 0
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 0
+#endif
+
+#if defined(L1D_TEST)
+#undef IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT
+#undef IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT 0
+#define IS_DYNAMIC_G_E_TXWIN_POSITION_SUPPORT_V2 0
+#endif
+
+//#if IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_MT6177M || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T
+#define IS_RF_DUAL_LOOP_AFC_CONTROL_SUPPORT 1
+//#else
+//#define IS_RF_DUAL_LOOP_AFC_CONTROL_SUPPORT 0
+//#endif
+
+#if defined(L1D_TEST)
+#define IS_DUAL_LOOP_AFC_CONTROL_SUPPORT 0
+#else
+ #if IS_VCXO_LC_SUPPORT
+#error "Please implement Dual Loop AFC Control for VCXO"
+ #elif IS_RF_DUAL_LOOP_AFC_CONTROL_SUPPORT
+#define IS_DUAL_LOOP_AFC_CONTROL_SUPPORT 1
+ #else
+#error "This RF Chip is not support Fix AFC and GPS Co-Clock"
+ #endif
+#endif
+
+#if IS_DUAL_LOOP_AFC_CONTROL_SUPPORT
+ #if IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T
+#define IS_FIX_AFC_OFFSET_CW_COMPENSATE_SUPPORT 1
+ #else
+#define IS_FIX_AFC_OFFSET_CW_COMPENSATE_SUPPORT 0
+ #endif
+#endif
+
+#if IS_DUAL_LOOP_AFC_CONTROL_SUPPORT
+ #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DSP_RX_NBIC_SUPPORT 1
+ #else
+#define IS_DSP_RX_NBIC_SUPPORT 0
+ #endif
+ #if defined(L1D_TEST)
+#define IS_DSP_RX_NBIC_SUPPORT 0
+ #endif
+#else
+#define IS_DSP_RX_NBIC_SUPPORT 0
+#endif
+
+#if IS_DUAL_LOOP_AFC_CONTROL_SUPPORT
+#define IS_LOCK_AFCDAC_AT_STARTUP_SUPPORT 1
+#else
+#define IS_LOCK_AFCDAC_AT_STARTUP_SUPPORT 0
+#endif
+
+#if defined(__AUDIO_DSP_LOWPOWER_V2__)
+#define IS_AUDIO_DSP_LOWPOWER_SUPPORT 1
+#else
+#define IS_AUDIO_DSP_LOWPOWER_SUPPORT 0
+#endif
+
+/* IS_AFC_EVENT_SUPPORT_CHIP: decide if the chip supports the AFC event register */
+#if IS_AST_B2S_SUPPORT || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2
+#define IS_AFC_EVENT_SUPPORT_CHIP 1
+#elif IS_SOC_CHIP || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_AFC_EVENT_SUPPORT_CHIP 0
+#else
+#define IS_AFC_EVENT_SUPPORT_CHIP 1
+#endif
+
+/* IS_DCXO_SUPPORT_CHIP: decide if the chip supports the way of sending AFCDAC values by BSI */
+#if IS_SOC_CHIP || IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DCXO_SUPPORT_CHIP 1
+#else
+#define IS_DCXO_SUPPORT_CHIP 0
+#endif
+
+/* IS_DFM_RF_TIMING_CHECK_SUPPORT: add RF-BFE timing constraints at RX/TX on/off in l1d_data.c */
+#if IS_RF_MT6252RF || IS_RF_MT6251RF || IS_RF_MT6256RF || IS_RF_MT6255RF || IS_RF_MT6162 || IS_RF_MT6163 || IS_RF_MT6250RF || IS_RF_MT6280RF || IS_RF_MT6169 || IS_RF_MT6166 || IS_RF_MT6165 || IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_DFM_RF_TIMING_CHECK_SUPPORT 1
+#else
+#define IS_DFM_RF_TIMING_CHECK_SUPPORT 0
+#endif
+
+/*IS_CONTINUOUS_TDMA_EVENT_TIMING_CHECK_SUPPORT: the timing difference of two succeed TDMA events should be larger than 1QB */
+#if IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION && (!IS_CHIP_MT6256) && (!IS_CHIP_MT6251) && (!IS_CHIP_MT6255)
+#define IS_CONTINUOUS_TDMA_EVENT_TIMING_CHECK_SUPPORT 1
+#else
+#define IS_CONTINUOUS_TDMA_EVENT_TIMING_CHECK_SUPPORT 0
+#endif
+
+#if IS_EDGE_SAIC_CHIP_MT6270A_AND_LATTER_VERSION || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_IMM_BSI_SEND_DUMMY_READ_ON 1
+#else
+#define IS_IMM_BSI_SEND_DUMMY_READ_ON 0
+#endif
+
+#if IS_RF_AD6548 || IS_RF_MT6139E || IS_RF_MTKSOC1 || IS_RF_MT6252RF || IS_RF_MT6251RF || IS_RF_MT6255RF
+#define IS_EPSK_TX_NOT_SUPPORT_RF 1
+#else
+#define IS_EPSK_TX_NOT_SUPPORT_RF 0
+#endif
+
+#if defined(L1_SIM)
+#define IS_TDMA_BSI_READBACK_SUPPORT 0
+#elif IS_EDGE_SAIC_CHIP_MT6256_AND_LATTER_VERSION
+#define IS_TDMA_BSI_READBACK_SUPPORT 1
+#else
+#define IS_TDMA_BSI_READBACK_SUPPORT 0
+#endif
+
+#if defined(__CLASS_33_34__)
+#define IS_MULTISLOT_CLASS_33_34_SUPPORT 1
+#else
+#define IS_MULTISLOT_CLASS_33_34_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6250 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_VAMOS_CAPABILITY 1
+
+#define IS_VAMOS_SUPPORT 1
+
+#define IS_SHIFTSACCH_SUPPORT 1
+
+#else
+#define IS_VAMOS_CAPABILITY 0
+#define IS_VAMOS_SUPPORT 0
+#define IS_SHIFTSACCH_SUPPORT 0
+#endif
+
+#if defined(L1D_TEST) && (IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 )
+#define IS_COSIM_IRDMA_MPU_FULL_TEST_SUPPORT 1
+#else
+#define IS_COSIM_IRDMA_MPU_FULL_TEST_SUPPORT 0
+#endif
+
+#if defined(__UDVT__) && (IS_CHIP_MT6250 || IS_CHIP_MT6280)
+/* move the UDVT FH codes from the meut folder to l1 */
+#define IS_UDVT_FH_SUPPORT 1
+#else
+#define IS_UDVT_FH_SUPPORT 0
+#endif
+
+// Enable TXDFE A-Die Dump
+#define IS_L1D_TXDFE_A_DIE_DUMP_ENABLE 0
+
+// Enable RXDFE dump API
+#define IS_L1D_RXDFE_DUMP_ENABLE 0
+// Debug use; for setup of parameters to L1 through catcher
+#define IS_L1D_INJECT_STRING_DEBUG_ON 1
+
+#if IS_2G_L1D_ROBUST_MODEM_ENABLE
+#define IS_2G_L1D_ROBUST_MODEM_TRACE_ENABLE 1
+#else
+#define IS_2G_L1D_ROBUST_MODEM_TRACE_ENABLE 0
+#endif /* IS_2G_L1D_ROBUST_MODEM_ENABLE */
+/* Enable the patch to compensate DAC when 2g is in stand by , gets
+ * dac from active rat but difference is more than thershold
+ */
+// TDMA debug info
+#define IS_2G_TDMA_DEBUG_INFO_ENABLE 1
+
+#define IS_2G_STANDBY_OWN_DAC_SUPPORT 1
+
+/*Compensate timing erro based on SIM*/
+#define IS_2G_TIMING_CORRECT_SIM_BASE 1
+/*
+ * To handle the false alarm for the patch compensating afc dac in standby mode
+ */
+#if IS_2G_STANDBY_OWN_DAC_SUPPORT
+#define IS_2G_STANDBY_DAC_ENHANCEMENT_ENABLE 1
+#else
+#define IS_2G_STANDBY_DAC_ENHANCEMENT_ENABLE 0
+#endif
+
+
+#if IS_CHIP_MT6280
+ #if IS_CHIP_MT6280_S00
+#define IS_DCM_ISSUE_WORKAROUND_ON 1
+ #else
+#define IS_DCM_ISSUE_WORKAROUND_ON 1
+ #endif
+#define IS_USE_INTERNAL_TEMP_SENSOR 1
+#define IS_LOW_POWER_HQA_PDN_SUPPORT 1
+#elif IS_CHIP_MT6583_MD1
+#define IS_DCM_ISSUE_WORKAROUND_ON 0
+#define IS_USE_INTERNAL_TEMP_SENSOR 1 /* MT6583_MD1 is matched with MT6167 */
+#define IS_LOW_POWER_HQA_PDN_SUPPORT 1
+#elif IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DCM_ISSUE_WORKAROUND_ON 0
+#define IS_USE_INTERNAL_TEMP_SENSOR 1 /* MT6572 is matched with MT6166 */
+#define IS_LOW_POWER_HQA_PDN_SUPPORT 1
+#else
+#define IS_DCM_ISSUE_WORKAROUND_ON 0
+#define IS_USE_INTERNAL_TEMP_SENSOR 0
+#define IS_LOW_POWER_HQA_PDN_SUPPORT 0
+#endif
+
+// There are two methods to solve TC21.1
+// 1. Advance the BFE RX DCOC timing (SW solution)
+// => IS_RX_DCOC_ADVANCED_SUPPORT
+// => This feathure was disable since the side effect of failing FTA in-band block TC.
+// 2. HW adds the NB_ENx field to the RX_TYPE_CONx register (HW solution)
+// to distinguish between NB & SB/FB for RX_TYPEx = 0
+// => IS_BFE_RX_TYPE_NB_EN_SUPPORT (MT6572 BFE HW adds this new function)
+#if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_RX_DCOC_ADVANCED_SUPPORT 0
+#define IS_BFE_RX_TYPE_NB_EN_SUPPORT 1
+#elif IS_CHIP_MT6256_S00 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_RX_DCOC_ADVANCED_SUPPORT 0
+#define IS_BFE_RX_TYPE_NB_EN_SUPPORT 0
+#elif IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255)
+#define IS_RX_DCOC_ADVANCED_SUPPORT 1
+#define IS_BFE_RX_TYPE_NB_EN_SUPPORT 0
+#else
+#define IS_RX_DCOC_ADVANCED_SUPPORT 0
+#define IS_BFE_RX_TYPE_NB_EN_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6280
+#define IS_ANALOG_RXIQ_DEBUG_MODE_ON 0
+#define IS_INJECT_SIGNAL2ADC_DEBUG_MODE_ON 0
+#endif
+
+#ifdef __UE_SIMULATOR__
+#define IS_UESIM_DM_RF_INIT_SUPPORT 1
+#else
+#define IS_UESIM_DM_RF_INIT_SUPPORT 0
+#endif
+
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1)
+/* the ADC/DAC control are moved from RF to BB */
+#define IS_TDMA_AD_DA_WINDOW_SUPPORT 1
+#else
+#define IS_TDMA_AD_DA_WINDOW_SUPPORT 0
+#endif
+
+#if IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1)
+/* the TDMA will do the clipping when tq_count+tq_bias is larger than 16383 */
+#define IS_TDMA_CLIPPING_SUPPORT 1
+#else
+#define IS_TDMA_CLIPPING_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_APC_HALF_QB_RESOLUTION_SUPPORT 0
+#elif IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6583_MD1)
+/* the APC supports 1/2 QB resolution */
+#define IS_APC_HALF_QB_RESOLUTION_SUPPORT 1
+#else
+#define IS_APC_HALF_QB_RESOLUTION_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6256 || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6255) || IS_CHIP_SER_AND_LATTER(CHIP_ID_MT6280)
+#define IS_DSP_P2X_SUPPORT 1
+#else
+#define IS_DSP_P2X_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_WRITE_DSP_PATCH_BY_L1 1
+#else
+#define IS_WRITE_DSP_PATCH_BY_L1 0
+#endif
+
+#if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572
+ #if defined(__MODEM_CCCI_EXIST__)
+#define IS_REPORT_RF_TEMPERATURE_SUPPORT 1
+ #else
+#define IS_REPORT_RF_TEMPERATURE_SUPPORT 0
+ #endif
+#else
+#define IS_REPORT_RF_TEMPERATURE_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6280
+#define IS_REPORT_RF_TEMPERATURE_BYATCMD_SUPPORT 1
+#else
+#define IS_REPORT_RF_TEMPERATURE_BYATCMD_SUPPORT 0
+#endif
+
+#if defined(__2G_TX_VOLTAGE_COMPENSATION_SUPPORT__)
+ #if defined(__MODEM_CCCI_EXIST__)
+#define IS_TX_VOLTAGE_COMPENSATION_SUPPORT 1
+ #else
+#define IS_TX_VOLTAGE_COMPENSATION_SUPPORT 0
+ #endif
+#else
+#define IS_TX_VOLTAGE_COMPENSATION_SUPPORT 0
+#endif
+
+#if defined(__RF_WIDE_TEMPERATURE_SUPPORT__)
+#define IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT 1
+#else
+#define IS_TELEMATICS_VOLT_TEMP_TX_COMPENSATION_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6583_MD2
+#define IS_SW_SECOND_VERSION_NEEDED 1
+#else
+#define IS_SW_SECOND_VERSION_NEEDED 0
+#endif
+
+#if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_TDMA_TDD_TIMER_SYNC_SUPPORT 1
+#else
+#define IS_TDMA_TDD_TIMER_SYNC_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2
+#define IS_GSM_BPI_MASK_NEEDED 1
+#else
+#define IS_GSM_BPI_MASK_NEEDED 0
+#endif
+
+#if IS_COSIM_ON_L1SIM_SUPPORT
+ #if IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 ||IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#undef IS_TDMA_BSI_READBACK_SUPPORT
+#define IS_TDMA_BSI_READBACK_SUPPORT 1
+ #endif
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_BSISPI_SEPARATE_SUPPORT 1
+#else
+#define IS_BSISPI_SEPARATE_SUPPORT 0
+#endif
+
+/* If IS_MMRF_CONTROL_BSI_TOP_SUPPORT is supported, it means that BSISPI and BPI_TOP control are moved to MMRF driver. */
+#if IS_BSISPI_SEPARATE_SUPPORT
+ #if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MMRF_CONTROL_BSI_TOP_SUPPORT 1
+ #else
+#define IS_MMRF_CONTROL_BSI_TOP_SUPPORT 0
+ #endif
+#else
+#define IS_MMRF_CONTROL_BSI_TOP_SUPPORT 0
+#endif
+
+#define IS_DUAL_TALK_SUPPORT 0
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_DMA_REMOVED 1
+#else
+#define IS_DMA_REMOVED 0
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_RF_CENTRAL_CONTROL_SUPPORT 1
+#else
+#define IS_RF_CENTRAL_CONTROL_SUPPORT 0
+#endif
+
+#if IS_RF_CENTRAL_CONTROL_SUPPORT && IS_RF_MT6169
+#define IS_RF_CENTRAL_CONTROL_ENABLE 1
+#define IS_LTE_POWERON_CALIBRATION_ENABLE 1
+#elif IS_RF_CENTRAL_CONTROL_SUPPORT && ( IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M)
+#define IS_RF_CENTRAL_CONTROL_ENABLE 1
+#define IS_LTE_POWERON_CALIBRATION_ENABLE 0
+#else
+#define IS_RF_CENTRAL_CONTROL_ENABLE 0
+#define IS_LTE_POWERON_CALIBRATION_ENABLE 0
+#endif
+
+#if IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_RF_RAMPPROFILE_ROLLBACK_SUPPORT 1 // adjust ramping profile based on TX power rollback
+#else
+#define IS_RF_RAMPPROFILE_ROLLBACK_SUPPORT 0
+#endif
+
+#if IS_RF_MT6176 || IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6177M
+/* This compile option will effect NVRAM/Cross-Core Custom Folder Setting, it's always enable for specific RF */
+#define IS_2G_MMPOC_SUPPORT 1
+#else
+#define IS_2G_MMPOC_SUPPORT 0 // Bypass 2G RFC data Init and copying and under this compile options for Gen97
+#endif
+
+#if defined(__2G_MIPI_SUPPORT__)
+/*Check __2G_MIPI_SUPPORT__ setting at option.mak , if platform has been added*/
+#define IS_MIPI_SUPPORT 1
+#else
+#define IS_MIPI_SUPPORT 0
+#endif
+
+#if IS_MIPI_SUPPORT && ( IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297_AND_LATTER_VERSION )
+#define IS_MIPI_CENTRAL_CONTROL_SUPPORT 1
+#define IS_MIPI_CENTRAL_CONTROL_ENABLE 1
+#else
+#define IS_MIPI_CENTRAL_CONTROL_SUPPORT 0
+#define IS_MIPI_CENTRAL_CONTROL_ENABLE 0
+#endif
+
+#if IS_MIPI_SUPPORT && defined(__2G_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT__)
+/* Macro IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT has been removed from GL1 code after TK6291 */
+#define IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT 1
+#else
+#define IS_MIPI_INTERSLOT_RAMPING_OPTIMIZE_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+/* the frequency hopping is controled by system service */
+#define IS_FH_CONTROL_BY_SS 1
+#else
+#define IS_FH_CONTROL_BY_SS 0
+#endif
+
+#if IS_FH_CONTROL_BY_SS
+#undef IS_MPLL_FH_SUPPORT
+#undef IS_MPLLFH_FREE_RUN_SUPPORT_CHIP
+#undef IS_MPLLFH_FREE_RUN_ON
+#define IS_MPLL_FH_SUPPORT 0
+#define IS_MPLLFH_FREE_RUN_SUPPORT_CHIP 0
+#define IS_MPLLFH_FREE_RUN_ON 0
+#endif
+
+#if IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+/* to support the DCS-TD co-existence feature */
+#define IS_DCS_NB_WB_SWITCH_SUPPORT 1
+#else
+#define IS_DCS_NB_WB_SWITCH_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6752_MD2
+#define IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT 1
+#else
+#define IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6752_MD2
+#define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_SUPPORT 1
+#else
+#define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_SUPPORT 0
+#endif
+
+#if IS_DSDA_DCS_TX_NOTCH_SWITCH_SUPPORT
+#define IS_DSDA_DCS_TX_NOTCH_SWITCH_ENABLE 0
+#else
+#define IS_DSDA_DCS_TX_NOTCH_SWITCH_ENABLE 0
+#endif
+
+#if IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_SUPPORT
+ #if defined(__LTE_TX_PATH_SWITCH_SUPPORT__)
+#define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_ENABLE 1
+ #else
+#define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_ENABLE 0
+ #endif
+#else
+#define IS_DSDA_PROVIDE_RX_STATUS_TO_LTE_ENABLE 0
+#endif
+
+#if defined(__PS_L1_DC_ARCH__)
+/* to support dual-core modem architecture */
+#define IS_DUAL_CORE_MODEM_SUPPORT 1
+#define IS_CTIRQ3_SUPPORT 0
+#else
+#define IS_DUAL_CORE_MODEM_SUPPORT 0
+#define IS_CTIRQ3_SUPPORT 0
+#endif /* defined(__PS_L1_DC_ARCH__) */
+
+#if IS_DUAL_CORE_MODEM_SUPPORT
+#define IS_DUAL_CORE_MODEM_L1D_UT_DEBUG 0
+ #if IS_CTIRQ3_SUPPORT
+#define IS_TRIGER_U1_AT_CT3 0
+ #else
+#define IS_TRIGER_U1_AT_CT3 0
+ #endif /* IS_CTIRQ3_SUPPORT */
+#define IS_SET_SBUF_AS_GLOBAL_VAR_SUPPORT 1
+#else
+#define IS_DUAL_CORE_MODEM_L1D_UT_DEBUG 0
+#define IS_TRIGER_U1_AT_CT3 0
+#define IS_SET_SBUF_AS_GLOBAL_VAR_SUPPORT 0
+#endif /* IS_DUAL_CORE_MODEM_SUPPORT */
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_OUTPUT_RF_VERSION_SUPPORT 1
+#else
+#define IS_OUTPUT_RF_VERSION_SUPPORT 0
+#endif
+
+#if defined (__ACC_NC_AFC_DB_UPDATE_SUPPORT__)
+#define IS_ACC_NC_AFC_DB_UPDATE_SUPPORT 1 /* Enable Accelerating NC AFC DB updating */
+#else
+#define IS_ACC_NC_AFC_DB_UPDATE_SUPPORT 0
+#endif
+
+
+#define IS_CSFB_WITH_SGLTE_HW_ENABLE 0
+
+#if IS_CSFB_WITH_SGLTE_HW_ENABLE
+ #if IS_RF_MT6165 || IS_RF_MT6166
+// CSFB_WITH_SGLTE_HW can only enable on MT6165/MT6166
+ #else
+#error "This RF Chip is not support CSFB with SGLTE HW."
+ #endif
+#endif
+
+#if IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297 /* Chipset support MML1 and DRDI */
+#define IS_L1_RF_DRDI_CUSTOM_SETTING_FROM_MML1 1
+#else
+#define IS_L1_RF_DRDI_CUSTOM_SETTING_FROM_MML1 0
+#endif
+
+#if defined (__TX_POWER_OFFSET_SUPPORT__)
+#define IS_TX_POWER_OFFSET_SUPPORT 1 /* Enable Tx power offset */
+#else
+#define IS_TX_POWER_OFFSET_SUPPORT 0 /* Disable Tx power offset */
+#endif /*__TX_POWER_OFFSET_SUPPORT__*/
+
+#if defined (__SAR_TX_POWER_BACKOFF_SUPPORT__)
+#define IS_SAR_TX_POWER_BACKOFF_SUPPORT 1 /* Enable Tx power offset for SAR test*/
+#define IS_2G_DYNAMIC_SAR_TABLE_SUPPORT 1
+#else
+#define IS_SAR_TX_POWER_BACKOFF_SUPPORT 0 /* Disable Tx power offset for SAR test*/
+#define IS_2G_DYNAMIC_SAR_TABLE_SUPPORT 0
+#endif /*__SAR_TX_POWER_BACKOFF_SUPPORT__*/
+#if defined(__RX_POWER_OFFSET_SUPPORT__)
+#define IS_RX_POWER_OFFSET_SUPPORT 1
+#else
+#define IS_RX_POWER_OFFSET_SUPPORT 0
+#endif/*__RX_POWER_OFFSET_SUPPORT__*/
+
+#if defined (__GSM_EM_TX_POWER_CONTROL_SUPPORT__)
+#define IS_GSM_EM_TX_POWER_CONTROL_SUPPORT 1 /* Enable EM Tx power control */
+#else
+#define IS_GSM_EM_TX_POWER_CONTROL_SUPPORT 0 /* Disable EM Tx power control */
+#endif
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_GSM_TX_DETECTOR_SUPPORT 1
+#else
+#define IS_GSM_TX_DETECTOR_SUPPORT 0
+#endif /* defined(__GSM_TX_DETECTOR_SUPPORT__) */
+
+#if defined (__NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__)
+
+ #if defined (__EPSK_ADJUST_TPO_SUPPORT__)
+#define IS_EPSK_ADJUST_TPO_SUPPORT 1 /*Enable Adjust TPO feature support on EPSK*/
+ #else
+#define IS_EPSK_ADJUST_TPO_SUPPORT 0 /*Disable Adjust TPO feature support on EPSK*/
+ #endif//__EPSK_ADJUST_TPO_SUPPORT__
+
+#define IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT 1 /* Enable NSFT Adjust Tx Power Offset */
+#else
+#define IS_NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT 0 /* Disable NSFT Adjust Tx Power Offset */
+#endif /*__NSFT_ADJUST_TX_POWER_OFFSET_SUPPORT__*/
+
+#if defined (__EM_MAX_TX_POWER_SUPPORT__)
+#define IS_MAX_TX_POWER_CONTROL_SUPPORT 1 /* Enable MAX Tx power control */
+#else
+#define IS_MAX_TX_POWER_CONTROL_SUPPORT 0 /* Disable MAX Tx power control */
+#endif
+
+#if defined (__GSM_INCREASE_RACH_TX_POWER_SUPPORT__)
+#define IS_GSM_INCREASE_RACH_TX_POWER_SUPPORT 1 /* Enable RACH Tx power control */
+#else
+#define IS_GSM_INCREASE_RACH_TX_POWER_SUPPORT 0 /* Disable RACH Tx power control */
+#endif
+
+#if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_CC_NVRAM_CUSTOM_DATA_SUPPORT 1
+#else
+#define IS_CC_NVRAM_CUSTOM_DATA_SUPPORT 0
+#endif
+
+#if IS_CHIP_TK6291
+#define IS_TK6291_HW_BUG_SW_WORKAROUND_SUPPORT 1
+#else
+#define IS_TK6291_HW_BUG_SW_WORKAROUND_SUPPORT 0
+#endif
+
+#if IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_MD2G_MEM_CONFIG_SUPPORT_CHIP 1
+#else
+#define IS_MD2G_MEM_CONFIG_SUPPORT_CHIP 0
+#endif
+
+#if (IS_MD2G_MEM_CONFIG_SUPPORT_CHIP)
+ #if IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_CENTRALIZED_SW_TYPE_SETTING_SUPPORT 1
+ #else
+#define IS_CENTRALIZED_SW_TYPE_SETTING_SUPPORT 0
+ #endif /* IS_CHIP_MT6295 */
+#else
+#define IS_CENTRALIZED_SW_TYPE_SETTING_SUPPORT 0
+#endif /* IS_MD2G_MEM_CONFIG_SUPPORT_CHIP */
+
+#if defined(__TAS_SUPPORT__)
+ #if defined(__MD93__)
+ #define IS_2G_TAS_SUPPORT 1
+ #define IS_2G_Gen95_UTAS_SUPPORT 0
+ #define IS_2G_Gen97_UTAS_SUPPORT 0
+ #define IS_2G_TAS_INHERIT_4G_ANT 1
+ #elif defined(__MD95__) /*GL1D is not involved from Gen95 onwards since GL1C is taking care of it*/
+ #define IS_2G_TAS_SUPPORT 0
+ #define IS_2G_Gen95_UTAS_SUPPORT 1
+ #define IS_2G_Gen97_UTAS_SUPPORT 0
+ #define IS_2G_TAS_INHERIT_4G_ANT 0
+ #elif (defined(__MD97__) || defined(__MD97P__))
+ #define IS_2G_TAS_SUPPORT 0
+ #define IS_2G_Gen95_UTAS_SUPPORT 0
+ #define IS_2G_Gen97_UTAS_SUPPORT 1
+ #define IS_2G_TAS_INHERIT_4G_ANT 0
+ #else
+ #error "[ERROR] Invalid MD generation"
+ #endif
+ #define IS_2G_TAS_ANT_IDX_FOR_PM_WINDOW_SUPPORT 1
+#else
+#define IS_2G_TAS_SUPPORT 0
+#define IS_2G_TAS_ANT_IDX_FOR_PM_WINDOW_SUPPORT 0
+#define IS_2G_TAS_INHERIT_4G_ANT 0
+#define IS_2G_Gen95_UTAS_SUPPORT 0
+#define IS_2G_Gen97_UTAS_SUPPORT 0
+#endif
+
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT 1 /*Gen97 DAT is default enable*/
+#else
+#define IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT defined (__DYNAMIC_ANTENNA_TUNING__)
+#endif
+/*Please review those code usign this feature option*/
+#define IS_L1D_USEC_TRACE_SUPPORT 1
+
+#define IS_2G_UTAS97_DETAIL_FE_TIMING_DEBUG_TRACE_SUPPORT 0 /* Used for UTAS 97 detailed FE timing information*/
+
+
+#if IS_2G_DYNAMIC_ANTENNA_TUNING_SUPPORT //defined(__DYNAMIC_ANTENNA_TUNING__)
+ #if defined(__MD93__)
+ #define IS_2G_DAT_SUPPORT 1
+ #define IS_2G_Gen95_UDAT_SUPPORT 0
+ #define IS_2G_Gen97_UDAT_SUPPORT 0
+ #elif defined(__MD95__)
+ #define IS_2G_DAT_SUPPORT 0
+ #define IS_2G_Gen95_UDAT_SUPPORT 1
+ #define IS_2G_Gen97_UDAT_SUPPORT 0
+ #elif (defined(__MD97__) || defined(__MD97P__))
+ #define IS_2G_DAT_SUPPORT 0
+ #define IS_2G_Gen95_UDAT_SUPPORT 0
+ #define IS_2G_Gen97_UDAT_SUPPORT 1
+ #else
+ #error "[ERROR] Invalid MD generation"
+ #endif
+#else
+#define IS_2G_DAT_SUPPORT 0
+#define IS_2G_Gen95_UDAT_SUPPORT 0
+#define IS_2G_Gen97_UDAT_SUPPORT 0
+#endif
+#if defined(__ANT_RXPWR_OFFSET_SUPPORT__)
+#define IS_ANT_RXPWR_OFFSET_SUPPORT 1
+#else
+#define IS_ANT_RXPWR_OFFSET_SUPPORT 0
+#endif
+
+/* Calculate TXRX active timing , default on for Andriod N feature */
+#define IS_TXRX_GET_INFO 1
+
+#define MD97_S2U_TIME 0
+#if IS_CHIP_MT6297_AND_LATTER_VERSION
+#define IS_MM_APC_NEW_RAMP_CONFIGURE 0
+#else
+#define IS_MM_APC_NEW_RAMP_CONFIGURE 1
+#endif
+
+/* DRDI support capability */
+#if defined(__RF_DRDI_CAPABILITY_SUPPORT__)
+#define IS_2G_DRDI_SUPPORT 1
+#else
+#define IS_2G_DRDI_SUPPORT 0
+#endif
+
+/* 2G support PRX1 or DRX1 */
+#if IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_2G_ALTERNATIVE_RX_PATH_SUPPORT 1
+#else
+#define IS_2G_ALTERNATIVE_RX_PATH_SUPPORT 0
+#endif
+
+/* 2G support PRX1 or DRX1 */
+#if defined(__2G_RX_DIVERSITY_PATH_SUPPORT__) && (IS_2GRXD_CHIP_MT6765_AND_LATTER_VERSION || IS_CHIP_MT6295) || IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT
+
+#define IS_2G_RXD_SUPPORT 1
+#define IS_2G_RXD_ENHANCEMENT_SUPPORT 1
+
+#define IS_GSM_RX_RXD_MODE_FIXED 0 //Force RXD mode before GL1C RAS involve
+
+#else
+
+#define IS_2G_RXD_SUPPORT 0
+#define IS_2G_RXD_ENHANCEMENT_SUPPORT 0
+
+#define IS_GSM_RX_RXD_MODE_FIXED 0
+#endif
+
+#if IS_2G_RXD_SUPPORT
+#define IS_2G_RAS_CROSS_MODE_SUPPORT 1
+#define IS_2G_RAS_DECISION_INCLUDE_DSP_POW_SUPPORT 1
+#if IS_CHIP_MT6853_AND_LATTER_VERSION // Gen97, C-value enable Mouton and latter
+#define IS_2G_C_VALUE_SUPPORT 1
+#endif
+#else
+#define IS_2G_RAS_CROSS_MODE_SUPPORT 0
+#define IS_2G_RAS_DECISION_INCLUDE_DSP_POW_SUPPORT 0
+#define IS_2G_C_VALUE_SUPPORT 0
+#endif
+
+#if defined(__2G_RXD_BLACKLIST_SUPPORT__)
+#define IS_2G_RXD_BLACKLIST_SUPPORT 1
+#else
+#define IS_2G_RXD_BLACKLIST_SUPPORT 0
+#endif
+
+/* For L1C Dummy LISR removal, added debug traces */
+#if (IS_CHIP_MT6292) && (defined __MTK_TARGET__)
+#define IS_2G_DUMMY_LISR_REMOVAL_DEBUG 1
+#else
+#define IS_2G_DUMMY_LISR_REMOVAL_DEBUG 0
+#endif
+
+#if defined(__GSM_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT__)
+#define IS_2G_DYNAMIC_HW_CLOCK_SUPPORT 1 //Adjust HW clock for specific ARFCNs
+#else
+#define IS_2G_DYNAMIC_HW_CLOCK_SUPPORT 0
+#endif
+
+/* Support using external LNA and adjust RX gain table in L1 code flow */
+#if IS_RF_MT6179 || IS_RF_MT6177L || IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M || IS_RF_MT6190T || IS_RF_MT6177M
+#define IS_2G_EXTERNAL_LNA_SUPPORT 1
+#else
+#define IS_2G_EXTERNAL_LNA_SUPPORT 0
+#endif
+
+#if IS_RF_MT6186M || IS_RF_MT6190T
+#define IS_2G_WITHOUT_MATCHING_NETWORK_SUPPORT 0
+#else
+#define IS_2G_WITHOUT_MATCHING_NETWORK_SUPPORT 0
+#endif
+
+/* Support using BYPASS and adjust RX gain table in L1 code flow */
+#if IS_2G_EXTERNAL_LNA_SUPPORT
+ #if IS_RF_MT6190T
+#define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0
+ #elif IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M
+#define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 1
+ #elif IS_RF_MT6177L || IS_RF_MT6177M
+#define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 1
+#define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0
+ #else
+#define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 0
+#define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 0
+#define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0
+ #endif
+#else
+#define IS_2G_EXTERNAL_LNA_BYPASS_SUPPORT 0
+#define IS_2G_EXTERNAL_LNA_HIGH_SENSITIVITY_SUPPORT 0
+#define IS_2G_EXTERNAL_LNA_BYPASS_WIDE_BAND_MATCHING_SUPPORT 0
+#endif
+
+#if IS_2G_EXTERNAL_LNA_SUPPORT
+#define IS_2G_EXTERNAL_LNA_FSI_SYNC_SUPPORT 1
+#else
+#define IS_2G_EXTERNAL_LNA_FSI_SYNC_SUPPORT 0
+#endif
+#if IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define IS_NEW_FD216_RESTART_FLOW_ENABLE 1
+#define IS_SPEECH_uSIP_SUPPORT 1
+#define IS_MD_TOPSM_API_USING 1
+#define IS_FIXED_DSPCLK 1
+#define IS_DSP_DM_4BYTE_ALIGN_CHIP 1
+#else
+#define IS_NEW_FD216_RESTART_FLOW_ENABLE 0
+#define IS_SPEECH_uSIP_SUPPORT 0
+#define IS_MD_TOPSM_API_USING 0
+#define IS_FIXED_DSPCLK 0
+#define IS_DSP_DM_4BYTE_ALIGN_CHIP 0
+#endif
+
+#if IS_CHIP_MT6295
+#define IS_DYNAMICAL_NOISE_FLOOR_AND_SATURATION_SUPPORT 1
+#else
+#define IS_DYNAMICAL_NOISE_FLOOR_AND_SATURATION_SUPPORT 0
+#endif
+
+#if defined(__A54_ALGORITHM_SUPPORT__)
+#define IS_A54_ALGORITHM_SUPPORT 1
+#else
+#define IS_A54_ALGORITHM_SUPPORT 0
+#endif
+
+#if defined(__MMRF_RF_HAL_SEQ_GEN_SUPPORT__)
+ #if IS_RF_TRINITYE1 || IS_RF_TRINITYL || IS_RF_MT6186 || IS_RF_MT6186M
+#define IS_HAL_SUPPORT 1
+ #else
+#define IS_HAL_SUPPORT 0
+ #endif
+#endif
+
+/*Some check condition for IS_2G_Gen95_UTAS_SUPPORT */
+//#if IS_2G_Gen95_UTAS_SUPPORT && XXXX
+//#error "IS_2G_Gen95_UTAS_SUPPORT not porting for XXXX yet!!!"
+//#endif
+
+#if defined(__MTK_TARGET__)
+ #if (IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT) && (!IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT)
+#error "(IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT) only porting for IS_L1D_MMRF_BSIBPIRS_DYNAMIC_ALLOCATION_SUPPORT !!!"
+ #endif
+
+ #if (IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT) && (!IS_2G_RXD_SUPPORT)
+#error "(IS_2G_Gen95_UTAS_SUPPORT || IS_2G_Gen97_UTAS_SUPPORT ) only porting for IS_2G_RXD_SUPPORT !!!"
+ #endif
+#endif
+
+#if IS_CHIP_MT6295
+#define IS_2G_TX_COARSE_DCOC_SUPPORT 1
+#else
+#define IS_2G_TX_COARSE_DCOC_SUPPORT 0
+#endif /* IS_CHIP_MT6295 */
+
+
+/*===================================================================*/
+/* BBTX/BBRX chip design version */
+/*===================================================================*/
+#define BBTXRX_VER_1 1
+#define BBTXRX_VER_2 2
+#define BBTXRX_VER_3 3
+
+#if IS_CHIP_MT6583_MD2
+#define BBTXRX_CHIP_DESIGN_VER BBTXRX_VER_3
+#elif IS_CHIP_MT6276 || IS_CHIP_MT6573 || IS_CHIP_MT6575
+#define BBTXRX_CHIP_DESIGN_VER BBTXRX_VER_2
+#else
+#define BBTXRX_CHIP_DESIGN_VER BBTXRX_VER_1
+#endif
+
+#define IS_BBTXRX_CHIP_DESIGN_VER_1 (BBTXRX_CHIP_DESIGN_VER == BBTXRX_VER_1)
+#define IS_BBTXRX_CHIP_DESIGN_VER_2 (BBTXRX_CHIP_DESIGN_VER == BBTXRX_VER_2)
+#define IS_BBTXRX_CHIP_DESIGN_VER_3 (BBTXRX_CHIP_DESIGN_VER == BBTXRX_VER_3)
+
+/*===================================================================*/
+/* CHIP ZIMAGE setting */
+/*===================================================================*/
+#if IS_CHIP_MT6252
+#define IS_PRIMARY_ROCODE 1
+#else
+#define IS_PRIMARY_ROCODE 0
+#endif
+
+/*===================================================================*/
+/* CHIP Partial Internal RAM settings */
+/*===================================================================*/
+#define INTERN_NULL 0
+#define INTERN_FULL 1
+#define INTERN_PARTIAL 2
+#define INTERN_PARTIAL_CRITICAL 3
+
+/*===================================================================*/
+/* WT co-bin feature compile option check */
+/*===================================================================*/
+
+#if L1D_WT_COBIN_ARCHITECTURE_SUPPORT
+ #if defined(__AST2001__) || defined(__AST3001__)
+#error "WT Co-bin feature does not support these phase out feature!"
+ #endif
+ #if IS_3GRF_DETECT
+#error "WT Co-bin feature does not support phase out feature: IS_3GRF_DETECT !"
+ #endif
+ #if IS_DEFAULT_TURNOFF_3GMTCMOS
+#error "WT Co-bin feature does not support phase out feature: IS_DEFAULT_TURNOFF_3GMTCMOS !"
+ #endif
+ #if IS_GCMACHINE_V3_UMTS_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_GCMACHINE_V3_UMTS_SUPPORT !"
+ #endif
+ #if IS_GCMACHINE_V4_HSPA_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_GCMACHINE_V4_HSPA_SUPPORT !"
+ #endif
+ #if IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_BSI_TRIG_OFFCHIP_BPI_SUPPORT !"
+ #endif
+ #if IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_BSI_TRIG_OFFCHIP_BSI_SWITCH_SUPPORT !"
+ #endif
+ #if IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_BSI_TRIG_OFFCHIP_VRF18_SUPPORT !"
+ #endif
+ #if IS_SRCLKENA_TRIG_VRF28_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_SRCLKENA_TRIG_VRF28_SUPPORT !"
+ #endif
+ #if IS_AST_B2S_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_AST_B2S_SUPPORT !"
+ #endif
+ #if IS_TDDM_AFC_TRANSFORM_SUPPORT
+#error "WT Co-bin feature does not support phase out feature: IS_TDDM_AFC_TRANSFORM_SUPPORT !"
+ #endif
+ #if IS_CSFB_WITH_SGLTE_HW_ENABLE
+#error "WT Co-bin feature does not support phase out feature: IS_CSFB_WITH_SGLTE_HW_ENABLE !"
+ #endif
+#endif
+/* ------------------------------------------------------------- */
+// Global compiler option for vs1 low power feature of MT6293
+/* ------------------------------------------------------------- */
+#if defined(__PMIC_VS1_LOW_POWER_CTRL_SUPPORT__ )
+ #define IS_2G_PMIC_VS1_LOW_POWER_CTRL_SUPPORT 1
+#else
+ #define IS_2G_PMIC_VS1_LOW_POWER_CTRL_SUPPORT 0
+#endif
+
+/* ------------------------------------------------------------- */
+// default value
+/* ------------------------------------------------------------- */
+#if IS_CHIP_MT6205 || IS_CHIP_MT6225 || IS_CHIP_MT6223 || IS_CHIP_MT6238_SER || IS_CHIP_MT6276 || IS_CHIP_MT6251 || IS_CHIP_MT6573 || IS_CHIP_MT6252 || IS_CHIP_MT6256 || IS_CHIP_MT6575 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define INTERNCODE_DEFAULT INTERN_NULL
+#else
+#define INTERNCODE_DEFAULT INTERN_FULL
+#endif
+/* ------------------------------------------------------------- */
+#if IS_CHIP_MT6205 || IS_CHIP_MT6225 || IS_CHIP_MT6223 || IS_CHIP_MT6238_SER || IS_CHIP_MT6276 || IS_CHIP_MT6253 || IS_CHIP_MT6251 || IS_CHIP_MT6573 || IS_CHIP_MT6256 || IS_CHIP_MT6575 || IS_CHIP_MT6255 || IS_CHIP_MT6250 || IS_CHIP_MT6280 || IS_CHIP_MT6583_MD1 || IS_CHIP_MT6583_MD2 || IS_CHIP_MT6572 || IS_CHIP_MT6290 || IS_CHIP_MT6595 || IS_CHIP_MT6752_MD1 || IS_CHIP_MT6752_MD2 || IS_CHIP_TK6291 || IS_CHIP_MT6755 || IS_CHIP_MT6292 || IS_CHIP_MT6293 || IS_CHIP_MT6295 || IS_CHIP_MT6297
+#define INTERNDATA_DEFAULT INTERN_NULL
+#else
+#define INTERNDATA_DEFAULT INTERN_FULL
+#endif
+/* ------------------------------------------------------------- */
+
+/* ------------------------------------------------------------- */
+#define INTERNCODE_M11303 INTERNCODE_DEFAULT
+#define INTERNCODE_M12100 INTERNCODE_DEFAULT
+#define INTERNCODE_M12110 INTERNCODE_DEFAULT
+#define INTERNCODE_M12120 INTERNCODE_DEFAULT
+#define INTERNCODE_M12160 INTERNCODE_DEFAULT
+#define INTERNCODE_M12168 INTERNCODE_DEFAULT
+#define INTERNCODE_M12170 INTERNCODE_DEFAULT
+#define INTERNCODE_M12180 INTERNCODE_DEFAULT
+/* ------------------------------------------------------------- */
+#define INTERNDATA_M11303 INTERNDATA_DEFAULT
+#define INTERNDATA_M12100 INTERNDATA_DEFAULT
+#define INTERNDATA_M12110 INTERNDATA_DEFAULT
+#define INTERNDATA_M12120 INTERNDATA_DEFAULT
+#define INTERNDATA_M12160 INTERNDATA_DEFAULT
+#define INTERNDATA_M12168 INTERNDATA_DEFAULT
+#define INTERNDATA_M12170 INTERNDATA_DEFAULT
+#define INTERNDATA_M12180 INTERNDATA_DEFAULT
+#define INTERNDATA_M12194 INTERNDATA_DEFAULT
+#define INTERNDATA_L1D_DATA INTERNDATA_DEFAULT
+#define INTERNDATA_L1D_INTERNAL_DATA INTERNDATA_DEFAULT
+/* ------------------------------------------------------------- */
+#if IS_EDGE_CHIP_MT6229_AND_LATTER_VERSION
+#define INTERNCODE_M12167 INTERNCODE_DEFAULT
+#define INTERNDATA_M12167 INTERNDATA_DEFAULT
+#else
+#define INTERNCODE_M12167 INTERN_NULL
+#define INTERNDATA_M12167 INTERN_NULL
+#endif
+/* ------------------------------------------------------------- */
+#if IS_CHIP_MT6253 || IS_CHIP_MT6236 /* MPLL FH support chips */
+#define INTERNCODE_M12171 INTERNCODE_DEFAULT
+#define INTERNDATA_M12171 INTERNDATA_DEFAULT
+#else
+#define INTERNCODE_M12171 INTERN_NULL
+#define INTERNDATA_M12171 INTERN_NULL
+#endif
+/* ------------------------------------------------------------- */
+
+#if IS_CHIP_MT6238_SER /* code: all off, data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M12100
+#undef INTERNCODE_M12110
+#undef INTERNCODE_M12120
+#undef INTERNCODE_M12160
+#undef INTERNCODE_M12170
+#define INTERNCODE_M12100 INTERN_FULL
+ #if IS_GEMINI_SUPPORT
+#define INTERNCODE_M12110 INTERN_PARTIAL
+#define INTERNCODE_M12120 INTERN_PARTIAL
+ #else
+#define INTERNCODE_M12110 INTERN_FULL
+#define INTERNCODE_M12120 INTERN_FULL
+ #endif
+#define INTERNCODE_M12160 INTERN_FULL
+#define INTERNCODE_M12170 INTERN_FULL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12100
+#undef INTERNDATA_M12110
+#undef INTERNDATA_M12120
+#undef INTERNDATA_M12160
+#undef INTERNDATA_M12170
+#undef INTERNDATA_L1D_DATA
+#undef INTERNDATA_L1D_INTERNAL_DATA
+#define INTERNDATA_M12100 INTERN_FULL
+#define INTERNDATA_M12110 INTERN_FULL
+#define INTERNDATA_M12120 INTERN_FULL
+#define INTERNDATA_M12160 INTERN_FULL
+#define INTERNDATA_M12170 INTERN_FULL
+#define INTERNDATA_L1D_DATA INTERN_FULL
+#define INTERNDATA_L1D_INTERNAL_DATA INTERN_FULL
+
+#elif IS_CHIP_MT6255 || IS_CHIP_MT6250
+
+#undef INTERNCODE_M11303
+#define INTERNCODE_M11303 INTERN_PARTIAL_CRITICAL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12100
+#undef INTERNDATA_M12168
+#undef INTERNDATA_M12170
+#define INTERNDATA_M12100 INTERN_FULL
+#define INTERNDATA_M12168 INTERN_FULL
+#define INTERNDATA_M12170 INTERN_FULL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6235_SER /* code: all on , data: all on */
+/* ------------------------------------------------------------- */
+ #if IS_GEMINI_SUPPORT
+#undef INTERNCODE_M12110
+#undef INTERNCODE_M12120
+#define INTERNCODE_M12110 INTERN_PARTIAL
+#define INTERNCODE_M12120 INTERN_PARTIAL
+ #endif
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6252 /* code: all off, data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M11303
+#undef INTERNCODE_M12110
+#undef INTERNCODE_M12120
+#undef INTERNCODE_M12168
+#undef INTERNCODE_M12180
+#define INTERNCODE_M11303 INTERN_PARTIAL_CRITICAL
+#define INTERNCODE_M12110 INTERN_PARTIAL_CRITICAL
+#define INTERNCODE_M12120 INTERN_PARTIAL_CRITICAL
+#define INTERNCODE_M12168 INTERN_PARTIAL_CRITICAL
+#define INTERNCODE_M12180 INTERN_PARTIAL_CRITICAL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6253 /* code: all on , data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M11303
+#undef INTERNCODE_M12110
+#undef INTERNCODE_M12120
+#undef INTERNCODE_M12160
+#undef INTERNCODE_M12167
+#undef INTERNCODE_M12168
+#define INTERNCODE_M11303 INTERN_PARTIAL
+#define INTERNCODE_M12110 INTERN_PARTIAL
+#define INTERNCODE_M12120 INTERN_PARTIAL
+#define INTERNCODE_M12160 INTERN_PARTIAL
+#define INTERNCODE_M12167 INTERN_NULL
+#define INTERNCODE_M12168 INTERN_NULL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12100
+#undef INTERNDATA_M12160
+#undef INTERNDATA_M12170
+#undef INTERNDATA_M12171
+#define INTERNDATA_M12100 INTERN_FULL
+#define INTERNDATA_M12160 INTERN_FULL
+#define INTERNDATA_M12170 INTERN_FULL
+#define INTERNDATA_M12171 INTERN_FULL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6223 /* code: all off, data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M11303
+#undef INTERNCODE_M12100
+#undef INTERNCODE_M12110
+#undef INTERNCODE_M12120
+#undef INTERNCODE_M12160
+#undef INTERNCODE_M12170
+#define INTERNCODE_M11303 INTERN_PARTIAL
+#define INTERNCODE_M12100 INTERN_FULL
+#define INTERNCODE_M12110 INTERN_PARTIAL
+#define INTERNCODE_M12120 INTERN_PARTIAL
+#define INTERNCODE_M12160 INTERN_PARTIAL
+#define INTERNCODE_M12170 INTERN_PARTIAL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6225 /* code: all off, data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M12160
+#undef INTERNCODE_M12170
+#define INTERNCODE_M12160 INTERN_FULL
+#define INTERNCODE_M12170 INTERN_FULL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12160
+#undef INTERNDATA_M12170
+#define INTERNDATA_M12160 INTERN_FULL
+#define INTERNDATA_M12170 INTERN_FULL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6218 || IS_CHIP_MT6219 || IS_CHIP_MT6227
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M12100
+#define INTERNCODE_M12100 INTERN_NULL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12100
+#define INTERNDATA_M12100 INTERN_NULL
+/* ------------------------------------------------------------- */
+#elif IS_CHIP_MT6205 /* code: all off, data: all off */
+/* ------------------------------------------------------------- */
+#undef INTERNCODE_M12160
+#undef INTERNCODE_M12170
+#define INTERNCODE_M12160 INTERN_FULL
+#define INTERNCODE_M12170 INTERN_FULL
+/* ------------------------------------------------------------- */
+#undef INTERNDATA_M12160
+#undef INTERNDATA_M12170
+#undef INTERNDATA_L1D_DATA
+#define INTERNDATA_M12160 INTERN_FULL
+#define INTERNDATA_M12170 INTERN_FULL
+#define INTERNDATA_L1D_DATA INTERN_FULL
+/* ------------------------------------------------------------- */
+#endif
+
+/*===============================================================================================*/
+#endif
+