[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/tl1/tl1_cc_public.h b/mcu/interface/l1/tl1/tl1_cc_public.h
new file mode 100644
index 0000000..467d76e
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1_cc_public.h
@@ -0,0 +1,122 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * tl1_cc_public.h
+ *
+ * Project:
+ * --------
+ * UMOLY_Software
+ *
+ * Description:
+ * ------------
+ * TL1 cross core interface declare
+ *****************************************************************************/
+#ifndef _TL1_CC_PUBLIC_H_
+#define _TL1_CC_PUBLIC_H_
+
+#include "kal_general_types.h"
+
+/*=======================================TL1 and DHL sharememory=================================*/
+//gTdSharedRegisterDumpInfo[0]: dump memory num; gTdSharedRegisterDumpInfo[1]: address, gTdSharedRegisterDumpInfo[2]: size;
+//gTdSharedRegisterDumpInfo[3]: address, gTdSharedRegisterDumpInfo[4]: size; ........
+//DECLARE_SHARED_ARRAY(kal_uint32, gTdSharedRegisterDumpInfo, 128)
+extern kal_uint32 gTdSharedRegisterDumpInfo[128];
+//ONLY L1CORE call this API for set MEM DUMP INFO
+#define TL1_SHARED_MEM_DUMP_INFO_TO_PCORE(dump_info_ptr, mem_num) do{\
+ volatile kal_uint32 *info_ptr; \
+ info_ptr = (volatile kal_uint32 *)SHARED_pARRAY(gTdSharedRegisterDumpInfo); \
+ *(volatile kal_uint32 *)info_ptr++ = mem_num; \
+ kal_mem_cpy((void *)info_ptr, (void *)dump_info_ptr, (sizeof(kal_uint32)*mem_num*2)); \
+ }while(0)
+//for DHL call TL1's API do memory dump in PCORE
+extern void GetTL1MemoryInfo(kal_uint32 **info, kal_uint16 *count, kal_uint8 *region_config);
+extern kal_uint32 GetTL1MemoryAccessType(kal_uint32 mem_addr);
+extern void tds_l1_slp_info(kal_uint64 *working_time, kal_uint32 *wakeup_cnt, kal_uint32 *sleep_cnt);
+
+#if 0 //MACRO API test pass, but no used because TL1 provide function API for DHL call
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*===============================================================================================*/
+
+
+/*======================================TDD efuse register for PCORE and L1CORE==================*/
+//efuse register is AP view, efuse_md1_3g_tdd_disable
+
+
+#define TDD_HW_EFUSE_REGISTER (0xA60F0350) //bit13 = 1, Disable 3G TDD(TDD_FEATURE_OFF). MD side efuse register
+#define TDD_FEATURE_OFF_BIT (13)
+
+/*======================================TL1 provide efuse API====================================*/
+#define TL1_READ_REG32(addr) (*(volatile kal_uint32 *)(addr))
+#define TL1_WRITE_REG32(addr, data) ((*(volatile kal_uint32 *)(addr)) = (kal_uint32)(data))
+/* if (TL1_IS_3G_TDD_EXIST() == KAL_TRUE), 3G TDD exist; if (TL1_IS_3G_TDD_EXIST() == KAL_FALSE), 3G TDD no exist; */
+#if defined(__UE_SIMULATOR__) || defined(__DISABLE_TL1__) //UESIM doesn't support 3G TDD, so return 3G TDD no exist
+#define TL1_IS_3G_TDD_EXIST() (KAL_FALSE)
+#else
+//#define TL1_IS_3G_TDD_EXIST() ((((TL1_READ_REG32(TDD_HW_EFUSE_REGISTER) >> TDD_FEATURE_OFF_BIT) & 0x1) == 1) ? (KAL_FALSE) : (KAL_TRUE)) //if 3G TDD Enabled, return KAL_TRUE; if 3G TDD Disabled, return KAL_FALSE;
+#define TL1_IS_3G_TDD_EXIST() (KAL_TRUE)
+#endif
+/*======================================TL1 provide efuse API====================================*/
+#endif //#ifndef _TL1_CC_PUBLIC_H_
\ No newline at end of file
diff --git a/mcu/interface/l1/tl1/tl1_cnst.h b/mcu/interface/l1/tl1/tl1_cnst.h
new file mode 100644
index 0000000..8f5e7ea
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1_cnst.h
@@ -0,0 +1,412 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2009
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/******************************************************************************
+ * Filename:
+ * --------------------------------------------------------
+ * tl1_cnst.h
+ *
+ * Project:
+ * --------------------------------------------------------
+ *
+ *
+ * Description:
+ * --------------------------------------------------------
+ *
+ *
+ * Author:
+ * --------------------------------------------------------
+ * -------
+ *
+ * --------------------------------------------------------
+ * $Log$
+ *
+ * 10 31 2018 xiaochi.zhang
+ * [MOLY00361478] [Gen97] Gemini Compile Option Clean Up
+ *
+ * .
+ *
+ * 05 23 2018 cruze.yu
+ * [MOLY00285698] [93/95 re-arch][TL1] tl1 option clean
+ *
+ * .
+ *
+ * 04 12 2017 weimin.zeng
+ * [MOLY00240270] [6293][Gemini][T+W] Phase 1: Common Interface Changes Check in
+ *
+ * , 3G TDD UMAC PCH buffer.
+ *
+ * 01 13 2017 weimin.zeng
+ * [MOLY00224780] [MT6293][UMOLYA][UMAC] memory shrink.
+ *
+ * .
+ *
+ * 04 29 2015 rong.yang
+ * [MOLY00109047] [UMOLY][new feature] Pich false alarm Optimization
+ * .
+ *
+ * 03 11 2015 marco.zhang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * __MAC_EHS_SUPPORT__ update to __TDD_MAC_EHS_SUPPORT__.
+ *
+ * 03 04 2015 chengwei.liu
+ * [MOLY00093594] [TK6291][3G TDD][FPGA DVT][MD8470][UPA.001.001]PING ²»Í¨
+ * .
+ *
+ * 12 29 2014 marco.zhang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * build error.
+ *
+ * 12 29 2014 marco.zhang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .
+ *
+ * 12 23 2014 marco.zhang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .
+ *
+ * 12 21 2014 marco.zhang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * prefix.
+ *
+ * 12 11 2014 rong.yang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .revise umac part about shared memory on tl1_ps_shared_mem.h/.c
+ *
+ * 12 10 2014 rong.yang
+ * [MOLY00087194] [3G UMAC] merge 6291 code from MOLY.U3G.90IT.DEV
+ * .
+ *
+ * 09 17 2013 shouzhu.zhang
+ * [MOLY00037556] remove compile option __ADD_MEAS_FREQ_NUM__
+ * <saved by Perforce>
+ *
+ * 04 01 2013 shouzhu.zhang
+ * [MOLY00013249] MM TL1 Code check in
+ * [TL1] Merge lastes WR8 + R9 + MM code to MOLY..
+ *
+ * 09 24 2012 xiaoyun.mao
+ * [MOLY00004069] [MOLY]TDD_R9_DEV Patch back to MOLY
+ * TDD_R9_DEV patch back to MOLY
+ *
+ * 09 19 2012 xiaoyun.mao
+ * [MOLY00002766]
+ * warning remove about CFN_IMMEIDATE: oxFFFF changed to -1
+ *
+ * 05 03 2012 wcpuser_integrator
+ * removed!
+ * .
+ *
+ * 03 02 2012 shuyang.yin
+ * removed!
+ * .
+ * (TL1 SAP)
+ *
+ * 02 24 2012 shuyang.yin
+ * removed!
+ * .
+ *
+ * 01 18 2011 xinqiu.wang
+ * removed!
+ * Add RHR feature to tl1 interface files.
+ *
+ * 12 01 2010 popcafa.shih
+ * removed!
+ * .
+ *
+ * 11 04 2010 xinqiu.wang
+ * removed!
+ * 1. Add ul_mac_event to cphy_dch_setup/modify/release_req
+ * 2. Add two ticks and structs for mac-tl1 interface.
+ * 3. Add two simulation structs according to MAC's requeset.
+ *
+ * 11 03 2010 xinqiu.wang
+ * removed!
+ * 1.SLCE-TL1 SAP Modify for R7
+ * 2. MAC-TL1 SAP Modify for UPA
+ *
+ * 08 24 2010 popcafa.shih
+ * removed!
+ * .
+ *
+ * 08 02 2010 qing.zhang
+ * removed!
+ * 1. Change the value of MAX_UL_TB from 16 to 32, change the value of MAX_DL_DATA from 953 to 1187, and change the value of MAX_UL_DATA from 829 to 1187 according to the requirement of UMAC.
+ *
+ * removed!
+ * removed!
+ * 1.Modify the description of MAX_HSDSCH_SIZE.
+ * 2.Modify BLER_INVALID to -64 according to the discussion result with SLCE.
+ *
+ * removed!
+ * removed!
+ * 1.Add max and min value of tm, off, rssi, rscp, iscp, sir, tx_power, tadv, doff, cpid, meas_id, bler.
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ * 1.Add HSUPA related cnst (MAX_EAGCH_NUM, MAX_EHICH_NUM, MAX_REF_BETA_NUM,MAX_EDCH_HARQ_PROC_PER_MODE )
+ *
+ * removed!
+ * removed!
+ * Add MAX_PREFERRED_PSC to solve tempory build error.
+ *
+ * removed!
+ * removed!
+ * 1.Add MAX_NUM_MEAS_CELL to solve tempory build error.
+ *
+ * removed!
+ * removed!
+ * 1.Delete pre-declare check of __UMTS_TDD128_MODE__
+ *
+ * removed!
+ * removed!
+ * Add check out history comments of last check in.
+ * 1.add check pre-declare of __UMTS_TDD128_MODE__
+ * 2.delete macro define of MAX_NUM_MEAS_CELL and MAX_PREFERRED_PSC
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ * Add TM_VALID and OFF_VALID in
+ *
+ * removed!
+ * removed!
+ * Rename __UMTS_TDD128_RAT__ to __UMTS_TDD128_MODE__
+ *
+ * removed!
+ * removed!
+ * correct the file name in the file header
+ *
+ * removed!
+ * removed!
+ * add log section for tl1interface header files
+ *
+ *******************************************************************************/
+
+#ifndef _TL1_CNST_H
+#define _TL1_CNST_H
+
+/*-------- BCH related constant ----------------------*/
+#define TDD_MAX_SIB_PATTERN (28) /* The maximum number of BCH SIB blocks */
+#define TDD_MAX_SIB_SEG_COUNT (16) /* The maximum number of segments in 1 BCH SIB */
+
+/*-------- TrCH related constant (For UL/DL 384Kbps capability) ----------------------*/
+#define TDD_MAX_TRCH_NUM (8) /* Maximum Simultaneous TrCHs of any kind (DL or UL).For 384kbps capability*/
+#define TDD_MAX_DL_TB (32) /* Maximum simultaneous DL TBs, For 384kbps capability.*/
+#define TDD_MAX_DL_TFC (128) /* Maximum number of TFCs per DL CCTrCH, For 384kbps capability */
+#define TDD_MAX_DL_TFs (64) /* Maximum numbre of TFs per DL CCTrCH,For 384kbps capability */
+#define TDD_MAXTF (32) /* Maximum number of TF per UL or DL TrCH TFS */
+#define TDD_MAXFACHPCH (8) /* Maximum number of FACHs and PCHs mapped onto one S-CCPCHs */
+#define TDD_MAX_UL_TFC (64) /* Maximum number of TFCs per UL CCTrCH,For 384kbps capability*/
+#define TDD_MAX_UL_TB (32) /* Maximum simultaneous DUL TBs */
+#define TDD_MAX_UL_TFs (32) /* Maximum numbre of TFs per UL CCTrCH, For 384kbps capability. */
+#define TDD_MAX_UL_TRCH (8) /* Maximum number of UL TrCH,UE declared capability. */
+#define TDD_MAX_DL_TRCH (8) /* Maximum number of DL TrCH,UE declared capability.*/
+
+/*(336/8)*24+(144+4)/8+80*2 = 1187*/
+#define TDD_MAX_DL_DATA (1187) /* Maximum DL transport block array size. */
+#define TDD_MAX_UL_DATA (1187) /* Maximum UL transport block array size. */
+
+
+
+/*-------- FS/Measurement related constant ----------------------*/
+#ifdef __GEMINI__
+#define TDD_MAX_FREQ_RANGE (36)
+#else
+#define TDD_MAX_FREQ_RANGE (8) /* Max size of frequency ranges for frequency scan. */
+#endif
+#define TDD_MAX_FREQ_LIST (33) /* Max size of stored frequency list for frequency scan */
+#define TDD_MAX_PREFERRED_CELL (96) /* Max number of preferred cells on 1 frequency for frequency scan */
+#define TDD_MAX_PREFERRED_PSC (96) /* Max number of preferred cells on 1 frequency for frequency scan */
+#define TDD_MAX_NUM_REPORT_CELL (32) /* Max number of reported cells in the CPHY_MEASUREMENT_CELL_IND */
+#define TDD_MAX_NUM_MEASURED_CELL (64) /* Max number of monitored cells in the CPHY_MEASUREMENT_CONFIG_CELL_REQ*/
+#define TDD_MAX_NUM_MEAS_CELL (64) /* Max number of monitored cells in the measurement cell request primitive */
+#define TDD_MAX_MEAS_EVENT (8) /* Maximum number of measurement events */
+#define TDD_MAX_UMTS_FREQ (13) /* Maximum number of DPCH radio links in TDD128 */
+#define TDD_MAX_NUM_MEAS_ID (16) /* Maximum number of "Measurement Identity" */
+#define TDD_REPORT_INFINITY (0xFF) /* Tx_power measurement report number infinity*/
+
+#define TDD_MAX_RSSI_SNIFFER_SCAN_LIST (36) /*Maximum number of RSSI SNIFFER UARFCN (Add by Janet) */
+
+/*-------- Magic value related constant ----------------------*/
+#define TDD_TM_INVALID (-1) /* Default value representing Tm unknown. */
+#define TDD_TM_VALID (6400*8) /* Default value representing Tm known. */
+#define TDD_MAX_TM (6400*8-1) /* Maximum effective value of tm.*/
+#define TDD_MIN_TM (0) /* Minimum effective value of tm.*/
+#define TDD_OFF_INVALID (-1) /* Default value representing OFF unknown. */
+#define TDD_OFF_VALID (8192) /* Default value representing Tm known. 8192 */
+#define TDD_MAX_OFF (8191) /* Maximum effective value of off.*/
+#define TDD_MIN_OFF (0) /* Minimum effective value of off.*/
+#define TDD_RSSI_INVALID (-32768) /* Default value representing RSSI unknown. */
+#define TDD_MAX_RSSI (-100) /* Maximum effective value of rssi.*/
+#define TDD_MIN_RSSI (-400) /* Minimum effective value of rssi.*/
+#define TDD_RSCP_INVALID (0) /* Default value representing RSCP unknown. */
+#define TDD_MAX_RSCP (-100) /* Maximum effective value of rscp.*/
+#define TDD_MIN_RSCP (-500) /* Minimum effective value of rscp.*/
+#define TDD_ISCP_INVALID (0) /* Default value representing ISCP unknown. */
+#define TDD_MAX_ISCP (-100) /* Maximum effective value of iscp.*/
+#define TDD_MIN_ISCP (-480) /* Minimum effective value of iscp.*/
+#define TDD_SIR_INVALID (-32768) /* Default value representing SIR unknown. */
+#define TDD_MAX_SIR (40) /* Maximum effective value of sir.*/
+#define TDD_MIN_SIR (-28) /* Minimum effective value of sir.*/
+#define TDD_TX_POWER_INVALID (-32768) /* Default value representing UE TX POWER unknown. */
+#define TDD_MAX_TX_POWER (136) /* Maximum effective value of UE tx_power.*/
+#define TDD_MIN_TX_POWER (-200) /* Minimum effective value of UE tx_power.*/
+#define TDD_TADV_INVALID (-1) /* Default value representing tadv unknown. */
+#define TDD_MAX_TADV (8191) /* Maximum effective value of tadv.*/
+#define TDD_MIN_TADV (0) /* Minimum effective value of tadv.*/
+#define TDD_UARFCN_INVALID (65535) /* Invalid UARFCN for setting empty freq. entry in meas. config req. */
+#define TDD_DOFF_INVALID (-1) /* Default value representing DOFF unknown. */
+#define TDD_MAX_DOFF (7) /* Maximum effective value of doff.*/
+#define TDD_MIN_DOFF (0) /* Minimum effective value of doff.*/
+#define TDD_CPID_INVALID (255) /* Default value representing CELL_PARAM_ID unknown. */
+#define TDD_MAX_CPID (127) /* Maximum effective value of CPID.*/
+#define TDD_MIN_CPID (0) /* Minimum effective value of CPID.*/
+#define TDD_MEAS_ID_INVALID (0) /* Default value representing MEAS_ID unknown.Valid value range from 1 to 16. */
+#define TDD_MAX_MEAS_ID (16) /* Maximum effective value of meas_id.*/
+#define TDD_MIN_MEAS_ID (1) /* Minimum effective value of meas_id.*/
+#define TDD_BLER_INVALID (-64) /* Default value representing BLER unknown. */
+#define TDD_MAX_BLER (0) /* Maximum effective value of bler.*/
+#define TDD_MIN_BLER (-63) /* Minimum effective value of bler.*/
+#define TDD_PCCPCH_TX_POWER_INVALID (0) /* Default value representing PCCPCH TX POWER unknown. */
+#define TDD_MAX_PCCPCH_TX_POWER (43) /* Maximum effective value of PCCPCH tx_power.*/
+#define TDD_MIN_PCCPCH_TX_POWER (6) /* Minimum effective value of PCCPCH tx_power.*/
+
+
+/*-------- Activation time related constant ----------------------*/
+#define TDD_CFN_IMMEDIATE (-1) /* Immediate CFN activation time. */
+#define TDD_SFN_IMMEDIATE (-1) /* Immediate SFN activation time. */
+
+/*-------- PhyCh related constant ---------------------*/
+#define TDD_MAX_ASC (8) /* Maximum access service class number */
+#define TDD_MAX_RL (1) /* Maximum number of DPCH radio links in TDD128 */
+#define TDD_MAX_TIMESLOT_PER_SUBFRAME (7) /* Maximum number of noraml timeslosts(TS0 ~ TS6) in a subframe in TDD128 */
+#define TDD_MAX_DL_TIMESLOT_PER_SUBFRAME (5) /*Max downlink timeslot in one subframe, only noraml timeslot is count*/
+#define TDD_MAX_UL_TIMESLOT_PER_SUBFRAME (5) /*Max uplink timeslot in one subframe,only noraml timeslot is count */
+#define TDD_MAX_UL_PHYCH_PER_SLOT (2) /*Max physical channel in one slot in uplink*/
+#define TDD_MAX_DL_PHYCH_PER_SLOT (16) /* Max physical channel in one slot in downlink*/
+#define TDD_MAX_DL_PHYCH_PER_SUBFRAME (48) /*Max physical channel in one subframe in downlink*/
+#define TDD_MAX_PRACH_FPACH_NUM (8) /*Maximum number of PRACH / FPACH pairs in a cell (1.28 Mcps TDD)*/
+
+/*-------- HSDPA related constant ---------------------*/
+#define TDD_MAX_HSSCCH_NUM (4) /*The maximum number of HSSCCH assigned to UE by NW*/
+#define TDD_MAX_HARQ_PROCESS_NUM (8) /*Maximum number of HARQ process supported in R5.*/
+#define TDD_MAX_HSDSCH_QUEUE (8) /*Maximum number of HS-DSCH queue supported in R5*/
+#define TDD_MAX_HSDSCH_SIZE (8) /*Maximum number of HS-DSCH size per queue supported in R5*/
+
+#ifdef __HSUPA_SUPPORT__
+#define TDD_MAX_EAGCH_NUM (4) /*Maximum number of E-AGCH assigned to UE by NW.*/
+#define TDD_MAX_EHICH_NUM (4) /*Maximum number of E-HICH assigned to UE by NW.*/
+#define TDD_MAX_REF_BETA_NUM (8) /*Maximum number of reference Beta informationto UE by NW.*/
+#define TDD_MAX_EDCH_HARQ_PROC_PER_MODE (4) /*Maximum number of allocated E-DCH HARQ processes per granting mode.*/
+#define TDD_MAX_EHICH_RESULT_NUM (6) /*Maximum number of E-HICH results can be sent to MAC at one time.*/
+#define TDD_MAX_ETFCI_BITMAP_SIZE (16) /*supported_etfci_bitmap array size. TDD_MAX_ETFCI_BITMAP_SIZE=64/4*/
+#endif
+
+
+/*#define TDD_MAX_ERUCCH (256) max number of ERUCCH*/
+#define TDD_MAX_ERUCCH (8) /*max number of ERUCCH*/
+#define TDD_maxEDCHTxPattern_TDD128 (4) /*max number of EDCH TX pattern for SPS*/
+//#endif
+//#if defined( __UMTS_R9__ ) && defined ( __AST3002__ )
+#define TDD_MAX_DMO_PATTERN_NUM (5)
+//#endif
+
+//replace enums temporarily
+//#ifdef __PS_L1_DC_ARCH__
+#define TDD_T_W_DEDICATED_PCH_BUFFER 1
+#define TDD_gRxPchBuffQueueSize (2)
+#define TDD_gRxDchBuffQueueSize (8)
+#define TDD_gRxDschBuffQueueSize (12)
+
+#define TDD_MAX_NUM_OF_EDCH_HARQ_PROCESS (8)
+#define TDD_MAC_E_PDU_MEMORY_SIZE (1408) // maximum 11160 for TDD128,1400->1408 for 64B Allign
+
+//for HSDPA
+// MAX_MAC_HS_PDU_NUM = MAX_MAC_PDP_SUPPORT * 32(MAX_MAC_HS_WINDOW_SIZE)+MAC_HS_PDU_NUM_MARGIN
+// When support<3 PDP, we leave MAC_HS_PDU_NUM_MARGIN=20, 10 for UL1 pre-get MAC-hs PDU, 10 for margin
+#define TDD_MAX_MAC_PDP_SUPPORT GPRS_MAX_PDP_SUPPORT
+#if TDD_MAX_MAC_PDP_SUPPORT<3
+#define TDD_MAC_HS_PDU_NUM_MARGIN 20
+#else
+#define TDD_MAC_HS_PDU_NUM_MARGIN 0
+#endif
+
+#define TDD_MAX_MAC_HS_PDU_NUM ((TDD_MAX_MAC_PDP_SUPPORT * 32) + TDD_MAC_HS_PDU_NUM_MARGIN)
+
+#define TDD_mBYTE_SIZE_TO_32_BYTE_ALIGN_INC(byteSize) (((byteSize) + 31) & 0xFFE0)
+
+#define TDD_MAX_HS_PDU_SIZE_IN_BYTES (((TDD_MAX_HS_PDU_SIZE_IN_BITS+32+31)/32)*4)
+
+#define TDD_MAX_HS_PDU_SIZE_IN_BITS 14043
+
+#define TDD_DL_ADR_OFFSET (4)
+
+//for RX
+//@review code, TDD_gRxDchBuffQueueSize defined as 8, so we simply redefine TDD_MAX_MAC_DCH_PDU_NUM as 8 + 1
+#if 0
+/* under construction !*/
+#else
+#define TDD_MAX_MAC_DCH_PDU_NUM (6+1+2)
+#define TDD_MAX_MAC_PCH_PDU_NUM (TDD_gRxPchBuffQueueSize+1) /*mac buffer should > tl1 pch buffer, or fator. When receive PCH msg, lumac will alloc new buff if no more will fatal.*/
+#endif
+#define TDD_MAX_MAC_DCH_PDU_SIZE (1472)
+#define TDD_MAX_MAC_PCH_PDU_SIZE (1472)
+//#endif
+
+#define TDD_MAX_MAC_HS_PDU_SIZE 1804 // Category 6 : 14411 bits and need 4-byte alignment
+
+
+
+#endif
diff --git a/mcu/interface/l1/tl1/tl1_def.h b/mcu/interface/l1/tl1/tl1_def.h
new file mode 100644
index 0000000..fc495e8
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1_def.h
@@ -0,0 +1,2444 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2009
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/******************************************************************************
+ * Filename:
+ * --------------------------------------------------------
+ * tl1_def.h
+ *
+ * Project:
+ * --------------------------------------------------------
+ *
+ *
+ * Description:
+ * --------------------------------------------------------
+ *
+ *
+ * Author:
+ * --------------------------------------------------------
+ * -------
+ *
+ * --------------------------------------------------------
+ * $Log$
+ *
+ * 11 14 2019 chason.cheng
+ * [MOLY00456996] TAS ÐèÒªÔö¼ÓSNÊýÁ¿
+ *
+ * .tds increase ant state and sar ant num
+ *
+ * 11 07 2019 chason.cheng
+ * [MOLY00456996] TAS ÐèÒªÔö¼ÓSNÊýÁ¿
+ *
+ * .roll back to 9720865
+ *
+ * 09 18 2019 chason.cheng
+ * [MOLY00425909] [GEN97][VMOLY][DAT]TDS DAT part develop
+ *
+ * .GEN97 SAR LID description
+ *
+ * 09 11 2019 chason.cheng
+ * [MOLY00400428] [GEN97][TAS][ANT] TDS UTAS
+ *
+ * .GEN97 merge SAR from oppo
+ *
+ * 08 26 2019 chason.cheng
+ * [MOLY00400428] [GEN97][TAS][ANT] TDS UTAS
+ *
+ * .merge SAR & SWTP
+ *
+ * 08 21 2019 chason.cheng
+ * [MOLY00400428] [GEN97][TAS][ANT] TDS UTAS
+ *
+ * .pertus tas mipi A D die data issue
+ *
+ * 07 29 2019 chason.cheng
+ * [MOLY00425909] [GEN97][VMOLY][DAT]TDS DAT part develop
+ *
+ * .TDS DAT
+ *
+ * 04 19 2019 chason.cheng
+ * [MOLY00400428] [GEN97][TAS][ANT] TDS UTAS.
+ *
+ * 10 31 2018 xiaochi.zhang
+ * [MOLY00361478] [Gen97] Gemini Compile Option Clean Up
+ *
+ * .
+ *
+ * 10 30 2018 chason.cheng
+ * [MOLY00325833] TDSCDMA GEN97 UNIFY TAS
+ *
+ * 08 27 2018 chason.cheng
+ * [MOLY00325833] TDSCDMA GEN95 UNIFY TAS.TDS fix build error
+ *
+ * 08 22 2018 ting.xu
+ * [MOLY00300045] [TDS][TRINITY POC] Trinity L MT6185M POC porting update debug
+ *
+ * ALIGN UMOLYE.
+ *
+ * 07 20 2018 chason.cheng
+ * [MOLY00325833] TDSCDMA GEN95 UNIFY TAS.TDD UTAS SAR
+ *
+ * 06 20 2018 chason.cheng
+ * [MOLY00325833] TDSCDMA GEN95 UNIFY TAS.GEN 95 DAT
+ *
+ * 06 08 2018 yanhai.xuan
+ * [MOLY00261463] [Coverity defect fix][TDSCDMA]TL1D coverity defect fix
+ * fix xl1sim build error
+ *
+ * 06 08 2018 chason.cheng
+ * [MOLY00325833] TDSCDMA GEN95 UNIFY TAS. UTAS UPDATE
+ *
+ * 05 23 2018 cruze.yu
+ * [MOLY00285698] [93/95 re-arch][TL1] tl1 option clean
+ *
+ * .
+ *
+ * 01 14 2016 yanhai.xuan
+ * [MOLY00159734] TX power detector support on Jade
+ * .
+ *
+ * 04 17 2015 marco.zhang
+ * [MOLY00096053] [TDD] Rx report for test (need turn on __TDS_RX_TEST_SUPPORT__)
+ * .
+ *
+ * 04 16 2015 chuansheng.zhang
+ * [MOLY00097620] [TK6291][UBin] TL1 Platform Patch
+ * TL1: Ubin Phase2 code merge.
+ *
+ * 01 07 2015 marco.zhang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .
+ *
+ * 01 05 2015 fanzhi.meng
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .
+ *
+ * 12 21 2014 marco.zhang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * prefix.
+ *
+ * 12 10 2014 rong.yang
+ * [MOLY00087194] [3G UMAC] merge 6291 code from MOLY.U3G.90IT.DEV
+ * .
+ *
+ * 05 23 2014 xiaoyun.mao
+ * [MOLY00066499] [3G TDD UMAC & L1] DPA & R4 rx memory revise
+ * .rx data path change
+ *
+ * 03 06 2014 xiaoyun.mao
+ * [MOLY00058570] [MT6290E2][SGLTE][82LTEv2][LT+G][GCF][ETC7310][MM][Band 38][Band A][case 8.4.2.2] fail,Öն˷¢ËÍÁËcell updateµ¼ÖÂÓÃÀýʧ°Ü
+ * .DMO optimization: ul tick tell mac DMO info
+ *
+ * 09 26 2013 xiaoyun.mao
+ * [MOLY00036017] [MOLY NOT NEED]GEMINI rxtx protect ÓÅ»¯
+ * .SRB information
+ *
+ * 05 23 2013 xiaoyun.mao
+ * [MOLY00023509] suspend and dm optimization get out of gemini
+ * .
+ *
+ * 05 16 2013 xiaoyun.mao
+ * [MOLY00016548] [MT6290 PO admit][MT6290E1][FirstCall][3G TDD]merge code to Trunk and Development branch
+ * .add bit14 & bch sib7 modify & fix macro redefinition problem
+ *
+ * 04 26 2013 fanzhi.meng
+ * [MOLY00019723] [MT6290 Bring-up]_SCIF MCU/DSP CODE CHECK IN
+ * .WR8 SYNC TO MOLY
+ *
+ * 04 26 2013 xiaoyun.mao
+ * [MOLY00020915] Check in Autonomous gap code
+ * .
+ *
+ * 04 09 2013 ast00029
+ * [MOLY00013377] [TDD128][ESL][MOLY]check-in ESL code.
+ * for ESL
+ *
+ * 04 01 2013 shouzhu.zhang
+ * [MOLY00013249] MM TL1 Code check in
+ * [TL1] Merge lastes WR8 + R9 + MM code to MOLY..
+ *
+ * 03 01 2013 shun.liu
+ * [MOLY00011182] MT6572/6582: RF TX test feature check in MOLY main
+ * EM tx test tl1 part.
+ *
+ * 10 25 2012 ast00029
+ * [MOLY00005252] AST3001µÄTDµÄʧͬ²½fail£¬³öÏÖµôÍø
+ * make c,r ast_l1_ast3001
+ *
+ * for MOLY00005252, don't dl init sync when UPCC and LBM2
+ *
+ * 10 11 2012 shouzhu.zhang
+ * [MOLY00004672] [new feature check in] TDD128 PS Tput optimization about DM gap
+ * .
+ *
+ * 10 10 2012 shouzhu.zhang
+ * [MOLY00004672] [new feature check in] TDD128 PS Tput optimization about DM gap
+ * .
+ *
+ * 10 10 2012 shouzhu.zhang
+ * [MOLY00004672] [new feature check in] TDD128 PS Tput optimization about DM gap
+ * .
+ *
+ * 09 24 2012 xiaoyun.mao
+ * [MOLY00004069] [MOLY]TDD_R9_DEV Patch back to MOLY
+ * TDD_R9_DEV patch back to MOLY
+ *
+ * 05 03 2012 wcpuser_integrator
+ * removed!
+ * .
+ *
+ * 05 03 2012 wcpuser_integrator
+ * removed!
+ * .
+ *
+ * 03 26 2012 shuyang.yin
+ * removed!
+ * .
+ *
+ * 03 21 2012 shuyang.yin
+ * removed!
+ * .
+ *
+ * 03 02 2012 shuyang.yin
+ * removed!
+ * .
+ * (TL1 SAP)
+ *
+ * 02 15 2012 shuyang.yin
+ * removed!
+ * .
+ *
+ * 01 13 2012 shuyang.yin
+ * removed!
+ * .
+ *
+ * 11 14 2011 shi.dong
+ * removed!
+ * TL1 code interface fta merge in MAUI.
+ *
+ * 10 11 2011 shuyang.yin
+ * removed!
+ * .
+ * add compile option to seperate different hardware
+ *
+ * 04 20 2011 xinqiu.wang
+ * removed!
+ * Modify some description.
+ *
+ * 04 19 2011 xinqiu.wang
+ * removed!
+ * merge code from daily LOAD to MAUI 10A.
+ *
+ * 01 18 2011 xinqiu.wang
+ * removed!
+ * Add RHR feature to tl1 interface files.
+ *
+ * 12 14 2010 xinqiu.wang
+ * removed!
+ * Modify the struct of phy_post_tx_ind.
+ *
+ * 12 01 2010 popcafa.shih
+ * removed!
+ * .
+ *
+ * 11 29 2010 xinqiu.wang
+ * removed!
+ * Modify the description of umts_power_class.
+ *
+ * 11 04 2010 xinqiu.wang
+ * removed!
+ * 1. Add ul_mac_event to cphy_dch_setup/modify/release_req
+ * 2. Add two ticks and structs for mac-tl1 interface.
+ * 3. Add two simulation structs according to MAC's requeset.
+ *
+ * 11 03 2010 xinqiu.wang
+ * removed!
+ * 1.SLCE-TL1 SAP Modify for R7
+ * 2. MAC-TL1 SAP Modify for UPA
+ *
+ * 08 24 2010 popcafa.shih
+ * removed!
+ * .
+ *
+ * removed!
+ * removed!
+ * 1.In etfc_eval_info_ind_T, modify the description of retx_pdu_timeslots_used[] and retx_pdu_etfci[], to replace MAC-d to MAC-e.
+ * 2.Modify the BLER_INVALID to -64 in related description.
+ *
+ * removed!
+ * removed!
+ * 1.Modify comments of mac_harq_event in etfc_eval_info_req_T.
+ * 2.Modify comments of is_new_tx_required in edch_data_req_T.
+ * 3.Modify the comments of tx_power in tx_power_info_T.
+ *
+ * removed!
+ * removed!
+ * 1.Add pccpch_tx_power in cell_info_list_T
+ * 2.Replace repeat_offset with act_time and subframe_num in edch_non_sched_grant_info_T
+ * 3.Modify the comments of mac_event in etfc_eval_info_req_T, which is to change the meaning of bit1 from release to modify.
+ * 4.Modify the comments to add range of ts_num in eagch_config_T, num_prach_definition in erucch_info_T,num_ref_qpsk & num_ref_16qam& ref_code_rate_qpsk& ref_beta_qpsk&ref_code_rate_16qam&ref_beta_16qam in edch_etfcs_T
+ * 5.Modify comments of sync_ul_bitmap in sync_ul_erucch_info_T
+ * 6.Modify range of bler_target in eagch_info_T
+ * 7.Modify comments of ss_tpc_symbols in phy_signaling_info_T, retx_pdu_etfci[] in etfc_eval_info_ind_T
+ * 8.Add uppch_shift, max_tx_power, umts_power_class in sync_ul_erucch_info_T.
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ * 1.Delete type definition of meas_control_E
+ * 2.Modify range of iscp_timeslot_bitmap from 2~6 to 0~6 in comments
+ * 3.Add HSUPA related type definition.
+ *
+ * removed!
+ * removed!
+ * 1.Delete pre-declare check of __UMTS_TDD128_MODE__
+ * 2.Add AI_PARAMERROR_NO_UPPCH_SUBCHANNEL, AI_PARAMERROR_NO_RACH_DATA and AI_PARAMERROR_NO_RACH_CFG in access_status_E
+ *
+ * removed!
+ * removed!
+ * 1.Add comments of BCH_PRIOMEDIUM in bch_priority_T
+ * 2.Modify UL1_RAT_FLIGHT/UMTS/GSM to TL1_RAT_FLIGHT/UMTS/GSM
+ * 3.Use TL1 to replace UL1 and L1 in comments
+ * 4.In ss_tpc_len_E, modify SS_TPC_X_SYMBOLS(X=2,4,8,16) to SS_TPC_16_DIVIDE_SF_SYMBOLS
+ * 5.Modify type phy_sigaling_info_T to phy_signaling_info_T and modify phy_signalling to phy_signaling
+ * 6.Modify comments of ccode in hssich_info_T, comments of ts_num in hsscch_config_T and comments of is_valid_data in hsdsch_data_T
+ * 7.add pre-declare check of __UMTS_TDD128_MODE__
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ * Add description of threshold in meas_event_T for internal measurement
+ *
+ * removed!
+ * removed!
+ * 1. rename the modulation_E to tdd128_modulation_E
+ *
+ * removed!
+ * removed!
+ * 1. remove the last comma in the enum defination, which cause compiling error
+ * 2.change the type of num_timeslot in dl_dpch_rl_T from "kal_int8" to "kal_uint8"
+ *
+ * removed!
+ * removed!
+ * Rename __UMTS_TDD128_RAT__ to __UMTS_TDD128_MODE__
+ *
+ * removed!
+ * removed!
+ * add log section for tl1interface header files
+ *
+*******************************************************************************/
+
+#ifndef _TL1_DEF_H
+#define _TL1_DEF_H
+
+#include "kal_public_api.h" //MSBB change #include "kal_release.h"
+#include "tl1_cnst.h"
+#include "gmss_public.h" /*Ubin xxx_duplex_mode_type define*/
+
+//MCU and DMA mode switch for TL1 and MAC using
+
+/*macro for for constant */
+#define CRC_LENGTH_0_BITS 0
+#define CRC_LENGTH_8_BITS 8
+#define CRC_LENGTH_12_BITS 12
+#define CRC_LENGTH_16_BITS 16
+#define CRC_LENGTH_24_BITS 24
+
+/*TTI length in subframe*/
+#define TTI_5_MS 1
+#define TTI_10_MS 2
+#define TTI_20_MS 4
+#define TTI_40_MS 8
+#define TTI_80_MS 16
+#define MAX_TTI TTI_80_MS
+
+/*bit map of channelisation code*/
+#define CCODE_16_1 (0x00000001)
+#define CCODE_16_2 (0x00000002)
+#define CCODE_16_3 (0x00000004)
+#define CCODE_16_4 (0x00000008)
+#define CCODE_16_5 (0x00000010)
+#define CCODE_16_6 (0x00000020)
+#define CCODE_16_7 (0x00000040)
+#define CCODE_16_8 (0x00000080)
+#define CCODE_16_9 (0x00000100)
+#define CCODE_16_10 (0x00000200)
+#define CCODE_16_11 (0x00000400)
+#define CCODE_16_12 (0x00000800)
+#define CCODE_16_13 (0x00001000)
+#define CCODE_16_14 (0x00002000)
+#define CCODE_16_15 (0x00004000)
+#define CCODE_16_16 (0x00008000)
+
+#define CCODE_8_1 (0x00010000)
+#define CCODE_8_2 (0x00020000)
+#define CCODE_8_3 (0x00040000)
+#define CCODE_8_4 (0x00080000)
+#define CCODE_8_5 (0x00100000)
+#define CCODE_8_6 (0x00200000)
+#define CCODE_8_7 (0x00400000)
+#define CCODE_8_8 (0x00800000)
+
+#define CCODE_4_1 (0x01000000)
+#define CCODE_4_2 (0x02000000)
+#define CCODE_4_3 (0x04000000)
+#define CCODE_4_4 (0x08000000)
+
+#define CCODE_2_1 (0x10000000)
+#define CCODE_2_2 (0x20000000)
+
+#define CCODE_1_1 (0x40000000)
+#define CCODE_RESERVED (0x80000000)
+
+#define CCODE_SF1_MASK (0x40000000)
+#define CCODE_SF2_MASK (0x30000000)
+#define CCODE_SF4_MASK (0x0F000000)
+#define CCODE_SF8_MASK (0x00FF0000)
+#define CCODE_SF16_MASK (0x0000FFFF)
+
+#define CCODE_SF1_SHFT (30)
+#define CCODE_SF2_SHFT (28)
+#define CCODE_SF4_SHFT (24)
+#define CCODE_SF8_SHFT (16)
+#define CCODE_SF16_SHFT (0)
+
+/*timeslot mask*/
+#define TIMESLOT_0_MASK (0x01)
+#define TIMESLOT_1_MASK (0x02)
+#define TIMESLOT_2_MASK (0x04)
+#define TIMESLOT_3_MASK (0x08)
+#define TIMESLOT_4_MASK (0x10)
+#define TIMESLOT_5_MASK (0x20)
+#define TIMESLOT_6_MASK (0x40)
+#define TIMESLOT_DWPTS_MASK (0x80) /*for rx */
+#define TIMESLOT_UPPCH_MASK (0x100) /*for tx*/
+
+
+/*dch modify field mask*/
+#define DCH_MODIFY_NONE 0x00000000
+#define DCH_MODIFY_DL_TRCH_PARAM 0x00000001
+#define DCH_MODIFY_DL_TFCS_PARAM 0x00000002
+#define DCH_MODIFY_UL_TRCH_PARAM 0x00000004
+#define DCH_MODIFY_UL_TFCS_PARAM 0x00000008
+#define DCH_MODIFY_DL_COMM_RL_PARAM 0x00000010
+#define DCH_MODIFY_DL_EACH_RL_PARAM 0x00000020
+#define DCH_MODIFY_UL_RL_PARAM 0x00000040
+#define DCH_MODIFY_PHY_PARAM 0x00000080
+#define DCH_MODIFY_DL_ESTABLISH_PARAM 0x00000100
+#define DCH_MODIFY_SBGP 0x00000200
+#define DCH_MODIFY_UL_POWER_INFO 0x00000400
+#define DCH_MODIFY_ALL 0xFFFFFFFF/*when dch-setup-req, set the value.*/
+
+/*bch modify_field bit mask*/
+#define BCH_PRIORITY_CAHNGE 0x01
+#define BCH_SIB_SCHEDULE_CAHNGE 0x02
+
+/*AST trace compile option*/
+//#ifdef NAND_SUPPORT
+//#ifndef __AST_TRACE_TST_ENABLE__
+//#define __AST_TRACE_TST_ENABLE__
+//#endif
+//#endif /*NAND_SUPPORT*/
+#if defined(__MD95__)
+#define TDS_TL1_SAR_ANT_PHYSICAL_TL1D_SUPPORT_NUMBER (8)
+#endif
+#if defined(__MD97__)
+#define TDS_TL1_SAR_ANT_PHYSICAL_TL1D_SUPPORT_NUMBER (16)
+#endif
+
+#if (defined(__MD95__) || defined(__MD97__))
+#define TDS_TL1_SAR_ANT_PHYSICAL_CUSTOMER_SUPPORT_NUMBER (5)
+#define TDS_TL1_SAR_ANT_FREQLIST_SUPPORT_NUMBER (3)
+#endif
+
+#if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__) && defined(__MD95__)
+#define TDS_TL1_SAR_ANT_SCENARIOR_SUPPORT_NUMBER (9)
+#endif
+
+#if defined(__SAR_TX_POWER_BACKOFF_SUPPORT__) && defined(__MD97__)
+#define TDS_TL1_SAR_ANT_SCENARIOR_SUPPORT_NUMBER (21)
+#endif
+
+#if defined(__TX_POWER_OFFSET_SUPPORT__)
+#define TDS_TL1_SWTP_ANT_SCENARIOR_SUPPORT_NUMBER (1)
+#endif
+
+#define TDS_TL1_SAR_ANT_POWERBACK_DIMON_NUMBER (3)
+#define TDS_TL1_SAR_ANT_DIFF_ANT_OFT_FIX_UTAS (7)
+
+
+#define TDS_TL1_TAS_PHYSICAL_SUPPORT_BAND (0x02)
+#define TDS_TL1_UTAS_SUPPORT_VERSION (0x03)
+#define TDS_TL1_UTAS_BAND34_IND (0x0)
+#define TDS_TL1_UTAS_BAND39_IND (0x1)
+#define TDS_TL1_UTAS_BAND34_NUMBER (34)
+#define TDS_TL1_UTAS_BAND39_NUMBER (39)
+
+#define TDS_TL1_TAS_PHYSICAL_MIPI_DEVICE_NUMBER (0x06)
+#define TDS_TL1_DAT_PHYSICAL_MIPI_DEVICE_NUMBER (0x05)
+/*2 ANT no need clear meas result, because alway meas the same ant
+ above 2 ant, we need clear period! 200ms switch ant port. 4 result(50ms/200ms) judge switch or not
+ this also the diff between V1.0 & V2.0 TAS*/
+#define TDS_TL1_TAS_STATE_CLEAR_RESULT_THREADHOLD (0x2)
+#define TDS_TL1_TAS_MEAS_COMMAND_IDX_SHIFT_LENGTH (0x2)
+#define TDS_TL1_TAS_BAND34_L1_MAX_FREQ (10125)
+#define TDS_TL1_TAS_BAND34_L1_MIN_FREQ (10050)
+#define TDS_TL1_TAS_BAND39_L1_MAX_FREQ_EXT (9600)
+#define TDS_TL1_TAS_BAND39_L1_MIN_FREQ_EXT (9400)
+#define TDS_TL1_TAS_BAND40_L1_MAX_FREQ_EXT1 (12000)
+#define TDS_TL1_TAS_BAND40_L1_MIN_FREQ_EXT1 (11500)
+#define TDS_TL1_TAS_BAND_MESSAGE_NULL_IND (0xFFFF)
+
+
+#if (defined(__MD95__) || defined(__MD97__))
+#define TDS_TL1_UTAS_SWITCH_IND (0x0)
+#define TDS_TL1_UTAS_TUNING_IND (0x1)
+#define TDS_TL1_UTAS_SWITCH_TUNER_NUM 2
+#define TDS_TL1_UTAS_ANT_INDEX_PORT_BIT_WIDTH (0x04)
+#define TDS_TL1_UTAS_ANT_INDEX_PORT_BIT_MASK (0x000F)
+#define TDS_TL1_UTAS_RX_PRIANT_PORT_NUMBER_IND (0x0)
+//#define TDS_TL1_UTAS_MML1_ANT_MAX_STATE_SETTING (24) // MMRFD_TAS_STATE_NUM MUST align with mml1
+#define TDS_TL1_UTAS_MML1_ANT_UNAVAILBLE_SETTING (0xFF) //MMRFD_TAS_STATE_NULL MUST align with mml1
+#define TDS_TL1_UTAS_ANT_TUNER_CONTROL_SETTING_NUM (34) //MMRFD_ANT_TUNER_CONTROL_SETTING_NUM MUST align with mml1
+#define TDS_TL1_UTAS_MMRFD_TAS_MAX_HW_GROUP_NUM (10) //MMRFD_TAS_MAX_HW_GROUP_NUM MUST align with mml1
+#define TDSCDMA_TAS_MIPI_TABLE_MAX_DATA_ROUTE 32
+
+#define TDSCDMA_DAT_MIPI_TABLE_MAX_DATA_ROUTE 32
+#define TDS_TL1_DAT_SWITCH_TUNER_NUM 2
+#define TDS_TL1_DAT_SWITCH_IND (0x0)
+#define TDS_TL1_DAT_TUNING_IND (0x1)
+#define TDS_TL1_RX_TX_NUM 2
+#define TDS_TL1_RX_INDEX 0
+#define TDS_TL1_TX_INDEX 1
+
+/*UTAS95 used for internal TDS state idx! careful: meaning IDX */
+typedef enum
+ {
+ TDSCDMA_TAS_STATE0,
+ TDSCDMA_TAS_STATE1,
+ TDSCDMA_TAS_STATE2,
+ TDSCDMA_TAS_STATE3,
+ TDSCDMA_TAS_STATE4,
+ TDSCDMA_TAS_STATE5,
+ TDSCDMA_TAS_STATE6,
+ TDSCDMA_TAS_STATE7,
+ TDSCDMA_TAS_STATE_NUM,
+ TDSCDMA_TAS_STATE_NULL = TDS_TL1_UTAS_MML1_ANT_UNAVAILBLE_SETTING,
+ }TDSCDMA_CUSTOM_TAS_STATE_E;
+
+/*UTAS95 used for internal TDS ant port! careful: meaning ant port number, physical ant port number */
+typedef enum
+ {
+ TDSCDMA_TAS_STATE0_ANT_PORT,
+ TDSCDMA_TAS_STATE1_ANT_PORT,
+ TDSCDMA_TAS_STATE2_ANT_PORT,
+ TDSCDMA_TAS_STATE3_ANT_PORT,
+ TDSCDMA_TAS_STATE4_ANT_PORT,
+ TDSCDMA_TAS_STATE5_ANT_PORT,
+ TDSCDMA_TAS_STATE6_ANT_PORT,
+ TDSCDMA_TAS_STATE7_ANT_PORT,
+ TDSCDMA_TAS_STATE8_ANT_PORT,
+ TDSCDMA_TAS_STATE9_ANT_PORT,
+ TDSCDMA_TAS_STATE10_ANT_PORT,
+ TDSCDMA_TAS_STATE11_ANT_PORT,
+ TDSCDMA_TAS_STATE12_ANT_PORT,
+ TDSCDMA_TAS_STATE13_ANT_PORT,
+ TDSCDMA_TAS_STATE14_ANT_PORT,
+ TDSCDMA_TAS_STATE15_ANT_PORT,
+ TDSCDMA_TAS_STATE_NUM_ANT_PORT,
+ TDSCDMA_TAS_STATE_NULL_ANT_PORT = TDS_TL1_UTAS_MML1_ANT_UNAVAILBLE_SETTING,
+ }TDSCDMA_CUSTOM_TAS_STATE_ANT_PORT_E;
+
+
+/*UTAS config check error code */
+
+#define TDS_TL1_UTAS_ERROR_CHECK_MMRFD_HW_GROUP_NUM_IDX (0x1)
+#define TDS_TL1_UTAS_ERROR_CHECK_MML1_ANT_TUNER_CONTROL_SETTING_IDX (0x2)
+#define TDS_TL1_UTAS_ERROR_CHECK_META_BAND_ROUTE_INIT_SETTING_REAL (0x3)
+#define TDS_TL1_UTAS_ERROR_CHECK_FORCE_MODE_TAS_FEATURE (0x4)
+#define TDS_TL1_UTAS_ERROR_CHECK_REALSIM_BAND34_INIT_STATE (0x5)
+#define TDS_TL1_UTAS_ERROR_CHECK_REALSIM_BAND39_INIT_STATE (0x6)
+#define TDS_TL1_UTAS_ERROR_CHECK_TESTSIM_BAND34_INIT_STATE (0x7)
+#define TDS_TL1_UTAS_ERROR_CHECK_TESTSIM_BAND39_INIT_STATE (0x8)
+#define TDS_TL1_UTAS_ERROR_CHECK_STATE_CHANGE_TO_IDX_FAIL (0x9)
+#define TDS_TL1_UTAS_ERROR_CHECK_BAND34_MAX_ANT_STATE_OVERRIDE (0xA)
+#define TDS_TL1_UTAS_ERROR_CHECK_BAND39_MAX_ANT_STATE_OVERRIDE (0xB)
+#define TDS_TL1_UTAS_ERROR_CHECK_FORCE_ENABLE_STATE_MISMATCH_BYBAND (0xC)
+#define TDS_TL1_UTAS_ERROR_CHECK_FORCE_ENABLE_STATE_MISMATCH_BYCOMMON (0xD)
+#define TDS_TL1_UTAS_ERROR_CHECK_TDS_REALSIM_STATE_MISMATCH_MML1_CONFIG (0xE)
+#define TDS_TL1_UTAS_ERROR_CHECK_TDS_TESTSIM_STATE_MISMATCH_MML1_CONFIG (0xF)
+#define TDS_TL1_UTAS_ERROR_CHECK_TDS_META_STATE_MISMATCH_MML1_CONFIG (0x10)
+
+
+#define TDS_TL1_TAS_PHYSICAL_MAX_ANT (0x08)
+#define TDS_TL1_TAS_STATE_BITMAP_LENGTH (0x08)
+#define TDS_TL1_TAS_D_DIE_IDX (0x0)
+#define TDS_TL1_TAS_A_DIE_IDX (0x1)
+#define TDS_TL1_TAS_A_D_DIE_NUM (0x2)
+#define TDS_TL1_TAS_PHYSICAL_ANT_NUM (0x10)
+#endif
+
+#define TDS_TL1_DAT_MAX_STATE (0x08)
+#define TDS_TL1_DAT_D_DIE_IDX (0x0)
+#define TDS_TL1_DAT_A_DIE_IDX (0x1)
+#define TDS_TL1_DAT_A_D_DIE_NUM (0x2)
+
+
+/*MTK80428 UMAC TL1 related definition*/
+typedef struct
+{
+ kal_bool IsPartOfMinSet;
+ kal_uint16 TFCI;
+ kal_uint32 CTFC;
+ kal_uint32 TFI[TDD_MAX_TRCH_NUM];
+ kal_int32 aPriorityBits[13];
+} TDD_tTFC;
+
+
+/*-------- PhyCH related definition ----------------------*/
+typedef enum _TDD_access_status_E
+{
+ TDD_AI_ACK = 0, /* Network ACK */
+ TDD_AI_NACK, /* Network NACK in AICH,TL1 will not support this item. */
+ TDD_AI_NOACK, /* Network sends "NO_ACK"*/
+ TDD_AI_ABORT, /* Access transaction has been aborted as result of high layer
+ reconfiguration(from RRC).EX:CPHY_RACH_RELEASE_REQ*/
+ TDD_AI_PARAMERROR, /*replaced by NO_UPPCH_SUBCHANNEL,NO_RACH_DATA and NO_RACH_CFG*/
+ TDD_AI_NESTEDREQUEST, /*Not used in TDD128*/
+ TDD_AI_PARAMERROR_NO_UPPCH_SUBCHANNEL, /*uppch subchannel is zero according to asc index*/
+ TDD_AI_PARAMERROR_NO_RACH_DATA, /*no valid rach data in TL1 when receiving PHY_ACCESS_REQ*/
+ TDD_AI_PARAMERROR_NO_RACH_CFG /*no active rach channel when receiving PHY_ACCESS_REQ*/
+} TDD_access_status_E;
+
+
+
+/*-------- TFS related definition ----------------------*/
+typedef enum _TDD_cc_type_T
+{
+ TDD_CC_NONE = 0, /*No coding*/
+ TDD_CC_CONV12, /*Convolution coding with coding rate 1/2*/
+ TDD_CC_CONV13, /*Convolution coding with coding rate 1/3*/
+ TDD_CC_TURBO /*Turbo coding */
+} TDD_cc_type_T;
+
+typedef enum
+{
+ TDD_GAIN_FACTOR_NONE = 0, /*no gian factor applied */
+ TDD_GAIN_FACTOR_SIGNAL, /*gain factor indicated by signal */
+ TDD_GAIN_FACTOR_COMPUTE /*computed gain factor */
+} TDD_gain_factor_E;
+
+typedef struct _TDD_tfs_static_T
+{
+ kal_uint8 tti; /* TTI. 1, 2, 4, 8, 16, in unit of subframe frame.*/
+ TDD_cc_type_T channel_coding; /* Coding type */
+ kal_uint8 rm_attr; /* RM attribute */
+ kal_uint8 crc_size; /* # of CRC bits. 0,8,12,16,24 */
+} TDD_tfs_static_T;
+
+typedef struct _TDD_tfs_dyn_T
+{
+ kal_uint8 tb_num; /* # of TB */
+ kal_uint16 tb_size; /* # of bibts in a TB */
+} TDD_tfs_dyn_T;
+
+typedef struct _TDD_tfs_T
+{
+ kal_uint8 tf_num; /* # of TF in this TFS */
+ TDD_tfs_dyn_T tfs_dynamic[TDD_MAXTF]; /* TFS dynamic part */
+ TDD_tfs_static_T tfs_static; /* TFS static part */
+} TDD_tfs_T;
+
+
+typedef struct _TDD_dl_establish_T
+{
+ kal_uint8 t312; /* T312 */
+ kal_uint16 n312; /* N312 */
+ kal_uint8 n313; /* N313 */
+ kal_uint8 t313; /* T313 */
+ kal_uint16 n315; /* N315 */
+} TDD_dl_establish_T;
+
+/*-------- TFCS related definition ----------------------*/
+typedef struct _TDD_sig_gain_T
+{
+ kal_uint8 beta_d; /* Bd. 0 ~ 15 */
+ kal_int8 ref_tfc_id; /* Reference TFC ID. -1 ~ 3. */
+ /* 0 ~ 3 : This TFCI is a referenced id for other computed TFC. */
+ /* -1 : It is an invalid value. Means it will not be referenced by other TFC. */
+} TDD_sig_gain_T;
+
+typedef union _TDD_gain_factor_U
+{
+ kal_int8 computed_gain_id; /* For computed gain factor using reference TFC id. 0 ~ 3 */
+ TDD_sig_gain_T sig_gain; /* The signaled gain factor. */
+} TDD_gain_factor_U;
+
+
+typedef struct _TDD_ul_dpch_tfc_T
+{
+ kal_uint8 tfi_list[TDD_MAX_TRCH_NUM]; /* The list of TFI for this TFCI for UL DCH TrCH */
+ TDD_gain_factor_E gain_factor_ind; /* Gain factor enum:TDD_GAIN_FACTOR_NONE,TDD_GAIN_FACTOR_SIGNAL,TDD_GAIN_FACTOR_COMPUTE */
+ TDD_gain_factor_U gain_factor; /* The union of gain factor for computed and signaled type. */
+} TDD_ul_dpch_tfc_T;
+
+typedef struct _TDD_rach_tfc_T
+{
+ kal_uint8 tfi_list; /* The list of TFI for this TFCI. The number of TrCH for PRACH is 1. */
+ kal_bool sig_gain_ind; /* True: Gain factor is siganled. False: Gain factor is computed from reference TFCI */
+ kal_int8 msg_pwr_offset; /* Power offset between the last preamble and the control part of RACH */
+ TDD_gain_factor_U gain_factor; /* Gain factor */
+} TDD_ul_rach_tfc_T;
+
+typedef struct _TDD_dl_tfc_T
+{
+ kal_uint8 tfi_list[TDD_MAX_TRCH_NUM]; /* The list of TFI for this TFCI for DL TrCH */
+} TDD_dl_tfc_T;
+
+/*-------- TrCH related definition ----------------------*/
+
+typedef struct _TDD_trch_T
+{
+ kal_uint8 trch_id; /* TrCH ID 1 ~ 32 */
+ kal_uint8 bit_offset; /* Bit offset. 0 ~ 7 ,Bit offset in PHY_DATA_IND*/
+ TDD_tfs_T tfs; /* TFS of this TrCH */
+ kal_int8 target_bler; /* [Range]: -63 ~ 0, -64.Dividing the value
+ of this field to 10 get the real BLER. "target_bler?value will be: -63 ~ 0
+ (real BLER: -6.3~0 = log10 (BLER)).-64 is used for invalid value to inform TL1
+ that this field is not configured by NW.*/
+} TDD_trch_T,
+ TDD_ul_rach_trch_T,
+ TDD_ul_dch_trch_T,
+ TDD_dl_fachpch_trch_T,
+ TDD_dl_dch_trch_T;
+
+
+/*-------- CCTrCH related definition ----------------------*/
+typedef enum _TDD_cctrch_type_E
+{
+ TDD_CCTRCH_UL_RACH, /* UL RACH CCTrCH */
+ TDD_CCTRCH_UL_DCH, /* UL DCH CCTrCH */
+ TDD_CCTRCH_DL_DCH, /* DL DCH CCTrCH */
+ TDD_CCTRCH_DL_PCH, /* DL PCH CCTrCH */
+ TDD_CCTRCH_DL_FACH, /* DL FACH CCTrCH */
+ TDD_CCTRCH_DL_BCH, /* DL BCH CCTrCH */
+ TDD_MAX_NUM_CCTRCH_TYPE /*2009/07/07 mtk80318: add */
+} TDD_cctrch_type_E;
+
+/*-------- BCH related definition ----------------------*/
+typedef struct _TDD_sib_info_T
+{
+ kal_uint8 seg_count; /* SEG_COUNT 1 ~ 16 */
+ kal_uint16 sib_rep; /* SIB_REP 2^2 ~ 2^12 */
+ kal_uint16 sib_pos; /* SIB_POS 0 ~ sib_rep-2 */
+ kal_uint8 sib_off[TDD_MAX_SIB_SEG_COUNT]; /* SIB_OFF 2 ~ 32 The # of elements of this field is equal to seg_count-1 */
+} TDD_sib_info_T;
+
+typedef enum _TDD_bch_priority_T
+{
+ TDD_BCH_PRIOHIGH, /* Priority High */
+ TDD_BCH_PRIOMEDIUM, /* Priority Medium, not used currrently, just keep for future use*/
+ TDD_BCH_PRIOLOW /* Priority Low */
+} TDD_bch_priority_T;
+
+/*-------- Data related definition ----------------------*/
+typedef struct _TDD_dlTrchData
+{
+ kal_uint8 trchId; /* TrCH ID */
+ kal_uint16 tb_size; /* TB size in bit. 0 ~ 4992 */
+ kal_uint16 num_tb; /* # of TB. 0 ~ 512 */
+} TDD_dlTrchData;
+
+typedef struct _TDD_ulTrchData
+{
+ kal_uint8 trchId; /* TrCH ID */
+ kal_uint16 tb_size; /* TB size in bit. 0 ~ 4992 */
+ kal_uint16 num_tb; /* # of TB. 0 ~ 512 */
+} TDD_ulTrchData;
+
+/*tx enable type*/
+typedef enum _TDD_tx_enable_type_E
+{
+ TDD_TX_ENABLED = 0,
+ TDD_TX_DISABLED_TDM_GAP,
+ TDD_TX_DISABLED_DCH_RELEASE_ONLY,
+ TDD_TX_DISABLED_DM_GAP,
+#ifdef __GEMINI__
+ TDD_TX_DISABLED_NO_DPCH,
+ TDD_TX_DISABLED_GEMINI_GAP,
+#else
+ TDD_TX_DISABLED_NO_DPCH
+#endif
+}TDD_tx_enable_type_E;
+
+typedef struct _TDD_uldch_data_req_T
+{
+ kal_uint8 cfn;
+ kal_uint8 ul_mac_event; /* bit 0: UL DCH setup, */
+ /* bit 1: UL DCH release, */
+ /* bit 2: UL DCH modify */
+ TDD_tx_enable_type_E tx_enable;
+ kal_bool tx_suspend;
+ kal_uint8 tfc_status[TDD_MAX_UL_TFC];
+
+ kal_uint8 meas_occasion_ind;
+
+} TDD_uldch_data_req_T;
+
+/* uldch data indication, mac to tl1 */
+typedef struct _TDD_uldch_data_ind_T
+{
+ kal_bool bTxDataAvailable; //KAL_FALSE: no data to send; KAL_TRUE: need send data, included SB
+ kal_uint8 cfn;
+ kal_bool is_10_srb;
+ kal_bool is_40_srb;
+ kal_uint8 num_trch;
+ TDD_ulTrchData trchInfo[TDD_MAX_TRCH_NUM]; /* TrCH information including number of TB and TB size. Note that only 1 TRCH is included in RACH data. */
+ kal_uint16 tfci;
+ kal_uint16 num_data[TDD_MAX_TRCH_NUM]; /* num_data[TDD_MAX_TRCH_NUM]. It means the total TB size on 1 TRCH. Value: 0 ~ TDD_MAX_UL_TB. */
+ kal_uint8 *data[TDD_MAX_TRCH_NUM]; /*Point to ÿÌõTRCH data buffer. Data buffÓÉMAC allocate and bufferÖ¸ÕëÓÉMACÌîÈ룬ÓÉTL1D¶ÁÈ¡¡£µ±TL1D´¦ÀíÍêTX dataºó»á·¢ËÍPOST TX DATA IND֪ͨMACÊÍ·Å¡£ÐèÒªsystem service±£Ö¤MAC of CR4ÓëTL1D of MD32¿´µ½µÄbufferµØÖ·ÊÇÒ»ÑùµÄ¡£*/
+ TDD_tTFC *pTFC; /* Store the chosen TFC structure pointer. Use it to assign pCCTrCh->pTFCInLastTTI */
+} TDD_uldch_data_ind_T;
+
+typedef enum _TDD_measured_type_T
+{
+ TDD_INTRA_FREQUENCY_MEASURED, /*Intra-Frequency measurement.*/
+ TDD_INTER_FREQUENCY_MEASURED, /*Inter-Frequency measurement.*/
+ TDD_FREQ_SCAN_DETECTED, /*The measured cell is detected in the frequency scan procedure.*/
+ TDD_SERVING_ONLY /*Serving cell measurement*/
+} TDD_measured_type_T;
+
+/*-------- FACH MO related definition ----------------------*/
+typedef struct _TDD_fach_mo_info_T
+{
+ kal_uint8 n; /* # of frames in max TTI. 1,2,4,8 */
+ kal_uint8 k; /* MO cycle length coefficient. M_REP=2^k */
+ kal_bool inter_freq_ind; /* Indicate if inter-frequency meas in MO */
+ kal_bool inter_rat_ind; /* Indicate if inter-RAT meas in MO */
+ kal_uint16 start_off; /* C_RNTI % M_REP. 0 ~ 4095 */
+} TDD_fach_mo_info_T;
+
+/*-------- Operation-Mode related definition ----------------------*/
+
+typedef enum _TDD_mode_type_E
+{
+ TDD_OM_SINGLE, /* Single Mode */
+ TDD_OM_MULTI, /* MULTI Mode */
+ TDD_OM_DUAL //for build
+} TDD_mode_type_E;
+
+typedef enum _TDD_rat_type_E
+{
+ TDD_TL1_RAT_UMTS_ACTIVE, /* UMTS active */
+ TDD_TL1_RAT_UMTS_INACTIVE, /* UMTS_Inactive*/
+ TDD_TL1_RAT_FLIGHT, /* Flight mode */
+ TDD_TL1_RAT_UMTS, //for build
+ TDD_TL1_RAT_GSM //for build
+} TDD_rat_type_E;
+
+typedef struct _TDD_duplex_mode_info_T
+{
+ umts_duplex_mode_type source_umts_duplex_mode;
+ umts_duplex_mode_type target_umts_duplex_mode;
+ lte_duplex_mode_type source_lte_duplex_mode;
+ lte_duplex_mode_type target_lte_duplex_mode;
+} TDD_duplex_mode_info_T;
+
+
+/*-------- Message(Primitive) related definition ----------------------*/
+
+typedef enum _TDD_dch_modify_msg_type_E
+{
+ TDD_DCH_RECONFIG = 0, /* Used when DCH is reconfigured */
+ TDD_DCH_LOOP_MODE_2 = 2, /* Used when DCH loop back mode 2 */
+ TDD_DCH_UPLINK_PHYSICAL_CHANNEL_CONTROL, /* Used when Physical channel control message received */
+} TDD_dch_modify_msg_type_E;
+
+
+typedef enum _TDD_msg_container_error_E /* Error cause of message container, MA only*/
+{
+ TDD_NONE,
+ TDD_DCH_FAIL,
+ TDD_COMMON_FAIL
+} TDD_msg_container_error_E;
+
+
+/*
+typedef enum _meas_control_E
+{
+ MEAS_CTRL_INVALID, // No meas. control action in current MSG_CONTAINER
+ MEAS_STOP, //TL1 do not need to resume measurement after apply current MSG_CONTAINER
+ MEAS_CONTI // TL1 do need to resume measurement after apply current MSG_CONTAINER
+} meas_control_E;
+*/
+/*Add for improving full band FS efficiency -- by excluding some UARFCN or some frequency range*/
+typedef enum _TDD_full_band_option_E
+{
+ TDD_FULL_BAND_ONLY, /*Normal full band FS*/
+ TDD_FULL_BAND_AND_EXCLUDE /*Full band FS but the indicated frequency list/range will be excluded in the full band FS procedure*/
+} TDD_full_band_option_E;
+
+
+
+
+typedef enum
+{
+ TDD_CRC_ERROR,
+ TDD_CRC_OK,
+ TDD_CRC_NO_CRC
+} TDD_crc_status_E;
+
+/*Define tineslot*/
+typedef enum
+{
+ TDD_TIMESLOT_0 = 0,
+ TDD_TIMESLOT_1,
+ TDD_TIMESLOT_2,
+ TDD_TIMESLOT_3,
+ TDD_TIMESLOT_4,
+ TDD_TIMESLOT_5,
+ TDD_TIMESLOT_6,
+ TDD_TIMESLOT_DWPTS,
+ TDD_TIMESLOT_UPPCH /*TDD_MAX_TIMESLOT_PER_SUBFRAME does not inlcude dwpts and uppch*/
+} TDD_timeslot_E;
+
+typedef enum
+{
+ TDD_DL_DIRECTION =0,
+ TDD_UL_DIRECTION,
+ TDD_MAX_NUM_DIRECTION
+}TDD_direction_E;
+
+typedef enum _TDD_tfci_len_E
+{
+ TDD_TFCI_0_BITS=0,
+ TDD_TFCI_4_BITS=4,
+ TDD_TFCI_8_BITS=8,
+ TDD_TFCI_16_BITS=16,
+ TDD_TFCI_32_BITS=32
+} TDD_tfci_len_E;
+
+typedef enum _TDD_midamble_alloction_mode_E
+{
+ TDD_MIDAMBLE_ALLOC_DMA=0,
+ TDD_MIDAMBLE_ALLOC_CMA=1,
+ TDD_MIDAMBLE_ALLOC_SPECIFIC=2
+} TDD_midamble_alloction_mode_E;
+
+typedef enum _TDD_ss_tpc_len_E
+{
+ TDD_SS_TPC_0_SYMBOLS = 0,
+ TDD_SS_TPC_1_SYMBOLS,
+ TDD_SS_TPC_16_DIVIDE_SF_SYMBOLS
+} TDD_ss_tpc_len_E;
+
+typedef enum _TDD_max_retrans_E
+{
+ TDD_MAX_RETRANS_1 = 1, /*max retranmit 1 time*/
+ TDD_MAX_RETRANS_2 = 2, /*max retranmit 2 times*/
+ TDD_MAX_RETRANS_4 = 4, /*max retranmit 4 times*/
+ TDD_MAX_RETRANS_8 = 8 /*max retranmit 8 times*/
+} TDD_max_retrans_E;
+
+typedef enum _TDD_tdd128_modulation_E
+{
+ TDD_TDD128_MODULATION_QPSK = 0, /*QPSK*/
+ TDD_TDD128_MODULATION_8PSK, /*8PSK*/
+ TDD_TDD128_MODULATION_16QAM /*16QAM*/
+} TDD_tdd128_modulation_E;
+
+typedef enum _TDD_midamble_config_E
+{
+ TDD_MIDAMBLE_CONFIG_2 = 2,
+ TDD_MIDAMBLE_CONFIG_4 = 4,
+ TDD_MIDAMBLE_CONFIG_6 = 6,
+ TDD_MIDAMBLE_CONFIG_8 = 8,
+ TDD_MIDAMBLE_CONFIG_10 = 10,
+ TDD_MIDAMBLE_CONFIG_12 = 12,
+ TDD_MIDAMBLE_CONFIG_14 = 14,
+ TDD_MIDAMBLE_CONFIG_16 = 16
+} TDD_midamble_config_E;
+
+typedef enum _TDD_second_interleave_mode_E
+{
+ TDD_SECOND_INTERLEAVE_FRAME = 0, /*frame interleval*/
+ TDD_SECOND_INTERLEAVE_TIMESLOT /*timeslot interleval*/
+} TDD_second_interleave_mode_E;
+
+typedef enum _TDD_fpach_wt_E
+{
+ TDD_FPACH_WT_1 = 1,
+ TDD_FPACH_WT_2 = 2,
+ TDD_FPACH_WT_3 = 3,
+ TDD_FPACH_WT_4 = 4
+} TDD_fpach_wt_E;
+
+typedef enum _TDD_repeat_period_E
+{
+ TDD_REPEAT_PERIOD_1 = 1,
+ TDD_REPEAT_PERIOD_2 = 2,
+ TDD_REPEAT_PERIOD_4 = 4,
+ TDD_REPEAT_PERIOD_8 = 8,
+ TDD_REPEAT_PERIOD_16 = 16,
+ TDD_REPEAT_PERIOD_32 = 32,
+ TDD_REPEAT_PERIOD_64 = 64
+} TDD_repeat_period_E;
+
+
+typedef enum _TDD_sib_rep_E
+{
+ TDD_SIB_REP_2 = 2,
+ TDD_SIB_REP_4 = 4,
+ TDD_SIB_REP_8 = 8,
+ TDD_SIB_REP_16 = 16,
+ TDD_SIB_REP_32 = 32,
+ TDD_SIB_REP_64 = 64,
+ TDD_SIB_REP_128 = 128,
+ TDD_SIB_REP_256 = 256,
+ TDD_SIB_REP_512 = 512,
+ TDD_SIB_REP_1024 = 1024,
+ TDD_SIB_REP_2048 = 2048,
+ TDD_SIB_REP_4096 = 4096
+} TDD_sib_rep_E;
+
+
+typedef struct _TDD_ul_pc_info_T
+{
+ kal_int8 prx_dpch_des; /*-120 - -58 by step 1 in dBm,UL DPCH expected receive power at NodeB */
+ kal_uint8 tpc_step; /*1 - 3, in dB,Tx power control step size*/
+ kal_uint8 pccpch_tx_power; /*6 - 43 by step 1 in dBm,P-CCPCH transmit power*/
+ kal_bool beacon_pl_est; /*TRUE: UE may take into account pathloss estimated from beacon function physical channels.
+ FALSE: UE shall not take into account pathloss estimation.*/
+} TDD_ul_pc_info_T;
+
+typedef struct _TDD_midamble_info_T
+{
+ TDD_midamble_alloction_mode_E midamble_allocation_mode; /*Midamble code allocation mode:DEFAULT,COMMON,UE_SPECIFIC.*/
+ TDD_midamble_config_E midamble_config; /*2, 4, 6, 8, 10, 12, 14, 16,Midamble code configuration,*/
+ kal_int8 midamble_shift; /*-1 - 15, -1 means invalid midamble shift. Midamble code shift*/
+} TDD_midamble_info_T;
+
+typedef struct _TDD_phy_signaling_info_T
+{
+ TDD_tfci_len_E tfci_bits; /*tfci bits length*/
+ TDD_ss_tpc_len_E ss_tpc_symbols; /*Amount of SS and TPC bits sent in this timeslot*/
+ kal_uint8 additional_ss_tpc_symbols; /* 0 -15 , 0 for no additional SS and TPC symbols,The number of additional codes in this timeslot that carry TPC and SS symbols*/
+} TDD_phy_signaling_info_T;
+
+typedef struct _TDD_timeslot_info_T
+{
+ kal_uint8 timeslot; /*0 - 6,Timeslot number, */
+ kal_uint8 num_ccode; /*1 - 16,The number of ccode in this timeslot.*/
+ kal_uint32 ccode_bitmap; /*bit0 is C16-1
+ ` bit1 is C16-2
+ ...
+ bit 15 is C16-16
+ bit16 is C8-1
+ ..
+ bit23 is C8-8
+ bit24 is C4-1
+ bit27 is C4-4
+ bit28 is C2-1
+ bit29 is C2-2
+ bit30 is C1-1
+ bit31 is reserved.*/
+ TDD_tdd128_modulation_E modulation; /*modulation type*/
+ TDD_midamble_info_T midamble; /*Midamble information*/
+ TDD_phy_signaling_info_T phy_signaling; /*Physical signaling information.*/
+} TDD_timeslot_info_T;
+
+typedef struct _TDD_fpach_info_T
+{
+ TDD_timeslot_info_T timeslot; /*0 - 6,Timeslot number, */
+ TDD_fpach_wt_E wait_time; /*1~4,The number of sub-frames, where UE should monitor FPACH after sending SYNC UL.*/
+} TDD_fpach_info_T;
+
+typedef struct _TDD_timeslot_common_T
+{
+ TDD_second_interleave_mode_E second_interleave;/*Mode of 2nd interleaving, Enums:FRAME_BASED,TIMESLOT_BASED*/
+ kal_uint8 punc_limit; /*40~100. This parameter is the puncturing limit. The value is from 40 to 100. The real puncturing limit is the value of this parameter divided by 100. */
+ TDD_repeat_period_E repeat_period; /*1, 2, 4, 8, 16, 32, 64, in frames. 1 means continuous allocation.Physical channel resource allocation period*/
+ kal_uint8 repeat_length; /*[1, (RepeatPeriod - 1)] in frames.Physical channel resource allocation length*/
+ kal_uint8 repeat_offset; /*[0, (RepeatPeriod - 1)],]: Physical channel resource allocation starting point, offset to RepeatPeriod.*/
+} TDD_timeslot_common_T;
+
+
+typedef struct _TDD_ul_dpch_info_T
+{
+ kal_uint8 ul_dpch_num; /*num of ul dpch, only can be 0 or 1;*/
+ kal_int16 duration; /*0-4096, 0 for infinity.Total number of frames the physical resource will exist*/
+ TDD_ul_pc_info_T ul_pc; /*UL power control info*/
+ kal_uint8 sync_step; /*1 - 8, in 1/8 chip,Uplink synchronization step size.*/
+ kal_uint8 sync_freq; /*1 - 8, in sub-frame,Uplink synchronization frequencies, */
+ TDD_timeslot_common_T common; /*time slot common info*/
+ kal_uint8 num_timeslot; /*number of UL timeslots*/
+ TDD_timeslot_info_T timeslot_list[TDD_MAX_TIMESLOT_PER_SUBFRAME];/*info of each timeslot*/
+} TDD_ul_dpch_info_T;
+
+typedef struct _TDD_dl_dpch_rla_T
+{
+ kal_uint8 tpc_step; /*1 - 3, in dB,Tx power control step size*/
+ kal_int32 doff; /*-1 ~7, -1 means invalid,Default DPCH offset value*/
+} TDD_dl_dpch_rla_T;
+
+
+typedef struct _TDD_dl_dpch_rl_T
+{
+ kal_uint16 cell_param_id; /*0-127,Cell parameter ID*/
+ kal_int32 tm; /*(-1~6400*8-1). 0~(6400*8-1) for a cell whose frame boundary offset has been measured by TL1.
+ Otherwise, it can be set to ¡°-1¡± as an unknown tm value.
+ Case TRHHO/DCH_Setup/BHO/TMHHO: PS needs to guarantee that tm and off is valid.
+ Case TRHHO_Revert/TMHHO_Revert/IRAT_Revert/BHO_Revert*/
+ kal_int16 off; /*Sub frame # offset to LST. -1 ~ 8191, -1 means unknown*/
+ kal_bool tstd; /*True/False. True: tstd is applied on this cell¡¯s P-CCPCH.*/
+ kal_int16 duration; /*0-4096, 0 for infinity,Total number of frames the physical resource will exist.*/
+ TDD_timeslot_common_T common; /*common info of timeslots*/
+ kal_uint8 num_timeslot; /*num of DL timeslot*/
+ TDD_timeslot_info_T timeslot_list[TDD_MAX_TIMESLOT_PER_SUBFRAME];/*timeslot info*/
+} TDD_dl_dpch_rl_T;
+
+typedef struct _TDD_sccpch_info_T
+{
+ TDD_timeslot_common_T common; /*common timeslot characters on cctrch level*/
+ TDD_timeslot_info_T timeslot; /*info about this timeslot*/
+} TDD_sccpch_info_T;
+
+
+typedef enum _TDD_pi_len_E
+{
+ TDD_PI_LEN_4_BITS=4,
+ TDD_PI_LEN_8_BITS=8,
+ TDD_PI_LEN_16_BITS=16
+} TDD_pi_len_E;
+
+typedef struct _TDD_pich_drx_T
+{
+ kal_uint8 pich_drx; /*[Range]: 3-9
+ [Meaning]: Max(k, k'), k' is derived from PBP with PBP=2^ k',
+ so the drx cycle length can be calculated via 2^pich_drx.*/
+ kal_uint16 sfn_po; /*PICH starting point, offset to RepeatPeriod, in frames.
+ sfn_po = {(IMSI div K) mod (DRX cycle length div PBP)} * PBP + frame_offset;
+ Indicate the start of the PICH frame in one DRX cycle.*/
+ kal_uint16 pi; /*The target PI¡¯s position in the paging indicator block.
+ pi = (IMSI / 8192) mod NP; where NP = NPICH * (352*16/ 8 /2/pi_len).
+ Indicate the UE¡¯s PI position in the paging indicator block*/
+ TDD_pi_len_E pi_len; /*paging indicator length in bits*/
+ kal_uint16 sfn_ro; /*PCH starting point, offset to the PagingOccasion, in frames.
+ sfn_ro = NPICH + NGAP + {(pi mod Npch } *2*/
+} TDD_pich_drx_T;
+
+typedef enum _TDD_pich_reconfig_type_E
+
+{
+
+ TDD_PCH_MODIFY, /* traditionaly PCH modify */
+
+ TDD_PCH_SMARTPAGE, /* to inform UL1 enable/disable SmartPaging*/
+
+} TDD_pich_reconfig_type_E;
+
+typedef struct _TDD_pich_smartpaging_T
+
+{
+
+ kal_bool support_repeat; /* If true: RRCE has detected that current NW can support smart paging (has repeated paging pattern) */
+
+ kal_uint16 sfn_po; /* DRX parameters for PICH.(when smartpging active) */
+
+ kal_uint16 sfn_ro; /* DRX parameters for PCH.(when smartpging active) */
+
+} TDD_pich_smartpaging_T;
+
+
+typedef struct _TDD_pich_info_T
+{
+
+ kal_uint8 pccpch_tx_power; /*[Range]: 6 ¨C 43 by step 1 in dBm
+ [Meaning]: P-CCPCH transmit power.*/
+ kal_int8 power_offset; /*[Range]: -10 ~ +5 in dB
+ [Meaning]: The power offset of PICH to P-CCPCH Tx Power.
+ TL1 can derive the PICH Tx power using power_offset and pccpch_tx_power. */
+ kal_uint8 timeslot; /*[Range]: 0-6
+ [Meaning]: The timeslot carring PICH info*/
+ kal_uint32 ccode_bitmap; /*Bit map of used channelisation code
+ bit0 is C16-1
+ bit1 is C16-2
+ ¡.
+ bit 15 is C16-16
+ bit16 is C8-1
+ ..
+ bit23 is C8-8
+ bit24 is C4-1
+ bit27 is C4-4
+ bit28 is C2-1
+ bit29 is C2-2
+ bit30 is C1-1
+ bit31 is reserved.
+ For PICH, only 2 SF=16 codes are used.*/
+ TDD_midamble_info_T midamble; /*midamble info for PICH*/
+ TDD_pich_drx_T pich_drx;
+ TDD_pich_smartpaging_T smartpaging_info;
+
+ TDD_pich_drx_T pich_drx_cycle2; /* DRX parameters 2 for PICH. Valid for CELL_PCH and URA_PCH, not valid for IDLE-PCH */
+ kal_uint16 drx_cycle2_time; /* if it's not 0. TL1 shall use pich_drx_2 for PICH receptin, else shall directly use pich_drx for PICH reception.
+ Valid value: 0, 80,160,320,640,1280,2560,5120 (Uint: ms) */
+
+} TDD_pich_info_T;
+
+
+typedef struct _TDD_tx_power_info_T
+{
+ kal_int16 tx_power[TDD_MAX_TIMESLOT_PER_SUBFRAME]; /*Tx power of each ul timeslot. The tx power is measured in both FACH and
+ DCH state, "TDD_TX_POWER_INVALID" is used to for non tx slots.
+ Range: -200- 136 means (-50dBm ~ 34dBm ) in 0.25dBm step*/
+} TDD_tx_power_info_T;
+
+
+typedef struct _TDD_tadv_info_T
+{
+ kal_int16 tadv; /*[Range]: Range: -1 -8191. 0-8191 means (0 ~ 1023.875 ) chips in 1/8 chip
+ step, -1 means unknown tadv [Meaning]:timing advance*/
+ kal_uint16 sfn; /*SFN during which the TADV measurement was performed*/
+} TDD_tadv_info_T;
+
+typedef enum _TDD_internal_meas_E
+{
+ TDD_MEAS_TX_PWR = 1, /*measure UE transmitted power*/
+ TDD_MEAS_RSSI, /*UTRA carrier RSSI*/
+ TDD_MEAS_TA /*Timing Advance*/
+} TDD_internal_meas_E;
+
+typedef enum _TDD_internal_meas_event_E
+{
+ TDD_EVENT_6A = 1, /*Measurement event 6A.*/
+ TDD_EVENT_6B, /*Measurement event 6B.*/
+ TDD_EVENT_6C, /*Measurement event 6C.*/
+ TDD_EVENT_6D, /*Measurement event 6D.*/
+ TDD_EVENT_6E, /*Measurement event 6E.*/
+ TDD_EVENT_6F /*Measurement event 6F.*/
+} TDD_internal_meas_event_E;
+
+typedef struct _TDD_meas_event_T
+{
+ TDD_internal_meas_event_E event_id; /*indicate internal measurement event ID.*/
+ kal_int16 threshold; /*used for event6a,6b,6f. For event6f, the range is 0~512, which means 0~63chip in 0.125 chip step. Since UTRAN will configure
+ the value in the range(768~1280) to UE, MEME will convert the value to range (0~512) by decreasing 768*/
+ kal_uint16 delay; /*Time to Triggered. [Range]: 0 ~ 500 frames When an event is triggered, the
+ report will be delayed until the time period indicated by this field has elapsed.*/
+} TDD_meas_event_T;
+
+typedef struct _TDD_measured_cell_T
+{
+ kal_bool sctd; /*True/False. True: sctd is applied on this cell's P-CCPCH.
+ False: sctd is not applied on this cell's P-CCPCH.*/
+ kal_int16 rscp; /*RSCP. Range: -500~ -100 means (-125~ -25 )dBm in 0.25 dB step*/
+ kal_uint16 cell_param_id; /*TS25.123:10.3.6.9*/
+ kal_uint16 freq; /*Cell's UARFCN*/
+ kal_int16 off; /*[Range]: (-1~8191). (0~8191) for a cell whose subframe SFN offset
+ to LST has been measured by TL1. "-1" for an unknown off value.
+ [Meaning]: sub frame number offset between target cell and LST.*/
+ kal_int32 tm; /*[Range]: (-1~6400*8-1). (0~6400*8-1) for a cell whose sub-frame
+ boundary offset has been measured by TL1. "-1" for an unknown tm value.
+ [Meaning]: sub frame boundary offset between target cell and LST.*/
+ kal_uint8 iscp_timeslot_bitmap; /*[Meaning]: the bitmap indicate which slots' iscp have been measured.
+ Bit x represents timeslot x. 0<= x <=6*/
+ kal_int16 iscp[TDD_MAX_TIMESLOT_PER_SUBFRAME]; /*ISCP range. -480 ~ -100 means (-120 ~ -25 )dBm in 0.25 dB step*/
+} TDD_measured_cell_T;
+
+//#ifdef __UMTS_R9__
+typedef enum _TDD_higher_prio_search_support_E
+{
+ TDD_REGULAR_MEAS_ONLY = 0, /*The cell should be measured according to regular period.*/
+ TDD_HIGHER_PRIORITY_ONLY, /*The cell should be measured according to higher priority search period.*/
+ TDD_HIGHER_PRIORITY_AND_REGULAR_MEAS /*The cell should be measured according to both higher priority search period and regular period.*/
+} TDD_higher_prio_search_support_E;
+//#endif
+typedef struct _TDD_cell_info_list_T
+{
+ kal_uint16 freq_uarfcn; /*Cell's frequency uarfcn.*/
+ kal_uint16 cell_param_id; /*[Range]: 0-127, 0xFF,
+ [Meaning]:Cell parameter ID,0xFF means unknown cell parameters id.*/
+//#ifdef __UMTS_R9__
+ TDD_higher_prio_search_support_E prio_search_control; /*Indicate measurement type*/
+//#endif
+ kal_bool sctd; /*True/False. True: sctd is applied on this cell's P-CCPCH.
+ False: sctd is not applied on this cell's P-CCPCH.*/
+ kal_bool tstd; /*True/False. True: tstd is applied on this cell's P-CCPCH.
+ False: tstd is not applied on this cell's P-CCPCH.*/
+ kal_int16 ref_timing; /*[Range ]: -1 ~ 12800-1, -1 means unknown timing
+ [Meaning]: Cell boundary*/
+ kal_bool ref_timing_sib; /*Indicate if the reference timing comes from SIB11 or Meas. Control.
+ True: this timing info is from SIB*/
+ kal_int32 tm; /*[Range ]: -1 ~ 6400*8-1 , -1 means unknown timing
+ [Meaning]: Sub Frame boundary offset between target cell and LST*/
+ kal_int16 off; /*[Range]: -1 ~ 8191, -1 means unknown timing
+ [Meaning]: Subframe SFN offset between target cell and LST.*/
+ kal_uint8 iscp_timeslot_bitmap; /*[Meaning]: Bitmap of timeslot for iscp measurement, valid only for DL slots.£I
+ if bit x is 1, iscp measurement should be carried on slot x. 0<=x <= 6*/
+#ifdef __HSUPA_SUPPORT__
+ kal_bool intra_sec_freq_indicator; /*True/False. True: this cell has configured a secondary frequency on the same frequency as UE working carrier.
+ False: this cell hasn't configured an intra-secondary frequency.*/
+ kal_uint8 pccpch_tx_power; /*[Range]: 6 ~ 43 by step 1 in dBm
+ [Meaning]:P-CCPCH transmit power*/
+#endif
+}TDD_cell_info_list_T;
+
+typedef enum _TDD_meas_act_E
+{
+ TDD_STOP_MEAS = 0, /*stop measurement.*/
+ TDD_START_MEAS_NEW_CIL = 3, /*start measurement if measurement is stopped and update CIL*/
+ TDD_START_MEAS_NEW_CIL_NEW_FMO = 7 /*start measurement if measurement is stopped and
+ update both CIL and FMO.*/
+ ,TDD_START_MEAS_NEW_PRIO_INFO = 9
+
+} TDD_meas_act_E;
+
+
+typedef struct _TDD_preferred_cell_list_T
+{
+ kal_uint8 uarfcn_index;
+ kal_uint16 cell_param_id;
+} TDD_preferred_cell_list_T;
+
+
+typedef struct _TDD_fach_pch_info_T
+{
+ kal_uint16 cell_param_id; /*cell parameter ID, range:0-127*/
+ kal_bool sctd; /*TRUE:sctd is applied on this cell's P-CCPCH,
+ FALSE:sctd is not applied on this cell's P-CCPCH*/
+ kal_bool tstd; /*TRUE:tstd is applied on this cell's P-CCPCH,
+ FALSE:tstd is not applied on this cell's P-CCPCH*/
+ kal_int16 rscp; /*serving cell rscp, range:-500 - -100 means (-125 - -25)dBm
+ in 0.25dB step*/
+ TDD_sccpch_info_T sccpch_info; /*physical channel info for PCH/FACH to be carried over*/
+ kal_uint16 tfc_num; /*number of tfc in attached tfcs[]*/
+ TDD_dl_tfc_T tfcs[TDD_MAX_DL_TFC]; /*tfcs info for this sccpch*/
+ kal_uint8 active_dl_trch_list; /*To represent active TRCHs by bit string. The MSB represents the
+ lowest numbered trch index, and so on in descending bit significance
+ and increasing numerical order.'1' represents for active channel,'0' for inactive
+ channel which decoding is not required.For CPHY_PCH_SETUP_REQ, the
+ number of bits which are set to ¡®1¡¯ should be equal to 1.
+ Namely, only 1 trch is activated. For CPHY_FACH_SETUP_REQ, indicate all
+ the trch multiplexed on this S-CCPCH.*/
+ kal_uint8 trch_num; /*number of trch in trch_list[TDD_MAXFACHPCH]*/
+ TDD_dl_fachpch_trch_T trch_list[TDD_MAXFACHPCH];
+ TDD_pich_info_T pich_info; /*pich info*/
+} TDD_fach_pch_info_T;
+
+typedef enum _TDD_num_uppch_subchannel_size_E
+{
+ TDD_NUM_UPPCH_SUBCH_1 = 1,
+ TDD_NUM_UPPCH_SUBCH_2 = 2,
+ TDD_NUM_UPPCH_SUBCH_4 = 4,
+ TDD_NUM_UPPCH_SUBCH_8 = 8
+} TDD_num_uppch_subchannel_size_E;
+
+typedef struct _TDD_asc_info_T
+{
+ kal_uint8 sync_ul_bitmap; /*available sync_ul for this asc*/
+ TDD_num_uppch_subchannel_size_E num_subchannel_size; /*[Range]: 1,2,4,8
+ [Meaning]:Number of uppch subchannel in cell */
+ kal_uint16 subchannel_bitmap; /*Bit map of uppch subchannel
+ bit0 indicate the first subchannel
+ bit1 indicate the second subchannel
+ bit (num_subchannel -1) indicates num_subchannelth subchannel.
+ At most 8 uppch sub channels defined <3GPP-TS25.331-v7.10.0:10.3.6.6>.
+ The low 8 bit will be used.*/
+} TDD_asc_info_T;
+
+typedef enum _TDD_ccode_lcr_E
+{
+ TDD_cc1_1 = 0, /*The index of 1st channelization code of SF=1*/
+ TDD_cc2_1, /*The index of 1st channelization code of SF=2*/
+ TDD_cc2_2, /*The index of 2nd channelization code of SF=2*/
+ TDD_cc4_1, /*The index of 1st channelization code of SF=4*/
+ TDD_cc4_2, /*The index of 2nd channelization code of SF=4*/
+ TDD_cc4_3, /*The index of 3rd channelization code of SF=4*/
+ TDD_cc4_4, /*The index of 4th channelization code of SF=4*/
+ TDD_cc8_1, /*The index of 1st channelization code of SF=8*/
+ TDD_cc8_2, /*The index of 2nd channelization code of SF=8*/
+ TDD_cc8_3, /*The index of 3rd channelization code of SF=8*/
+ TDD_cc8_4, /*The index of 4th channelization code of SF=8*/
+ TDD_cc8_5, /*The index of 5th channelization code of SF=8*/
+ TDD_cc8_6, /*The index of 6th channelization code of SF=8*/
+ TDD_cc8_7, /*The index of 7th channelization code of SF=8*/
+ TDD_cc8_8, /*The index of 8th channelization code of SF=8*/
+ TDD_cc16_1, /*The index of 1st channelization code of SF=16*/
+ TDD_cc16_2, /*The index of 2nd channelization code of SF=16*/
+ TDD_cc16_3, /*The index of 3rd channelization code of SF=16*/
+ TDD_cc16_4, /*The index of 4th channelization code of SF=16*/
+ TDD_cc16_5, /*The index of 5th channelization code of SF=16*/
+ TDD_cc16_6, /*The index of 6th channelization code of SF=16*/
+ TDD_cc16_7, /*The index of 7th channelization code of SF=16*/
+ TDD_cc16_8, /*The index of 8th channelization code of SF=16*/
+ TDD_cc16_9, /*The index of 9th channelization code of SF=16*/
+ TDD_cc16_10, /*The index of 10th channelization code of SF=16*/
+ TDD_cc16_11, /*The index of 11th channelization code of SF=16*/
+ TDD_cc16_12, /*The index of 12th channelization code of SF=16*/
+ TDD_cc16_13, /*The index of 13th channelization code of SF=16*/
+ TDD_cc16_14, /*The index of 14th channelization code of SF=16*/
+ TDD_cc16_15, /*The index of 15th channelization code of SF=16*/
+ TDD_cc16_16 /*The index of 16th channelization code of SF=16*/
+}TDD_ccode_lcr_E;
+
+
+/*prach resource info*/
+typedef struct _TDD_prach_resource_info_T
+{
+ kal_uint8 timeslot; /*prach timeslot number*/
+ TDD_midamble_info_T midamble; /*Midamble information*/
+ kal_uint8 code_num; /*number of prach code*/
+ TDD_ccode_lcr_E prach_code_list[4] ; /*prach channel code list*/
+
+}TDD_prach_resource_info_T ;
+
+typedef enum _TDD_dch_setup_msg_type_E
+{
+ TDD_DCH_SETUP = 0, /* The setup request is used when dch is established in the first time. */
+ TDD_DCH_TRHHO, /* The setup request is to perform timing-reinitialized hard handover.*/
+ TDD_DCH_TRHHO_REVERT, /* The setup request is to perform timing-reinitialized hard handover revert.*/
+ TDD_DCH_TMHHO, /* The modify request is to perform timing-maintained hard handover. */
+ TDD_DCH_TMHHO_REVERT, /* The modify request is to perform timing-maintained hard handover revert. */
+ TDD_DCH_IRAT_REVERT, /* The setup request is to perform inter-RAT hand over revert.*/
+ TDD_DCH_TRBHO, /*timing-reinitialized baton handover*/
+ TDD_DCH_TRBHO_REVERT, /*The setup request is to perform timing-reinitialized baton handover revert*/
+ TDD_DCH_TMBHO, /*timing- maintained baton handover*/
+ TDD_DCH_TMBHO_REVERT /*The setup request is to perform timing- maintained baton handover revert. */
+} TDD_dch_setup_msg_type_E;
+
+typedef struct _TDD_hssich_info_T
+{
+ kal_uint8 ts_num; /*[rang]: 0 ~ 6 [meaning]:The number of time slot in which
+ HS-SICH is allocated.*/
+ TDD_ccode_lcr_E ccode; /*[range]:15~30, the channelization code of HS-SICH*/
+ TDD_midamble_info_T midamble_info; /*Midamble info for HS-SICH*/
+
+ kal_int8 ack_nack_power_offset; /*[Range]: -7~8 [Meaning]:the power offset of HS-SICH when sending ACK. */
+ kal_int8 power_level; /*[Range]: -120~ -58 [Meaning]:Desired HS-SICH RX power at the cell's receiver in dBm*/
+ kal_uint8 tpc_step; /*[Rang]: 1,2,3. The transmission power control step size.*/
+} TDD_hssich_info_T;
+
+typedef struct _TDD_hsscch_config_T
+{
+ kal_uint8 ts_num; /*The number of time slot in which HS-SCCH is allocated.*/
+ TDD_ccode_lcr_E first_ccode; /*The first channelization code of HS-SCCH*/
+ TDD_ccode_lcr_E second_ccode; /*The second channelization code of HS-SCCH*/
+ TDD_midamble_info_T midamble_info; /*Midamble info for HS-SCCH*/
+ TDD_hssich_info_T hssich_info; /*The information of HS_SICH*/
+} TDD_hsscch_config_T;
+
+typedef struct _TDD_hsscch_info_T
+{
+ kal_uint8 num_hsscch; /*The number of hs-scch*/
+ TDD_hsscch_config_T hsscch_config[TDD_MAX_HSSCCH_NUM]; /*Physical channel config of HS-SCCH & HS-SICH.*/
+ kal_int8 hsscch_bler_target; /*[Range]: -63 ~ 0, -64. [Meaning]: multiply the value of this IE with 0.05 to get the real value.
+ (Real BLER: -3.15~0 = log10 (BLER)). -64 is used for invalid value.*/
+ kal_uint8 hssich_power_ctrl_gap; /*[Range]: 1 ~ 255. [default]: 1 [Meaning]: number of subframes as the threshold of
+ hssich gap power control.*/
+ kal_bool path_loss_compensation; /*TRUE: UE shall perform the pathloss compensation for HS-SICH power control
+ when HS-SICH transmission gap is less than "Power Control GAP".
+ FALSE: UE shall not consider the pathloss compensation for HS-SICH power control.
+ Default: FALSE.*/
+
+ kal_uint8 hs_scch_tpc_size; /* [Rang]: 1,2,3 the transmission power control step size.*/
+
+} TDD_hsscch_info_T;
+
+typedef struct _TDD_hs_harq_info_T
+{
+ kal_uint8 process_num; /*[Rang]: 1 ~ 8. The number of HARQ process.*/
+ kal_bool explicit_partition; /*TRUE indicates explicit memory partition. FALSE indicates implicit memory partition*/
+ kal_uint8 process_mem_size[TDD_MAX_HARQ_PROCESS_NUM]; /*[Range] 0~60. Index of HARQ memory size. range: 0~60. Only valid when memory partition is explicit*/
+} TDD_hs_harq_info_T;
+
+typedef struct _TDD_hs_queue_config_T
+{
+ kal_uint8 queue_id; /*Queue identifier of this MAC-hs PDU*/
+ kal_uint8 bit_offset; /*Heading bit offset for each TB: 0 or 4 bits*/
+ kal_uint8 num_size; /*Number of valid size[] and size_index[]*/
+ kal_uint16 size[TDD_MAX_HSDSCH_SIZE]; /*Configured size list*/
+ kal_uint8 size_index[TDD_MAX_HSDSCH_SIZE]; /*Configured size index list*/
+
+} TDD_hs_queue_config_T;
+
+typedef struct _TDD_hs_queue_info_T
+{
+ kal_uint8 num_queue; /*Number of configured MAC-hs queues*/
+ TDD_hs_queue_config_T queue_config[TDD_MAX_HSDSCH_QUEUE]; /*MAC-hs Queue Information*/
+} TDD_hs_queue_info_T;
+
+typedef struct _TDD_hsdsch_size_info_T
+{
+ kal_uint16 tb_size; /*Size of each TB in bits*/
+ kal_uint8 num_tb; /*Number of TB with the same size*/
+} TDD_hsdsch_size_info_T;
+
+
+typedef enum
+{
+ TDD_DSCH_NO_HRNTI_DETECTED = 0, /*HS-SCCH CRC check is failed*/
+ TDD_DSCH_D_HRNTI_DETECTED = 1, /*HS-PDSCH is indicated by HS-SCCH with dH-RNTI*/
+ TDD_DSCH_C_HRNTI_DETECTED = 2, /*HS-PDSCH is indicated by HS-SCCH with cH-RNTI*/
+ TDD_DSCH_B_HRNTI_DETECTED = 3, /*HS-PDSCH is indicated by HS-SCCH with bH-RNTI*/
+ TDD_DSCH_HRNTI_LESS = 4, /*HS-PDSCH is decoded blindly without HS-SCCH */
+ //DSCH_NOT_RECEIVE = 5, /*This subframe is not received by HW */
+
+} TDD_hs_dsch_decode_hrnti_E;
+
+typedef struct _TDD_hsdsch_data_T
+{
+ kal_bool is_valid_data; /*Indicate MAC-hs PDU is valid (CRC right) or not.*/
+ kal_uint8 queue_id; /*Queue identifier of this MAC-hs PDU*/
+ kal_uint8 tsn; /*TSN of this MAC-hs PDU*/
+ kal_uint8 num_size_info; /*Number of valid size_info*/
+ TDD_hsdsch_size_info_T size_info[TDD_MAX_HSDSCH_SIZE]; /*Decoded combination of SID and N*/
+ kal_uint16 num_data; /*The size in byte of the buffer containing the data. It is the exact
+ size of data, including the byte for TB number.*/
+
+ kal_uint16 EMI_buffer_index;
+
+ kal_uint8* data; /*The buffer contains data for each TB received in this MAC-hs PDU. This buffer
+ is allocated by TL1, and freed by PS. The buffer is from ADM. The first byte in the
+ data indicates the number of TB in this data indication.*/
+
+ TDD_hs_dsch_decode_hrnti_E decode_hrnti; /*[R8] H-RNTI dectected info*/
+ kal_bool ndi; /*true:new decoded data; false:old decoded data.*/
+ kal_uint16 tb_size; /*Indicated the size of each TB*/
+
+ kal_int8 pi_repeat_cycle; /* -1:invalid, -2:retransmission with CRC pass, 1~20:valid pi_repeat_cyle */
+} TDD_hsdsch_data_T;
+
+/*ul_sync/rach/erucch struct*/
+typedef struct _TDD_random_access_info_T
+{
+ kal_uint16 uarfcn; /*For cphy_dch_setup_req, this is fpach uarfcn for HHO, others, this field is working uarfcn.E */
+ kal_uint8 pccpch_tx_power; /*[Range]: 6 ~ 43 by step 1 in dBm
+ [Meaning]:P-CCPCH transmit power*/
+ kal_int8 max_tx_power; /*Range]: -50 ~ 33 dBm
+ [Meaning]: Max. allowed TX power.*/
+ kal_int8 umts_power_class; /*UE capability(in dBm)
+ The value's unit configured by SLCE is dBm.
+ define MAX_OUTPUT_POWER_CLASS_1 33 :+33dBm
+ define MAX_OUTPUT_POWER_CLASS_2 24 : +24dBm
+ define MAX_OUTPUT_POWER_CLASS_3 21 : +21dBm
+ define MAX_OUTPUT_POWER_CLASS_4 27 : +27dBm */
+ kal_bool sync_param_ind; /*True: The following parameters exist,False: The following parameter does not exist.
+ For cphy_dch_setup_req only. In case of HHO, the related fileds must be valid.*/
+ kal_uint8 sync_ul_bitmap; /*sync ul code bitmap,For cphy_dch_setup_req only.*/
+ kal_uint8 num_asc; /*valid asc number in asc[], 1-8*/
+ TDD_asc_info_T asc[TDD_MAX_ASC];
+ kal_uint8 num_prach_fpach; /*[Range]: 1- TDD_MAX_PRACH_FPACH_NUM
+ [Meaning]: number of fpach-PRACH pair.*/
+ TDD_prach_resource_info_T prach_list[TDD_MAX_PRACH_FPACH_NUM];
+ TDD_fpach_info_T fpach_list[TDD_MAX_PRACH_FPACH_NUM]; /*fpach info for this UE*/
+ kal_int8 prx_uppch_des; /*[-120, -58] by step 1 in dBm.UpPCH expected receive power at NodeB, */
+ kal_uint8 power_ramp_step; /*0 - 3, in dB,power ramp step */
+ TDD_max_retrans_E max_retrans; /*1,2, 4, or 8,max retrans times in one power ramping procedure*/
+ kal_uint8 uppch_shift; /*0 - 127, Default: 0,UpPCH shifting position in a cell,
+ UpPCH position = UpPTS position + uppch_shift*16*/
+}TDD_random_access_info_T;
+
+#ifdef __HSUPA_SUPPORT__
+
+typedef enum _TDD_edch_t_wait_E
+{
+ TDD_EDCH_T_WAIT_TIMER_EVERY_TTI = 0,
+ TDD_EDCH_T_WAIT_TIMER_40MS,
+ TDD_EDCH_T_WAIT_TIMER_80MS,
+ TDD_EDCH_T_WAIT_TIMER_160MS,
+ TDD_EDCH_T_WAIT_TIMER_320MS,
+ TDD_EDCH_T_WAIT_TIMER_640MS,
+ TDD_EDCH_T_WAIT_TIMER_1000MS,
+ TDD_EDCH_T_WAIT_TIMER_2000MS
+} TDD_edch_t_wait_E;
+
+typedef enum _TDD_edch_t_rucch_E
+{
+ TDD_EDCH_T_RUCCH_TIMER_20MS = 0,
+ TDD_EDCH_T_RUCCH_TIMER_40MS,
+ TDD_EDCH_T_RUCCH_TIMER_60MS,
+ TDD_EDCH_T_RUCCH_TIMER_80MS,
+ TDD_EDCH_T_RUCCH_TIMER_120MS,
+ TDD_EDCH_T_RUCCH_TIMER_160MS,
+ TDD_EDCH_T_RUCCH_TIMER_200MS,
+ TDD_EDCH_T_RUCCH_TIMER_240MS,
+ TDD_EDCH_T_RUCCH_TIMER_280MS,
+ TDD_EDCH_T_RUCCH_TIMER_320MS,
+ TDD_EDCH_T_RUCCH_TIMER_400MS,
+ TDD_EDCH_T_RUCCH_TIMER_500MS,
+ TDD_EDCH_T_RUCCH_TIMER_600MS,
+ TDD_EDCH_T_RUCCH_TIMER_800MS,
+ TDD_EDCH_T_RUCCH_TIMER_1000MS,
+ TDD_EDCH_T_RUCCH_TIMER_2000MS
+} TDD_edch_t_rucch_E;
+
+/*E-AGCH Physical Channel Configuration, <3GPP-TS25.331:10.3.6.100>*/
+typedef struct _TDD_eagch_config_T
+{
+ kal_uint8 ts_num; /*[Range]: 0 ~ 6.The number of time slot in which E-AGCH is llocated.*/
+ TDD_ccode_lcr_E first_ccode; /*The first channelization code of E-AGCH.*/
+ TDD_ccode_lcr_E second_ccode; /*The second channelization code of E-AGCH.*/
+ TDD_midamble_info_T midamble_info; /*Midamble info for E-AGCH.*/
+} TDD_eagch_config_T;
+
+/*E-AGCH Informtion, <3GPP-TS25.331:10.3.6.100>*/
+typedef struct _TDD_eagch_info_T
+{
+ kal_bool rdi_indicator; /*TRUE: RDI is present in E-AGCH block.
+ FALSE: RDI is absent in E-AGCH block.*/
+ kal_uint8 tpc_step; /*[Range]: 1,2,3. The transmission power control step size.*/
+ kal_int8 bler_target; /*[Range]: -63 ~ 0, -64
+ [Meaning]: multiply the value of this IE with 0.05 to get the real value.
+ (Real BLER: -3.15~0 = log10 (BLER)). -64 is used for invalid value.*/
+ kal_uint8 num_eagch; /*[Range]: 1 ~ 4
+ [Meaning]: The number of configured E-AGCH.*/
+ TDD_eagch_config_T eagch_config[TDD_MAX_EAGCH_NUM];/*Physical channel config of E-AGCH.*/
+} TDD_eagch_info_T;
+
+/*E-HICH Physical Channel Configuration, <3GPP-TS25.331:10.3.6.100>*/
+typedef struct _TDD_ehich_config_T
+{
+ kal_uint8 ei; /*[range]: 0~3.
+ [meaning]: The E-HICH identifier to match the EI field in E-AGCH.
+ [notes]: 255 for non-scheduled E-HICH.*/
+ kal_uint8 ts_num; /*[range]: 0 ~ 6.
+ [meaning]:The number of time slot in which E-HICH is allocated.*/
+ TDD_ccode_lcr_E ccode; /*[range]:15~30.
+ [meaning]: the channelization code of E-HICH.*/
+ TDD_midamble_info_T midamble_info; /*Midamble info for E-HICH*/
+} TDD_ehich_config_T;
+
+/*E-HICH Informtion, <3GPP-TS25.331:10.3.6.101>*/
+typedef struct _TDD_ehich_info_T
+{
+ kal_uint8 n_e_hich; /*[range]: 4~15.
+ [meaning]: Minumum number of slots betwen start last active E-DCH TTI and start of ACK/NACK on E-HICH.*/
+ kal_uint8 num_ehich; /*[range]: 1~4
+ [meaning]: The number of configured E-HICH.*/
+ TDD_ehich_config_T ehich_config[TDD_MAX_EHICH_NUM];/*Physical channel config of E-HICH.*/
+} TDD_ehich_info_T;
+
+
+/*E-DCH Scheduled Informtion, <3GPP-TS25.331:10.3.6.100/101/103>*/
+typedef struct _TDD_edch_sched_info_T
+{
+
+ TDD_eagch_info_T eagch_info; /*E-AGCH Information*/
+ TDD_ehich_info_T ehich_info; /*E-HICH Information*/
+ TDD_random_access_info_T erucch_info; /*E-RUCCH Information*/
+ TDD_edch_t_wait_E t_wait; /*E-AGCH monitoring delay after last scheduled grant received*/
+ TDD_edch_t_rucch_E t_rucch; /*E-AGCH monitoring duration after successful E-RUCCH performed*/
+} TDD_edch_sched_info_T;
+
+/*E-DCH Non-Scheduled Granting Informtion, <3GPP-TS25.331:10.3.6.41c>*/
+typedef struct _TDD_edch_non_sched_grant_info_T
+{
+ kal_uint8 trri; /*Timeslot Resource Related Information, bitmap of assigned timeslots.
+ Bit0-TS5, Bit1-TS4, Bit2-TS3, Bit3-TS2,Bit4-TS1.*/
+ kal_uint8 prri; /*[range]: 1~32, i.e. -12dB~19dB, in step of 1dB.
+ [meaning]: Power Resource Related Information*/
+ TDD_ccode_lcr_E crri; /*Assigned channelisation code*/
+ kal_uint8 repeat_offset; /*[Meaning]: non-schedule E-PUCH resource allocation starting point in subframe.
+ [Range]: [0, (repeat_period - 1)]*/
+ TDD_repeat_period_E repeat_period; /*[range]: 1, 2, 4, 8, 16, 32, 64, in TTI. 1 means continuous allocation.
+ [meaning]: Physical channel resource allocation period.*/
+ kal_uint8 repeat_length; /*[range]: 1~(RepeatPeriod - 1), in TTI.
+ [meaning]: Physical channel resource allocation length.*/
+} TDD_edch_non_sched_grant_info_T;
+
+/*E-DCH Non-Scheduled Transmission Informtion, <3GPP-TS25.331:10.3.6.41c>*/
+typedef struct _TDD_edch_non_sched_info_T
+{
+ kal_uint8 n_e_ucch; /*[range]: 1~8.
+ [meaning]: Number of E-UCCH and TPC instances within an non-scheduled E-DCH TTI.*/
+ kal_uint8 n_e_hich; /*[range]: 4~15.
+ [meaning]: Minumum number of slots betwen start last active E-DCH TTI and start of ACN/NACK on E-HICH.*/
+ kal_uint8 ehich_sigature_group_index; /*[range]: 0~19.
+ [meaning]: which signature sequence group index to use.*/
+ TDD_ehich_config_T ehich_config; /*E-HICH Physical Channel Information*/
+ TDD_edch_non_sched_grant_info_T edch_non_sched_grant; /*Non-Scheduled transmission grant information.*/
+} TDD_edch_non_sched_info_T;
+
+/*E-DCH E-TFCS Definitions, <3GPP-TS25.331:10.3.6.105>*/
+typedef struct _TDD_edch_etfcs_T
+{
+ kal_uint8 num_ref_qpsk; /*[Range]: 2 ~ 8
+ Number of reference beta information for QPSK.
+ [notes]: as CCSA-2009-060Q, 2~8 is correct.*/
+ kal_uint8 ref_code_rate_qpsk[TDD_MAX_REF_BETA_NUM]; /*[Range]: 0 ~ 10, which means 0 ~ 1 in step of 0.1
+ List of configured reference code rate for QPSK.*/
+ kal_int8 ref_beta_qpsk[TDD_MAX_REF_BETA_NUM]; /*[Range]: -15 ~ 16, whose unit is dB.
+ List of configured reference beta for QPSK.*/
+ kal_uint8 num_ref_16qam; /*[Range]: 2 ~ 8
+ Number of reference beta information for 16QAM.
+ [notes]: as CCSA-2009-060Q, 2~8 is correct.*/
+ kal_uint8 ref_code_rate_16qam[TDD_MAX_REF_BETA_NUM]; /*[Range]: 0 ~ 10, which means 0 ~ 1 in step of 0.1
+ List of configured reference code rate for QPSK.*/
+ kal_int8 ref_beta_16qam[TDD_MAX_REF_BETA_NUM]; /*[Range]: -15 ~ 16, whose unit is dB.
+ List of configured reference beta for QPSK.*/
+
+} TDD_edch_etfcs_T;
+
+
+/*E-PUCH Timeslot Information, <3GPP-TS25.331:10.3.6.104>*/
+typedef struct _TDD_epuch_timeslot_info_T
+{
+ kal_uint8 ts_num; /*[range]: 0 ~ 6.
+ [meaning]:The number of time slot in which E-HICH is allocated.*/
+ TDD_midamble_info_T midamble_info; /*Midamble info for E-HICH*/
+} TDD_epuch_timeslot_info_T;
+
+/*SNPL Report Type, <3GPP-TS25.331:10.3.6.104>*/
+typedef enum _TDD_snpl_report_type_E
+{
+ TDD_SNPL_TYPE_1 = 0,
+ TDD_SNPL_TYPE_2,
+ TDD_SNPL_TYPE_INVALID
+} TDD_snpl_report_type_E;
+
+/*E-PUCH Information, <3GPP-TS25.331:10.3.6.104>*/
+typedef struct _TDD_epuch_info_T
+{
+ TDD_snpl_report_type_E snpl_report_type; /*SNPL report type.*/
+ TDD_edch_etfcs_T etfcs; /*E-TFCS information. <3GPP-TS25.331:10.3.6.105>*/
+ kal_int8 prx_base_des; /*[range]: -112~-50, in step of 1dBm.
+ [meaning]: Expected Pe-base.*/
+ kal_bool beacon_pl_est; /*TRUE: UE may take into account pathloss estimated from beacon function physical channels.
+ FALSE: UE shall not take into account pathloss estimation.*/
+ kal_uint8 tpc_step; /*[range]: 1,2,3. The transmission power control step size.*/
+ kal_uint8 pebase_pc_gap; /*[range]: 1~255, in sub-frames.
+ [meaning]: Gap of open-loop power control during closed-loop entered.*/
+ kal_uint8 sync_step; /*1 - 8, in 1/8 chip,Uplink synchronization step size.*/
+ kal_uint8 sync_freq; /*1 - 8, in sub-frame,Uplink synchronization frequencies, */
+ kal_uint8 min_allowed_code_rate; /*[range]: 0~63, in step of 0.015, i.e. 0.055~1.000.
+ [meaning]: Minimum allowed code rate during E-TFC procedure-2.*/
+ kal_uint8 max_allowed_code_rate; /*[range]: 0~63, in step of 0.015, i.e. 0.055~1.000.
+ [meaning]: Maximum allowed code rate during E-TFC procedure-2.*/
+ kal_uint8 num_epuch_timeslot; /*[range]: 1~5.
+ [meaning]: number of E-PUCH timeslots.*/
+ TDD_epuch_timeslot_info_T epuch_timeslot_list[TDD_MAX_UL_TIMESLOT_PER_SUBFRAME];/*E-PUCH timeslot info list*/
+ kal_uint8 pccpch_tx_power; /*[Range]: 6 ~ 43 by step 1 in dBm
+ [Meaning]:P-CCPCH transmit power*/
+ kal_int8 max_tx_power; /*[Range]: -50 ~ 33 dBm
+ [Meaning]: Max. allowed TX power.*/
+ kal_int8 umts_power_class; /*UE capability(in dBm)
+ The value's unit configured by SLCE is dBm.
+ define MAX_OUTPUT_POWER_CLASS_1 33 :+33dBm
+ define MAX_OUTPUT_POWER_CLASS_2 24 : +24dBm
+ define MAX_OUTPUT_POWER_CLASS_3 21 : +21dBm
+ define MAX_OUTPUT_POWER_CLASS_4 27 : +27dBm */
+} TDD_epuch_info_T;
+
+/*E-DCH HARQ RV Configuration, <3GPP-TS25.331:10.3.5.7d>*/
+typedef enum _TDD_edch_rv_config_E
+{
+ TDD_EDCH_RV0 = 0,
+ TDD_EDCH_RVTABLE
+} TDD_edch_rv_config_E;
+
+/*E-DCH HARQ Information, <3GPP-TS25.331:10.3.5.7d>*/
+typedef struct _TDD_edch_harq_info_T
+{
+ TDD_edch_rv_config_E edch_rv_config; /*RV configuration*/
+} TDD_edch_harq_info_T;
+
+
+
+/* [R8] Specify that E-DCH transmission is in dedicated state or common state */
+typedef enum _TDD_edch_transmission_type_E
+{
+ TDD_EDCH_IN_DCH_STATE = 0, /* E-DCH allocated in dedicated state */
+ TDD_EDCH_IN_COMMON_STATE /* E-DCH allocated in common state */
+}TDD_edch_transmission_type_E;
+
+/*****common EDCH info*****/
+typedef struct _TDD_common_e_rnti_info_T
+{
+ kal_uint16 starting_e_rnti; /*indicating the starting ERNTI related to one certain ERUCCH*/
+ kal_uint8 number_group; /*Indicates the number of common E-RNTI groups related to the E-RUCCH*/
+ kal_uint8 number_e_rnti_per_group; /*Indicates the number of common E-RNTIs per group*/
+}TDD_common_e_rnti_info_T;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+typedef struct _TDD_common_edch_info_T
+{
+ /*ccch_trans_info_T ccch_trans_info; CCCH transmission configuration for CELL_FACH on Prim-freq and Secondary-freq*/
+ kal_uint8 common_e_rnti_num;
+ TDD_common_e_rnti_info_T common_e_rnti_info[TDD_MAX_ERUCCH];
+}TDD_common_edch_info_T;
+/*****common EDCH info*****/
+
+
+/*****DRX related definitions*****/
+/*DRX cycle length k, real DRX cycle = 2^k*/
+typedef enum _TDD_ctrl_ch_drx_cycle_E
+{
+ TDD_drx_cycle_1 = 0,
+ TDD_drx_cycle_2,
+ TDD_drx_cycle_4,
+ TDD_drx_cycle_8,
+ TDD_drx_cycle_16,
+ TDD_drx_cycle_32,
+ TDD_drx_cycle_64
+}TDD_ctrl_ch_drx_cycle_E;
+
+/*subframe, use as EAGCH inactivity monitor threshold*/
+typedef enum _TDD_agch_drx_inact_TrHd_E
+{
+ TDD_drx_inaTrHd_0 = 0,
+ TDD_drx_inaTrHd_1,
+ TDD_drx_inaTrHd_2,
+ TDD_drx_inaTrHd_4,
+ TDD_drx_inaTrHd_8,
+ TDD_drx_inaTrHd_16,
+ TDD_drx_inaTrHd_32,
+ TDD_drx_inaTrHd_64,
+ TDD_drx_inaTrHd_128,
+ TDD_drx_inaTrHd_256,
+ TDD_drx_inaTrHd_512,
+ TDD_drx_inaTrHd_spare5, /*Add spare value*/
+ TDD_drx_inaTrHd_spare4,
+ TDD_drx_inaTrHd_spare3,
+ TDD_drx_inaTrHd_spare2, /*Add spare value*/
+ TDD_drx_inaTrHd_infinity
+}TDD_agch_drx_inact_TrHd_E;
+
+typedef struct _TDD_eagch_drx_info_T
+{
+ TDD_ctrl_ch_drx_cycle_E eagch_drx_cycle; /*DRX cycle = 2^k, k=0~6.*/
+ //kal_bool eagch_inact_TrHd_valid;
+ TDD_agch_drx_inact_TrHd_E eagch_inact_TrHd; /*subframe, use as EAGCH inactivity monitor threshold*/
+ kal_uint8 eagch_drx_offset; /*integer[0~63], subframe, offset of E-AGCH DRX cycle*/
+}TDD_eagch_drx_info_T;
+/*****DRX related definitions*****/
+
+
+/*****SPS info related definitions*****/
+typedef struct _TDD_trans_pattern_info_T
+{
+ kal_uint8 repet_period; /*repetition period: 1, 2, 4, 8, 16, 32 subframe*/
+ kal_uint8 repet_length; /*repetition length: 1~repet_period-1*/
+}TDD_trans_pattern_info_T;
+
+typedef struct _TDD_init_sps_edch_info_T
+{
+ kal_uint8 n_eucch;
+ TDD_ccode_lcr_E ccode; /*indicating which CH codes used for EDCH on SPS resources*/
+ kal_uint8 trri; /*Bit1: TS1, Bit2: TS2, ..., Bit5: Ts5.
+ Bit5 indicating the rightmost bit*/
+ kal_uint8 prri;
+ kal_uint8 active_time;
+ kal_uint8 subframe_num; /*0, 1; indicating activite on which subframe in one radio frame*/
+ kal_uint8 init_tx_pattern_idx; /*0 ~ maxEDCHTxPattern-TDD128 - 1*/
+}TDD_init_sps_edch_info_T;
+
+typedef struct _TDD_edch_sps_info_T
+{
+ kal_bool eagch_init_sps_valid; /*indicating whether init SPS PARAM is configured or not*/
+ kal_uint8 ehich_sigature_group_index; /*[range]: 0~19.*/
+ TDD_ehich_config_T sps_ehich_info;
+ kal_uint8 trans_pattern_num;
+ TDD_trans_pattern_info_T trans_pattern_list[TDD_maxEDCHTxPattern_TDD128];
+ TDD_init_sps_edch_info_T init_sps_edch_info; /*EDCH SPS resource info*/
+}TDD_edch_sps_info_T;
+/*****SPS info related definitions*****/
+
+/*****ERUCCH access type, TL1 trigger UAMC*****/
+typedef enum _TDD_erucch_access_type_E
+{
+ TDD_SCHEDULING_REQUEST= 0,
+ TDD_UL_SYNC_ORDER,
+ TDD_CELL_RESELECTION_IND
+}TDD_erucch_access_type_E;
+/*****ERUCCH access type, TL1 trigger UAMC*****/
+
+
+
+
+/*E-DCH Category Definitions, <3GPP-TS25.306:Table 5.1m>*/
+typedef enum _TDD_edch_category_E
+{
+ TDD_EDCH_CATEGORY_1 = 0, /*Maximum 2 timeslots for QPSK only UE.*/
+ TDD_EDCH_CATEGORY_2, /*Maximum 3 timeslots for QPSK only UE.*/
+ TDD_EDCH_CATEGORY_3, /*Maximum 2 timeslots for QPSK+16QAM only UE.*/
+ TDD_EDCH_CATEGORY_4, /*Maximum 3 timeslots for QPSK+16QAM only UE.*/
+ TDD_EDCH_CATEGORY_5, /*Maximum 4 timeslots for QPSK+16QAM only UE.*/
+ TDD_EDCH_CATEGORY_6 /*Maximum 5 timeslots for QPSK+16QAM only UE.*/
+} TDD_edch_category_E;
+
+/*PRACH Access Type, <3GPP-TS25.302:10.1.1>*/
+typedef enum _TDD_access_type_E
+{
+ TDD_ACCESS_TYPE_RACH = 0, /*Access Type is RACH*/
+ TDD_ACCESS_TYPE_ERUCCH /*Access Type is E-RUCCH*/
+} TDD_access_type_E;
+
+/*E-DCH Transmission Grant Mode*/
+typedef enum _TDD_edch_grant_mode_E
+{
+ TDD_EDCH_GRANT_MODE_SCHEDULED = 0,
+ TDD_EDCH_GRANT_MODE_NON_SCHEDULED,
+ TDD_EDCH_GRANT_MODE_INVALID
+
+ ,TDD_EDCH_GRANT_MODE_SPS
+
+} TDD_edch_grant_mode_E;
+
+/*E-HICH Result Code*/
+typedef enum _TDD_ehich_result_E
+{
+ TDD_EHICH_RESULT_NACK = 0,
+ TDD_EHICH_RESULT_ACK,
+ TDD_EHICH_RESULT_DISCARD,
+ TDD_EHICH_RESULT_INVALID
+} TDD_ehich_result_E;
+
+typedef enum _TDD_tx_suspend_E
+{
+ TDD_NO_SUSPEND = 0,
+ TDD_SUSPEND_NORMAL_DATA,
+ TDD_SUSPEND_DM,
+#ifdef __GEMINI__
+ TDD_SUSPEND_ALL_DATA,
+ TDD_SUSPEND_GEMINI,
+#else
+ TDD_SUSPEND_ALL_DATA
+#endif
+} TDD_tx_suspend_E;
+
+typedef struct _TDD_edch_retx_harq_info_T
+{
+ kal_uint8 harq_id; /*[range]: 0~7, 255 for invalid*/
+ kal_uint8 timeslots; /*[range]: 1~5, 0 when num_retx_pdu = 0.
+ [meaning]: how many timeslots granted for first transmission of this MAC-e PDU.*/
+ kal_uint8 etfci; /*[Range]: 0~63, 255 for invalid value.
+ [meaning]: E-TFCI granted for first transmission of this MAC-e PDU.*/
+ TDD_tdd128_modulation_E modulation; /*[meaning]: modulation used for the first transmission of this MAC-e PDU
+ only QPSK and 16QAM supportted */
+}TDD_edch_retx_harq_info_T;
+
+typedef enum _TDD_cedch_status_E
+{
+ TDD_CEDCH_IDLE = 0 ,
+ TDD_CEDCH_START,
+ TDD_CEDCH_ONGOING,
+ TDD_CEDCH_END
+}TDD_cedch_status_E;
+
+
+typedef struct _TDD_etfc_eval_info_req_T
+{
+ /*Grant Information for this E-DCH TTI*/
+ kal_uint16 sub_cfn; /*[range]: 0~511.
+ [meaning]: sub-frame number.*/
+ TDD_edch_grant_mode_E grant_mode; /*[meaning]: invalid grant, scheduled grant, or non-scheduled grant.*/
+ kal_bool is_scheduled_grant_detected; /*TRUE: shcheduled grant detected, even if preempted by non-scheduled TTI
+ FALSE: no scheduled grant detected.
+ [notes]Trigger UMAC to start T-WAIT,if running.*/
+ kal_bool is_final_scheduled_grant; /*TRUE: this is the final scheduled mode grant.
+ FALSE: not the final scheduled mode grant or non-scheduled mode grant.
+ [notes]: Trigger UMAC to start T-WAIT.*/
+ kal_uint8 num_timeslot_granted; /*[range]: 1~5, 0 for control signal only case.
+ [meaning]: how many timeslot granted for this E-DCH TTI.
+ [note]: Considered when evaluate scheduled MAC-e PDU retransmission.*/
+ kal_uint8 snpl_index; /*[range]: 0~31, and 255 when is_new_tx_required == KAL_FALSE.
+ [meaing]: the SNPL index to report when SI to included.*/
+ kal_uint8 uph_index; /*[range]: 0~31, and 255 when is_new_tx_required == KAL_FALSE.
+ [meaing]: the UPH index to report when SI to included.*/
+
+ /*E-HICH results for latest E-DCH TTI*/
+ kal_uint8 ehich_harq_id[TDD_MAX_EHICH_RESULT_NUM]; /*[range]: 0~7, 255 when no E-HICH result.
+ [meaning]: Ack/Nack is for which HARQ process.*/
+ TDD_ehich_result_E ehich_result[TDD_MAX_EHICH_RESULT_NUM]; /*[meaning]: E-HICH result, INVALID when no E-HICH result.*/
+
+ /*Control Signals*/
+ kal_uint8 mac_event; /*[meaning]: Forwarded MAC-e/es configuration activation signal.
+ Bit-mask of configuration:
+ * bit0: mac-e/es setup
+ * bit1: mac-e/es release
+ * bit2: mac-e/es modify.*/
+ TDD_tx_suspend_E tx_suspend;
+
+ kal_bool is_working_freq_changed; /*TRUE: Working frequency is changed, and UMAC shall start E-RUCCH access if TEBS > 0.
+ FALSE: Working frequency is the same.
+ [note]: <3GPP-TS25.321:11.9.1.5> requires both serving cell change and working frequency change
+ leads to E-RUCCH access. TDD128 doesn't support soft-handover, i.e. UMAC clearly knows the
+ handover procedure. As a result, we needn't the serving cell change indication in tick_1().*/
+ kal_bool mac_es_e_reset; /*KAL_TRUE: indicates the MAC-e/es entity needs to be reset*/
+ kal_uint8 mac_harq_event; /*MAC-e HARQ Events.
+ Bit-mask:
+ * bit0: E-TFC table changed
+ * bit1: HARQ RV Re-Configuration.
+ * bit2: capability category change.*/
+
+ kal_uint8 meas_occasion; /*bit0 indicates whether it is in DCH measurement occasion;
+ bit1 indicates whether it is in idle interval for E-UTRA Measurement.
+ value 1 means in the measurement occasion,
+ value 0 means not in the measurement occasion*/
+
+ kal_bool is_cedch;
+ kal_bool ernti_modify;
+ TDD_cedch_status_E cedch_status;
+
+} TDD_etfc_eval_info_req_T;
+
+typedef struct _TDD_etfc_eval_info_ind_T
+{
+ /*Grant Information for this E-DCH TTI*/
+ kal_uint16 sub_cfn; /*[range]: 0~511.
+ [meaning]: sub-frame number*/
+ TDD_edch_grant_mode_E grant_mode; /*[meaning]: invalid grant, scheduled grant, or non-scheduled grant.*/
+
+ /*E-TFC Evaluation Preparation Information for this E-DCH TTI*/
+ kal_bool tx_enable; /*TRUE: TL1 need to call tick_2() and tick_4().
+ FALSE: TL1 skip the call on tick_2() and tick_4().
+ [meaning]: Currently, UMAC set to FALSE only when is_tx_suspend = TRUE.
+ [notes]: Redundant if equal to is_tx_suspend, and keep it for future extension.*/
+ kal_bool is_user_data_avaialble; /*TRUE: user data is available to transmit, and TL1 perform E-TFC procedure-2.
+ FALSE: no user data is available to transmit, and TL1 select SI only E-TFC.*/
+ kal_uint8 delta_harq; /*[range]: 0~6dB.
+ [meaning]: the maximum Power Offset of all the MAC-d flows on scheduled mode or non-scheduled mode.
+ [notes]: TL1 ignore delta_harq when is_si_only = TRUE.*/
+
+ /*List of NACKed MAC-e PDU to Evaluate*/
+ kal_uint8 num_retx_pdu; /*[range]: 0~4, 0 is no HARQ process to retransmit.
+ [meaning]: how many NACKed HARQ processes to evaluation.
+ [notes]: UMAC will sort the MAC-e PDUs to ReTx from old to new.
+ TL1 can stop the evaluation if one is supported from both data size and power margin.
+ [notes]: Power restriction not apply to non-scheduled mode retransmission, <3GPP-TS25.321:11.9.1.4>.
+ To align the scheduled and non-schedulded mode, UMAC will return the ReTx MAC-e PDU to TL1,
+ while TL1 can jump over the ReTx evaluation procedure for non-scheduled mode.*/
+ TDD_edch_retx_harq_info_T retx_harq_info[TDD_MAX_EDCH_HARQ_PROC_PER_MODE]; /* [meaning]: harq releated information for retransmission PDU */
+
+ kal_uint8 tebs; /*indicating TEBS is zero or not for EAGCH monitoring*/
+
+} TDD_etfc_eval_info_ind_T;
+
+typedef struct _TDD_edch_data_req_T
+{
+ /*Grant Information for this E-DCH TTI*/
+ kal_uint16 sub_cfn; /*[range]: 0~511.
+ [meaning]: sub-frame number.*/
+ TDD_edch_grant_mode_E grant_mode; /*[meaning]: invalid grant, scheduled grant, or non-scheduled grant.*/
+
+ /*Re-transmission information*/
+ kal_uint8 selected_retx_harq_id; /*[range]: 0~7, 255 if no retx-pdu allowed.
+ [meaning]: Harq id of selected ReTx MAC-e PDU in retx_harq_info[].*/
+
+ /*New-transmission information*/
+ kal_bool is_new_tx_required; /*TRUE: new transmission required, due to either no ReTx available or allowed.
+ FALSE: no new transmission required, and UMAC ignore the following parameters.
+ [notes]: UMAC will ASSERT if both selected_retx_pdu == 255 and is_new_tx_required == KAL_FALSE.*/
+ kal_uint8 supported_etfci_num ; /*[Range]: 0~63
+ [Meaning]: The supported ETFC number,exclude ETFCI=0.*/
+ kal_uint8 supported_etfci_bitmap[TDD_MAX_ETFCI_BITMAP_SIZE] ; /*The bitmap indicates the status of ETFCr,exclude ETFCI=0.
+ Two bits indicate status of one ETFC.
+ 11: supported, 10: power not support, 01: TB size not support, 00: not support.
+ e.g. 2 LSB of supported_etfci_bitmap[0] indicates the status of ETFC0,
+ and 2 MSB of supported_etfci_bitmap[0] indicates the status of ETFC3.*/
+ kal_uint8 max_supported_etfci ; /* The max supported ETFCI, exclude ETFCI=0.
+ If SI only, this field should be set to 0xff.*/
+ kal_uint8 min_supported_etfci ; /* The min supported ETFCI, exclude ETFCI=0.
+ If SI only, this field should be set to 0xff.*/
+
+ kal_bool cell_reselection; /*indicating whether to carry SI for TDD_CELL_RESELECTION_IND*/
+
+} TDD_edch_data_req_T;
+
+typedef struct _TDD_edch_data_ind_T
+{
+ /*Grant Information for this E-DCH TTI*/
+ kal_uint16 sub_cfn; /*[range]: 0~511.
+ [meaning]: sub-frame number*/
+ TDD_edch_grant_mode_E grant_mode; /*[meaning]: invalid grant, scheduled grant, or non-scheduled grant.*/
+
+ /*E-UCCH information*/
+ kal_uint8 harq_id; /*[range]: 0~7.
+ [meaning]: the HARQ process identifier.*/
+ kal_uint8 etfci; /*[range]: 0~63.
+ [meaning]: the E-TFCI to transmit, with the configured category and granted timeslots.*/
+ kal_uint8 rsn; /*[range]: 0~3.
+ [meaning]: the RSN to use for this MAC-e PDU.*/
+
+ /*MAC-e PDU description*/
+ kal_bool is_new_tx; /*TRUE: first transmission of a new MAC-e PDU.
+ FALSE: retransmission of a MAC-e PDU.*/
+ kal_bool is_si_only; /*TRUE: SI only MAC-e PDU.
+ FALSE: a regular MAC-e PDU.*/
+ kal_uint16 tb_size; /*[range]: 23~11160, in bits, and 0 when is_new_tx_required == KAL_FALSE.
+ [meaning]: Bit length of data.*/
+ kal_uint32 *data; /*Point to MAC-e PDU data buffer. ¸ÃbufferÖ¸ÕëÓÉMACÌîÈëºÍÊÍ·Å£¬ÓÉTL1D¶ÁÈ¡¡£ÐèÒªsystem service±£Ö¤MAC of CR4ÓëTL1D of MD32¿´µ½µÄbufferµØÖ·ÊÇÒ»ÑùµÄ*/
+} TDD_edch_data_ind_T;
+
+#endif
+
+typedef enum _TDD_dmo_status_E
+{
+ TDD_ACTIVATE = 0, /*to activate this dmo pattern*/
+ TDD_DEACTIVATE = 1, /*to deactivate this dmo pattern*/
+}TDD_dmo_status_E;
+typedef enum _TDD_dmo_purpose_E
+{
+ TDD_DMO_INTER_FREQ = 1 << 0,
+ TDD_DMO_GSM_RSSI = 1 << 1,
+ TDD_DMO_GSM_INITIAL_BSIC = 1 << 2,
+ TDD_DMO_GSM_BSIC_RECFN = 1 << 3,
+ TDD_DMO_LTE_MEAS = 1 << 4,
+ TDD_DMO_ALL_PURPOSE = TDD_DMO_INTER_FREQ|TDD_DMO_GSM_RSSI|TDD_DMO_GSM_INITIAL_BSIC|TDD_DMO_GSM_BSIC_RECFN|TDD_DMO_LTE_MEAS,
+}TDD_dmo_purpose_E;
+typedef struct _TDD_dch_mo_info_T
+{
+ kal_uint8 pattern_id; /* Pattern sequence identifier.
+ [Range]: 0,1,¡, dmo_pattern_num-1.*/
+ TDD_dmo_status_E status_flag;
+ kal_uint8 purpose; /*Measurement Purpose. The value 1 of a bit means that the measurement occasion pattern sequence is applicable for the corresponding type of measurement.
+ Bit 0 is for Inter-frequency measurement.
+ Bit 1 is for GSM carrier RSSI measurement.
+ Bit 2 is for Initial BSIC identification.
+ Bit 3 is for BSIC re-confirmation.
+ Bit 4 is for E-UTRA measurement.
+ Note: Bit 0 is the first/leftmost bit of the bit string....*/
+ kal_uint8 k; /*CELL_DCH measurement occasion cycle length coefficient. [Range]: 0,1,¡, 9.
+ The actual measurement occasion period equal to 2^k radio frames.
+ Value 0 indicates continuous allocation*/
+ kal_uint16 offset; /*In frames. The measurement occasion position in the measurement period.
+ [Range]: 0,1,¡, 2^k-1*/
+ kal_uint16 length; /*The measurement occasion length in frames starting from the Offset.
+ [Range]: 1,¡, 2^k*/
+ kal_uint8 timeslot_bmp; /*Bitmap indicating which of the timeslot(s) is/are allocated for measurement.
+ Bit 0 is for timeslot 0.
+ Bit 1 is for timeslot 1.
+ Bit 2 is for timeslot 2.
+ Bit 3 is for timeslot 3.
+ Bit 4 is for timeslot 4.
+ Bit 5 is for timeslot 5.
+ Bit 6 is for timeslot 6.
+
+ The value 0 of a bit means the corresponding timeslot is not used for measurement.
+ The value 1 of a bit means the corresponding timeslot is used for measurement.
+ Note1: Bit 0 is the first/leftmost bit of the bit string.
+ Note2: all 1 means all the timeslots can be used for measurement.*/
+}TDD_dch_mo_info_T;
+
+/*UL dpch reconfig type*/
+typedef enum _TDD_ul_dpch_reconfig_type_E
+{
+ TDD_UL_DPCH_NONE = 0, /*Do nothing with ul dpch.*/
+ TDD_UL_DPCH_SETUP, /*Setup ul dpch.*/
+ TDD_UL_DPCH_MODIFY, /*modify ul dpch.*/
+ TDD_UL_DPCH_RELEASE /*Release ul dpch.*/
+} TDD_ul_dpch_reconfig_type_E;
+
+
+/*DL dpch reconfig type*/
+typedef enum _TDD_dl_dpch_reconfig_type_E
+{
+ TDD_DL_DPCH_NONE = 0, /*Do nothing with dl dpch.*/
+ TDD_DL_DPCH_SETUP, /*Setup dl dpch.*/
+ TDD_DL_DPCH_MODIFY, /*modify dl dpch.*/
+ TDD_DL_DPCH_RELEASE /*Release dl dpch.*/
+} TDD_dl_dpch_reconfig_type_E;
+
+/*post tx type*/
+typedef enum _TDD_post_tx_type_E
+{
+ TDD_POST_TX_RACH = 0,
+ TDD_POST_TX_DCH,
+ TDD_POST_TX_ERUCCH
+} TDD_post_tx_type_E;
+
+#if defined (__GEMINI__) && defined (__UMTS_RAT__)
+typedef enum TDD_uas_gemini_conflict_cause_enum
+{
+ TDD_URR_NO_CONFLICT = 0, /*UConflictWithNone*/
+ TDD_URR_CONFLICT_WITH_UMTS_BCH_HIGH = 1, /*UConflictWithSIB_HIGH*/
+ TDD_URR_CONFLICT_WITH_UMTS_PICH = 2, /*UConflictWithPICH*/
+ TDD_URR_CONFLICT_WITH_UMTS_CTCH = 3, /*UConflictWithCTCH*/
+ TDD_URR_CONFLICT_WITH_UMTS_BCH_LOW = 4, /*UConflictWithSIB_LOW*/
+ TDD_URR_CONFLICT_WITH_GSM_NBCCH = 5, /*UConflictWithNBCCh*/
+ TDD_URR_CONFLICT_WITH_GSM_PCH = 6, /*UConflictWithPCh*/
+ TDD_URR_CONFLICT_WITH_GSM_BCCH = 7, /*UConflictWithBCCh*/
+ TDD_URR_CONFLICT_WITH_GSM_OTHERS = 8, /*UConflictWithOther*/
+} TDD_uas_gemini_conflict_cause_enum;
+#endif
+/* [R8] Enumeration of hs_dsch transmission type. */
+typedef enum _TDD_rrc_state_E
+{
+ TDD_CELL_DCH = 0,
+ TDD_URA_PCH,
+ TDD_CELL_PCH,
+ TDD_IDLE_FACH,
+ TDD_CELL_FACH
+} TDD_rrc_state_E;
+
+
+/* [R8] Enumeration of enabling delay. Uint is radio frame. */
+typedef enum _TDD_enabling_delay_E
+{
+ TDD_ED_0 = 0,
+ TDD_ED_1,
+ TDD_ED_2,
+ TDD_ED_4,
+ TDD_ED_8,
+ TDD_ED_16,
+ TDD_ED_32,
+ TDD_ED_64,
+ TDD_ED_128,
+ TDD_ED_spare7,
+ TDD_ED_spare6,
+ TDD_ED_spare5,
+ TDD_ED_spare4,
+ TDD_ED_spare3,
+ TDD_ED_spare2,
+ TDD_ED_INFINITY
+} TDD_enabling_delay_E;
+
+/* [R8] Enumeration of HS-SCCH/E-AGCH DRX cycle. Uint is subframe. */
+/*
+typedef enum _control_channel_drx_cycle_E
+{
+ TDD_drx_cycle_1 = 0,
+ TDD_drx_cycle_2,
+ TDD_drx_cycle_4,
+ TDD_drx_cycle_8,
+ TDD_drx_cycle_16,
+ TDD_drx_cycle_32,
+ TDD_drx_cycle_64
+} control_channel_drx_cycle_E;
+*/
+/* [R8] Enumeration of ue_drx_cycle_inactivity_threshold. Uint is subframe. */
+typedef enum _TDD_scch_drx_cycle_inactivity_threshold_E
+{
+ TDD_drx_cycle_inaTrHd_1,
+ TDD_drx_cycle_inaTrHd_2,
+ TDD_drx_cycle_inaTrHd_4,
+ TDD_drx_cycle_inaTrHd_8,
+ TDD_drx_cycle_inaTrHd_16,
+ TDD_drx_cycle_inaTrHd_32,
+ TDD_drx_cycle_inaTrHd_64,
+ TDD_drx_cycle_inaTrHd_128,
+ TDD_drx_cycle_inaTrHd_256,
+ TDD_drx_cycle_inaTrHd_512,
+ TDD_drx_cycle_inaTrHd_spare6,
+ TDD_drx_cycle_inaTrHd_spare5,
+ TDD_drx_cycle_inaTrHd_spare4,
+ TDD_drx_cycle_inaTrHd_spare3,
+ TDD_drx_cycle_inaTrHd_spare2,
+ TDD_drx_cycle_inaTrHd_infinity
+} TDD_scch_drx_cycle_inactivity_threshold_E;
+
+/* [R8] Enumeration of out-of-sync window. Uint is ms. */
+typedef enum _TDD_out_of_sync_win_E
+{
+ TDD_out_of_sync_win_40 = 0,
+ TDD_out_of_sync_win_80,
+ TDD_out_of_sync_win_160,
+ TDD_out_of_sync_win_320,
+ TDD_out_of_sync_win_640,
+} TDD_out_of_sync_win_E;
+
+/* [R8] Enumeration of enhanced CELL_FACH DRX status */
+typedef enum _TDD_hs_cell_fach_drx_status_E
+{
+ TDD_DRX_OFF = 0, /* No DRX in CELL_FACH state or ETWS reception is on-going */
+ TDD_DRX_ON_NORMAL, /* UL1 should start CELL_FACH DRX when the normal criterion is fulfilled */
+ TDD_DRX_ON_ETWS_END, /* SLCE should set this enum when the ETWS procedure ends */
+ TDD_DRX_INVALID /* SLCE internal use. Invalid for UL1. */
+}TDD_hs_cell_fach_drx_status_E;
+
+typedef struct _TDD_receive_pattern_list_info_T
+{
+ kal_uint8 repetition_period; /* Integer (1, 2, 4, 8, 16, 32). Value 1 indicate continuous*/
+ kal_uint8 repetition_length; /* Integer (1.. Repetition period - 1)*/
+} TDD_receive_pattern_list_info_T;
+
+typedef struct _TDD_harq_Info_sps_T
+{
+ kal_uint8 processes_number; /*Integer (1..8)*/
+ kal_uint16 process_memory_size; /*Integer (800 .. 16000 by step of 800, 17600 .. 32000 by step of 1600, 36000 .. 80000 by step of 4000, 88000 .. 160000 by step of 8000, 176000 .. 304000 by step of 16000)
+ Maximum number of soft channel bits available in the virtual IR buffer */
+} TDD_harq_Info_sps_T;
+
+typedef struct _TDD_hs_dsch_paging_info_T
+{
+ kal_uint8 trri; /* BitString(6) Timeslot Resource Related Information, bitmap of assigned timeslots.
+ Bit0-TS0, Bit1-TS2, Bit2-TS3, ... Bit5-TS6.
+ Notes: for TL1, only check Bit1 -- Bit5*/
+ TDD_ccode_lcr_E start_ccode; /*The start channelization code of HS-PDSCH.*/
+ TDD_ccode_lcr_E stop_ccode; /*The stop channelization code of HS-PDSCH.*/
+ TDD_midamble_info_T hspdsch_midamble_info; /*Midamble info for HS-PDSCH*/
+ kal_uint8 paging_sub_channel_size; /* [Range] Integer (1..3) number of frames for a Paging sub-channel*/
+ kal_int8 pcch_tb_size_index[2]; /* [Range] Integer (1..32). -1 if this is invalid. Index of value range 1 to 32 of the MAC-ehs transport block size as described in Table9.2.2.3.8 of 3GPP 25.321. */
+} TDD_hs_dsch_paging_info_T;
+
+
+typedef struct _TDD_hs_scch_drx_info_T
+{
+ TDD_ctrl_ch_drx_cycle_E hs_scch_drx_cycle; /* [Meaning]: HS-SCCH reception pattern, i.e. how often UE has to monitor HSSCCH. Units of subframes*/
+ kal_bool hs_scch_drx_inaTrHd_valid;
+ TDD_scch_drx_cycle_inactivity_threshold_E hs_scch_drx_inaTrHd; /* [Meaning]: Units of subframes.Five spare values are needed.*/
+ kal_uint8 hs_scch_drx_offset; /*[Range]: Integer (0..63).
+ [Meaning]: Units of subframes. Offset of the HS-SCCH DRX cycles*/
+} TDD_hs_scch_drx_info_T;
+
+typedef struct _TDD_initial_sps_info_hsdsch_T
+{
+ kal_uint8 trri; /*BitStrin(5) indicating which of the timeslots configured for HS-PDSCH are allocated for SPS resource.
+ if ts0 indicator == TRUE, Bit1: TS0, Bit2: TS3, ..., Bit5: Ts6
+ else Bit1: TS2, Bit2: TS3, ..., Bit5: Ts6
+ Bit5 indicating the rightmost bit!*/
+ TDD_ccode_lcr_E start_ccode; /*The start channelization code of HS-PDSCH.*/
+ TDD_ccode_lcr_E stop_ccode; /*The stop channelization code of HS-PDSCH.*/
+ kal_uint8 active_time; /*0~~255, Specifies the HS-PDSCH Offset in Radio Frame level*/
+ kal_uint8 subframe_number; /*Integer (0..1),Specifies the HS-PDSCH Offset in subframe level*/
+ kal_uint8 init_tb_size_index; /*Integer (0.. maxTbsForHSDSCH-TDD128-1)*/
+ kal_uint8 init_rx_pattern_index; /*Integer (0.. maxRxPatternForHSDSCH-TDD128-1)*/
+ kal_uint8 hs_sich_index; /*Integer (0.. maxHSSICH-TDD128-1)*/
+ TDD_tdd128_modulation_E modulation; /*Enumerated (QPSK, 16QAM)*/
+} TDD_initial_sps_info_hsdsch_T;
+
+typedef struct _TDD_hs_cell_fach_drx_T
+{
+ TDD_hs_cell_fach_drx_status_E hs_cell_fach_drx_status; /* enhanced CELL_FACH DRX status */
+ kal_uint16 timer_length; /* inactivity timer to start HS CELL_FACH DRX (100/200/400/800 ms)*/
+ kal_uint8 drx_cycle_length; /* HS CELL_FACH DRX cycle length (4/8/16/32 frames) */
+ kal_uint8 drx_burst_length; /* the period within the HS DRX cycle that the UE continuously receive HS-DSCH (1/2/4/8/16 frames) */
+}TDD_hs_cell_fach_drx_T;
+
+typedef struct _TDD_hs_dsch_sps_info_T
+{
+ kal_bool hs_dsch_init_sps_valid; /*indicating
+ whether init SPS PARAM is configured or not*/
+ kal_uint8 tb_size_num; /* maxTbsForHSDSCH-TDD128 = 4*/
+ kal_uint8 tb_size_list[4]; /* Integer (1..63).
+ Index of the MAC-hs transport block size.*/
+ kal_uint8 receive_pattern_num; /* maxRxPatternForHSDSCH-TDD128 = 4*/
+ TDD_receive_pattern_list_info_T receive_pattern_list[4];
+ TDD_harq_Info_sps_T harq_Info_sps;
+ kal_uint8 sich_num; /* maxHSSICH-TDD128 = 4*/
+ TDD_hssich_info_T hs_sich_list[TDD_MAX_HSSCCH_NUM];
+ TDD_initial_sps_info_hsdsch_T initial_sps_info_hsdsch;
+} TDD_hs_dsch_sps_info_T;
+
+typedef struct _TDD_hs_cell_pch_state_info_T
+{
+ TDD_pich_info_T pich_info;
+ kal_uint8 reception_window_size; /* [Range] Integer (1¡16) Number of subframes for UE to detect the HS-SCCH */
+ kal_bool hs_dsch_paging_info_valid; /* TRUE: The hs_dsch_paging_info is valid. TRUE also means UE donot have dedicated H-RNTI*/
+ TDD_hs_dsch_paging_info_T hs_dsch_paging_info; /* HSDSCH Paging info*/
+} TDD_hs_cell_pch_state_info_T;
+
+typedef struct _TDD_hs_cell_fach_state_info_T
+{
+ kal_bool ts0_indicator; /* 1: TS0 used for HSDSCH; 0: TS0 is not used for HSDSCH*/
+ TDD_hs_cell_fach_drx_T fach_drx_info;
+} TDD_hs_cell_fach_state_info_T;
+
+typedef struct _TDD_hs_cell_dch_state_info_T
+{
+ kal_uint8 pa_plus_valid_flag; /* Bit mask:
+ Bit 0: control_channel_drx_status en/disable
+ Bit 1: sps_status en/disable
+
+ Bit 2: drx_param_valid. When Bit0 is "1", but Bit2 is "0", indicating DRX keeps enabled but PARAM not modify
+ Bit 3: hs_dsch_sps_param_valid. Reference Bit2 comments*/
+ TDD_hs_scch_drx_info_T hs_scch_drx_param; /* HS-SCCH DRX relate parameters*/
+ TDD_enabling_delay_E enabling_delay;
+ TDD_hs_dsch_sps_info_T hs_dsch_sps_info; /* HS-DSCH SPS Configuration Information*/
+ TDD_out_of_sync_win_E out_of_sync_window; /* Enumerated (40, 80, 160, 320, 640). Value in milliseconds.*/
+ kal_bool ts0_indicator; /* Absence of this IE means that the enhanced TS0 is not used. The presence of this IE means that the first bit of timeslot information on HS-SCCH is used to indicate TS0.*/
+} TDD_hs_cell_dch_state_info_T;
+
+typedef union _TDD_hspdsch_state_info_T
+{
+ TDD_hs_cell_pch_state_info_T cell_pch; /* The parameters in CELL_PCH or URA state. */
+ TDD_hs_cell_fach_state_info_T cell_fach;
+ TDD_hs_cell_dch_state_info_T cell_dch; /* The parameters in CELL_DCH state. */
+} TDD_hspdsch_state_info_T;
+
+
+
+typedef enum _TDD_tl1_em_tstcmdtype
+{
+ TDD_TL1_EM_TST_TX_START = 0,
+ TDD_TL1_EM_TST_TX_STOP = 1,
+ TDD_TL1_EM_TST_RX_REPORT = 2,
+ TDD_TL1_EM_TST_TX_REPORT = 3
+}TDD_tl1_em_tstcmdtype;
+
+typedef struct _TDD_tl1_em_tstcmdpara
+{
+ kal_uint8 band;
+ kal_uint16 freq;
+ kal_uint8 power;
+}TDD_tl1_em_tstcmdpara;
+#if defined(__SIMULATION_PS_TL1_BOTH__) || defined(__TL1_TST_LOG_DSP_RESP__)
+typedef enum
+{
+ TDD_TL1_TIMER_SYNC = 1,
+ TDD_TL1_TIMER_SNIFFER,
+ TDD_TL1_TIMER_DSP_CEHCK,
+} TDD_tl1_timer_E;
+#endif
+
+
+#endif
diff --git a/mcu/interface/l1/tl1/tl1_ps_cc_itf.h b/mcu/interface/l1/tl1/tl1_ps_cc_itf.h
new file mode 100644
index 0000000..69b8f19
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1_ps_cc_itf.h
@@ -0,0 +1,207 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * tl1_ps_cc_itf.h
+ *
+ * Project:
+ * --------
+ * UMOLY_Software
+ *
+ * Description:
+ * ------------
+ * TL1 and PS cross core share memory interface declare
+ *****************************************************************************/
+#ifndef _TL1_PS_CC_ITF_H_
+#define _TL1_PS_CC_ITF_H_
+
+#include "tl1_struct.h"
+#include "tl1_cc_public.h"
+
+/*=======================================TL1 and MAC sharememory=================================*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+extern TDD_etfc_eval_info_req_T g_tl1_edch_tick1_req;
+extern TDD_etfc_eval_info_ind_T g_mac_edch_tick1_ind;
+extern TDD_edch_data_req_T g_tl1_edch_tick2_req;
+extern TDD_edch_data_ind_T g_mac_edch_tick2_ind;
+extern TDD_uldch_data_req_T g_tl1_uldch_data_req;
+extern TDD_uldch_data_ind_T g_mac_uldch_data_ind;
+extern tdd_phy_hsdsch_data_ind_struct g_tl1_to_mac_dsch_data_ind[2];
+
+extern MAC_TO_TL1_RX_BUF_T gMacToTl1RxPchBufInfo[DL_PCH_DATA_BUF_NUM];
+extern MAC_TO_TL1_RX_BUF_T gMacToTl1RxDchBufInfo[DL_DCH_DATA_BUF_NUM];
+extern MAC_TO_TL1_RX_BUF_T gMacToTl1RxDschBufInfo[HSDSCH_DATA_BUF_NUM];
+
+
+//@wei tang: R4 pdu buffer
+DECLARE_SHARED_VAR(kal_bool, TDD_gIsMacR4PduAllocated)
+DECLARE_SHARED_VAR(kal_uint32, TDD_gInIndexMacR4PduFreeList)
+DECLARE_SHARED_VAR(kal_uint32, TDD_gOutIndexMacR4PduFreeList)
+DECLARE_SHARED_ARRAY(kal_uint8*, TDD_gBackupMacR4PduBuffer,1)
+DECLARE_SHARED_ARRAY(kal_uint8*,TDD_gMacR4PduBufferFreeList,TDD_MAX_MAC_DCH_PDU_NUM)
+
+//@Weimin: PCH pdu buffer
+DECLARE_SHARED_VAR(kal_bool, TDD_gIsMacPchPduAllocated)
+DECLARE_SHARED_VAR(kal_uint32, TDD_gInIndexMacPchPduFreeList)
+DECLARE_SHARED_VAR(kal_uint32, TDD_gOutIndexMacPchPduFreeList)
+DECLARE_SHARED_ARRAY(kal_uint8*, TDD_gBackupMacPchPduBuffer,1)
+DECLARE_SHARED_ARRAY(kal_uint8*,TDD_gMacPchPduBufferFreeList,TDD_MAX_MAC_PCH_PDU_NUM)
+
+
+//DECLARE_SHARED_VAR(kal_bool,TDD_gIsMacR4PduAllocated)
+
+#if !defined(__L1_STANDALONE__)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+DECLARE_SHARED_VAR(kal_uint8 *, TDD_gMacHsPduBufferArray)
+DECLARE_SHARED_VAR(kal_uint8 *, TDD_gBackupMacHsPduBufferArray)
+DECLARE_SHARED_VAR(kal_uint8 *, TDD_gMacR4PduBufferArray)
+DECLARE_SHARED_VAR(kal_uint8 *, TDD_gBackupMacR4PduBufferArray)
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+DECLARE_SHARED_ARRAY(kal_uint8, TDD_gMacR99TxDataMem, 4096)
+DECLARE_SHARED_ARRAY(kal_uint8, TDD_gERucch_SI_Output, 5)
+DECLARE_SHARED_ARRAY(kal_uint32, TDD_gMACeiPDU_CC_Buf, (TDD_MAX_NUM_OF_EDCH_HARQ_PROCESS * TDD_MAC_E_PDU_MEMORY_SIZE/4))
+#endif
+
+DECLARE_SHARED_VAR(kal_bool, IsPCHRBest)
+DECLARE_SHARED_VAR(kal_bool, IsPCHAssemble)
+
+//TL1 and MAC interactive function for 6292/6293 project
+#if !defined(__L1_STANDALONE__)
+extern void l2p_tdd0_cc_irq_lisr_cb(kal_uint32 op_code, kal_uint32 addr, kal_uint32 size); //UPADCHCSR trigger
+extern void l2p_tdd1_cc_irq_lisr_cb(kal_uint32 op_code, kal_uint32 addr, kal_uint32 size); //DPADATA trigger
+#endif
+extern void tl1_m_l_entry(kal_uint32 trigger_type, kal_uint32 trigger_address, kal_uint32 trigger_size);
+#if !defined(__L1_STANDALONE__)
+#define TL1_TRIGGER_MAC_INTERRUPT(irq_index, trigger_type, address_ptr, trigger_size) \
+do{\
+ switch(irq_index) \
+ {\
+ case TL1_TRIGGER_MAC_UPADCHCSR_CC_IRQ: \
+ {\
+ l2p_tdd0_cc_irq_lisr_cb(trigger_type, (kal_int32)address_ptr, trigger_size); \
+ break; \
+ }\
+ case TL1_TRIGGER_MAC_DPADATA_CC_IRQ: \
+ {\
+ l2p_tdd1_cc_irq_lisr_cb(trigger_type, (kal_int32)address_ptr, trigger_size); \
+ break; \
+ }\
+ default: \
+ {\
+ ASSERT(0); \
+ }\
+ }\
+}while(0)
+#else //#if !defined(__L1_STANDALONE__)
+#define TL1_TRIGGER_MAC_INTERRUPT(irq_index, trigger_type, address_ptr, trigger_size)
+#endif //#if !defined(__L1_STANDALONE__)
+#define MAC_TRIGGER_TL1_INTERRUPT(trigger_type, trigger_address, trigger_size) tl1_m_l_entry(trigger_type, trigger_address, trigger_size)
+
+
+/*===============================================================================================*/
+
+/*======================================TL1 and NAC sharememory==================================*/
+DECLARE_SHARED_ARRAY(kal_uint32, g_tdd_rrm_env_state, 2)
+/* For RRM env state setting: void set_rrm_env_state(kal_bool rrm_state1, kal_bool rrm_state2);
+ µ±RRM״̬±ä»»Ê±NAS module¼°Ê±CALL this API¸üÐÂRRM״̬ÐÅÏ¢£¬
+ rrm_state1£ºKAL_TRUE or KAL_FALSE
+ rrm_state2£ºKAL_TRUE or KAL_FALSE
+ ÆäÖÐrrm_state1µÄÐÅϢΪÔAPI: is_rrm_env(KAL_FALSE)ʱµÃµ½µÄÊä³ö״̬¡£
+ rrm_state2µÄÐÅϢΪÔAPI: is_rrm_env(KAL_TRUE)ʱµÃµ½µÄÊä³ö״̬ */
+#define TDD_SET_RRM_ENV_STATE(rrm_state1, rrm_state2) do{\
+ volatile kal_uint32 *rrm_env_state_ptr; \
+ rrm_env_state_ptr = (volatile kal_uint32 *)SHARED_pARRAY(g_tdd_rrm_env_state); \
+ *(volatile kal_uint32 *)rrm_env_state_ptr = rrm_state1; \
+ *(volatile kal_uint32 *)(rrm_env_state_ptr + 1) = rrm_state2; \
+ }while(0)
+#define TDD_GET_RRM_ENV_STATE(is_rrm_flag, rrm_state) do{\
+ volatile kal_uint32 *rrm_env_state_ptr; \
+ rrm_env_state_ptr = (volatile kal_uint32 *)SHARED_pARRAY(g_tdd_rrm_env_state); \
+ rrm_state = ((is_rrm_flag == KAL_FALSE) ? (*(volatile kal_uint32 *)rrm_env_state_ptr) : (*(volatile kal_uint32 *)(rrm_env_state_ptr + 1))); \
+ }while(0)
+
+/*======================================TL1 and NAS sharememory==================================*/
+
+/*======================================TL1 and UAS sharememory==================================*/
+DECLARE_SHARED_ARRAY(kal_uint32, g_tdd_sfn_cfn, 2)
+#define TDD_SET_CURRENT_TIME(sfn, cfn) do{\
+ volatile kal_uint32 *tdd_current_time_ptr; \
+ tdd_current_time_ptr = (volatile kal_uint32 *)SHARED_pARRAY(g_tdd_sfn_cfn); \
+ *(volatile kal_uint32 *)tdd_current_time_ptr = sfn; \
+ *(volatile kal_uint32 *)(tdd_current_time_ptr + 1) = cfn; \
+ }while(0)
+#define TDD_GET_CURRENT_TIME(sfn, cfn) do{\
+ volatile kal_uint32 *tdd_current_time_ptr; \
+ tdd_current_time_ptr = (volatile kal_uint32 *)SHARED_pARRAY(g_tdd_sfn_cfn); \
+ sfn = *(volatile kal_uint32 *)tdd_current_time_ptr; \
+ cfn = *(volatile kal_uint32 *)(tdd_current_time_ptr + 1); \
+ }while(0)
+/*======================================TL1 and UAS sharememory==================================*/
+
+
+/*======================================TL1 and SLT sharememory==================================*/
+#if defined(__IC_SLT__)
+DECLARE_SHARED_VAR(TL1_SLT_CC_INFO_T, g_tdscdma_slt_result)
+#endif
+/*======================================TL1 and SLT sharememory==================================*/
+#endif //#ifndef _TL1_PS_CC_ITF_H_
diff --git a/mcu/interface/l1/tl1/tl1_rf_cc_shm_data.h b/mcu/interface/l1/tl1/tl1_rf_cc_shm_data.h
new file mode 100644
index 0000000..a6dd69b
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1_rf_cc_shm_data.h
@@ -0,0 +1,135 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mml1_rf_cc_shm_data.h
+ *
+ * Project:
+ * --------
+ * TK6291 Project
+ *
+ * Description:
+ * ------------
+ * MMRF share memory data
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*===============================================================================*/
+
+#ifndef _TL1_RF_CC_SHM_DATA_H_
+#define _TL1_RF_CC_SHM_DATA_H_
+
+#include "kal_general_types.h"
+#include "mmrf_kal.h"
+
+#include "tl1d_custom_drdi.h"
+#include "t12193.h"
+#include "tl1cal_ast.h"
+#include "tl1d_rf_cal_poc_data.h"
+
+#ifdef __TAS_SUPPORT__
+#include "tl1d_custom_rf_tas_struct.h"
+#endif
+typedef struct{
+ast_tl1cal_tempdacData_T dac;
+ast_tl1cal_afcData_T afc;
+ast_tl1cal_capData_T capid;
+ast_tl1cal_pathlossData_T agc[3];
+ast_tl1cal_txdacData_T apc[3];
+ast_tl1cal_txPdData_T pdcomp[3];
+}T_AST_RF_CAL_DATA_T;
+
+typedef T_MIPI_CUSTOMIZATION_STRUCT T_AST_RF_MIPI_DATA_T;
+typedef T_TD_CUSTOMIZATION_STRUCT T_AST_RF_CUSTOM_DATA_T;
+typedef T_RF_PROG_SEQ_STRUCT T_AST_RF_TIMING_DATA_T;
+typedef TDS_RF_POC_COMP_T T_AST_RF_POC_DATA_T;
+typedef T_TD_CUSTOMIZATION_DAT_STRUCT T_AST_RF_DAT_DATA_T;
+
+
+//Tl1 Custom Data SHM Definition
+MMRF_CUSTOM_DECLARE_SHARED_VAR( T_AST_RF_CUSTOM_DATA_T, TDS_RF_COMMON_DATA_SHM);
+MMRF_CUSTOM_DECLARE_SHARED_VAR( T_AST_RF_MIPI_DATA_T, TDS_RF_MIPI_DATA_SHM);
+MMRF_CUSTOM_DECLARE_SHARED_VAR( T_AST_RF_CAL_DATA_T, TDS_RF_CAL_DATA_SHM);
+MMRF_CUSTOM_DECLARE_SHARED_VAR( T_AST_RF_TIMING_DATA_T, TDS_RF_TIMING_DATA_SHM);
+MMRF_CUSTOM_DECLARE_SHARED_VAR( T_AST_RF_POC_DATA_T, TDS_RF_POC_DATA_SHM);
+#ifdef __TAS_SUPPORT__
+MMRF_CUSTOM_DECLARE_SHARED_VAR( T_TD_CUSTOMIZATION_TAS_STRUCT, TDS_RF_TAS_DATA_SHM);
+#endif
+MMRF_CUSTOM_DECLARE_SHARED_VAR( T_AST_RF_DAT_DATA_T, TDS_RF_DAT_DATA_SHM);
+
+#endif //#ifndef _MML1_RF_CC_SHM_DATA_H_
diff --git a/mcu/interface/l1/tl1/tl1_struct.h b/mcu/interface/l1/tl1/tl1_struct.h
new file mode 100644
index 0000000..c407298
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1_struct.h
@@ -0,0 +1,2895 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2009
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/******************************************************************************
+ * Filename:
+ * --------------------------------------------------------
+ * tl1_struct.h
+ *
+ * Project:
+ * --------------------------------------------------------
+ *
+ *
+ * Description:
+ * --------------------------------------------------------
+ *
+ *
+ * Author:
+ * --------------------------------------------------------
+ * -------
+ *
+ * --------------------------------------------------------
+ * $Log$
+ *
+ * 09 25 2019 xiaochi.zhang
+ * [MOLY00394636] AT+ERFTX error handling enhancement - R3 TDSCDMA Part
+ * .
+ * rf desense tl1
+ *
+ * 02 21 2019 chason.cheng
+ * [MOLY00384995] [VMOLY] GEMINI 3.0, AFR, Unify Frequency scan, BGSEARCH
+ *
+ * .
+ *
+ * 02 18 2019 yanjuan.feng
+ * [MOLY00384995] [VMOLY] GEMINI 3.0, AFR, Unify Frequency scan, BGSEARCH
+ * .tdd-csce part,background search,resume cnf,freq priority unify
+ *
+ * 01 23 2019 vend_mtb_mobiveil012
+ * [MOLY00349793] [L4 HDR] ERFSCAN feature changes to VMOLYE
+ *
+ * 10 31 2018 xiaochi.zhang
+ * [MOLY00361478] [Gen97] Gemini Compile Option Clean Up
+ *
+ * .
+ *
+ * 08 29 2018 chason.cheng
+ * [MOLY00325833] TDSCDMA GEN95 UNIFY TAS.TDS build error debug
+ *
+ * 06 08 2018 chason.cheng
+ * [MOLY00325833] TDSCDMA GEN95 UNIFY TAS
+ *
+ * .TDS TAS UTAS UPDATE
+ *
+ * 05 23 2018 cruze.yu
+ * [MOLY00285698] [93/95 re-arch][TL1] tl1 option clean
+ *
+ * .
+ *
+ * 08 03 2017 fanzhi.meng
+ * [MOLY00268223] ÔÚAP²à´ò¿ª»ò¹Ø±Õij¸öBandµÄTAS¹¦Äܼ°»ñȡij¸öBandÊÇ·ñÖ§³ÖTAS
+ *
+ * .TAS new requirement TDS SW update.
+ *
+ * 06 21 2017 fanzhi.meng
+ * [MOLY00258592] Titan_DAT_SAR_feature patch back and Add DRDI custom paramter "RO" property in MT6293 project
+ *
+ * 1. titan DAT and SAR feature patch back.
+ * 2. custom data change to "RO".
+ *
+ * 04 12 2017 weimin.zeng
+ * [MOLY00240270] [6293][Gemini][T+W] Phase 1: Common Interface Changes Check in
+ *
+ * , 3G TDD UMAC PCH buffer.
+ *
+ * 02 09 2017 xiaochi.zhang
+ * [MOLY00204784] [Android N]TL1 add Tx Rx active time for Android N
+ *
+ * .
+ *
+ * 01 17 2017 fanzhi.meng
+ * [MOLY00214807] MT6292/UMOLY_MT6293/UMOLYA TL1 CODE maintain
+ * .
+ *
+ * 01 17 2017 yanhai.xuan
+ * [MOLY00168027] check in code to MT6293_TL1SIM_DEV
+ *
+ * new caseman over elt
+ *
+ * 11 02 2016 ting.xu
+ * [MOLY00208907] [TAS]remove __TAS_MAX_TXPWR_REDUCTION__&modify customer version
+ *
+ * delete marco TAS_MAX_TXPWR_REDUCTION.
+ *
+ * 10 14 2016 ting.xu
+ * [MOLY00203409] [MT6292&6293][TAS2.0]code check in
+ *
+ * align 3GTDSCDMA mt6292 tas2.0.TO mt6293
+ *
+ * 06 28 2016 zheng.zou
+ * [MOLY00179446] TASÇл»µ½ÉÏÌìÏß½µ¹¦ÂÊ
+ * sync TAS patches from UMOLY.
+ *
+ * 06 18 2016 fanzhi.meng
+ * [MOLY00184438] 6293 TL1 CODE MAINTAIN
+ *
+ * tl1 code sync from 93 SIM DEV.
+ *
+ * 06 18 2016 fanzhi.meng
+ * [MOLY00184438] 6293 TL1 CODE MAINTAIN
+ *
+ * tl1 code sync from 93 SIM DEV.
+ *
+ * 01 14 2016 yanhai.xuan
+ * [MOLY00159734] TX power detector support on Jade
+ * .
+ *
+ * 12 22 2015 xuejing.chen
+ * [MOLY00152614] RSSI edBm support on LR11
+ * +ERSSI report value in 1/8 dBm (exclude 4G).
+ *
+ * 12 09 2015 fanzhi.meng
+ * [MOLY00119767] Jade TL1 code maintain
+ *
+ * .
+ *
+ * 11 04 2015 yunlong.li
+ * [MOLY00139750] [MT6755][TDD]
+ * .remove l1core pcore
+ *
+ * 10 22 2015 yunlong.li
+ * [MOLY00139750] [MT6755][TDD]
+ * .add tl1_l1adt_enter_tdd_mode_ind
+ *
+ * 10 18 2015 chuansheng.zhang
+ * [MOLY00145677] [91+][TL1] Platform patch check in
+ * (1) LR11 until patch CL1745309 merge to UMOLY;
+ * (2) 91+ for MIPS: l1core->__SMP_ARCH__ modify, and build error clr;
+ * (3) TL1 IRQ code part modify
+ *
+ * 08 27 2015 yunlong.li
+ * [MOLY00135310] [TK6291][E1EVB] [ADT]add adt feature
+ * Rollback //UMOLY/TRUNK/UMOLY/mcu/common/interface/modem/l1/tdd/tl1_struct.h to revision 20
+ *
+ * 08 24 2015 yunlong.li
+ * [MOLY00135310] [TK6291][E1EVB] [ADT]add adt feature
+ * .fix 6291+ build error
+ *
+ * 08 04 2015 yunlong.li
+ * [MOLY00135310] [TK6291][E1EVB] [ADT]add adt feature
+ * .add adt feature
+ *
+ * 07 28 2015 chuansheng.zhang
+ * [MOLY00132771] [MT6755][TDD3G][SLT] Dev
+ * Jade: TDSCDMA SLT code check in.
+ *
+ * 05 21 2015 yanhai.xuan
+ * [MOLY00115289] [TK6291E1][RMPU][Pre-Sanity][3G][Blocking][TDD] CMCC network 23G DM ×öÊý¾ÝÒµÎñ»á³öÏÖ²»Ã÷ÔÒòËÀ»ú
+ * .
+ *
+ * 05 19 2015 qianli.li
+ * [MOLY00114091] [MT6291][TAS feature] Add TDD_TAS feature
+ * .
+ *
+ * 05 19 2015 qianli.li
+ * [MOLY00114091] [UMOLY][tas feature] TAS for 6291
+ * .
+ *
+ * 04 29 2015 rong.yang
+ * [MOLY00109047] [UMOLY][new feature] Pich false alarm Optimization
+ * .
+ *
+ * 04 27 2015 chengwei.liu
+ * [MOLY00109507] [UMOLY][TDD] [Memory Access Permission] UMAC Share buffer code change check in
+ * .
+ *
+ * 04 19 2015 chuansheng.zhang
+ * [MOLY00097620] [TK6291][UBin] TL1 Platform Patch
+ * fix ubin duplex struct issue.
+ *
+ * 04 17 2015 marco.zhang
+ * [MOLY00096053] [TDD] Rx report for test (need turn on __TDS_RX_TEST_SUPPORT__)
+ * .
+ *
+ * 04 16 2015 chuansheng.zhang
+ * [MOLY00097620] [TK6291][UBin] TL1 Platform Patch
+ * TL1: Ubin Phase2 code merge.
+ *
+ * 02 10 2015 fanzhi.meng
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .code sync
+ *
+ * 01 07 2015 marco.zhang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .
+ *
+ * 01 07 2015 fanzhi.meng
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .
+ *
+ * 01 05 2015 marco.zhang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .
+ *
+ * 01 05 2015 fanzhi.meng
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .
+ *
+ * 12 29 2014 marco.zhang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .
+ *
+ * 12 21 2014 marco.zhang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * prefix.
+ *
+ * 12 11 2014 rong.yang
+ * [MOLY00086950] UMOLY TL1 MAINTAIN
+ * .revise umac part about shared memory on tl1_ps_shared_mem.h/.c
+ *
+ * 12 10 2014 rong.yang
+ * [MOLY00087194] [3G UMAC] merge 6291 code from MOLY.U3G.90IT.DEV
+ * .
+ *
+ * 08 27 2014 marco.zhang
+ * [MOLY00077352] [MT6291]TAS cross core dev
+ * .
+ *
+ * 05 23 2014 xiaoyun.mao
+ * [MOLY00066499] [3G TDD UMAC & L1] DPA & R4 rx memory revise
+ * .rx data path change
+ *
+ * 05 22 2014 shouzhu.zhang
+ * [MOLY00066398] [Known Issue][MT6592TDD][SGLTE][LTTG][KK][Thermal] The tsPA didn't report temperature information in downloading/call (always -127 degreeC)
+ * report thermal.
+ *
+ * 05 13 2014 jt.tan
+ * [MOLY00064338] [MT6592TDD][CSFB][CMCC Case][FT][GZ][Regression 3][5.4.6] Ping suspend time larger than CMCC criteria (20seconds) [FOCUS ISSUE]
+ * patch for CMCC 5.4.6
+ *
+ * 03 11 2014 xiaoyun.mao
+ * [MOLY00059209] [Blocking][Critical][CMCC MTBF][CMCC Case][EE][MT6582QHD512][SGLTE]µÇ½ÓÊÏä²»³É¹¦
+ * .add mac ut struct with meas_occasion_ind
+ *
+ * 03 06 2014 xiaoyun.mao
+ * [MOLY00058570] [MT6290E2][SGLTE][82LTEv2][LT+G][GCF][ETC7310][MM][Band 38][Band A][case 8.4.2.2] fail,Öն˷¢ËÍÁËcell updateµ¼ÖÂÓÃÀýʧ°Ü
+ * .DMO optimization: ul tick tell mac DMO info
+ *
+ * 03 06 2014 xiaoyun.mao
+ * [MOLY00058505] [check in]B3B39 co-existence code
+ * .TL1 check in
+ *
+ * 12 31 2013 shouzhu.zhang
+ * [MOLY00048478] [MT6290E1][LTG][GCF][CMW500][MM][Pre-Test][case 9.2.3.3.4][Band 38] Fail
+ * 4G OOS Measurement change.
+ *
+ * 12 17 2013 shouzhu.zhang
+ * [MOLY00050653] [TL1][Check in]Remove TL1 MCU needless compile option
+ * .
+ *
+ * 10 18 2013 hongwei.zhang
+ * [MOLY00042501] [TDD][MMDC EM Dev]SINR & SupportBand Info
+ * MMDC EM Dev: Report SINR Info to Uplayer.
+ *
+ * 09 18 2013 ast00029
+ * [MOLY00032095] [3G TDD][RxCFN] Activation time and RRC message RX CFN record
+ * for cr:MOLY00032095,Record this situation: Calculate active_sfn with current_cfn and last rx_cfn, if the result is different, trace it.
+ *
+ * 08 19 2013 shouzhu.zhang
+ * [MOLY00031436] [FDD2TDD][MT6290E1][NAS RTD][MM][FDD] Could not receive SIB-3 so 4G3 evaluation fails
+ * Report bch ind with standby no gap when no gap to rx bch.
+ *
+ * 08 09 2013 fanzhi.meng
+ * [MOLY00033092] MT6592/MT6290 MCU code update
+ * .add dsp changelist trace
+ *
+ * 08 02 2013 ast00029
+ * [MOLY00032095] [3G TDD][RxCFN] Activation time and RRC message RX CFN record
+ * for cr:MOLY00032095,Record this situation: Calculate active_sfn with current_cfn and last rx_cfn, if the result is different, trace the it.
+ *
+ * 08 02 2013 ast00029
+ * [MOLY00032095] [3G TDD][RxCFN] Activation time and RRC message RX CFN record
+ * for cr:MOLY00032095,Record this situation: Calculate active_sfn with current_cfn and last rx_cfn, if the result is different, trace the it.
+ *
+ *
+ * 08 02 2013 ast00029
+ * [MOLY00032095][3G TDD][RxCFN] Activation time and RRC message RX CFN record
+ * Record this situation: Calculate active_sfn with current_cfn and last rx_cfn, if the result is different, trace the it.
+ *
+ * 07 23 2013 shouzhu.zhang
+ * [MOLY00023935] [MT6290E1][W/G][Target IT] Meas result is received so frequently when priority measurement and drx measurement are on-going
+ * MEME control trigger short period measurement immediatly or not.
+ *
+ * 05 30 2013 ast00033
+ * [MOLY00024285] [MT6572][CMCC Case FT][LCA_GEMINI][Beijing][Regression-7th time][C6.3 ¿¨²Û1Ë«PDPºÍ¿¨²Û2ÓïÒô²¢·¢ ]8th_11:38:34_ÔÝʱÎÞ·¨½Óͨ_ÈýÔªÎ÷ÇÅ
+ * .
+ *
+ * 05 15 2013 xiaoyun.mao
+ * [MOLY00007737] [WR8][UMAC]3G speech UL delay improve phase 2
+ * .remove __PREPARE_TX_AHEAD__
+ *
+ * 04 17 2013 shouzhu.zhang
+ * [MOLY00013948] [MT6290 PO admit] Check in AST3002 & protocol code for 6290 MULTI_MODE_TDS project
+ * add auto gap interface.
+ *
+ * 04 01 2013 shouzhu.zhang
+ * [MOLY00013249] MM TL1 Code check in
+ * [TL1] Merge lastes WR8 + R9 + MM code to MOLY..
+ *
+ * 03 01 2013 shun.liu
+ * [MOLY00011182] MT6572/6582: RF TX test feature check in MOLY main
+ * EM tx test tl1 part.
+ *
+ * 12 07 2012 xiaoyun.mao
+ * [MOLY00007252] [MOLY][UMAC]fixing build error
+ * add parameter of ul_inform_MAC
+ *
+ * 11 02 2012 shouzhu.zhang
+ * [MOLY00005657] Thermal function implementation
+ * .
+ *
+ * 10 12 2012 jingjing.ma
+ * [MOLY00004752] add new variable
+ * remove option for islongperiodin3gstandby.
+ *
+ * 10 10 2012 shouzhu.zhang
+ *
+ * [MOLY00004236] [interface][service][kal]remove stack_ltlcom.h
+ * <saved by Perforce>
+ *
+ * 09 26 2012 xiaoyun.mao
+ * [MOLY00004157] [TDD_R9_DEV]change of interface with MEME
+ * .
+ *
+ * 09 24 2012 xiaoyun.mao
+ * [MOLY00004069] [MOLY]TDD_R9_DEV Patch back to MOLY
+ * TDD_R9_DEV patch back to MOLY
+ *
+ * 09 12 2012 xiaoyun.mao
+ * [MOLY00002766] rremove __UMAC_DCH_LISR__
+ *
+ * 09 11 2012 xiaoyun.mao
+ * [MOLY00002766] warning removal
+ * .
+ * remove __UMAC_DCH_LISR__
+ *
+ * 09 11 2012 willie.pan
+ * [MOLY00000302] [TST] MOLY Branch check-in
+ * Rollback //MOLY/TRUNK/MOLY/mcu/interface/modem/tl1interface/tl1_struct.h to revision 2
+ *
+ * 08 06 2012 riley.ou
+ * [MOLY00001452] CTCH L2 schedule improvement
+ * .
+ *
+ * 05 03 2012 wcpuser_integrator
+ * removed!
+ * .
+ *
+ * 05 03 2012 wcpuser_integrator
+ * removed!
+ * .
+ *
+ * 03 21 2012 shuyang.yin
+ * removed!
+ * .
+ *
+ * 03 02 2012 shuyang.yin
+ * removed!
+ * .
+ * (TL1 SAP)
+ *
+ * 02 28 2012 shuyang.yin
+ * removed!
+ * .
+ *
+ * 12 06 2011 shuyang.yin
+ * removed!
+ * .
+ *
+ * 11 14 2011 shi.dong
+ * removed!
+ * TL1 code interface fta merge in MAUI.
+ *
+ * 09 13 2011 shuyang.yin
+ * removed!
+ * .
+ *
+ * 09 07 2011 shuyang.yin
+ *
+ * removed!
+ * <saved by Perforce>
+ *
+ * 07 21 2011 qing.zhang
+ * removed!
+ * Update SAP according to UMAC requirement
+ *
+ * 06 13 2011 popcafa.shih
+ * removed!
+ * Help vendor_ast to merge PS_RESTRUCT_DEV
+ *
+ * 04 20 2011 xinqiu.wang
+ * removed!
+ * Modify some description.
+ *
+ * 04 19 2011 xinqiu.wang
+ * removed!
+ * merge code from daily LOAD to MAUI 10A.
+ *
+ * 04 19 2011 xinqiu.wang
+ * removed!
+ * Remove LOCAL_PARA_HDR define.
+ *
+ * 01 18 2011 xinqiu.wang
+ * removed!
+ * Add RHR feature to tl1 interface files.
+ *
+ * 12 28 2010 bo.lu
+ * removed!
+ * .
+ *
+ * 12 14 2010 xinqiu.wang
+ * removed!
+ * Modify the struct of phy_post_tx_ind.
+ *
+ * 12 01 2010 popcafa.shih
+ * removed!
+ * .
+ *
+ * 11 29 2010 xinqiu.wang
+ * removed!
+ * Modify the description of umts_power_class.
+ *
+ * 11 04 2010 xinqiu.wang
+ * removed!
+ * 1. Add ul_mac_event to cphy_dch_setup/modify/release_req
+ * 2. Add two ticks and structs for mac-tl1 interface.
+ * 3. Add two simulation structs according to MAC's requeset.
+ *
+ * 11 03 2010 xinqiu.wang
+ * removed!
+ * 1.SLCE-TL1 SAP Modify for R7
+ * 2. MAC-TL1 SAP Modify for UPA
+ *
+ * 08 24 2010 popcafa.shih
+ * removed!
+ * .
+ *
+ * removed!
+ * removed!
+ * Add tx_enable in phy_simulate_dch_ul_cctrch_hisr_rsp_struct according to the discussion result with UMAC
+ *
+ * removed!
+ * removed!
+ * 1.Add tx_enable in ul_dpch_cctrch_task(), ul_dpch_cctrch_HISR(), phy_simulate_dch_ul_cctrch_task_struct and phy_simulate_dch_ul_cctrch_hisr_struct
+ * 2.Add access_type in phy_access_ind_struct with HSUPA compile option
+ *
+ * removed!
+ * removed!
+ * Modify dpch_SIR_lta to dpdch_SIR_lta in L1_info_struct
+ *
+ * removed!
+ * removed!
+ * 1.In tl1_info, modify the struct name of tl1_speech_info_T to L1_info_struct to use the same interface to FDD according to l1audio team¡¯s requirement.
+ * 2.In L1_info_struct, modify the parameter name and type to use the same interface to FDD according to l1audio team¡¯s requirement.
+ *
+ * removed!
+ * removed!
+ * 1.Add rssi and rscp in PHY_BCH_DATA_IND, and add comments of the parameters in PHY_BCH_DATA_IND
+ * 2.Add PHY_END_EDCH_TX_IND
+ * 3.Modify comments of sfn in phy_dch_setup_ind_struct, phy_dch_release_ind_struct
+ * 4.Modify the comments of TL1_GetCurrentTime.
+ *
+ * removed!
+ * removed!
+ * 1.Add cphy_hsdsch_setup/modify/release_req and cphy_edch_setup/modify/release_req into local_para_unpack_T
+ * 2.Add midamble_shift_detection_result, max_value_of_midamble_correlation_result and noise_of_midamble_correlation_result in tl1_speech_info_struct_T
+ * 3.seperate rscp to dpch_rscp and pccpch_rscp in tl1_speech_info_struct_T
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ * 1.Add type definition of cphy_edch_setup/modify/release_req_struct.
+ * 2.Delete meas_control and idx_intra_freq in cphy_msg_container_req_struct and cphy_msg_container_req_unpack_struct
+ * 3.Add access_type in tdd_phy_rach_data_req_struct and tdd_phy_access_req_struct
+ * 4.Add HSDPA and HSUPA related callback function declaration
+ *
+ * removed!
+ * removed!
+ * 1.Delete pre-declare check of __UMTS_TDD128_MODE__
+ *
+ * removed!
+ * removed!
+ * 1.add check of __UMTS_TDD128_MODE__
+ * 2.delete the parameter of act_time in cphy_bch_setup/modify_req
+ * 3.delete strcut of cphy_measurement_config_fmo_req_struct
+ * 4.Use TL1 to replace UL1 and L1 in comments
+ * 5.Modify comments of mac_event in cphy_hsdsch_setup/modify/release_req to sync with TL1 SAP doc
+ * 6.add comments of cfn in phy_end_dch_tx_ind_struct
+ * 7.Modify type of sub_cfn in phy_hsdsch_data_ind_struct from kal_uint8 to kal_uint16, and modify type of mac_hs_reset in phy_hsdsch_data_ind_struct from kal_uint8 to kal_bool
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ * Add meas_id in cphy_measurement_internal_result_ind according to discussion conclusion with MEME module owner
+ *
+ * removed!
+ * removed!
+ * Modify type of event_id in CPHY_MEASUREMENT_INTERNAL_EVENT_IND from kal_uint8 to internal_meas_event_E
+ *
+ * removed!
+ * removed!
+ * 1 rename "dpdch_SIR_lta" in phy_data_ind_struct to "dpch_SIR_lta"
+ *
+ * removed!
+ * removed!
+ * 1. change the type of sib7_factor from "kal_int8" to "kal_uint8" to compiance with SLCE
+ * 2. add h_msg and e_msg for DPA and UPA
+ * 3. change the type of off in cphy_sfn_ind_struct from kal_uint16 to kal_int16
+ *
+ * removed!
+ * removed!
+ * remove typo error "ul1_def"
+ *
+ * removed!
+ * removed!
+ * modify phy_data_ind_struct for UT test
+ *
+ * removed!
+ * removed!
+ * Rename __UMTS_TDD128_RAT__ to __UMTS_TDD128_MODE__
+ *
+ * removed!
+ * removed!
+ * add log section for tl1interface header files
+ *
+*******************************************************************************/
+
+
+#ifndef _TL1_STRUCT_H
+#define _TL1_STRUCT_H
+
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "tl1_def.h"
+#include "global_type.h" /* [UBin] For inclusion of erac_rat_enum */
+#if (!defined(TL1_SIM))
+#include "rsvak_public_enum.h"
+#endif
+#ifdef __ATERFTX_ERROR_HANDLE_ENHANCE__
+#include "ps_public_enum.h"
+#endif
+/*****************************************************************************
+Request from SLCE/MEME to TL1
+*****************************************************************************/
+
+/*bch*/
+typedef struct _TDD_cphy_bch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 rx_sfn; /*[Range]: (-1~4095). (0-4095) for frame number type, and "-1" for immediate type.
+ [Meaning]: This is the SFN to start to setup BCH channel, and receive SIB */
+ kal_int32 tm; /*[Range]: -1 ~ (6400*8-1). -1 for unknown timing.
+ [Meaning]:Sub Frame boundary offset between target cell and LST
+ For a cell with unknown tm value, it can not be issued to TL1. */
+ kal_int16 off; /*[Range]: -1~8191, (0-8191) for a cell whose Sub SFN offset to LST has been measured by TL1. -1 means off unknown.
+ [Meaning]: Sub frame number offset between target cell and LST.
+ For a cell with unknown off value, it can not be issued to TL1. */
+ kal_bool sfn_only; /*True/False. True: The BCH setup request is only for the SFN reading,
+ and TL1 will only send CPHY_SFN_IND to RRC,
+ False: The BCH setup request is for the BCH data reading.*/
+ kal_uint16 uarfcn; /*uarfcn*/
+ kal_uint16 cell_param_id; /*[Range]: 0-127, TDD_CPID_INVALID
+ [Meaning]:Cell parameter ID*/
+ kal_bool sctd; /*True: sctd is applied on this cell's P-CCPCH.
+ False: sctd is not applied on this cell's P-CCPCH.*/
+ kal_bool tstd; /*True: tstd is applied on this cell's P-CCPCH.
+ False: tstd is not applied on this cell's P-CCPCH.*/
+ kal_int8 sib7_index; /*[Range]: -1 ~ (sibnum-1)
+ [Meaning]: Indicate which SIB Info in sib_list[] is SIB7,-1 means there is no SIB7 in the list*/
+ kal_uint16 sib7_rep_cycle; /* 2~256 .The meaning of sib7_rp_cycle becomes "SIB7 expiration timer/ SIB_REP" */
+
+ TDD_bch_priority_T bch_priority; /*Enum:TDD_BCH_PRIOHIGH,TDD_BCH_PRIOMEDIUM(not used in TDD18), TDD_BCH_PRIOLOW */
+ kal_uint8 sib_num; /*[Range]: 0~ TDD_MAX_SIB_PATTERN.
+ [Meaning]: the number of sib in sib list.
+ 0 means all SIBs reception.0 is not used in current implementation.*/
+ TDD_sib_info_T sib_list[TDD_MAX_SIB_PATTERN]; /*SIB information*/
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ kal_uint16 priority_index; /*Priority_index for same priority channel in 3G Gemini project*/
+#endif
+ kal_bool is_auto_gap_support; /*This BCH req is for report CGI*/
+
+} tdd_cphy_bch_setup_req_struct;
+
+typedef struct _TDD_cphy_bch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 rx_sfn; /*[Range]: (-1~4095). (0-4095) for frame number type, and "-1" for immediate type.
+ [Meaning]: This is the SFN to start to setup BCH channel, and receive SIB */
+ kal_uint8 modify_flag; /*A flag to indicate the field to be modified.
+ 0x01 "bch_priority" is changed
+ 0x02: "sib_num", "sib_list", sib7_index, sib7_factor are changed.
+ 0x03: both above item are changed*/
+ kal_int8 sib7_index; /*[Range]: -1 ~ (sibnum-1)
+ [Meaning]: Indicate which SIB Info in sib_list[] is SIB7,-1 means there is no SIB7 in the list*/
+ kal_uint16 sib7_rep_cycle; /* 2~256 .The meaning of sib7_rp_cycle becomes "SIB7 expiration timer/ SIB_REP" */
+
+ TDD_bch_priority_T bch_priority; /*Enum:TDD_BCH_PRIOHIGH,TDD_BCH_PRIOMEDIUM(not used in TDD18), TDD_BCH_PRIOLOW */
+ kal_uint8 sib_num; /*[Range]: 0~ TDD_MAX_SIB_PATTERN.
+ [Meaning]: the number of sib in sib list.
+ 0 means all SIBs reception.0 is not used in current implementation.*/
+ TDD_sib_info_T sib_list[TDD_MAX_SIB_PATTERN]; /*SIB information*/
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ TDD_uas_gemini_conflict_cause_enum conflict_cause; /*Channel conflict casue with peer channel*/
+ kal_uint16 priority_index; /*Priority_index for same priority channel in 3G Gemini project*/
+#endif
+} tdd_cphy_bch_modify_req_struct;
+
+
+typedef struct _TDD_cphy_bch_release_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_bch_release_req_struct;
+
+
+/*pch*/
+typedef struct _TDD_cphy_pch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ kal_uint16 uarfcn; /*uarfcn*/
+ kal_int32 tm; /*[Range]: -1 ~ (6400*8-1). -1 for unknown timing.
+ [Meaning]:Sub Frame boundary offset between target cell and LST
+ For a cell with unknown tm value, it can not be issued to TL1. */
+ kal_int16 off; /*[Range]: -1~8191, (0-8191) for a cell whose Sub SFN offset to LST has been measured by TL1. -1 means off unknown.
+ [Meaning]: Sub frame number offset between target cell and LST.
+ For a cell with unknown off value, it can not be issued to TL1. */
+ TDD_fach_pch_info_T fach_pch_info; /*FACH/PCH channel information*/
+} tdd_cphy_pch_setup_req_struct;
+
+typedef struct _TDD_cphy_pch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ TDD_pich_drx_T pich_drx; /*new drx info of PCH/PICH*/
+
+ TDD_pich_reconfig_type_E reconfig_type;
+ TDD_pich_smartpaging_T smartpaging_info;
+} tdd_cphy_pch_modify_req_struct;
+
+typedef struct _TDD_cphy_pch_release_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+} tdd_cphy_pch_release_req_struct;
+
+
+/*fach*/
+typedef struct _TDD_cphy_fach_setup_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ kal_uint16 uarfcn; /*uarfcn*/
+ kal_int32 tm; /*[Range]: -1 ~ (6400*8-1). -1 for unknown timing.
+ [Meaning]:Sub Frame boundary offset between target cell and LST
+ For a cell with unknown tm value, it can not be issued to TL1. */
+ kal_int16 off; /*[Range]: -1~8191, (0-8191) for a cell whose Sub SFN offset to LST has been measured by TL1. -1 means off unknown.
+ [Meaning]: Sub frame number offset between target cell and LST.
+ For a cell with unknown off value, it can not be issued to TL1. */
+ TDD_fach_pch_info_T fach_pch_info; /*FACH/PCH channel information*/
+} tdd_cphy_fach_setup_req_struct;
+
+typedef struct _TDD_cphy_fach_release_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+} tdd_cphy_fach_release_req_struct;
+
+
+/*rach*/
+typedef struct _TDD_cphy_rach_setup_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ TDD_random_access_info_T prach_info; /*prach related info for this UE*/
+ TDD_ul_rach_trch_T trch_list[1]; /*SLCE will select one rach trch for TL1*/
+} tdd_cphy_rach_setup_req_struct;
+
+typedef struct _TDD_cphy_rach_release_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+} tdd_cphy_rach_release_req_struct;
+
+
+/*dch*/
+typedef struct _TDD_cphy_dch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /*(-1~255). (0~255) for CFN type, "-1" for immediate type.*/
+ TDD_dch_setup_msg_type_E setup_type; /*DCH setup type,setup,HHO,baton HO,revert,etc.*/
+
+ kal_bool is_ul_dch_setup; /*Indicate whether UL dch will be set up. */
+ kal_bool is_dl_dch_setup; /*Indicate whether DL dch will be set up.
+ Before R8£¬ this field should always be set to KAL_TRUE*/
+ kal_int16 rscp; /* -500 ~ -100 means (-125 ~ -25 )dBm in 0.25 dB step,serving cell rscp*/
+ kal_uint8 tid; /*Transaction id*/
+ kal_uint8 dl_crc_ind; /* For those TrCHs whose CRC data should be sent to MAC,
+ their corresponding bit will be set to 1.
+ The MSB represents the lowest numbered TrCH ID.*/
+ kal_uint16 prim_uarfcn; /*Primary uarfcn of the cell*/
+ kal_uint16 work_uarfcn; /*Working uarfcn of the UE */
+ kal_uint16 ul_tfc_num; /*Number of TFC for UL DPCH*/
+ TDD_ul_dpch_tfc_T ul_tfcs[TDD_MAX_UL_TFC]; /*ul TFCS*/
+ kal_uint8 ul_trch_num; /*Number of UL TrCH*/
+ TDD_ul_dch_trch_T ul_trch_list[TDD_MAX_UL_TRCH]; /*UL TrCH Info*/
+ TDD_ul_dpch_info_T ul_dpch_info; /*UL DPCH info*/
+ kal_uint16 dl_tfc_num; /*Number of DL TFCS*/
+ TDD_dl_tfc_T dl_tfcs[TDD_MAX_DL_TFC]; /*DL TFCS*/
+ kal_uint8 dl_trch_num; /*Number of DL TrCH*/
+ TDD_dl_dch_trch_T dl_trch_list[TDD_MAX_DL_TRCH]; /*DL Trch Info*/
+ kal_int8 max_tx_power; /*50 ~ 33 dBm,Max. allowed TX power. */
+ kal_int8 umts_power_class; /*UE capability(in dBm)*/
+ TDD_dl_dpch_rla_T dl_dpch_rla; /*DL Info & DL DPCH Info common for all RLs*/
+ TDD_dl_dpch_rl_T dl_dpch_rl[TDD_MAX_RL]; /*DL Info & DL DPCH Info. for each RL*/
+ TDD_dl_establish_T dl_establish_info; /*DL DPCH establishment criterion*/
+ kal_uint8 sbgp; /*Value represents number of radio frames
+ 0 = 2 frames, 1 = 4 frames,
+ 2 = 8 frames, 3 = 16 frames,
+ 4 = 32 frames, 5 = 64 frames,
+ 6 = 128 frames, 7 =256 frames.*/
+ TDD_random_access_info_T ul_sync; /*UL sync parameter for enter DCH to another cell, handover or handover revert.*/
+ kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event
+ Bit 0 : Setup; Bit 1 : Release ; Bit 2 : Modify
+ And in this primitive, only Bit 0 can be set to 1*/
+}tdd_cphy_dch_setup_req_struct;
+
+typedef struct _TDD_cphy_dch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /*(-1~255). (0~255) for CFN type, "-1" for immediate type.*/
+ kal_uint16 work_uarfcn; /*Working uarfcn of the cell */
+ TDD_dch_modify_msg_type_E modify_type; /*Enums:TDD_DCH_RECONFIG,TDD_DCH_LOOP_MODE_2*/
+ kal_uint8 tid; /*Transaction id*/
+ TDD_ul_dpch_reconfig_type_E ul_dpch_reconfig_type ;/* 0: Do nothing with ul dpch.
+ 1: Setup ul dpch.
+ 2: modify ul dpch
+ 3.Release ul dpch*/
+
+ TDD_dl_dpch_reconfig_type_E dl_dpch_reconfig_type ;/* 0: Do nothing with dl dpch.
+ 1: Setup dl dpch.
+ 2: modify dl dpch
+ 3.Release dl dpch*/
+
+ kal_bool ul_mod_ind; /*Indicate whether UL modify indication should be sent to MAC*/
+ kal_bool dl_mod_ind; /*Indicate whether DL modify indication should be sent to MAC*/
+ kal_uint8 dl_crc_ind; /*For those TrCHs whose CRC data should be sent to MAC.
+ their corresponding bit will be set to 1.
+ The MSB represents the lowest numbered TrCH ID.*/
+ kal_uint16 modify_field; /*Bit field to represent for the parameters that should be modified
+ Bit0: DL TrCH parameter
+ Bit1: DL TFCS parameter
+ Bit2: UL TrCH parameter
+ Bit3: UL TFCS parameter
+ Bit4: downlink common RL parameters
+ Bit5: downlink each RL parameters.
+ Bit 6 : UL RL parameter
+ Bit 7 : Physical parameters such as working_uarfcn
+ Bit8: dl_establish_info
+ Bit9: SBGP
+ Bit10: uplink power control related parameters, such as max _tx_power, umts_power_class. */
+ kal_uint16 ul_tfc_num; /*Number of TFC for UL DPCH*/
+ TDD_ul_dpch_tfc_T ul_tfcs[TDD_MAX_UL_TFC]; /*ul TFCS*/
+ kal_uint8 ul_trch_num; /*Number of UL TrCH*/
+ TDD_ul_dch_trch_T ul_trch_list[TDD_MAX_UL_TRCH];/*UL TrCH Info*/
+ kal_uint16 dl_tfc_num; /*Number of DL TFCS*/
+ TDD_dl_tfc_T dl_tfcs[TDD_MAX_DL_TFC]; /*DL TFCS*/
+ kal_uint8 dl_trch_num; /*Number of DL TrCH*/
+ TDD_dl_dch_trch_T dl_trch_list[TDD_MAX_DL_TRCH];/*DL Trch Info*/
+ TDD_dl_dpch_rla_T dl_dpch_rla; /*DL Info & DL DPCH Info common for all RLs*/
+ TDD_ul_dpch_info_T ul_dpch_info; /*UL DPCH info*/
+ kal_int8 max_tx_power; /*50 ~ 33 dBm,Max. allowed TX power. */
+ kal_int8 umts_power_class; /*UE capability(in dBm)*/
+ TDD_dl_dpch_rl_T dl_dpch_rl[TDD_MAX_RL]; /*DL Info & DL DPCH Info. for each RL*/
+ TDD_dl_establish_T dl_establish_info; /*DL DPCH establishment criterion*/
+ kal_uint8 sbgp; /*Value represents number of radio frames
+ 0 = 2 frames, 1 = 4 frames,
+ 2 = 8 frames, 3 = 16 frames,
+ 4 = 32 frames, 5 = 64 frames,
+ 6 = 128 frames, 7 =256 frames.*/
+ kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event
+ Bit 0 : Setup; Bit 1 : Release ; Bit 2 : Modify
+ And in this primitive, only Bit 2 can be set to 1*/
+}tdd_cphy_dch_modify_req_struct;
+
+typedef struct _TDD_cphy_dch_release_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /*(-1~255). (0~255) for CFN type, "-1" for immediate type.*/
+ kal_bool isStopLoopTestM2First; /*TRUE: Stop Loop Mode 2 before releasing DCH.*/
+ kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event
+ Bit 0 : Setup; Bit 1 : Release ; Bit 2 : Modify
+ And in this primitive, only Bit 1 can be set to 1*/
+} tdd_cphy_dch_release_req_struct;
+
+
+/*fs*/
+typedef struct _TDD_cphy_frequency_scan_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 max_num_cell; /*Maximum number of cells reported in 1 frequency during scan.
+ MIN(max_num_cell, num_found_cell) cells to MEME
+ it shall halt the frequency scan procedure.*/
+ kal_uint16 timeout; /*Maximum time spent to do cell search on 1 frequency.
+ If TL1 has spent so much time to do cell search on 1 frequency,
+ it will send an indication to MEME and halt the frequency scan procedure.
+ [Unit]: ms.*/
+ kal_uint8 num_freq_range; /*Number of range list*/
+ kal_uint16 uarfcn_begin[TDD_MAX_FREQ_RANGE]; /*Begin of UARFCN for range cell search*/
+ kal_uint16 uarfcn_end[TDD_MAX_FREQ_RANGE]; /*End of UARFCN for range cell search */
+ kal_uint8 num_freq_list; /*Number of freq for preferred freq list */
+ kal_uint16 uarfcn_list[TDD_MAX_FREQ_LIST]; /*List of UARFCN */
+ kal_uint8 num_preferred_cell; /*Number of preferred cells. */
+ TDD_preferred_cell_list_T preferred_cell_list[TDD_MAX_PREFERRED_CELL]; /*Preferred cell list. */
+ kal_bool full_band_search; /*True/False. True: Perform full band scan. */
+ kal_bool freq_correct; /*True/False. True: TL1 need to do frequency correction. */
+ kal_bool resume; /*True/False. True:TL1 should resume previous freq scan,
+ TL1 didn't care the other fields in this msg,
+ False: TL1 should start a new freq scan according to this msg */
+ TDD_full_band_option_E full_band_option; /*- TDD_FULL_BAND_ONLY: Normal full band FS
+ - TDD_FULL_BAND_AND_EXCLUDE: Full band FS but the indicated frequency list/range will be excluded */
+ #if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+#if (!defined(TL1_SIM))
+ freq_scan_type_enum freq_scan_type;
+#else
+ kal_uint16 priority_index;
+#endif
+ #endif
+ #ifdef __GEMINI__
+ kal_uint8 priority_level; /*[Range: 0-2] Indicate which gap pattern shoud be used for this freq scan in Virtual mode*/
+ /*0=highest priority; 1=2nd priority; 2=lowest priority*/
+ #endif
+ kal_bool is_auto_gap_support; /*This FS req is for report CGI*/
+#if defined(__LTE_RAT__) && defined (__UMTS_TDD128_MODE__)
+ kal_bool trigger_by_4g_plmn_loss;
+#endif
+/*Yajiang 20150114 :add for TL1 to differ manual plmn search or autonmous*/
+ kal_bool is_plmn_list;
+} tdd_cphy_frequency_scan_req_struct;
+
+typedef struct _TDD_cphy_frequency_scan_suspend_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_frequency_scan_suspend_req_struct;
+
+
+typedef struct _TDD_cphy_frequency_scan_continue_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool continue_cell; /*True if MEME want TL1 to do continue cell search on current frequency
+ instead of jumping to next specified frequency. */
+} tdd_cphy_frequency_scan_continue_req_struct;
+
+
+/*meas*/
+typedef struct _TDD_cphy_measurement_config_cell_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tid; /*Transaction ID to sync between request and indication*/
+ TDD_meas_act_E action; /*[Range]: TDD_STOP_MEAS,
+ TDD_START_MEAS_NEW_CIL,
+ TDD_START_MEAS_NEW_CIL_NEW_FMO*/
+ kal_bool ds_meas; /*True: Indicate that TL1 shall make detected cell measure.*/
+ kal_uint16 intra_uarfcn; /*Intra-frequency uarfcn, TL1 has knowledge about intra_uarfcn,
+ just double check the value. MEME shall send the primitive after
+ channel enters stable state to guarantee the value is the same
+ with TL1. But it is possible different with TL1 when channel transition.*/
+ kal_uint8 num_cell; /*[Range]:0-64,[Meaning]: Number of cells in the following
+ cell_info_list[]. Must be greater than 0 if bit1 of 'action' is set.*/
+ TDD_cell_info_list_T cell_info_list[TDD_MAX_NUM_MEASURED_CELL]; /*List of all monitor cells to be measured indicated by network. It
+ is ascending sort by cell's uarfcn and cell_param_id. Cells on the
+ same frequency will be collected together. The cells on different
+ frequencies will not be interleaved.*/
+ TDD_fach_mo_info_T fach_mo_info; /*The structure is used to express the FACH measurement occasion
+ parameters. It is valid when bit2 of 'action' is set*/
+ kal_bool intra_rscp_meas_period_valid; /*Configure Intra-freq. RSCP meas. period in DCH/FACH.*/
+ kal_uint8 intra_rscp_period_N; /*Num. of 50/40 ms.*/
+ kal_bool inter_rscp_meas_period_valid; /*Configure Inter-freq. RSCP meas. period in DCH/FACH*/
+ kal_uint8 inter_rscp_period_N; /*Num. of 50/40 ms.*/
+ kal_bool intra_iscp_meas_period_valid; /*Configure Intra-freq. ISCP meas. period in DCH/FACH.*/
+ kal_uint8 intra_iscp_period_N; /*Num. of 50/40 ms.*/
+//#ifdef __UMTS_R9__
+ kal_int16 T_higher_prio_search; /*Higher priority search period (s) when use priority based cell reselection, -1 means use regular period.*/
+ kal_bool is_meas_period_reset_standby;
+ kal_bool prohibit_apply_n_layer_standby; /* [R8][MM] Due to 4G OOS, MEME notifies TL1 not to apply n_layer factor to accelerate meas frequency */
+
+//#endif
+} tdd_cphy_measurement_config_cell_req_struct;
+
+
+#ifdef __TAS_SUPPORT__
+typedef struct _TDD_cphy_tas_custom_config_param_T
+{
+ kal_uint16 tas_ver;
+ kal_uint16 tas_state_number;
+ kal_uint16 is_test_sim;
+ kal_uint16 tas_enable_flag; //1/0: enable/disable TAS
+
+ kal_uint16 tas_ics_init_state; //reserve for future or align 32bit
+ kal_uint16 tas_force_ant_enable;
+ kal_uint16 tas_force_ant_state;
+ kal_uint16 tas_force_tx_band_state;
+ kal_uint16 tas_real_sim_enable; //1/0: enable/disable realSIM
+
+ kal_uint16 tas_test_sim_enable; //1/0: enable/disable testSIM
+ kal_uint16 tds_with_b34_real_sim_tas_status; //1/0: enable/disable realSIM
+ kal_uint16 tds_with_b34_real_sim_init_state; //ant state realSIM
+ kal_uint16 tds_with_b39_real_sim_tas_status; //1/0: enable/disable realSIM
+
+ kal_uint16 tds_with_b39_real_sim_init_state; //ant state realSIM
+ kal_uint16 tds_with_b34_test_sim_tas_status; //1/0: enable/disable testSIM
+ kal_uint16 tds_with_b34_test_sim_init_state; //ant state testSIM
+ kal_uint16 tds_with_b39_test_sim_tas_status; //1/0: enable/disable testSIM
+
+ kal_uint16 tds_with_b39_test_sim_init_state; //ant state testSIM
+ kal_uint16 reserve;
+}tdd_cphy_tas_custom_config_param_T;
+
+typedef struct _TDD_cphy_tas_algorithm_param_T
+{
+ //TAS period
+ kal_int16 period_N;//TAS period in connected mode,DCH n*200ms,default=1;
+ kal_int16 drx_period_N;//TAS period in DRX: drx_period_n * drx;
+
+ //TAS antenna offset
+#if defined(__MD95__) || defined(__MD97__)
+ kal_int16 diff_ant_oft_utas[8];
+#else
+ kal_int16 diff_ant_oft0;
+ kal_int16 diff_ant_oft1;
+ kal_int16 diff_ant_oft2;
+ kal_int16 diff_ant_oft3;
+#endif
+ kal_int16 diff_htp;
+ kal_int16 htp_oft;
+ kal_int16 max_htp_tx_pwr;
+ kal_int16 threshold_htp;
+#if defined(__MD95__) || defined(__MD97__)
+ kal_int16 diff_drx_ant_oft_utas[8];
+#else
+ kal_int16 diff_drx_ant_oft0;
+ kal_int16 diff_drx_ant_oft1;
+ kal_int16 diff_drx_ant_oft2;
+ kal_int16 diff_drx_ant_oft3;
+#endif
+
+ //TAS threshold
+ kal_int16 threshold_diff_rscp;
+ kal_int16 threshold_diff_snr;
+ kal_int16 snr_good;
+
+ kal_int16 threshold_drx_diff_rscp;
+ kal_int16 threshold_drx_diff_snr;
+ kal_int16 drx_snr_good;
+
+ kal_int16 threshold_drx_rscp_low;
+ kal_int16 threshold_drx_snr_low;
+
+ //TAS fall back algorithm
+ kal_int16 diff_fall_back;
+ kal_int16 diff_drx_fall_back;
+
+ kal_int16 diff_htp_backup_n;
+ kal_int16 htp_oft_backup_n;
+ kal_int16 threshold_diff_rscp_backup_n;
+ kal_int16 tds_tp_oft_backup_n;
+
+ //TAS SAR new fall back algorithm param
+#if defined(__MD95__) || defined(__MD97__)
+ kal_int16 tds_sar_ant_oft_utas[8];
+#else
+ kal_int16 tds_sar_ant_oft0;
+ kal_int16 tds_sar_ant_oft1;
+ kal_int16 tds_sar_ant_oft2;
+ kal_int16 tds_sar_ant_oft3;
+#endif
+ kal_int16 tds_sar_diff_htp;
+ kal_int16 tds_sar_htp_oft;
+
+ kal_int16 tds_sar_threshold_diff_rscp;
+ kal_int16 tds_sar_tp_oft;
+
+ kal_int16 tds_sar_reserve1;
+ kal_int16 tds_sar_reserve2;
+}tdd_cphy_tas_algorithm_param_T;
+#endif
+
+/*specific cell search*/
+typedef struct _TDD_cphy_specific_cell_search_req_struct /*RRCE->TL1*/
+{
+ LOCAL_PARA_HDR
+ kal_uint16 uarfcn; /*uarfcn*/
+ kal_uint16 cell_param_id; /*[Range]: 0-127 [Meaning]:Cell parameter ID*/
+ kal_bool sctd; /*True/False. True: sctd is applied on this cell's P-CCPCH.
+ False: sctd is not applied on this cell's P-CCPCH.*/
+ kal_bool tstd; /*True/False. True: tstd is applied on this cell's P-CCPCH.
+ False: tstd is not applied on this cell's P-CCPCH.*/
+} tdd_cphy_specific_cell_search_req_struct;
+
+typedef struct _TDD_cphy_specific_cell_search_stop_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_specific_cell_search_stop_req_struct;
+
+/*reset and set rat*/
+typedef struct _TDD_cphy_reset_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_reset_req_struct;
+
+typedef struct _TDD_cphy_rf_on_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 working_UMTS_band[2];
+} tdd_cphy_rf_on_req_struct;
+
+typedef struct _TDD_cphy_rf_off_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_rf_off_req_struct;
+
+typedef struct _TDD_cphy_set_active_rat_req_struct
+{
+ LOCAL_PARA_HDR
+ TDD_mode_type_E mode; /* Curernt mode setting (Single, Dual) */
+ TDD_rat_type_E rat; /* Current active RAT setting (Flight, UMTS, GSM) */
+ erac_rat_enum full_rat_info; /* Full RAT info */
+} tdd_cphy_set_active_rat_req_struct;
+
+/*internal meas*/
+typedef struct _TDD_cphy_measurement_internal_config_req_struct /*MEME->TL1*/
+{
+ LOCAL_PARA_HDR
+ kal_uint8 meas_id; /*[Range] 0-16, 0 is INVALID_MEAS_ID and is forbidden use here.
+ [Meaning] <TS25.331:10.3.7.48>, it is 'Measurement Identity'
+ in the 'MEASUREMENT CONTROL', follow fields are all derived from the message.*/
+ TDD_internal_meas_E meas_quantity; /*[Range] TDD_MEAS_TX_PWR, TDD_MEAS_RSSI, TDD_MEAS_TA
+ [Meaning] Indicates internal measurement type in the primitive.*/
+ kal_bool periodic_ind; /*[Range]True/False.
+ [Meaning] Indicates whether TL1 report result of 'meas_type' periodically.
+ When 'meas_type' is TDD_MEAS_RSSI, always set with 'False'.*/
+ kal_uint8 report_num; /*[Range]: 0 ~ 64. Number of periodic reports to be reported. TL1 will ignore
+ this value if periodic_ind=False. If the value is 0, it means infinity.*/
+ kal_uint16 period; /*[Range]: 250 ~ 6400 frames. The reporting interval of periodic measurement.
+ TL1 will ignore this value if periodic_ind=False.*/
+ kal_uint8 event_num; /*Number of events in the below event[] list.*/
+ TDD_meas_event_T event[TDD_MAX_MEAS_EVENT]; /*The list of event.*/
+ kal_uint8 filter; /*[Range] 0-14.(fc0,fc1,fc2,fc3,fc4,fc5,fc6,fc7,fc8,fc9,fc11,fc13,fc15,fc17,fc19),
+ L3 filtering, apply for UTRA carrier RSSI and UE transmitted power.*/
+}tdd_cphy_measurement_internal_config_req_struct;
+
+
+typedef struct _TDD_cphy_measurement_internal_result_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 meas_id; /*[Range] 0-16, 0 is INVALID_MEAS_ID
+ [Meaning] Measurement Identity<TS25.331:10.3.7.48>; Indicate
+ TL1 return Tx-Pwr results with filter coefficient in 'MEASUREMENT
+ CONTROL' indicated by meas_id. If meas_id is 0, it means TL1
+ return Tx-Pwr value without filter.*/
+}tdd_cphy_measurement_internal_result_req_struct;
+
+
+typedef struct _TDD_cphy_measurement_internal_stop_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 num_meas_id; /*[Range] 1-TDD_MAX_NUM_MEAS_ID
+ [Meaning] The number of valid 'meas_id' in 'meas_id[]'.*/
+ kal_uint8 meas_id[TDD_MAX_NUM_MEAS_ID]; /*[Range] 1-16 [Meaning] <TS25.331:10.3.7.48>, it is 'Measurement
+ Identity' in the 'MEASUREMENT CONTROL', TL1 shall stop internal
+ measurement configured by these message.*/
+}tdd_cphy_measurement_internal_stop_req_struct;
+
+
+
+/*sniffer */
+typedef struct _TDD_cphy_rssi_sniffer_start_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 num_freq_list; /* Num of of freq for scan list of RSSI sniffer */
+ kal_uint16 uarfcn_list[TDD_MAX_RSSI_SNIFFER_SCAN_LIST]; /* Array of UARFCNs for RSSI sniffer*/
+} tdd_cphy_rssi_sniffer_start_req_struct;
+
+typedef struct _TDD_cphy_rssi_sniffer_stop_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_rssi_sniffer_stop_req_struct;
+
+
+/*HSPDA*/
+typedef struct _TDD_cphy_hsdsch_setup_req_struct
+{
+
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /*[meaning]: The activation time for this message.
+ TL1 will schedule the activation time to the TTI boundary.
+ [Range]: (-1~255). (0-255) for CFN type, "-1" for immediate type.*/
+
+ kal_bool h_rnti_valid; /*if H_RNTI valid*/
+
+ kal_uint16 h_rnti; /*H-RNTI assigned to UE*/
+
+ kal_uint16 prim_uarfcn; /*if H_RNTI valid*/
+
+ kal_uint16 work_uarfcn; /*Working uarfcn of the UE */
+ kal_uint16 cell_param_id; /*0-127,Cell parameter ID*/
+ TDD_hsscch_info_T hsscch_info; /*HS-SCCH Information*/
+ TDD_midamble_info_T hspdsch_midamble_info; /*HS-PDSCH Midamble Configuration*/
+ TDD_hs_harq_info_T harq_info; /*Harq process & IR buffer information*/
+ kal_bool mac_hs_reset; /*TRUE indicates the MAC-hs entity needs to be reset*/
+ kal_uint8 mac_event; /*Indicate whether HS-DSCH events indication should be sent to MAC:
+ Bit 0 : Setup; Bit 1 : Release ; Bit 2 : Modify
+ And in this primitive, only Bit 0 can be set to 1*/
+ TDD_hs_queue_info_T queue_info; /*MAC-hs Queue Information*/
+ kal_uint8 pccpch_tx_power; /*[Range]: 6 ~ 43 by step 1 in dBm
+ [Meaning]:P-CCPCH transmit power*/
+ kal_int8 max_tx_power; /*[Range]: -50 ~ 33 dBm
+ [Meaning]: Max. allowed TX power.*/
+ kal_int8 umts_power_class; /*UE capability(in dBm)
+ The value's unit configured by SLCE is dBm.
+ define MAX_OUTPUT_POWER_CLASS_1 33 :+33dBm
+ define MAX_OUTPUT_POWER_CLASS_2 24 : +24dBm
+ define MAX_OUTPUT_POWER_CLASS_3 21 : +21dBm
+ define MAX_OUTPUT_POWER_CLASS_4 27 : +27dBm */
+
+ kal_int16 rscp; /* -500 ~ -100 means (-125 ~ -25 )dBm in 0.25 dB step,serving cell rscp*/
+ kal_uint8 capability_category; /*[Meaning]: indicate TL1 to usewhich category (1,9,24)*/
+ kal_uint8 tid; /*Transation ID, used for reporting DL INIT SYNC*/
+ TDD_rrc_state_E rrc_status; /* Indicate the RRC current status */
+ TDD_hspdsch_state_info_T hspdsch_state_info;
+ kal_int32 Tm;
+ kal_int16 Off;
+ kal_uint8 doff;
+ TDD_dl_establish_T dl_sync_info; /*Downlink establishment criterion*/
+ kal_bool c_h_rnti_valid; /*Indicate if common H-RNTI is valid for UL1. This field shall be set to FALSE when rrc_status is equal to CELL_DCH.*/
+ kal_uint16 c_h_rnti; /*Common H-RNTI assigned to UE, Never use in CELL_PCH/URA_PCH*/
+ kal_bool b_h_rnti_valid; /* [R7] Indicate if bcch-specific H-RNTI is valid for UL1 */
+ kal_uint16 b_h_rnti; /* [R7] bcch-specific H-RNTI assigned to UE. UL1 should not refer to this field if b_h_rnti_valid = KAL_FALSE. */
+
+} tdd_cphy_hsdsch_setup_req_struct;
+
+typedef struct _TDD_cphy_hsdsch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /*[meaning]: The activation time for this message. TL1 will schedule
+ the activation time to the TTI boundary. [Range]: (-1~255).
+ (0-255) for CFN type, "-1" for immediate type.*/
+
+ /*kal_uint8 modify_field;*/
+//#else /*R8*/
+ kal_uint16 modify_field; /*Bit field to represent for the parameters that should be modified
+ Bit 0 : H-RNTI, including D/B-HRNTI type;
+ Bit 1 : HS-SCCH Info;
+ Bit 2 : HSPDSCH_midamble_info
+ Bit 3 : HARQ Info;
+ Bit 4 : Queue Info.
+ Bit 5 : Uplink power control related parameters,such as
+ "pccpch_tx_power", "max_tx_power" and "umts_power_class"
+ Bit 6 : work_uarfcn
+ Bit 7 : capability_category
+ Bit 8 : hspdsch_state_info
+ Bit 9 : hs_cell_fach_drx_info
+ Bit 10: Tm, NO USE now
+ Bit 11: Off, NO USE now
+ Bit 12: doff, NO USE now
+ Bit 13: dl_sync_info
+ Bit 14: cHrnti
+ Note: modify_field can be "0" only when mac_hs_reset = true. */
+
+//#endif
+ kal_uint16 h_rnti; /*H-RNTI assigned to UE*/
+ kal_uint16 work_uarfcn; /*Working uarfcn of the UE */
+ TDD_hsscch_info_T hsscch_info; /*HS-SCCH Information*/
+ TDD_midamble_info_T hspdsch_midamble_info; /*HS-PDSCH Midamble Configuration*/
+ TDD_hs_harq_info_T harq_info; /*Harq process & IR buffer information*/
+ kal_bool mac_hs_reset; /*TRUE indicates the MAC-hs entity needs to be reset*/
+ kal_uint8 mac_event; /*Indicate whether HS-DSCH events indication should be sent to MAC:
+ Bit 0 : Setup; Bit 1 : Release ; Bit 2 : Modify
+ And in this primitive, only Bit 2 can be set to 1*/
+ TDD_hs_queue_info_T queue_info; /*MAC-hs Queue Information*/
+ kal_uint8 pccpch_tx_power; /*[Range]: 6 ~ 43 by step 1 in dBm
+ [Meaning]:P-CCPCH transmit power*/
+ kal_int8 max_tx_power; /*Range]: -50 ~ 33 dBm
+ [Meaning]: Max. allowed TX power.*/
+ kal_int8 umts_power_class; /*UE capability(in dBm)
+ The value's unit configured by SLCE is dBm.
+ define MAX_OUTPUT_POWER_CLASS_1 33 :+33dBm
+ define MAX_OUTPUT_POWER_CLASS_2 24 : +24dBm
+ define MAX_OUTPUT_POWER_CLASS_3 21 : +21dBm
+ define MAX_OUTPUT_POWER_CLASS_4 27 : +27dBm */
+
+ kal_uint8 capability_category; /*[Meaning]: indicate TL1 to usewhich category (1,9,24)*/
+ kal_uint8 tid; /*Transation ID, used for reporting DL INIT SYNC*/
+ TDD_rrc_state_E rrc_status; /*[R8] Specify that HS-DCH transmission type*/
+ TDD_hspdsch_state_info_T hspdsch_state_info;
+ kal_int32 Tm;
+ kal_int16 Off;
+ kal_uint8 doff;
+ kal_int16 rscp;
+ TDD_dl_establish_T dl_sync_info; /*Downlink establishment criterion*/
+ kal_bool h_rnti_valid; /* Indicate if h_rnti field is valid for UL1. H-RNTI shall be always valid for CELL_DCH, CELL_FACH, TDD_IDLE_FACH, and shall be always invalid for URA_PCH. */
+ kal_bool b_h_rnti_valid; /* [R7] Indicate if bcch-specific H-RNTI is valid for UL1 */
+ kal_uint16 b_h_rnti; /* [R7] bcch-specific H-RNTI assigned to UE. UL1 should not refer to this field if b_h_rnti_valid = KAL_FALSE. */
+ kal_bool c_h_rnti_valid; /*Indicate if common H-RNTI is valid for UL1. This field shall be set to FALSE when rrc_status is equal to CELL_DCH.*/
+ kal_uint16 c_h_rnti; /*Common H-RNTI assigned to UE, Never use in CELL_PCH/URA_PCH*/
+//#endif
+} tdd_cphy_hsdsch_modify_req_struct;
+
+typedef struct _TDD_cphy_hsdsch_release_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /*[meaning]: The activation time for this message. TL1 will schedule the activation time to the
+ TTI boundary. [Range]: (-1~255). (0-255) for CFN type, "-1" for immediate type.*/
+ kal_bool mac_hs_reset; /*TRUE indicates the MAC-hs entity needs to be reset*/
+ kal_uint8 mac_event; /*Indicate whether HS-DSCH events indication should be sent to MAC:
+ Bit 0 : Setup; Bit 1 : Release ; Bit 2 : Modify
+ And in this primitive, only Bit 1 can be set to 1*/
+} tdd_cphy_hsdsch_release_req_struct;
+
+#ifdef __HSUPA_SUPPORT__
+typedef struct _TDD_cphy_edch_setup_req_struct
+{
+
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /*[meaning]: The activation time for this message. L1 will schedule the activation time
+ to the TTI boundary. [Range]: (-1~255). (0-255) for CFN type, "-1" for immediate type.*/
+
+ kal_bool e_rnti_valid;
+
+ kal_uint16 e_rnti; /*E-RNTI assigned to UE.*/
+
+ kal_uint8 capability_category; /*indicating which category [1,15] TL1 to use*/
+
+ kal_bool is_lowest_capability_category; /*[Meaning]: indicate TL1 to use whether the lowest category or not.*/
+
+ kal_uint16 work_uarfcn; /*Working uarfcn of the UE */
+ kal_uint16 cell_param_id; /*0-127,Cell parameter ID*/
+ kal_bool edch_sched_info_valid; /*The following edch_sched_info valid or not.*/
+ TDD_edch_sched_info_T edch_sched_info; /*Scheduled Transmission Information.*/
+ kal_bool edch_non_sched_info_valid; /*The following edch_sched_info valid or not.*/
+ TDD_edch_non_sched_info_T edch_non_sched_info; /*Non-Scheduled Transmission Information.*/
+ TDD_epuch_info_T epuch_info; /*E-PUCH Information, common to both scheduled and non-scheduled E-DCH transmission.*/
+ TDD_edch_harq_info_T edch_harq_info; /*Harq Configuration Information.*/
+ kal_bool mac_es_e_reset; /*TRUE indicates the MAC-es/e entity needs to be reset.*/
+ kal_uint8 mac_event; /*Indicate whether E-DCH events indication should be sent to MAC:
+ Bit 0 : Setup; Bit 1 : Release ; Bit 2 : Modify
+ And in this primitive, only Bit 0 can be set to 1*/
+
+ TDD_edch_transmission_type_E transmission_type; /*[R8] specify that EDCH is allocated in dedicated state or common state*/
+ TDD_common_edch_info_T common_edch_info; /*[R8]This field is only valid when transmission_type == TDD_EDCH_IN_COMMON_STATE*/
+ kal_uint8 pa_plus_valid_flag; /*bitmask bit0: eagch_drx_info_valid
+ bit1: edch_sps_info_valid*/
+ TDD_eagch_drx_info_T eagch_drx_param; /*EAGCH DRX related param*/
+ TDD_edch_sps_info_T edch_sps_info; /*EDCH SPS related param*/
+ kal_bool ul_sync_flag;
+ kal_uint16 t321; /*100, 200, 400, 800 ms*/
+
+} tdd_cphy_edch_setup_req_struct;
+
+typedef struct _TDD_cphy_edch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /*[meaning]: The activation time for this message. L1 will schedule
+ the activation time to the TTI boundary. [Range]: (-1~255).
+ (0-255) for CFN type, "-1" for immediate type.*/
+
+ kal_uint16 modify_field; /*Bit0 ~ Bit6: refer to the below comments
+ Bit7 ~ Bit9: new added for PA+
+ Bit7: common edch info
+ Bit8: EAGCH DRX info
+ Bit9: EDCH SPS info*/
+//#else
+ //kal_uint8 modify_field;
+ /*Bit field to represent for the parameters that should be modified
+ Bit0: E-RNTI;
+ Bit1: scheduled mode information;
+ Bit2: non-scheduled mode information;
+ Bit3: e-puch information;
+ Bit4: HARQ information;
+ Bit 5: is_lowest_capablility_category .
+ Bit6: work_uarfcn
+ Note: modify_field can be "0" only when mac_e_es_reset = true. */
+//#endif
+ kal_uint16 e_rnti; /*E-RNTI assigned to UE.*/
+
+ kal_uint8 capability_category; /*indicating which category [1,15] TL1 to use*/
+
+ kal_bool is_lowest_capability_category; /*[Meaning]: indicate TL1 to use whether the lowest category or not.*/
+
+ kal_uint16 work_uarfcn; /*Working uarfcn of the UE */
+ kal_bool edch_sched_info_valid; /*Schedule EPUCH is valid or not after this msg.*/
+ TDD_edch_sched_info_T edch_sched_info; /*Scheduled Transmission Information.*/
+ kal_bool edch_non_sched_info_valid; /*Non-schedule EPUCH isalid or notafter this msg.*/
+ TDD_edch_non_sched_info_T edch_non_sched_info; /*Non-Scheduled Transmission Information.*/
+ TDD_epuch_info_T epuch_info; /*E-PUCH Information, common to both scheduled and non-scheduled E-DCH transmission.*/
+ TDD_edch_harq_info_T edch_harq_info; /*Harq Configuration Information.*/
+ kal_bool mac_es_e_reset; /*TRUE indicates the MAC-es/e entity needs to be reset.*/
+ kal_uint8 mac_event; /*Indicate whether E-DCH events indication should be sent to MAC:
+ Bit 0 : Setup; Bit 1 : Release ; Bit 2 : Modify
+ And in this primitive, only Bit 2 can be set to 1*/
+
+ TDD_edch_transmission_type_E transmission_type; /*[R8] specify that EDCH is allocated in dedicated state or common state*/
+ TDD_common_edch_info_T common_edch_info; /*[R8]This field is only valid when transmission_type == TDD_EDCH_IN_COMMON_STATE*/
+ kal_uint8 pa_plus_valid_flag; /*Bit0: DRX en/disable; Bit1: SPS en/disable*/
+ TDD_eagch_drx_info_T eagch_drx_param; /*EAGCH DRX related param*/
+ TDD_edch_sps_info_T edch_sps_info; /*EDCH SPS related param*/
+ kal_bool e_rnti_valid;
+
+
+} tdd_cphy_edch_modify_req_struct;
+
+typedef struct _TDD_cphy_edch_release_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time; /*[meaning]: The activation time for this message. L1 will schedule the activation time to the
+ TTI boundary. [Range]: (-1~255). (0-255) for CFN type, "-1" for immediate type.*/
+ kal_bool mac_es_e_reset; /*TRUE indicates the MAC-es/e entity needs to be reset.*/
+ kal_uint8 mac_event; /*Indicate whether EDCH events indication should be sent to MAC:
+ Bit 0 : Setup; Bit 1 : Release ; Bit 2 : Modify
+ And in this primitive, only Bit 1 can be set to 1*/
+} tdd_cphy_edch_release_req_struct;
+#endif
+
+//#if defined( __UMTS_R9__ ) && defined ( __AST3002__ )
+typedef struct _TDD_cphy_measurement_config_dmo_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 act_time;
+
+ kal_uint8 dmo_bitmap;
+ TDD_dch_mo_info_T dmo_pattern[TDD_MAX_DMO_PATTERN_NUM];
+}tdd_cphy_measurement_config_dmo_req_struct;
+//#endif
+
+typedef struct _TDD_cphy_measurement_config_idle_interval_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 k;
+ kal_uint8 Offset;
+}tdd_cphy_measurement_config_idle_interval_req_struct;
+
+/*****************************************************************************
+ container request
+*****************************************************************************/
+
+/*-------- Message(Primitive) related definition ----------------------*/
+
+typedef struct _TDD_msg_buf_T /* Buffer of message container */
+{
+ kal_uint8 channel_id; /* Channel ID */
+ msg_type msg_id; /* Message ID */
+ kal_uint16 buff_size; /* Buffer size */
+ local_para_struct* buffer; /* Channel configuration message buffer */
+} TDD_msg_buf_T;
+
+
+typedef struct _TDD_cphy_msg_container_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 at_ref; /* Reference channge of activation time.
+ 0 : Ref channel is the released channel.
+ There should be ch to be released
+ 1 : Ref channel is the setup channel.
+ There should be ch to be setup. */
+ /*
+ meas_control_E meas_control; // Indicate whether TL1 need to not to resume meas. after apply corresponding buffer's config.
+ kal_int8 idx_intra_freq; // [Range]: 0 ~ 2. Indicate which frequency in the array uarfcn[TDD_MAX_UMTS_FREQ] is intra-frequency, -1 means invalid
+ */
+ kal_uint8 rab_domain_field; /* BIT0: CS present,
+ BIT1: PS present */
+
+ kal_int16 rx_cfn; /* Indicate peer message receive cfn. Ex: tti = 4, receive frame number : 0,1,2,3. rx_cfn = 3 (set by tl1)
+ [Range]: -1 ~ 255.
+ -1 : Means upper layer internal control
+ */
+
+ kal_uint8 msg_num; /* # of included msg. 1 ~ 4 */
+ TDD_msg_buf_T msg_buffer[4]; /* List of msg buffer for included channel msg */
+ /* [R5R6] For HS-DSCH and E-DCH */
+ kal_uint8 h_msg_num; /* # of included H-msg. 0~2 */
+ TDD_msg_buf_T h_msg_buffer[2]; /* List of msg buffer for included channel msg */
+ kal_uint8 e_msg_num; /* # of included E-msg. 0~2 */
+ TDD_msg_buf_T e_msg_buffer[2]; /* List of msg buffer for included channel msg */
+
+// #if defined (__UMTS_R9__) && defined (__AST3002__)
+ kal_uint8 dmo_msg_num; /* # of included dmo-msg. 0~1 */
+ TDD_msg_buf_T dmo_msg_buffer[1]; /* List of msg buffer for included channel msg */
+//#endif
+
+} tdd_cphy_msg_container_req_struct;
+
+typedef struct _TDD_cphy_abort_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_abort_req_struct;
+
+typedef struct _TDD_cphy_abort_bch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_abort_bch_setup_req_struct;
+
+#if defined (__GEMINI__) && defined (__UMTS_RAT__)
+typedef struct _TDD_rsvas_tl1_suspend_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_rsvas_tl1_suspend_req_struct;
+typedef struct _TDD_rsvas_tl1_resume_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_rsvas_tl1_resume_req_struct;
+#endif
+
+#ifdef __GEMINI__
+typedef struct _TDD_cphy_channel_priority_adjustment_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool channel_priority_high; /*TRUE: TL1 channel priority is set to high;*/
+ /*FALSE: TL1 channel priority is set to normal */
+ kal_int16 act_time; /*-1:active immediately,usually is -1 */
+ /*only dch modify and handover(R+S),the value is the real AT*/
+} tdd_cphy_channel_priority_adjustment_req_struct;
+typedef struct _TDD_urr_tl1_switch_gemini_mode_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_virtual_mode; /*TRUE: TL1 will switch from normal mode to virtual mode;*/
+ /*FALSE: TL1 will switch from virtual mode to normal mode */
+} tdd_urr_tl1_switch_gemini_mode_req_struct;
+typedef struct _TDD_rsvas_tl1_virtual_resume_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_rsvas_tl1_virtual_resume_req_struct;
+typedef struct _TDD_phy_channel_priority_adjustment_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool channel_priority_high; /*TRUE: TL1 channel priority is set to high;*/
+ /*FALSE: TL1 channel priority is set to normal */
+} tdd_phy_channel_priority_adjustment_req_struct;
+
+#endif
+
+typedef struct _l4ctl1_get_rf_temperature_req_struct
+{
+ LOCAL_PARA_HDR
+} l4ctl1_get_rf_temperature_req_struct;
+
+typedef struct _l4ctl1_get_rf_temperature_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 modem_temperature;
+} l4ctl1_get_rf_temperature_cnf_struct;
+
+typedef struct _l4ctl1a_txrx_active_time_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 src_id;
+
+} l4ctl1a_txrx_active_time_req_struct;
+
+
+typedef struct _l4ctl1a_txrx_active_time_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 src_id; // just piggyback the src_id sent by l4cel1_txrx_active_time_req_struct from L4C.
+ kal_uint32 tx_mode_time_ms[5];
+ kal_uint32 rx_mode_time_ms;
+ kal_uint32 txrx_mode_union_time_ms;
+
+} l4ctl1a_txrx_active_time_cnf_struct;
+
+typedef struct _l4ctl1_em_tst_control_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 src_id;
+ TDD_tl1_em_tstcmdtype type;
+ TDD_tl1_em_tstcmdpara param;
+} l4ctl1_em_tst_control_req_struct;
+
+#if defined (__MML1_ADT_ENABLE__)
+/*****************************************************************************
+ TL1 req for ADT Task
+*****************************************************************************/
+typedef struct _TDD_tl1_l1adt_enter_connected_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_tl1_l1adt_enter_connected_req_struct;
+
+typedef struct _TDD_tl1_l1adt_leave_connected_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_tl1_l1adt_leave_connected_req_struct;
+
+typedef struct _TDD_tl1_l1adt_enter_tdd_mode_req_struct
+{
+ LOCAL_PARA_HDR
+} tdd_tl1_l1adt_enter_tdd_mode_req_struct;
+
+
+
+/*****************************************************************************
+ confirm from ADT Task to TL1
+*****************************************************************************/
+typedef struct _TDD_tl1_l1adt_enter_connected_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_int32 adt_dl_result;
+/*
+{//PASS_DL_(UN)COMPLETE_xxx -> xxx means the current RAT mode
+ FAIL_OTHER_RAT_IS_CONN,
+ PASS_DL_COMPLETE_CONN,
+ PASS_DL_NOT_YET_FINISHED_CONN,
+ PASS_DL_COMPLETE_IDLE,
+ PASS_DL_NOT_YET_FINISHED_IDLE,
+ PASS_STOP_N_RESTART_DL_IDLE,
+ PASS_START_DL_IDLE
+}
+*/
+} tdd_tl1_l1adt_enter_connected_cnf_struct;
+
+typedef struct _TDD_tl1_l1adt_leave_connected_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_int32 idle_result;
+/*
+{
+ NORMAL,
+ ABNORMAL_IDLE,
+ ABNORMAL_OTHER_CONN
+}
+*/
+} tdd_tl1_l1adt_leave_connected_cnf_struct;
+
+typedef struct _TDD_tl1_l1adt_enter_tdd_mode_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_tl1_l1adt_enter_tdd_mode_cnf_struct;
+
+/*****************************************************************************
+ TL1 ind for ADT Task
+*****************************************************************************/
+typedef struct _TDD_tl1_l1adt_enter_tdd_mode_ind_struct
+{
+ LOCAL_PARA_HDR
+} tdd_tl1_l1adt_enter_tdd_mode_ind_struct;
+
+
+
+#endif
+
+/*****************************************************************************
+ confirm & indication from TL1 to L4C
+*****************************************************************************/
+typedef struct _l4ctl1_em_tst_control_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 src_id;
+ kal_bool success;
+#ifdef __ATERFTX_ERROR_HANDLE_ENHANCE__
+ ps_cause_enum err_cause;
+#endif
+}l4ctl1_em_tst_control_cnf_struct;
+typedef struct _l4ctl1_em_tx_report_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_int32 tx_power; //1/8db
+}l4ctl1_em_tx_report_ind_struct;
+
+/*****************************************************************************
+ confirm & indication from TL1 to SLCE
+*****************************************************************************/
+typedef struct _TDD_cphy_bch_setup_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_bch_setup_cnf_struct;
+
+typedef struct _TDD_cphy_bch_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool success; /* Indicate if BCH setup success. For current TL1, it always return true. */
+} tdd_cphy_bch_setup_ind_struct;
+
+typedef struct _TDD_cphy_bch_modify_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_bch_modify_cnf_struct;
+
+typedef struct _TDD_cphy_bch_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_bch_modify_ind_struct;
+
+typedef struct _TDD_cphy_bch_release_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_bch_release_cnf_struct;
+
+typedef struct _TDD_cphy_bch_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_bch_release_ind_struct;
+
+
+typedef struct _TDD_cphy_sfn_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool success; /*True/False. True: The SFN result is success. The SFN is in the following (tm, off).
+ False: The SFN reading is failed. The SFN in the following (tm, off) will be ignored.*/
+ kal_int32 tm; /*[Range]: -1 ~ (6400*8-1). -1 for unknown timing.
+ [Meaning]:Sub Frame boundary offset between target cell and LST
+ For a cell with unknown tm value, it can not be issued to TL1. */
+ kal_int16 off; /*[Range]: -1~8191, (0-8191) for a cell whose Sub SFN offset to LST has been measured by TL1. -1 means off unknown.
+ [Meaning]: Sub frame number offset between target cell and LST.
+ For a cell with unknown off value, it can not be issued to TL1. */
+ kal_uint16 uarfcn; /*uarfcn*/
+ kal_uint16 cell_param_id; /*[Range]: 0-127, TDD_CPID_INVALID
+ [Meaning]:Cell parameter ID*/
+#if defined (__GEMINI__) && defined (__UMTS_RAT__)
+ TDD_uas_gemini_conflict_cause_enum conflict_cause; /*Channel conflict casue with peer channel*/
+ kal_uint16 peer_priority_index; /* Channel conflict priority index with peer channel*/
+#endif
+} tdd_cphy_sfn_ind_struct;
+
+
+typedef struct _TDD_cphy_t312_expiry_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tid; /* Transaction id */
+
+} tdd_cphy_t312_expiry_ind_struct;
+
+typedef struct _TDD_cphy_dl_init_sync_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tid; /* Transaction id */
+ kal_int32 dpch_tm; /* For CFN-SFN TD */
+ kal_int16 dpch_off; /* For CFN-SFN TD */
+} tdd_cphy_dl_init_sync_ind_struct;
+
+typedef struct _TDD_cphy_rl_failure_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool intrafreq_interference_flag; /* TRUE: Indicate Radio Link Failure is caused by Intra-freq interference */
+} tdd_cphy_rl_failure_ind_struct;
+
+typedef struct _TDD_cphy_frequency_scan_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_frequency_scan_cnf_struct;
+
+typedef struct _TDD_cphy_frequency_scan_ind_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_frequency_scan_ind_struct;
+
+typedef struct _TDD_cphy_frequency_scan_suspend_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_frequency_scan_suspend_cnf_struct;
+
+typedef struct _TDD_cphy_frequency_scan_suspend_ind_struct
+{
+ LOCAL_PARA_HDR
+ } tdd_cphy_frequency_scan_suspend_ind_struct;
+
+typedef struct _TDD_cphy_frequency_scan_continue_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_frequency_scan_continue_cnf_struct;
+
+
+typedef struct _TDD_cphy_measurement_config_cell_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_measurement_config_cell_cnf_struct;
+
+
+
+typedef struct _TDD_cphy_measurement_cell_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tid; /*Transaction ID to synchronize between request and indication.
+ Its value will be the same as the 'tid' field used in
+ CPHY_MEASUREMENT_CONFIG_CELL_REQ. This field is unused for
+ the frequency scan report.*/
+ TDD_measured_type_T measured_type; /*Measurement report type: TDD_INTRA_FREQUENCY_MEASURED,
+ TDD_INTER_FREQUENCY_MEASURED,FREQ _SCAN_DETECTED,TDD_SERVING_ONLY
+ If UE works in the primary freq, the serving cell measurement is included
+ in intra-freq measurement report. If it works in the second freq, the serving
+ cell measurement is included in the inter-freq measurement report.*/
+ kal_bool iscp_included; /*True: Indicate this message contains the iscp measurement result.
+ This field is only used for INTRA-FREQUENCY report.*/
+ kal_bool fs_halt; /*True: Frequency scan procedure is temporary halt. TL1 will wait for
+ CPHY_FREQSCAN_CONTINUE_REQ. False: Frequency scan procedure
+ is in progress. It can be set with 'TRUE' when report cell scan result.
+ This field is only used for frequency scan report. This field is un-used
+ for the cell measurement report.*/
+ kal_int16 rssi[TDD_MAX_UMTS_FREQ]; /*indicate the TS0's RSSI of each frequency included in 'measured_cell[]'.
+ Range: -400 ~ -100 means (-100 ~ -25) dBm 0.25 dB step. The sequence
+ of frequency RSSI is same with 'measured_cell[]'*/
+ kal_uint8 num_cell; /*[range]: 0- TDD_MAX_NUM_REPORT_CELL Number of cells reported in this message*/
+ TDD_measured_cell_T measured_cell[TDD_MAX_NUM_REPORT_CELL]; /*List of measured cells' measurement result. TL1 may report multi-frequency's
+ measurement result in the same list, It is ascending sort by cell's uarfcn and
+ cell_param_id. Cells on the same frequency will be collected together.
+ The cells on different frequencies will not be interleaved.*/
+ kal_uint8 sinr;
+ kal_bool evaluate_req;
+ kal_int8 tx_power;
+ kal_bool isLongPeriodIn3GStandby; /* [Rel8][ABPCR] For RR, Indicate if it is prio search peiorid*/
+} tdd_cphy_measurement_cell_ind_struct;
+
+
+
+typedef struct _TDD_cphy_specific_cell_search_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool success; /* Indicate if search success */
+ TDD_measured_cell_T measured_cell; /* The found(1) cell */
+} tdd_cphy_specific_cell_search_ind_struct;
+
+typedef struct _TDD_cphy_specific_cell_search_stop_ind_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_specific_cell_search_stop_ind_struct;
+
+
+/*reset&set rat*/
+typedef struct _TDD_cphy_reset_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool success; /* Indicate whether the TL1 initialization sucess or fail
+ 'True' - L1 successfully initialize itself.
+ 'False' - L1 fail to initialize itself.
+ */
+} tdd_cphy_reset_cnf_struct;
+
+
+typedef struct _TDD_cphy_rf_on_cnf_struct
+{
+ LOCAL_PARA_HDR
+ } tdd_cphy_rf_on_cnf_struct;
+
+typedef struct _TDD_cphy_rf_off_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_rf_off_cnf_struct;
+
+typedef struct _TDD_cphy_set_active_rat_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_set_active_rat_cnf_struct;
+
+/*tx status*/
+typedef struct _TDD_cphy_tx_status_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_tx_allow; /* the current TX status
+ TRUE : Currentlly, TX is available in TL1.
+ FALSE : Currentlly, TX is not available in TL1. */
+} tdd_cphy_tx_status_ind_struct;
+
+/*gap status*/
+typedef struct _TDD_cphy_gsm_gap_status_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_bsic_gap_valid;
+
+} tdd_cphy_gsm_gap_status_ind_struct;
+
+/*internal measu*/
+typedef struct _TDD_cphy_measurement_internal_config_cnf_struct
+{
+ LOCAL_PARA_HDR
+}tdd_cphy_measurement_internal_config_cnf_struct;
+
+typedef struct _TDD_cphy_measurement_internal_event_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 meas_id; /*[Range] 1-16 Measurement Identity<TS25.331:10.3.7.48>*/
+ TDD_internal_meas_event_E event_id; /*indicate internal measurement event id*/
+ TDD_tx_power_info_T tx_power_info; /*The averaged TX power measurement result. It is a filter value with filter
+ coefficient in 'MEASUREMENT CONTROL' indicated by meas_id.*/
+ TDD_tadv_info_T tadv_info; /*time advance */
+} tdd_cphy_measurement_internal_event_ind_struct;
+
+typedef struct _TDD_cphy_measurement_internal_periodic_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 meas_id; /*[Range] 1-16, Measurement Identity<TS25.331:10.3.7.48>*/
+ kal_bool last_report; /*True/False. True: Indicate that the 'report_num' is reached,
+ and no more periodic report will be returned to RRC.*/
+ TDD_tadv_info_T tadv_info; /*time advance*/
+ TDD_tx_power_info_T tx_power_info; /*The averaged TX power measurement result.It is a filter value with filter
+ coefficient in 'MEASUREMENT CONTROL' indicated by meas_id.*/
+
+} tdd_cphy_measurement_internal_periodic_ind_struct;
+
+
+typedef struct _TDD_cphy_measurement_internal_result_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 meas_id; /*[Range] 0-16, 0 is TDD_MEAS_ID_INVALID.
+ [Meaning] it is the ¡®Measurement Identity¡¯ same as the request
+ meas_id in related tdd_cphy_measurement_internal_result_req_struct primitive.
+ If Tl1 doesn¡¯t contain the meas_id as in tdd_cphy_measurement_internal_result_req_struct,
+ it will treat the meas_id as 0, and return Tx-Pwr value without filter.*/
+ kal_int16 sir[TDD_MAX_TIMESLOT_PER_SUBFRAME]; /*[Range]: -28 ...40 means(-14dB - 20dB ) in 0.5 dB step*/
+ TDD_tx_power_info_T tx_power_info; /*The averaged TX power measurement result.*/
+ TDD_tadv_info_T tadv_info; /*time advance*/
+
+} tdd_cphy_measurement_internal_result_ind_struct;
+
+
+typedef struct _TDD_cphy_measurement_internal_stop_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_measurement_internal_stop_cnf_struct;
+
+
+
+
+/*sniffer*/
+typedef struct _TDD_cphy_rssi_sniffer_start_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_rssi_sniffer_start_cnf_struct;
+
+
+typedef struct _TDD_cphy_rssi_sniffer_stop_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+} tdd_cphy_rssi_sniffer_stop_cnf_struct;
+
+
+
+typedef struct _TDD_cphy_rssi_sniffer_signal_appear_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 num_freq_list; /*Number of freq for scan list of RSSI sniffer */
+ kal_uint16 uarfcn_list[TDD_MAX_RSSI_SNIFFER_SCAN_LIST]; /* Array of UARFCNs on which cells are found */
+
+} tdd_cphy_rssi_sniffer_signal_appear_ind_struct;
+
+
+typedef struct _TDD_cphy_msg_container_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+} tdd_cphy_msg_container_cnf_struct;
+
+typedef struct _TDD_cphy_msg_container_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool success_flag;
+} tdd_cphy_msg_container_ind_struct;
+
+
+typedef struct _TDD_cphy_abort_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool success; /* Indicate if abort request success
+ TRUE : TL1 will back to the old channel configure.
+ FALSE : TL1 will go forward to the new channel configure.*/
+} tdd_cphy_abort_cnf_struct;
+
+#if defined (__GEMINI__) && defined (__UMTS_RAT__)
+typedef struct _TDD_rsvas_tl1_suspend_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_rsvas_tl1_suspend_cnf_struct;
+#endif
+
+
+/*****************************************************************************
+ request from MAC to TL1
+*****************************************************************************/
+typedef struct _TDD_phy_rach_data_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 tfci; /* TFCI. 0 ~ 1023 */
+ TDD_ulTrchData TrchInfo; /* UL TrCH information */
+ kal_uint16 size_data; /* This parameter represents the number of bytes of the buffer. This number will be equal to the size of allocated buffer plus 4 bytes. */
+ kal_uint8 *data[TDD_MAX_UL_TB]; /* data for each TB. PS shoul allocate the buffer */
+#ifdef __HSUPA_SUPPORT__
+ TDD_access_type_E access_type; /*Type of random access, RACH or E-RUCCH.
+ [Notes]:
+ #1. Fixed parameters for E-RUCCH:
+ TrchInfo.trchId = 0, TrchInfo.tb_size = 39(23 + 16), TrchInfo.num_tb = 1,
+ tfci = 0, size_data = 9(5 + 4).
+ #2. Data layout:
+ Padding(1bit) + SNPL(5bits) + UPH(5bits) + TEBS(5bits) + HLBS(4bits) + HLID(4bits) + E-RNTI(16bits)
+ #3. TL1 shall fill the following parameters:
+ SNPL, bit6/byte0 ~ bit2/byte0;
+ UPH, bit1/byte0 ~ bit5/byte1.*/
+#endif
+} tdd_phy_rach_data_req_struct;
+
+typedef struct _TDD_phy_access_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool retry; /*True: RACH transmission failed in the last access procedure,
+ and TL1 will use the same RACH data and ASC as in the last access procedure.
+ False: It¡¯s a new RACH procedure. TL1 will apply new RACH data and ASC from MAC.*/
+ kal_uint8 asc; /*The index value of configured asc array.*/
+#ifdef __HSUPA_SUPPORT__
+ TDD_access_type_E access_type; /*Type of random access, RACH or E-RUCCH.*/
+#endif
+
+
+ TDD_erucch_access_type_E erucch_type; /*ERUCCH type: CELL RESELECTION IND, UL SYNC ORDER, or SI REQUEST*/
+
+} tdd_phy_access_req_struct;
+
+/*****************************************************************************
+ indication from TL1 to MAC
+*****************************************************************************/
+
+typedef struct _TDD_phy_pch_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+} tdd_phy_pch_setup_ind_struct;
+
+typedef struct _TDD_phy_pch_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} tdd_phy_pch_release_ind_struct;
+
+typedef struct _TDD_phy_fach_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+} tdd_phy_fach_setup_ind_struct;
+
+
+typedef struct _TDD_phy_fach_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} tdd_phy_fach_release_ind_struct;
+
+typedef struct _TDD_phy_rach_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+} tdd_phy_rach_setup_ind_struct;
+
+typedef struct _TDD_phy_rach_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} tdd_phy_rach_release_ind_struct;
+
+typedef struct _TDD_phy_dch_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+ TDD_direction_E direction; /* Indicate UL or DL is being setup, 0 : DL , 1 : UL*/
+ kal_uint16 sfn; /* [Range]: 0 ~4095
+ [Meaning]: when DL DCH is setup. (Only used for downlink).*/
+} tdd_phy_dch_setup_ind_struct;
+
+typedef struct _TDD_phy_dch_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+ TDD_direction_E direction; /* Indicate UL or DL is being setup, 0 : DL , 1 : UL*/
+} tdd_phy_dch_modify_ind_struct;
+
+typedef struct _TDD_phy_dch_release_ind_struct
+{
+ LOCAL_PARA_HDR
+ TDD_direction_E direction; /* Indicate UL or DL is being setup, 0 : DL , 1 : UL*/
+ kal_uint16 sfn; /* [Range]: 0 ~4095
+ [Meaning]: when DL DCH is released. (Only used for downlink).*/
+} tdd_phy_dch_release_ind_struct;
+
+typedef struct _TDD_phy_config_abort_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool success; /* Indicate if abort request success
+ TRUE : TL1 will back to old channel configure
+ FALSE : TL1 will go forward to new channel configure*/
+} tdd_phy_config_abort_ind_struct;
+
+typedef struct _TDD_phy_dl_init_sync_ind_struct
+{
+ LOCAL_PARA_HDR
+
+} tdd_phy_dl_init_sync_ind_struct;
+
+
+typedef struct _TDD_phy_bch_data_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 *data; /* Used by PS only. TL1 would assign it as ¡°NULL¡±*/
+ kal_bool no_path; /* True/False. True: it means TL1 could not find the cell
+ other parameter should be ignored and protocol should release this BCH channel.
+ False: This cell has been found */
+ kal_int32 tm; /* [Range ]: -1 ~ 6400*8-1 , -1 means unknown timing
+ [Meaning]: Sub Frame boundary offset between target cell and LST*/
+ kal_int16 off; /* [Range]: -1~8191, -1 for off unknown cell.
+ [Meaning]: Sub frame number offset between target cell and LST.*/
+ kal_int16 rx_sfn; /* [Range]: 0 ~4095
+ [Meaning]: The sfn where the SIB/MIB is received.*/
+ kal_uint16 uarfcn; /* uarfcn*/
+ kal_uint16 cell_param_id; /* [Range]: 0-127, TDD_CPID_INVALID
+ [Meaning]:Cell parameter ID*/
+ kal_uint8 crc_status; /* 0: crc_error, 1: crc_ok, 2: no_crc*/
+ kal_int16 rssi; /* [Range]: -400 ~ -100 means (-100 ~ -25) dBm 0.25 dB step.
+ [Meaning]: TS0¡¯s RSSI.*/
+ kal_int16 rscp; /* [Range]: -500 ~ -100 means (-125 ~ -25 )dBm in 0.25 dB step
+ [Meaning]: Serving cell RSCP.*/
+ kal_bool standby_no_gap; /* True: L1 has no enough gap time for SIB reception */
+
+
+#if defined (__GEMINI__) && defined (__UMTS_RAT__)
+ TDD_uas_gemini_conflict_cause_enum conflict_cause; /*Channel conflict casue with peer channel*/
+ kal_uint16 peer_priority_index; /* Channel conflict priority index with peer channel*/
+#endif
+} tdd_phy_bch_data_ind_struct;
+
+
+typedef struct _TDD_phy_data_ind_struct
+{
+ LOCAL_PARA_HDR
+ TDD_cctrch_type_E dl_cctrch; /*For PCH, FACH or DCH CCTRCH.*/
+ kal_uint8 rx_fn; /*0-255.This is the FN of the last frame in the TTI that was received.
+ When DCH channel is activated, the reported FN is the true DCH CFN.
+ When DCH channel is not activated, FN is the value of (SFN%256).*/
+ kal_uint16 rx_sfn;
+ kal_uint16 uarfcn; /*uarfcn*/
+ kal_uint16 cell_param_id; /*0-127,Cell parameter ID*/
+ kal_uint8 num_trch; /*Number of Trch*/
+ TDD_dlTrchData TrchInfo[TDD_MAX_TRCH_NUM]; /*Downlink TRCH information. When TL1 is configured in Loopback mode 2,
+ the tb_size specifies the total of data bits and crc bits.*/
+ kal_uint32 crc; /*The crc result (Pass/Fail) for each TB. A bit 1 represents for "Pass', and 0 for"Fail"*/
+ kal_uint16 num_data; /*The size in byte of the buffer containing the data. It is the exact size of data,
+ including the byte for TB number.*/
+
+ kal_uint16 EMI_buffer_index; /*MAC allocate this buffer and free this EMI buffer,TL1D provide the buffer index where data stored,and MAC read it and free it*/
+
+
+
+/*mtk80854, here we do not if 0 *data, because in mac internal code, many *data are used*/
+/*to convinient coding, we keep *data in 6291, but only used by mac.*/
+/*need to confirm with L1!!!*/
+ #ifndef __TL1_UT_TEST__
+ /*for MT6291, we also use *data pointing to share buffer address*/
+ kal_uint8 *data; /*The buffer contains data for each TB received in this min TTI. This buffer is allocated
+ by TL1,and freed by PS. The buffer is from ADM. The first byte in the data indicates the number
+ of TB in this data indication*/
+ #else
+ kal_uint8 data[1000];
+ #endif
+ kal_uint32 raw_crc; /*Unmodified CRC for speech decoder */
+ kal_uint32 s_value[TDD_MAX_TRCH_NUM]; /*Viterbi decoder output S value for speech decoder */
+ kal_int16 tpc_SIR_lta; /*The measured SIR value of DPCH TPC field. It is TL1D debugging information for speech quality.*/
+ kal_int16 dpch_SIR_lta; /*The measured SIR value of DPCH pilot field. It is TL1D debugging information for speech quality.*/
+ kal_int16 TFCI_max_corr; /*The measured correlation value of DPCH TFCI field from TFCI decoder.
+ It is TL1D debugging information for speech quality.*/
+#if defined (__GEMINI__) && defined (__UMTS_RAT__)
+ TDD_uas_gemini_conflict_cause_enum conflict_cause; /*Channel conflict casue with peer channel*/
+#endif
+#ifdef __GEMINI__
+ kal_uint8 rx_suspend; /*It is a bitmap to indicate if some TrCH is conflicted with SIM2 gap.*/
+ /* The bit is set to "1" only when the TrCH TTI ends in this frame and SIM2 gap exists in this TTI.*/
+ /* LSB bit is mapped to trchInfo[0].*/
+#endif
+//#if defined( __UMTS_R9__ ) && defined ( __AST3002__ )
+ kal_uint8 meas_occasion_ind;
+//#endif
+ kal_int8 pi_repeat_cycle;/* -1:invalid, -2:retransmission with CRC pass, 1~20:valid pi_repeat_cyle */
+
+ /* serving cell information for speech debug. */
+ /* These values are valid only when DCH state and RL exists, otherwise, the value will be "0". */
+ kal_uint8 RSSI;
+ kal_uint8 RSCP;
+ kal_uint8 ECIO;
+ kal_uint8 HHO_SHO;
+
+} tdd_phy_data_ind_struct;
+
+typedef struct _tdd_phy_pch_data_ind_struct
+{
+ LOCAL_PARA_HDR
+ TDD_cctrch_type_E dl_cctrch; /*For PCH, FACH or DCH CCTRCH.*/
+ kal_uint8 rx_fn; /*0-255.This is the FN of the last frame in the TTI that was received.
+ When DCH channel is activated, the reported FN is the true DCH CFN.
+ When DCH channel is not activated, FN is the value of (SFN%256).*/
+ kal_uint16 rx_sfn;
+ kal_uint16 uarfcn; /*uarfcn*/
+ kal_uint16 cell_param_id; /*0-127,Cell parameter ID*/
+ kal_uint8 num_trch; /*Number of Trch*/
+ TDD_dlTrchData TrchInfo[TDD_MAX_TRCH_NUM]; /*Downlink TRCH information. When TL1 is configured in Loopback mode 2,
+ the tb_size specifies the total of data bits and crc bits.*/
+ kal_uint32 crc; /*The crc result (Pass/Fail) for each TB. A bit 1 represents for "Pass', and 0 for"Fail"*/
+ kal_uint16 num_data; /*The size in byte of the buffer containing the data. It is the exact size of data,
+ including the byte for TB number.*/
+
+ kal_uint16 EMI_buffer_index; /*LUMAC allocate this buffer and LURLC free this EMI buffer,TL1D provide the buffer index where data stored,and MAC read it and handle it*/
+
+ #ifndef __TL1_UT_TEST__
+ kal_uint8 *data; /*The buffer contains data for each TB received in this min TTI. This buffer is allocated
+ by TL1,and freed by PS. The buffer is from ADM. The first byte in the data indicates the number
+ of TB in this data indication*/
+ #else
+ kal_uint8 data[1000];
+ #endif
+ kal_uint32 raw_crc; /*Unmodified CRC for speech decoder */
+ kal_uint32 s_value[TDD_MAX_TRCH_NUM]; /*Viterbi decoder output S value for speech decoder */
+ kal_int16 tpc_SIR_lta; /*The measured SIR value of DPCH TPC field. It is TL1D debugging information for speech quality.*/
+ kal_int16 dpch_SIR_lta; /*The measured SIR value of DPCH pilot field. It is TL1D debugging information for speech quality.*/
+ kal_int16 TFCI_max_corr; /*The measured correlation value of DPCH TFCI field from TFCI decoder.
+ It is TL1D debugging information for speech quality.*/
+#if defined (__GEMINI__) && defined (__UMTS_RAT__)
+ TDD_uas_gemini_conflict_cause_enum conflict_cause; /*Channel conflict casue with peer channel*/
+#endif
+#ifdef __GEMINI__
+ kal_uint8 rx_suspend; /*It is a bitmap to indicate if some TrCH is conflicted with SIM2 gap.*/
+ /* The bit is set to "1" only when the TrCH TTI ends in this frame and SIM2 gap exists in this TTI.*/
+ /* LSB bit is mapped to trchInfo[0].*/
+#endif
+//#if defined( __UMTS_R9__ ) && defined ( __AST3002__ )
+ kal_uint8 meas_occasion_ind;
+//#endif
+ kal_int8 pi_repeat_cycle;/* -1:invalid, -2:retransmission with CRC pass, 1~20:valid pi_repeat_cyle */
+
+ /* serving cell information for speech debug. */
+ /* These values are valid only when DCH state and RL exists, otherwise, the value will be "0". */
+ kal_uint8 RSSI;
+ kal_uint8 RSCP;
+ kal_uint8 ECIO;
+ kal_uint8 HHO_SHO;
+}tdd_phy_pch_data_ind_struct;
+typedef struct _TDD_phy_access_ind_struct
+{
+ LOCAL_PARA_HDR
+ TDD_access_status_E access_status; /* The result of RACH access */
+#ifdef __HSUPA_SUPPORT__
+ TDD_access_type_E access_type; /*Type of random access, RACH or E-RUCCH.*/
+#endif
+
+
+ TDD_erucch_access_type_E erucch_type; /*ERUCCH type: CELL RESELECTION IND, UL SYNC ORDER, or SI REQUEST*/
+
+} tdd_phy_access_ind_struct;
+
+
+typedef struct _TDD_phy_post_tx_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ TDD_post_tx_type_E post_tx_type;
+ kal_uint8 cfn;
+#ifdef __GEMINI__
+ kal_bool is_tx_suspend; /*It indicates if there is SIM2 gap in the minTTI period of the released ul data. For RACH, this flag is always false*/
+#endif
+} tdd_phy_post_tx_ind_struct;
+
+
+typedef struct _TDD_phy_end_dch_tx_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 cfn; /*When MAC receives PHY_END_DCH_TX_IND, it's possible that time has
+ passed more than one TTI. So give this cfn value for MAC to handle
+ remaining things at the right CFN*/
+
+} tdd_phy_end_dch_tx_ind_struct;
+
+
+typedef struct _TDD_cphy_measurement_config_idle_interval_cnf_struct
+{
+ LOCAL_PARA_HDR
+} tdd_cphy_measurement_config_idle_interval_cnf_struct;
+
+
+
+typedef struct _TDD_phy_erucch_access_ind_struct
+{
+ LOCAL_PARA_HDR
+ TDD_erucch_access_type_E access_type; /*the type of TL1 triggerring ERUCCH Procedure,
+ TDD_UL_SYNC_ORDER or TDD_CELL_RESELECTION_IND*/
+}tdd_phy_erucch_access_ind_struct;
+
+
+typedef struct _TDD_phy_hsdsch_data_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 sub_cfn; /*[Range]: 0-511.*/
+ kal_uint8 config_operation; /*Bit 0: HS-DSCH setup; Bit1: HS-DSCH release; Bit 2: HS-DSCH modify*/
+ kal_bool mac_hs_reset; /*When TL1 does MAC-hs reset , the flag is set to tell MAC (it is also needed in
+ setup and release cases, not only for modify indication)*/
+ kal_uint8 size_info_modified; /*Bitmask of maximum 8 MAC-hs queues, with size info list modified
+ Bit 0: queue_id = 0; Bit 1: queue_id = 1; ¡;Bit 7: quque_id = 7*/
+ TDD_hsdsch_data_T hsdsch_data; /*The received MAC-hs data descriptor*/
+#ifdef __GEMINI__
+ kal_bool is_rx_suspend; /*It indicates if there is SIM2 gap in the TTI receiving dsch data*/
+#endif
+//#if defined( __UMTS_R9__ ) && defined ( __AST3002__ )
+ kal_uint8 meas_occasion_ind; /*bit0 indicates whether it is in DCH measurement occasion;
+ bit1 indicates whether it is in idle interval for E-UTRA Measurement.*/
+//#endif
+} tdd_phy_hsdsch_data_ind_struct;
+
+#ifdef __HSUPA_SUPPORT__
+
+typedef struct _TDD_phy_end_edch_tx_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 sub_cfn; /*[Range]: 0-511.*/
+
+
+ kal_uint8 harq_id; /*[Range]: 0~7 [Meaning]: Harq process id.*/
+} tdd_phy_end_edch_tx_ind_struct;
+#endif
+
+#if defined(TL1_SIM)
+kal_bool tl1_active_time_difference();
+
+/*------------------- Function prototype -----------------------------*/
+/* TL1 provides this function to other entities to get current CFN & SFN
+ CFN : -1 ~ 255. 0 ~ 255 if UE in DCH/FACH mode otherwise -1
+ SFN : -1 ~ 4095. 0 ~ 4095 for the base station frame number. -1 for an invalid value.*/
+void TL1_GetCurrentTime(kal_int16 *cfn, kal_int16 *sfn);
+#endif
+
+//extern kal_bool Tl1_FreeDataBuf(kal_uint8 type, kal_uint8* rel_buffer_ptr);
+
+typedef struct _TDD_tl1_data_buf_info_T
+{
+ kal_uint8 min_left_data_buffers;
+ kal_uint8 min_left_hsdsch_buffers;
+}TDD_tl1_data_buf_info_T;
+
+//extern void TL1_GetDataBufInfo(tl1_data_buf_info_T *tl1_data_buf_info_ptr);
+
+#if 0 //no used in U3G
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+//#if defined (__UMAC_DCH_LISR__) || defined (__HSUPA_SUPPORT__)
+typedef void (*TDD_pul_inform_MAC)(void *data);
+//#endif
+
+
+//#ifndef __UMAC_DCH_LISR__
+//extern void UMAC_UL_DCH_Tick(TDD_uldch_data_req_T * uldch_data_req);
+//extern void UMAC_UL_DCH_Tick_End(kal_bool tx_suspend,TDD_tx_enable_type_E tx_enable,TDD_uldch_data_ind_T * uldch_data_ind);
+//#else
+//extern void TDD_TL1D_L2PutHISRDCHQueue(TDD_pul_inform_MAC func, void *data);
+//#endif
+
+//extern void TDD_ul_inform_MAC(kal_uint8 cfn);
+
+//extern void TDD_ul_dpch_power(kal_uint8 cfn, kal_uint8 tfc_status[TDD_MAX_UL_TFC]);
+
+//extern TDD_uldch_data_ind_T* TDD_UMAC_UL_DCH_Tick_Low_Lisr(TDD_uldch_data_req_T * uldch_data_req);
+//extern void TL1_OTD_Calculation(kal_int16 off_s, kal_int16 off_n,
+// kal_int32 tm_ec_s, kal_int32 tm_ec_n,
+// kal_int16 *off_opt, kal_int32 *tm_ec_opt);
+
+//extern kal_int8 TL1_SelectSyncUlFpach(kal_uint8 *sync_ul_bitmap, kal_int8 num_fpach); /*Return index of FPACH in FPACH set.*/
+
+//extern void TDD_mac_hs_get_pdu_buffer(kal_uint8 **buffer_ptr, kal_uint16 size);
+
+//extern void TDD_try_to_trigger_CSR_STATUS_IND_LISR(kal_uint8 cfn);
+//extern void TDD_TL1D_L2PutHISRCsrQueue(TDD_pul_inform_MAC func, void *data);
+
+
+//extern void mac_hs_get_variable_pdu_buffer(kal_uint8 **buffer_ptr, kal_uint32 num);
+/*hs pdu buffer free shall only be invoked by UMAC, so no extern here */
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+//extern void mac_r4_get_variable_pdu_buffer(kal_uint8 **buffer_ptr, kal_uint32 num);
+extern void lumac_pch_get_variable_pdu_buffer(kal_uint8 **ppBuffer, kal_uint32 num);//interface to L1
+
+
+#ifdef __HSUPA_SUPPORT__
+/* Data path interface from TL1D, LISR / HISR / Task not decided yet */
+//extern etfc_eval_info_ind_T* umac_e_dch_tick_1(etfc_eval_info_req_T *etfc_eval_input);
+
+//extern edch_data_ind_T* umac_e_dch_tick_2(edch_data_req_T *edch_data_input);
+
+//extern void umac_e_dch_tick_3(kal_uint8 harq_id, tdd128_modulation_E modulation);
+
+//extern void umac_e_dch_tick_4(void); /*for MTK in-hourse project only*/
+
+//extern void ul_inform_Edch_MAC(void *data);
+
+//extern void TL1D_L2PutHISRQueue(pul_inform_MAC func, void *data);
+
+/*TL1 return the Non-Scheduled Tx TTIs in the specified extended estimation window.*/
+//extern kal_uint8 tl1_eval_ext_est_wnd(kal_uint8 ext_est_wnd);
+#endif
+
+/*****************************************************************************
+ UMAC UT SIMULATE MESSAGE
+*****************************************************************************/
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+typedef struct
+{
+ kal_uint8 ref_count;
+ kal_uint16 msg_len;
+
+ kal_uint8 cfn;
+ kal_uint8 ul_mac_event; /* bit 0: UL DCH setup, */
+ /* bit 1: UL DCH release, */
+ /* bit 2: UL DCH modify */
+ TDD_tx_enable_type_E tx_enable; /* set true if TX data could be sent (min TTI) */
+ kal_bool tx_suspend;
+ kal_uint8 tfc_status[TDD_MAX_UL_TFC];
+ kal_uint8 meas_occasion_ind;
+}tdd_phy_simulate_dch_ul_cctrch_lisr_struct;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+typedef struct
+/*UMAC*/{
+/*UMAC*/ kal_uint8 ref_count;
+/*UMAC*/ kal_uint16 msg_len;
+/*UMAC*/
+/*UMAC*/ kal_uint8 cfn;
+/*UMAC*/ kal_uint8 num_trch;
+/*UMAC*/ TDD_ulTrchData trchInfo[TDD_MAX_TRCH_NUM];
+/*UMAC*/ kal_uint16 tfci;
+/*UMAC*/ kal_uint16 num_data[TDD_MAX_TRCH_NUM];
+/*UMAC*/ kal_uint8 *data[TDD_MAX_TRCH_NUM];
+}tdd_phy_simulate_dch_ul_cctrch_lisr_rsp_struct;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#ifdef __HSUPA_SUPPORT__
+typedef struct
+{
+ kal_uint8 ref_count;
+ kal_uint16 msg_len;
+
+ TDD_etfc_eval_info_req_T etfc_eval_input;
+}tdd_phy_simulate_umac_e_dch_tick_1_struct;
+
+
+typedef struct
+{
+ kal_uint8 ref_count;
+ kal_uint16 msg_len;
+
+ TDD_etfc_eval_info_ind_T etfc_eval_info_ind;
+}tdd_phy_simulate_umac_e_dch_tick_1_rsp_struct;
+
+
+typedef struct
+{
+ kal_uint8 ref_count;
+ kal_uint16 msg_len;
+
+ TDD_edch_data_req_T edch_data_input;
+}tdd_phy_simulate_umac_e_dch_tick_2_struct;
+
+
+typedef struct
+{
+ kal_uint8 ref_count;
+ kal_uint16 msg_len;
+
+ TDD_edch_data_ind_T edch_data_ind;
+}tdd_phy_simulate_umac_e_dch_tick_2_rsp_struct;
+
+typedef struct
+{
+ kal_uint8 ref_count;
+ kal_uint16 msg_len;
+
+ kal_uint8 harq_id;
+ TDD_tdd128_modulation_E modulation;
+}tdd_phy_simulate_umac_e_dch_tick_3_struct;
+#endif
+
+/*****************************************************************************
+ MSC Composer
+*****************************************************************************/
+/* The following definition is used only for MSC composer. */
+typedef union _TDD_local_para_unpack_T
+{
+ tdd_cphy_pch_setup_req_struct cphy_pch_setup_req;
+ tdd_cphy_pch_modify_req_struct cphy_pch_modify_req;
+ tdd_cphy_pch_release_req_struct cphy_pch_release_req;
+ tdd_cphy_fach_setup_req_struct cphy_fach_setup_req;
+ tdd_cphy_fach_release_req_struct cphy_fach_release_req;
+ tdd_cphy_dch_setup_req_struct cphy_dch_setup_req;
+ tdd_cphy_dch_modify_req_struct cphy_dch_modify_req;
+ tdd_cphy_dch_release_req_struct cphy_dch_release_req;
+ tdd_cphy_rach_setup_req_struct cphy_rach_setup_req;
+ tdd_cphy_rach_release_req_struct cphy_rach_release_req;
+ tdd_cphy_hsdsch_setup_req_struct cphy_hsdsch_setup_req;
+ tdd_cphy_hsdsch_modify_req_struct cphy_hsdsch_modify_req;
+ tdd_cphy_hsdsch_release_req_struct cphy_hsdsch_release_req;
+#ifdef __HSUPA_SUPPORT__
+ tdd_cphy_edch_setup_req_struct cphy_edch_setup_req;
+ tdd_cphy_edch_modify_req_struct cphy_edch_modify_req;
+ tdd_cphy_edch_release_req_struct cphy_edch_release_req;
+#endif
+ tdd_cphy_measurement_config_dmo_req_struct cphy_measurement_config_dmo_req;
+} TDD_local_para_unpack_T;
+
+typedef struct _TDD_msg_buf_unpack_T /* Buffer of message container */
+{
+ kal_uint8 channel_id; /* Channel ID */
+ msg_type msg_id; /* Message ID */
+ kal_uint16 buff_size; /* Buffer size */
+ TDD_local_para_unpack_T buffer; /* Channel configuration message buffer */
+} TDD_msg_buf_unpack_T;
+
+typedef struct _TDD_cphy_msg_container_req_unpack_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 at_ref; /* Reference channge of activation time.
+ 0 : Ref channel is the released channel.
+ There should be ch to be released
+ 1 : Ref channel is the setup channel.
+ There should be ch to be setup.*/
+
+ /*
+ meas_control_E meas_control; // Indicate whether TL1 need to not to resume meas. after apply corresponding buffer's config.
+ kal_int8 idx_intra_freq; // [Range]: 0 ~ 2. Indicate which frequency in the array uarfcn[TDD_MAX_UMTS_FREQ] is intra-frequency, -1 means invalid
+ */
+ kal_uint8 rab_domain_field; /* BIT0: CS present,
+ BIT1: PS present */
+
+ kal_int16 rx_cfn; /* Indicate peer message receive cfn. Ex: tti = 4, receive frame number : 0,1,2,3. rx_cfn = 3 (set by tl1)
+ [Range]: -1 ~ 255.
+ -1 : Means upper layer internal control
+ */
+
+ kal_uint8 msg_num; /* # of included msg. 1 ~ 4 */
+ TDD_msg_buf_unpack_T msg_buffer[4]; /* List of msg buffer for included channel msg */
+
+ /* [R5R6] For HS-DSCH and E-DCH */
+ kal_uint8 h_msg_num; /* # of included H-msg. 0~2 */
+ TDD_msg_buf_unpack_T h_msg_buffer[2]; /* List of msg buffer for included channel msg */
+ kal_uint8 e_msg_num; /* # of included E-msg. 0~2 */
+ TDD_msg_buf_unpack_T e_msg_buffer[2]; /* List of msg buffer for included channel msg */
+//#if defined( __UMTS_R9__ ) && defined ( __AST3002__ )
+ kal_uint8 dmo_msg_num; /* # of included dmo-msg. 0~1 */
+ TDD_msg_buf_unpack_T dmo_msg_buffer[1]; /* List of msg buffer for included channel msg */
+ //#endif
+
+} tdd_cphy_msg_container_req_unpack_struct;
+
+typedef struct _TDD_cphy_channel_quality_status_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_triggered;
+} tdd_cphy_channel_quality_status_ind_struct;
+
+//add for TDD SAR
+#if 1 //__TDD_TX_PWR_REDUCE__
+typedef struct _tl1_umts_max_tx_pwr_red_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool valid;
+ kal_uint8 umts_power_reduction_in_edb[20][2];
+ /*SAR_BAND_UMTS_TDSCDMA_A_BAND_2010 = 21; [0][0],[0][1] (first for no upa or dpa, second for upa or dpa)
+ SAR_BAND_UMTS_TDSCDMA_F_BAND_1880 = 22; [1][0],[1][1]
+ SAR_BAND_UMTS_TDSCDMA_E_BAND_2300 = 23; [2][0],[2][1]
+ SAR_BAND_UMTS_TDSCDMA_A_BAND_1900 = 24; [3][0],[3][1]
+ SAR_BAND_UMTS_TDSCDMA_B_BAND_1850 = 25; [4][0],[4][1]
+ SAR_BAND_UMTS_TDSCDMA_C_BAND_1910 = 27; [5][0],[5][1]
+ SAR_BAND_UMTS_TDSCDMA_D_BAND_2570 = 28; [6][0],[6][1]*/
+
+/* add power reduction value for ANT1 (op=9/10).
+* when user only specify one set of values by using op=1/3, L4C help copy parameters from umts_power_reduction_in_edb[] to umts_power_reduction_in_edb_ANT1[]*/
+ kal_uint8 umts_power_reduction_in_edb_tas[20][2/*Service*/];
+
+}tl1_umts_max_tx_pwr_red_req_struct;
+#endif
+
+#ifdef __RF_SCAN_FOR_DESENSE_TEST__
+typedef struct _l4ctl1_rssi_measurement_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_int32 rssi1;
+ kal_int32 rssi0;
+}l4ctl1_rssi_measurement_ind_struct;
+#else
+typedef struct _l4ctl1_rssi_measurement_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_int32 rssi_edBm;
+}l4ctl1_rssi_measurement_ind_struct;
+#endif
+
+
+typedef struct _tdd_cphy_duplex_mode_change_req_struct
+{
+ LOCAL_PARA_HDR
+ TDD_duplex_mode_info_T duplex_mode_info;
+} tdd_cphy_duplex_mode_change_req_struct;
+
+typedef struct _tdd_cphy_duplex_mode_change_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool result;
+} tdd_cphy_duplex_mode_change_cnf_struct;
+
+//251 = 63360*4 +128+64+2*128 BYTE=32128 *8(MAX HARE)=251K
+//126 =253440*4+8*2*16*64=1030144bit/8=128768byte/1024=125.8K ALIGN 128 BYTE
+//#define HARQ_BUFFER_MAX_SIZE_DEFINE (69632) //move to td_dpa.h
+
+//TL1 AND MAC SHARE RX data buffer define
+
+/*Weimin. Same as TDD_gRxPchBuffQueueSize, TDD_MAX_MAC_PCH_PDU_NUM in tl1_cnst.h*/
+#define DL_PCH_DATA_BUF_NUM 2
+#define DL_DCH_DATA_BUF_NUM 8
+#define HSDSCH_DATA_BUF_NUM 12
+#define DL_DCH_BUF_SIZE 1472 //10240/8+32*2+32*4=1472
+#define HSDSCH_DATA_BUF_SIZE 1860 //14043/8+45*2=1846
+
+/*//////////////////////////////////////below - interface for MT6291////////////////////////*/
+typedef struct __MAC_TO_TL1_RX_BUF_T_
+{
+ kal_uint32 EmiBufFlag; //when MAC fill one avaliable EMI buf, set to true, and TL1 can configure this buffer to RXBRP
+ //when TL1 configure this buffer to RXBRP, set to false
+ //kal_uint32 EmiBufIndex; //MAC use, no need any more
+ kal_uint32 EmiBufAdress; //TL1 use
+ kal_uint32 padding; //reserved
+}MAC_TO_TL1_RX_BUF_T;
+
+//TDSCDMA SLT Status
+#if defined(__IC_SLT__)
+#define TDSCDMA_SLT_DONE_PATTERN 0x3535
+#define TDSCDMA_SLT_SUCCESS_PATTERN 0xF7F7
+typedef struct _TL1_SLT_CC_INFO_T_
+{
+ kal_uint16 tl1SltDonePattern;
+ kal_uint16 tl1SltResult;
+
+ kal_uint8 rxFinalStatus;
+ kal_uint8 txResult;
+ kal_uint16 duration; //ms
+
+}TL1_SLT_CC_INFO_T;
+#endif
+
+/*move to tl1_cnst.h*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*add include file to share a defined varialbe -- dose not work*/
+//@2014/12/11, set tick2_output->data non-shared memory
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+typedef struct __MAC_TO_TL1_EDCH_BUF_T__
+{
+ kal_uint32 TDD_gMACeiPDU[TDD_MAX_NUM_OF_EDCH_HARQ_PROCESS][TDD_MAC_E_PDU_MEMORY_SIZE / 4];
+}MAC_TO_TL1_EDCH_BUF_T;
+
+
+/*move to tl1_cnst.h*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+typedef struct _MAC_HS_Pdu_Buf_T_
+{
+ kal_uint8 tMacHsPduBufferArray[TDD_MAX_MAC_HS_PDU_NUM][TDD_mBYTE_SIZE_TO_32_BYTE_ALIGN_INC(TDD_MAX_HS_PDU_SIZE_IN_BYTES + TDD_DL_ADR_OFFSET)];
+}MAC_HS_Pdu_Buf_T;
+
+/*move to tl1_cnst.h*/
+#if 0
+/* under construction !*/
+/* under construction !*/
+#endif
+
+typedef struct _MAC_R4_Pdu_Buf_T
+{
+ kal_uint8 tMacR4PduBufferArray[TDD_MAX_MAC_DCH_PDU_NUM][TDD_MAX_MAC_DCH_PDU_SIZE];
+}MAC_R4_Pdu_Buf_T;
+
+typedef struct _MAC_Pch_Pdu_Buf_T
+{
+ kal_uint8 tMacPchPduBufferArray[TDD_MAX_MAC_PCH_PDU_NUM][TDD_MAX_MAC_PCH_PDU_SIZE];
+}MAC_Pch_Pdu_Buf_T;
+
+typedef struct _MAC_Pch_Pdus_Buf_T
+{
+ kal_uint8 tMacPchPdusBufferArray[TDD_MAX_MAC_PCH_PDU_NUM*TDD_MAX_MAC_PCH_PDU_SIZE];
+}MAC_Pch_Pdus_Buf_T;
+
+
+//TL1 and MAC cross core IRQ trigger Type define
+typedef enum _TL1_and_MAC_IRQ_TYPE_T
+{
+ //TL1_TO_MAC_IRQ_TYPE
+ TL1_EDCH_TICK1_START_TRIGGER = 0x1000,
+ TL1_EDCH_TICK2_START_TRIGGER,
+ TL1_UL_DCH_TICK_START_TRIGGER,
+ TL1_UL_DCH_PREPARE_TX_AHEAD_TRIGGER,
+ TL1_PHY_HSDSCH_DATA_IND_TRIGGER,
+ //MAC_TO_TL1_IRQ_TYPE
+ MAC_EDCH_TICK1_END_TRIGGER = 0x2000,
+ MAC_EDCH_TICK2_END_TRIGGER,
+ MAC_UL_DCH_TICK_END_TRIGGER
+} TL1_and_MAC_IRQ_TYPE_T;
+//****************interface for 6291 between UMAC & TL1 END**********************//
+
+typedef struct _cphy_list_mode_cnf_struct
+{
+ LOCAL_PARA_HDR
+} cphy_list_mode_cnf_struct;
+
+
+typedef struct _T_L1CASE_TX_CHECKSUM_IND
+{
+ kal_uint32 CrpChkSum[16];
+ kal_uint32 BrpRU1ChkSum[16];
+ kal_uint32 BrpRU2ChkSum[16];
+}T_L1CASE_TX_CHECKSUM_IND;
+typedef struct _T_L1CASE_TXTFCI
+{
+ kal_uint16 tfci[16];
+}T_L1CASE_TXTFCI;
+#ifdef __HSUPA_SUPPORT__
+typedef struct _fta_edch_tick_1_output_para_T
+{
+ kal_bool is_user_data_available;
+}fta_edch_tick_1_output_para_T;
+
+typedef struct _fta_edch_tick_retx_set_T
+{
+ kal_uint8 sched_retx_harq_num;
+ kal_uint8 sched_retx_harq_id[4];
+ kal_uint8 non_sched_retx_harq_num;
+ kal_uint8 non_sched_retx_harq_id[4];
+}fta_edch_tick_retx_set_T;
+
+typedef struct _fta_edch_tick_newtx_set_T
+{
+ kal_uint8 sched_newtx_harq_num;
+ kal_uint8 sched_newtx_harq_id[4];
+ kal_uint8 non_sched_newtx_harq_num;
+ kal_uint8 non_sched_newtx_harq_id[4];
+}fta_edch_tick_newtx_set_T;
+
+typedef struct _fta_edch_case_ctrl_para_T
+{
+ kal_bool stub_use_case_set;
+ kal_bool use_case_set;
+ kal_uint8 twait_timeout;
+ kal_uint8 etfci;
+ kal_uint16 data_size;
+ TDD_tdd128_modulation_E modulation;
+ fta_edch_tick_1_output_para_T tick_1_output;
+ fta_edch_tick_retx_set_T tick_retx_set;
+ fta_edch_tick_newtx_set_T tick_newtx_set;
+}fta_edch_case_ctrl_para_T;
+#endif
+
+typedef struct _tl1test_init_req_struct
+{
+ LOCAL_PARA_HDR
+}tl1test_init_req_struct;
+
+typedef enum _tl1test_ul_msgid_T
+{
+ TL1TEST_SET_TFCI,
+ TL1TEST_GET_CHECKSUM,
+ TL1TEST_EDCH_PARAM,
+}tl1test_ul_msgid_T;
+typedef struct _tl1test_ul_param_req_struct
+{
+ LOCAL_PARA_HDR
+ tl1test_ul_msgid_T msgid;
+ T_L1CASE_TXTFCI tfci;
+#ifdef __HSUPA_SUPPORT__
+ fta_edch_case_ctrl_para_T edch_param;
+#endif
+}tl1test_ul_param_req_struct;
+typedef struct _tl1test_ul_info_ind_struct
+{
+ LOCAL_PARA_HDR
+ tl1test_ul_msgid_T msgid;
+
+ T_L1CASE_TX_CHECKSUM_IND checksum;
+}tl1test_ul_info_ind_struct;
+
+#endif
diff --git a/mcu/interface/l1/tl1/tl1cal_ast.h b/mcu/interface/l1/tl1/tl1cal_ast.h
new file mode 100644
index 0000000..209c93d
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1cal_ast.h
@@ -0,0 +1,173 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * tl1cal_ast.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * The structure definition of TL1 AST calibration data
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+#ifndef TL1CAL_AST_H
+#define TL1CAL_AST_H
+
+#include "dcl.h"
+
+#define AST_CAL_TEMP_SECTION (8)
+#define AST_CAL_UARFCN_SECTION (15)
+#define AST_CAL_RX_GAIN_MODEN_MAX (8)
+
+ /*****************************************************************************
+* Constant : TL1_CUSTOM_GPIO_MAX_NUM_OF_DEFINED_DETECT_PIN_NAME
+* Group : Real target, Internals, UL1D common operation
+* Description : Constant to be used to determine the max number of GPIO
+* detection pin names defined so far at AP side GPIO driver
+*****************************************************************************/
+#define TL1_CUSTOM_GPIO_MAX_NUM_OF_DEFINED_DETECT_PIN_NAME (3)
+
+/* ------------------------------------------------------------------------- */
+typedef struct
+{
+ kal_uint16 tempdacData[AST_CAL_TEMP_SECTION];
+}ast_tl1cal_tempdacData_T;
+
+typedef struct
+{
+ kal_uint16 initDac;
+ kal_uint16 slope;
+}ast_tl1cal_afcData_T;
+
+typedef struct
+{
+ kal_uint16 freqTable[AST_CAL_UARFCN_SECTION];
+ kal_int16 compByFreq[AST_CAL_RX_GAIN_MODEN_MAX][AST_CAL_UARFCN_SECTION];
+ kal_int16 compByTemp[AST_CAL_RX_GAIN_MODEN_MAX][AST_CAL_TEMP_SECTION];
+}ast_tl1cal_pathlossData_T;
+
+typedef struct
+{
+ kal_uint16 paData[3][4];
+ kal_int16 paPower[3][4];
+ kal_uint16 freqTable[AST_CAL_UARFCN_SECTION];
+ kal_int16 compByFreq[3][AST_CAL_UARFCN_SECTION];
+ kal_int16 compByTemp[3][AST_CAL_TEMP_SECTION];
+ kal_uint16 paSwitch[2][2];
+ kal_int16 maxPaPower;
+ kal_uint16 maxPaData;
+ kal_int16 maxPower_offset;
+ kal_int16 midgain_offset;
+}ast_tl1cal_txdacData_T;
+
+typedef struct
+{
+ /// first boot-up indicator 1: yes, 0: no (mcu power on ABB auto-cal when is_first_boot is 1)
+ kal_uint16 is_first_boot;
+ /// ABB calibration data
+ kal_uint16 abbData[15];
+}ast_tl1cal_abbData_T;
+
+typedef struct
+{
+ /// CAP ID
+ kal_uint32 capId;
+}ast_tl1cal_capData_T;
+typedef struct
+{
+ kal_int16 pdCompMidChannel[3];
+ kal_int16 pdCompByFreq[AST_CAL_UARFCN_SECTION];
+}ast_tl1cal_txPdData_T;
+
+
+
+/*******************************************************************************
+ * Type Definitions *
+ *******************************************************************************/
+
+/*****************************************************************************
+* Typedef : Tl1CustomDynamicInitDebug
+* Group : Real target, Internals, TL1D common operation
+* Type : structure
+* Description : Internal typedef used by TL1CUSTOM GPIO detection HW setting
+* mechanism
+*****************************************************************************/
+#if 1
+typedef struct
+{
+ kal_uint16 combined_config_index;
+ kal_uint8 first_config_index_base;
+ kal_uint8 second_config_index_base;
+ kal_uint8 third_config_index_base;
+
+ kal_int32 gpio_get_pin_rpc_status;
+ kal_uint32 gpio_return_pin_num[TL1_CUSTOM_GPIO_MAX_NUM_OF_DEFINED_DETECT_PIN_NAME];
+ kal_uint32 gpio_pin_value[TL1_CUSTOM_GPIO_MAX_NUM_OF_DEFINED_DETECT_PIN_NAME];
+ kal_uint32 gpio_combined_pin_value;
+ kal_int32 adc_get_ch_num_rpc_status;
+ DCL_STATUS adc_dcl_handle_status;
+ DCL_STATUS adc_cal_dcl_handle_status;
+ kal_uint32 adc_get_ch_num;
+ kal_uint32 adc_dac_read_result;
+ kal_uint32 adc_volt_translate_result;
+ kal_uint8 adc_volt_level;
+ kal_bool barcode_lid_read_status;
+ kal_uint8 barcode_digit_read_result;
+ kal_uint16 custom_total_set_nums;
+
+} Tl1CustomDynamicInitDebug;
+#endif
+
+#endif
diff --git a/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data.h b/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data.h
new file mode 100644
index 0000000..0ce98e2
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data.h
@@ -0,0 +1,226 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * tl1d_rf_cal_poc_data.h
+ *
+ * Project:
+ * --------
+ * TK6291 Project
+ *
+ * Description:
+ * ------------
+ * poc data struction definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*===============================================================================*/
+
+#ifndef _TL1_RF_CAL_POC_DATA_H_
+#define _TL1_RF_CAL_POC_DATA_H_
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "mml1_rf_cal_def.h"
+#include "tl1d_rf_cid.h"
+
+#if IS_TL1D_RF_COLUMBUS || IS_TL1D_RF_COLUMBUSL
+#include "tl1d_rf_cal_poc_data_columbus.h"
+#elif IS_TL1D_RF_MT6186ME1
+#include "tl1d_rf_cal_poc_data_mt6186me1.h"
+#else
+#include "tl1d_rf_cal_poc_data_org.h"
+#endif
+
+
+#endif //#ifndef _MML1_RF_CC_SHM_DATA_H_
diff --git a/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data_columbus.h b/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data_columbus.h
new file mode 100644
index 0000000..740c884
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data_columbus.h
@@ -0,0 +1,116 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * tl1d_rf_cal_poc_data.h
+ *
+ * Project:
+ * --------
+ * TK6291 Project
+ *
+ * Description:
+ * ------------
+ * poc data struction definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*===============================================================================*/
+
+#ifndef _TL1_RF_CAL_POC_DATA_COLUMBUS_H_
+#define _TL1_RF_CAL_POC_DATA_COLUMBUS_H_
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "mml1_rf_cal_def.h"
+#include "tl1d_rf_cid.h"
+
+/************************************************************/
+/* TrinityE1 definition */
+/************************************************************/
+
+
+typedef struct
+{
+ kal_uint32 verno;
+
+
+
+} TDS_RF_POC_COMP_PER_BAND_T;
+
+
+typedef struct
+{
+ TDS_RF_POC_COMP_PER_BAND_T tds_result[2];
+
+} TDS_RF_POC_COMP_T;
+
+
+/******************************
+* POC Default data
+*******************************/
+#ifdef _TL1_RF_CC_SHM_DATA_C_
+TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT = {0};
+
+#else
+extern TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT;
+#endif
+
+
+
+#endif //#ifndef _MML1_RF_CC_SHM_DATA_H_
diff --git a/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data_mt6186me1.h b/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data_mt6186me1.h
new file mode 100644
index 0000000..9779198
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data_mt6186me1.h
@@ -0,0 +1,570 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * tl1d_rf_cal_poc_data.h
+ *
+ * Project:
+ * --------
+ * TK6291 Project
+ *
+ * Description:
+ * ------------
+ * poc data struction definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*===============================================================================*/
+
+#ifndef _TL1_RF_CAL_POC_DATA_MT6186ME1_H_
+#define _TL1_RF_CAL_POC_DATA_MT6186ME1_H_
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "mml1_rf_cal_def.h"
+#include "tl1d_rf_cid.h"
+
+#define TDS_RF_POC_TX_FDAD_COMP_COEFF_NUM (13)
+#define TDS_PGA_BIAS_COMP_PGA_SLICE_SET_NUM (3)
+
+#define TL1D_RXDC_TIA_GAIN_STEPS (4)
+#define TL1D_RXDC_PGA_GAIN_STEPS (6)
+
+#define TL1D_RXDC_HPM_TIA_GAIN_STEPS (TL1D_RXDC_TIA_GAIN_STEPS)
+#define TL1D_RXDC_HPM_PGA_GAIN_STEPS (TL1D_RXDC_PGA_GAIN_STEPS)
+
+#define TL1D_RFC_RXDFE_FDPM_TAPS_NUM_MAX (7) /*MMRFC_RXIRR_FILT_TAPS_NUM*/
+#define TL1D_RXIRR_MAX_TONE_PAIRS (3) /*from MMRFC_RXIRR_MAX_TONE_PAIRS*/
+
+#define TL1D_DET_FE_GAIN_STEPS (2 ) /* from MMRFC_DET_FE_GAIN_STEPS */
+#define TL1D_DET_GAIN_STEPS (10 ) /* from MMRFC_DET_GAIN_STEPS */
+#define TL1D_DET_EQLPF_TAP_NUM (13) /* from MMRFC_DET_EQLPF_TAP_NUM */
+#define TL1D_TX_DNL_PGA_A_GAIN_STEPS (21) /* from MMRFC_TX_DNL_PGA_A_GAIN_STEPS */
+#define TL1D_TX_DNL_PGA_B_GAIN_STEPS (10 ) /* from MMRFC_TX_DNL_PGA_B_GAIN_STEPS */
+#define TL1D_TX_DNL_PGA_AUX_GAIN_STEPS (7 ) /* from MMRFC_TX_DNL_PGA_AUX_GAIN_STEPS */
+#define TL1D_TX_PGA_A_SLICE_NUM (5 ) /* from MMRFC_TX_PGA_A_SLICE_NUM */
+#define TL1D_TX_PGA_B_SLICE_NUM (2 ) /* from MMRFC_TX_PGA_B_SLICE_NUM */
+#define TL1D_ANT_NUM (2 ) /* from MMRFC_ANT_NUM */
+
+#define TL1D_TX_DNL_PGA_TOTAL_NUM (TL1D_TX_DNL_PGA_A_GAIN_STEPS + TL1D_TX_DNL_PGA_AUX_GAIN_STEPS -1)
+#define TL1D_TX_PGA_SLICE_NUM (TL1D_TX_PGA_A_SLICE_NUM + TL1D_TX_PGA_B_SLICE_NUM)/* from MMRFC_TX_PGA_SLICE_NUM*/
+#define TL1D_TX_COARSE_DC_COMP_PGA_SLICE_SET_NUM (TL1D_TX_PGA_SLICE_NUM)//Need to check with owner
+/*Below define MML1 interface Diff size */
+#define TL1D_TX_PGA_SLICE_NUM_MML1_INTERFACE (6)/* from MMRFC_TX_PGA_SLICE_NUM*/
+#define TL1D_TX_IQ_COMP_PGA_SLICE_SET_MML1_INTERFACE (6)/* MML1_TX_IQ_COMP_PGA_SLICE_SET_NUM*/
+
+typedef enum
+{
+ TDS_RF_POC_TX_FMT_S2P11,
+ TDS_RF_POC_TX_FMT_S3P10,
+}TDS_RF_POC_TX_FDAD_COEFF_FORMAT_E;
+
+#if 0//IS_TL1D_DIMENSION_CHECK_ENABLE
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif/*IS_TL1D_DIMENSION_CHECK_ENABLE*/
+
+/******************************
+* Rx POC Part
+*******************************/
+typedef struct
+{
+ kal_int32 gain_est[TL1D_RXIRR_MAX_TONE_PAIRS];
+ kal_int32 gain_est_hw;
+ kal_int32 phase_est_hw;
+ kal_int32 freq_dep_phase_est[TL1D_RXIRR_MAX_TONE_PAIRS];
+ kal_int32 freq_dep_filt[TL1D_RFC_RXDFE_FDPM_TAPS_NUM_MAX]; ///< Valid for 2-point meas.
+} TDS_RF_POC_RX_IRR_COMP_T;
+
+
+typedef struct
+{
+ kal_int32 dc_i;
+ kal_int32 dc_q;
+} TDS_RF_POC_RX_DC_COMP_T;
+
+typedef struct
+{
+ TDS_RF_POC_RX_DC_COMP_T rx_dc[TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+} TDS_RF_POC_RX_DC_HPM_COMP_T;
+
+
+/******************************
+* Tx DET POC Part
+*******************************/
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+} TDS_RF_POC_DET_FREQ_DEP_T;
+
+typedef struct
+{
+ TDS_RF_POC_DET_FREQ_DEP_T coef[TL1D_DET_EQLPF_TAP_NUM];
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+} TDS_DET_FDADPCB_EQLPF_COMP_T;
+
+typedef struct
+{
+ kal_int32 gain_est_hw; //FIIQ gain
+ kal_int32 phase_est_hw; //FIIQ phase
+ TDS_DET_FDADPCB_EQLPF_COMP_T fd_ad_pcb; //FDIQ, AD coefficient, 3G do not contain PCB information
+} TDS_RF_POC_DET_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int32 dc_i;
+ kal_int32 dc_q;
+} TDS_RF_POC_DET_DC_COMP_T;
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoc_i; /* MRX coarse DC offset I channel */
+ kal_uint32 mrx_cdcoc_q; /* MRX coarse DC offset Q channel */
+}TDS_RF_POC_MRX_COARSE_DC_T;
+
+/******************************
+* Tx FOWRAD POC Part
+*******************************/
+typedef struct{
+ kal_int32 gain_est;
+ kal_int32 phase_est;
+} TDS_RF_POC_TX_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int32 dc_est_i;
+ kal_int32 dc_est_q;
+} TDS_RF_POC_TX_DC_COMP_T;
+
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+
+} TDS_RF_POC_TX_CDCOC_COMP_T;
+
+typedef struct
+{
+ TDS_RF_POC_TX_CDCOC_COMP_T comp_tab[TL1D_TX_COARSE_DC_COMP_PGA_SLICE_SET_NUM];
+
+} TDS_RF_POC_TX_CDCOC_COMP_TAB_T;
+
+typedef struct
+{
+ kal_int16 i_part;
+ kal_int16 q_part;
+
+} TDS_RF_POC_TX_FDAD_COMP_COEFF_UNIT_T;
+
+typedef struct
+{
+ TDS_RF_POC_TX_FDAD_COMP_COEFF_UNIT_T cof[TDS_RF_POC_TX_FDAD_COMP_COEFF_NUM];
+
+} TDS_RF_POC_TX_FDAD_COMP_COEFF_T;
+
+
+typedef struct
+{
+
+
+ kal_uint32 verno;
+
+
+ /* RX IRR */
+ TDS_RF_POC_RX_IRR_COMP_T rx_irr_hpm[TL1D_ANT_NUM];
+
+ /* RX DC */
+ #if IS_TRF_RXDC_GXE_SUPPORT
+ TDS_RF_POC_RX_DC_COMP_T rx_dc_hpm[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ TDS_RF_POC_RX_DC_COMP_T rx_dc_hpm_gxe[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ TDS_RF_POC_RX_DC_COMP_T rx_dig_dc_hpm[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ TDS_RF_POC_RX_DC_COMP_T rx_dig_dc_hpm_gxe[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ #else
+ TDS_RF_POC_RX_DC_COMP_T rx_dc_hpm[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ TDS_RF_POC_RX_DC_COMP_T rx_dig_dc_hpm[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ #endif
+ /* DET IQ/DC/DNL Forward */
+ kal_int32 det_dnl[TL1D_DET_GAIN_STEPS];
+
+ TDS_RF_POC_DET_IQ_COMP_T det_iq[TL1D_DET_FE_GAIN_STEPS];
+ TDS_RF_POC_DET_DC_COMP_T det_dc[TL1D_DET_GAIN_STEPS];
+
+ /* DET Coarse DCOC */
+ TDS_RF_POC_MRX_COARSE_DC_T det_cdcoc[TL1D_DET_GAIN_STEPS];
+
+ TDS_RF_POC_DET_DC_COMP_T det_dc_txlpb[TL1D_DET_GAIN_STEPS];
+ /* DET Coarse DCOC */
+ TDS_RF_POC_MRX_COARSE_DC_T det_cdcoc_txlpb[TL1D_DET_GAIN_STEPS];
+ /* TX LPF*/
+ kal_int32 tx_lpf_abb_rsel;
+ kal_int32 tx_lpf_abb_csel_1;
+ kal_int32 tx_lpf_abb_csel_2;
+
+ /* TX FIIQ/DC/DNL Linear Mode */
+ TDS_RF_POC_TX_IQ_COMP_T tx_iq_lin[TL1D_TX_PGA_SLICE_NUM+1]; //+1 for PGA-AUX
+ TDS_RF_POC_TX_DC_COMP_T tx_dc_lin[TL1D_TX_PGA_SLICE_NUM+1]; //+1 for PGA-AUX
+
+ /*TX CORSE DC*/
+ TDS_RF_POC_TX_CDCOC_COMP_TAB_T tx_cdcoc;
+
+ kal_int32 tx_dnl_lin_pga_a[TL1D_TX_DNL_PGA_TOTAL_NUM];
+
+ /* TX PGA Cap Tuning */
+ kal_uint32 cap_opt_a;
+ kal_uint32 tx_drv_ctunemod;
+
+} TDS_RF_POC_COMP_PER_BAND_T;
+
+typedef struct
+{
+ kal_uint32 tds_pga_bias[TDS_PGA_BIAS_COMP_PGA_SLICE_SET_NUM];
+} TDS_RF_POC_PGA_BIAS_COMP_STRUCT_T;
+
+
+typedef struct
+{
+ TDS_RF_POC_COMP_PER_BAND_T tds_result[2];
+ TDS_RF_POC_PGA_BIAS_COMP_STRUCT_T tds_pga_bias_result[2];
+} TDS_RF_POC_COMP_T;
+
+
+/******************************
+* POC Default data
+*******************************/
+#ifdef _TL1_RF_CC_SHM_DATA_C_
+#if IS_TRF_RXDC_GXE_SUPPORT
+TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT = {
+{{
+
+ 0,
+
+ {{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}},
+ {{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}}},
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ {0,0,0,0,0,0,0,0,0,0},
+ {{0,0,{{{4,4}, {-22,-22}, {74,74}, {-186,-186}, {417,417}, {-1021,-1021}, {3513,3513}, {-1010,-1010}, {401,401}, {-171,-171}, {65,65}, {-18,-18}, {3,3}},1,1}}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ 1,
+ 172,
+ 172,
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {0 ,-18 ,-36 ,-56 ,-78 ,-102 ,-127 ,-154 ,-201 ,-236 ,-277 ,-326 ,-364 ,-455 ,-469 ,-598 ,-707 ,-831 ,-963 ,-1147,-1336,-1525,-1734,-1908,-2106,-2255,-2408},
+ 0xE,
+ 0x6
+},
+{
+
+ 0,
+
+ {{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}},
+ {{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}}},
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ {0,0,0,0,0,0,0,0,0,0},
+ {{0,0,{{{4,4}, {-22,-22}, {74,74}, {-186,-186}, {417,417}, {-1021,-1021}, {3513,3513}, {-1010,-1010}, {401,401}, {-171,-171}, {65,65}, {-18,-18}, {3,3}},1,1}}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ 1,
+ 172,
+ 172,
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {0 ,-18 ,-36 ,-56 ,-78 ,-102 ,-127 ,-154 ,-201 ,-236 ,-277 ,-326 ,-364 ,-455 ,-469 ,-598 ,-707 ,-831 ,-963 ,-1147,-1336,-1525,-1734,-1908,-2106,-2255,-2408},
+ 0x12,
+ 0xB
+}},
+{
+ {{0x44,0x3a,0x4c}},
+ {{0x44,0x3a,0x4c}}
+}};
+
+#else
+TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT = {
+{{
+
+ 0,
+
+ {{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}},
+ {{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}}},
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ {0,0,0,0,0,0,0,0,0,0},
+ {{0,0,{{{4,4}, {-22,-22}, {74,74}, {-186,-186}, {417,417}, {-1021,-1021}, {3513,3513}, {-1010,-1010}, {401,401}, {-171,-171}, {65,65}, {-18,-18}, {3,3}},1,1}}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ 1,
+ 172,
+ 172,
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {0 ,-18 ,-36 ,-56 ,-78 ,-102 ,-127 ,-154 ,-201 ,-236 ,-277 ,-326 ,-364 ,-455 ,-469 ,-598 ,-707 ,-831 ,-963 ,-1147,-1336,-1525,-1734,-1908,-2106,-2255,-2408},
+ 0xE,
+ 0x6
+},
+{
+
+ 0,
+
+ {{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}},
+ {{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}}},
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ {0,0,0,0,0,0,0,0,0,0},
+ {{0,0,{{{4,4}, {-22,-22}, {74,74}, {-186,-186}, {417,417}, {-1021,-1021}, {3513,3513}, {-1010,-1010}, {401,401}, {-171,-171}, {65,65}, {-18,-18}, {3,3}},1,1}}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ 1,
+ 172,
+ 172,
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {0 ,-18 ,-36 ,-56 ,-78 ,-102 ,-127 ,-154 ,-201 ,-236 ,-277 ,-326 ,-364 ,-455 ,-469 ,-598 ,-707 ,-831 ,-963 ,-1147,-1336,-1525,-1734,-1908,-2106,-2255,-2408},
+ 0x12,
+ 0xB
+}},
+{
+ {{0x44,0x3a,0x4c}},
+ {{0x44,0x3a,0x4c}}
+}};
+#endif
+#else
+extern TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT;
+#endif
+
+#endif //#ifndef _MML1_RF_CC_SHM_DATA_H_
diff --git a/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data_org.h b/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data_org.h
new file mode 100644
index 0000000..fb84cc0
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1d_rf_cal_poc_data_org.h
@@ -0,0 +1,964 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * tl1d_rf_cal_poc_data.h
+ *
+ * Project:
+ * --------
+ * TK6291 Project
+ *
+ * Description:
+ * ------------
+ * poc data struction definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*===============================================================================*/
+
+#ifndef _TL1_RF_CAL_POC_DATA_ORG_H_
+#define _TL1_RF_CAL_POC_DATA_ORG_H_
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "mml1_rf_cal_def.h"
+#include "tl1d_rf_cid.h"
+
+/************************************************************/
+/* TrinityE1 definition */
+/************************************************************/
+
+#if (IS_TL1D_RF_TRINITYE1 || IS_TL1D_RF_MT6185M|| IS_TL1D_RF_MT6186)
+#define TDS_RF_POC_TX_FDAD_COMP_COEFF_NUM (13)
+#define TDS_PGA_BIAS_COMP_PGA_SLICE_SET_NUM (3)
+
+#if IS_TL1D_RF_TRINITYE1
+/*******************************************************************************
+** RFC dimension define
+*******************************************************************************/
+
+#define TL1D_RXDC_TIA_GAIN_STEPS (3)
+#define TL1D_RXDC_PGA_GAIN_STEPS (6)
+
+#define TL1D_RXDC_HPM_TIA_GAIN_STEPS (TL1D_RXDC_TIA_GAIN_STEPS)
+#define TL1D_RXDC_HPM_PGA_GAIN_STEPS (TL1D_RXDC_PGA_GAIN_STEPS)
+
+#define TL1D_RFC_RXDFE_FDPM_TAPS_NUM_MAX (5)
+#define TL1D_RXIRR_MAX_TONE_PAIRS (3) /*from MMRFC_RXIRR_MAX_TONE_PAIRS*/
+
+#define TL1D_DET_FE_GAIN_STEPS (2 ) /* from MMRFC_DET_FE_GAIN_STEPS */
+#define TL1D_DET_PGA_BW_NUM (1 ) /* from MMRFC_DET_PGA_BW_NUM */
+#define TL1D_DET_GAIN_STEPS (10 ) /* from MMRFC_DET_GAIN_STEPS MML1_DET_DC_COMP_SET */
+#define TL1D_DET_EQLPF_TAP_NUM (11) /* from MMRFC_DET_EQLPF_TAP_NUM */
+#define TL1D_TX_DNL_PGA_A_GAIN_STEPS (22) /* from MMRFC_TX_DNL_PGA_A_GAIN_STEPS */
+#define TL1D_TX_DNL_PGA_B_GAIN_STEPS (0 ) /* from MMRFC_TX_DNL_PGA_B_GAIN_STEPS */
+#define TL1D_TX_DNL_PGA_AUX_GAIN_STEPS (5 ) /* from MMRFC_TX_DNL_PGA_AUX_GAIN_STEPS */
+#define TL1D_TX_PGA_A_SLICE_NUM (5 ) /* from MMRFC_TX_PGA_A_SLICE_NUM */
+#define TL1D_TX_PGA_B_SLICE_NUM (2 ) /* from MMRFC_TX_PGA_B_SLICE_NUM */
+#define TL1D_ANT_NUM (2 ) /* from MMRFC_ANT_NUM */
+
+#define TL1D_TX_DNL_PGA_TOTAL_NUM (TL1D_TX_DNL_PGA_A_GAIN_STEPS + TL1D_TX_DNL_PGA_B_GAIN_STEPS + TL1D_TX_DNL_PGA_AUX_GAIN_STEPS)
+#define TL1D_TX_PGA_SLICE_NUM (TL1D_TX_PGA_A_SLICE_NUM + TL1D_TX_PGA_B_SLICE_NUM)/* from MMRFC_TX_PGA_SLICE_NUM*/
+#define TL1D_TX_COARSE_DC_COMP_PGA_SLICE_SET_NUM (6)//Need to check with owner
+#define TL1D_TX_PGA_SLICE_NUM_MML1_INTERFACE (6)/* from MMRFC_TX_PGA_SLICE_NUM*/
+#define TL1D_TX_IQ_COMP_PGA_SLICE_SET_MML1_INTERFACE (6)/* MML1_TX_IQ_COMP_PGA_SLICE_SET_NUM*/
+
+#elif IS_TL1D_RF_MT6185M //For MT6185
+
+#define TL1D_RXDC_TIA_GAIN_STEPS (4)
+#define TL1D_RXDC_PGA_GAIN_STEPS (6)
+
+#define TL1D_RXDC_HPM_TIA_GAIN_STEPS (TL1D_RXDC_TIA_GAIN_STEPS)
+#define TL1D_RXDC_HPM_PGA_GAIN_STEPS (TL1D_RXDC_PGA_GAIN_STEPS)
+
+#define TL1D_RFC_RXDFE_FDPM_TAPS_NUM_MAX (7) /*MMRFC_RXIRR_FILT_TAPS_NUM*/
+#define TL1D_RXIRR_MAX_TONE_PAIRS (3) /*from MMRFC_RXIRR_MAX_TONE_PAIRS*/
+
+#define TL1D_DET_FE_GAIN_STEPS (2 ) /* from MMRFC_DET_FE_GAIN_STEPS */
+#define TL1D_DET_GAIN_STEPS (10 ) /* from MMRFC_DET_GAIN_STEPS */
+#define TL1D_DET_EQLPF_TAP_NUM (13) /* from MMRFC_DET_EQLPF_TAP_NUM */
+#define TL1D_TX_DNL_PGA_A_GAIN_STEPS (21) /* from MMRFC_TX_DNL_PGA_A_GAIN_STEPS */
+#define TL1D_TX_DNL_PGA_B_GAIN_STEPS (10 ) /* from MMRFC_TX_DNL_PGA_B_GAIN_STEPS */
+#define TL1D_TX_DNL_PGA_AUX_GAIN_STEPS (7 ) /* from MMRFC_TX_DNL_PGA_AUX_GAIN_STEPS */
+#define TL1D_TX_PGA_A_SLICE_NUM (5 ) /* from MMRFC_TX_PGA_A_SLICE_NUM */
+#define TL1D_TX_PGA_B_SLICE_NUM (2 ) /* from MMRFC_TX_PGA_B_SLICE_NUM */
+#define TL1D_ANT_NUM (2 ) /* from MMRFC_ANT_NUM */
+
+#define TL1D_TX_DNL_PGA_TOTAL_NUM (TL1D_TX_DNL_PGA_A_GAIN_STEPS + TL1D_TX_DNL_PGA_AUX_GAIN_STEPS -1)
+#define TL1D_TX_PGA_SLICE_NUM (TL1D_TX_PGA_A_SLICE_NUM + TL1D_TX_PGA_B_SLICE_NUM)/* from MMRFC_TX_PGA_SLICE_NUM*/
+#define TL1D_TX_COARSE_DC_COMP_PGA_SLICE_SET_NUM (TL1D_TX_PGA_SLICE_NUM)//Need to check with owner
+/*Below define MML1 interface Diff size */
+#define TL1D_TX_PGA_SLICE_NUM_MML1_INTERFACE (6)/* from MMRFC_TX_PGA_SLICE_NUM*/
+#define TL1D_TX_IQ_COMP_PGA_SLICE_SET_MML1_INTERFACE (6)/* MML1_TX_IQ_COMP_PGA_SLICE_SET_NUM*/
+#elif IS_TL1D_RF_MT6186 //For MT6185
+
+#define TL1D_RXDC_TIA_GAIN_STEPS (4)
+#define TL1D_RXDC_PGA_GAIN_STEPS (6)
+
+#define TL1D_RXDC_HPM_TIA_GAIN_STEPS (TL1D_RXDC_TIA_GAIN_STEPS)
+#define TL1D_RXDC_HPM_PGA_GAIN_STEPS (TL1D_RXDC_PGA_GAIN_STEPS)
+
+#define TL1D_RFC_RXDFE_FDPM_TAPS_NUM_MAX (7) /*MMRFC_RXIRR_FILT_TAPS_NUM*/
+#define TL1D_RXIRR_MAX_TONE_PAIRS (3) /*from MMRFC_RXIRR_MAX_TONE_PAIRS*/
+
+#define TL1D_DET_FE_GAIN_STEPS (2 ) /* from MMRFC_DET_FE_GAIN_STEPS */
+#define TL1D_DET_GAIN_STEPS (10 ) /* from MMRFC_DET_GAIN_STEPS */
+#define TL1D_DET_EQLPF_TAP_NUM (13) /* from MMRFC_DET_EQLPF_TAP_NUM */
+#define TL1D_TX_DNL_PGA_A_GAIN_STEPS (21) /* from MMRFC_TX_DNL_PGA_A_GAIN_STEPS */
+#define TL1D_TX_DNL_PGA_B_GAIN_STEPS (10 ) /* from MMRFC_TX_DNL_PGA_B_GAIN_STEPS */
+#define TL1D_TX_DNL_PGA_AUX_GAIN_STEPS (7 ) /* from MMRFC_TX_DNL_PGA_AUX_GAIN_STEPS */
+#define TL1D_TX_PGA_A_SLICE_NUM (5 ) /* from MMRFC_TX_PGA_A_SLICE_NUM */
+#define TL1D_TX_PGA_B_SLICE_NUM (2 ) /* from MMRFC_TX_PGA_B_SLICE_NUM */
+#define TL1D_ANT_NUM (2 ) /* from MMRFC_ANT_NUM */
+
+#define TL1D_TX_DNL_PGA_TOTAL_NUM (TL1D_TX_DNL_PGA_A_GAIN_STEPS + TL1D_TX_DNL_PGA_AUX_GAIN_STEPS -1)
+#define TL1D_TX_PGA_SLICE_NUM (TL1D_TX_PGA_A_SLICE_NUM + TL1D_TX_PGA_B_SLICE_NUM)/* from MMRFC_TX_PGA_SLICE_NUM*/
+#define TL1D_TX_COARSE_DC_COMP_PGA_SLICE_SET_NUM (TL1D_TX_PGA_SLICE_NUM)//Need to check with owner
+/*Below define MML1 interface Diff size */
+#define TL1D_TX_PGA_SLICE_NUM_MML1_INTERFACE (6)/* from MMRFC_TX_PGA_SLICE_NUM*/
+#define TL1D_TX_IQ_COMP_PGA_SLICE_SET_MML1_INTERFACE (6)/* MML1_TX_IQ_COMP_PGA_SLICE_SET_NUM*/
+#endif
+
+typedef enum
+{
+ TDS_RF_POC_TX_FMT_S2P11,
+ TDS_RF_POC_TX_FMT_S3P10,
+}TDS_RF_POC_TX_FDAD_COEFF_FORMAT_E;
+
+#if 0//IS_TL1D_DIMENSION_CHECK_ENABLE
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif/*IS_TL1D_DIMENSION_CHECK_ENABLE*/
+
+/******************************
+* Rx POC Part
+*******************************/
+typedef struct
+{
+ kal_int32 gain_est[TL1D_RXIRR_MAX_TONE_PAIRS];
+ kal_int32 gain_est_hw;
+ kal_int32 phase_est_hw;
+ kal_int32 freq_dep_phase_est[TL1D_RXIRR_MAX_TONE_PAIRS];
+ kal_int32 freq_dep_filt[TL1D_RFC_RXDFE_FDPM_TAPS_NUM_MAX]; ///< Valid for 2-point meas.
+} TDS_RF_POC_RX_IRR_COMP_T;
+
+
+typedef struct
+{
+ kal_int32 dc_i;
+ kal_int32 dc_q;
+} TDS_RF_POC_RX_DC_COMP_T;
+
+typedef struct
+{
+ TDS_RF_POC_RX_DC_COMP_T rx_dc[TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+} TDS_RF_POC_RX_DC_HPM_COMP_T;
+
+
+/******************************
+* Tx DET POC Part
+*******************************/
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+} TDS_RF_POC_DET_FREQ_DEP_T;
+
+typedef struct
+{
+ TDS_RF_POC_DET_FREQ_DEP_T coef[TL1D_DET_EQLPF_TAP_NUM];
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+} TDS_DET_FDADPCB_EQLPF_COMP_T;
+
+typedef struct
+{
+ kal_int32 gain_est_hw; //FIIQ gain
+ kal_int32 phase_est_hw; //FIIQ phase
+ TDS_DET_FDADPCB_EQLPF_COMP_T fd_ad_pcb; //FDIQ, AD coefficient, 3G do not contain PCB information
+} TDS_RF_POC_DET_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int32 dc_i;
+ kal_int32 dc_q;
+} TDS_RF_POC_DET_DC_COMP_T;
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoc_i; /* MRX coarse DC offset I channel */
+ kal_uint32 mrx_cdcoc_q; /* MRX coarse DC offset Q channel */
+}TDS_RF_POC_MRX_COARSE_DC_T;
+
+/******************************
+* Tx FOWRAD POC Part
+*******************************/
+typedef struct{
+ kal_int32 gain_est;
+ kal_int32 phase_est;
+} TDS_RF_POC_TX_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int32 dc_est_i;
+ kal_int32 dc_est_q;
+} TDS_RF_POC_TX_DC_COMP_T;
+
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+
+} TDS_RF_POC_TX_CDCOC_COMP_T;
+
+typedef struct
+{
+ TDS_RF_POC_TX_CDCOC_COMP_T comp_tab[TL1D_TX_COARSE_DC_COMP_PGA_SLICE_SET_NUM];
+
+} TDS_RF_POC_TX_CDCOC_COMP_TAB_T;
+
+typedef struct
+{
+ kal_int16 i_part;
+ kal_int16 q_part;
+
+} TDS_RF_POC_TX_FDAD_COMP_COEFF_UNIT_T;
+
+typedef struct
+{
+ TDS_RF_POC_TX_FDAD_COMP_COEFF_UNIT_T cof[TDS_RF_POC_TX_FDAD_COMP_COEFF_NUM];
+
+} TDS_RF_POC_TX_FDAD_COMP_COEFF_T;
+
+
+typedef struct
+{
+
+
+ kal_uint32 verno;
+
+
+ /* RX IRR */
+ TDS_RF_POC_RX_IRR_COMP_T rx_irr_hpm[TL1D_ANT_NUM];
+
+ /* RX DC */
+ #if IS_TRF_RXDC_GXE_SUPPORT
+ TDS_RF_POC_RX_DC_COMP_T rx_dc_hpm[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ TDS_RF_POC_RX_DC_COMP_T rx_dc_hpm_gxe[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ TDS_RF_POC_RX_DC_COMP_T rx_dig_dc_hpm[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ TDS_RF_POC_RX_DC_COMP_T rx_dig_dc_hpm_gxe[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ #else
+ TDS_RF_POC_RX_DC_COMP_T rx_dc_hpm[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ TDS_RF_POC_RX_DC_COMP_T rx_dig_dc_hpm[TL1D_ANT_NUM][TL1D_RXDC_HPM_TIA_GAIN_STEPS][TL1D_RXDC_HPM_PGA_GAIN_STEPS];
+ #endif
+
+ /* DET IQ/DC/DNL Forward */
+ kal_int32 det_dnl[TL1D_DET_GAIN_STEPS];
+
+ TDS_RF_POC_DET_IQ_COMP_T det_iq[TL1D_DET_FE_GAIN_STEPS];
+ TDS_RF_POC_DET_DC_COMP_T det_dc[TL1D_DET_GAIN_STEPS];
+
+ /* DET Coarse DCOC */
+ TDS_RF_POC_MRX_COARSE_DC_T det_cdcoc[TL1D_DET_GAIN_STEPS];
+#if IS_TL1D_RF_MT6186
+ TDS_RF_POC_DET_DC_COMP_T det_dc_txlpb[TL1D_DET_GAIN_STEPS];
+ /* DET Coarse DCOC */
+ TDS_RF_POC_MRX_COARSE_DC_T det_cdcoc_txlpb[TL1D_DET_GAIN_STEPS];
+#endif
+ /* TX LPF*/
+ kal_int32 tx_lpf_abb_rsel;
+ kal_int32 tx_lpf_abb_csel_1;
+ kal_int32 tx_lpf_abb_csel_2;
+
+ /* TX FIIQ/DC/DNL Linear Mode */
+ TDS_RF_POC_TX_IQ_COMP_T tx_iq_lin[TL1D_TX_PGA_SLICE_NUM+1]; //+1 for PGA-AUX
+ TDS_RF_POC_TX_DC_COMP_T tx_dc_lin[TL1D_TX_PGA_SLICE_NUM+1]; //+1 for PGA-AUX
+
+ /*TX CORSE DC*/
+ TDS_RF_POC_TX_CDCOC_COMP_TAB_T tx_cdcoc;
+
+ kal_int32 tx_dnl_lin_pga_a[TL1D_TX_DNL_PGA_TOTAL_NUM];
+
+ /* TX PGA Cap Tuning */
+ kal_uint32 cap_opt_a;
+ kal_uint32 tx_drv_ctunemod;
+
+} TDS_RF_POC_COMP_PER_BAND_T;
+
+typedef struct
+{
+ kal_uint32 tds_pga_bias[TDS_PGA_BIAS_COMP_PGA_SLICE_SET_NUM];
+} TDS_RF_POC_PGA_BIAS_COMP_STRUCT_T;
+
+
+typedef struct
+{
+ TDS_RF_POC_COMP_PER_BAND_T tds_result[2];
+ TDS_RF_POC_PGA_BIAS_COMP_STRUCT_T tds_pga_bias_result[2];
+} TDS_RF_POC_COMP_T;
+
+
+/******************************
+* POC Default data
+*******************************/
+#ifdef _TL1_RF_CC_SHM_DATA_C_
+#if IS_TL1D_RF_TRINITYE1
+TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT = {
+{{
+
+ 0,
+
+ {{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}},{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {0,0,0,0,0},
+ {{0,0,{{{5,5}, {-35,-35}, {144,144}, {-454,-454}, {-350,-350}, {312,312}, {-218,-218}, {127,127}, {-59,-59}, {19,19}, {-3,-3}},0,0}},\
+ {0,0,{{{5,5}, {-36,-36}, {144,144}, {-437,-437}, {-371,-371}, {316,316}, {-215,-215}, {123,123}, {-56,-56}, {18,18}, {-3,-3}},0,0}}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ 0,
+ 0,
+ 0,
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {-156,-147,-163,-172,-190,-208,-234,-233,-287,-374,-398,-516,-626,-906,-288,-341,-400,-462,-623,-908,-624,-894,-295,-328,-406,-471,-634},
+ 0,
+ 0
+},
+{
+
+ 0,
+
+ {{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}},{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {0,0,0,0,0},
+ {{0,0,{{{5,5}, {-35,-35}, {144,144}, {-454,-454}, {-350,-350}, {312,312}, {-218,-218}, {127,127}, {-59,-59}, {19,19}, {-3,-3}},0,0}},\
+ {0,0,{{{5,5}, {-36,-36}, {144,144}, {-437,-437}, {-371,-371}, {316,316}, {-215,-215}, {123,123}, {-56,-56}, {18,18}, {-3,-3}},0,0}}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ 0,
+ 0,
+ 0,
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {-156,-147,-163,-172,-190,-208,-234,-233,-287,-374,-398,-516,-626,-906,-288,-341,-400,-462,-623,-908,-624,-894,-295,-328,-406,-471,-634},
+ 0,
+ 0
+}},
+{
+ {{0x44,0x39,0x4a}},
+ {{0x44,0x39,0x4a}}
+}};
+
+#elif IS_TL1D_RF_MT6185M //For MT6185
+TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT = {
+{{
+
+ 0,
+
+ {{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}},
+ {{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}}},
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ {0,0,0,0,0,0,0,0,0,0},
+ {{0,0,{{{4,4}, {-22,-22}, {74,74}, {-186,-186}, {417,417}, {-1021,-1021}, {3513,3513}, {-1010,-1010}, {401,401}, {-171,-171}, {65,65}, {-18,-18}, {3,3}},1,1}}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ 0,
+ 0,
+ 0,
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {0 ,-18 ,-36 ,-56 ,-78 ,-102 ,-127 ,-154 ,-201 ,-236 ,-277 ,-326 ,-364 ,-455 ,-469 ,-598 ,-707 ,-831 ,-963 ,-1147,-1336,-1525,-1734,-1908,-2106,-2255,-2408},
+ 0xE,
+ 0x6
+},
+{
+
+ 0,
+
+ {{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}},
+ {{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}}},
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ {0,0,0,0,0,0,0,0,0,0},
+ {{0,0,{{{4,4}, {-22,-22}, {74,74}, {-186,-186}, {417,417}, {-1021,-1021}, {3513,3513}, {-1010,-1010}, {401,401}, {-171,-171}, {65,65}, {-18,-18}, {3,3}},1,1}}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ 0,
+ 0,
+ 0,
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {0 ,-18 ,-36 ,-56 ,-78 ,-102 ,-127 ,-154 ,-201 ,-236 ,-277 ,-326 ,-364 ,-455 ,-469 ,-598 ,-707 ,-831 ,-963 ,-1147,-1336,-1525,-1734,-1908,-2106,-2255,-2408},
+ 0x12,
+ 0xB
+}},
+{
+ {{0x44,0x3a,0x4c}},
+ {{0x44,0x3a,0x4c}}
+}};
+#elif IS_TL1D_RF_MT6186 //For MT6185
+TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT = {
+{{
+
+ 0,
+
+ {{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}},
+ {{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}}},
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ #if IS_TRF_RXDC_GXE_SUPPORT
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ #endif
+ {0,0,0,0,0,0,0,0,0,0},
+ {{0,0,{{{4,4}, {-22,-22}, {74,74}, {-186,-186}, {417,417}, {-1021,-1021}, {3513,3513}, {-1010,-1010}, {401,401}, {-171,-171}, {65,65}, {-18,-18}, {3,3}},1,1}}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ 1,
+ 172,
+ 172,
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {0 ,-18 ,-36 ,-56 ,-78 ,-102 ,-127 ,-154 ,-201 ,-236 ,-277 ,-326 ,-364 ,-455 ,-469 ,-598 ,-707 ,-831 ,-963 ,-1147,-1336,-1525,-1734,-1908,-2106,-2255,-2408},
+ 0xE,
+ 0x6
+},
+{
+
+ 0,
+
+ {{{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}},
+ {{0,0,0},0,0,{0,0,0},{0,0,0,1024,0,0,0}}},
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ #if IS_TRF_RXDC_GXE_SUPPORT
+ {{{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}},
+ {{{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}},
+ {{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20},{0x20,0x20}}}},
+ {{{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}}},
+ #endif
+ {0,0,0,0,0,0,0,0,0,0},
+ {{0,0,{{{4,4}, {-22,-22}, {74,74}, {-186,-186}, {417,417}, {-1021,-1021}, {3513,3513}, {-1010,-1010}, {401,401}, {-171,-171}, {65,65}, {-18,-18}, {3,3}},1,1}}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},
+ 1,
+ 172,
+ 172,
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{0,0},{0,0},{0,0},{0,0},{0,0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {0 ,-18 ,-36 ,-56 ,-78 ,-102 ,-127 ,-154 ,-201 ,-236 ,-277 ,-326 ,-364 ,-455 ,-469 ,-598 ,-707 ,-831 ,-963 ,-1147,-1336,-1525,-1734,-1908,-2106,-2255,-2408},
+ 0x12,
+ 0xB
+}},
+{
+ {{0x44,0x3a,0x4c}},
+ {{0x44,0x3a,0x4c}}
+}};
+
+#endif
+#else
+extern TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT;
+#endif
+
+
+/************************************************************/
+/* MT6177&MT6177M definition */
+/************************************************************/
+
+#elif (IS_TL1D_RF_MT6177M ||IS_TL1D_RF_MT6177L)
+
+
+
+typedef struct{
+ kal_int32 gain_est_hw;
+ kal_int32 phase_est_hw;
+ kal_int32 freq_dep_filt[MMRFC_FILT_TAPS_NUM]; ///< Valid for 2-point meas.
+} TDS_RF_POC_RX_IRR_COMP_T;
+
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} TDS_RF_POC_RX_DC_COMP_T;
+
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+} TDS_RF_POC_DET_FREQ_DEP_T;
+
+typedef struct{
+ kal_int32 gain_est_hw;
+ kal_int32 phase_est_hw;
+ TDS_RF_POC_DET_FREQ_DEP_T freq_dep_filt[MMRFC_DET_EQLPF_TAP_NUM]; ///< Valid for 2-point meas.
+ kal_int32 dnl;
+} TDS_RF_POC_DET_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int32 dc_i;
+ kal_int32 dc_q;
+} TDS_RF_POC_DET_DC_COMP_T;
+
+typedef struct
+{
+ kal_int32 gain_est;
+ kal_int32 phase_est;
+ kal_int32 dc_est_i;
+ kal_int32 dc_est_q;
+ kal_int32 freq_dep_phase_tx; ///< temp output for TX FDIQ
+} TDS_RF_POC_TX_IQDC_COMP_T;
+
+
+
+typedef struct{
+ kal_int16 freq_dep_filt_mode1[MMRFC_FILT_TAPS_NUM];
+ kal_int16 freq_dep_filt_mode2[MMRFC_FILT_TAPS_NUM];
+} TDS_RF_POC_TX_FDIQ_COMP_T;
+
+
+typedef struct
+{
+
+ kal_uint32 verno;
+
+ /* RX IRR */
+ TDS_RF_POC_RX_IRR_COMP_T rx_irr_hpm[MMRFC_ANT_NUM]; //3
+ TDS_RF_POC_RX_IRR_COMP_T rx_irr_lpm[MMRFC_ANT_NUM]; //3
+
+ /* RX DC */
+ TDS_RF_POC_RX_DC_COMP_T rx_dc_hpm[MMRFC_RXDC_TIA_GAIN_STEPS][MMRFC_RXDC_PGA_GAIN_STEPS]; //3
+ TDS_RF_POC_RX_DC_COMP_T rx_dc_lpm[MMRFC_RXDC_TIA_GAIN_STEPS][MMRFC_RXDC_PGA_GAIN_STEPS]; //3
+
+ TDS_RF_POC_RX_DC_COMP_T rx_dig_dc_hpm[MMRFC_RXDC_TIA_GAIN_STEPS][MMRFC_RXDC_PGA_GAIN_STEPS]; //3
+
+
+ /* DET */
+ /* Only FDIQ is dependent with sample rates, other redundent items need to be removed in NVRAM/share memory structure */
+ TDS_RF_POC_DET_IQ_COMP_T det_iqdnl[MMRFC_DET_FE_GAIN_STEPS]; //2
+ TDS_RF_POC_DET_DC_COMP_T det_dc[MMRFC_DET_GAIN_STEPS+2]; //15 DET gain step
+
+ kal_uint32 det_coarse_dcoc_cw807; //CW807, V_TXCDCOC1[19:0]
+ kal_uint32 det_coarse_dcoc_cw808; //CW808, V_TXCDCOC2[19:0]
+
+ kal_uint32 tx_lo; //CW714, {2'b00,V_TXLOCAP[6:0],V_TXLOIND,V_TXLOINBIAS[4:0],V_TXLOINBIAS[4:0]}
+ kal_uint8 tx_lo_ind;
+ kal_uint8 tx_lo_capcal_peak_cap; //CW714
+ kal_uint8 tx_lo_in_bias_hpm; //CW714
+ kal_uint8 tx_lo_in_bias_lpm; //CW714
+ /* TX RC */
+ kal_int16 tx_rc_lpf;
+ kal_int16 tx_rc_rcf;
+
+ /* TX IQDC */
+ /* TXIQ: G0, G9, G10, G12a, G14a, G12b, G14b */
+ /* TXDC: G0, G9, G10, G12a, G14a, G12b, G14b, G21 */
+ /* freq_dep_phase_tx is temp output for FDIQ cal */
+ TDS_RF_POC_TX_IQDC_COMP_T tx_iqdc_lin[MMRFC_TX_PGA_SLICE_NUM+1]; //+1 only for DC with PGA-AUX
+ TDS_RF_POC_TX_IQDC_COMP_T tx_iqdc_dpd[MMRFC_TX_PGA_SLICE_NUM+1]; //+1 only for DC with PGA-AUX
+ TDS_RF_POC_TX_FDIQ_COMP_T tx_fdiq[MMRFC_TX_PGA_SLICE_NUM+1];
+
+ /* TX DNL */
+ kal_int16 tx_dnl_lin_pga_a[MMRFC_TX_DNL_PGA_A_SEQ_NUM]; //20 gain diff
+ kal_int16 tx_dnl_lin_pga_b[MMRFC_TX_DNL_PGA_B_SEQ_NUM]; //15 gain diff
+ kal_int16 tx_dnl_dpd_pga_a[MMRFC_TX_DNL_PGA_A_SEQ_NUM]; //20 gain diff
+ kal_int16 tx_dnl_dpd_pga_b[MMRFC_TX_DNL_PGA_B_SEQ_NUM]; //15 gain diff
+
+ /* TX PGA Gain Step */
+ kal_int16 pga_gain_step[MMRFC_TX_PGA_GAIN_STEP_NUM];
+
+ /* TX PGA Cap Tuning */
+ kal_int16 cap_tuning_pga_a;
+ kal_int16 cap_tuning_pga_b;
+
+} TDS_RF_POC_COMP_PER_BAND_T;
+
+typedef struct
+{
+ TDS_RF_POC_COMP_PER_BAND_T tds_result[2];
+} TDS_RF_POC_COMP_T;
+
+
+
+/*POC NVRAM DATA, DON NOT CHANGE*/
+#ifdef _TL1_RF_CC_SHM_DATA_C_
+#if IS_TL1D_RF_MT6177L
+TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT = {
+{{
+
+ 0,
+
+ {{0},{0}},
+ {{0},{0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{0,0,{{5,5}, {-35,-35}, {144,144}, {-454,-454}, {-350,-350}, {312,312}, {-218,-218}, {127,127}, {-59,-59}, {19,19}, {-3,-3}},701},\
+ {0,0,{{5,5}, {-36,-36}, {144,144}, {-437,-437}, {-371,-371}, {316,316}, {-215,-215}, {123,123}, {-56,-56}, {18,18}, {-3,-3}},701}},
+ {{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}},
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 172,
+ 13,
+ {{0},{0},{0},{0},{0},{0},{0},{0}},
+ {{0},{0},{0},{0},{0},{0},{0},{0}},
+ {{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}}},
+ {-156,-147,-163,-172,-190,-208,-234,-233,-287,-374,-398,-516,-626,-906,-288,-341,-400,-462,-623,-908},
+ {-624,-894,-295,-328,-406,-471,-634,-867,-1513,-1505,-1671,-1457,-1583,-1563,-1502,-1520},
+ {0},
+ {0},
+ {0},
+ 0,
+ 0
+},
+{
+
+ 0,
+
+ {{0},{0}},
+ {{0},{0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{0,0,{{5,5}, {-35,-35}, {144,144}, {-454,-454}, {-350,-350}, {312,312}, {-218,-218}, {127,127}, {-59,-59}, {19,19}, {-3,-3}},701},\
+ {0,0,{{5,5}, {-36,-36}, {144,144}, {-437,-437}, {-371,-371}, {316,316}, {-215,-215}, {123,123}, {-56,-56}, {18,18}, {-3,-3}},701}},
+ {{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}},
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 172,
+ 13,
+ {{0},{0},{0},{0},{0},{0},{0},{0}},
+ {{0},{0},{0},{0},{0},{0},{0},{0}},
+ {{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}}},
+ {-156,-147,-163,-172,-190,-208,-234,-233,-287,-374,-398,-516,-626,-906,-288,-341,-400,-462,-623,-908},
+ {-624,-894,-295,-328,-406,-471,-634,-867,-1513,-1505,-1671,-1457,-1583,-1563,-1502,-1520},
+ {0},
+ {0},
+ {0},
+ 0,
+ 0
+}}
+};
+#elif IS_TL1D_RF_MT6177M
+TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT = {
+{{
+
+ 0,
+
+ {{0},{0}},
+ {{0},{0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{0,0,{{5,5}, {-35,-35}, {144,144}, {-454,-454}, {-350,-350}, {312,312}, {-218,-218}, {127,127}, {-59,-59}, {19,19}, {-3,-3}},701},\
+ {0,0,{{5,5}, {-36,-36}, {144,144}, {-437,-437}, {-371,-371}, {316,316}, {-215,-215}, {123,123}, {-56,-56}, {18,18}, {-3,-3}},701}},
+ {{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}},
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 26,
+ 22,
+ {{0},{0},{0},{0},{0}},
+ {{0},{0},{0},{0},{0}},
+ {{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}}},
+ { -136,-160,-160,-184,-192,-208,-240,-256,-296,-344,-408,-496,-640,-896,-304,-336,-408,-496,-640,-904,-1536}, //21
+ { -256,-1536, -1536, -1536, -1536, -1536, -1536,-1536 },
+ {0},
+ {0},
+ {0},
+ 0,
+ 0
+},
+{
+
+ 0,
+
+ {{0},{0}},
+ {{0},{0}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}},{{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0}}},
+ {{0,0,{{5,5}, {-35,-35}, {144,144}, {-454,-454}, {-350,-350}, {312,312}, {-218,-218}, {127,127}, {-59,-59}, {19,19}, {-3,-3}},701},\
+ {0,0,{{5,5}, {-36,-36}, {144,144}, {-437,-437}, {-371,-371}, {316,316}, {-215,-215}, {123,123}, {-56,-56}, {18,18}, {-3,-3}},701}},
+ {{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}},
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 26,
+ 22,
+ {{0},{0},{0},{0},{0}},
+ {{0},{0},{0},{0},{0}},
+ {{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}}},
+ { -136,-160,-160,-184,-192,-208,-240,-256,-296,-344,-408,-496,-640,-896,-304,-336,-408,-496,-640,-904,-1536}, //21
+ { -256,-1536, -1536, -1536, -1536, -1536, -1536,-1536 },
+ {0},
+ {0},
+ {0},
+ 0,
+ 0
+}}
+};
+#else
+#error "Unexpected RF Chip was defined"
+#endif
+#else
+extern TDS_RF_POC_COMP_T NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT;
+#endif
+
+#else
+#error "Unexpected RF Chip was defined"
+#endif
+
+
+#endif //#ifndef _MML1_RF_CC_SHM_DATA_H_
diff --git a/mcu/interface/l1/tl1/tl1d_rf_cid.h b/mcu/interface/l1/tl1/tl1d_rf_cid.h
new file mode 100644
index 0000000..f231087
--- /dev/null
+++ b/mcu/interface/l1/tl1/tl1d_rf_cid.h
@@ -0,0 +1,123 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2016
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * tl1d_rf_cid.h
+ *
+ * Project:
+ * --------
+ * 93m
+ *
+ * Description:
+ * ------------
+ * This file contains TDD RF related compile option id.
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================*/
+
+
+#ifndef __TL1D_RF_CID_H__
+#define __TL1D_RF_CID_H__
+
+/************************************************************************************
+* Include
+************************************************************************************/
+/*.................................................................*/
+/*............Chip ID definition.............................*/
+/*.................................................................*/
+
+
+#define TL1D_COMMON_INNER_RF_ID_MT6177L 0x00000008
+#define TL1D_COMMON_INNER_RF_ID_MT6177M 0x00000009 //define same as FTA tl1
+#define TL1D_COMMON_INNER_RF_ID_TRINITYE1 0x00000010
+#define TL1D_COMMON_INNER_RF_ID_MT6185M 0x00000011 //Trinity-L
+#define TL1D_COMMON_INNER_RF_ID_MT6186 0x00000012 //Trinity-L
+#define TL1D_COMMON_INNER_RF_ID_MT6186ME1 0x00000013 //Trinity 2l E1
+#define TL1D_COMMON_INNER_RF_ID_COLUMBUS 0x00000020 //95 columbus
+#define TL1D_COMMON_INNER_RF_ID_COLUMBUSL 0x00000021 //95 columbus
+#ifndef TL1D_RF_ID
+ #if defined(TRINITYE1_UMTS_TDD)
+#define TL1D_RF_ID TL1D_COMMON_INNER_RF_ID_TRINITYE1
+ #elif defined(TRINITYL_UMTS_TDD) || defined(MT6185M_UMTS_TDD)
+#define TL1D_RF_ID TL1D_COMMON_INNER_RF_ID_MT6185M //TRINITY L
+ #elif defined(TRINITYL_UMTS_TDD) || defined(MT6186_UMTS_TDD)
+#define TL1D_RF_ID TL1D_COMMON_INNER_RF_ID_MT6186 //TRINITY L E2
+ #elif defined(MT6186M_UMTS_TDD)
+#define TL1D_RF_ID TL1D_COMMON_INNER_RF_ID_MT6186ME1 //TRINITY 2L
+ #elif defined(MT6177L_UMTS_TDD)
+#define TL1D_RF_ID TL1D_COMMON_INNER_RF_ID_MT6177L
+ #elif defined(MT6177M_UMTS_TDD)
+#define TL1D_RF_ID TL1D_COMMON_INNER_RF_ID_MT6177M
+ #elif defined(COLUMBUS_UMTS_TDD) || defined(MT6190T_UMTS_TDD)|| defined(MT6190_UMTS_TDD)
+#define TL1D_RF_ID TL1D_COMMON_INNER_RF_ID_COLUMBUS
+ #elif defined(MT6190M_UMTS_TDD) || defined(MT6195_UMTS_TDD)
+#define TL1D_RF_ID TL1D_COMMON_INNER_RF_ID_COLUMBUSL
+ #else
+#error "No Valid RF Chip was defined"
+ #endif
+#else
+#error "Unexpected RF Chip was defined"
+#endif
+
+#define IS_TL1D_RF_MT6177L (TL1D_RF_ID == TL1D_COMMON_INNER_RF_ID_MT6177L)
+#define IS_TL1D_RF_MT6177M (TL1D_RF_ID == TL1D_COMMON_INNER_RF_ID_MT6177M)
+#define IS_TL1D_RF_TRINITYE1 (TL1D_RF_ID == TL1D_COMMON_INNER_RF_ID_TRINITYE1)
+#define IS_TL1D_RF_MT6185M (TL1D_RF_ID == TL1D_COMMON_INNER_RF_ID_MT6185M)
+#define IS_TL1D_RF_MT6186 (TL1D_RF_ID == TL1D_COMMON_INNER_RF_ID_MT6186)
+#define IS_TL1D_RF_MT6186ME1 (TL1D_RF_ID == TL1D_COMMON_INNER_RF_ID_MT6186ME1)
+#define IS_TL1D_RF_COLUMBUS (TL1D_RF_ID == TL1D_COMMON_INNER_RF_ID_COLUMBUS)
+#define IS_TL1D_RF_COLUMBUSL (TL1D_RF_ID == TL1D_COMMON_INNER_RF_ID_COLUMBUSL)
+#if defined(__MD95__)
+
+#if defined(MT3967)||defined(MT6295M)
+#define IS_TRF_RXDC_GXE_SUPPORT (0)
+#else
+#if (( IS_TL1D_RF_TRINITYE1)||( IS_TL1D_RF_MT6185M))
+#define IS_TRF_RXDC_GXE_SUPPORT (0)
+#else
+#define IS_TRF_RXDC_GXE_SUPPORT (1)
+#endif
+#endif/*MT3967 or MT6295M*/
+
+#endif/*__MD95__*/
+
+
+#endif /* __CL1D_RF_CID_H__ */