[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/ul1/external/hal_ul1_def.h b/mcu/interface/l1/ul1/external/hal_ul1_def.h
new file mode 100644
index 0000000..f1ae8d1
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/hal_ul1_def.h
@@ -0,0 +1,181 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * hal_ul1_def.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * This file contains common typedef, definition prototypes exported by L1 for MMI/Middleware
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _HAL_UL1_DEF_H
+#define _HAL_UL1_DEF_H
+
+#if defined (__UMTS_FDD_MODE__)
+#define UMTS_FDD_QUERY_UE_BAND_CAPABILITY(ADDR, INDEX) UL1D_UeCaBandCapability(ADDR, INDEX);
+#else
+#define UMTS_FDD_QUERY_UE_BAND_CAPABILITY(ADDR)
+#endif
+
+#define UL1D_EXIT() //Null function
+
+#define RF_GET_CAL_DATA_ARRAY_BAND_IDX(BAND, NVRAM_INIT) UL1D_RF_CalDataGetBand(BAND, NVRAM_INIT)
+
+#if defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__) || defined(__L1_GPS_REF_TIME_SUPPORT__)
+/* __GPS_FRAME_SYNC_SUPPORT__ */
+/*-------------- A-GPS Related ----------------*/
+typedef enum _ul1_agps_frame_sync_app_E
+{
+ UL1_AGPS_APP_FINE_TIME_ASSISTANCE = 0,
+ UL1_AGPS_APP_EVENT7C_PERIODIC,
+ UL1_AGPS_APP_FRAME_TIME_AIDING,
+ UL1_AGPS_APP_END
+} ul1_agps_frame_sync_app_E;
+
+typedef enum _ul1_agps_frame_sync_fail_reason_E
+{
+ UL1_AGPS_FAIL_NO_FAILURE = 0, /* No failure. */
+ UL1_AGPS_FAIL_3G_NOT_ACTIVE, /* 3G is not active. */
+ UL1_AGPS_FAIL_NO_SERVING_CELL, /* This fail reason means there is no serving cell. */
+ UL1_AGPS_FAIL_CELL_NOT_FOUND, /* Only for Type1/2, the fail reason means the cell indicated from the request is not in current BA list.*/
+ UL1_AGPS_FAIL_TIMING_NOT_ACCURATE, /* Timing result is not accurate due to some specific scenario. */
+ UL1_AGPS_FAIL_LCT_IN_OTHER_RAT, /* The fail reason is set by UL1D to indicate that LCT is currently controlled by other RAT. */
+ UL1_AGPS_FAIL_END
+} ul1_agps_frame_sync_fail_reason_E;
+#endif
+
+/* ---------------------- L+W Gemini ----------------------*/
+typedef enum _UL1_EXT_SIM_INDEX_E
+{
+ UL1_EXT_SIM_1 = 0,
+#ifdef __GEMINI_WCDMA__
+ UL1_EXT_SIM_2,
+#if (GEMINI_PLUS_WCDMA >= 3)
+ UL1_EXT_SIM_3,
+#if (GEMINI_PLUS_WCDMA >= 4)
+ UL1_EXT_SIM_4,
+#endif /* GEMINI_PLUS_WCDMA >= 4 */
+#endif /* GEMINI_PLUS_WCDMA >= 3 */
+#endif /* __GEMINI_WCDMA__ */
+ UL1_EXT_SIM_NUM
+} UL1_EXT_SIM_INDEX_E;
+
+#endif
diff --git a/mcu/interface/l1/ul1/external/hal_ul1_struct.h b/mcu/interface/l1/ul1/external/hal_ul1_struct.h
new file mode 100644
index 0000000..bfa9b52
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/hal_ul1_struct.h
@@ -0,0 +1,271 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * hal_ul1_struct.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * Layer 1 and Protocol Stack message and callback function definition for MMI/Middleware
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _HAL_UL1_STRUCT_H
+#define _HAL_UL1_STRUCT_H
+
+#include "hal_ul1_def.h"
+#include "kal_public_api.h"
+
+#if defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__) || defined(__L1_GPS_REF_TIME_SUPPORT__)
+/* __GPS_FRAME_SYNC_SUPPORT__ */
+/*****************************************************************************
+Request from GPS Task
+*****************************************************************************/
+typedef struct _ul1_gps_time_sync_req_struct
+{
+ LOCAL_PARA_HDR
+
+ ul1_agps_frame_sync_app_E application_type;
+
+ kal_bool maintain_phase; /* This flag is only useful when FRAME_TIME_AIDING_APP (Type3).
+ FALSE: The type3 request is aiding phase, and must check if timing is not accurate.
+ TRUE: The type3 request is maintain phase, and do not check if timing is not accurate. */
+
+ /* When application_type is FRAME_TIME_AIDING_APP, uarfcn and psc are unused. */
+ kal_uint16 uarfcn;
+ kal_uint16 psc; /* Primary scrambling code */
+} ul1_gps_time_sync_req_struct;
+
+/*****************************************************************************
+Confirm and indication to GPS Task
+*****************************************************************************/
+typedef struct _ul1_gps_time_sync_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ ul1_agps_frame_sync_app_E application_type;
+ ul1_agps_frame_sync_fail_reason_E fail_reason;
+
+ /* result_valid, sfn adn echip are useful only when
+ application_type in CPHY_GPS_TIME_SYNC_REQ is not FRAME_TIME_AIDING_APP. */
+ kal_bool result_valid;
+ kal_uint16 sfn; /* sfn is valid only when result_valid is true. */
+ kal_uint32 echip; /* echip is valid only when result_valid is true. */
+
+ kal_bool local_time_valid;
+ kal_uint64 local_time; /* uint=1/104 us.
+ local_time is valid only when local_time_valid is true. */
+} ul1_gps_time_sync_ind_struct;
+
+#endif
+
+/* ============================== Maintained by UL1D ==============================*/
+typedef enum
+{
+ FDD_HSDPA_OFF,
+ FDD_HSDPA_PHY_CAT1,
+ FDD_HSDPA_PHY_CAT2,
+ FDD_HSDPA_PHY_CAT3,
+ FDD_HSDPA_PHY_CAT4,
+ FDD_HSDPA_PHY_CAT5,
+ FDD_HSDPA_PHY_CAT6,
+ FDD_HSDPA_PHY_CAT7,
+ FDD_HSDPA_PHY_CAT8,
+ FDD_HSDPA_PHY_CAT9,
+ FDD_HSDPA_PHY_CAT10,
+ FDD_HSDPA_PHY_CAT11,
+ FDD_HSDPA_PHY_CAT12,
+#if defined(__UMTS_R8__)
+ FDD_HSDPA_PHY_CAT13,
+ FDD_HSDPA_PHY_CAT14,
+ FDD_HSDPA_PHY_CAT15,
+ FDD_HSDPA_PHY_CAT16,
+ FDD_HSDPA_PHY_CAT17,
+ FDD_HSDPA_PHY_CAT18,
+ FDD_HSDPA_PHY_CAT19,
+ FDD_HSDPA_PHY_CAT20,
+ FDD_HSDPA_PHY_CAT21,
+ FDD_HSDPA_PHY_CAT22,
+ FDD_HSDPA_PHY_CAT23,
+ FDD_HSDPA_PHY_CAT24,
+ FDD_HSDPA_PHY_CAT25,
+ FDD_HSDPA_PHY_CAT26,
+ FDD_HSDPA_PHY_CAT27,
+ FDD_HSDPA_PHY_CAT28,
+ FDD_HSDPA_PHY_CAT29
+#endif
+} FDD_HSDPA_CATEGORY_E;
+
+typedef enum
+{
+ FDD_HSUPA_OFF,
+ FDD_HSUPA_PHY_CAT1,
+ FDD_HSUPA_PHY_CAT2,
+ FDD_HSUPA_PHY_CAT3,
+ FDD_HSUPA_PHY_CAT4,
+ FDD_HSUPA_PHY_CAT5,
+ FDD_HSUPA_PHY_CAT6,
+ FDD_HSUPA_PHY_CAT7,
+ FDD_HSUPA_PHY_CAT8,
+ FDD_HSUPA_PHY_CAT9
+} FDD_HSUPA_CATEGORY_E;
+
+/* =================================================
+API for querying the supported Cat. of target chip
+
+hsdpa_cat: HSDPA PHY supported Cat.
+hsupa_cat: HSUPA PHY supported Cat.
+
+Return: Indicate whether the obtained HSDPA/HSUPA
+ category is valid or not
+===================================================*/
+extern kal_bool UL1D_Get_FDD_HSPA_Phy_Category( UL1_EXT_SIM_INDEX_E sim_idx,
+ FDD_HSDPA_CATEGORY_E *hsdpa_cat,
+ FDD_HSUPA_CATEGORY_E *hsupa_cat);
+extern kal_bool UL1D_Get_FDD_HSPA_Phy_Category_Extension(UL1_EXT_SIM_INDEX_E sim_idx,
+ FDD_HSDPA_CATEGORY_E *hsdpa_cat,
+ FDD_HSUPA_CATEGORY_E *hsupa_cat );
+extern kal_bool UL1D_Get_FDD_HSPA_Phy_Category_Extension_2( FDD_HSDPA_CATEGORY_E *hsdpa_cat,
+ FDD_HSUPA_CATEGORY_E *hsupa_cat );
+extern kal_bool UL1_IS_3G_FDD_EXIST(void);
+extern kal_bool UL1_IS_3G_FDD_EXIST_PCORE(void);
+
+/* ============================== Maintained by UL1D ==============================*/
+
+/* =================================================
+API for 3G USB LOGGING for HAL Rules
+===================================================*/
+/* ============================== Maintained by UL1D ==============================*/
+
+#endif /*_HAL_UL1_STRUCT_H*/
+
+/* ---------------------- Neighbor user detection ----------------------*/
+#if defined(__MTK_TARGET__)
+void ul1d_neighbor_user_detection_update_pcore(kal_bool result, kal_uint8 sim_idx);
+#endif
+
diff --git a/mcu/interface/l1/ul1/external/ul1cal.h b/mcu/interface/l1/ul1/external/ul1cal.h
new file mode 100644
index 0000000..b126703
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1cal.h
@@ -0,0 +1,686 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1cal.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * The structure definition of UL1 calibration data
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *==============================================================================
+ *******************************************************************************/
+#ifndef UL1CAL_H
+#define UL1CAL_H
+
+/*===============================================================================*/
+
+#include "kal_general_types.h"
+#include "ul1d_rf_public.h"
+#include "dcl.h" //SmartPhone Project's CommonModemImage need this
+#include "ul1d_rf_cid.h"
+#include "ul1d_rf_cal_poc_data.h"
+#include "ul1d_mipi_public.h"
+/*===============================================================================*/
+
+/* ------------------------------------------------------------------------- */
+typedef struct
+{
+ kal_uint16 tempdacData[8];
+}ul1cal_tempdacData_T;
+
+typedef struct
+{
+ U_sTEMPAGCOFFSET pathlossData;
+}ul1cal_pathlossData_T;
+
+typedef struct
+{
+ U_sRAMPDATA txdacData;
+}ul1cal_txdacData_T;
+
+/* PA 8-level control (MT6276, MT6573) */
+typedef struct
+{
+ U_sPAOCTLVLSETTING txPaOctLevData;
+}ul1cal_txPaOctLevData_T;
+
+typedef struct
+{
+ U_sPARACHTMCOMPDATA txPrachTmCompData;
+}ul1cal_txPrachTmCompData_T;
+
+typedef struct
+{
+ U_sAFCDACDATA afcDacData;
+}ul1cal_afcDacData_T;
+
+typedef struct
+{
+ U_sAFCCAPDATA afcCapData;
+}ul1cal_afcCapData_T;
+
+#if defined (__UL1_HS_PLATFORM__) || defined (__UL1_HS_PLUS_PLATFORM__)
+
+typedef struct
+{
+ U_sUl1dRfCustomInputData umtsRfCustomInput;
+}ul1cal_umtsRfCustomInput_T;
+
+#endif
+
+typedef struct
+{
+ U_sTEMPAGCOFFSET pathlossData;
+}ul1cal_pathlossRxdData_T;
+
+typedef struct
+{
+ U_sPADRIFTSETTING txPaDriftCompData;
+}ul1cal_txPaDriftCompData_T;
+
+
+#if IS_3G_SAR_TX_POWER_BACKOFF_SUPPORT
+typedef struct
+{
+ U_sSARBackoffDATA sarBackoffData;
+}ul1cal_SARBackoffData_T;
+
+typedef struct
+{
+ const U_sSARBackoffDATA* const* sarBackoffData_p;
+}Ul1CustomDynamicSARBackoffData;
+
+#endif
+
+
+#if IS_3G_TX_POWER_OFFSET_SUPPORT
+typedef struct
+{
+ U_sTXPOWEROFFSETDATA txPowerOffsetData;
+}ul1cal_txPowerOffsetData_T;
+
+typedef struct
+{
+ const U_sTXPOWEROFFSETDATA* const* TpoData_p;
+}Ul1CustomDynamicTpoData;
+
+#endif
+
+#if IS_3G_TX_NSFT_POWER_OFFSET_SUPPORT
+typedef struct
+{
+ const U_sTXNSFTPOWEROFFSETDATA* const* nsftTpoData_p;
+}Ul1CustomDynamicNsftTpoData;
+#endif
+
+#if (IS_3G_RX_POWER_OFFSET_SUPPORT )
+typedef struct
+{
+ U_sUl1dMetaRxPowerOffsetSetting RpoSetting;
+ const U_sRXPOWEROFFSETDATA* const* RpoData_p;
+}Ul1CustomDynamicRpoData;
+#endif
+#if (IS_3G_VPA_SEL_BY_BAND_SUPPORT)
+typedef struct
+{
+ const UMTS_VPA_SOURCE_TYPE* const* vpaSrcSelTable_p;
+}Ul1CustomDynamicVpaSrcSelData;
+#endif/*IS_3G_VPA_SEL_BY_BAND_SUPPORT*/
+
+/*------------- Single Software Load for Multiple Components Compatible -------------*/
+/*****************************************************************************
+* Constant : UL1CUSTOM_MAX_RF_BPI_EVENT_NUM
+* Group : Real target, Internal, UL1D common operation
+* Description : Constant to be used for record the maximum 3G BPI event
+* support numbers currently in use
+*****************************************************************************/
+#define UL1CUSTOM_MAX_RF_BPI_EVENT_NUM (15) //MT6280 Changes to 15
+
+/*****************************************************************************
+* Constant : UL1CUSTOM_MAX_RF_SUPPORT_BAND_NUM
+* Group : Real target, Internal, UL1D common operation
+* Description : Constant to be used for record the maximum 3G RF band
+* support numbers currently in use
+*****************************************************************************/
+#define UL1CUSTOM_MAX_RF_SUPPORT_BAND_NUM (MAX_SUPPORTED_BAND_INDEX) //MT6280 Changes to 5
+
+/*****************************************************************************
+* Constant : UL1CUSTOM_NULL_ACTION
+* UL1CUSTOM_GPIO_DETECTION_ID
+* UL1CUSTOM_ADC_DETECTION_ID
+* UL1CUSTOM_NVRAM_BARCODE_DETECTION_ID
+* Group : Real target, Internals, UL1D common operation
+* Description : Constant to be used to define the value to be used in
+* enumeration Ul1CustomActionId
+*****************************************************************************/
+#define UL1CUSTOM_NULL_ACTION (0)
+#define UL1CUSTOM_GPIO_DETECTION_ID (1)
+#define UL1CUSTOM_ADC_DETECTION_ID (2)
+#define UL1CUSTOM_NVRAM_BARCODE_DETECTION_ID (3)
+
+/*****************************************************************************
+* Typedef : Ul1CustomFunction
+* Group : Real target, Internals, UL1D common operation
+* Type : Function pointer
+* Description : Internal typedef used by UL1 Custom action function prototype
+*****************************************************************************/
+typedef void (*Ul1CustomFunction)(void *usrDataPtr);
+
+/*****************************************************************************
+* Typedef : Ul1CustomDynamicInitLnaPortTxPath
+* Group : Real target, Internals, UL1D common operation
+* Type : structure
+* Description : Internal typedef used by UL1 Custom dynamic initialization data
+* for LNA port and Tx path setting
+*****************************************************************************/
+typedef struct
+{
+ /* User input to notify the band of the data to be modified */
+ kal_uint32 bandToModify;
+
+ /* LNA port selection */
+ kal_uint8 lnaPortNum;
+
+ /* TX output path selection */
+ kal_uint8 txOutputSel;
+
+ /* RXD LNA port selection */
+ kal_uint8 lnaPortNum2;
+} Ul1CustomDynamicInitLnaPortTxPath;
+
+/*****************************************************************************
+* Typedef : Ul1CustomDynamicInitUmtsBpiData
+* Group : Real target, Internals, UL1D common operation
+* Type : structure
+* Description : Internal typedef used by UL1 Custom dynamic initialization data
+* 3G BPI data
+*****************************************************************************/
+typedef struct
+{
+ /* User input to notify the band of the data to be modified */
+ kal_uint32 bandToModify;
+
+ /* ASM logics */
+ kal_uint16 asmLogics[UL1CUSTOM_MAX_RF_BPI_EVENT_NUM];
+
+ /* PA enable control bits */
+// kal_uint8 paEnables[UL1CUSTOM_MAX_RF_BPI_EVENT_NUM];
+
+} Ul1CustomDynamicInitUmtsBpiData;
+
+/*****************************************************************************
+* Typedef : Ul1CustomDynamicInitUmtsTxRampData
+* Group : Real target, Internals, UL1D common operation
+* Type : structure
+* Description : Internal typedef used by UL1 Custom dynamic initialization data
+* 3G Tx Ramp data
+*****************************************************************************/
+typedef struct
+{
+ /* 3G TX Ramp data array */
+ U_sRAMPDATA *TxRampData[UL1CUSTOM_MAX_RF_SUPPORT_BAND_NUM];
+
+} Ul1CustomDynamicInitUmtsTxRampData;
+
+/*****************************************************************************
+* Typedef : Ul1CustomDynamicInitUmtsTxPaOctLvlData
+* Group : Real target, Internals, UL1D common operation
+* Type : structure
+* Description : Internal typedef used by UL1 Custom dynamic initialization data
+* 3G Tx PA oct-level data
+*****************************************************************************/
+typedef struct
+{
+ /* 3G TX Ramp data array */
+ U_sPAOCTLVLSETTING *TxPaOctLvl[UL1CUSTOM_MAX_RF_SUPPORT_BAND_NUM];
+
+} Ul1CustomDynamicInitUmtsTxPaOctLvlData;
+
+/*****************************************************************************
+* Typedef : Ul1CustomDynamicInitUmtsRxPathLossData
+* Group : Real target, Internals, UL1D common operation
+* Type : structure
+* Description : Internal typedef used by UL1 Custom dynamic initialization data
+* 3G Rx path loss data
+*****************************************************************************/
+
+typedef struct
+{
+ /* 3G TX Ramp data array */
+ U_sTEMPAGCOFFSET **RxPathLoss_p;
+
+} Ul1CustomDynamicInitUmtsRxPathLossData;
+
+typedef struct
+{
+ /* 3G RX path loss */
+ const U_sTEMPAGCOFFSET* const* RxPathLoss_p;
+ const U_sTEMPAGCOFFSET* const* RxDPathLoss_p;
+ const U_sPAOCTLVLSETTING* const* PaOctLev_p;
+ const U_sPARACHTMCOMPDATA* const* PaRachComp_p;
+ const U_sPADRIFTSETTING* const* PaDrift_p;
+ const U_sRAMPDATA* const* RampData_p;
+ const kal_uint16 *TempDac_p;
+ const U_sAFCCAPDATA *AfcCap_p;
+ const U_sAFCDACDATA *AfcDac_p;
+} Ul1CustomDynamicInitUmtsCalData;
+
+typedef struct
+{
+ const UMTS_FE_ROUTE_TABLE_T *FeSetting;
+
+} Ul1CustomDynamicInitUmtsFeSettingData;
+
+typedef struct
+{
+ const U_sDPD_COMMON_CTRL **DpdCtrlData_p;
+ const U_UL1D_PCFE_DPD_OTFC_CUSTOM_PARA_T *DpdPcfeCustomData_p;
+#if IS_3G_MIPI_SUPPORT
+ const UL1_UMTS_MIPI_TPC_T **DpdTpcTable_p;
+#endif
+ DPD_ENABLE_E dpd_enable;
+} Ul1CustomDynamicInitUmtsDpdfactoryData;
+
+/*****************************************************************************
+* Typedef : Ul1CustomDynamicInitUmtsTxPrachTmCompData
+* Group : Real target, Internals, UL1D common operation
+* Type : structure
+* Description : Internal typedef used by UL1 Custom dynamic initialization data
+* 3G Tx PRACH TM comp. data
+*****************************************************************************/
+typedef struct
+{
+ /* 3G TX PRACH TM comp data array */
+ U_sPARACHTMCOMPDATA *TxPrachTmComp[UL1CUSTOM_MAX_RF_SUPPORT_BAND_NUM];
+
+} Ul1CustomDynamicInitUmtsTxPrachTmCompData;
+
+/*****************************************************************************
+* Typedef : Ul1CustomDynamicInitUmtsTempDac
+* Group : Real target, Internals, UL1D common operation
+* Type : structure
+* Description : Internal typedef used by UL1 Custom dynamic initialization data
+* 3G temperature DAC data
+*****************************************************************************/
+typedef struct
+{
+ /* 3G Temperature DAC */
+ kal_uint16 *UTempDac;
+
+} Ul1CustomDynamicInitUmtsTempDac;
+
+/*****************************************************************************
+* Typedef : Ul1CustomDynamicInitUmtsAfcDac
+* Group : Real target, Internals, UL1D common operation
+* Type : structure
+* Description : Internal typedef used by UL1 Custom dynamic initialization data
+* 3G temperature DAC data
+*****************************************************************************/
+typedef struct
+{
+ /* 3G AFC DAC */
+ U_sAFCDACDATA *UAfcDac;
+
+} Ul1CustomDynamicInitUmtsAfcDac;
+
+/*****************************************************************************
+* Typedef : Ul1CustomDynamicInitUmtsAfcCap
+* Group : Real target, Internals, UL1D common operation
+* Type : structure
+* Description : Internal typedef used by UL1 Custom dynamic initialization data
+* 3G temperature DAC data
+*****************************************************************************/
+typedef struct
+{
+ /* 3G AFC CAP */
+ U_sAFCCAPDATA *UAfcCap;
+
+} Ul1CustomDynamicInitUmtsAfcCap;
+
+#if (IS_3G_MIPI_SUPPORT)
+typedef struct
+{
+ MIPI_Setting mipiSetting;
+ const UL1_MIPI_EVENT_TABLE_T* const* rxEventTable_p;
+ const UL1_MIPI_DATA_SUBBAND_TABLE_T* const* rxDataTable_p;
+ const UL1_MIPI_EVENT_TABLE_T* const* txEventTable_p;
+ const UL1_MIPI_DATA_SUBBAND_TABLE_T* const* txDataTable_p;
+ const UL1_UMTS_MIPI_TPC_T* const* tpcTable_p;
+ const UL1_MIPI_DATA_TABLE_T* const* asmIsoTable_p;
+}Ul1CustomDynamicInitMipiData;
+
+typedef struct
+{
+ const UL1_MIPI_SIMPLE_EVENT_TABLE_T* const* txEventTable_p;
+ const UL1_MIPI_SIMPLE_DATA_SUBBAND_TABLE_T* const* txDataTable_p;
+ const UL1_MIPI_SIMPLE_EVENT_TABLE_T* const* tpcEventTable_p;
+ const UL1_MIPI_SIMPLE_DATA_SUBBAND_TABLE_T* const* tpcDataTable_p;
+} Ul1CustomDynamicInitMipiEtmData;
+
+#endif
+
+#if (IS_3G_DAT_UL1_CUSTOM_SUPPORT)
+
+#if !IS_3G_GEN97_DAT_SUPPORT
+typedef struct
+{
+ const UMTS_CUSTOM_DAT_FE_ROUTE_DATABASE_T *dat_fe_route;
+}Ul1CustomDynamicDatRoute;
+#endif
+
+typedef struct
+{
+ UMTS_CUSTOM_DAT_FEATURE_BY_RAT_T dat_feature_byRat;
+}Ul1CustomDynamicDatFeatureByRat;
+
+#if !IS_3G_UDAT_SUPPORT
+typedef struct
+{
+ const UMTS_CUSTOM_DAT_FE_CAT_A_T *dat_cat_a_fe_db;
+ const UMTS_CUSTOM_DAT_FE_CAT_B_T *dat_cat_b_fe_db;
+}Ul1CustomDynamicDatDb;
+
+#if (IS_3G_MIPI_SUPPORT)
+typedef struct
+{
+ const UL1_MIPI_EVENT_TABLE_T* const* catA_eventTable_p;
+ const UL1_MIPI_DATA_SUBBAND_TABLE_T* const* catA_dataTable_p;
+ const UL1_MIPI_EVENT_TABLE_T* const* catB_eventTable_p;
+ const UL1_MIPI_DATA_SUBBAND_TABLE_T* const* catB_dataTable_p;
+}Ul1CustomDynamicDatMipiData;
+#endif
+#endif /*!IS_3G_UDAT_SUPPORT*/
+#endif
+
+#if (IS_3G_TAS_UL1_CUSTOM_SUPPORT)
+
+#if IS_3G_GEN97_TAS_SUPPORT
+typedef struct
+{
+ const UMTS_CUSTOM_TAS_FE_ROUTE_DATA_T *tas_fe_route;
+}Ul1CustomDynamicTasRoute;
+#else
+typedef struct
+{
+ const UMTS_CUSTOM_TAS_FE_ROUTE_DATABASE_T *tas_fe_route;
+}Ul1CustomDynamicTasRoute;
+#endif
+
+typedef struct
+{
+ const UMTS_CUSTOM_TAS_FE_CAT_A_T *tas_cat_a_fe_db;
+ const UMTS_CUSTOM_TAS_FE_CAT_B_T *tas_cat_b_fe_db;
+ const UMTS_CUSTOM_TAS_FE_CAT_C_T *tas_cat_c_fe_db;
+}Ul1CustomDynamicTasDb;
+
+typedef struct
+{
+ UMTS_CUSTOM_TAS_FEATURE_BY_RAT_T tas_feature_byRat;
+}Ul1CustomDynamicTasFeatureByRat;
+
+#if (IS_3G_MIPI_SUPPORT)
+typedef struct
+{
+ const UL1_MIPI_EVENT_TABLE_T* const* catA_eventTable_p;
+ const UL1_MIPI_DATA_SUBBAND_TABLE_T* const* catA_dataTable_p;
+ const UL1_MIPI_EVENT_TABLE_T* const* catB_eventTable_p;
+ const UL1_MIPI_DATA_SUBBAND_TABLE_T* const* catB_dataTable_p;
+ const UL1_MIPI_EVENT_TABLE_T* const* catC_eventTable_p;
+ const UL1_MIPI_DATA_SUBBAND_TABLE_T* const* catC_dataTable_p;
+}Ul1CustomDynamicTasMipiData;
+#endif
+
+#if IS_3G_TAS_TST_SUPPORT
+typedef struct
+{
+ const UMTS_CUSTOM_TAS_TST_FE_ROUTE_DATABASE_T *tas_tst_fe_route;
+}Ul1CustomDynamicTasTstRoute;
+#endif
+#endif
+
+#if IS_3G_TAS_INHERIT_4G_ANT
+typedef struct
+{
+ const UMTS_CUSTOM_TAS_INHERIT_LTE_BAND_T* const* inheritLteAntTable_p;
+}Ul1CustomDynamicTasInheritLteAnt;
+#endif
+
+#if IS_3G_REMOVE_MIPI
+typedef struct
+{
+ kal_bool xPMU_PA_CONTROL;
+ kal_bool umtsRxDAlwaysOn;
+ kal_bool ultra_low_cost_solution;
+ kal_uint32 umtsPADriftCompensation;
+ kal_uint8 PA_section;
+ kal_bool band5_and_band6_indicator;
+#if IS_3G_B5_AND_B19_INDICATOR_SUPPORT
+ kal_bool band5_and_band19_indicator;
+ kal_bool disable_band5_indicator;
+#endif
+ U_sUl1dRfBsiBpiTiming RfBpiTiming;
+ U_sUl1dRfPaControlTiming RfPaControlTiming;
+#if defined (__UL1_HS_PLUS_PLATFORM__)
+ U_sUl1dMprBackOff umtsMprBackOff;
+#endif
+#if IS_3G_MIPI_SUPPORT
+ U_sUl1dRfMipiSetting umtsRfMipiSetting;
+#endif
+
+}Ul1CustomDynamicRfParameter;
+#else
+typedef struct
+{
+ kal_bool xPMU_PA_CONTROL;
+ kal_bool umtsRxDAlwaysOn;
+ kal_bool ultra_low_cost_solution;
+ kal_uint32 umtsPADriftCompensation;
+ kal_uint8 PA_section;
+ kal_bool band5_and_band6_indicator;
+#if IS_3G_B5_AND_B19_INDICATOR_SUPPORT
+ kal_bool band5_and_band19_indicator;
+ kal_bool disable_band5_indicator;
+#endif
+ U_sUl1dRfBsiBpiTiming RfBpiTiming;
+ U_sUl1dRfPaControlTiming RfPaControlTiming;
+#if defined (__UL1_HS_PLUS_PLATFORM__)
+ U_sUl1dMprBackOff umtsMprBackOff;
+#endif
+#if IS_3G_MIPI_SUPPORT
+ //U_sUl1dRfMipiSetting umtsRfMipiSetting;
+#endif
+
+}Ul1CustomDynamicRfParameter;
+#endif
+
+#if IS_3G_ELNA_IDX_SUPPORT
+typedef struct
+{
+ UMTS_CUSTOM_ELNA_IDX_T umtsRxElnaIdxSetting;
+}Ul1CustomDynamicElnaIdxData;
+#endif
+
+#if IS_3G_RFEQ_COEF_SUBBAND_SUPPORT
+typedef struct
+{
+ const hs_dsch_rfeq_info_band_T* const* rfeqCoef_p;
+}Ul1CustomDynamicRfeqCoefData;
+#endif
+
+#if IS_3G_RFEQ_REAL_COEF_TEST
+typedef struct
+{
+ const URXDFE_REAL_RFEQ_CUSTOM_BAND_T* const* realRfeqCoef_p;
+}Ul1CustomDynamicRealRfeqCoefData;
+#endif
+
+#if IS_3G_FDD_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+typedef struct
+{
+ UMTS_RF_INTERFERENCE_FREQUENCY_T umtsRfInterferenceFreq;
+}Ul1CustomDynamicInterferenceFrequencyTable;
+#endif
+
+/*****************************************************************************
+* Typedef : Ul1CustomActionId
+* Group : Real target, Internals, UL1D common operation
+* Type : Enumeration
+* Description : Internal typedef used by UL1 Custom action ID constant value
+*****************************************************************************/
+typedef enum
+{
+ UL1CUSTOM_NULL_ACTION_ID = UL1CUSTOM_NULL_ACTION,
+ UL1CUSTOM_BASE_PROC_ACTION_ID = UL1CUSTOM_NULL_ACTION_ID,
+ UL1CUSTOM_GPIO_DETECTION = UL1CUSTOM_GPIO_DETECTION_ID,
+ UL1CUSTOM_ADC_DETECTION = UL1CUSTOM_ADC_DETECTION_ID,
+ UL1CUSTOM_NVRAM_BARCODE_DETECTION = UL1CUSTOM_NVRAM_BARCODE_DETECTION_ID,
+ UL1CUSTOM_MAX_PROC_ACTIONS
+
+} Ul1CustomActionId;
+
+/*****************************************************************************
+* Typedef : Ul1CustomDynamicInitResultRFParams
+* Group : Real target, Internals, UL1D common operation
+* Type : Enumeration
+* Description : Internal typedef used by UL1 Custom Dynamic init debug
+*****************************************************************************/
+typedef struct
+{
+ /* BPI data allocation */
+ U_sUl1dRfBpiData umtsPdata;
+
+ /* RF Hign-band and Low-band indicator */
+ U_sUl1dRfBandIndicator umtsBandIndicator;
+
+ /* RX LNA port selection */
+ U_sUl1dRfRxLnaPortSel umtsRxLnaPortSel;
+
+ /* TX output path selection */
+ U_sUl1dRfTxPathSel umtsTxPathSel;
+
+ /* RXd Path Setting (Main/Diversity on off Switch) */
+ U_sUl1dRxdPathSetting umtsRxdPathSetting;
+
+ /* PA Drift Compensation (On/Off Switch Mask) */
+ kal_uint32 umtsPADriftCompensation;
+} Ul1CustomDynamicInitResultRFParams;
+
+/*****************************************************************************
+* Typedef : Ul1CustomDynamicInitDebug
+* Group : Real target, Internals, UL1D common operation
+* Type : Enumeration
+* Description : Internal typedef used by UL1 Custom Dynamic init debug
+*****************************************************************************/
+typedef struct
+{
+ kal_uint16 combined_config_index;
+ kal_uint8 first_config_index_base;
+ kal_uint8 second_config_index_base;
+ kal_uint8 third_config_index_base;
+ kal_int32 gpio_get_pin_rpc_status;
+ kal_uint32 gpio_return_pin_num[3];
+ kal_uint32 gpio_pin_value[3];
+ kal_uint32 gpio_combined_pin_value;
+ kal_int32 adc_get_ch_num_rpc_status;
+ DCL_STATUS adc_dcl_handle_status;
+ DCL_STATUS adc_cal_dcl_handle_status;
+ kal_uint32 adc_get_ch_num;
+ kal_uint32 adc_dac_read_result;
+ kal_uint32 adc_volt_translate_result;
+ kal_uint8 adc_volt_level;
+ kal_bool barcode_lid_read_status;
+ kal_uint8 barcode_digit_read_result;
+ kal_bool umts_tempdac_lid_write_status;
+ kal_bool umts_txrampdata_lid_write_status;
+ kal_bool umts_txpaoctlvl_lid_write_status;
+ kal_bool umts_rxpathloss_lid_write_status;
+ kal_bool umts_txprachtmcomp_lid_write_status;
+ kal_bool umts_rf_params_lid_write_status;
+ Ul1CustomDynamicInitResultRFParams custom_dynamic_init_result_params;
+
+} Ul1CustomDynamicInitDebug;
+/*------------- Single Software Load for Multiple Components Compatible -------------*/
+
+/*****************************************************************************
+* Description : POC calibration global
+*****************************************************************************/
+/************************************************************************************
+* Global Functions Prototype (Interface)
+************************************************************************************/
+/* Function Prototypes can be used by other files */
+void UL1D_RFC_SHARE_CW_INIT(void);
+
+/************************************************************************************
+* Global Variables extern (Interface)
+************************************************************************************/
+#if 0/* No more used */
+/* under construction !*/
+#endif
+
+#ifdef __MTK_TARGET__
+#if IS_3G_SAR_TX_POWER_OFFSET_CONDI_SUPPORT
+extern const Ul1CustomDynamicSARBackoffData ul1CustomSarBackoffDataCondi[TPO_3G_TABLE_TYPE_NUM];
+extern kal_uint32 TPO_3G_TOTAL_TYPE_NUM;
+#endif
+#endif//__MTK_TARGET__
+
+extern void UL1D_RF_DynamicCustomTable_Update(const Ul1CustomDynamicInitUmtsFeSettingData *RfFeRoute_array_ptr);
+extern void UL1D_RF_DynamicSetRfParameter(U_sUl1dRfCustomInputData *dst, const Ul1CustomDynamicRfParameter *RfTiming_ptr );
+ #if(IS_3G_RX_POWER_OFFSET_SUPPORT)
+extern void UL1D_RF_DynamicRxPowerOffset_Update(U_sUl1dRfCustomInputData *dst, const Ul1CustomDynamicRpoData *source);
+ #endif
+
+#endif
diff --git a/mcu/interface/l1/ul1/external/ul1d_gpt_if.h b/mcu/interface/l1/ul1/external/ul1d_gpt_if.h
new file mode 100644
index 0000000..4978d3c
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_gpt_if.h
@@ -0,0 +1,9 @@
+#if (defined __MD93__)
+#include "ul1d_gpt_if_gen93.h"
+#elif (defined __MD95__)
+#include "ul1d_gpt_if_gen95.h"
+#elif (defined __MD97__) || (defined __MD97P__)
+#include "ul1d_gpt_if_gen97.h"
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
diff --git a/mcu/interface/l1/ul1/external/ul1d_gpt_if_gen93.h b/mcu/interface/l1/ul1/external/ul1d_gpt_if_gen93.h
new file mode 100644
index 0000000..e190f16
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_gpt_if_gen93.h
@@ -0,0 +1,337 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * File name:
+ * ---------
+ * ul1d_gpt_if.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * WCDMA test mode specific definitions for synchronizing with HOST tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 04 23 2018 alan.wong
+ * [MOLY00320644] [UL1D][RF] RFEQ Subband Setting and RXDFE IQ Dump by META Auto Tool
+ * . RF part 2.
+ *
+ * 02 08 2018 alan.wong
+ * [MOLY00304150] WCDMA ?ºÝBER???¥ÎMETA_3Grf_NSFT_Reset_BER_Result_r¥¢?
+ * -fix NSFT reset BER flow sync from R2 5055617
+ *
+ * 02 23 2017 alan.wong
+ * [MOLY00231464] [Bianco Bring-up][WCDMA][UL1TST] Add GP tool command
+ * .
+ *
+ * 05 30 2016 yu-hsuan.sung
+ * [MOLY00180557] [ELBRUS] add capability for META update parameter
+ *
+ ****************************************************************************/
+
+#ifndef __UL1D_GPT_IF_H__
+#define __UL1D_GPT_IF_H__
+
+/*******************************************************************************
+ * Include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "ft_msg_ul1rf.h"
+
+#define GPTOOL_EN_BSI_CW_NUMBER 64
+/*******************************************************************************
+ * Enumeration
+ ******************************************************************************/
+typedef enum
+{
+ u_test_command = URF_TEST_CMD_GP_TOOL_COMMAND_START,
+ //u_set_get_bsi,
+ /* --------------- please add new command posterior to this line --------------- */
+ //93new
+ u_get_rxtx_cal_data = URF_TEST_CMD_GET_RXTX_CALIBRATION_DATA_V3,
+ u_set_rxtx_cal_data = URF_TEST_CMD_SET_RXTX_CALIBRATION_DATA_V3,
+ u_get_calinfo_v3 =URF_TEST_CMD_GET_CALIBRATION_INFO_V3,
+ u_start_fhc_v3 =URF_TEST_CMD_START_FHC_V3,
+ u_get_fhc_result_v3 =URF_TEST_CMD_GET_FHC_RESULT_V3,
+ u_get_rssi_v3 =URF_TEST_CMD_GET_RSSI_V3,
+ u_gain_select_pwr_v3 =URF_TEST_CMD_GAIN_SELECT_PWR_V3,
+ u_gain_select_lna_v3 =URF_TEST_CMD_GAIN_SELECT_LNA_V3,
+ u_trigger_iq_dump_mode_v3 =URF_TEST_CMD_TRIGGER_IQ_DUMP_MODE_V3,
+ u_get_iq_dump_result_v3 =URF_TEST_CMD_GET_IQ_DUMP_RESULT_V3,
+ u_set_rfeq_subband_result_v3 =URF_TEST_CMD_SET_RFEQ_SUBBAND_RESULT_V3,
+ u_hsdpa_r5_tx =URF_TEST_CMD_START_HSDPA_NSFT,
+ u_hsupa_r6_tx =URF_TEST_CMD_START_HSUPA_NSFT,
+ u_stop =URF_TEST_CMD_STOP,
+ u_nsft_ex =URF_TEST_CMD_START_NSFT_EX,
+ u_nsft_get_rssi =URF_TEST_CMD_NSFT_GET_RSSI,
+ u_nsft_reset_ber =URF_TEST_CMD_NSFT_RESET_BER_RESULT,
+ u_get_single_end_ber =URF_TEST_CMD_GET_BIT_COUNT_FOR_SINGLE_ENDED_BER,
+}ft_urf_test_req_id_cmd_enum_type;
+
+
+/*******************************************************************************
+ * Legacy LTE RF Tool Commands
+ ******************************************************************************/
+
+
+
+/* --------------- please add new command structure posterior to this line --------------- */
+
+/*******************************************************************************
+ * GP RF Tool Commands
+ ******************************************************************************/
+
+/* -------------- *\
+|* U_TEST_COMMAND *|
+\* -------------- */
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} u_test_command_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} u_test_command_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} u_test_command_cnf_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} u_test_command_cnf_pdu_struct;
+
+/* -------------- *\
+|* U_SET_GET_BSI *|
+\* -------------- */
+typedef enum
+{
+ U_SET_GET_BSI_WRITE = 0,
+ U_SET_GET_BSI_READ = 1
+} U_SET_GET_BSI_E;
+
+typedef enum
+{
+ U_SET_GET_BSI_DISABLE = 0,
+ U_SET_GET_BSI_ENABLE = 1
+} U_SET_GET_BSI_ENABLE_E;
+
+typedef enum
+{ /* following number are according to HWPOR port select */
+ UL1TST_RF_RFIC1 = 0x0000,
+ UL1TST_RF_RFIC2 = 0x0001,
+ UL1TST_RF_PMIC = 0x0002,
+ UL1TST_RF_MIPI0 = 0x0003,
+ UL1TST_RF_MIPI1 = 0x0004,
+ UL1TST_RF_MIPI2 = 0x0005,
+ UL1TST_RF_MIPI3 = 0x0006,
+ UL1TST_RF_MIPI4 = 0x0007,
+ UL1TST_RF_PORT_CNT,
+}UL1TST_RF_BSIMM_PORT_T;
+
+
+typedef struct
+{
+ U_SET_GET_BSI_ENABLE_E gpt_bsi_enable;
+ U_SET_GET_BSI_E w_r;
+ UL1TST_RF_BSIMM_PORT_T sel_rfic;
+ kal_uint32 cw_address;
+ kal_uint32 cw_data;
+ kal_uint32 delay_us;
+} BSI_INFORMATION;
+
+typedef struct
+{
+ kal_uint32 void_param;
+} u_set_get_bsi_req_param_struct;
+
+typedef struct
+{
+ BSI_INFORMATION BSI[GPTOOL_EN_BSI_CW_NUMBER];
+} u_set_get_bsi_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint32 void_param;
+} u_set_get_bsi_cnf_param_struct;
+
+typedef struct
+{
+ BSI_INFORMATION BSI[GPTOOL_EN_BSI_CW_NUMBER];
+} u_set_get_bsi_cnf_pdu_struct;
+
+
+/*93 get set*/
+typedef URfTestCmd_GetRxTxCalData_ReqParam_V3 u_get_rxtx_cal_data_req_param_struct;
+typedef URfTestCmd_GetRxTxCalData_CnfParam_V3 u_get_rxtx_cal_data_cnf_param_struct;
+
+typedef struct //fix structure
+{
+ UTSTPathlossV3 RXM_peer_buf[5];
+ UTSTPathlossV3 RXD_peer_buf[5];
+ URfTestTXDaTaItem TX_peer_buf[5];
+}u_get_rxtx_cal_data_cnf_pdu_struct;
+
+typedef URfTestCmd_SetRxTxCalData_ReqParam_V3 u_set_rxtx_cal_data_req_param_struct;
+typedef URfTestCmd_SetRxTxCalData_CnfParam_V3 u_set_rxtx_cal_data_cnf_param_struct;
+
+typedef struct //fix structure
+{
+ UTSTPathlossV3 RXM_peer_buf[5];
+ UTSTPathlossV3 RXD_peer_buf[5];
+ URfTestTXDaTaItem TX_peer_buf[5];
+}u_set_rxtx_cal_data_req_pdu_struct;
+
+//get_calinfo_v3
+typedef UTSTReqGetCalInfoV3lp u_get_calinfo_v3_req_param_struct;
+typedef UTSTCnfGetCalInfoV3lp u_get_calinfo_v3_cnf_param_struct;
+typedef struct
+{
+ UTSTCnfGetCalInfoV3pb calinfo[5];
+}u_get_calinfo_v3_cnf_pdu_struct;
+
+//get_RSSI_V3
+typedef UTSTReqGetRSSIV3lp u_get_rssi_v3_req_param_struct;
+typedef UTSTCnfGetRSSIV3lp u_get_rssi_v3_cnf_param_struct;
+//powertogain
+typedef UTSTReqPwrtoGainV3lp u_gain_select_pwr_v3_req_param_struct;
+typedef UTSTCnfPwrtoGainV3lp u_gain_select_pwr_v3_cnf_param_struct;
+//powertoLNA
+typedef UTSTReqLnatoGainV3lp u_gain_select_lna_v3_req_param_struct;
+typedef UTSTCnfLnatoGainV3lp u_gain_select_lna_v3_cnf_param_struct;
+//start_fhc_v3(One band only)
+typedef UTSTReqFHCeLNAV3lp u_start_fhc_v3_req_param_struct;
+typedef UTSTCnfFHCeLNAV3lp u_start_fhc_v3_cnf_param_struct;
+typedef UTSTReqFHCeLNAV3pb u_start_fhc_v3_req_pdu_struct;
+//get_fhc_result_v3
+typedef struct
+{
+ kal_bool get_result;
+}u_get_fhc_result_v3_req_param_struct;
+typedef UTSTCnfGetFHCResultV3lp u_get_fhc_result_v3_cnf_param_struct;
+typedef UTSTCnfGetFHCResultV3pb u_get_fhc_result_v3_cnf_pdu_struct;
+
+//u_trigger_iq_dump_mode_v3
+typedef UTSTReqTriggerIqDumpModeV3lp u_trigger_iq_dump_mode_v3_req_param_struct;
+typedef UTSTCnfTriggerIqDumpModeV3lp u_trigger_iq_dump_mode_v3_cnf_param_struct;
+
+//u_get_iq_dump_result_v3
+typedef struct
+{
+ kal_bool get_result;
+}u_get_iq_dump_result_v3_req_param_struct;
+typedef UTSTCnfGetIqDumpResultV3lp u_get_iq_dump_result_v3_cnf_param_struct;
+typedef struct
+{
+ UTSTCnfGetIqDumpResultV3pb iq_dump_result[8192];
+}u_get_iq_dump_result_v3_cnf_pdu_struct;
+
+//u_set_rfeq_subband_result_v3
+typedef UTSTReqSetRfeqSubbandV3lp u_set_rfeq_subband_result_v3_req_param_struct;
+typedef struct
+{
+ UTSTReqSetRfeqSubbandV3pb rfeq_data[10];
+}u_set_rfeq_subband_result_v3_req_pdu_struct;
+typedef UTSTCnfSetRfeqSubbandV3lp u_set_rfeq_subband_result_v3_cnf_param_struct;
+
+//R5
+typedef struct
+{
+ kal_bool open_R5_test;
+}u_hsdpa_r5_tx_req_param_struct;
+typedef URfTestCmdHspaNsft u_hsdpa_r5_tx_req_pdu_struct;
+typedef FT_UMTS_NSFTLinkStatusReport u_hsdpa_r5_tx_cnf_param_struct;
+//R6
+typedef struct
+{
+ kal_bool open_R6_test;
+}u_hsupa_r6_tx_req_param_struct;
+typedef URfTestCmdHspaNsft u_hsupa_r6_tx_req_pdu_struct;
+typedef FT_UMTS_NSFTLinkStatusReport u_hsupa_r6_tx_cnf_param_struct;
+//STOP
+typedef struct
+{
+ kal_bool stop;
+}u_stop_req_param_struct;
+typedef struct
+{
+ kal_bool ok;
+}u_stop_cnf_param_struct;
+
+//u_nsft_ex
+typedef struct
+{
+ kal_bool open_nsft_test;
+}u_nsft_ex_req_param_struct;
+typedef UL1D_RF_NSFT_REQ_T u_nsft_ex_req_pdu_struct;
+typedef FT_UMTS_NSFTLinkStatusReport u_nsft_ex_cnf_param_struct;
+//u_nsft_get_rssi
+typedef struct
+{
+ kal_bool get_rssi;
+}u_nsft_get_rssi_req_param_struct;
+typedef URfTestResultNSFTRSSI u_nsft_get_rssi_cnf_param_struct;
+
+
+//u_nsft_reset_ber
+typedef URFTestCmdResetBERResult u_nsft_reset_ber_req_param_struct;
+typedef URFTestResultResetBERResult u_nsft_reset_ber_cnf_param_struct;
+//u_get_single_end_ber
+typedef struct
+{
+ kal_bool get_single_end_ber;
+}u_get_single_end_ber_req_param_struct;
+typedef UL1D_RF_NSFT_BET_BIT_CNT_FOR_BER_CNF_T u_get_single_end_ber_cnf_param_struct;
+#endif
diff --git a/mcu/interface/l1/ul1/external/ul1d_gpt_if_gen95.h b/mcu/interface/l1/ul1/external/ul1d_gpt_if_gen95.h
new file mode 100644
index 0000000..b6bafa6
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_gpt_if_gen95.h
@@ -0,0 +1,421 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * File name:
+ * ---------
+ * ul1d_gpt_if.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * WCDMA test mode specific definitions for synchronizing with HOST tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 22 2018 alan.wong
+ * [MOLY00347056] [UL1D][RF] NSFT TX Power Offset - sync 95 97 part
+ *
+ * 04 23 2018 alan.wong
+ * [MOLY00320644] [UL1D][RF] RFEQ Subband Setting and RXDFE IQ Dump by META Auto Tool
+ * . RF part 2.
+ *
+ * 02 08 2018 alan.wong
+ * [MOLY00304150] WCDMA ?ºÝBER???¥ÎMETA_3Grf_NSFT_Reset_BER_Result_r¥¢?
+ * -fix NSFT reset BER flow sync from R2 5055617
+ *
+ * 02 07 2018 alan.wong
+ * [MOLY00306660] eLNA support 18 dB & 13.5 dB feature change
+ * .
+ *
+ * 10 25 2017 alan.wong
+ * [MOLY00278686] [MT6295][WCDMA][TST] porting
+ * -get/set command
+ * -FHC start command modify
+ *
+ * 09 29 2017 alan.wong
+ * [MOLY00278686] [MT6295][WCDMA][TST] porting
+ * -capability
+ * -FHC start/result
+ *
+ * 02 23 2017 alan.wong
+ * [MOLY00231464] [Bianco Bring-up][WCDMA][UL1TST] Add GP tool command
+ * .
+ *
+ * 05 30 2016 yu-hsuan.sung
+ * [MOLY00180557] [ELBRUS] add capability for META update parameter
+ *
+ ****************************************************************************/
+
+#ifndef __UL1D_GPT_IF_H__
+#define __UL1D_GPT_IF_H__
+
+/*******************************************************************************
+ * Include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "ft_msg_ul1rf.h"
+
+#define GPTOOL_EN_BSI_CW_NUMBER 64
+/*******************************************************************************
+ * Enumeration
+ ******************************************************************************/
+typedef enum
+{
+ u_test_command = URF_TEST_CMD_GP_TOOL_COMMAND_START,
+ //u_set_get_bsi,
+ /* --------------- please add new command posterior to this line --------------- */
+ //93new
+ //u_get_rxtx_cal_data = URF_TEST_CMD_GET_RXTX_CALIBRATION_DATA_V3,
+ //u_set_rxtx_cal_data = URF_TEST_CMD_SET_RXTX_CALIBRATION_DATA_V3,
+ //u_get_calinfo_v3 =URF_TEST_CMD_GET_CALIBRATION_INFO_V3,
+ //u_start_fhc_v3 =URF_TEST_CMD_START_FHC_V3,
+ //u_get_fhc_result_v3 =URF_TEST_CMD_GET_FHC_RESULT_V3,
+ //u_get_rssi_v3 =URF_TEST_CMD_GET_RSSI_V3,
+ //u_gain_select_pwr_v3 =URF_TEST_CMD_GAIN_SELECT_PWR_V3,
+ //u_gain_select_lna_v3 =URF_TEST_CMD_GAIN_SELECT_LNA_V3,
+ //95 new
+ u_get_calinfo_v5 =URF_TEST_CMD_GET_CALIBRATION_INFO_V5,
+ u_start_fhc_v5 =URF_TEST_CMD_START_FHC_V5,
+ u_get_fhc_result_v5 =URF_TEST_CMD_GET_FHC_RESULT_V5,
+ u_get_rxtx_cal_data_v5 =URF_TEST_CMD_GET_RXTX_CALIBRATION_DATA_V5,
+ u_set_rxtx_cal_data_v5 =URF_TEST_CMD_SET_RXTX_CALIBRATION_DATA_V5,
+ u_get_rssi_v5 =URF_TEST_CMD_GET_RSSI_V5,
+ u_gain_select_pwr_v5 =URF_TEST_CMD_GAIN_SELECT_PWR_V5,
+ u_gain_select_lna_v5 =URF_TEST_CMD_GAIN_SELECT_LNA_V5,
+ u_trigger_iq_dump_mode_v3 =URF_TEST_CMD_TRIGGER_IQ_DUMP_MODE_V3,
+ u_get_iq_dump_result_v3 =URF_TEST_CMD_GET_IQ_DUMP_RESULT_V3,
+ u_set_rfeq_subband_result_v3 =URF_TEST_CMD_SET_RFEQ_SUBBAND_RESULT_V3,
+ //nsft
+ u_hsdpa_r5_tx =URF_TEST_CMD_START_HSDPA_NSFT,
+ u_hsupa_r6_tx =URF_TEST_CMD_START_HSUPA_NSFT,
+ u_stop =URF_TEST_CMD_STOP,
+ u_nsft_ex =URF_TEST_CMD_START_NSFT_EX,
+ u_nsft_get_rssi =URF_TEST_CMD_NSFT_GET_RSSI,
+ u_nsft_reset_ber =URF_TEST_CMD_NSFT_RESET_BER_RESULT,
+ u_get_single_end_ber =URF_TEST_CMD_GET_BIT_COUNT_FOR_SINGLE_ENDED_BER,
+ u_get_tx_power_offset =URF_TEST_CMD_GET_TX_POWER_OFFSET_V5,
+ u_set_tx_power_offset =URF_TEST_CMD_SET_TX_POWER_OFFSET_V5,
+}ft_urf_test_req_id_cmd_enum_type;
+
+
+/*******************************************************************************
+ * Legacy LTE RF Tool Commands
+ ******************************************************************************/
+
+
+
+/* --------------- please add new command structure posterior to this line --------------- */
+
+/*******************************************************************************
+ * GP RF Tool Commands
+ ******************************************************************************/
+
+/* -------------- *\
+|* U_TEST_COMMAND *|
+\* -------------- */
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} u_test_command_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} u_test_command_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} u_test_command_cnf_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} u_test_command_cnf_pdu_struct;
+
+/* -------------- *\
+|* U_SET_GET_BSI *|
+\* -------------- */
+typedef enum
+{
+ U_SET_GET_BSI_WRITE = 0,
+ U_SET_GET_BSI_READ = 1
+} U_SET_GET_BSI_E;
+
+typedef enum
+{
+ U_SET_GET_BSI_DISABLE = 0,
+ U_SET_GET_BSI_ENABLE = 1
+} U_SET_GET_BSI_ENABLE_E;
+
+typedef enum
+{ /* following number are according to HWPOR port select */
+ UL1TST_RF_RFIC1 = 0x0000,
+ UL1TST_RF_RFIC2 = 0x0001,
+ UL1TST_RF_PMIC = 0x0002,
+ UL1TST_RF_MIPI0 = 0x0003,
+ UL1TST_RF_MIPI1 = 0x0004,
+ UL1TST_RF_MIPI2 = 0x0005,
+ UL1TST_RF_MIPI3 = 0x0006,
+ UL1TST_RF_MIPI4 = 0x0007,
+ UL1TST_RF_PORT_CNT,
+}UL1TST_RF_BSIMM_PORT_T;
+
+
+typedef struct
+{
+ U_SET_GET_BSI_ENABLE_E gpt_bsi_enable;
+ U_SET_GET_BSI_E w_r;
+ UL1TST_RF_BSIMM_PORT_T sel_rfic;
+ kal_uint32 cw_address;
+ kal_uint32 cw_data;
+ kal_uint32 delay_us;
+} BSI_INFORMATION;
+
+typedef struct
+{
+ kal_uint32 void_param;
+} u_set_get_bsi_req_param_struct;
+
+typedef struct
+{
+ BSI_INFORMATION BSI[GPTOOL_EN_BSI_CW_NUMBER];
+} u_set_get_bsi_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint32 void_param;
+} u_set_get_bsi_cnf_param_struct;
+
+typedef struct
+{
+ BSI_INFORMATION BSI[GPTOOL_EN_BSI_CW_NUMBER];
+} u_set_get_bsi_cnf_pdu_struct;
+
+
+/*93 get set*/
+//typedef URfTestCmd_GetRxTxCalData_ReqParam_V3 u_get_rxtx_cal_data_req_param_struct;
+//typedef URfTestCmd_GetRxTxCalData_CnfParam_V3 u_get_rxtx_cal_data_cnf_param_struct;
+//
+//typedef struct //fix structure
+//{
+// UTSTPathlossV3 RXM_peer_buf[5];
+// UTSTPathlossV3 RXD_peer_buf[5];
+// URfTestTXDaTaItem TX_peer_buf[5];
+//}u_get_rxtx_cal_data_cnf_pdu_struct;
+//
+//typedef URfTestCmd_SetRxTxCalData_ReqParam_V3 u_set_rxtx_cal_data_req_param_struct;
+//typedef URfTestCmd_SetRxTxCalData_CnfParam_V3 u_set_rxtx_cal_data_cnf_param_struct;
+//
+//typedef struct //fix structure
+//{
+// UTSTPathlossV3 RXM_peer_buf[5];
+// UTSTPathlossV3 RXD_peer_buf[5];
+// URfTestTXDaTaItem TX_peer_buf[5];
+//}u_set_rxtx_cal_data_req_pdu_struct;
+
+//get_calinfo_v3
+//typedef UTSTReqGetCalInfoV3lp u_get_calinfo_v3_req_param_struct;
+//typedef UTSTCnfGetCalInfoV3lp u_get_calinfo_v3_cnf_param_struct;
+//typedef struct
+//{
+// UTSTCnfGetCalInfoV3pb calinfo[5];
+//}u_get_calinfo_v3_cnf_pdu_struct;
+
+////get_RSSI_V3
+//typedef UTSTReqGetRSSIV3lp u_get_rssi_v3_req_param_struct;
+//typedef UTSTCnfGetRSSIV3lp u_get_rssi_v3_cnf_param_struct;
+////powertogain
+//typedef UTSTReqPwrtoGainV3lp u_gain_select_pwr_v3_req_param_struct;
+//typedef UTSTCnfPwrtoGainV3lp u_gain_select_pwr_v3_cnf_param_struct;
+////powertoLNA
+//typedef UTSTReqLnatoGainV3lp u_gain_select_lna_v3_req_param_struct;
+//typedef UTSTCnfLnatoGainV3lp u_gain_select_lna_v3_cnf_param_struct;
+////start_fhc_v3(One band only)
+//typedef UTSTReqFHCeLNAV3lp u_start_fhc_v3_req_param_struct;
+//typedef UTSTCnfFHCeLNAV3lp u_start_fhc_v3_cnf_param_struct;
+//typedef UTSTReqFHCeLNAV3pb u_start_fhc_v3_req_pdu_struct;
+////get_fhc_result_v3
+//typedef struct
+//{
+// kal_bool get_result;
+//}u_get_fhc_result_v3_req_param_struct;
+//typedef UTSTCnfGetFHCResultV3lp u_get_fhc_result_v3_cnf_param_struct;
+//typedef UTSTCnfGetFHCResultV3pb u_get_fhc_result_v3_cnf_pdu_struct;
+
+//get_calinfo_v5 95
+typedef UTSTReqGetCalInfoV5lp u_get_calinfo_v5_req_param_struct;
+typedef UTSTCnfGetCalInfoV5lp u_get_calinfo_v5_cnf_param_struct;
+typedef struct
+{
+ UTSTCnfGetCalInfoV5pb calinfo[8];
+}u_get_calinfo_v5_cnf_pdu_struct;
+//start_fhc_v5(One band only)
+typedef UTSTReqFHCV5lp u_start_fhc_v5_req_param_struct;
+typedef UTSTCnfFHCV5lp u_start_fhc_v5_cnf_param_struct;
+typedef UTSTReqFHCV5pb u_start_fhc_v5_req_pdu_struct;
+//get_fhc_result_v5
+typedef struct
+{
+ kal_bool get_result;
+}u_get_fhc_result_v5_req_param_struct;
+typedef UTSTCnfGetFHCResultV5lp u_get_fhc_result_v5_cnf_param_struct;
+typedef UTSTCnfGetFHCResultV5pb u_get_fhc_result_v5_cnf_pdu_struct;
+/*95 get set*/
+typedef URfTestCmd_GetRxTxCalData_ReqParam_V5 u_get_rxtx_cal_data_v5_req_param_struct;
+typedef URfTestCmd_GetRxTxCalData_CnfParam_V5 u_get_rxtx_cal_data_v5_cnf_param_struct;
+
+typedef struct //fix structure
+{
+ UTSTPathlossV3 RXM_peer_buf[8];
+ UTSTPathlossV3 RXD_peer_buf[8];
+ URfTestTXDaTaItem TX_peer_buf[8];
+}u_get_rxtx_cal_data_v5_cnf_pdu_struct;
+
+typedef URfTestCmd_SetRxTxCalData_ReqParam_V5 u_set_rxtx_cal_data_v5_req_param_struct;
+typedef URfTestCmd_SetRxTxCalData_CnfParam_V5 u_set_rxtx_cal_data_v5_cnf_param_struct;
+
+typedef struct //fix structure
+{
+ UTSTPathlossV3 RXM_peer_buf[8];
+ UTSTPathlossV3 RXD_peer_buf[8];
+ URfTestTXDaTaItem TX_peer_buf[8];
+}u_set_rxtx_cal_data_v5_req_pdu_struct;
+//get_RSSI_V5 95
+typedef UTSTReqGetRSSIV5lp u_get_rssi_v5_req_param_struct;
+typedef UTSTCnfGetRSSIV5lp u_get_rssi_v5_cnf_param_struct;
+//powertogain 95
+typedef UTSTReqPwrtoGainV5lp u_gain_select_pwr_v5_req_param_struct;
+typedef UTSTCnfPwrtoGainV5lp u_gain_select_pwr_v5_cnf_param_struct;
+//powertoLNA 95
+typedef UTSTReqLnatoGainV5lp u_gain_select_lna_v5_req_param_struct;
+typedef UTSTCnfLnatoGainV5lp u_gain_select_lna_v5_cnf_param_struct;
+
+//u_trigger_iq_dump_mode_v3
+typedef UTSTReqTriggerIqDumpModeV3lp u_trigger_iq_dump_mode_v3_req_param_struct;
+typedef UTSTCnfTriggerIqDumpModeV3lp u_trigger_iq_dump_mode_v3_cnf_param_struct;
+
+//u_get_iq_dump_result_v3
+typedef struct
+{
+ kal_bool get_result;
+}u_get_iq_dump_result_v3_req_param_struct;
+typedef UTSTCnfGetIqDumpResultV3lp u_get_iq_dump_result_v3_cnf_param_struct;
+typedef struct
+{
+ UTSTCnfGetIqDumpResultV3pb iq_dump_result[8192];
+}u_get_iq_dump_result_v3_cnf_pdu_struct;
+
+//u_set_rfeq_subband_result_v3
+typedef UTSTReqSetRfeqSubbandV3lp u_set_rfeq_subband_result_v3_req_param_struct;
+typedef struct
+{
+ UTSTReqSetRfeqSubbandV3pb rfeq_data[10];
+}u_set_rfeq_subband_result_v3_req_pdu_struct;
+typedef UTSTCnfSetRfeqSubbandV3lp u_set_rfeq_subband_result_v3_cnf_param_struct;
+
+//R5
+typedef struct
+{
+ kal_bool open_R5_test;
+}u_hsdpa_r5_tx_req_param_struct;
+typedef URfTestCmdHspaNsft u_hsdpa_r5_tx_req_pdu_struct;
+typedef FT_UMTS_NSFTLinkStatusReport u_hsdpa_r5_tx_cnf_param_struct;
+//R6
+typedef struct
+{
+ kal_bool open_R6_test;
+}u_hsupa_r6_tx_req_param_struct;
+typedef URfTestCmdHspaNsft u_hsupa_r6_tx_req_pdu_struct;
+typedef FT_UMTS_NSFTLinkStatusReport u_hsupa_r6_tx_cnf_param_struct;
+//STOP
+typedef struct
+{
+ kal_bool stop;
+}u_stop_req_param_struct;
+typedef struct
+{
+ kal_bool ok;
+}u_stop_cnf_param_struct;
+
+//u_nsft_ex
+typedef struct
+{
+ kal_bool open_nsft_test;
+}u_nsft_ex_req_param_struct;
+typedef UL1D_RF_NSFT_REQ_T u_nsft_ex_req_pdu_struct;
+typedef FT_UMTS_NSFTLinkStatusReport u_nsft_ex_cnf_param_struct;
+//u_nsft_get_rssi
+typedef struct
+{
+ kal_bool get_rssi;
+}u_nsft_get_rssi_req_param_struct;
+typedef URfTestResultNSFTRSSI u_nsft_get_rssi_cnf_param_struct;
+
+
+//u_nsft_reset_ber
+typedef URFTestCmdResetBERResult u_nsft_reset_ber_req_param_struct;
+typedef URFTestResultResetBERResult u_nsft_reset_ber_cnf_param_struct;
+//u_get_single_end_ber
+typedef struct
+{
+ kal_bool get_single_end_ber;
+}u_get_single_end_ber_req_param_struct;
+typedef UL1D_RF_NSFT_BET_BIT_CNT_FOR_BER_CNF_T u_get_single_end_ber_cnf_param_struct;
+
+//u_get_tx_power_offset =URF_TEST_CMD_GET_TX_POWER_OFFSET,
+typedef UTSTReqGetTXpowerOffsetV5lp u_get_tx_power_offset_req_param_struct;
+typedef UTSTCnfGetTXpowerOffsetV5lp u_get_tx_power_offset_cnf_param_struct;
+//u_set_tx_power_offset =URF_TEST_CMD_SET_TX_POWER_OFFSET,
+typedef UTSTReqSetTXpowerOffsetV5lp u_set_tx_power_offset_req_param_struct;
+typedef UTSTCnfSetTXpowerOffsetV5lp u_set_tx_power_offset_cnf_param_struct;
+#endif
diff --git a/mcu/interface/l1/ul1/external/ul1d_gpt_if_gen97.h b/mcu/interface/l1/ul1/external/ul1d_gpt_if_gen97.h
new file mode 100644
index 0000000..7335b56
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_gpt_if_gen97.h
@@ -0,0 +1,424 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * File name:
+ * ---------
+ * ul1d_gpt_if.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * WCDMA test mode specific definitions for synchronizing with HOST tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 01 30 2019 alan.wong
+ * [MOLY00368807] [MT6297][Apollo Bring-up][WCDMA] TST porting
+ *
+ * - dpch tx IF change interface [ERS00028738]
+ *
+ * 01 21 2019 alan.wong
+ * [MOLY00368807] [MT6297][Apollo Bring-up][WCDMA] TST porting- GP UBIN CMD [ERS00027867]
+ *
+ * 12 27 2018 alan.wong
+ * [MOLY00368807] [MT6297][Apollo Bring-up][WCDMA] TST porting
+ *
+ * -TX ILPC API / fix RSSI idx passing IF part [ERS00025688]
+ *
+ * 11 23 2018 alan.wong
+ * [MOLY00365628] [GEN97][VMOLY] RF tool related functionality for phnoe call use
+ *
+ * -DPCH gptool[ERS00022757]
+ *
+ * 10 22 2018 alan.wong
+ * [MOLY00329245] [MT6297][WCDMA] TST part porting [ERS00018518]
+ * - improve FHC CMD interface part
+ *
+ * 09 18 2018 alan.wong
+ * [MOLY00329245] [MT6297][WCDMA] TST part porting
+ *
+ * -sync 6319626 6320482 6325766 6326076
+ *
+ * 08 22 2018 alan.wong
+ * [MOLY00347056] [UL1D][RF] NSFT TX Power Offset - sync 95 97 part
+ *
+ * 04 23 2018 alan.wong
+ * [MOLY00320644] [UL1D][RF] RFEQ Subband Setting and RXDFE IQ Dump by META Auto Tool
+ * . RF part 2.
+ *
+ * 02 08 2018 alan.wong
+ * [MOLY00304150] WCDMA ?ºÝBER???¥ÎMETA_3Grf_NSFT_Reset_BER_Result_r¥¢?
+ * -fix NSFT reset BER flow sync from R2 5055617
+ *
+ * 02 07 2018 alan.wong
+ * [MOLY00306660] eLNA support 18 dB & 13.5 dB feature change
+ * .
+ *
+ * 10 25 2017 alan.wong
+ * [MOLY00278686] [MT6295][WCDMA][TST] porting
+ * -get/set command
+ * -FHC start command modify
+ *
+ * 09 29 2017 alan.wong
+ * [MOLY00278686] [MT6295][WCDMA][TST] porting
+ * -capability
+ * -FHC start/result
+ *
+ * 02 23 2017 alan.wong
+ * [MOLY00231464] [Bianco Bring-up][WCDMA][UL1TST] Add GP tool command
+ * .
+ *
+ * 05 30 2016 yu-hsuan.sung
+ * [MOLY00180557] [ELBRUS] add capability for META update parameter
+ *
+ ****************************************************************************/
+
+#ifndef __UL1D_GPT_IF_H__
+#define __UL1D_GPT_IF_H__
+
+/*******************************************************************************
+ * Include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "ft_msg_ul1rf.h"
+
+#define GPTOOL_EN_BSI_CW_NUMBER 64
+/*******************************************************************************
+ * Enumeration
+ ******************************************************************************/
+typedef enum
+{
+ u_test_command = URF_TEST_CMD_GP_TOOL_COMMAND_START,
+ //u_set_get_bsi,
+ /* --------------- please add new command posterior to this line --------------- */
+ //97 new
+ u_get_calinfo_v7 =URF_TEST_CMD_GET_CALIBRATION_INFO_V7,
+ u_start_fhc_v7 =URF_TEST_CMD_FHC_V7,
+ //u_get_fhc_result_v7 =URF_TEST_CMD_GET_FHC_RESULT_V7,
+ u_get_rxtx_cal_data_v7 =URF_TEST_CMD_GET_RXTX_CALIBRATION_DATA_V7,
+ u_set_rxtx_cal_data_v7 =URF_TEST_CMD_SET_RXTX_CALIBRATION_DATA_V7,
+ u_get_rssi_v7 =URF_TEST_CMD_GET_RSSI_V7,
+ u_gain_select_pwr_v7 =URF_TEST_CMD_GAIN_SELECT_PWR_V7,
+ u_gain_select_lna_v7 =URF_TEST_CMD_GAIN_SELECT_LNA_V7,
+ u_tx_power_adjust_v7 =URF_TEST_CMD_TX_POWER_ADJUST_V7,
+ u_ubin_setup =URF_TEST_CMD_UBIN_MODE_SETUP,
+ u_dpch_tx_v7 =URF_TEST_CMD_TX_DPCH_V7,
+ u_set_rx_bw =URF_TEST_CMD_SET_RX_BANDWIDTH,
+ u_trigger_iq_dump_mode_v3 =URF_TEST_CMD_TRIGGER_IQ_DUMP_MODE_V3,
+ u_get_iq_dump_result_v3 =URF_TEST_CMD_GET_IQ_DUMP_RESULT_V3,
+ u_set_rfeq_subband_result_v3 =URF_TEST_CMD_SET_RFEQ_SUBBAND_RESULT_V3,
+ //nsft
+ u_hsdpa_r5_tx =URF_TEST_CMD_START_HSDPA_NSFT,
+ u_hsupa_r6_tx =URF_TEST_CMD_START_HSUPA_NSFT,
+ u_stop =URF_TEST_CMD_STOP,
+ u_nsft_ex =URF_TEST_CMD_START_NSFT_EX,
+ u_nsft_get_rssi =URF_TEST_CMD_NSFT_GET_RSSI,
+ u_nsft_reset_ber =URF_TEST_CMD_NSFT_RESET_BER_RESULT,
+ u_get_single_end_ber =URF_TEST_CMD_GET_BIT_COUNT_FOR_SINGLE_ENDED_BER,
+ u_get_tx_power_offset =URF_TEST_CMD_GET_TX_POWER_OFFSET_V5,
+ u_set_tx_power_offset =URF_TEST_CMD_SET_TX_POWER_OFFSET_V5,
+}ft_urf_test_req_id_cmd_enum_type;
+
+
+/*******************************************************************************
+ * Legacy LTE RF Tool Commands
+ ******************************************************************************/
+
+
+
+/* --------------- please add new command structure posterior to this line --------------- */
+
+/*******************************************************************************
+ * GP RF Tool Commands
+ ******************************************************************************/
+
+/* -------------- *\
+|* U_TEST_COMMAND *|
+\* -------------- */
+typedef struct
+{
+ kal_uint16 req_param1;
+ kal_uint16 req_param2;
+ kal_uint16 req_param3;
+} u_test_command_req_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} u_test_command_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint16 cnf_param1;
+ kal_uint16 cnf_param2;
+ kal_uint16 cnf_param3;
+} u_test_command_cnf_param_struct;
+
+typedef struct
+{
+ kal_uint16 req_pdu1;
+ kal_uint16 req_pdu2;
+ kal_uint16 req_pdu3;
+} u_test_command_cnf_pdu_struct;
+
+/* -------------- *\
+|* U_SET_GET_BSI *|
+\* -------------- */
+typedef enum
+{
+ U_SET_GET_BSI_WRITE = 0,
+ U_SET_GET_BSI_READ = 1
+} U_SET_GET_BSI_E;
+
+typedef enum
+{
+ U_SET_GET_BSI_DISABLE = 0,
+ U_SET_GET_BSI_ENABLE = 1
+} U_SET_GET_BSI_ENABLE_E;
+
+typedef enum
+{ /* following number are according to HWPOR port select */
+ UL1TST_RF_RFIC1 = 0x0000,
+ UL1TST_RF_RFIC2 = 0x0001,
+ UL1TST_RF_PMIC = 0x0002,
+ UL1TST_RF_MIPI0 = 0x0003,
+ UL1TST_RF_MIPI1 = 0x0004,
+ UL1TST_RF_MIPI2 = 0x0005,
+ UL1TST_RF_MIPI3 = 0x0006,
+ UL1TST_RF_MIPI4 = 0x0007,
+ UL1TST_RF_PORT_CNT,
+}UL1TST_RF_BSIMM_PORT_T;
+
+
+typedef struct
+{
+ U_SET_GET_BSI_ENABLE_E gpt_bsi_enable;
+ U_SET_GET_BSI_E w_r;
+ UL1TST_RF_BSIMM_PORT_T sel_rfic;
+ kal_uint32 cw_address;
+ kal_uint32 cw_data;
+ kal_uint32 delay_us;
+} BSI_INFORMATION;
+
+typedef struct
+{
+ kal_uint32 void_param;
+} u_set_get_bsi_req_param_struct;
+
+typedef struct
+{
+ BSI_INFORMATION BSI[GPTOOL_EN_BSI_CW_NUMBER];
+} u_set_get_bsi_req_pdu_struct;
+
+typedef struct
+{
+ kal_uint32 void_param;
+} u_set_get_bsi_cnf_param_struct;
+
+typedef struct
+{
+ BSI_INFORMATION BSI[GPTOOL_EN_BSI_CW_NUMBER];
+} u_set_get_bsi_cnf_pdu_struct;
+
+
+//get_calinfo_v7
+typedef UTSTReqGetCalInfoV7lp u_get_calinfo_v7_req_param_struct;
+typedef UTSTCnfGetCalInfoV7lp u_get_calinfo_v7_cnf_param_struct;
+typedef struct
+{
+ UTSTCnfGetCalInfoV7pb calinfo[8];
+}u_get_calinfo_v7_cnf_pdu_struct;
+//start_fhc_v7(One band only)
+typedef UTSTReqFHCV7lp u_start_fhc_v7_req_param_struct;
+//typedef UTSTCnfFHCV7lp u_start_fhc_v7_cnf_param_struct;
+typedef UTSTReqFHCV7pb u_start_fhc_v7_req_pdu_struct;
+typedef UTSTCnfFHCResultV7lp u_start_fhc_v7_cnf_param_struct;
+typedef UTSTCnfFHCResultV7pb u_start_fhc_v7_cnf_pdu_struct;
+#if 0//get_fhc_result_v7
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*97 get set*/
+typedef UTSTReqGetRxTxCalDataV7lp u_get_rxtx_cal_data_v7_req_param_struct;
+typedef UTSTCnfGetRxTxCalDataV7lp u_get_rxtx_cal_data_v7_cnf_param_struct;
+
+typedef struct //fix structure
+{
+ UTSTPathlossV7 RXM_peer_buf[8];
+ UTSTPathlossV7 RXD_peer_buf[8];
+ URfTestTXDaTaItem TX_peer_buf[8];
+}u_get_rxtx_cal_data_v7_cnf_pdu_struct;
+
+typedef UTSTReqSetRxTxCalDataV7lp u_set_rxtx_cal_data_v7_req_param_struct;
+typedef UTSTCnfSetRxTxCalDataV7lp u_set_rxtx_cal_data_v7_cnf_param_struct;
+
+typedef struct //fix structure
+{
+ UTSTPathlossV7 RXM_peer_buf[8];
+ UTSTPathlossV7 RXD_peer_buf[8];
+ URfTestTXDaTaItem TX_peer_buf[8];
+}u_set_rxtx_cal_data_v7_req_pdu_struct;
+//get_RSSI_V7
+typedef UTSTReqGetRSSIV7lp u_get_rssi_v7_req_param_struct;
+typedef UTSTCnfGetRSSIV7lp u_get_rssi_v7_cnf_param_struct;
+//powertogain
+typedef UTSTReqPwrtoGainV7lp u_gain_select_pwr_v7_req_param_struct;
+typedef UTSTCnfPwrtoGainV7lp u_gain_select_pwr_v7_cnf_param_struct;
+//powertoLNA
+typedef UTSTReqLnatoGainV7lp u_gain_select_lna_v7_req_param_struct;
+typedef UTSTCnfLnatoGainV7lp u_gain_select_lna_v7_cnf_param_struct;
+
+// tx power adjust
+typedef UTSTReqTxPwrAdjustV7lp u_tx_power_adjust_v7_req_param_struct;
+typedef UTSTCnfTxPwrAdjustV7lp u_tx_power_adjust_v7_cnf_param_struct;
+
+//UBIN setup u_ubin_setup
+typedef struct
+{
+ kal_uint8 ubin_fdd_mode_init;
+}u_ubin_setup_req_param_struct;
+typedef URfTestResultUbinModeSetup u_ubin_setup_cnf_param_struct;
+
+//DPCH TX
+typedef UTSTReqTxDPChV7lp u_dpch_tx_v7_req_param_struct;
+typedef struct
+{
+ kal_bool ok;
+}u_dpch_tx_v7_cnf_param_struct;
+
+//RX bandwidth
+typedef struct
+{
+ kal_uint8 is_5mhz;
+}u_set_rx_bw_req_param_struct;
+typedef struct
+{
+ kal_bool ok;
+}u_set_rx_bw_cnf_param_struct;
+
+//u_trigger_iq_dump_mode_v3
+typedef UTSTReqTriggerIqDumpModeV3lp u_trigger_iq_dump_mode_v3_req_param_struct;
+typedef UTSTCnfTriggerIqDumpModeV3lp u_trigger_iq_dump_mode_v3_cnf_param_struct;
+
+//u_get_iq_dump_result_v3
+typedef struct
+{
+ kal_bool get_result;
+}u_get_iq_dump_result_v3_req_param_struct;
+typedef UTSTCnfGetIqDumpResultV3lp u_get_iq_dump_result_v3_cnf_param_struct;
+typedef struct
+{
+ UTSTCnfGetIqDumpResultV3pb iq_dump_result[8192];
+}u_get_iq_dump_result_v3_cnf_pdu_struct;
+
+//u_set_rfeq_subband_result_v3
+typedef UTSTReqSetRfeqSubbandV3lp u_set_rfeq_subband_result_v3_req_param_struct;
+typedef struct
+{
+ UTSTReqSetRfeqSubbandV3pb rfeq_data[10];
+}u_set_rfeq_subband_result_v3_req_pdu_struct;
+typedef UTSTCnfSetRfeqSubbandV3lp u_set_rfeq_subband_result_v3_cnf_param_struct;
+
+//R5
+typedef struct
+{
+ kal_bool open_R5_test;
+}u_hsdpa_r5_tx_req_param_struct;
+typedef URfTestCmdHspaNsft u_hsdpa_r5_tx_req_pdu_struct;
+typedef FT_UMTS_NSFTLinkStatusReport u_hsdpa_r5_tx_cnf_param_struct;
+//R6
+typedef struct
+{
+ kal_bool open_R6_test;
+}u_hsupa_r6_tx_req_param_struct;
+typedef URfTestCmdHspaNsft u_hsupa_r6_tx_req_pdu_struct;
+typedef FT_UMTS_NSFTLinkStatusReport u_hsupa_r6_tx_cnf_param_struct;
+//STOP
+typedef struct
+{
+ kal_bool stop;
+}u_stop_req_param_struct;
+typedef struct
+{
+ kal_bool ok;
+}u_stop_cnf_param_struct;
+
+//u_nsft_ex
+typedef struct
+{
+ kal_bool open_nsft_test;
+}u_nsft_ex_req_param_struct;
+typedef UL1D_RF_NSFT_REQ_T u_nsft_ex_req_pdu_struct;
+typedef FT_UMTS_NSFTLinkStatusReport u_nsft_ex_cnf_param_struct;
+//u_nsft_get_rssi
+typedef struct
+{
+ kal_bool get_rssi;
+}u_nsft_get_rssi_req_param_struct;
+typedef URfTestResultNSFTRSSI u_nsft_get_rssi_cnf_param_struct;
+
+
+//u_nsft_reset_ber
+typedef URFTestCmdResetBERResult u_nsft_reset_ber_req_param_struct;
+typedef URFTestResultResetBERResult u_nsft_reset_ber_cnf_param_struct;
+//u_get_single_end_ber
+typedef struct
+{
+ kal_bool get_single_end_ber;
+}u_get_single_end_ber_req_param_struct;
+typedef UL1D_RF_NSFT_BET_BIT_CNT_FOR_BER_CNF_T u_get_single_end_ber_cnf_param_struct;
+
+//u_get_tx_power_offset =URF_TEST_CMD_GET_TX_POWER_OFFSET,
+typedef UTSTReqGetTXpowerOffsetV5lp u_get_tx_power_offset_req_param_struct;
+typedef UTSTCnfGetTXpowerOffsetV5lp u_get_tx_power_offset_cnf_param_struct;
+//u_set_tx_power_offset =URF_TEST_CMD_SET_TX_POWER_OFFSET,
+typedef UTSTReqSetTXpowerOffsetV5lp u_set_tx_power_offset_req_param_struct;
+typedef UTSTCnfSetTXpowerOffsetV5lp u_set_tx_power_offset_cnf_param_struct;
+#endif
diff --git a/mcu/interface/l1/ul1/external/ul1d_mipi_public.h b/mcu/interface/l1/ul1/external/ul1d_mipi_public.h
new file mode 100644
index 0000000..9944ce3
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_mipi_public.h
@@ -0,0 +1,887 @@
+/*******************************************************************************
+* Modification Notice :
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1d_mipi_public.h
+ *
+ * Project:
+ * --------
+ * 3G Project Common File
+ *
+ * Description:
+ * ------------
+ * Definition of some of customization setting not defined in ul1d_custom_rf.h
+ * And the stuff needs to be recognized by UL1D external module (wdata.c)
+ * Also some of data structure, global data, global function prototypes to be used
+ * by inter-category module (e.g. NVRAM)
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef UL1D_MIPI_PUBLIC_H
+#define UL1D_MIPI_PUBLIC_H
+
+
+/*******************************************************************************
+** Includes
+*******************************************************************************/
+#include "ul1d_rf_cid.h"
+#if IS_URF_PCORE
+
+#if defined(L1_SIM)
+#else
+#include "ul1d_custom_rf_ca.h"
+#endif
+
+#endif
+#include "ul1d_rf_public.h"
+#include "mml1_mipi_public.h"
+#include "mml1_dpd_def.h"
+
+#if (IS_3G_MIPI_SUPPORT)
+/*******************************************************************************
+** Constants
+*******************************************************************************/
+/////////////////////////
+//Should not modify
+//(2ASM + 4ATs for RX main & diversity; RX main:2ATs, RX diversity:2ATs)
+#define UL1_MIPI_RX_EVENT_NUM 24
+#define UL1_MIPI_RX_DATA_NUM 28
+
+#define UL1_MIPI_INIT_DATA_NUM 8
+
+ //(1ASM + 2AT + PA for TX)
+#define UL1_MIPI_TX_EVENT_NUM 16
+#define UL1_MIPI_TX_DATA_NUM 18
+
+ //(For MIPI PA META UI tuning)
+#define UL1_META_MIPI_PA_SECTION_NUM 8
+#define UL1_META_MIPI_PA_SECTION_DATA_NUM 4
+
+#define UL1_MIPI_TPC_EVENT_NUM 8
+#define UL1_MIPI_TPC_DATA_NUM 40
+
+#define UL1_MIPI_ETM_TX_EVENT_NUM 5
+#define UL1_MIPI_ETM_TX_DATA_NUM 12
+
+#define UL1_MIPI_ETM_TPC_EVENT_NUM 2
+#define UL1_MIPI_ETM_TPC_DATA_NUM 5
+
+#if IS_3G_TPC9LV_OFFPOWER_SUPPORT
+#define UL1_MIPI_TPC_OFF_DATA_NUM 5
+#else
+#define UL1_MIPI_TPC_OFF_DATA_NUM 0
+#endif
+
+ //(PA setting of TPC set)
+#define UL1_MIPI_PA_SECTION_NUM 8
+#define UL1_MIPI_PA_SECTION_DATA_NUM 5
+
+#define MIPI_SUBBAND_NUM 5 /*Max subband number is 5*/
+
+ //the first band is UMTSBandNone, actually support 5 bands
+#define UL1_MIPI_MAX_BAND_NUM (MAX_SUPPORTED_BAND_INDEX+1)
+
+#define UL1_MIPI_DATA_NULL 0x0000
+
+ //port slectiong
+#define UL1_MIPI_PORT0 0x0000
+#define UL1_MIPI_PORT1 0x0001
+#define UL1_MIPI_PORT2 0x0002
+#define UL1_MIPI_PORT3 0x0003
+#define UL1_MIPI_PORT4 0x0004
+#define UL1_MIPI_PORT5 0x0005
+#define UL1_MIPI_PORT6 0x0006
+#define UL1_MIPI_PORT7 0x0007
+#define UL1_MIPI_PORT_OFFSET_TO_MML1 (0)
+#define UL1_MIPI_PORT_OFFSET_TO_MML1_R (MML1_RF_MIPI0-UL1_MIPI_PORT0) /*MML1 use Port0/1/2/3 with value 2/3/4/5*/
+
+#define UL1_MIPI_PORT0_MSK (0x1<<(UL1_MIPI_PORT0))
+#define UL1_MIPI_PORT1_MSK (0x1<<(UL1_MIPI_PORT1))
+
+#define MIPI_DATA_IDX(start,stop) (((stop)<<8)|(start))
+
+//event type
+#define UL1_MIPI_TRX_ON 0x0001
+#define UL1_MIPI_TRX_OFF 0x0002
+#define UL1_MIPI_TPC_SET 0x0003
+#define UL1_MIPI_EVENT_NULL 0x0000
+
+//element type
+#define UL1_MIPI_NULL 0x0000
+#define UL1_MIPI_ASM 0x0001
+#define UL1_MIPI_ANT 0x0002
+#define UL1_MIPI_PA 0x0003
+#if IS_3G_TAS_UL1_CUSTOM_SUPPORT
+#define UL1_MIPI_TAS 0x0004
+#endif
+#if IS_3G_DAT_UL1_CUSTOM_SUPPORT
+#define UL1_MIPI_DAT 0x0005
+#endif
+#if IS_3G_RXD_FE_CONTROL_SUPPORT
+#define UL1_MIPI_ASM_RXD 0x0006
+#define UL1_MIPI_ANT_RXD 0x0007
+#endif
+
+#define UL1_MIPI_ETM 0x0008
+
+#if IS_3G_UTAS_SUPPORT
+#define UL1_MIPI_SWITCH 0x0009
+#endif
+
+#define UL1_MIPI_END 0xFFFF
+
+//data write seq. format
+#define UL1_SEQ_NULL 0x0000
+#define UL1_REG_0_W MML1_REG_0_W
+#define UL1_REG_W MML1_REG_W
+#define UL1_REG_W_EXT_1ST MML1_REG_W_EXT_1ST
+#define UL1_REG_W_EXT_BYTE MML1_REG_W_EXT_BYTE
+#define UL1_REG_W_EXT_END MML1_REG_W_EXT_END
+#define UL1_IMM_BSI_WAIT MML1_IMM_BSI_WAIT
+#define UL1_REG_W_EXT MML1_REG_W_EXT
+#if IS_3G_MIPI_EXTENDED_READ_ENABLE
+#define UL1_REG_EXT_R MML1_REG_R_EXT_ONLY_ONE_BYTE
+#define UL1_REG_R MML1_REG_R
+#endif
+
+
+//TPC PA SECTION DATA PATTERN
+#define UL1_MIPI_PA_SECTION_DATA0 0x10000000
+#define UL1_MIPI_PA_SECTION_DATA1 0x10000001
+#define UL1_MIPI_PA_SECTION_DATA2 0x10000002
+#define UL1_MIPI_PA_SECTION_DATA3 0x10000003
+
+#define US2CHIPCNT(us) ((us)*3.84)
+
+#define UL1_MIPI_MAX_INITIAL_CW_NUM 30
+
+#define UL1_MIPI_MAX_SLEEP_CW_NUM 20
+
+#define MIPI_MAX_INITIAL_IMM_BSI_CW_NUM UL1_MIPI_INIT_DATA_NUM
+
+#define MIPI_MAX_SLEEP_IMM_BSI_CW_NUM 20
+
+#define MIPI_MAX_ASM_ISOLATION_IMM_BSI_CW_NUM 1
+
+#if IS_3G_TAS_UL1_CUSTOM_SUPPORT
+#if IS_3G_UTAS_SUPPORT
+#define UL1_MIPI_TAS_EVENT_NUM MMRFD_MIPI_ANT_EVENT_NUM
+#define UL1_MIPI_TAS_DATA_NUM MMRFD_MIPI_ANT_DATA_NUM
+#else
+#define UL1_MIPI_TAS_EVENT_NUM (8)
+#define UL1_MIPI_TAS_DATA_NUM (20)
+#endif
+#define UL1_MIPI_TAS_ROUTE_A_NUM (UMTS_TAS_MAX_CAT_A_ROUTE_NUM)
+#define UL1_MIPI_TAS_ROUTE_B_NUM (UMTS_TAS_MAX_CAT_B_ROUTE_NUM)
+#define UL1_MIPI_TAS_ROUTE_C_NUM (UMTS_TAS_MAX_CAT_C_ROUTE_NUM)
+#define UL1_TAS_NO_SPLIT_BAND (0xFF)
+#endif
+
+#if IS_3G_DAT_UL1_CUSTOM_SUPPORT
+#define UL1_MIPI_DAT_EVENT_NUM (8)
+#define UL1_MIPI_DAT_DATA_NUM (20)
+#define UL1_MIPI_DAT_ROUTE_A_NUM (UMTS_DAT_MAX_CAT_A_ROUTE_NUM)
+#define UL1_MIPI_DAT_ROUTE_B_NUM (UMTS_DAT_MAX_CAT_B_ROUTE_NUM)
+#define UL1_DAT_NO_SPLIT_BAND (0xFF)
+#endif
+/*******************************************************************************
+** Macro define
+*******************************************************************************/
+#if IS_URF_PCORE
+#define M_UMTS_MIPI_RX_EVENT(x, sET) UMTS_MIPI_RX_EVENT_##x##_##sET
+#define M_UMTS_RX_EVENT(x, sET) M_UMTS_MIPI_RX_EVENT(x, sET)
+
+#define M_UMTS_MIPI_RX_DATA(x,sET) UMTS_MIPI_RX_DATA_##x##_##sET
+#define M_UMTS_RX_DATA(x,sET) M_UMTS_MIPI_RX_DATA(x,sET)
+
+#define M_UMTS_MIPI_TX_EVENT(x,sET) UMTS_MIPI_TX_EVENT_##x##_##sET
+#define M_UMTS_TX_EVENT(x,sET) M_UMTS_MIPI_TX_EVENT(x,sET)
+
+#define M_UMTS_MIPI_TX_DATA(x,sET) UMTS_MIPI_TX_DATA_##x##_##sET
+#define M_UMTS_TX_DATA(x,sET) M_UMTS_MIPI_TX_DATA(x,sET)
+
+#define M_UMTS_MIPI_TPC(x,sET) &UMTS_MIPI_TPC_##x##_##sET
+#define M_UMTS_TPC(x,sET) M_UMTS_MIPI_TPC(x,sET)
+
+#define M_UMTS_MIPI_ASM_ISO(x,sET) UMTS_MIPI_ASM_ISOLATION_DATA_##x##_##sET
+#define M_UMTS_ASM_ISO(x,sET) M_UMTS_MIPI_ASM_ISO(x,sET)
+
+#define M_UMTS_MIPI_DPD_TPC(x,sET) &UMTS_MIPI_DPD_TPC_##x##_##sET
+#define M_UMTS_DPD_TPC(x,sET) M_UMTS_MIPI_DPD_TPC(x,sET)
+
+#define M_UMTS_MIPI_ETM_TX_EVENT(x,sET) UMTS_MIPI_ETM_TX_EVENT_##x##_##sET
+#define M_UMTS_ETM_TX_EVENT(x,sET) M_UMTS_MIPI_ETM_TX_EVENT(x,sET)
+
+#define M_UMTS_MIPI_ETM_TX_DATA(x,sET) UMTS_MIPI_ETM_TX_DATA_##x##_##sET
+#define M_UMTS_ETM_TX_DATA(x,sET) M_UMTS_MIPI_ETM_TX_DATA(x,sET)
+
+#define M_UMTS_MIPI_ETM_TPC_EVENT(x,sET) UMTS_MIPI_ETM_TPC_EVENT_##x##_##sET
+#define M_UMTS_ETM_TPC_EVENT(x,sET) M_UMTS_MIPI_ETM_TPC_EVENT(x,sET)
+
+#define M_UMTS_MIPI_ETM_TPC_DATA(x,sET) UMTS_MIPI_ETM_TPC_DATA_##x##_##sET
+#define M_UMTS_ETM_TPC_DATA(x,sET) M_UMTS_MIPI_ETM_TPC_DATA(x,sET)
+
+
+/*------------------*/
+/* Macro Definition */
+/*------------------*/
+#define M_UMTS_ROUTE_OF_CACFG_IND(i,c,x) i##_CC##c##_##x##_MIPI_TBL_IDX
+#define M_UMTS_ROUTE_OF(i,c,x) M_UMTS_ROUTE_OF_CACFG_IND(i,c,x)
+
+#define M_CONSTRUCT_ROUTE(r) (1<<(r&0xF))
+#define M_ROUTE_MAP_IND(i,x) (M_CONSTRUCT_ROUTE(M_UMTS_ROUTE_OF(i,0,x)) | M_CONSTRUCT_ROUTE(M_UMTS_ROUTE_OF(i,1,x)))
+#define M_ROUTE_MAP_GROUP(x) (M_ROUTE_MAP_IND(RX_CABAND_IND_00,x) | M_ROUTE_MAP_IND(RX_CABAND_IND_01,x) | \
+ M_ROUTE_MAP_IND(RX_CABAND_IND_02,x) | M_ROUTE_MAP_IND(RX_CABAND_IND_03,x) | \
+ M_ROUTE_MAP_IND(RX_CABAND_IND_04,x))
+
+/*------------------------*/
+/* MIPI RX Route Settings */
+/*------------------------*/
+/*Single Band*/ #if M_ROUTE_MAP_GROUP(RX) & (1<<0)
+/*Single Band*/ #define __UMTS_MIPI_RX_ROUTE0__
+/*Single Band*/ #endif
+/*Single Band*/
+/*Single Band*/ #if M_ROUTE_MAP_GROUP(RX) & (1<<1)
+/*Single Band*/ #define __UMTS_MIPI_RX_ROUTE1__
+/*Single Band*/ #endif
+/*Single Band*/
+/*Single Band*/ #if M_ROUTE_MAP_GROUP(RX) & (1<<2)
+/*Single Band*/ #define __UMTS_MIPI_RX_ROUTE2__
+/*Single Band*/ #endif
+/*Single Band*/
+/*Single Band*/ #if M_ROUTE_MAP_GROUP(RX) & (1<<3)
+/*Single Band*/ #define __UMTS_MIPI_RX_ROUTE3__
+/*Single Band*/ #endif
+/*Single Band*/
+/*Single Band*/ #if M_ROUTE_MAP_GROUP(RX) & (1<<4)
+/*Single Band*/ #define __UMTS_MIPI_RX_ROUTE4__
+/*Single Band*/ #endif
+
+/* CA Band */ #if M_ROUTE_MAP_GROUP(RX) & (1<<5)
+/* CA Band */ #define __UMTS_MIPI_RX_ROUTE5__
+/* CA Band */ #endif
+/* CA Band */
+/* CA Band */ #if M_ROUTE_MAP_GROUP(RX) & (1<<6)
+/* CA Band */ #define __UMTS_MIPI_RX_ROUTE6__
+/* CA Band */ #endif
+/* CA Band */
+/* CA Band */ #if M_ROUTE_MAP_GROUP(RX) & (1<<7)
+/* CA Band */ #define __UMTS_MIPI_RX_ROUTE7__
+/* CA Band */ #endif
+/* CA Band */
+/* CA Band */ #if M_ROUTE_MAP_GROUP(RX) & (1<<8)
+/* CA Band */ #define __UMTS_MIPI_RX_ROUTE8__
+/* CA Band */ #endif
+/* CA Band */
+/* CA Band */ #if M_ROUTE_MAP_GROUP(RX) & (1<<9)
+/* CA Band */ #define __UMTS_MIPI_RX_ROUTE9__
+/* CA Band */ #endif
+/* CA Band */
+/* CA Band */ #if M_ROUTE_MAP_GROUP(RX) & (1<<10)
+/* CA Band */ #define __UMTS_MIPI_RX_ROUTE10__
+/* CA Band */ #endif
+/* CA Band */
+/* CA Band */ #if M_ROUTE_MAP_GROUP(RX) & (1<<11)
+/* CA Band */ #define __UMTS_MIPI_RX_ROUTE11__
+/* CA Band */ #endif
+/* CA Band */
+/* CA Band */ #if M_ROUTE_MAP_GROUP(RX) & (1<<12)
+/* CA Band */ #define __UMTS_MIPI_RX_ROUTE12__
+/* CA Band */ #endif
+/* CA Band */
+/* CA Band */ #if M_ROUTE_MAP_GROUP(RX) & (1<<13)
+/* CA Band */ #define __UMTS_MIPI_RX_ROUTE13__
+/* CA Band */ #endif
+/* CA Band */
+/* CA Band */ #if M_ROUTE_MAP_GROUP(RX) & (1<<14)
+/* CA Band */ #define __UMTS_MIPI_RX_ROUTE14__
+/* CA Band */ #endif
+
+
+/*-----------------------*/
+/* RX CA Common Settings */
+/*-----------------------*/
+#ifdef __UMTS_MIPI_RX_ROUTE5__
+#define MIPI_RX_ROUTE_IND_5 UMTS_Route5
+#else
+#define MIPI_RX_ROUTE_IND_5 UMTSBandNone
+#endif
+
+#ifdef __UMTS_MIPI_RX_ROUTE6__
+#define MIPI_RX_ROUTE_IND_6 UMTS_Route6
+#else
+#define MIPI_RX_ROUTE_IND_6 UMTSBandNone
+#endif
+
+#ifdef __UMTS_MIPI_RX_ROUTE7__
+#define MIPI_RX_ROUTE_IND_7 UMTS_Route7
+#else
+#define MIPI_RX_ROUTE_IND_7 UMTSBandNone
+#endif
+
+#ifdef __UMTS_MIPI_RX_ROUTE8__
+#define MIPI_RX_ROUTE_IND_8 UMTS_Route8
+#else
+#define MIPI_RX_ROUTE_IND_8 UMTSBandNone
+#endif
+
+#ifdef __UMTS_MIPI_RX_ROUTE9__
+#define MIPI_RX_ROUTE_IND_9 UMTS_Route9
+#else
+#define MIPI_RX_ROUTE_IND_9 UMTSBandNone
+#endif
+
+#ifdef __UMTS_MIPI_RX_ROUTE10__
+#define MIPI_RX_ROUTE_IND_10 UMTS_Route10
+#else
+#define MIPI_RX_ROUTE_IND_10 UMTSBandNone
+#endif
+
+#ifdef __UMTS_MIPI_RX_ROUTE11__
+#define MIPI_RX_ROUTE_IND_11 UMTS_Route11
+#else
+#define MIPI_RX_ROUTE_IND_11 UMTSBandNone
+#endif
+
+#ifdef __UMTS_MIPI_RX_ROUTE12__
+#define MIPI_RX_ROUTE_IND_12 UMTS_Route12
+#else
+#define MIPI_RX_ROUTE_IND_12 UMTSBandNone
+#endif
+
+#ifdef __UMTS_MIPI_RX_ROUTE13__
+#define MIPI_RX_ROUTE_IND_13 UMTS_Route13
+#else
+#define MIPI_RX_ROUTE_IND_13 UMTSBandNone
+#endif
+
+#ifdef __UMTS_MIPI_RX_ROUTE14__
+#define MIPI_RX_ROUTE_IND_14 UMTS_Route14
+#else
+#define MIPI_RX_ROUTE_IND_14 UMTSBandNone
+#endif
+
+#endif
+/*******************************************************************************
+** Typedefs
+*******************************************************************************/
+typedef struct
+{
+ kal_uint16 mipi_data_st;//mipi data start index
+ kal_uint16 mipi_data_sp;//mipi data stop index
+}UL1_MIPI_DATA_STSP;
+
+typedef struct
+{
+ kal_uint16 addr;
+ kal_uint32 data;
+}UL1_MIPI_ADDR_DATA_EXPAND_TABLE_T;
+
+typedef struct
+{
+ kal_uint16 mipi_elm_type; //mipi element type
+ UL1_MIPI_DATA_STSP mipi_data_stsp;
+ kal_uint16 mipi_evt_type; //event type
+ kal_uint32 mipi_evt_offset; //event offset
+}UL1_MIPI_EVENT_TABLE_T;
+
+typedef struct
+{
+ UL1_MIPI_DATA_STSP mipi_data_stsp;
+ kal_uint16 mipi_evt_type; //event type
+ kal_uint32 mipi_evt_offset; //event offset
+} UL1_MIPI_SIMPLE_EVENT_TABLE_T;
+
+typedef struct
+{
+ kal_uint16 mipi_subband_freq; // Port where data to send
+ UL1_MIPI_ADDR_DATA_EXPAND_TABLE_T mipi_data; // mipi data
+}UL1_MIPI_DATA_EXPAND_TABLE_T; //expanded by sub-freq
+
+typedef struct
+{
+ kal_uint16 mipi_elm_type; //mipi element type
+ kal_uint16 mipi_port_sel; //0:for Port0, 1:for Port1
+ kal_uint16 mipi_data_seq; // data write sequence format
+ kal_uint16 mipi_usid; //mipi USID
+ UL1_MIPI_DATA_EXPAND_TABLE_T mipi_subband_data[MIPI_SUBBAND_NUM]; // mipi data
+}UL1_MIPI_DATA_SUBBAND_TABLE_T;
+
+typedef struct
+{
+ kal_uint8 device_index;
+ kal_uint16 mipi_data_seq; // data write sequence format
+ UL1_MIPI_ADDR_DATA_EXPAND_TABLE_T mipi_subband_data[ MIPI_SUBBAND_NUM ]; // mipi data
+} UL1_MIPI_SIMPLE_DATA_SUBBAND_TABLE_T;
+
+typedef struct
+{
+ kal_uint16 mipi_elm_type; //mipi element type
+ kal_uint16 mipi_port_sel; //0:for Port0, 1:for Port1
+ kal_uint16 mipi_data_seq; // data write sequence format
+ kal_uint16 mipi_usid; //mipi USID
+ UL1_MIPI_ADDR_DATA_EXPAND_TABLE_T mipi_data; // mipi data
+}UL1_MIPI_DATA_TABLE_T;
+
+typedef struct
+{
+ UL1_MIPI_EVENT_TABLE_T umts_mipi_tpc_event[UL1_MIPI_TPC_EVENT_NUM];
+ UL1_MIPI_DATA_SUBBAND_TABLE_T umts_mipi_tpc_data[UL1_MIPI_TPC_DATA_NUM];
+}UL1_UMTS_MIPI_TPC_T;
+
+typedef struct
+{
+ kal_uint16 mipi_subband_freq;
+ kal_uint32 mipi_pa_tpc_data[UL1_MIPI_PA_SECTION_NUM][UL1_MIPI_PA_SECTION_DATA_NUM];
+}UL1_MIPI_PA_TPC_SECTION_TABLE_T;
+
+typedef UL1_UMTS_MIPI_TPC_T ul1mipi_tpcData_T;
+
+#if (IS_3G_MIPI_NVRAM_FULL_SUPPORT)
+typedef struct
+{
+ UL1_MIPI_DATA_SUBBAND_TABLE_T mipiTxData[UL1_MIPI_TX_DATA_NUM];
+}ul1mipi_txData_T;
+
+typedef struct
+{
+ UL1_MIPI_DATA_TABLE_T mipiAsmIsoData[MIPI_MAX_ASM_ISOLATION_IMM_BSI_CW_NUM];
+}ul1mipi_asmIsoData_T;
+
+typedef struct
+{
+ UL1_MIPI_EVENT_TABLE_T mipiTxEvent[UL1_MIPI_TX_EVENT_NUM];
+}ul1mipi_txEvent_T;
+
+typedef struct
+{
+ UL1_MIPI_SIMPLE_DATA_SUBBAND_TABLE_T mipiTxData[ UL1_MIPI_ETM_TX_DATA_NUM ];
+}ul1mipiEtm_txData_T;
+
+typedef struct
+{
+ UL1_MIPI_SIMPLE_DATA_SUBBAND_TABLE_T mipiTpcData[ UL1_MIPI_ETM_TPC_DATA_NUM ];
+}ul1mipiEtm_tpcData_T;
+
+typedef struct
+{
+ UL1_MIPI_SIMPLE_EVENT_TABLE_T mipiTxEvent[ UL1_MIPI_ETM_TX_EVENT_NUM ];
+} ul1mipiEtm_txEvent_T;
+
+typedef struct
+{
+ UL1_MIPI_SIMPLE_EVENT_TABLE_T mipiTpcEvent[ UL1_MIPI_ETM_TPC_EVENT_NUM ];
+} ul1mipiEtm_tpcEvent_T;
+
+typedef struct
+{
+ UL1_MIPI_DATA_SUBBAND_TABLE_T mipiRxData[UL1_MIPI_RX_DATA_NUM];
+}ul1mipi_rxData_T;
+
+typedef struct
+{
+ UL1_MIPI_EVENT_TABLE_T mipiRxEvent[UL1_MIPI_RX_EVENT_NUM];
+}ul1mipi_rxEvent_T;
+
+typedef struct
+{
+ UL1_MIPI_DATA_TABLE_T mipiInitData[MIPI_MAX_INITIAL_IMM_BSI_CW_NUM];
+}ul1mipi_initCwData_T;
+
+typedef struct
+{
+ UL1_MIPI_DATA_TABLE_T mipiSleepData[MIPI_MAX_SLEEP_IMM_BSI_CW_NUM];
+}ul1mipi_sleepCwData_T;
+
+#endif/*IS_3G_MIPI_NVRAM_FULL_SUPPORT*/
+
+#if (IS_3G_MIPI_SUPPORT)
+typedef enum
+{
+ MIPI_DEFAULT = 0,
+ MIPI_DISABLE = 1,
+ MIPI_ENABLE = 2
+}MIPI_Setting;
+
+
+#endif
+
+#if IS_3G_TAS_UL1_CUSTOM_SUPPORT
+typedef struct
+{
+ UL1_MIPI_EVENT_TABLE_T mipiTasEvent[UL1_MIPI_TAS_EVENT_NUM];
+}ul1mipi_tasEvent_T;
+
+typedef struct
+{
+ ul1mipi_tasEvent_T mipiTasEventRoute[UL1_MIPI_TAS_ROUTE_A_NUM];
+}ul1mipi_tasEvent_CatA_T;
+
+typedef struct
+{
+ ul1mipi_tasEvent_T mipiTasEventRoute[UL1_MIPI_TAS_ROUTE_B_NUM];
+}ul1mipi_tasEvent_CatB_T;
+
+typedef struct
+{
+ ul1mipi_tasEvent_T mipiTasEventRoute[UL1_MIPI_TAS_ROUTE_C_NUM];
+}ul1mipi_tasEvent_CatC_T;
+
+typedef struct
+{
+ UL1_MIPI_DATA_TABLE_T mipiTasData[UL1_MIPI_TAS_DATA_NUM];
+}ul1mipi_tasData_T;
+
+typedef struct
+{
+ UL1_MIPI_DATA_SUBBAND_TABLE_T mipiTasData[UL1_MIPI_TAS_DATA_NUM];
+}ul1mipi_tasSubBandData_T;
+
+typedef struct
+{
+ ul1mipi_tasSubBandData_T mipiTasDataRoute[UL1_MIPI_TAS_ROUTE_A_NUM];
+}ul1mipi_tasData_CatA_T;
+
+typedef struct
+{
+ ul1mipi_tasSubBandData_T mipiTasDataRoute[UL1_MIPI_TAS_ROUTE_B_NUM];
+}ul1mipi_tasData_CatB_T;
+
+typedef struct
+{
+ ul1mipi_tasSubBandData_T mipiTasDataRoute[UL1_MIPI_TAS_ROUTE_C_NUM];
+}ul1mipi_tasData_CatC_T;
+#endif
+
+#if IS_3G_DAT_UL1_CUSTOM_SUPPORT
+typedef struct
+{
+ UL1_MIPI_EVENT_TABLE_T mipiDatEvent[UL1_MIPI_DAT_EVENT_NUM];
+}ul1mipi_datEvent_T;
+
+typedef struct
+{
+ ul1mipi_datEvent_T mipiDatEventRoute[UL1_MIPI_DAT_ROUTE_A_NUM];
+}ul1mipi_datEvent_CatA_T;
+
+typedef struct
+{
+ ul1mipi_datEvent_T mipiDatEventRoute[UL1_MIPI_DAT_ROUTE_B_NUM];
+}ul1mipi_datEvent_CatB_T;
+
+typedef struct
+{
+ UL1_MIPI_DATA_SUBBAND_TABLE_T mipiDatData[UL1_MIPI_DAT_DATA_NUM];
+}ul1mipi_datSubBandData_T;
+
+typedef struct
+{
+ ul1mipi_datSubBandData_T mipiDatDataRoute[UL1_MIPI_DAT_ROUTE_A_NUM];
+}ul1mipi_datData_CatA_T;
+
+typedef struct
+{
+ ul1mipi_datSubBandData_T mipiDatDataRoute[UL1_MIPI_DAT_ROUTE_B_NUM];
+}ul1mipi_datData_CatB_T;
+#endif
+/*******************************************************************************
+** Function Prototype
+*******************************************************************************/
+
+#if (IS_3G_MIPI_NVRAM_FULL_SUPPORT)
+void nvram_init_uL1_mipiTxData(void);
+void nvram_init_uL1_mipiTxEvent(void);
+void nvram_init_uL1_mipiRxData(void);
+void nvram_init_uL1_mipiRxEvent(void);
+void nvram_init_uL1_mipiInitCw(void);
+void nvram_init_uL1_mipiSleepCw(void);
+#endif/*IS_3G_MIPI_NVRAM_FULL_SUPPORT*/
+
+
+/*******************************************************************************
+** Global Extern Func and Variables
+*******************************************************************************/
+#if IS_3G_RF_NCCA_SUPPORT
+#if IS_URF_PCORE
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_RX_EVENT_TABLE[UMTS_MIPI_RX_TBL_SIZE];
+#elif IS_URF_L1CORE && IS_URF_MT6291_DUAL_CORE_ARCH
+//extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_RX_EVENT_TABLE[UMTS_MIPI_RX_TBL_SIZE];
+#endif
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_MIPI_RX_DATA_TABLE[UMTS_MIPI_RX_TBL_SIZE];
+#else
+#if IS_URF_PCORE
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_RX_EVENT_TABLE[UL1D_RF_CUSTOM_BAND];
+#elif IS_URF_L1CORE && IS_URF_MT6291_DUAL_CORE_ARCH
+//extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_RX_EVENT_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_MIPI_RX_DATA_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_TX_EVENT_TABLE[UL1D_RF_CUSTOM_BAND];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_MIPI_TX_DATA_TABLE[UL1D_RF_CUSTOM_BAND];
+extern UL1_UMTS_MIPI_TPC_T *UMTS_MIPI_TPC_TABLE[UL1D_RF_CUSTOM_BAND];
+extern UL1_MIPI_DATA_TABLE_T UMTS_MIPI_INITIAL_CW[UL1_MIPI_INIT_DATA_NUM];
+extern UL1_MIPI_DATA_TABLE_T *UMTS_MIPI_ASM_ISOLATION_DATA_TABLE[UL1D_RF_CUSTOM_BAND];
+
+#if IS_3G_RF_NCCA_SUPPORT
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_RX_EVENT_PCORE_TABLE[UMTS_MIPI_RX_TBL_SIZE];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_MIPI_RX_DATA_PCORE_TABLE[UMTS_MIPI_RX_TBL_SIZE];
+#else
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_RX_EVENT_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_MIPI_RX_DATA_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_TX_EVENT_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_MIPI_TX_DATA_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+extern UL1_UMTS_MIPI_TPC_T *UMTS_MIPI_TPC_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+extern UL1_MIPI_DATA_TABLE_T *UMTS_MIPI_INITIAL_CW_PCORE_ptr;
+extern UL1_MIPI_DATA_TABLE_T *UMTS_MIPI_SLEEP_CW_PCORE_ptr;
+extern UL1_MIPI_DATA_TABLE_T *UMTS_MIPI_ASM_ISOLATION_DATA_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+
+#if __IS_UL1D_DPD_SUPPORT__
+extern UL1_UMTS_MIPI_TPC_T *UMTS_MIPI_DPD_TPC_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+extern UL1_UMTS_MIPI_TPC_T *UMTS_MIPI_DPD_TPC_TABLE[UL1D_RF_CUSTOM_BAND];
+extern const UL1_UMTS_MIPI_TPC_T* UMTS_MIPI_DPD_TPC_TABLE_SetDefault[];
+#endif
+
+#if __IS_UL1D_ETM_SUPPORT__
+extern UL1_MIPI_SIMPLE_EVENT_TABLE_T *UMTS_MIPI_ETM_TX_EVENT_TABLE[ UL1D_RF_CUSTOM_BAND ];
+extern UL1_MIPI_SIMPLE_DATA_SUBBAND_TABLE_T *UMTS_MIPI_ETM_TX_DATA_TABLE[ UL1D_RF_CUSTOM_BAND ];
+extern UL1_MIPI_SIMPLE_EVENT_TABLE_T *UMTS_MIPI_ETM_TPC_EVENT_TABLE[ UL1D_RF_CUSTOM_BAND ];
+extern UL1_MIPI_SIMPLE_DATA_SUBBAND_TABLE_T *UMTS_MIPI_ETM_TPC_DATA_TABLE[ UL1D_RF_CUSTOM_BAND ];
+
+extern UL1_MIPI_SIMPLE_EVENT_TABLE_T *UMTS_MIPI_ETM_TX_EVENT_PCORE_TABLE[ UL1D_RF_CUSTOM_BAND ];
+extern UL1_MIPI_SIMPLE_DATA_SUBBAND_TABLE_T *UMTS_MIPI_ETM_TX_DATA_PCORE_TABLE[ UL1D_RF_CUSTOM_BAND ];
+extern UL1_MIPI_SIMPLE_EVENT_TABLE_T *UMTS_MIPI_ETM_TPC_EVENT_PCORE_TABLE[ UL1D_RF_CUSTOM_BAND ];
+extern UL1_MIPI_SIMPLE_DATA_SUBBAND_TABLE_T *UMTS_MIPI_ETM_TPC_DATA_PCORE_TABLE[ UL1D_RF_CUSTOM_BAND ];
+#endif // #if __IS_UL1D_ETM_SUPPORT__
+
+#ifdef __UMTS_MIPI_RX_ROUTE5__
+extern UL1_MIPI_EVENT_TABLE_T UMTS_MIPI_RX_EVENT_UMTS_Route5[];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T UMTS_MIPI_RX_DATA_UMTS_Route5[];
+#endif
+#ifdef __UMTS_MIPI_RX_ROUTE6__
+extern UL1_MIPI_EVENT_TABLE_T UMTS_MIPI_RX_EVENT_UMTS_Route6[];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T UMTS_MIPI_RX_DATA_UMTS_Route6[];
+#endif
+#ifdef __UMTS_MIPI_RX_ROUTE7__
+extern UL1_MIPI_EVENT_TABLE_T UMTS_MIPI_RX_EVENT_UMTS_Route7[];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T UMTS_MIPI_RX_DATA_UMTS_Route7[];
+#endif
+#ifdef __UMTS_MIPI_RX_ROUTE8__
+extern UL1_MIPI_EVENT_TABLE_T UMTS_MIPI_RX_EVENT_UMTS_Route8[];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T UMTS_MIPI_RX_DATA_UMTS_Route8[];
+#endif
+#ifdef __UMTS_MIPI_RX_ROUTE9__
+extern UL1_MIPI_EVENT_TABLE_T UMTS_MIPI_RX_EVENT_UMTS_Route9[];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T UMTS_MIPI_RX_DATA_UMTS_Route9[];
+#endif
+#ifdef __UMTS_MIPI_RX_ROUTE10__
+extern UL1_MIPI_EVENT_TABLE_T UMTS_MIPI_RX_EVENT_UMTS_Route10[];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T UMTS_MIPI_RX_DATA_UMTS_Route10[];
+#endif
+#ifdef __UMTS_MIPI_RX_ROUTE11__
+extern UL1_MIPI_EVENT_TABLE_T UMTS_MIPI_RX_EVENT_UMTS_Route11[];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T UMTS_MIPI_RX_DATA_UMTS_Route11[];
+#endif
+#ifdef __UMTS_MIPI_RX_ROUTE12__
+extern UL1_MIPI_EVENT_TABLE_T UMTS_MIPI_RX_EVENT_UMTS_Route12[];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T UMTS_MIPI_RX_DATA_UMTS_Route12[];
+#endif
+#ifdef __UMTS_MIPI_RX_ROUTE13__
+extern UL1_MIPI_EVENT_TABLE_T UMTS_MIPI_RX_EVENT_UMTS_Route13[];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T UMTS_MIPI_RX_DATA_UMTS_Route13[];
+#endif
+#ifdef __UMTS_MIPI_RX_ROUTE14__
+extern UL1_MIPI_EVENT_TABLE_T UMTS_MIPI_RX_EVENT_UMTS_Route14[];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T UMTS_MIPI_RX_DATA_UMTS_Route14[];
+#endif
+
+#if IS_3G_TAS_UL1_CUSTOM_SUPPORT
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_TAS_CAT_A_EVENT_TABLE_ptr[UL1_MIPI_TAS_ROUTE_A_NUM];
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_TAS_CAT_B_EVENT_TABLE_ptr[UL1_MIPI_TAS_ROUTE_B_NUM];
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_TAS_CAT_C_EVENT_TABLE_ptr[UL1_MIPI_TAS_ROUTE_C_NUM];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_MIPI_TAS_CAT_A_DATA_TABLE_ptr[UL1_MIPI_TAS_ROUTE_A_NUM];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_MIPI_TAS_CAT_B_DATA_TABLE_ptr[UL1_MIPI_TAS_ROUTE_B_NUM];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_MIPI_TAS_CAT_C_DATA_TABLE_ptr[UL1_MIPI_TAS_ROUTE_C_NUM];
+
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_TAS_CAT_A_MIPI_EVENT_TABLE_PCORE_ptr[UL1_MIPI_TAS_ROUTE_A_NUM];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_TAS_CAT_A_MIPI_DATA_TABLE_PCORE_ptr[UL1_MIPI_TAS_ROUTE_A_NUM];
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_TAS_CAT_B_MIPI_EVENT_TABLE_PCORE_ptr[UL1_MIPI_TAS_ROUTE_B_NUM];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_TAS_CAT_B_MIPI_DATA_TABLE_PCORE_ptr[UL1_MIPI_TAS_ROUTE_B_NUM];
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_TAS_CAT_C_MIPI_EVENT_TABLE_PCORE_ptr[UL1_MIPI_TAS_ROUTE_C_NUM];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_TAS_CAT_C_MIPI_DATA_TABLE_PCORE_ptr[UL1_MIPI_TAS_ROUTE_C_NUM];
+
+extern const UL1_MIPI_EVENT_TABLE_T* const UMTS_TAS_CAT_A_MIPI_EVENT_TABLE_SetDefault[];
+extern const UL1_MIPI_DATA_SUBBAND_TABLE_T* const UMTS_TAS_CAT_A_MIPI_DATA_TABLE_SetDefault[];
+extern const UL1_MIPI_EVENT_TABLE_T* const UMTS_TAS_CAT_B_MIPI_EVENT_TABLE_SetDefault[];
+extern const UL1_MIPI_DATA_SUBBAND_TABLE_T* const UMTS_TAS_CAT_B_MIPI_DATA_TABLE_SetDefault[];
+extern const UL1_MIPI_EVENT_TABLE_T* const UMTS_TAS_CAT_C_MIPI_EVENT_TABLE_SetDefault[];
+extern const UL1_MIPI_DATA_SUBBAND_TABLE_T* const UMTS_TAS_CAT_C_MIPI_DATA_TABLE_SetDefault[];
+#endif
+
+#if IS_3G_DAT_UL1_CUSTOM_SUPPORT
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_DAT_CAT_A_EVENT_TABLE_ptr[UL1_MIPI_DAT_ROUTE_A_NUM];
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_MIPI_DAT_CAT_B_EVENT_TABLE_ptr[UL1_MIPI_DAT_ROUTE_B_NUM];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_MIPI_DAT_CAT_A_DATA_TABLE_ptr[UL1_MIPI_DAT_ROUTE_A_NUM];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_MIPI_DAT_CAT_B_DATA_TABLE_ptr[UL1_MIPI_DAT_ROUTE_B_NUM];
+
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_DAT_CAT_A_MIPI_EVENT_TABLE_PCORE_ptr[UL1_MIPI_DAT_ROUTE_A_NUM];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_DAT_CAT_A_MIPI_DATA_TABLE_PCORE_ptr[UL1_MIPI_DAT_ROUTE_A_NUM];
+extern UL1_MIPI_EVENT_TABLE_T *UMTS_DAT_CAT_B_MIPI_EVENT_TABLE_PCORE_ptr[UL1_MIPI_DAT_ROUTE_B_NUM];
+extern UL1_MIPI_DATA_SUBBAND_TABLE_T *UMTS_DAT_CAT_B_MIPI_DATA_TABLE_PCORE_ptr[UL1_MIPI_DAT_ROUTE_B_NUM];
+
+extern const UL1_MIPI_EVENT_TABLE_T* const UMTS_DAT_CAT_A_MIPI_EVENT_TABLE_SetDefault[];
+extern const UL1_MIPI_DATA_SUBBAND_TABLE_T* const UMTS_DAT_CAT_A_MIPI_DATA_TABLE_SetDefault[];
+extern const UL1_MIPI_EVENT_TABLE_T* const UMTS_DAT_CAT_B_MIPI_EVENT_TABLE_SetDefault[];
+extern const UL1_MIPI_DATA_SUBBAND_TABLE_T* const UMTS_DAT_CAT_B_MIPI_DATA_TABLE_SetDefault[];
+#endif
+
+#endif
+
+#endif /* End of #ifndef UL1D_RF_PUBLIC_H */
+
diff --git a/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data.h b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data.h
new file mode 100644
index 0000000..a62f291
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data.h
@@ -0,0 +1,221 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygen Group Header ****************************************************//**
+ * @addtogroup UL1D_RF_CUSTOM_DATA
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @file ul1d_rf_cal_poc_data.h
+ * @author Neil Chung(MTK08266)
+ * @date 2015.01.26
+ * @brief UL1D RF POC SHM data header file
+ * @details Provide RF POC data structure for PCORE and L1CORE (SHM)
+ ******************************************************************************/
+
+#ifndef __UL1D_RF_CAL_POC_DATA_H__
+#define __UL1D_RF_CAL_POC_DATA_H__
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#if IS_URF_TRINITY_2L
+ #include "ul1d_rf_cal_poc_data_mt6186m.h"
+#elif IS_URF_TRINITY_L_E2
+ #include "ul1d_rf_cal_poc_data_mt6186.h"
+#elif IS_URF_MT6185M || IS_URF_TRINITY_L
+ #include "ul1d_rf_cal_poc_data_mt6185m.h"
+#elif IS_URF_TRINITYE1||IS_URF_COLUMBUS_TO_DO
+ #include "ul1d_rf_cal_poc_data_trinitye1.h"
+#elif IS_URF_MT6177L
+ #include "ul1d_rf_cal_poc_data_mt6177.h"
+#elif IS_URF_MT6173
+ #include "ul1d_rf_cal_poc_data_mt6173.h"
+#else
+ #error "un-defined RF"
+#endif
+
+
+/*******************************************************************************
+ * Global Functions Prototype (Interface)
+ ******************************************************************************/
+
+#endif /*__UL1D_RF_CAL_POC_DATA_H__*/
+
+/* Doxygen Group End ***************************************************//**@}*/
diff --git a/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6173.h b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6173.h
new file mode 100644
index 0000000..6d8294f
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6173.h
@@ -0,0 +1,1115 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygen Group Header ****************************************************//**
+ * @addtogroup UL1D_RF_CUSTOM_DATA
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @file ul1d_rf_cal_poc_data.h
+ * @author Neil Chung(MTK08266)
+ * @date 2015.01.26
+ * @brief UL1D RF POC SHM data header file
+ * @details Provide RF POC data structure for PCORE and L1CORE (SHM)
+ ******************************************************************************/
+
+#ifndef __UL1D_RFC_DATA_MT6173_H__
+#define __UL1D_RFC_DATA_MT6173_H__
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "mml1_rf_cal_def.h"
+
+
+/*******************************************************************************
+ * Typedef
+ ******************************************************************************/
+/** Structure Prototypes can be seen by other files */
+typedef enum
+{
+ UMTSBandNone = 0,
+ UMTSBand1 = 1,
+ UMTSBand2 = 2,
+ UMTSBand3 = 3,
+ UMTSBand4 = 4,
+ UMTSBand5 = 5,
+ UMTSBand6 = 6,
+ UMTSBand7 = 7,
+ UMTSBand8 = 8,
+ UMTSBand9 = 9,
+ UMTSBand10 = 10,
+ UMTSBand11 = 11,
+ UMTSBand12 = 12,
+ UMTSBand13 = 13,
+ UMTSBand14 = 14,
+ UMTSBand15 = 15,
+ UMTSBand16 = 16,
+ UMTSBand17 = 17,
+ UMTSBand18 = 18,
+ UMTSBand19 = 19,
+ UMTSBand20 = 20,
+ UMTSBand21 = 21,
+ UMTSBand22 = 22,
+ UMTSBandcount
+} UMTSBand;
+
+
+/*******************************************************************************
+** RFC dimension define
+*******************************************************************************/
+
+#define UL1D_RXDC_HPM_TIA_GAIN_STEPS (2)
+#define UL1D_RXDC_HPM_PGA_GAIN_STEPS (7)
+#define UL1D_RXDC_LPM_TIA_GAIN_STEPS (1)
+#define UL1D_RXDC_LPM_PGA_GAIN_STEPS (7)
+
+#define UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX (5)
+#define UL1D_RF_RX_ROUTE_MAX (5)
+#define UL1D_RF_RX_DC_COMP_ROUTE_MAX (1)//UL1D_RF_RX_ROUTE_MAX
+#define UL1D_RF_RX_IRR_COMP_ROUTE_MAX (1)
+#define UL1D_RF_RX_IIP2_COMP_ROUTE_MAX (1)//11
+
+#define UL1D_RX_CBW_NUM (MMRFC_UMTS_RX_CBW_NUM )
+#define UL1D_DET_FE_GAIN_STEPS (MMRFC_DET_FE_GAIN_STEPS )
+#define UL1D_DET_GAIN_STEPS (MMRFC_DET_GAIN_STEPS )
+#define UL1D_DET_EQLPF_TAP_NUM (MMRFC_DET_EQLPF_TAP_NUM )
+#define UL1D_TX_PGA_TYPE_NUM (MMRFC_TX_PGA_TYPE_NUM )
+#define UL1D_TX_DNL_PGA_A_GAIN_STEPS (MMRFC_TX_DNL_PGA_A_GAIN_STEPS )
+#define UL1D_TX_DNL_PGA_B_GAIN_STEPS (MMRFC_TX_DNL_PGA_B_GAIN_STEPS )
+#define UL1D_TX_DNL_PGA_AUX_GAIN_STEPS (MMRFC_TX_DNL_PGA_AUX_GAIN_STEPS )
+#define UL1D_TX_PGA_A_SLICE_NUM (MMRFC_TX_PGA_A_SLICE_NUM )
+#define UL1D_TX_PGA_B_SLICE_NUM (MMRFC_TX_PGA_B_SLICE_NUM )
+#define UL1D_TX_DNL_PGA_A_SEQ_NUM (MMRFC_TX_DNL_PGA_A_SEQ_NUM )
+#define UL1D_TX_DNL_PGA_B_SEQ_NUM (MMRFC_TX_DNL_PGA_B_SEQ_NUM )
+#define UL1D_TX_CBW_NUM (MMRFC_UMTS_TX_CBW_NUM )
+#define UL1D_TX_PGA_SLICE_NUM (MMRFC_TX_PGA_SLICE_NUM )
+#define UL1D_TX_RC_LPF_CBW_NUM (MMRFC_TX_RC_LPF_CBW_NUM )
+#define UL1D_TX_PGA_GAIN_STEP_SUBBAND_NUM (MMRFC_TX_PGA_GAIN_STEP_SUBBAND_NUM )
+#define UL1D_TX_PGA_GAIN_STEP_NUM (MMRFC_TX_PGA_GAIN_STEP_NUM )
+#define UL1D_TX_SUBBAND_NUM (MMRFC_TX_SUBBAND_NUM )
+#define UL1D_TX_PGA_CAP_TUNING_SUBBAND_NUM (MMRFC_TX_PGA_CAP_TUNING_SUBBAND_NUM)
+#define UL1D_ANT_NUM (MMRFC_ANT_NUM)
+
+/******************************
+* Rx POC Part
+*******************************/
+typedef struct
+{
+ kal_int8 gain_est_hw;
+ kal_int8 phase_est_hw;
+ kal_int16 freq_dep_filt[UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX];
+} UMTS_RF_POC_RX_IRR_COMP_T;
+
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_RX_DC_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_HPM_TIA_GAIN_STEPS][UL1D_RXDC_HPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_HPM_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_LPM_TIA_GAIN_STEPS][UL1D_RXDC_LPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_LPM_COMP_T;
+
+typedef struct
+{
+ kal_int8 gate_bias_i;
+ kal_int8 gate_bias_q;
+} UMTS_RF_POC_RX_IIP2_COMP_T;
+
+typedef struct
+{
+ /* RX IRR */
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_hpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_lpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+
+ /* RX DC */
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_rf_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_rf_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dig_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dig_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+
+ /* RX IIP2 */
+ UMTS_RF_POC_RX_IIP2_COMP_T rx_iip2[UL1D_ANT_NUM][UL1D_RF_RX_IIP2_COMP_ROUTE_MAX];
+
+} UMTS_RF_POC_RX_COMP_DATA_T;
+
+
+/******************************
+* Tx DET POC Part
+*******************************/
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+
+} UMTS_DET_EQLPF_COMP_T;
+
+typedef struct
+{
+ UMTS_DET_EQLPF_COMP_T coef[UL1D_DET_EQLPF_TAP_NUM];
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+} UMTS_DET_FDADPCB_EQLPF_COMP_T;
+
+typedef struct{
+ kal_int8 gain_est_hw; //FIIQ gain
+ kal_int8 phase_est_hw; //FIIQ phase
+ UMTS_DET_FDADPCB_EQLPF_COMP_T fd_ad_pcb; //FDIQ, AD coefficient, 3G do not contain PCB information
+} UMTS_RF_POC_DET_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_DET_DC_COMP_T;
+
+
+
+typedef struct
+{
+ /* DET Coarse DCOC */
+ kal_uint32 det_coarse_dcoc_cw807;
+ kal_uint32 det_coarse_dcoc_cw808;
+
+ /* DET IQ/DC/DNL Forward */
+
+ UMTS_RF_POC_DET_IQ_COMP_T det_iq_fwd[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_fwd[UL1D_DET_GAIN_STEPS];
+ kal_int16 det_dnl_fwd[UL1D_DET_GAIN_STEPS];
+
+ /* DET IQ/DC/DNL Reverse */
+ UMTS_RF_POC_DET_IQ_COMP_T det_iq_rev[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_rev[UL1D_DET_GAIN_STEPS];
+ kal_int16 det_dnl_rev[UL1D_DET_GAIN_STEPS];
+
+} UMTS_RF_POC_DET_COMP_DATA_T;
+
+/******************************
+* Tx FOWRAD POC Part
+*******************************/
+typedef struct{
+ kal_int8 gain_est;
+ kal_int8 phase_est;
+} UMTS_RF_POC_TX_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_TX_DC_COMP_T;
+
+typedef struct{
+ kal_int16 freq_dep_filt[MMRFC_FILT_TAPS_NUM];
+} UMTS_TX_FD_FILT_COMP_T;
+
+typedef struct{
+ kal_int16 re;
+ kal_int16 im;
+} UMTS_COMPLEX_16_T;
+
+typedef struct
+{
+ UMTS_COMPLEX_16_T tx_ga_filt_lin_1[MMRFC_FILT_TAPS_NUM];
+ UMTS_COMPLEX_16_T tx_ga_filt_lin_2[MMRFC_FILT_TAPS_NUM];
+} UMTS_RF_POC_TX_GA_FILT_COMP_T;
+
+typedef struct
+{
+ kal_int16 slope[13];//[MMRFC_TXGA_MAX_TONES-1];
+ kal_int16 mag_inv_norm[14];//[MMRFC_TXGA_MAX_TONES];
+} UMTS_RF_POC_TX_GA_TPC_COMP_T;
+
+typedef struct{
+ UMTS_RF_POC_TX_GA_FILT_COMP_T tx_ga_filt_comp;
+ UMTS_RF_POC_TX_GA_TPC_COMP_T tx_ga_tpc_comp;
+} UMTS_RF_POC_TX_GA_COMP_T;
+
+typedef struct
+{
+ /* TX LO Cal */
+ kal_uint32 tx_lo;
+ kal_uint8 tx_lo_ind;
+ kal_uint8 tx_lo_capcal_peak_cap;
+ kal_uint8 tx_lo_in_bias_hpm;
+ kal_uint8 tx_lo_in_bias_lpm;
+ kal_uint32 stx_dcc_delta_nc;
+
+ /* TX RC */
+ kal_int16 tx_rc_lpf[UL1D_TX_CBW_NUM];
+ kal_int16 tx_rc_rcf;
+
+ /* TX FIIQ/DC/DNL Linear Mode */
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_lin[UL1D_TX_PGA_SLICE_NUM+1];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_lin[UL1D_TX_PGA_SLICE_NUM+1];
+
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_dpd[UL1D_TX_PGA_SLICE_NUM+1];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_dpd[UL1D_TX_PGA_SLICE_NUM+1];
+
+ kal_int16 tx_dnl_lin_pga_a[UL1D_TX_DNL_PGA_A_GAIN_STEPS];
+ kal_int16 tx_dnl_lin_pga_b[UL1D_TX_DNL_PGA_B_GAIN_STEPS+UL1D_TX_DNL_PGA_AUX_GAIN_STEPS];
+
+ /* TX FDIQ Linear Mode 1 */
+ UMTS_TX_FD_FILT_COMP_T tx_fdiq_lin_1[UL1D_TX_CBW_NUM][UL1D_TX_PGA_SLICE_NUM+1];
+ /* TX FDIQ Linear Mode 2 */
+ UMTS_TX_FD_FILT_COMP_T tx_fdiq_lin_2[UL1D_TX_CBW_NUM][UL1D_TX_PGA_SLICE_NUM+1];
+
+ /* TX GA */
+ UMTS_RF_POC_TX_GA_COMP_T tx_ga_w_ET[UL1D_TX_PGA_TYPE_NUM][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_TX_GA_COMP_T tx_ga_wo_ET[UL1D_TX_PGA_TYPE_NUM][UL1D_TX_CBW_NUM];
+
+ /* TX PGA Phase Step */
+ kal_int16 pga_phase_step;
+
+ /* TX PGA Gain Step */
+ kal_int16 pga_gain_step[UL1D_TX_PGA_GAIN_STEP_SUBBAND_NUM][UL1D_TX_PGA_GAIN_STEP_NUM];
+
+ /* TX PGA Cap Tuning */
+ kal_int8 cap_tuning_pga_a;
+ kal_int8 cap_tuning_pga_b;
+
+} UMTS_RF_POC_TX_COMP_DATA_T;
+
+typedef struct
+{
+ kal_uint32 verno;
+ UMTSBand band;
+ UMTS_RF_POC_RX_COMP_DATA_T umts_rx_comp;
+ UMTS_RF_POC_DET_COMP_DATA_T umts_det_comp;
+ UMTS_RF_POC_TX_COMP_DATA_T umts_tx_comp;
+} UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T;
+
+
+/*******************************************************************************
+** Macro define for POC default value
+*******************************************************************************/
+
+
+#define UMTS_RXDC_RF_I_Default (0xFFE0)
+#define UMTS_RXDC_RF_Q_Default (0xFFE0)
+#define UMTS_RXDC_Dig_I_Default (0)
+#define UMTS_RXDC_Dig_Q_Default (0)
+
+#define UMTS_RXDC_RF_IQ_Default \
+{\
+ UMTS_RXDC_RF_I_Default, UMTS_RXDC_RF_Q_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_Default \
+{\
+ UMTS_RXDC_Dig_I_Default,\
+ UMTS_RXDC_Dig_Q_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default,\
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default \
+{\
+/*rx_dc[2:RX_TIA_GAIN_63p5dB][0~6]*/UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+/*rx_dc[3:RX_TIA_GAIN_69p5dB][0~6]*/UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default \
+{\
+/*rx_dc[2:RX_TIA_GAIN_63p5dB][0~6]*/UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+/*rx_dc[3:RX_TIA_GAIN_69p5dB][0~6]*/UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+}
+
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default \
+{\
+ /*rx_dc[0:RX_TIA_GAIN_67p5dB][0~6]*/UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default \
+{\
+ /*rx_dc[0:RX_TIA_GAIN_67p5dB][0~6]*/UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+}
+
+
+#define UMTS_RXDC_RF_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_RF_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+
+
+
+//ANT0/1
+#define W_Rx_Irr_5Tap_Comp_Poc_Default \
+{ \
+ {0,0,{0,0,512,0,0}}, \
+ {0,0,{0,0,512,0,0}}, \
+}
+
+//ANT0/1
+#define W_Rx_Irr_7Tap_Comp_Poc_Default \
+{ \
+ {0,0,{0,0,512,0,0}}, \
+ {0,0,{0,0,512,0,0}}, \
+}
+
+
+
+#define M_IIP2_I_DEFAULT (64)
+#define M_IIP2_Q_DEFAULT (64)
+
+#define W_Rx_Iip2_Comp_Poc_Default {M_IIP2_I_DEFAULT, M_IIP2_Q_DEFAULT}
+
+#define UMTS_TX_FD_Iq_5Tap_Comp_Default {{0,0,511,0,0,0,0}}
+#define UMTS_TX_FD_Iq_7Tap_Comp_Default {{0,0,0,511,0,0,0}}
+
+
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default {0,0,{{{5,5},{-35,-35},{144,144},{-454,-454},{-350,-350},{312,312},{-218,-218},{127,127},{-59,-59},{19,19},{-3,-3}},9,9}}
+#define UMTS_Det_Iq_MG_DC_Comp_Default {0,0,{{{5,5},{-35,-35},{144,144},{-454,-454},{-350,-350},{312,312},{-218,-218},{127,127},{-59,-59},{19,19},{-3,-3}},9,9}}
+#define UMTS_Det_Iq_LG_SC_Comp_Default {0,0,{{{5,5},{-36,-36},{144,144},{-437,-437},{-371,-371},{316,316},{-215,-215},{123,123},{-56,-56},{18,18},{-3,-3}},9,9}}
+#define UMTS_Det_Iq_LG_DC_Comp_Default {0,0,{{{5,5},{-36,-36},{144,144},{-437,-437},{-371,-371},{316,316},{-215,-215},{123,123},{-56,-56},{18,18},{-3,-3}},9,9}}
+
+
+#define UMTS_DET_IQ_MG_DDFAULT \
+ { /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default,\
+ UMTS_Det_Iq_MG_DC_Comp_Default,\
+ },
+
+#define UMTS_DET_IQ_LG_DDFAULT \
+ { /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_LG_SC_Comp_Default,\
+ UMTS_Det_Iq_LG_DC_Comp_Default,\
+ },
+
+#define UMTS_DET_DC_DEFAULT {0/*DC_I*/, 0/*DC_Q*/}
+
+#define UMTS_TX_GA_5tap_Comp_Default \
+{ \
+ { \
+ { {0, 0}, {0, 0}, {0x1FF, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /*tx_ga_filt_lin_1*/ \
+ { {0, 0}, {0, 0}, {0x1FF, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /*tx_ga_filt_lin_2*/ \
+ }, \
+ { \
+ {0,0,0,0,0,0,0,0,0}, /*slope : MMRFC_TXGA_MAX_TONES-1 */ \
+ {0,0,0,0,0,0,0,0,0,0},/*mag_inv_norm : MMRFC_TXGA_MAX_TONES */ \
+ }, \
+}
+
+#define UMTS_TX_GA_7tap_Comp_Default \
+{ \
+ { \
+ { {0, 0}, {0, 0}, {0, 0}, {0x1FF, 0}, {0, 0}, {0, 0}, {0, 0} }, /*tx_ga_filt_lin_1*/ \
+ { {0, 0}, {0, 0}, {0, 0}, {0x1FF, 0}, {0, 0}, {0, 0}, {0, 0} }, /*tx_ga_filt_lin_2*/ \
+ }, \
+ { \
+ {0,0,0,0,0,0,0,0,0}, /*slope : MMRFC_TXGA_MAX_TONES-1 */ \
+ {0,0,0,0,0,0,0,0,0,0},/*mag_inv_norm : MMRFC_TXGA_MAX_TONES */ \
+ }, \
+}
+
+#define TX_FDIQ_5Tap_COMP_DEFAULT \
+{ /* UL1D_TX_PGA_SLICE_NUM+1 = 5 */ \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+}
+#define TX_FDIQ_7Tap_COMP_DEFAULT \
+{ /* UL1D_TX_PGA_SLICE_NUM+1 = 5 */ \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+}
+
+
+#define UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+{ \
+ UMTS_RXDC_RF_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+{ \
+ UMTS_RXDC_RF_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+{ \
+ UMTS_RXDC_Dig_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+{ \
+ UMTS_RXDC_Dig_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+
+#define UL1D_DEFAULT_RFC_RX_IRR_HPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 1, HPM*/ \
+ { \
+ W_Rx_Irr_5Tap_Comp_Poc_Default, \
+ W_Rx_Irr_7Tap_Comp_Poc_Default, \
+ W_Rx_Irr_7Tap_Comp_Poc_Default \
+ }, \
+},
+
+#define UL1D_DEFAULT_RFC_RX_IRR_LPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 5, HPM*/ \
+ { \
+ W_Rx_Irr_5Tap_Comp_Poc_Default, \
+ W_Rx_Irr_7Tap_Comp_Poc_Default, \
+ W_Rx_Irr_7Tap_Comp_Poc_Default \
+ }, \
+},
+
+
+#define UL1D_DEFAULT_RFC_RX_IIP2 \
+{ \
+ { /*RXP*/ \
+ W_Rx_Iip2_Comp_Poc_Default,/*ROUTE00*/ \
+ }, \
+ { /*RXD*/ \
+ W_Rx_Iip2_Comp_Poc_Default,/*ROUTE00*/ \
+ } \
+},
+
+#define UL1D_DEFAULT_RFC_TX_IQ_DC \
+ /*tx_iq_lin*/{{0,0}}, \
+ /*tx_dc_lin*/{{0,0}}, \
+ /*tx_iq_dpd*/{{0,0}}, \
+ /*tx_dc_dpd*/{{0,0}},
+
+//TX part
+#define UL1D_DEFAULT_RFC_DET_CDCOC 0x84210, // Designer David : If you run without POC than use 0x84210 in both of them. This will not apply any offset correction.
+
+
+#define UL1D_DEFAULT_RFC_DET_IQ_FWD \
+ { /* UL1D_DET_FE_GAIN_STEPS = 2 */ \
+ UMTS_DET_IQ_MG_DDFAULT \
+ UMTS_DET_IQ_LG_DDFAULT \
+ },
+
+#define UL1D_DEFAULT_RFC_DET_IQ_REV \
+ { /* UL1D_DET_FE_GAIN_STEPS = 2 */ \
+ UMTS_DET_IQ_MG_DDFAULT \
+ UMTS_DET_IQ_LG_DDFAULT \
+ },
+
+
+
+
+#define UL1D_DEFAULT_RFC_DET_DC_FWD \
+ { /* UL1D_DET_GAIN_STEPS = 15*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG00*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG01*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG02*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG03*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG04*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG05*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG06*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG07*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG08*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG09*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG10*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG11*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG12*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG13*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG14*/ \
+ },
+
+#define UL1D_DEFAULT_RFC_DET_DC_REV \
+ { /* UL1D_DET_GAIN_STEPS = 15*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG00*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG01*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG02*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG03*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG04*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG05*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG06*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG07*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG08*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG09*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG10*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG11*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG12*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG13*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG14*/ \
+ },
+
+
+
+
+
+
+#define UL1D_DEFAULT_RFC_TX_GA \
+{ \
+ /*tx_ga_w_ET*/ \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+}, \
+{ \
+ /*tx_ga_wo_ET*/ \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+}, \
+
+
+
+
+/* Default value from MT6177L, FXP=s6.5 */
+#define UL1D_DEFAULT_RFC_DET_DNL \
+{ \
+ 918, /* G0*/ \
+ 822, /* G1*/ \
+ 726, /* G2*/ \
+ 630, /* G3*/ \
+ 534, /* G4*/ \
+ 438, /* G5*/ \
+ 342, /* G6*/ \
+ 342, /* G7*/ \
+ 246, /* G8*/ \
+ 150, /* G9*/ \
+ 54, /* G10*/ \
+ -42, /* G11*/ \
+ -138, /* G12*/ \
+ -234, /* G13*/ \
+ -330, /* G14*/ \
+},
+
+#define UL1D_DEFAULT_RFC_DET_DNL_FWD UL1D_DEFAULT_RFC_DET_DNL
+#define UL1D_DEFAULT_RFC_DET_DNL_REV UL1D_DEFAULT_RFC_DET_DNL
+
+
+
+
+
+//pga_gain_step[UL1D_TX_PGA_GAIN_STEP_SUBBAND_NUM/*12*/][UL1D_TX_PGA_GAIN_STEP_NUM/*10*/]
+#define UL1D_DEFAULT_RFC_TX_PGA_AB \
+{ \
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_PHASE (0),
+
+
+
+
+#define UL1D_DEFAULT_RFC_TX_LO_BNone \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0x2C, \
+ /*tx_lo_in_bias_hpm */0x0F, \
+ /*tx_lo_in_bias_lpm */0x0F, \
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B1 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */1, \
+ /*tx_lo_capcal_peak_cap*/0xF, \
+ /*tx_lo_in_bias_hpm */0x8, \
+ /*tx_lo_in_bias_lpm */0x8, \
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B2 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */1, \
+ /*tx_lo_capcal_peak_cap*/0x17,\
+ /*tx_lo_in_bias_hpm */0x0C,\
+ /*tx_lo_in_bias_lpm */0x0C,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B3 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0x51,\
+ /*tx_lo_in_bias_hpm */0x1D,\
+ /*tx_lo_in_bias_lpm */0x1D,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B4 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */1, \
+ /*tx_lo_capcal_peak_cap*/0x2B,\
+ /*tx_lo_in_bias_hpm */0x0F,\
+ /*tx_lo_in_bias_lpm */0x0F,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B5 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */1, \
+ /*tx_lo_capcal_peak_cap*/0x24,\
+ /*tx_lo_in_bias_hpm */0x0E,\
+ /*tx_lo_in_bias_lpm */0x0E,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B6 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0, \
+ /*tx_lo_in_bias_hpm */0, \
+ /*tx_lo_in_bias_lpm */0, \
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B8 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */1, \
+ /*tx_lo_capcal_peak_cap*/0x14,\
+ /*tx_lo_in_bias_hpm */0x0C,\
+ /*tx_lo_in_bias_lpm */0x0C,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B9 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0x51,\
+ /*tx_lo_in_bias_hpm */0x1D,\
+ /*tx_lo_in_bias_lpm */0x1D,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B11 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */1, \
+ /*tx_lo_capcal_peak_cap*/0x52,\
+ /*tx_lo_in_bias_hpm */0x1B,\
+ /*tx_lo_in_bias_lpm */0x1B,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B18 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0, \
+ /*tx_lo_in_bias_hpm */0, \
+ /*tx_lo_in_bias_lpm */0, \
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B19 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0, \
+ /*tx_lo_in_bias_hpm */0, \
+ /*tx_lo_in_bias_lpm */0, \
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_BNone \
+ /*tx_rc_lpf*/{160,128},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B1 \
+ /*tx_rc_lpf*/{26,21},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B2 \
+ /*tx_rc_lpf*/{26,21},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B3 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B4 \
+ /*tx_rc_lpf*/{26,21},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B5 \
+ /*tx_rc_lpf*/{26,21},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B6 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B8 \
+ /*tx_rc_lpf*/{26,21},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B9 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B11 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B18 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B19 \
+ /*tx_rc_lpf*/{172,138},
+
+
+#define UL1D_DEFAULT_RFC_TX_RC_RCF \
+ /* MT6173_3wire_Table, #RCF, 16&20MHz*/(0x10),
+
+#define UL1D_DEFAULT_RFC_TX_CAP_BNone \
+ /*cap_tuning_pga_a*/5, \
+ /*cap_tuning_pga_b*/14,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B1 \
+ /*cap_tuning_pga_a*/0xB,\
+ /*cap_tuning_pga_b*/0xB,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B2 \
+ /*cap_tuning_pga_a*/0xF,\
+ /*cap_tuning_pga_b*/0xF,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B3 \
+ /*cap_tuning_pga_a*/0x13,\
+ /*cap_tuning_pga_b*/0x15,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B4 \
+ /*cap_tuning_pga_a*/0x18,\
+ /*cap_tuning_pga_b*/0x18,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B5 \
+ /*cap_tuning_pga_a*/0x11,\
+ /*cap_tuning_pga_b*/0x11,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B6 \
+ /*cap_tuning_pga_a*/0xC,\
+ /*cap_tuning_pga_b*/0xA,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B8 \
+ /*cap_tuning_pga_a*/0xD,\
+ /*cap_tuning_pga_b*/0xD,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B9 \
+ /*cap_tuning_pga_a*/0xF,\
+ /*cap_tuning_pga_b*/0x16,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B11 \
+ /*cap_tuning_pga_a*/0x27,\
+ /*cap_tuning_pga_b*/0x2A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B18 \
+ /*cap_tuning_pga_a*/0xF,\
+ /*cap_tuning_pga_b*/0xD,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B19 \
+ /*cap_tuning_pga_a*/0xD,\
+ /*cap_tuning_pga_b*/0xC,
+
+
+
+#define UL1D_DEFAULT_RFC_TX_DNL_PGA_A \
+{ \
+ 0, /* G0, 0dB */ \
+ -18, /* G1, -0.56dB */ \
+ -37, /* G2, -1.16dB */ \
+ -58, /* G3, -1.80dB */ \
+ -80, /* G4, -2.50dB */ \
+ -104, /* G5, -3.25dB */ \
+ -131, /* G6, -4.08dB */ \
+ -160, /* G7, -5.00dB */ \
+ -193, /* G8, -6.02dB */ \
+ -230, /* G9, -7.18dB */ \
+ -273, /* G10, -8.52dB */ \
+ -323, /* G11, -10.10dB */ \
+ -385, /* G12, -12.04dB */ \
+ -465, /* G13, -14.54dB */ \
+ -578, /* G14, -18.06dB */ \
+ -615, /* G15, -19.22dB */ \
+ -658, /* G16, -20.56dB */ \
+ -709, /* G17, -22.14dB */ \
+ -771, /* G18, -24.08dB */ \
+ -851, /* G19, -26.58dB */ \
+ -963 /* G20, -30.10dB */ \
+ -1156 /* G21, -36.12dB */ \
+},
+
+#define UL1D_DEFAULT_RFC_TX_DNL_PGA_B \
+{ \
+ -1188, /* G22, -37.12dB */ \
+ -1380, /* G23, -43.12dB */ \
+ -1572, /* G24, -49.12dB */ \
+ -1764, /* G25, -55.12dB */ \
+ -1956, /* G26, -61.12dB */ \
+ -2148, /* G27, -67.12dB */ \
+ -2340, /* G28, -73.12dB */ \
+ -2532, /* G29, -79.12dB */ \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_FDIQ \
+{ /*UL1D_TX_CBW_NUM = 2*/ \
+ TX_FDIQ_5Tap_COMP_DEFAULT, \
+ TX_FDIQ_7Tap_COMP_DEFAULT, \
+}, /*tx_fdiq_lin_1*/ \
+{ /*UL1D_TX_CBW_NUM = 2*/ \
+ TX_FDIQ_5Tap_COMP_DEFAULT, \
+ TX_FDIQ_7Tap_COMP_DEFAULT, \
+}, /*tx_fdiq_lin_2*/
+
+
+#define VERNO_BNone (0),
+#define VERNO_B1 (0),
+#define VERNO_B2 (0),
+#define VERNO_B3 (0),
+#define VERNO_B4 (0),
+#define VERNO_B5 (0),
+#define VERNO_B6 (0),
+#define VERNO_B8 (0),
+#define VERNO_B9 (0),
+#define VERNO_B11 (0),
+#define VERNO_B18 (0),
+#define VERNO_B19 (0),
+
+
+#define M_UL1D_DEFAULT_RFC_B(BAND_ID) \
+{ \
+ VERNO_B##BAND_ID \
+ UMTSBand##BAND_ID, \
+ { \
+ UL1D_DEFAULT_RFC_RX_IRR_HPM \
+ UL1D_DEFAULT_RFC_RX_IRR_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+ UL1D_DEFAULT_RFC_RX_IIP2 \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_DET_CDCOC \
+ UL1D_DEFAULT_RFC_DET_CDCOC \
+ UL1D_DEFAULT_RFC_DET_IQ_FWD \
+ UL1D_DEFAULT_RFC_DET_DC_FWD \
+ UL1D_DEFAULT_RFC_DET_DNL_FWD \
+ UL1D_DEFAULT_RFC_DET_IQ_REV \
+ UL1D_DEFAULT_RFC_DET_DC_REV \
+ UL1D_DEFAULT_RFC_DET_DNL_REV \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_TX_LO_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_RC_LPF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_RC_RCF \
+ UL1D_DEFAULT_RFC_TX_IQ_DC \
+ UL1D_DEFAULT_RFC_TX_DNL_PGA_A \
+ UL1D_DEFAULT_RFC_TX_DNL_PGA_B \
+ UL1D_DEFAULT_RFC_TX_FDIQ \
+ UL1D_DEFAULT_RFC_TX_GA \
+ UL1D_DEFAULT_RFC_TX_PGA_PHASE \
+ UL1D_DEFAULT_RFC_TX_PGA_AB \
+ UL1D_DEFAULT_RFC_TX_CAP_B##BAND_ID \
+ } \
+}
+
+#if UMTS_POC_RECAL_ENABLE
+/******************************
+* POC Recal Part
+*******************************/
+typedef struct
+{
+ kal_int8 gain_est_hw;
+ kal_int8 phase_est_hw;
+ kal_int16 freq_dep_filt[MMRFC_FILT_TAPS_NUM];
+} UMTS_RX_IRR_RESULT_DBG_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RX_DC_RESULT_DBG_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[MMRFC_RXDC_TIA_GAIN_STEPS][MMRFC_RXDC_PGA_GAIN_WCDMA_STEPS];
+} UMTS_RX_DC_HPM_RESULT_DBG_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[MMRFC_RXDC_TIA_GAIN_LPM_STEPS][MMRFC_RXDC_PGA_GAIN_LPM_STEPS];
+} UMTS_RX_DC_LPM_RESULT_DBG_T;
+
+typedef struct{
+ kal_int8 gain_est;
+ kal_int8 phase_est;
+} UMTS_TX_IQ_RESULT_DBG_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_TX_DC_RESULT_DBG_T;
+
+
+typedef struct
+{
+ /* RX IRR */
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_hpm_recal[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_lpm_recal[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dc_hpm_recal[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dc_lpm_recal[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+
+ /* DET Coarse DCOC */
+ kal_uint32 det_coarse_dcoc_cw807;
+ kal_uint32 det_coarse_dcoc_cw808;
+
+ /* DET IQ/DC/DNL Forward */
+ UMTS_RF_POC_DET_IQ_COMP_T det_iq_fwd[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_fwd[UL1D_DET_GAIN_STEPS];
+ kal_int16 det_dnl_fwd[UL1D_DET_GAIN_STEPS];
+
+ /* TX */
+ UMTS_TX_IQ_RESULT_DBG_T tx_iq_lin[UL1D_TX_PGA_SLICE_NUM+1];
+ UMTS_TX_DC_RESULT_DBG_T tx_dc_lin[UL1D_TX_PGA_SLICE_NUM+1];
+
+ UMTS_TX_IQ_RESULT_DBG_T tx_iq_dpd[UL1D_TX_PGA_SLICE_NUM+1];
+ UMTS_TX_DC_RESULT_DBG_T tx_dc_dpd[UL1D_TX_PGA_SLICE_NUM+1];
+}UMTS_RF_POC_RECAL_DATA_T;
+
+#endif/*UMTS_POC_RECAL_ENABLE*/
+
+
+#endif /*__UL1D_RFC_DATA_MT6173_H__*/
+
+/* Doxygen Group End ***************************************************//**@}*/
diff --git a/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6177.h b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6177.h
new file mode 100644
index 0000000..df3b482
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6177.h
@@ -0,0 +1,1121 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygen Group Header ****************************************************//**
+ * @addtogroup UL1D_RF_CUSTOM_DATA
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @file ul1d_rf_cal_poc_data.h
+ * @author Neil Chung(MTK08266)
+ * @date 2015.01.26
+ * @brief UL1D RF POC SHM data header file
+ * @details Provide RF POC data structure for PCORE and L1CORE (SHM)
+ ******************************************************************************/
+
+#ifndef __UL1D_RFC_DATA_MT6177_H__
+#define __UL1D_RFC_DATA_MT6177_H__
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "mml1_rf_cal_def.h"
+
+
+/*******************************************************************************
+ * Typedef
+ ******************************************************************************/
+/** Structure Prototypes can be seen by other files */
+typedef enum
+{
+ UMTSBandNone = 0,
+ UMTSBand1 = 1,
+ UMTSBand2 = 2,
+ UMTSBand3 = 3,
+ UMTSBand4 = 4,
+ UMTSBand5 = 5,
+ UMTSBand6 = 6,
+ UMTSBand7 = 7,
+ UMTSBand8 = 8,
+ UMTSBand9 = 9,
+ UMTSBand10 = 10,
+ UMTSBand11 = 11,
+ UMTSBand12 = 12,
+ UMTSBand13 = 13,
+ UMTSBand14 = 14,
+ UMTSBand15 = 15,
+ UMTSBand16 = 16,
+ UMTSBand17 = 17,
+ UMTSBand18 = 18,
+ UMTSBand19 = 19,
+ UMTSBand20 = 20,
+ UMTSBand21 = 21,
+ UMTSBand22 = 22,
+ UMTSBandcount
+} UMTSBand;
+
+/*******************************************************************************
+** RFC dimension define
+*******************************************************************************/
+
+#define UL1D_RXDC_HPM_TIA_GAIN_STEPS (2)
+#define UL1D_RXDC_HPM_PGA_GAIN_STEPS (7)
+#define UL1D_RXDC_LPM_TIA_GAIN_STEPS (1)
+#define UL1D_RXDC_LPM_PGA_GAIN_STEPS (7)
+
+#define UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX (5)
+#define UL1D_RF_RX_ROUTE_MAX (5)
+#define UL1D_RF_RX_DC_COMP_ROUTE_MAX (1)//UL1D_RF_RX_ROUTE_MAX
+#define UL1D_RF_RX_IRR_COMP_ROUTE_MAX (1)
+#define UL1D_RF_RX_IIP2_COMP_ROUTE_MAX (1)//11
+
+#define UL1D_RX_CBW_NUM (MMRFC_UMTS_RX_CBW_NUM )
+#define UL1D_DET_FE_GAIN_STEPS (MMRFC_DET_FE_GAIN_STEPS )
+#define UL1D_DET_GAIN_STEPS (MMRFC_DET_GAIN_STEPS )
+#define UL1D_DET_EQLPF_TAP_NUM (MMRFC_DET_EQLPF_TAP_NUM )
+#define UL1D_TX_PGA_TYPE_NUM (MMRFC_TX_PGA_TYPE_NUM )
+#define UL1D_TX_DNL_PGA_A_GAIN_STEPS (MMRFC_TX_DNL_PGA_A_GAIN_STEPS )
+#define UL1D_TX_DNL_PGA_B_GAIN_STEPS (MMRFC_TX_DNL_PGA_B_GAIN_STEPS )
+#define UL1D_TX_DNL_PGA_AUX_GAIN_STEPS (MMRFC_TX_DNL_PGA_AUX_GAIN_STEPS )
+#define UL1D_TX_PGA_A_SLICE_NUM (MMRFC_TX_PGA_A_SLICE_NUM )
+#define UL1D_TX_PGA_B_SLICE_NUM (MMRFC_TX_PGA_B_SLICE_NUM )
+#define UL1D_TX_DNL_PGA_A_SEQ_NUM (MMRFC_TX_DNL_PGA_A_SEQ_NUM )
+#define UL1D_TX_DNL_PGA_B_SEQ_NUM (MMRFC_TX_DNL_PGA_B_SEQ_NUM )
+#define UL1D_TX_CBW_NUM (MMRFC_UMTS_TX_CBW_NUM )
+#define UL1D_TX_PGA_SLICE_NUM (MMRFC_TX_PGA_SLICE_NUM )
+#define UL1D_TX_RC_LPF_CBW_NUM (MMRFC_TX_RC_LPF_CBW_NUM )
+#define UL1D_TX_PGA_GAIN_STEP_SUBBAND_NUM (MMRFC_TX_PGA_GAIN_STEP_SUBBAND_NUM )
+#define UL1D_TX_PGA_GAIN_STEP_NUM (MMRFC_TX_PGA_GAIN_STEP_NUM )
+#define UL1D_TX_SUBBAND_NUM (MMRFC_TX_SUBBAND_NUM )
+#define UL1D_TX_PGA_CAP_TUNING_SUBBAND_NUM (MMRFC_TX_PGA_CAP_TUNING_SUBBAND_NUM)
+#define UL1D_ANT_NUM (MMRFC_ANT_NUM)
+
+
+
+/******************************
+* Rx POC Part
+*******************************/
+typedef struct
+{
+ kal_int8 gain_est_hw;
+ kal_int8 phase_est_hw;
+ kal_int16 freq_dep_filt[UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX];
+} UMTS_RF_POC_RX_IRR_COMP_T;
+
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_RX_DC_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_HPM_TIA_GAIN_STEPS][UL1D_RXDC_HPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_HPM_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_LPM_TIA_GAIN_STEPS][UL1D_RXDC_LPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_LPM_COMP_T;
+
+typedef struct
+{
+ kal_int8 gate_bias_i;
+ kal_int8 gate_bias_q;
+} UMTS_RF_POC_RX_IIP2_COMP_T;
+
+typedef struct
+{
+ /* RX IRR */
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_hpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_lpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+
+ /* RX DC */
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_rf_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_rf_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dig_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dig_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+
+ /* RX IIP2 */
+ UMTS_RF_POC_RX_IIP2_COMP_T rx_iip2[UL1D_ANT_NUM][UL1D_RF_RX_IIP2_COMP_ROUTE_MAX];
+
+} UMTS_RF_POC_RX_COMP_DATA_T;
+
+
+/******************************
+* Tx DET POC Part
+*******************************/
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+
+} UMTS_DET_EQLPF_COMP_T;
+
+typedef struct
+{
+ UMTS_DET_EQLPF_COMP_T coef[UL1D_DET_EQLPF_TAP_NUM];
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+} UMTS_DET_FDADPCB_EQLPF_COMP_T;
+
+typedef struct{
+ kal_int8 gain_est_hw; //FIIQ gain
+ kal_int8 phase_est_hw; //FIIQ phase
+ UMTS_DET_FDADPCB_EQLPF_COMP_T fd_ad_pcb; //FDIQ, AD coefficient, 3G do not contain PCB information
+} UMTS_RF_POC_DET_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_DET_DC_COMP_T;
+
+
+
+typedef struct
+{
+ /* DET Coarse DCOC */
+ kal_uint32 det_coarse_dcoc_cw807;
+ kal_uint32 det_coarse_dcoc_cw808;
+
+ /* DET IQ/DC/DNL Forward */
+
+ UMTS_RF_POC_DET_IQ_COMP_T det_iq_fwd[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_fwd[UL1D_DET_GAIN_STEPS];
+ kal_int16 det_dnl_fwd[UL1D_DET_GAIN_STEPS];
+
+ /* DET IQ/DC/DNL Reverse */
+ UMTS_RF_POC_DET_IQ_COMP_T det_iq_rev[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_rev[UL1D_DET_GAIN_STEPS];
+ kal_int16 det_dnl_rev[UL1D_DET_GAIN_STEPS];
+
+} UMTS_RF_POC_DET_COMP_DATA_T;
+
+/******************************
+* Tx FOWRAD POC Part
+*******************************/
+typedef struct{
+ kal_int8 gain_est;
+ kal_int8 phase_est;
+} UMTS_RF_POC_TX_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_TX_DC_COMP_T;
+
+typedef struct{
+ kal_int16 freq_dep_filt[MMRFC_FILT_TAPS_NUM];
+} UMTS_TX_FD_FILT_COMP_T;
+
+typedef struct{
+ kal_int16 re;
+ kal_int16 im;
+} UMTS_COMPLEX_16_T;
+
+typedef struct
+{
+ UMTS_COMPLEX_16_T tx_ga_filt_lin_1[MMRFC_FILT_TAPS_NUM];
+ UMTS_COMPLEX_16_T tx_ga_filt_lin_2[MMRFC_FILT_TAPS_NUM];
+} UMTS_RF_POC_TX_GA_FILT_COMP_T;
+
+typedef struct
+{
+ kal_int16 slope[13];//[MMRFC_TXGA_MAX_TONES-1];
+ kal_int16 mag_inv_norm[14];//[MMRFC_TXGA_MAX_TONES];
+} UMTS_RF_POC_TX_GA_TPC_COMP_T;
+
+typedef struct{
+ UMTS_RF_POC_TX_GA_FILT_COMP_T tx_ga_filt_comp;
+ UMTS_RF_POC_TX_GA_TPC_COMP_T tx_ga_tpc_comp;
+} UMTS_RF_POC_TX_GA_COMP_T;
+
+typedef struct
+{
+ /* TX LO Cal */
+ kal_uint32 tx_lo;
+ kal_uint8 tx_lo_ind;
+ kal_uint8 tx_lo_capcal_peak_cap;
+ kal_uint8 tx_lo_in_bias_hpm;
+ kal_uint8 tx_lo_in_bias_lpm;
+ kal_uint32 stx_dcc_delta_nc;
+
+ /* TX RC */
+ kal_int16 tx_rc_lpf[UL1D_TX_CBW_NUM];
+ kal_int16 tx_rc_rcf;
+
+ /* TX FIIQ/DC/DNL Linear Mode */
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_lin[UL1D_TX_PGA_SLICE_NUM+1];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_lin[UL1D_TX_PGA_SLICE_NUM+1];
+
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_dpd[UL1D_TX_PGA_SLICE_NUM+1];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_dpd[UL1D_TX_PGA_SLICE_NUM+1];
+
+ kal_int16 tx_dnl_lin_pga_a[UL1D_TX_DNL_PGA_A_GAIN_STEPS];
+ kal_int16 tx_dnl_lin_pga_b[UL1D_TX_DNL_PGA_B_GAIN_STEPS+UL1D_TX_DNL_PGA_AUX_GAIN_STEPS];
+
+ /* TX FDIQ Linear Mode 1 */
+ UMTS_TX_FD_FILT_COMP_T tx_fdiq_lin_1[UL1D_TX_CBW_NUM][UL1D_TX_PGA_SLICE_NUM+1];
+ /* TX FDIQ Linear Mode 2 */
+ UMTS_TX_FD_FILT_COMP_T tx_fdiq_lin_2[UL1D_TX_CBW_NUM][UL1D_TX_PGA_SLICE_NUM+1];
+
+ /* TX GA */
+ UMTS_RF_POC_TX_GA_COMP_T tx_ga_w_ET[UL1D_TX_PGA_TYPE_NUM][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_TX_GA_COMP_T tx_ga_wo_ET[UL1D_TX_PGA_TYPE_NUM][UL1D_TX_CBW_NUM];
+
+ /* TX PGA Phase Step */
+ kal_int16 pga_phase_step;
+
+ /* TX PGA Gain Step */
+ kal_int16 pga_gain_step[UL1D_TX_PGA_GAIN_STEP_SUBBAND_NUM][UL1D_TX_PGA_GAIN_STEP_NUM];
+
+ /* TX PGA Cap Tuning */
+ kal_int8 cap_tuning_pga_a;
+ kal_int8 cap_tuning_pga_b;
+
+} UMTS_RF_POC_TX_COMP_DATA_T;
+
+typedef struct
+{
+ kal_uint32 verno;
+ UMTSBand band;
+ UMTS_RF_POC_RX_COMP_DATA_T umts_rx_comp;
+ UMTS_RF_POC_DET_COMP_DATA_T umts_det_comp;
+ UMTS_RF_POC_TX_COMP_DATA_T umts_tx_comp;
+} UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T;
+
+
+/*******************************************************************************
+** Macro define for POC default value
+*******************************************************************************/
+
+#define UMTS_RXDC_RF_I_Default (0xFFE0)
+#define UMTS_RXDC_RF_Q_Default (0xFFE0)
+#define UMTS_RXDC_Dig_I_Default (0)
+#define UMTS_RXDC_Dig_Q_Default (0)
+
+#define UMTS_RXDC_RF_IQ_Default \
+{\
+ UMTS_RXDC_RF_I_Default, UMTS_RXDC_RF_Q_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_Default \
+{\
+ UMTS_RXDC_Dig_I_Default,\
+ UMTS_RXDC_Dig_Q_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default,\
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default \
+{\
+/*rx_dc[2:RX_TIA_GAIN_63p5dB][0~6]*/UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+/*rx_dc[3:RX_TIA_GAIN_69p5dB][0~6]*/UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default \
+{\
+/*rx_dc[2:RX_TIA_GAIN_63p5dB][0~6]*/UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+/*rx_dc[3:RX_TIA_GAIN_69p5dB][0~6]*/UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+}
+
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default \
+{\
+ /*rx_dc[0:RX_TIA_GAIN_67p5dB][0~6]*/UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default \
+{\
+ /*rx_dc[0:RX_TIA_GAIN_67p5dB][0~6]*/UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+}
+
+
+#define UMTS_RXDC_RF_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_RF_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+
+//ANT0/1
+#define W_Rx_Irr_5Tap_Comp_Poc_Default \
+{ \
+ {0,0,{0,0,512,0,0}}, \
+ {0,0,{0,0,512,0,0}}, \
+}
+
+//ANT0/1
+#define W_Rx_Irr_7Tap_Comp_Poc_Default \
+{ \
+ {0,0,{0,0,512,0,0}}, \
+ {0,0,{0,0,512,0,0}}, \
+}
+
+
+
+
+#define M_IIP2_I_DEFAULT (64)
+#define M_IIP2_Q_DEFAULT (64)
+
+#define W_Rx_Iip2_Comp_Poc_Default {M_IIP2_I_DEFAULT, M_IIP2_Q_DEFAULT}
+
+#define UMTS_TX_FD_Iq_5Tap_Comp_Default {{0,0,511,0,0,0,0}}
+#define UMTS_TX_FD_Iq_7Tap_Comp_Default {{0,0,0,511,0,0,0}}
+
+
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default {0,0,{{{5,5},{-35,-35},{144,144},{-454,-454},{-350,-350},{312,312},{-218,-218},{127,127},{-59,-59},{19,19},{-3,-3}},9,9}}
+#define UMTS_Det_Iq_MG_DC_Comp_Default {0,0,{{{5,5},{-35,-35},{144,144},{-454,-454},{-350,-350},{312,312},{-218,-218},{127,127},{-59,-59},{19,19},{-3,-3}},9,9}}
+#define UMTS_Det_Iq_LG_SC_Comp_Default {0,0,{{{5,5},{-36,-36},{144,144},{-437,-437},{-371,-371},{316,316},{-215,-215},{123,123},{-56,-56},{18,18},{-3,-3}},9,9}}
+#define UMTS_Det_Iq_LG_DC_Comp_Default {0,0,{{{5,5},{-36,-36},{144,144},{-437,-437},{-371,-371},{316,316},{-215,-215},{123,123},{-56,-56},{18,18},{-3,-3}},9,9}}
+
+
+#define UMTS_DET_IQ_MG_DDFAULT \
+ { /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default,\
+ UMTS_Det_Iq_MG_DC_Comp_Default,\
+ },
+
+#define UMTS_DET_IQ_LG_DDFAULT \
+ { /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_LG_SC_Comp_Default,\
+ UMTS_Det_Iq_LG_DC_Comp_Default,\
+ },
+
+#define UMTS_DET_DC_DEFAULT {0/*DC_I*/, 0/*DC_Q*/}
+
+
+#define UMTS_TX_GA_5tap_Comp_Default \
+{ \
+ { \
+ { {0, 0}, {0, 0}, {0x1FF, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /*tx_ga_filt_lin_1*/ \
+ { {0, 0}, {0, 0}, {0x1FF, 0}, {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /*tx_ga_filt_lin_2*/ \
+ }, \
+ { \
+ {0,0,0,0,0,0,0,0,0}, /*slope : MMRFC_TXGA_MAX_TONES-1 */ \
+ {0,0,0,0,0,0,0,0,0,0},/*mag_inv_norm : MMRFC_TXGA_MAX_TONES */ \
+ }, \
+}
+
+#define UMTS_TX_GA_7tap_Comp_Default \
+{ \
+ { \
+ { {0, 0}, {0, 0}, {0, 0}, {0x1FF, 0}, {0, 0}, {0, 0}, {0, 0} }, /*tx_ga_filt_lin_1*/ \
+ { {0, 0}, {0, 0}, {0, 0}, {0x1FF, 0}, {0, 0}, {0, 0}, {0, 0} }, /*tx_ga_filt_lin_2*/ \
+ }, \
+ { \
+ {0,0,0,0,0,0,0,0,0}, /*slope : MMRFC_TXGA_MAX_TONES-1 */ \
+ {0,0,0,0,0,0,0,0,0,0},/*mag_inv_norm : MMRFC_TXGA_MAX_TONES */ \
+ }, \
+}
+
+#define TX_FDIQ_5Tap_COMP_DEFAULT \
+{ /* UL1D_TX_PGA_SLICE_NUM+1 = 8 */ \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_5Tap_Comp_Default, \
+ }
+#define TX_FDIQ_7Tap_COMP_DEFAULT \
+{ /* UL1D_TX_PGA_SLICE_NUM+1 = 8 */ \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ UMTS_TX_FD_Iq_7Tap_Comp_Default, \
+ }
+
+
+#define UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+{ \
+ UMTS_RXDC_RF_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+{ \
+ UMTS_RXDC_RF_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+{ \
+ UMTS_RXDC_Dig_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+{ \
+ UMTS_RXDC_Dig_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+
+#define UL1D_DEFAULT_RFC_RX_IRR_HPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 1, HPM*/ \
+ { \
+ W_Rx_Irr_5Tap_Comp_Poc_Default, \
+ W_Rx_Irr_7Tap_Comp_Poc_Default, \
+ W_Rx_Irr_7Tap_Comp_Poc_Default \
+ }, \
+},
+
+#define UL1D_DEFAULT_RFC_RX_IRR_LPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 5, HPM*/ \
+ { \
+ W_Rx_Irr_5Tap_Comp_Poc_Default, \
+ W_Rx_Irr_7Tap_Comp_Poc_Default, \
+ W_Rx_Irr_7Tap_Comp_Poc_Default \
+ }, \
+},
+
+
+#define UL1D_DEFAULT_RFC_RX_IIP2 \
+{ \
+ { /*RXP*/ \
+ W_Rx_Iip2_Comp_Poc_Default,/*ROUTE00*/ \
+ }, \
+ { /*RXD*/ \
+ W_Rx_Iip2_Comp_Poc_Default,/*ROUTE00*/ \
+ } \
+},
+
+#define UL1D_DEFAULT_RFC_TX_IQ_DC \
+ /*tx_iq_lin*/{{0,0}}, \
+ /*tx_dc_lin*/{{0,0}}, \
+ /*tx_iq_dpd*/{{0,0}}, \
+ /*tx_dc_dpd*/{{0,0}},
+
+//TX part
+#define UL1D_DEFAULT_RFC_DET_CDCOC 0x84210, // Designer David : If you run without POC than use 0x84210 in both of them. This will not apply any offset correction.
+
+
+#define UL1D_DEFAULT_RFC_DET_IQ_FWD \
+ { /* UL1D_DET_FE_GAIN_STEPS = 2 */ \
+ UMTS_DET_IQ_MG_DDFAULT \
+ UMTS_DET_IQ_LG_DDFAULT \
+ },
+
+#define UL1D_DEFAULT_RFC_DET_IQ_REV \
+ { /* UL1D_DET_FE_GAIN_STEPS = 2 */ \
+ UMTS_DET_IQ_MG_DDFAULT \
+ UMTS_DET_IQ_LG_DDFAULT \
+ },
+
+#define UL1D_DEFAULT_RFC_DET_DC_FWD \
+ { /* UL1D_DET_GAIN_STEPS = 15*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG00*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG01*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG02*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG03*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG04*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG05*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG06*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG07*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG08*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG09*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG10*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG11*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG12*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG13*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG14*/ \
+ },
+
+#define UL1D_DEFAULT_RFC_DET_DC_REV \
+ { /* UL1D_DET_GAIN_STEPS = 15*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG00*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG01*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG02*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG03*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG04*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG05*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG06*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG07*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG08*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG09*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG10*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG11*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG12*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG13*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG14*/ \
+ },
+
+#define UL1D_DEFAULT_RFC_TX_GA \
+{ \
+ /*tx_ga_w_ET*/ \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+}, \
+{ \
+ /*tx_ga_wo_ET*/ \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+ { \
+ UMTS_TX_GA_5tap_Comp_Default, \
+ UMTS_TX_GA_7tap_Comp_Default, \
+ }, \
+}, \
+
+
+
+
+/* Default value from MT6177L, FXP=s6.5 */
+#define UL1D_DEFAULT_RFC_DET_DNL \
+{ \
+ 918, /* G0*/ \
+ 822, /* G1*/ \
+ 726, /* G2*/ \
+ 630, /* G3*/ \
+ 534, /* G4*/ \
+ 438, /* G5*/ \
+ 342, /* G6*/ \
+ 342, /* G7*/ \
+ 246, /* G8*/ \
+ 150, /* G9*/ \
+ 54, /* G10*/ \
+ -42, /* G11*/ \
+ -138, /* G12*/ \
+ -234, /* G13*/ \
+ -330, /* G14*/ \
+},
+
+#define UL1D_DEFAULT_RFC_DET_DNL_FWD UL1D_DEFAULT_RFC_DET_DNL
+#define UL1D_DEFAULT_RFC_DET_DNL_REV UL1D_DEFAULT_RFC_DET_DNL
+
+
+
+
+
+//pga_gain_step[UL1D_TX_PGA_GAIN_STEP_SUBBAND_NUM/*12*/][UL1D_TX_PGA_GAIN_STEP_NUM/*10*/]
+#define UL1D_DEFAULT_RFC_TX_PGA_AB \
+{ \
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},\
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_PHASE (0),
+
+
+
+
+#define UL1D_DEFAULT_RFC_TX_LO_BNone \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0x2C, \
+ /*tx_lo_in_bias_hpm */0x0F, \
+ /*tx_lo_in_bias_lpm */0x0F, \
+ /*stx_delta_duty_cycle */0,
+
+
+#define UL1D_DEFAULT_RFC_TX_LO_B1 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0x24,\
+ /*tx_lo_in_bias_hpm */0x20,\
+ /*tx_lo_in_bias_lpm */0x20,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B2 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0x34,\
+ /*tx_lo_in_bias_hpm */0x22,\
+ /*tx_lo_in_bias_lpm */0x22,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B3 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0x51,\
+ /*tx_lo_in_bias_hpm */0x1D,\
+ /*tx_lo_in_bias_lpm */0x1D,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B4 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0x51,\
+ /*tx_lo_in_bias_hpm */0x1D,\
+ /*tx_lo_in_bias_lpm */0x1D,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B5 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0, \
+ /*tx_lo_in_bias_hpm */0, \
+ /*tx_lo_in_bias_lpm */0, \
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B6 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0, \
+ /*tx_lo_in_bias_hpm */0, \
+ /*tx_lo_in_bias_lpm */0, \
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B8 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0, \
+ /*tx_lo_in_bias_hpm */0, \
+ /*tx_lo_in_bias_lpm */0, \
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B9 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0x51,\
+ /*tx_lo_in_bias_hpm */0x1D,\
+ /*tx_lo_in_bias_lpm */0x1D,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B11 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */1, \
+ /*tx_lo_capcal_peak_cap*/0x52,\
+ /*tx_lo_in_bias_hpm */0x1B,\
+ /*tx_lo_in_bias_lpm */0x1B,\
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B18 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0, \
+ /*tx_lo_in_bias_hpm */0, \
+ /*tx_lo_in_bias_lpm */0, \
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_LO_B19 \
+ /*tx_lo: no use */0, \
+ /*tx_lo_ind */0, \
+ /*tx_lo_capcal_peak_cap*/0, \
+ /*tx_lo_in_bias_hpm */0, \
+ /*tx_lo_in_bias_lpm */0, \
+ /*stx_delta_duty_cycle */0,
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_BNone \
+ /*tx_rc_lpf*/{160,128},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B1 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B2 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B3 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B4 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B5 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B6 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B8 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B9 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B11 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B18 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_LPF_B19 \
+ /*tx_rc_lpf*/{172,138},
+
+#define UL1D_DEFAULT_RFC_TX_RC_RCF \
+ /*MT6177L E2_3wire_Table, #RCF, 16MHz*/(0xE),
+
+#define UL1D_DEFAULT_RFC_TX_CAP_BNone \
+ /*cap_tuning_pga_a*/5, \
+ /*cap_tuning_pga_b*/14,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B1 \
+ /*cap_tuning_pga_a*/0x8,\
+ /*cap_tuning_pga_b*/0xB,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B2 \
+ /*cap_tuning_pga_a*/0xC,\
+ /*cap_tuning_pga_b*/0xE,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B3 \
+ /*cap_tuning_pga_a*/0x13,\
+ /*cap_tuning_pga_b*/0x15,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B4 \
+ /*cap_tuning_pga_a*/0x13,\
+ /*cap_tuning_pga_b*/0x15,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B5 \
+ /*cap_tuning_pga_a*/0xC,\
+ /*cap_tuning_pga_b*/0xA,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B6 \
+ /*cap_tuning_pga_a*/0xC,\
+ /*cap_tuning_pga_b*/0xA,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B8 \
+ /*cap_tuning_pga_a*/0x9,\
+ /*cap_tuning_pga_b*/0x8,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B9 \
+ /*cap_tuning_pga_a*/0xF,\
+ /*cap_tuning_pga_b*/0x16,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B11 \
+ /*cap_tuning_pga_a*/0x27,\
+ /*cap_tuning_pga_b*/0x2A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B18 \
+ /*cap_tuning_pga_a*/0xF,\
+ /*cap_tuning_pga_b*/0xD,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B19 \
+ /*cap_tuning_pga_a*/0xD,\
+ /*cap_tuning_pga_b*/0xC,
+
+/* Default value from MT6177L, FXP=s6.5 */
+#define UL1D_DEFAULT_RFC_TX_DNL_PGA_A \
+{ \
+ 0, /* G0, 0dB */ \
+ -18, /* G1, -0.56dB */ \
+ -37, /* G2, -1.16dB */ \
+ -58, /* G3, -1.80dB */ \
+ -80, /* G4, -2.50dB */ \
+ -104, /* G5, -3.25dB */ \
+ -131, /* G6, -4.08dB */ \
+ -160, /* G7, -5.00dB */ \
+ -193, /* G8, -6.02dB */ \
+ -230, /* G9, -7.18dB */ \
+ -273, /* G10, -8.52dB */ \
+ -323, /* G11, -10.10dB */ \
+ -385, /* G12a, -12.04dB */ \
+ -465, /* G13a, -14.54dB */ \
+ -578, /* G14a, -18.06dB */ \
+ -615, /* G15a, -19.22dB */ \
+ -658, /* G16a, -20.56dB */ \
+ -709, /* G17a, -22.14dB */ \
+ -771, /* G18a, -24.08dB */ \
+ -851, /* G19a, -26.58dB */ \
+ -963 /* G20a, -30.10dB */ \
+},
+
+/* Default value from MT6177L, FXP=s6.5 */
+#define UL1D_DEFAULT_RFC_TX_DNL_PGA_B \
+{ \
+ -385, /* G1, -12.04dB */ \
+ -465, /* G1, -14.54dB */ \
+ -578, /* G1, -18.06dB */ \
+ -615, /* G1, -19.22dB */ \
+ -658, /* G1, -20.56dB */ \
+ -709, /* G1, -22.14dB */ \
+ -771, /* G1, -24.08dB */ \
+ -851, /* G1, -26.58dB */ \
+ -963, /* G1, -30.10dB */ \
+ -1156, /* G1, -36.12dB */ \
+ -1348, /* G1, -42.12dB */ \
+ -1540, /* G1, -48.12dB */ \
+ -1732, /* G1, -54.12dB */ \
+ -1924, /* G1, -60.12dB */ \
+ -2116, /* G1, -66.12dB */ \
+ -2308, /* G1, -72.12dB */ \
+ -2500 /* G1, -78.12dB */ \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_FDIQ \
+{ /*UL1D_TX_CBW_NUM = 2*/ \
+ TX_FDIQ_5Tap_COMP_DEFAULT, \
+ TX_FDIQ_7Tap_COMP_DEFAULT, \
+}, /*tx_fdiq_lin_1*/ \
+{ /*UL1D_TX_CBW_NUM = 2*/ \
+ TX_FDIQ_5Tap_COMP_DEFAULT, \
+ TX_FDIQ_7Tap_COMP_DEFAULT, \
+}, /*tx_fdiq_lin_2*/
+
+
+#define VERNO_BNone (0),
+#define VERNO_B1 (0),
+#define VERNO_B2 (0),
+#define VERNO_B3 (0),
+#define VERNO_B4 (0),
+#define VERNO_B5 (0),
+#define VERNO_B6 (0),
+#define VERNO_B8 (0),
+#define VERNO_B9 (0),
+#define VERNO_B11 (0),
+#define VERNO_B18 (0),
+#define VERNO_B19 (0),
+
+
+#define M_UL1D_DEFAULT_RFC_B(BAND_ID) \
+{ \
+ VERNO_B##BAND_ID \
+ UMTSBand##BAND_ID, \
+ { \
+ UL1D_DEFAULT_RFC_RX_IRR_HPM \
+ UL1D_DEFAULT_RFC_RX_IRR_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+ UL1D_DEFAULT_RFC_RX_IIP2 \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_DET_CDCOC \
+ UL1D_DEFAULT_RFC_DET_CDCOC \
+ UL1D_DEFAULT_RFC_DET_IQ_FWD \
+ UL1D_DEFAULT_RFC_DET_DC_FWD \
+ UL1D_DEFAULT_RFC_DET_DNL_FWD \
+ UL1D_DEFAULT_RFC_DET_IQ_REV \
+ UL1D_DEFAULT_RFC_DET_DC_REV \
+ UL1D_DEFAULT_RFC_DET_DNL_REV \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_TX_LO_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_RC_LPF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_RC_RCF \
+ UL1D_DEFAULT_RFC_TX_IQ_DC \
+ UL1D_DEFAULT_RFC_TX_DNL_PGA_A \
+ UL1D_DEFAULT_RFC_TX_DNL_PGA_B \
+ UL1D_DEFAULT_RFC_TX_FDIQ \
+ UL1D_DEFAULT_RFC_TX_GA \
+ UL1D_DEFAULT_RFC_TX_PGA_PHASE \
+ UL1D_DEFAULT_RFC_TX_PGA_AB \
+ UL1D_DEFAULT_RFC_TX_CAP_B##BAND_ID \
+ } \
+}
+
+#if UMTS_POC_RECAL_ENABLE
+/******************************
+* POC Recal Part
+*******************************/
+typedef struct
+{
+ kal_int8 gain_est_hw;
+ kal_int8 phase_est_hw;
+ kal_int16 freq_dep_filt[MMRFC_FILT_TAPS_NUM];
+} UMTS_RX_IRR_RESULT_DBG_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RX_DC_RESULT_DBG_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[MMRFC_RXDC_TIA_GAIN_STEPS][MMRFC_RXDC_PGA_GAIN_WCDMA_STEPS];
+} UMTS_RX_DC_HPM_RESULT_DBG_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[MMRFC_RXDC_TIA_GAIN_LPM_STEPS][MMRFC_RXDC_PGA_GAIN_LPM_STEPS];
+} UMTS_RX_DC_LPM_RESULT_DBG_T;
+
+typedef struct{
+ kal_int8 gain_est;
+ kal_int8 phase_est;
+} UMTS_TX_IQ_RESULT_DBG_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_TX_DC_RESULT_DBG_T;
+
+
+typedef struct
+{
+ /* RX IRR */
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_hpm_recal[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_lpm_recal[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dc_hpm_recal[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dc_lpm_recal[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+
+ /* DET Coarse DCOC */
+ kal_uint32 det_coarse_dcoc_cw807;
+ kal_uint32 det_coarse_dcoc_cw808;
+
+ /* DET IQ/DC/DNL Forward */
+ UMTS_RF_POC_DET_IQ_COMP_T det_iq_fwd[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_fwd[UL1D_DET_GAIN_STEPS];
+ kal_int16 det_dnl_fwd[UL1D_DET_GAIN_STEPS];
+
+ /* TX */
+ UMTS_TX_IQ_RESULT_DBG_T tx_iq_lin[UL1D_TX_PGA_SLICE_NUM+1];
+ UMTS_TX_DC_RESULT_DBG_T tx_dc_lin[UL1D_TX_PGA_SLICE_NUM+1];
+
+ UMTS_TX_IQ_RESULT_DBG_T tx_iq_dpd[UL1D_TX_PGA_SLICE_NUM+1];
+ UMTS_TX_DC_RESULT_DBG_T tx_dc_dpd[UL1D_TX_PGA_SLICE_NUM+1];
+}UMTS_RF_POC_RECAL_DATA_T;
+
+#endif/*UMTS_POC_RECAL_ENABLE*/
+
+
+#endif /*__UL1D_RFC_DATA_MT6177_H__*/
+
+/* Doxygen Group End ***************************************************//**@}*/
diff --git a/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6185m.h b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6185m.h
new file mode 100644
index 0000000..450af0a
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6185m.h
@@ -0,0 +1,1791 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygen Group Header ****************************************************//**
+ * @addtogroup UL1D_RF_CUSTOM_DATA
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @file ul1d_rf_cal_poc_data.h
+ * @author Neil Chung(MTK08266)
+ * @date 2015.01.26
+ * @brief UL1D RF POC SHM data header file
+ * @details Provide RF POC data structure for PCORE and L1CORE (SHM)
+ ******************************************************************************/
+
+#ifndef __UL1D_RFC_DATA_MT6185M_H__
+#define __UL1D_RFC_DATA_MT6185M_H__
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "mml1_rf_cal_def.h"
+
+/*******************************************************************************
+ * Typedef
+ ******************************************************************************/
+/** Structure Prototypes can be seen by other files */
+typedef enum
+{
+ UMTSBandNone = 0,
+ UMTSBand1 = 1,
+ UMTSBand2 = 2,
+ UMTSBand3 = 3,
+ UMTSBand4 = 4,
+ UMTSBand5 = 5,
+ UMTSBand6 = 6,
+ UMTSBand7 = 7,
+ UMTSBand8 = 8,
+ UMTSBand9 = 9,
+ UMTSBand10 = 10,
+ UMTSBand11 = 11,
+ UMTSBand12 = 12,
+ UMTSBand13 = 13,
+ UMTSBand14 = 14,
+ UMTSBand15 = 15,
+ UMTSBand16 = 16,
+ UMTSBand17 = 17,
+ UMTSBand18 = 18,
+ UMTSBand19 = 19,
+ UMTSBand20 = 20,
+ UMTSBand21 = 21,
+ UMTSBand22 = 22,
+ UMTSBandcount
+} UMTSBand;
+
+
+/*******************************************************************************
+** RFC dimension define
+*******************************************************************************/
+
+#define UL1D_RXDC_TIA_GAIN_STEPS (4)
+#define UL1D_RXDC_PGA_GAIN_STEPS (7)
+
+#define UL1D_RXDC_HPM_TIA_GAIN_STEPS (UL1D_RXDC_TIA_GAIN_STEPS)
+#define UL1D_RXDC_HPM_PGA_GAIN_STEPS (UL1D_RXDC_PGA_GAIN_STEPS)
+#define UL1D_RXDC_LPM_TIA_GAIN_STEPS (UL1D_RXDC_TIA_GAIN_STEPS)
+#define UL1D_RXDC_LPM_PGA_GAIN_STEPS (UL1D_RXDC_PGA_GAIN_STEPS)
+
+#define UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX (7) /* from MMRFC_RXIRR_FILT_TAPS_NUM */
+#define UL1D_RF_RX_DC_COMP_ROUTE_MAX (1)
+#define UL1D_RF_RX_IRR_COMP_ROUTE_MAX (1)
+#define UL1D_RF_RX_IIP2_COMP_ROUTE_MAX (1)
+
+#define UL1D_RX_CBW_NUM (3 ) /* from MMRFC_UMTS_RX_CBW_NUM */
+#define UL1D_DET_FE_GAIN_STEPS (1 ) /* from MMRFC_DET_FE_GAIN_STEPS */
+#define UL1D_DET_GAIN_STEPS (5 ) /* from MMRFC_DET_GAIN_STEPS */
+#define UL1D_DET_EQLPF_TAP_NUM (13) /* from MMRFC_DET_EQLPF_TAP_NUM */
+#define UL1D_TX_PGA_TYPE_NUM (3 ) /* from MMRFC_TX_PGA_TYPE_NUM */
+#define UL1D_TX_DNL_PGA_A_GAIN_STEPS (22) /* from MMRFC_TX_DNL_PGA_A_GAIN_STEPS */
+#define UL1D_TX_DNL_PGA_B_GAIN_STEPS (0 ) /* from MMRFC_TX_DNL_PGA_B_GAIN_STEPS */
+#define UL1D_TX_DNL_PGA_AUX_GAIN_STEPS (5 ) /* from MMRFC_TX_DNL_PGA_AUX_GAIN_STEPS */
+#define UL1D_TX_PGA_SLICE_NUM (4 ) /* from MMRFC_TX_PGA_SLICE_NUM */
+#define UL1D_TX_PGA_BIAS_NUM (3 ) /* from MMRFC_TX_PGA_BIAS_STEP_NUM */
+#define UL1D_TX_CBW_NUM (2 ) /* from MMRFC_UMTS_TX_CBW_NUM */
+#define UL1D_TX_PGA_GAIN_STEP_NUM (10) /* from MMRFC_TX_PGA_GAIN_STEP_NUM */
+#define UL1D_TX_SUBBAND_NUM (3 ) /* from MMRFC_TX_SUBBAND_NUM */
+#define UL1D_ANT_NUM (2 ) /* from MMRFC_ANT_NUM */
+
+#define UL1D_TX_PGA_CAP_TUNING_SUBBAND_NUM (UL1D_TX_SUBBAND_NUM)/* from MMRFC_TX_PGA_CAP_TUNING_SUBBAND_NUM */
+#define UL1D_TX_DNL_PGA_TOTAL_NUM (UL1D_TX_DNL_PGA_A_GAIN_STEPS + UL1D_TX_DNL_PGA_B_GAIN_STEPS + UL1D_TX_DNL_PGA_AUX_GAIN_STEPS)
+
+
+/******************************
+* Rx POC Part
+*******************************/
+typedef struct
+{
+ kal_int8 gain_est_hw;
+ kal_int8 phase_est_hw;
+ kal_int16 freq_dep_filt[UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX];
+} UMTS_RF_POC_RX_IRR_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_RX_DC_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_HPM_TIA_GAIN_STEPS][UL1D_RXDC_HPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_HPM_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_LPM_TIA_GAIN_STEPS][UL1D_RXDC_LPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_LPM_COMP_T;
+
+typedef struct
+{
+ kal_int8 gate_bias_i;
+ kal_int8 gate_bias_q;
+} UMTS_RF_POC_RX_IIP2_COMP_T;
+
+typedef struct
+{
+ /* RX IRR */
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_hpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_lpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+
+ /* RX DC */
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_rf_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_rf_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dig_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dig_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+
+ /* RX IIP2 */
+ UMTS_RF_POC_RX_IIP2_COMP_T rx_iip2[UL1D_ANT_NUM][UL1D_RF_RX_IIP2_COMP_ROUTE_MAX];
+
+} UMTS_RF_POC_RX_COMP_DATA_T;
+
+
+/******************************
+* Tx DET POC Part
+*******************************/
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+
+} UMTS_DET_EQLPF_COMP_T;
+
+typedef struct
+{
+ UMTS_DET_EQLPF_COMP_T coef[UL1D_DET_EQLPF_TAP_NUM];
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+} UMTS_DET_FDADPCB_EQLPF_COMP_T;
+
+typedef struct{
+ kal_int8 tx_mod_slice_phase_aux; //For TrinityL E2
+ kal_int8 phase_est_hw; //FIIQ phase
+ UMTS_DET_FDADPCB_EQLPF_COMP_T fd_ad_pcb; //FDIQ, AD coefficient, 3G do not contain PCB information
+} UMTS_RF_POC_DET_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_DET_DC_COMP_T;
+
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoc_i;
+ kal_uint32 mrx_cdcoc_q;
+}
+UMTS_RF_POC_MRX_CDCOC_PGA_T;
+
+typedef struct
+{
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_pos_15_db;
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_pos_09_db;
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_pos_03_db;
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_neg_03_db;
+}
+UMTS_RF_POC_MRX_COARSE_DC_T;
+
+
+
+typedef struct
+{
+ /* DET Coarse DCOC */
+ /*
+ Trinity TX Calibrations V1.1 Draft.docx
+ 5.1 MRX Coarse DC-offset Calibration (ES2 Approach)
+
+ We need to calibrate PGA = 15dB, PGA = 9dB, PGA = 3dB, and -3dB.
+ We need to calibrate the TX-loopback and the antenna-loopback separately.
+ DPD also uses PGA gain -9dB, but that PGA gain can reuse the -3dB calibration.
+
+ det_cdcoc[0]: PGA = 15dB --> CW939 : TX1_MRX_CDCOC_I/Q1[4:0]
+ det_cdcoc[0]: PGA = 15dB --> CW1006: TX0_MRX_CDCOC_I/Q1[4:0]
+
+ det_cdcoc[1]: PGA = 9dB --> CW939 : TX1_MRX_CDCOC_I/Q2[4:0]
+ det_cdcoc[1]: PGA = 9dB --> CW1006: TX0_MRX_CDCOC_I/Q2[4:0]
+
+ det_cdcoc[2]: PGA = 3dB --> CW940 : TX1_MRX_CDCOC_I/Q3[4:0]
+ det_cdcoc[2]: PGA = 3dB --> CW1007: TX0_MRX_CDCOC_I/Q3[4:0]
+
+ det_cdcoc[3]: PGA = -3dB --> CW940 : TX1_MRX_CDCOC_I/Q4[4:0]
+ det_cdcoc[3]: PGA = -3dB --> CW1007: TX0_MRX_CDCOC_I/Q4[4:0]
+ */
+ UMTS_RF_POC_MRX_COARSE_DC_T det_cdcoc;
+
+ /* DET IQ/DC/DNL Forward */
+ UMTS_RF_POC_DET_IQ_COMP_T det_iq_fwd[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_fwd[UL1D_DET_GAIN_STEPS];
+ kal_int16 det_dnl_fwd[UL1D_DET_GAIN_STEPS];
+
+ kal_int16 mrx_ctune_pga[2/*MMRFC_MRX_PGA_TZA_BW_CNT*/];
+ kal_int16 mrx_ctune_tza[2/*MMRFC_MRX_PGA_TZA_BW_CNT*/];
+
+} UMTS_RF_POC_DET_COMP_DATA_T;
+
+/******************************
+* Tx FOWRAD POC Part
+*******************************/
+typedef struct{
+ kal_int8 gain_est;
+ kal_int8 phase_est;
+} UMTS_RF_POC_TX_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_TX_DC_COMP_T;
+
+typedef struct
+{
+
+ /* TX LPF*/
+ kal_int16 tx_lpf_abb_rsel;
+ kal_int16 tx_lpf_abb_csel_1;
+ kal_int16 tx_lpf_abb_csel_2;
+
+ /* TX RCF*/
+ kal_int16 tx_rcf_rsel;
+ kal_int16 tx_rcf_csel_4a;
+ kal_int16 tx_rcf_csel_1b;
+ kal_int16 tx_rcf_csel_2a;
+
+ /* TX CDCOC */
+ /*
+ Trinity TX Calibrations Table V1.1 Draft.xlsx
+ 1) Coarse DC offset compensator located in DAC IP (modem). Compensation changes with # of slices (gain word).
+ 2) Requires recalibration per RAT because of changes in R used in ABB. RAT's using same R can reuse calibration
+ 3) Requires L1 and CSD support
+
+ per ABB slice CM: 4A, 2A, 1A, 1B
+ */
+ UMTS_RF_POC_TX_DC_COMP_T tx_cdcoc[UL1D_TX_PGA_SLICE_NUM];
+
+ /* TX FIIQ/DC/DNL Linear Mode */
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_lin[UL1D_TX_PGA_SLICE_NUM];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_lin[UL1D_TX_PGA_SLICE_NUM];
+
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_dpd[UL1D_TX_PGA_SLICE_NUM];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_dpd[UL1D_TX_PGA_SLICE_NUM];
+
+ kal_int16 tx_dnl_lin_pga_a[UL1D_TX_DNL_PGA_TOTAL_NUM];
+
+ /* TX PGA Phase Step */
+ kal_int32 tx_mod_slice_phase[UL1D_TX_PGA_SLICE_NUM-1/*Slice: 0:4A, 1:2A, 2:1A*/];
+
+ /* TX PGA Cap Tuning */
+ kal_uint32 cap_opt_a;
+ kal_uint32 tx_drv_ctunemod;
+
+ /* TX PGA BIAS: 4 calibrated BMA_CAL<7:0> codes */
+ /* 3 BMA values used for different number of PGA slices (4/2/1)*/
+ /* 1 additional BMA value used in DPD mode. The latter is never used in practice*/
+ /* A60864_TX_Programming_Guide_v1p0.docx
+ 4.3.1 PGA Bias Calibration programming
+
+ CW888: TX1_PGABIAS_BMA1_DEF[7:0]-->PGABIAS BMA4 gain lookup default-->DPD
+ CW888: TX1_PGABIAS_BMA2_DEF[7:0]-->PGABIAS BMA3 gain lookup default-->1 Slice
+ CW887: TX1_PGABIAS_BMA3_DEF[7:0]-->PGABIAS BMA2 gain lookup default-->2 Slices
+ CW887: TX1_PGABIAS_BMA4_DEF[7:0]-->PGABIAS BMA1 gain lookup default-->4 Slices
+
+ CW955: TX0_PGABIAS_BMA1_DEF[7:0]-->PGABIAS BMA4 gain lookup default-->DPD
+ CW955: TX0_PGABIAS_BMA2_DEF[7:0]-->PGABIAS BMA3 gain lookup default-->1 Slice
+ CW954: TX0_PGABIAS_BMA3_DEF[7:0]-->PGABIAS BMA2 gain lookup default-->2 Slices
+ CW954: TX0_PGABIAS_BMA4_DEF[7:0]-->PGABIAS BMA2 gain lookup default-->4 Slices
+ */
+ kal_int32 tx_pga_bias[UL1D_TX_PGA_BIAS_NUM/* Slice: 0:4A, 1:2A, 2:1A */];
+
+} UMTS_RF_POC_TX_COMP_DATA_T;
+
+typedef struct
+{
+ kal_uint32 verno;
+ UMTSBand band;
+ UMTS_RF_POC_RX_COMP_DATA_T umts_rx_comp;
+ UMTS_RF_POC_DET_COMP_DATA_T umts_det_comp;
+ UMTS_RF_POC_TX_COMP_DATA_T umts_tx_comp;
+} UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T;
+
+
+/*******************************************************************************
+** Macro define for POC default value
+*******************************************************************************/
+
+
+/*Trinity_RX_Programming_Guide_0p1_20170607 */
+/*Table 4-3 DCOC Mapping Table */
+/*Offset Voltage(V) = 0V, DCOC[5:0] = 6'b100000 */
+
+#define UMTS_RXDC_RF_I_Default (0xFFE0)
+#define UMTS_RXDC_RF_Q_Default (0xFFE0)
+#define UMTS_RXDC_Dig_I_Default (0)
+#define UMTS_RXDC_Dig_Q_Default (0)
+
+#define UMTS_RXDC_RF_IQ_Default \
+{\
+ UMTS_RXDC_RF_I_Default, UMTS_RXDC_RF_Q_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_Default \
+{\
+ UMTS_RXDC_Dig_I_Default,\
+ UMTS_RXDC_Dig_Q_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default,\
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default \
+{\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default \
+{\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+}
+
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default \
+{\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default \
+{\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+}
+
+
+
+#define UMTS_RXDC_RF_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_RF_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+#define UMTS_RX_IRR_TAP_DEFAULT \
+{ \
+ /*ANT0*/{0,0,{0,0,0,1024,0,0,0}}, \
+ /*ANT1*/{0,0,{0,0,0,1024,0,0,0}}, \
+}
+
+#define UMTS_RX_IIP2_I_DEFAULT (64)
+#define UMTS_RX_IIP2_Q_DEFAULT (64)
+#define UMTS_RX_IIP2_DEFAULT {UMTS_RX_IIP2_I_DEFAULT, UMTS_RX_IIP2_Q_DEFAULT}
+
+/*
+Manel:
+Please note that the table shows the phase change introduced by RF.
+The DFE compensation must have the opposite sign than what is shown on the table.
+*/
+
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_4_to_2 (-14 ) // 2.5*1024/180
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_2_to_1 (-4 ) // 0.7*1024/180
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_4_to_1 (-18 ) // 3.2*1024/180
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_1_to_AUX (0 ) // 0*1024/180
+
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_4_to_2 (-40 ) // 7*1024/180
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_2_to_1 (-57 ) // 10*1024/180
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_4_to_1 (-97 ) // 17*1024/180
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_1_to_AUX (0 ) // 0*1024/180
+
+#define UMTS_TX_PHASE_LB_4A_DEFAULT (0)
+#define UMTS_TX_PHASE_LB_2A_DEFAULT (UMTS_TX_PHASE_LB_4A_DEFAULT+UMTS_TX_LB_PHASE_SLICE_CHANGE_4_to_2)
+#define UMTS_TX_PHASE_LB_1A_DEFAULT (UMTS_TX_PHASE_LB_2A_DEFAULT+UMTS_TX_LB_PHASE_SLICE_CHANGE_2_to_1)
+#define UMTS_TX_PHASE_LB_AUX_DEFAULT (UMTS_TX_PHASE_LB_1A_DEFAULT+UMTS_TX_LB_PHASE_SLICE_CHANGE_1_to_AUX)
+
+
+#define UMTS_TX_PHASE_MB_4A_DEFAULT (0)
+#define UMTS_TX_PHASE_MB_2A_DEFAULT (UMTS_TX_PHASE_MB_4A_DEFAULT+UMTS_TX_MB_PHASE_SLICE_CHANGE_4_to_2)
+#define UMTS_TX_PHASE_MB_1A_DEFAULT (UMTS_TX_PHASE_MB_2A_DEFAULT+UMTS_TX_MB_PHASE_SLICE_CHANGE_2_to_1)
+#define UMTS_TX_PHASE_MB_AUX_DEFAULT (UMTS_TX_PHASE_MB_1A_DEFAULT+UMTS_TX_MB_PHASE_SLICE_CHANGE_1_to_AUX)
+
+
+#define UMTS_TX_PHASE_AUX_BNone \
+( \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+)
+
+#define UMTS_TX_PHASE_AUX_B1 \
+( \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+)
+
+#define UMTS_TX_PHASE_AUX_B2 \
+( \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+)
+
+#define UMTS_TX_PHASE_AUX_B3 \
+( \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+)
+
+#define UMTS_TX_PHASE_AUX_B4 \
+( \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+)
+
+#define UMTS_TX_PHASE_AUX_B5 \
+( \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+)
+
+#define UMTS_TX_PHASE_AUX_B6 \
+( \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+)
+
+#define UMTS_TX_PHASE_AUX_B8 \
+( \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+)
+
+#define UMTS_TX_PHASE_AUX_B9 \
+( \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+)
+
+#define UMTS_TX_PHASE_AUX_B11 \
+( \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+)
+
+#define UMTS_TX_PHASE_AUX_B18 \
+( \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+)
+
+#define UMTS_TX_PHASE_AUX_B19 \
+( \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+)
+
+/*95_TxDFERF_TxK_default_settings_20171027.xlsx*/
+#define UMTS_DET_IQ_PHASE_EST_HW_DEFAULT (0)/*phase_est_hw: DET_FI (S-4.10.9) POC*/
+
+#define UMTS_DET_IQ_EQLPF_I_SCALE_DEFAULT (1)/*scale_i: DET_EQLPF_I_SCALE (U2.0)*/
+
+#define UMTS_DET_IQ_EQLPF_Q_SCALE_DEFAULT (1)/*scale_q: DET_EQLPF_Q_SCALE (U2.0)*/
+
+#define UMTS_DET_IQ_EQ_COEF_DEFAULT \
+ { \
+ { 4, 4},/*coef[00]: DET_EQLPF_I_C00, DET_EQLPF_Q_C00*/ \
+ { -22, -22},/*coef[01]: DET_EQLPF_I_C01, DET_EQLPF_Q_C01*/ \
+ { 74, 74},/*coef[02]: DET_EQLPF_I_C02, DET_EQLPF_Q_C02*/ \
+ { -186, -186},/*coef[03]: DET_EQLPF_I_C03, DET_EQLPF_Q_C03*/ \
+ { 417, 417},/*coef[04]: DET_EQLPF_I_C04, DET_EQLPF_Q_C04*/ \
+ {-1021,-1021},/*coef[05]: DET_EQLPF_I_C05, DET_EQLPF_Q_C05*/ \
+ { 3513, 3513},/*coef[06]: DET_EQLPF_I_C06, DET_EQLPF_Q_C06*/ \
+ {-1010,-1010},/*coef[07]: DET_EQLPF_I_C07, DET_EQLPF_Q_C07*/ \
+ { 401, 401},/*coef[08]: DET_EQLPF_I_C08, DET_EQLPF_Q_C08*/ \
+ { -171, -171},/*coef[09]: DET_EQLPF_I_C09, DET_EQLPF_Q_C09*/ \
+ { 65, 65},/*coef[10]: DET_EQLPF_I_C10, DET_EQLPF_Q_C10*/ \
+ { -18, -18},/*coef[11]: DET_EQLPF_I_C11, DET_EQLPF_Q_C11*/ \
+ { 3, 3} /*coef[12]: DET_EQLPF_I_C12, DET_EQLPF_Q_C12*/ \
+}
+
+
+/*95_TxDFERF_TxK_default_settings_20171027.xlsx*/
+#define UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+ UMTS_DET_IQ_PHASE_EST_HW_DEFAULT, \
+ { /* fd_ad_pcb: */ \
+ UMTS_DET_IQ_EQ_COEF_DEFAULT, \
+ UMTS_DET_IQ_EQLPF_I_SCALE_DEFAULT, \
+ UMTS_DET_IQ_EQLPF_Q_SCALE_DEFAULT \
+ }
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_BNone \
+{ \
+ UMTS_TX_PHASE_AUX_BNone, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B1 \
+{ \
+ UMTS_TX_PHASE_AUX_B1, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B2 \
+{ \
+ UMTS_TX_PHASE_AUX_B2, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B3 \
+{ \
+ UMTS_TX_PHASE_AUX_B3, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B4 \
+{ \
+ UMTS_TX_PHASE_AUX_B4, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B5 \
+{ \
+ UMTS_TX_PHASE_AUX_B5, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B6 \
+{ \
+ UMTS_TX_PHASE_AUX_B6, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B8 \
+{ \
+ UMTS_TX_PHASE_AUX_B8, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B9 \
+{ \
+ UMTS_TX_PHASE_AUX_B9, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B11 \
+{ \
+ UMTS_TX_PHASE_AUX_B11, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B18 \
+{ \
+ UMTS_TX_PHASE_AUX_B18, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B19 \
+{ \
+ UMTS_TX_PHASE_AUX_B19, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_DET_IQ_MG_DFAULT_BNone \
+ { /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_BNone,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_BNone,\
+ },
+
+#define UMTS_DET_IQ_MG_DFAULT_B1 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B1,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B1,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B2 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B2,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B2,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B3 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B3,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B3,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B4 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B4,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B4,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B5 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B5,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B5,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B6 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B6,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B6,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B8 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B8,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B8,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B9 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B9,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B9,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B11 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B11,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B11,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B18 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B18,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B18,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B19 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B19,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B19,\
+},
+
+
+#define UMTS_DET_DC_DEFAULT {0/*DC_I*/, 0/*DC_Q*/}
+
+
+// RX
+//============================================================
+#define UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+{ \
+ UMTS_RXDC_RF_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+{ \
+ UMTS_RXDC_RF_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+{ \
+ UMTS_RXDC_Dig_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+{ \
+ UMTS_RXDC_Dig_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_IRR_HPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 1, HPM*/ \
+ { \
+ /*SC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*DC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*3C*/UMTS_RX_IRR_TAP_DEFAULT \
+ }, \
+},
+
+#define UL1D_DEFAULT_RFC_RX_IRR_LPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 1, LPM*/ \
+ { \
+ /*SC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*DC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*3C*/UMTS_RX_IRR_TAP_DEFAULT \
+ }, \
+},
+
+
+#define UL1D_DEFAULT_RFC_RX_IIP2 \
+{ \
+ { /*RXP*/ \
+ UMTS_RX_IIP2_DEFAULT,/*ROUTE00*/ \
+ }, \
+ { /*RXD*/ \
+ UMTS_RX_IIP2_DEFAULT,/*ROUTE00*/ \
+ } \
+},
+
+
+//DET
+//============================================================
+
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_BNone \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_BNone \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B1 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B1 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B2 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B2 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B3 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B3 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B4 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B4 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B5 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B5 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B6 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B6 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B8 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B8 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B9 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B9 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B11 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B11 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B18 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B18 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B19 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B19 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_DC \
+ { /* UL1D_DET_GAIN_STEPS = 5*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG00*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG01*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG02*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG03*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG04*/ \
+ },
+
+/* A60864A_BBBM_TABLE_MERGED.xlsx */
+/* sheet: MRX0_GAIN & MRX1_GAIN */
+/* MRX Gain*/
+#define UL1D_DEFAULT_RFC_MRX_DNL \
+{ \
+ 192, /* G0: 6 dB*/ \
+ 0 , /* G1: 0 dB*/ \
+ -192, /* G2: -6dB*/ \
+ -384, /* G3: -12 dB*/ \
+ -576, /* G4: -18dB*/ \
+},
+
+
+#define UL1D_DEFAULT_RFC_MRX_CDCOC_PGA \
+{ \
+ /* mrx_cdcoc_i */0, \
+ /* mrx_cdcoc_q */0 \
+}
+
+
+#define UL1D_DEFAULT_RFC_MRX_CDCOC \
+{ \
+ /* pga_pos_15_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA, \
+ /* pga_pos_09_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA, \
+ /* pga_pos_03_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA, \
+ /* pga_neg_03_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA \
+},
+
+
+
+/*
+ A60827_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+ CW718[D07:D00] RG_TX1_MRX_PGA_CTUNE[7:0] = 0x3C
+ CW718[D15:D08] RG_TX1_MRX_TZA_CTUNE[7:0] = 0x18
+ CW738[D07:D00] RG_TX0_MRX_PGA_CTUNE[7:0] = 0x3C
+ CW738[D15:D08] RG_TX0_MRX_TZA_CTUNE[7:0] = 0x18
+*/
+
+#define UL1D_DEFAULT_RFC_MRX_CTUNE_PGA \
+{ \
+ /* MMRFC_MRX_PGA_TZA_BW_22P5 */0x3C,\
+ /* MMRFC_MRX_PGA_TZA_BW_67P5 */0x3C \
+},
+
+#define UL1D_DEFAULT_RFC_MRX_CTUNE_TZA \
+{ \
+ /* MMRFC_MRX_PGA_TZA_BW_22P5 */0x18,\
+ /* MMRFC_MRX_PGA_TZA_BW_67P5 */0x18 \
+},
+
+
+//TX
+//============================================================
+
+
+/*DOC : Trinity-L TX Gain Table V1.1 Draft.xlsx */
+/*Sheet: Gain Tables */
+/*Table: LB & MB & HB_UHB */
+
+#define UL1D_DEFAULT_RFC_TX_DNL_PGA \
+{ \
+ 0 , /* G0 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = 0.00 dB */ \
+ -18 , /* G1 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -0.56 dB */ \
+ -37 , /* G2 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -1.16 dB */ \
+ -58 , /* G3 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -1.80 dB */ \
+ -80 , /* G4 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -2.50 dB */ \
+ -104 , /* G5 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -3.25 dB */ \
+ -131 , /* G6 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -4.08 dB */ \
+ -160 , /* G7 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -4.99 dB */ \
+ -193 , /* G8 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -6.02 dB */ \
+ -230 , /* G9 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -7.18 dB */ \
+ -273 , /* G10, A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -8.52 dB */ \
+ -323 , /* G11, A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -10.10dB */ \
+ -366 , /* G12, A , ABB MOD LO Slice = 2, PGA Slice = 4, Gain = -11.43dB */ \
+ -468 , /* G13, A , ABB MOD LO Slice = 2, PGA Slice = 2, Gain = -14.62dB */ \
+ -526 , /* G14, A , ABB MOD LO Slice = 1, PGA Slice = 4, Gain = -16.45dB */ \
+ -621 , /* G15, A , ABB MOD LO Slice = 1, PGA Slice = 2, Gain = -19.40dB */ \
+ -734 , /* G16, A , ABB MOD LO Slice = 1, PGA Slice = 2, Gain = -22.93dB */ \
+ -853 , /* G17, A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -26.67dB */ \
+ -988 , /* G18, A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -30.89dB */ \
+ -1181, /* G19, A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -36.91dB */ \
+ -1374, /* G20, A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -42.93dB */ \
+ -1566, /* G21, A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -48.95dB */ \
+ -1759, /* G22, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -54.97dB */ \
+ -1952, /* G23, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -60.99dB */ \
+ -2144, /* G24, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -67.01dB */ \
+ -2337, /* G25, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -73.03dB */ \
+ -2530 /* G26, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -79.05dB */ \
+},
+
+
+/*DOC : Trinity-L TX Gain Table V1.1 Draft.xlsx */
+/*Sheet: Gain Tables */
+/*Table: LB & MB & HB_UHB */
+
+#define UL1D_DEFAULT_RFC_TX_DNL_PGA_E2 \
+{ \
+ 0 , /* G0 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = 0.00 dB */ \
+ -18 , /* G1 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -0.56 dB */ \
+ -37 , /* G2 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -1.16 dB */ \
+ -58 , /* G3 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -1.80 dB */ \
+ -80 , /* G4 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -2.50 dB */ \
+ -104 , /* G5 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -3.25 dB */ \
+ -131 , /* G6 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -4.08 dB */ \
+ -160 , /* G7 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -4.99 dB */ \
+ -193 , /* G8 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -6.02 dB */ \
+ -230 , /* G9 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -7.18 dB */ \
+ -273 , /* G10, A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -8.52 dB */ \
+ -323 , /* G11, A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -10.10dB */ \
+ -366 , /* G12, A , ABB MOD LO Slice = 2, PGA Slice = 4, Gain = -11.43dB */ \
+ -468 , /* G13, A , ABB MOD LO Slice = 2, PGA Slice = 2, Gain = -14.62dB */ \
+ -526 , /* G14, A , ABB MOD LO Slice = 1, PGA Slice = 4, Gain = -16.45dB */ \
+ -621 , /* G15, A , ABB MOD LO Slice = 1, PGA Slice = 2, Gain = -19.40dB */ \
+ -734 , /* G16, A , ABB MOD LO Slice = 1, PGA Slice = 2, Gain = -22.93dB */ \
+ -853 , /* G17, A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -26.67dB */ \
+ -988 , /* G18, A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -30.89dB */ \
+ -1181, /* G19, A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -36.91dB */ \
+ -1374, /* G20, A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -42.93dB */ \
+ -1566, /* G21, A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -48.95dB */ \
+ -1759, /* G22, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -54.97dB */ \
+ -1952, /* G23, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -60.99dB */ \
+ -2144, /* G24, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -67.01dB */ \
+ -2337, /* G25, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -73.03dB */ \
+ -2530 /* G26, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -79.05dB */ \
+},
+
+
+
+#define UL1D_DEFAULT_RFC_TX_IQ_DC \
+ /*tx_iq_lin*/{{0,0}}, \
+ /*tx_dc_lin*/{{0,0}}, \
+ /*tx_iq_dpd*/{{0,0}}, \
+ /*tx_dc_dpd*/{{0,0}},
+
+#define UL1D_DEFAULT_RFC_TX_CDCOC \
+ { \
+ /*tx_cdcoc[0:MMRFC_TX_ABB_SLICE_CAL_4A ]*/{/*dc_i*/0,/*dc_q*/0}, \
+ /*tx_cdcoc[1:MMRFC_TX_ABB_SLICE_CAL_2A ]*/{/*dc_i*/0,/*dc_q*/0}, \
+ /*tx_cdcoc[2:MMRFC_TX_ABB_SLICE_CAL_1A ]*/{/*dc_i*/0,/*dc_q*/0}, \
+ /*tx_cdcoc[3:MMRFC_TX_ABB_SLICE_CAL_AUX]*/{/*dc_i*/0,/*dc_q*/0} \
+ },
+
+/* TX LPF*/
+/* ==============================================================================
+
+ A60864_TX_Programming_Guide_v1p0.docx,
+ - 3.7 Bandwidth control, Table 3 15 3G Filter Configurations: LPF_6P8M/CW719/CW739
+ - 3.7.1 ABB BW Controls, Table 3 18 ABB RC Controls: TX0_BBBM10 & TX1_BBBM10
+ Trinity_L_divider_table_v0d1_20170922_1012temporary_L1.xlsx
+ Sheet: 1RX_1TX
+ Band TX Path
+ 1 1
+ 2 1
+ 3 1
+ 4 1
+ 5 0
+ 6 0
+ 7 1
+ 8 0
+ 9 1
+ 10 1
+ 11 1
+ 12 0
+ 13 0
+ 14 0
+ 15 0
+ 17 0
+ 18 0
+ 19 0
+
+ A60864A_BBBM_TABLE_MERGED.xlsx
+ A60864_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+
+ CW739 TX0_BBBM10 TX0_ABB_CSEL1/2[7:0] TX0_ABB_RSEL [1:0]
+ CW719 TX1_BBBM10 TX1_ABB_CSEL1/2[7:0] TX1_ABB_RSEL [1:0] --> 2 bits
+ CW890 TX1_ABBMAN1 TX1_ABB_CSEL1_M[7:0] -------------------
+ TX1_ABB_CSEL2_M[7:0] -------------------
+ CW957 TX2_ABBMAN1 TX2_ABB_CSEL1_M[7:0] -------------------
+ TX2_ABB_CSEL2_M[7:0] -------------------
+ CW891 TX1_ABBMAN2 -------------------- TX1_ABB_RSEL_M[3:0] --> 4 bits ?
+ CW958 TX2_ABBMAN2 -------------------- TX2_ABB_RSEL_M[3:0]
+
+ |Band | Path | Mode | TX0/1_ABB_CSEL1[7:0]| TX0/1_ABB_CSEL2[7:0]| TX0/1_ABB_RSEL[1:0]|
+ |-------------|---------|----------|---------------------|---------------------|--------------------|
+ |3G_FDD_Band01| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band02| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band03| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band04| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band05| 0 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band06| 0 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band08| 0 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band09| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band11| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band18| 0 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band19| 0 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+
+ =============================================================================*/
+
+#define UL1D_DEFAULT_RFC_TX_LPF_BNone \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2,\
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B1 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B2 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B3 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B4 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B5 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B6 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B8 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B9 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B11 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B18 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B19 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+
+
+
+/* TX RCF*/
+/*
+ A60864A_BBBM_TABLE_MERGED.xlsx
+ A60864_TX_Programming_Guide_v1p0.docx,
+ - 3.7.2 RCF BW Controls
+ CW729 TX0_BBBM5 RCEL [15:8] CSEL_4[7:0]
+ CW730 TX0_BBBM6 CSEL1[15:8] CSEL_2[7:0]
+
+ CW709 TX1_BBBM5 RCEL [15:8] CSEL_4[7:0]
+ CW710 TX1_BBBM6 CSEL1[15:8] CSEL_2[7:0]
+
+ Trinity_L_divider_table_v0d1_20170922_1012temporary_L1.xlsx
+ Sheet: 1RX_1TX
+ Band TX Path
+ 1 1
+ 2 1
+ 3 1
+ 4 1
+ 5 0
+ 6 0
+ 7 1
+ 8 0
+ 9 1
+ 10 1
+ 11 1
+ 12 0
+ 13 0
+ 14 0
+ 15 0
+ 17 0
+ 18 0
+ 19 0
+
+ A60864_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+
+ CW729[15:8] CW729[7:0] CW730[15:8] CW730[7:0]
+ |Band | Path | Mode:TX0 | RG_TX0_RCF_RSEL[7:0]|TX0_RCF_CSEL_4[7:0]| TX0_RCF_CSEL_1[7:0] | TX0_RCF_CSEL_2[7:0]|
+ |--------------|-------|-----------------|---------------------|------------------ |----------------------|---------------------|
+ |3G_FDD_Band01 | 1 | RCF_MB1_16M | 0x2A | 0x1D | 0x27 | 0x21 |
+ |3G_FDD_Band02 | 1 | RCF_MB2_16M | 0x2F | 0x20 | 0x28 | 0x22 |
+ |3G_FDD_Band03 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x29 | 0x23 |
+ |3G_FDD_Band04 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x22 | 0x22 |
+ |3G_FDD_Band05 | 0 | RCF_MB2_16M | 0x21 | 0x20 | 0x28 | 0x22 |
+ |3G_FDD_Band06 | 0 | RCF_MB2_16M | 0x21 | 0x20 | 0x28 | 0x22 |
+ |3G_FDD_Band08 | 0 | RCF_MB1_16M | 0x1C | 0x1D | 0x27 | 0x21 |
+ |3G_FDD_Band09 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x29 | 0x23 |
+ |3G_FDD_Band11 | 1 | RCF_MB4_16M | 0x37 | 0x23 | 0x2A | 0x24 |
+ |3G_FDD_Band18 | 0 | RCF_LB3_16M | 0x24 | 0x19 | 0x23 | 0x1D |
+ |3G_FDD_Band19 | 0 | RCF_LB2_16M | 0x21 | 0x19 | 0x23 | 0x1D |
+
+ CW709[15:8] CW709[7:0] CW710[15:8] CW710[7:0]
+ |Band | Path | Mode:TX1 | RG_TX1_RCF_RSEL[7:0]|TX1_RCF_CSEL_4[7:0]| TX1_RCF_CSEL_1[7:0] | TX1_RCF_CSEL_2[7:0]|
+ |--------------|-------|-----------------|---------------------|------------------ |----------------------|---------------------|
+ |3G_FDD_Band01 | 1 | RCF_MB1_16M | 0x2A | 0x1D | 0x27 | 0x21 |
+ |3G_FDD_Band02 | 1 | RCF_MB2_16M | 0x2F | 0x20 | 0x28 | 0x22 |
+ |3G_FDD_Band03 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x29 | 0x23 |
+ |3G_FDD_Band04 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x29 | 0x23 |
+ |3G_FDD_Band05 | NA | NA | NA | NA | NA | NA |
+ |3G_FDD_Band06 | NA | NA | NA | NA | NA | NA |
+ |3G_FDD_Band08 | NA | NA | NA | NA | NA | NA |
+ |3G_FDD_Band09 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x29 | 0x23 |
+ |3G_FDD_Band11 | 1 | RCF_MB4_16M | 0x37 | 0x23 | 0x2A | 0x24 |
+ |3G_FDD_Band18 | NA | NA | NA | NA | NA | NA |
+ |3G_FDD_Band19 | NA | NA | NA | NA | NA | NA |
+*/
+
+#define UL1D_DEFAULT_RFC_TX_RCF_BNone \
+ /*tx_rcf_rsel */ 0x2A, \
+ /*tx_rcf_csel_4a */ 0x1D, \
+ /*tx_rcf_csel_1b */ 0x27, \
+ /*tx_rcf_csel_2a */ 0x21,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B1 \
+ /*tx_rcf_rsel */ 0x2A, \
+ /*tx_rcf_csel_4a */ 0x1D, \
+ /*tx_rcf_csel_1b */ 0x27, \
+ /*tx_rcf_csel_2a */ 0x21,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B2 \
+ /*tx_rcf_rsel */ 0x2F, \
+ /*tx_rcf_csel_4a */ 0x20, \
+ /*tx_rcf_csel_1b */ 0x28, \
+ /*tx_rcf_csel_2a */ 0x22,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B3 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x22, \
+ /*tx_rcf_csel_1b */ 0x29, \
+ /*tx_rcf_csel_2a */ 0x23,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B4 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x22, \
+ /*tx_rcf_csel_1b */ 0x29, \
+ /*tx_rcf_csel_2a */ 0x23,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B5 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x20, \
+ /*tx_rcf_csel_1b */ 0x28, \
+ /*tx_rcf_csel_2a */ 0x22,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B6 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x20, \
+ /*tx_rcf_csel_1b */ 0x28, \
+ /*tx_rcf_csel_2a */ 0x22,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B8 \
+ /*tx_rcf_rsel */ 0x1C, \
+ /*tx_rcf_csel_4a */ 0x1D, \
+ /*tx_rcf_csel_1b */ 0x27, \
+ /*tx_rcf_csel_2a */ 0x21,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B9 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x22, \
+ /*tx_rcf_csel_1b */ 0x29, \
+ /*tx_rcf_csel_2a */ 0x23,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B11 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x23, \
+ /*tx_rcf_csel_1b */ 0x2A, \
+ /*tx_rcf_csel_2a */ 0x24,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B18 \
+ /*tx_rcf_rsel */ 0x24, \
+ /*tx_rcf_csel_4a */ 0x19, \
+ /*tx_rcf_csel_1b */ 0x23, \
+ /*tx_rcf_csel_2a */ 0x1D,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B19 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x19, \
+ /*tx_rcf_csel_1b */ 0x23, \
+ /*tx_rcf_csel_2a */ 0x1D,
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_BNone \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B1 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B2 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B3 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B4 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B5 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B6 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B8 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B9 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B11 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B18 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B19 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT \
+},
+
+
+/*
+ Trinity_L_divider_table_v0d1_20170922_1012temporary_L1.xlsx
+ Sheet: 1RX_1TX
+ Band TX Path
+ 1 1
+ 2 1
+ 3 1
+ 4 1
+ 5 0
+ 6 0
+ 7 1
+ 8 0
+ 9 1
+ 10 1
+ 11 1
+ 12 0
+ 13 0
+ 14 0
+ 15 0
+ 17 0
+ 18 0
+ 19 0
+
+ A60864_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+ ------------------------------------------------------------------------------------------------------------------------------
+ | | | CW726[D19~D12]: | CW726[D11~D4]: | CW706[D19~D12]: | CW706[D11~D4]: |
+ |Band | Path | RG_TX0_DRV_CTUNEMOD[7:0] | RG_TX0_PGA_CTUNE[7:0] | RG_TX1_DRV_CTUNEMOD[7:0] | RG_TX1_PGA_CTUNE[7:0] |
+ |--------------|------|---------------------------|-----------------------|--------------------------|-----------------------|
+ |3G_FDD_Band01 | 1 | 0x09 | 0x0F | 0x09 | 0x10 |
+ |3G_FDD_Band02 | 1 | 0x0D | 0x11 | 0x0D | 0x13 |
+ |3G_FDD_Band03 | 1 | 0x14 | 0x17 | 0x13 | 0x19 |
+ |3G_FDD_Band04 | 1 | 0x14 | 0x17 | 0x14 | 0x19 |
+ |3G_FDD_Band05 | 0 | 0x0A | 0x0B | XXXX | XXXX |
+ |3G_FDD_Band06 | 0 | 0x0A | 0x0B | XXXX | XXXX |
+ |3G_FDD_Band08 | 0 | 0x07 | 0x09 | XXXX | XXXX |
+ |3G_FDD_Band09 | 1 | 0x12 | 0x16 | XXXX | XXXX |
+ |3G_FDD_Band11 | 1 | 0x2C | 0x26 | 0x2C | 0x26 |
+ |3G_FDD_Band18 | 0 | 0x0A | 0x0B | XXXX | XXXX |
+ |3G_FDD_Band19 | 0 | 0x0A | 0x0B | XXXX | XXXX |
+ ------------------------------------------------------------------------------------------------------------------------------
+*/
+
+#define UL1D_DEFAULT_RFC_TX_CAP_BNone \
+ /*cap_opt_a */0, \
+ /*tx_drv_ctunemod*/0,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B1 \
+ /*cap_opt_a */0x10, \
+ /*tx_drv_ctunemod*/0x09,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B2 \
+ /*cap_opt_a */0x13, \
+ /*tx_drv_ctunemod*/0x0D,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B3 \
+ /*cap_opt_a */0x19, \
+ /*tx_drv_ctunemod*/0x13,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B4 \
+ /*cap_opt_a */0x19, \
+ /*tx_drv_ctunemod*/0x14,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B5 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B6 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B8 \
+ /*cap_opt_a */0x09, \
+ /*tx_drv_ctunemod*/0x07,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B9 \
+ /*cap_opt_a */0x16, \
+ /*tx_drv_ctunemod*/0x12,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B11 \
+ /*cap_opt_a */0x26, \
+ /*tx_drv_ctunemod*/0x2C,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B18 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B19 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+/*
+ Trinity_L_divider_table_v0d1_20170922_1012temporary_L1.xlsx
+ Sheet: 1RX_1TX
+ Band TX Path
+ 1 1
+ 2 1
+ 3 1
+ 4 1
+ 5 0
+ 6 0
+ 7 1
+ 8 0
+ 9 1
+ 10 1
+ 11 1
+ 12 0
+ 13 0
+ 14 0
+ 15 0
+ 17 0
+ 18 0
+ 19 0
+
+ A60864_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+ ------------------------------------------------------------------------------------------------------------------------------
+ | | | CW726[D19~D12]: | CW726[D11~D4]: | CW706[D19~D12]: | CW706[D11~D4]: |
+ |Band | Path | RG_TX0_DRV_CTUNEMOD[7:0] | RG_TX0_PGA_CTUNE[7:0] | RG_TX1_DRV_CTUNEMOD[7:0] | RG_TX1_PGA_CTUNE[7:0] |
+ |--------------|------|---------------------------|-----------------------|--------------------------|-----------------------|
+ |3G_FDD_Band01 | 1 | 0x09 | 0x0F | 0x09 | 0x10 |
+ |3G_FDD_Band02 | 1 | 0x0D | 0x11 | 0x0D | 0x13 |
+ |3G_FDD_Band03 | 1 | 0x14 | 0x17 | 0x13 | 0x19 |
+ |3G_FDD_Band04 | 1 | 0x14 | 0x17 | 0x14 | 0x19 |
+ |3G_FDD_Band05 | 0 | 0x0A | 0x0B | XXXX | XXXX |
+ |3G_FDD_Band06 | 0 | 0x0A | 0x0B | XXXX | XXXX |
+ |3G_FDD_Band08 | 0 | 0x07 | 0x09 | XXXX | XXXX |
+ |3G_FDD_Band09 | 1 | 0x12 | 0x16 | XXXX | XXXX |
+ |3G_FDD_Band11 | 1 | 0x2C | 0x26 | 0x2C | 0x26 |
+ |3G_FDD_Band18 | 0 | 0x0A | 0x0B | XXXX | XXXX |
+ |3G_FDD_Band19 | 0 | 0x0A | 0x0B | XXXX | XXXX |
+ ------------------------------------------------------------------------------------------------------------------------------
+*/
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_BNone \
+ /*cap_opt_a */0, \
+ /*tx_drv_ctunemod*/0,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_B1 \
+ /*cap_opt_a */0x10, \
+ /*tx_drv_ctunemod*/0x09,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_B2 \
+ /*cap_opt_a */0x13, \
+ /*tx_drv_ctunemod*/0x0D,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_B3 \
+ /*cap_opt_a */0x19, \
+ /*tx_drv_ctunemod*/0x13,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_B4 \
+ /*cap_opt_a */0x19, \
+ /*tx_drv_ctunemod*/0x14,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_B5 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_B6 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_B8 \
+ /*cap_opt_a */0x09, \
+ /*tx_drv_ctunemod*/0x07,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_B9 \
+ /*cap_opt_a */0x16, \
+ /*tx_drv_ctunemod*/0x12,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_B11 \
+ /*cap_opt_a */0x26, \
+ /*tx_drv_ctunemod*/0x2C,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_B18 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_E2_B19 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+
+/*
+A60864A_BBBM_TABLE_v120_PGABIAS_DEF.XLSX
+
+TX0_PGABIAS_BMA1_DEF[7:0] --> Slice 4
+TX0_PGABIAS_BMA2_DEF[7:0] --> Slice 2
+TX0_PGABIAS_BMA3_DEF[7:0] --> Slice 1
+
+TX1_PGABIAS_BMA1_DEF[7:0] --> Slice 4
+TX1_PGABIAS_BMA2_DEF[7:0] --> Slice 2
+TX1_PGABIAS_BMA3_DEF[7:0] --> Slice 1
+
+Trinity_L_divider_table_v0d1_20170922_1012temporary_L1.xlsx
+Sheet: 1RX_1TX
+Band TX Path
+1 1
+2 1
+3 1
+4 1
+5 0
+6 0
+7 1
+8 0
+9 1
+10 1
+11 1
+12 0
+13 0
+14 0
+15 0
+17 0
+18 0
+19 0
+
+*/
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_BNone \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0, \
+ /*BMA2 for PGA_SLICE_2A */0, \
+ /*BMA3 for PGA_SLICE_1A */0 \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B1 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B2 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B3 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B4 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B5 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x54, \
+ /*BMA2 for PGA_SLICE_2A */0x48, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B6 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x54, \
+ /*BMA2 for PGA_SLICE_2A */0x48, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B7 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B8 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x54, \
+ /*BMA2 for PGA_SLICE_2A */0x48, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B9 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B10 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B11 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B18 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x54, \
+ /*BMA2 for PGA_SLICE_2A */0x48, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B19 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x54, \
+ /*BMA2 for PGA_SLICE_2A */0x48, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+
+#define VERNO_BNone (0),
+#define VERNO_B1 (0),
+#define VERNO_B2 (0),
+#define VERNO_B3 (0),
+#define VERNO_B4 (0),
+#define VERNO_B5 (0),
+#define VERNO_B6 (0),
+#define VERNO_B8 (0),
+#define VERNO_B9 (0),
+#define VERNO_B11 (0),
+#define VERNO_B18 (0),
+#define VERNO_B19 (0),
+
+
+#define M_UL1D_DEFAULT_RFC_B(BAND_ID) \
+{ \
+ VERNO_B##BAND_ID \
+ UMTSBand##BAND_ID, \
+ { \
+ UL1D_DEFAULT_RFC_RX_IRR_HPM \
+ UL1D_DEFAULT_RFC_RX_IRR_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+ UL1D_DEFAULT_RFC_RX_IIP2 \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_MRX_CDCOC \
+ UL1D_DEFAULT_RFC_MRX_IQ_B##BAND_ID \
+ UL1D_DEFAULT_RFC_MRX_DC \
+ UL1D_DEFAULT_RFC_MRX_DNL \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_PGA \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_TZA \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_TX_LPF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_RCF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_CDCOC \
+ UL1D_DEFAULT_RFC_TX_IQ_DC \
+ UL1D_DEFAULT_RFC_TX_DNL_PGA_E2 \
+ UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_CAP_E2_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_PGA_BIAS_B##BAND_ID \
+ } \
+}
+
+#endif /*__UL1D_RFC_DATA_MT6185M_H__*/
+
+/* Doxygen Group End ***************************************************//**@}*/
diff --git a/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6186.h b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6186.h
new file mode 100644
index 0000000..8e08897
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6186.h
@@ -0,0 +1,1703 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygen Group Header ****************************************************//**
+ * @addtogroup UL1D_RF_CUSTOM_DATA
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @file ul1d_rf_cal_poc_data.h
+ * @author Neil Chung(MTK08266)
+ * @date 2015.01.26
+ * @brief UL1D RF POC SHM data header file
+ * @details Provide RF POC data structure for PCORE and L1CORE (SHM)
+ ******************************************************************************/
+
+#ifndef __UL1D_RFC_DATA_MT6186_H__
+#define __UL1D_RFC_DATA_MT6186_H__
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "mml1_rf_cal_def.h"
+
+/*******************************************************************************
+ * Typedef
+ ******************************************************************************/
+/** Structure Prototypes can be seen by other files */
+typedef enum
+{
+ UMTSBandNone = 0,
+ UMTSBand1 = 1,
+ UMTSBand2 = 2,
+ UMTSBand3 = 3,
+ UMTSBand4 = 4,
+ UMTSBand5 = 5,
+ UMTSBand6 = 6,
+ UMTSBand7 = 7,
+ UMTSBand8 = 8,
+ UMTSBand9 = 9,
+ UMTSBand10 = 10,
+ UMTSBand11 = 11,
+ UMTSBand12 = 12,
+ UMTSBand13 = 13,
+ UMTSBand14 = 14,
+ UMTSBand15 = 15,
+ UMTSBand16 = 16,
+ UMTSBand17 = 17,
+ UMTSBand18 = 18,
+ UMTSBand19 = 19,
+ UMTSBand20 = 20,
+ UMTSBand21 = 21,
+ UMTSBand22 = 22,
+ UMTSBandcount
+} UMTSBand;
+
+
+/*******************************************************************************
+** RFC dimension define
+*******************************************************************************/
+
+#define UL1D_RXDC_TIA_GAIN_STEPS (4)
+#define UL1D_RXDC_PGA_GAIN_STEPS (7)
+
+#define UL1D_RXDC_HPM_TIA_GAIN_STEPS (UL1D_RXDC_TIA_GAIN_STEPS)
+#define UL1D_RXDC_HPM_PGA_GAIN_STEPS (UL1D_RXDC_PGA_GAIN_STEPS)
+#define UL1D_RXDC_LPM_TIA_GAIN_STEPS (UL1D_RXDC_TIA_GAIN_STEPS)
+#define UL1D_RXDC_LPM_PGA_GAIN_STEPS (UL1D_RXDC_PGA_GAIN_STEPS)
+
+#define UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX (7) /* from MMRFC_RXIRR_FILT_TAPS_NUM */
+#define UL1D_RF_RX_DC_COMP_ROUTE_MAX (1)
+#define UL1D_RF_RX_IRR_COMP_ROUTE_MAX (1)
+#define UL1D_RF_RX_IIP2_COMP_ROUTE_MAX (1)
+
+#define UL1D_RX_CBW_NUM (3 ) /* from MMRFC_UMTS_RX_CBW_NUM */
+#define UL1D_DET_FE_GAIN_STEPS (1 ) /* from MMRFC_DET_FE_GAIN_STEPS */
+#define UL1D_DET_GAIN_STEPS (5 ) /* from MMRFC_DET_GAIN_STEPS */
+#define UL1D_DET_EQLPF_TAP_NUM (13) /* from MMRFC_DET_EQLPF_TAP_NUM */
+#define UL1D_TX_PGA_TYPE_NUM (3 ) /* from MMRFC_TX_PGA_TYPE_NUM */
+#define UL1D_TX_DNL_PGA_A_GAIN_STEPS (22) /* from MMRFC_TX_DNL_PGA_A_GAIN_STEPS */
+#define UL1D_TX_DNL_PGA_B_GAIN_STEPS (0 ) /* from MMRFC_TX_DNL_PGA_B_GAIN_STEPS */
+#define UL1D_TX_DNL_PGA_AUX_GAIN_STEPS (5 ) /* from MMRFC_TX_DNL_PGA_AUX_GAIN_STEPS */
+#define UL1D_TX_PGA_SLICE_NUM (4 ) /* from MMRFC_TX_PGA_SLICE_NUM */
+#define UL1D_TX_PGA_BIAS_NUM (3 ) /* from MMRFC_TX_PGA_BIAS_STEP_NUM */
+#define UL1D_TX_CBW_NUM (2 ) /* from MMRFC_UMTS_TX_CBW_NUM */
+#define UL1D_TX_PGA_GAIN_STEP_NUM (10) /* from MMRFC_TX_PGA_GAIN_STEP_NUM */
+#define UL1D_TX_SUBBAND_NUM (3 ) /* from MMRFC_TX_SUBBAND_NUM */
+#define UL1D_ANT_NUM (2 ) /* from MMRFC_ANT_NUM */
+
+#define UL1D_TX_PGA_CAP_TUNING_SUBBAND_NUM (UL1D_TX_SUBBAND_NUM)/* from MMRFC_TX_PGA_CAP_TUNING_SUBBAND_NUM */
+#define UL1D_TX_DNL_PGA_TOTAL_NUM (UL1D_TX_DNL_PGA_A_GAIN_STEPS + UL1D_TX_DNL_PGA_B_GAIN_STEPS + UL1D_TX_DNL_PGA_AUX_GAIN_STEPS)
+
+
+/******************************
+* Rx POC Part
+*******************************/
+typedef struct
+{
+ kal_int8 gain_est_hw;
+ kal_int8 phase_est_hw;
+ kal_int16 freq_dep_filt[UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX];
+} UMTS_RF_POC_RX_IRR_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_RX_DC_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_HPM_TIA_GAIN_STEPS][UL1D_RXDC_HPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_HPM_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_LPM_TIA_GAIN_STEPS][UL1D_RXDC_LPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_LPM_COMP_T;
+
+typedef struct
+{
+ kal_int8 gate_bias_i;
+ kal_int8 gate_bias_q;
+} UMTS_RF_POC_RX_IIP2_COMP_T;
+
+typedef struct
+{
+ /* RX IRR */
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_hpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_lpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+
+ /* RX DC */
+ #if IS_URF_RXDC_GXE_SUPPORT
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_rf_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_rf_dc_hpm_gxe[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_rf_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_rf_dc_lpm_gxe[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dig_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dig_dc_hpm_gxe[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dig_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dig_dc_lpm_gxe[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ #else
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_rf_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_rf_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dig_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dig_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ #endif
+
+ /* RX IIP2 */
+ UMTS_RF_POC_RX_IIP2_COMP_T rx_iip2[UL1D_ANT_NUM][UL1D_RF_RX_IIP2_COMP_ROUTE_MAX];
+
+} UMTS_RF_POC_RX_COMP_DATA_T;
+
+
+/******************************
+* Tx DET POC Part
+*******************************/
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+
+} UMTS_DET_EQLPF_COMP_T;
+
+typedef struct
+{
+ UMTS_DET_EQLPF_COMP_T coef[UL1D_DET_EQLPF_TAP_NUM];
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+} UMTS_DET_FDADPCB_EQLPF_COMP_T;
+
+typedef struct{
+ kal_int8 dummy;
+ kal_int8 phase_est_hw; //FIIQ phase
+ UMTS_DET_FDADPCB_EQLPF_COMP_T fd_ad_pcb; //FDIQ, AD coefficient, 3G do not contain PCB information
+} UMTS_RF_POC_DET_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_DET_DC_COMP_T;
+
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoc_i;
+ kal_uint32 mrx_cdcoc_q;
+}
+UMTS_RF_POC_MRX_CDCOC_PGA_T;
+
+typedef struct
+{
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_pos_15_db;
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_pos_09_db;
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_pos_03_db;
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_neg_03_db;
+}
+UMTS_RF_POC_MRX_COARSE_DC_T;
+
+
+
+typedef struct
+{
+ /* DET Coarse DCOC */
+ /*
+ Trinity TX Calibrations V1.1 Draft.docx
+ 5.1 MRX Coarse DC-offset Calibration (ES2 Approach)
+
+ We need to calibrate PGA = 15dB, PGA = 9dB, PGA = 3dB, and -3dB.
+ We need to calibrate the TX-loopback and the antenna-loopback separately.
+ DPD also uses PGA gain -9dB, but that PGA gain can reuse the -3dB calibration.
+
+ det_cdcoc[0]: PGA = 15dB --> CW939 : TX1_MRX_CDCOC_I/Q1[4:0]
+ det_cdcoc[0]: PGA = 15dB --> CW1006: TX0_MRX_CDCOC_I/Q1[4:0]
+
+ det_cdcoc[1]: PGA = 9dB --> CW939 : TX1_MRX_CDCOC_I/Q2[4:0]
+ det_cdcoc[1]: PGA = 9dB --> CW1006: TX0_MRX_CDCOC_I/Q2[4:0]
+
+ det_cdcoc[2]: PGA = 3dB --> CW940 : TX1_MRX_CDCOC_I/Q3[4:0]
+ det_cdcoc[2]: PGA = 3dB --> CW1007: TX0_MRX_CDCOC_I/Q3[4:0]
+
+ det_cdcoc[3]: PGA = -3dB --> CW940 : TX1_MRX_CDCOC_I/Q4[4:0]
+ det_cdcoc[3]: PGA = -3dB --> CW1007: TX0_MRX_CDCOC_I/Q4[4:0]
+ */
+ UMTS_RF_POC_MRX_COARSE_DC_T det_cdcoc;
+ UMTS_RF_POC_MRX_COARSE_DC_T det_cdcoc_tx_lb;
+
+ /* DET IQ/DC/DNL Forward */
+ UMTS_RF_POC_DET_IQ_COMP_T det_iq_fwd[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_fwd[UL1D_DET_GAIN_STEPS];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_fwd_tx_lb[UL1D_DET_GAIN_STEPS];
+ kal_int16 det_dnl_fwd[UL1D_DET_GAIN_STEPS];
+
+ kal_int16 mrx_ctune_pga[2/*MMRFC_MRX_PGA_TZA_BW_CNT*/];
+ kal_int16 mrx_ctune_tza[2/*MMRFC_MRX_PGA_TZA_BW_CNT*/];
+
+} UMTS_RF_POC_DET_COMP_DATA_T;
+
+/******************************
+* Tx FOWRAD POC Part
+*******************************/
+typedef struct{
+ kal_int8 gain_est;
+ kal_int8 phase_est;
+} UMTS_RF_POC_TX_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_TX_DC_COMP_T;
+
+typedef struct
+{
+
+ /* TX LPF*/
+ kal_int16 tx_lpf_abb_rsel;
+ kal_int16 tx_lpf_abb_csel_1;
+ kal_int16 tx_lpf_abb_csel_2;
+
+ /* TX RCF*/
+ kal_int16 tx_rcf_rsel;
+ kal_int16 tx_rcf_csel_4a;
+ kal_int16 tx_rcf_csel_1b;
+ kal_int16 tx_rcf_csel_2a;
+
+ /* TX CDCOC */
+ /*
+ Trinity TX Calibrations Table V1.1 Draft.xlsx
+ 1) Coarse DC offset compensator located in DAC IP (modem). Compensation changes with # of slices (gain word).
+ 2) Requires recalibration per RAT because of changes in R used in ABB. RAT's using same R can reuse calibration
+ 3) Requires L1 and CSD support
+
+ per ABB slice CM: 4A, 2A, 1A, 1B
+ */
+ UMTS_RF_POC_TX_DC_COMP_T tx_cdcoc[UL1D_TX_PGA_SLICE_NUM];
+
+ /* TX FIIQ/DC/DNL Linear Mode */
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_lin[UL1D_TX_PGA_SLICE_NUM];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_lin[UL1D_TX_PGA_SLICE_NUM];
+
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_dpd[UL1D_TX_PGA_SLICE_NUM];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_dpd[UL1D_TX_PGA_SLICE_NUM];
+
+ kal_int16 tx_dnl_lin_pga_a[UL1D_TX_DNL_PGA_TOTAL_NUM];
+
+ /* TX PGA Phase Step */
+ kal_int32 tx_mod_slice_phase[UL1D_TX_PGA_SLICE_NUM/*Slice: 0:4A, 1:2A, 2:1A, 3:AUX*/];
+
+ /* TX PGA Cap Tuning */
+ kal_uint32 cap_opt_a;
+ kal_uint32 tx_drv_ctunemod;
+
+ /* TX PGA BIAS: 4 calibrated BMA_CAL<7:0> codes */
+ /* 3 BMA values used for different number of PGA slices (4/2/1)*/
+ /* 1 additional BMA value used in DPD mode. The latter is never used in practice*/
+ /* A60864_TX_Programming_Guide_v1p0.docx
+ 4.3.1 PGA Bias Calibration programming
+
+ CW888: TX1_PGABIAS_BMA1_DEF[7:0]-->PGABIAS BMA4 gain lookup default-->DPD
+ CW888: TX1_PGABIAS_BMA2_DEF[7:0]-->PGABIAS BMA3 gain lookup default-->1 Slice
+ CW887: TX1_PGABIAS_BMA3_DEF[7:0]-->PGABIAS BMA2 gain lookup default-->2 Slices
+ CW887: TX1_PGABIAS_BMA4_DEF[7:0]-->PGABIAS BMA1 gain lookup default-->4 Slices
+
+ CW955: TX0_PGABIAS_BMA1_DEF[7:0]-->PGABIAS BMA4 gain lookup default-->DPD
+ CW955: TX0_PGABIAS_BMA2_DEF[7:0]-->PGABIAS BMA3 gain lookup default-->1 Slice
+ CW954: TX0_PGABIAS_BMA3_DEF[7:0]-->PGABIAS BMA2 gain lookup default-->2 Slices
+ CW954: TX0_PGABIAS_BMA4_DEF[7:0]-->PGABIAS BMA2 gain lookup default-->4 Slices
+ */
+ kal_int32 tx_pga_bias[UL1D_TX_PGA_BIAS_NUM/* Slice: 0:4A, 1:2A, 2:1A */];
+
+} UMTS_RF_POC_TX_COMP_DATA_T;
+
+typedef struct
+{
+ kal_uint32 verno;
+ UMTSBand band;
+ UMTS_RF_POC_RX_COMP_DATA_T umts_rx_comp;
+ UMTS_RF_POC_DET_COMP_DATA_T umts_det_comp;
+ UMTS_RF_POC_TX_COMP_DATA_T umts_tx_comp;
+} UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T;
+
+
+/*******************************************************************************
+** Macro define for POC default value
+*******************************************************************************/
+
+
+/*Trinity_RX_Programming_Guide_0p1_20170607 */
+/*Table 4-3 DCOC Mapping Table */
+/*Offset Voltage(V) = 0V, DCOC[5:0] = 6'b100000 */
+
+#define UMTS_RXDC_RF_I_Default (0xFFE0)
+#define UMTS_RXDC_RF_Q_Default (0xFFE0)
+#define UMTS_RXDC_Dig_I_Default (0)
+#define UMTS_RXDC_Dig_Q_Default (0)
+
+#define UMTS_RXDC_RF_IQ_Default \
+{\
+ UMTS_RXDC_RF_I_Default, UMTS_RXDC_RF_Q_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_Default \
+{\
+ UMTS_RXDC_Dig_I_Default,\
+ UMTS_RXDC_Dig_Q_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default,\
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default \
+{\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default \
+{\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+}
+
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default \
+{\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default \
+{\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+}
+
+
+
+#define UMTS_RXDC_RF_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_RF_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+#define UMTS_RX_IRR_TAP_DEFAULT \
+{ \
+ /*ANT0*/{0,0,{0,0,0,1024,0,0,0}}, \
+ /*ANT1*/{0,0,{0,0,0,1024,0,0,0}}, \
+}
+
+#define UMTS_RX_IIP2_I_DEFAULT (64)
+#define UMTS_RX_IIP2_Q_DEFAULT (64)
+#define UMTS_RX_IIP2_DEFAULT {UMTS_RX_IIP2_I_DEFAULT, UMTS_RX_IIP2_Q_DEFAULT}
+
+/*
+Manel:
+Please note that the table shows the phase change introduced by RF.
+The DFE compensation must have the opposite sign than what is shown on the table.
+
+03/09/2018 Update Phase Jump Table
+*/
+
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_4_to_2 (-20 ) // 3.5x(-1)x1024/180
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_2_to_1 (-14 ) // 2.5x(-1)x1024/180
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_4_to_1 (0 ) // NOT defined
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_1_to_AUX (28 ) // -5x(-1)x1024/180
+
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_4_to_2 (-28 ) // 5x(-1)x1024/180
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_2_to_1 (-46 ) // 8x(-1)x1024/180
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_4_to_1 (0 ) // NOT defined
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_1_to_AUX ( 46 ) // -8x(-1)x1024/180
+
+
+#define UMTS_TX_PHASE_LB_4A_DEFAULT (0)
+#define UMTS_TX_PHASE_LB_2A_DEFAULT (UMTS_TX_PHASE_LB_4A_DEFAULT+UMTS_TX_LB_PHASE_SLICE_CHANGE_4_to_2)
+#define UMTS_TX_PHASE_LB_1A_DEFAULT (UMTS_TX_PHASE_LB_2A_DEFAULT+UMTS_TX_LB_PHASE_SLICE_CHANGE_2_to_1)
+#define UMTS_TX_PHASE_LB_AUX_DEFAULT (UMTS_TX_PHASE_LB_1A_DEFAULT+UMTS_TX_LB_PHASE_SLICE_CHANGE_1_to_AUX)
+
+
+#define UMTS_TX_PHASE_MB_4A_DEFAULT (0)
+#define UMTS_TX_PHASE_MB_2A_DEFAULT (UMTS_TX_PHASE_MB_4A_DEFAULT+UMTS_TX_MB_PHASE_SLICE_CHANGE_4_to_2)
+#define UMTS_TX_PHASE_MB_1A_DEFAULT (UMTS_TX_PHASE_MB_2A_DEFAULT+UMTS_TX_MB_PHASE_SLICE_CHANGE_2_to_1)
+#define UMTS_TX_PHASE_MB_AUX_DEFAULT (UMTS_TX_PHASE_MB_1A_DEFAULT+UMTS_TX_MB_PHASE_SLICE_CHANGE_1_to_AUX)
+
+
+/*95_TxDFERF_TxK_default_settings_20171027.xlsx*/
+#define UMTS_DET_IQ_PHASE_EST_HW_DEFAULT (0)/*phase_est_hw: DET_FI (S-4.10.9) POC*/
+
+#define UMTS_DET_IQ_EQLPF_I_SCALE_DEFAULT (1)/*scale_i: DET_EQLPF_I_SCALE (U2.0)*/
+
+#define UMTS_DET_IQ_EQLPF_Q_SCALE_DEFAULT (1)/*scale_q: DET_EQLPF_Q_SCALE (U2.0)*/
+
+#define UMTS_DET_IQ_EQ_COEF_DEFAULT \
+{ \
+ { 4, 4},/*coef[00]: DET_EQLPF_I_C00, DET_EQLPF_Q_C00*/ \
+ { -22, -22},/*coef[01]: DET_EQLPF_I_C01, DET_EQLPF_Q_C01*/ \
+ { 74, 74},/*coef[02]: DET_EQLPF_I_C02, DET_EQLPF_Q_C02*/ \
+ { -186, -186},/*coef[03]: DET_EQLPF_I_C03, DET_EQLPF_Q_C03*/ \
+ { 417, 417},/*coef[04]: DET_EQLPF_I_C04, DET_EQLPF_Q_C04*/ \
+ {-1021,-1021},/*coef[05]: DET_EQLPF_I_C05, DET_EQLPF_Q_C05*/ \
+ { 3513, 3513},/*coef[06]: DET_EQLPF_I_C06, DET_EQLPF_Q_C06*/ \
+ {-1010,-1010},/*coef[07]: DET_EQLPF_I_C07, DET_EQLPF_Q_C07*/ \
+ { 401, 401},/*coef[08]: DET_EQLPF_I_C08, DET_EQLPF_Q_C08*/ \
+ { -171, -171},/*coef[09]: DET_EQLPF_I_C09, DET_EQLPF_Q_C09*/ \
+ { 65, 65},/*coef[10]: DET_EQLPF_I_C10, DET_EQLPF_Q_C10*/ \
+ { -18, -18},/*coef[11]: DET_EQLPF_I_C11, DET_EQLPF_Q_C11*/ \
+ { 3, 3} /*coef[12]: DET_EQLPF_I_C12, DET_EQLPF_Q_C12*/ \
+}
+
+
+/*95_TxDFERF_TxK_default_settings_20171027.xlsx*/
+#define UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+ UMTS_DET_IQ_PHASE_EST_HW_DEFAULT, \
+ { /* fd_ad_pcb: */ \
+ UMTS_DET_IQ_EQ_COEF_DEFAULT, \
+ UMTS_DET_IQ_EQLPF_I_SCALE_DEFAULT, \
+ UMTS_DET_IQ_EQLPF_Q_SCALE_DEFAULT \
+ }
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_BNone \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B1 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B2 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B3 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B4 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B5 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B6 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B8 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B9 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B11 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B18 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B19 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_DET_IQ_MG_DFAULT_BNone \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_BNone,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_BNone,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B1 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B1,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B1,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B2 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B2,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B2,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B3 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B3,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B3,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B4 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B4,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B4,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B5 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B5,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B5,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B6 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B6,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B6,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B8 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B8,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B8,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B9 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B9,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B9,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B11 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B11,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B11,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B18 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B18,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B18,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B19 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B19,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B19,\
+},
+
+
+#define UMTS_DET_DC_DEFAULT {0/*DC_I*/, 0/*DC_Q*/}
+
+
+// RX
+//============================================================
+#define UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+{ \
+ UMTS_RXDC_RF_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+{ \
+ UMTS_RXDC_RF_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+{ \
+ UMTS_RXDC_Dig_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+{ \
+ UMTS_RXDC_Dig_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_IRR_HPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 1, HPM*/ \
+ { \
+ /*SC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*DC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*3C*/UMTS_RX_IRR_TAP_DEFAULT \
+ }, \
+},
+
+#define UL1D_DEFAULT_RFC_RX_IRR_LPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 1, LPM*/ \
+ { \
+ /*SC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*DC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*3C*/UMTS_RX_IRR_TAP_DEFAULT \
+ }, \
+},
+
+
+#define UL1D_DEFAULT_RFC_RX_IIP2 \
+{ \
+ { /*RXP*/ \
+ UMTS_RX_IIP2_DEFAULT,/*ROUTE00*/ \
+ }, \
+ { /*RXD*/ \
+ UMTS_RX_IIP2_DEFAULT,/*ROUTE00*/ \
+ } \
+},
+
+
+//DET
+//============================================================
+
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_BNone \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_BNone \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B1 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B1 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B2 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B2 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B3 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B3 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B4 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B4 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B5 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B5 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B6 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B6 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B8 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B8 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B9 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B9 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B11 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B11 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B18 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B18 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B19 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B19 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_DC \
+ { /* UL1D_DET_GAIN_STEPS = 5*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG00*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG01*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG02*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG03*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG04*/ \
+ },
+
+/* B60864A_BBBM_TABLE.xlsx */
+/* sheet: MRX0_GAIN & MRX1_GAIN */
+/* MRX Gain*/
+#define UL1D_DEFAULT_RFC_MRX_DNL \
+{ \
+ 384, /* G0: 12 dB*/ \
+ 192, /* G1: 6 dB*/ \
+ 0, /* G2: 0 dB*/ \
+ -192, /* G3: -6 dB*/ \
+ -384, /* G4: -12 dB*/ \
+},
+
+
+#define UL1D_DEFAULT_RFC_MRX_CDCOC_PGA \
+{ \
+ /* mrx_cdcoc_i */0, \
+ /* mrx_cdcoc_q */0 \
+}
+
+
+#define UL1D_DEFAULT_RFC_MRX_CDCOC \
+{ \
+ /* pga_pos_15_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA, \
+ /* pga_pos_09_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA, \
+ /* pga_pos_03_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA, \
+ /* pga_neg_03_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA \
+},
+
+
+
+/*
+ A60827_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+ CW718[D07:D00] RG_TX1_MRX_PGA_CTUNE[7:0] = 0x3C
+ CW718[D15:D08] RG_TX1_MRX_TZA_CTUNE[7:0] = 0x18
+ CW738[D07:D00] RG_TX0_MRX_PGA_CTUNE[7:0] = 0x3C
+ CW738[D15:D08] RG_TX0_MRX_TZA_CTUNE[7:0] = 0x18
+*/
+
+#define UL1D_DEFAULT_RFC_MRX_CTUNE_PGA \
+{ \
+ /* MMRFC_MRX_PGA_TZA_BW_22P5 */0x3C,\
+ /* MMRFC_MRX_PGA_TZA_BW_67P5 */0x3C \
+},
+
+#define UL1D_DEFAULT_RFC_MRX_CTUNE_TZA \
+{ \
+ /* MMRFC_MRX_PGA_TZA_BW_22P5 */0x18,\
+ /* MMRFC_MRX_PGA_TZA_BW_67P5 */0x18 \
+},
+
+
+//TX
+//============================================================
+
+
+/*DOC : Trinity-L TX Gain Table V3.0 Released.xlsx */
+/*Sheet: Gain Tables */
+/*Table: LB & MB & HB_UHB */
+
+#define UL1D_DEFAULT_RFC_TX_DNL_PGA \
+{ \
+ 0 , /* G0 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = 0.00 dB */ \
+ -18 , /* G1 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -0.56 dB */ \
+ -37 , /* G2 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -1.16 dB */ \
+ -58 , /* G3 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -1.80 dB */ \
+ -80 , /* G4 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -2.50 dB */ \
+ -104 , /* G5 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -3.25 dB */ \
+ -131 , /* G6 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -4.08 dB */ \
+ -160 , /* G7 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -4.99 dB */ \
+ -193 , /* G8 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -6.02 dB */ \
+ -230 , /* G9 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -7.18 dB */ \
+ -273 , /* G10 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -8.52 dB */ \
+ -323 , /* G11 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -10.10dB */ \
+ -366 , /* G12 , A , ABB MOD LO Slice = 2, PGA Slice = 4, Gain = -11.43dB */ \
+ -468 , /* G13 , A , ABB MOD LO Slice = 2, PGA Slice = 2, Gain = -14.62dB */ \
+ -526 , /* G14 , A , ABB MOD LO Slice = 1, PGA Slice = 4, Gain = -16.45dB */ \
+ -621 , /* G15 , A , ABB MOD LO Slice = 1, PGA Slice = 2, Gain = -19.40dB */ \
+ -734 , /* G16 , A , ABB MOD LO Slice = 1, PGA Slice = 2, Gain = -22.93dB */ \
+ -853 , /* G17 , A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -26.67dB */ \
+ -988 , /* G18 , A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -30.89dB */ \
+ -1181, /* G19 , A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -36.91dB */ \
+ -1374, /* G20 , A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -42.93dB */ \
+ -1566, /* G21 , A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -48.95dB */ \
+ -1759, /* G22 , AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -54.97dB */ \
+ -1952, /* G23 , AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -60.99dB */ \
+ -2144, /* G24 , AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -67.01dB */ \
+ -1759, /* G25DNL, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -54.97dB */ \
+ -1952 /* G26DNL, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -60.99dB */ \
+},
+
+#define UL1D_DEFAULT_RFC_TX_IQ_DC \
+ /*tx_iq_lin*/{{0,0}}, \
+ /*tx_dc_lin*/{{0,0}}, \
+ /*tx_iq_dpd*/{{0,0}}, \
+ /*tx_dc_dpd*/{{0,0}},
+
+#define UL1D_DEFAULT_RFC_TX_CDCOC \
+ { \
+ /*tx_cdcoc[0:MMRFC_TX_ABB_SLICE_CAL_4A ]*/{/*dc_i*/0,/*dc_q*/0}, \
+ /*tx_cdcoc[1:MMRFC_TX_ABB_SLICE_CAL_2A ]*/{/*dc_i*/0,/*dc_q*/0}, \
+ /*tx_cdcoc[2:MMRFC_TX_ABB_SLICE_CAL_1A ]*/{/*dc_i*/0,/*dc_q*/0}, \
+ /*tx_cdcoc[3:MMRFC_TX_ABB_SLICE_CAL_AUX]*/{/*dc_i*/0,/*dc_q*/0} \
+ },
+
+/* TX LPF*/
+/* ==============================================================================
+
+ A60864_TX_Programming_Guide_v1p0.docx,
+ - 3.7 Bandwidth control, Table 3 15 3G Filter Configurations: LPF_6P8M/CW719/CW739
+ - 3.7.1 ABB BW Controls, Table 3 18 ABB RC Controls: TX0_BBBM10 & TX1_BBBM10
+ Trinity_L_divider_table_v0d1_20170922_1012temporary_L1.xlsx
+ Sheet: 1RX_1TX
+ Band TX Path
+ 1 1
+ 2 1
+ 3 1
+ 4 1
+ 5 0
+ 6 0
+ 7 1
+ 8 0
+ 9 1
+ 10 1
+ 11 1
+ 12 0
+ 13 0
+ 14 0
+ 15 0
+ 17 0
+ 18 0
+ 19 0
+
+ B60864A_BBBM_TABLE_MERGED.xlsx
+ sheet: TX0 & TX0_LPF
+ sheet: TX1 & TX1_LPF
+
+ CW739 TX0_BBBM10 TX0_ABB_CSEL1/2[7:0] TX0_ABB_RSEL [1:0]
+ CW719 TX1_BBBM10 TX1_ABB_CSEL1/2[7:0] TX1_ABB_RSEL [1:0] --> 2 bits
+ CW890 TX1_ABBMAN1 TX1_ABB_CSEL1_M[7:0] -------------------
+ TX1_ABB_CSEL2_M[7:0] -------------------
+ CW957 TX2_ABBMAN1 TX2_ABB_CSEL1_M[7:0] -------------------
+ TX2_ABB_CSEL2_M[7:0] -------------------
+ CW891 TX1_ABBMAN2 -------------------- TX1_ABB_RSEL_M[3:0] --> 4 bits ?
+ CW958 TX2_ABBMAN2 -------------------- TX2_ABB_RSEL_M[3:0]
+
+ |Band | Path | Mode | TX0/1_ABB_CSEL1[7:0]| TX0/1_ABB_CSEL2[7:0]| TX0/1_ABB_RSEL[1:0]|
+ |-------------|---------|----------|---------------------|---------------------|--------------------|
+ |3G_FDD_Band01| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band02| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band03| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band04| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band05| 0 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band06| 0 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band08| 0 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band09| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band11| 1 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band18| 0 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+ |3G_FDD_Band19| 0 |LPF_6P8M | 0xA2 | 0xAC | 0x2 |
+
+ =============================================================================*/
+
+#define UL1D_DEFAULT_RFC_TX_LPF_BNone \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2,\
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B1 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B2 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B3 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B4 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B5 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B6 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B8 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B9 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B11 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B18 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B19 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xA2, \
+ /*tx_lpf_abb_csel_2*/ 0xAC,
+
+
+
+
+/* TX RCF*/
+/*
+ A60864A_BBBM_TABLE_MERGED.xlsx
+ A60864_TX_Programming_Guide_v1p0.docx,
+ - 3.7.2 RCF BW Controls
+ CW729 TX0_BBBM5 RCEL [15:8] CSEL_4[7:0]
+ CW730 TX0_BBBM6 CSEL1[15:8] CSEL_2[7:0]
+
+ CW709 TX1_BBBM5 RCEL [15:8] CSEL_4[7:0]
+ CW710 TX1_BBBM6 CSEL1[15:8] CSEL_2[7:0]
+
+ Trinity_L_divider_table_v0d1_20170922_1012temporary_L1.xlsx
+ Sheet: 1RX_1TX
+ Band TX Path
+ 1 1
+ 2 1
+ 3 1
+ 4 1
+ 5 0
+ 6 0
+ 7 1
+ 8 0
+ 9 1
+ 10 1
+ 11 1
+ 12 0
+ 13 0
+ 14 0
+ 15 0
+ 17 0
+ 18 0
+ 19 0
+
+ A60864_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+
+ CW729[15:8] CW729[7:0] CW730[15:8] CW730[7:0]
+ |Band | Path | Mode:TX0 | RG_TX0_RCF_RSEL[7:0]|TX0_RCF_CSEL_4[7:0]| TX0_RCF_CSEL_1[7:0] | TX0_RCF_CSEL_2[7:0]|
+ |--------------|-------|-----------------|---------------------|------------------ |----------------------|---------------------|
+ |3G_FDD_Band01 | 1 | RCF_MB1_16M | 0x2A | 0x1D | 0x27 | 0x21 |
+ |3G_FDD_Band02 | 1 | RCF_MB2_16M | 0x2F | 0x20 | 0x28 | 0x22 |
+ |3G_FDD_Band03 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x29 | 0x23 |
+ |3G_FDD_Band04 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x22 | 0x22 |
+ |3G_FDD_Band05 | 0 | RCF_LB2_16M | 0x21 | 0x19 | 0x23 | 0x1D |
+ |3G_FDD_Band06 | 0 | RCF_LB2_16M | 0x21 | 0x19 | 0x23 | 0x1D |
+ |3G_FDD_Band08 | 0 | RCF_LB1_16M | 0x1C | 0x14 | 0x1E | 0x19 |
+ |3G_FDD_Band09 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x29 | 0x23 |
+ |3G_FDD_Band11 | 1 | RCF_MB4_16M | 0x37 | 0x23 | 0x2A | 0x24 |
+ |3G_FDD_Band18 | 0 | RCF_LB3_16M | 0x24 | 0x19 | 0x23 | 0x1D |
+ |3G_FDD_Band19 | 0 | RCF_LB2_16M | 0x21 | 0x19 | 0x23 | 0x1D |
+
+ CW709[15:8] CW709[7:0] CW710[15:8] CW710[7:0]
+ |Band | Path | Mode:TX1 | RG_TX1_RCF_RSEL[7:0]|TX1_RCF_CSEL_4[7:0]| TX1_RCF_CSEL_1[7:0] | TX1_RCF_CSEL_2[7:0]|
+ |--------------|-------|-----------------|---------------------|------------------ |----------------------|---------------------|
+ |3G_FDD_Band01 | 1 | RCF_MB1_16M | 0x2A | 0x1D | 0x27 | 0x21 |
+ |3G_FDD_Band02 | 1 | RCF_MB2_16M | 0x2F | 0x20 | 0x28 | 0x22 |
+ |3G_FDD_Band03 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x29 | 0x23 |
+ |3G_FDD_Band04 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x29 | 0x23 |
+ |3G_FDD_Band05 | NA | NA | NA | NA | NA | NA |
+ |3G_FDD_Band06 | NA | NA | NA | NA | NA | NA |
+ |3G_FDD_Band08 | NA | NA | NA | NA | NA | NA |
+ |3G_FDD_Band09 | 1 | RCF_MB3_16M | 0x37 | 0x22 | 0x29 | 0x23 |
+ |3G_FDD_Band11 | 1 | RCF_MB4_16M | 0x37 | 0x23 | 0x2A | 0x24 |
+ |3G_FDD_Band18 | NA | NA | NA | NA | NA | NA |
+ |3G_FDD_Band19 | NA | NA | NA | NA | NA | NA |
+*/
+
+#define UL1D_DEFAULT_RFC_TX_RCF_BNone \
+ /*tx_rcf_rsel */ 0x2A, \
+ /*tx_rcf_csel_4a */ 0x1D, \
+ /*tx_rcf_csel_1b */ 0x27, \
+ /*tx_rcf_csel_2a */ 0x21,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B1 \
+ /*tx_rcf_rsel */ 0x2A, \
+ /*tx_rcf_csel_4a */ 0x1D, \
+ /*tx_rcf_csel_1b */ 0x27, \
+ /*tx_rcf_csel_2a */ 0x21,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B2 \
+ /*tx_rcf_rsel */ 0x2F, \
+ /*tx_rcf_csel_4a */ 0x20, \
+ /*tx_rcf_csel_1b */ 0x28, \
+ /*tx_rcf_csel_2a */ 0x22,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B3 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x22, \
+ /*tx_rcf_csel_1b */ 0x29, \
+ /*tx_rcf_csel_2a */ 0x23,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B4 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x22, \
+ /*tx_rcf_csel_1b */ 0x29, \
+ /*tx_rcf_csel_2a */ 0x23,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B5 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x19, \
+ /*tx_rcf_csel_1b */ 0x23, \
+ /*tx_rcf_csel_2a */ 0x1D,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B6 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x19, \
+ /*tx_rcf_csel_1b */ 0x23, \
+ /*tx_rcf_csel_2a */ 0x1D,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B8 \
+ /*tx_rcf_rsel */ 0x1C, \
+ /*tx_rcf_csel_4a */ 0x14, \
+ /*tx_rcf_csel_1b */ 0x1E, \
+ /*tx_rcf_csel_2a */ 0x19,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B9 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x22, \
+ /*tx_rcf_csel_1b */ 0x29, \
+ /*tx_rcf_csel_2a */ 0x23,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B11 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x23, \
+ /*tx_rcf_csel_1b */ 0x2A, \
+ /*tx_rcf_csel_2a */ 0x24,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B18 \
+ /*tx_rcf_rsel */ 0x24, \
+ /*tx_rcf_csel_4a */ 0x19, \
+ /*tx_rcf_csel_1b */ 0x23, \
+ /*tx_rcf_csel_2a */ 0x1D,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B19 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x19, \
+ /*tx_rcf_csel_1b */ 0x23, \
+ /*tx_rcf_csel_2a */ 0x1D,
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_BNone \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT, \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B1 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT, \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B2 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT, \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B3 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT, \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B4 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT, \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B5 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B6 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B8 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B9 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B11 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B18 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B19 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+
+/*
+ Trinity_L_divider_table_v0d1_20170922_1012temporary_L1.xlsx
+ Sheet: 1RX_1TX
+ Band TX Path
+ 1 1
+ 2 1
+ 3 1
+ 4 1
+ 5 0
+ 6 0
+ 7 1
+ 8 0
+ 9 1
+ 10 1
+ 11 1
+ 12 0
+ 13 0
+ 14 0
+ 15 0
+ 17 0
+ 18 0
+ 19 0
+
+ B60864_E2_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value.xls
+ ------------------------------------------------------------------------------------------------------------------------------
+ | | | CW726[D19~D12]: | CW726[D11~D4]: | CW706[D19~D12]: | CW706[D11~D4]: |
+ |Band | Path | RG_TX0_DRV_CTUNEMOD[7:0] | RG_TX0_PGA_CTUNE[7:0] | RG_TX1_DRV_CTUNEMOD[7:0] | RG_TX1_PGA_CTUNE[7:0] |
+ |--------------|------|---------------------------|-----------------------|--------------------------|-----------------------|
+ |3G_FDD_Band01 | 1 | 0x09 | 0x0F | 0x09 | 0x10 |
+ |3G_FDD_Band02 | 1 | 0x0D | 0x11 | 0x0D | 0x13 |
+ |3G_FDD_Band03 | 1 | 0x14 | 0x17 | 0x13 | 0x19 |
+ |3G_FDD_Band04 | 1 | 0x14 | 0x17 | 0x14 | 0x19 |
+ |3G_FDD_Band05 | 0 | 0x14 | 0x0B | XXXX | XXXX |
+ |3G_FDD_Band06 | 0 | 0x14 | 0x0B | XXXX | XXXX |
+ |3G_FDD_Band08 | 0 | 0x0E | 0x09 | 0x0E | 0x09 |
+ |3G_FDD_Band09 | 1 | 0x12 | 0x16 | 0x12 | 0x16 |
+ |3G_FDD_Band11 | 1 | 0x2C | 0x2B | 0x2C | 0x2B |
+ |3G_FDD_Band18 | 0 | 0x14 | 0x0B | XXXX | XXXX |
+ |3G_FDD_Band19 | 0 | 0x14 | 0x0B | XXXX | XXXX |
+ ------------------------------------------------------------------------------------------------------------------------------
+*/
+
+#define UL1D_DEFAULT_RFC_TX_CAP_BNone \
+ /*cap_opt_a */0, \
+ /*tx_drv_ctunemod*/0,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B1 \
+ /*cap_opt_a */0x10, \
+ /*tx_drv_ctunemod*/0x09,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B2 \
+ /*cap_opt_a */0x13, \
+ /*tx_drv_ctunemod*/0x0D,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B3 \
+ /*cap_opt_a */0x19, \
+ /*tx_drv_ctunemod*/0x13,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B4 \
+ /*cap_opt_a */0x19, \
+ /*tx_drv_ctunemod*/0x14,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B5 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x14,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B6 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x14,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B8 \
+ /*cap_opt_a */0x09, \
+ /*tx_drv_ctunemod*/0x0E,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B9 \
+ /*cap_opt_a */0x16, \
+ /*tx_drv_ctunemod*/0x12,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B11 \
+ /*cap_opt_a */0x2B, \
+ /*tx_drv_ctunemod*/0x2C,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B18 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x14,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B19 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x14,
+
+
+/*
+B60864A_BBBM_TABLE.xlsx
+sheet: TX0 & TX1
+
+TX0_PGABIAS_BMA1_DEF[7:0] --> Slice 4
+TX0_PGABIAS_BMA2_DEF[7:0] --> Slice 2
+TX0_PGABIAS_BMA3_DEF[7:0] --> Slice 1
+
+TX1_PGABIAS_BMA1_DEF[7:0] --> Slice 4
+TX1_PGABIAS_BMA2_DEF[7:0] --> Slice 2
+TX1_PGABIAS_BMA3_DEF[7:0] --> Slice 1
+
+Trinity_L_divider_table_v0d1_20170922_1012temporary_L1.xlsx
+Sheet: 1RX_1TX
+Band TX Path
+1 1
+2 1
+3 1
+4 1
+5 0
+6 0
+7 1
+8 0
+9 1
+10 1
+11 1
+12 0
+13 0
+14 0
+15 0
+17 0
+18 0
+19 0
+
+*/
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_BNone \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0, \
+ /*BMA2 for PGA_SLICE_2A */0, \
+ /*BMA3 for PGA_SLICE_1A */0 \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B1 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B2 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B3 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B4 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B5 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x54, \
+ /*BMA2 for PGA_SLICE_2A */0x48, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B6 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x54, \
+ /*BMA2 for PGA_SLICE_2A */0x48, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B7 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B8 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x54, \
+ /*BMA2 for PGA_SLICE_2A */0x48, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B9 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B10 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B11 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B18 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x54, \
+ /*BMA2 for PGA_SLICE_2A */0x48, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B19 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x54, \
+ /*BMA2 for PGA_SLICE_2A */0x48, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+
+#define VERNO_BNone (0),
+#define VERNO_B1 (0),
+#define VERNO_B2 (0),
+#define VERNO_B3 (0),
+#define VERNO_B4 (0),
+#define VERNO_B5 (0),
+#define VERNO_B6 (0),
+#define VERNO_B8 (0),
+#define VERNO_B9 (0),
+#define VERNO_B11 (0),
+#define VERNO_B18 (0),
+#define VERNO_B19 (0),
+
+#if IS_URF_RXDC_GXE_SUPPORT
+#define M_UL1D_DEFAULT_RFC_B(BAND_ID) \
+{ \
+ VERNO_B##BAND_ID \
+ UMTSBand##BAND_ID, \
+ { \
+ UL1D_DEFAULT_RFC_RX_IRR_HPM \
+ UL1D_DEFAULT_RFC_RX_IRR_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+ UL1D_DEFAULT_RFC_RX_IIP2 \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_MRX_CDCOC \
+ UL1D_DEFAULT_RFC_MRX_CDCOC \
+ UL1D_DEFAULT_RFC_MRX_IQ_B##BAND_ID \
+ UL1D_DEFAULT_RFC_MRX_DC \
+ UL1D_DEFAULT_RFC_MRX_DC \
+ UL1D_DEFAULT_RFC_MRX_DNL \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_PGA \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_TZA \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_TX_LPF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_RCF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_CDCOC \
+ UL1D_DEFAULT_RFC_TX_IQ_DC \
+ UL1D_DEFAULT_RFC_TX_DNL_PGA \
+ UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_CAP_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_PGA_BIAS_B##BAND_ID \
+ } \
+}
+
+#else
+
+#define M_UL1D_DEFAULT_RFC_B(BAND_ID) \
+{ \
+ VERNO_B##BAND_ID \
+ UMTSBand##BAND_ID, \
+ { \
+ UL1D_DEFAULT_RFC_RX_IRR_HPM \
+ UL1D_DEFAULT_RFC_RX_IRR_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+ UL1D_DEFAULT_RFC_RX_IIP2 \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_MRX_CDCOC \
+ UL1D_DEFAULT_RFC_MRX_CDCOC \
+ UL1D_DEFAULT_RFC_MRX_IQ_B##BAND_ID \
+ UL1D_DEFAULT_RFC_MRX_DC \
+ UL1D_DEFAULT_RFC_MRX_DC \
+ UL1D_DEFAULT_RFC_MRX_DNL \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_PGA \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_TZA \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_TX_LPF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_RCF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_CDCOC \
+ UL1D_DEFAULT_RFC_TX_IQ_DC \
+ UL1D_DEFAULT_RFC_TX_DNL_PGA \
+ UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_CAP_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_PGA_BIAS_B##BAND_ID \
+ } \
+}
+#endif/*IS_URF_RXDC_GXE_SUPPORT*/
+
+#endif /*__UL1D_RFC_DATA_MT6186_H__*/
+
+/* Doxygen Group End ***************************************************//**@}*/
diff --git a/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6186m.h b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6186m.h
new file mode 100644
index 0000000..d554fe4
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_mt6186m.h
@@ -0,0 +1,1600 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygen Group Header ****************************************************//**
+ * @addtogroup UL1D_RF_CUSTOM_DATA
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @file ul1d_rf_cal_poc_data.h
+ * @author Neil Chung(MTK08266)
+ * @date 2015.01.26
+ * @brief UL1D RF POC SHM data header file
+ * @details Provide RF POC data structure for PCORE and L1CORE (SHM)
+ ******************************************************************************/
+
+#ifndef __UL1D_RFC_DATA_MT6186M_H__
+#define __UL1D_RFC_DATA_MT6186M_H__
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "mml1_rf_cal_def.h"
+
+/*******************************************************************************
+ * Typedef
+ ******************************************************************************/
+/** Structure Prototypes can be seen by other files */
+typedef enum
+{
+ UMTSBandNone = 0,
+ UMTSBand1 = 1,
+ UMTSBand2 = 2,
+ UMTSBand3 = 3,
+ UMTSBand4 = 4,
+ UMTSBand5 = 5,
+ UMTSBand6 = 6,
+ UMTSBand7 = 7,
+ UMTSBand8 = 8,
+ UMTSBand9 = 9,
+ UMTSBand10 = 10,
+ UMTSBand11 = 11,
+ UMTSBand12 = 12,
+ UMTSBand13 = 13,
+ UMTSBand14 = 14,
+ UMTSBand15 = 15,
+ UMTSBand16 = 16,
+ UMTSBand17 = 17,
+ UMTSBand18 = 18,
+ UMTSBand19 = 19,
+ UMTSBand20 = 20,
+ UMTSBand21 = 21,
+ UMTSBand22 = 22,
+ UMTSBandcount
+} UMTSBand;
+
+
+/*******************************************************************************
+** RFC dimension define
+*******************************************************************************/
+
+#define UL1D_RXDC_TIA_GAIN_STEPS (4)
+#define UL1D_RXDC_PGA_GAIN_STEPS (7)
+
+#define UL1D_RXDC_HPM_TIA_GAIN_STEPS (UL1D_RXDC_TIA_GAIN_STEPS)
+#define UL1D_RXDC_HPM_PGA_GAIN_STEPS (UL1D_RXDC_PGA_GAIN_STEPS)
+#define UL1D_RXDC_LPM_TIA_GAIN_STEPS (UL1D_RXDC_TIA_GAIN_STEPS)
+#define UL1D_RXDC_LPM_PGA_GAIN_STEPS (UL1D_RXDC_PGA_GAIN_STEPS)
+
+#define UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX (7) /* from MMRFC_RXIRR_FILT_TAPS_NUM */
+#define UL1D_RF_RX_DC_COMP_ROUTE_MAX (1)
+#define UL1D_RF_RX_IRR_COMP_ROUTE_MAX (1)
+#define UL1D_RF_RX_IIP2_COMP_ROUTE_MAX (1)
+
+#define UL1D_RX_CBW_NUM (3 ) /* from MMRFC_UMTS_RX_CBW_NUM */
+#define UL1D_DET_FE_GAIN_STEPS (1 ) /* from MMRFC_DET_FE_GAIN_STEPS */
+#define UL1D_DET_GAIN_STEPS (5 ) /* from MMRFC_DET_GAIN_STEPS */
+#define UL1D_DET_EQLPF_TAP_NUM (13) /* from MMRFC_DET_EQLPF_TAP_NUM */
+#define UL1D_TX_PGA_TYPE_NUM (3 ) /* from MMRFC_TX_PGA_TYPE_NUM */
+#define UL1D_TX_DNL_PGA_A_GAIN_STEPS (22) /* from MMRFC_TX_DNL_PGA_A_GAIN_STEPS */
+#define UL1D_TX_DNL_PGA_B_GAIN_STEPS (0 ) /* from MMRFC_TX_DNL_PGA_B_GAIN_STEPS */
+#define UL1D_TX_DNL_PGA_AUX_GAIN_STEPS (5 ) /* from MMRFC_TX_DNL_PGA_AUX_GAIN_STEPS */
+#define UL1D_TX_PGA_SLICE_NUM (4 ) /* from MMRFC_TX_PGA_SLICE_NUM */
+#define UL1D_TX_PGA_BIAS_NUM (3 ) /* from MMRFC_TX_PGA_BIAS_STEP_NUM */
+#define UL1D_TX_CBW_NUM (2 ) /* from MMRFC_UMTS_TX_CBW_NUM */
+#define UL1D_TX_PGA_GAIN_STEP_NUM (10) /* from MMRFC_TX_PGA_GAIN_STEP_NUM */
+#define UL1D_TX_SUBBAND_NUM (3 ) /* from MMRFC_TX_SUBBAND_NUM */
+#define UL1D_ANT_NUM (2 ) /* from MMRFC_ANT_NUM */
+
+#define UL1D_TX_PGA_CAP_TUNING_SUBBAND_NUM (UL1D_TX_SUBBAND_NUM)/* from MMRFC_TX_PGA_CAP_TUNING_SUBBAND_NUM */
+#define UL1D_TX_DNL_PGA_TOTAL_NUM (UL1D_TX_DNL_PGA_A_GAIN_STEPS + UL1D_TX_DNL_PGA_B_GAIN_STEPS + UL1D_TX_DNL_PGA_AUX_GAIN_STEPS)
+
+
+/******************************
+* Rx POC Part
+*******************************/
+typedef struct
+{
+ kal_int8 gain_est_hw;
+ kal_int8 phase_est_hw;
+ kal_int16 freq_dep_filt[UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX];
+} UMTS_RF_POC_RX_IRR_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_RX_DC_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_HPM_TIA_GAIN_STEPS][UL1D_RXDC_HPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_HPM_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_LPM_TIA_GAIN_STEPS][UL1D_RXDC_LPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_LPM_COMP_T;
+
+typedef struct
+{
+ kal_int8 gate_bias_i;
+ kal_int8 gate_bias_q;
+} UMTS_RF_POC_RX_IIP2_COMP_T;
+
+typedef struct
+{
+ /* RX IRR */
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_hpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_lpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+
+ /* RX DC */
+ #if IS_URF_RXDC_GXE_SUPPORT
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_rf_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_rf_dc_hpm_gxe[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_rf_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_rf_dc_lpm_gxe[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dig_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dig_dc_hpm_gxe[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dig_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dig_dc_lpm_gxe[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ #else
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_rf_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_rf_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dig_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dig_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ #endif
+
+ /* RX IIP2 */
+ UMTS_RF_POC_RX_IIP2_COMP_T rx_iip2[UL1D_ANT_NUM][UL1D_RF_RX_IIP2_COMP_ROUTE_MAX];
+
+} UMTS_RF_POC_RX_COMP_DATA_T;
+
+
+/******************************
+* Tx DET POC Part
+*******************************/
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+
+} UMTS_DET_EQLPF_COMP_T;
+
+typedef struct
+{
+ UMTS_DET_EQLPF_COMP_T coef[UL1D_DET_EQLPF_TAP_NUM];
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+} UMTS_DET_FDADPCB_EQLPF_COMP_T;
+
+typedef struct{
+ kal_int8 dummy;
+ kal_int8 phase_est_hw; //FIIQ phase
+ UMTS_DET_FDADPCB_EQLPF_COMP_T fd_ad_pcb; //FDIQ, AD coefficient, 3G do not contain PCB information
+} UMTS_RF_POC_DET_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_DET_DC_COMP_T;
+
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoc_i;
+ kal_uint32 mrx_cdcoc_q;
+}
+UMTS_RF_POC_MRX_CDCOC_PGA_T;
+
+typedef struct
+{
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_pos_15_db;
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_pos_09_db;
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_pos_03_db;
+ UMTS_RF_POC_MRX_CDCOC_PGA_T pga_neg_03_db;
+}
+UMTS_RF_POC_MRX_COARSE_DC_T;
+
+
+
+typedef struct
+{
+ /* DET Coarse DCOC */
+ /*
+ Trinity TX Calibrations V1.1 Draft.docx
+ 5.1 MRX Coarse DC-offset Calibration (ES2 Approach)
+
+ We need to calibrate PGA = 15dB, PGA = 9dB, PGA = 3dB, and -3dB.
+ We need to calibrate the TX-loopback and the antenna-loopback separately.
+ DPD also uses PGA gain -9dB, but that PGA gain can reuse the -3dB calibration.
+
+ det_cdcoc[0]: PGA = 15dB --> CW939 : TX1_MRX_CDCOC_I/Q1[4:0]
+ det_cdcoc[0]: PGA = 15dB --> CW1006: TX0_MRX_CDCOC_I/Q1[4:0]
+
+ det_cdcoc[1]: PGA = 9dB --> CW939 : TX1_MRX_CDCOC_I/Q2[4:0]
+ det_cdcoc[1]: PGA = 9dB --> CW1006: TX0_MRX_CDCOC_I/Q2[4:0]
+
+ det_cdcoc[2]: PGA = 3dB --> CW940 : TX1_MRX_CDCOC_I/Q3[4:0]
+ det_cdcoc[2]: PGA = 3dB --> CW1007: TX0_MRX_CDCOC_I/Q3[4:0]
+
+ det_cdcoc[3]: PGA = -3dB --> CW940 : TX1_MRX_CDCOC_I/Q4[4:0]
+ det_cdcoc[3]: PGA = -3dB --> CW1007: TX0_MRX_CDCOC_I/Q4[4:0]
+ */
+ UMTS_RF_POC_MRX_COARSE_DC_T det_cdcoc;
+ UMTS_RF_POC_MRX_COARSE_DC_T det_cdcoc_tx_lb;
+
+ /* DET IQ/DC/DNL Forward */
+ UMTS_RF_POC_DET_IQ_COMP_T det_iq_fwd[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_fwd[UL1D_DET_GAIN_STEPS];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_fwd_tx_lb[UL1D_DET_GAIN_STEPS];
+ kal_int16 det_dnl_fwd[UL1D_DET_GAIN_STEPS];
+
+ kal_int16 mrx_ctune_pga[2/*MMRFC_MRX_PGA_TZA_BW_CNT*/];
+ kal_int16 mrx_ctune_tza[2/*MMRFC_MRX_PGA_TZA_BW_CNT*/];
+
+} UMTS_RF_POC_DET_COMP_DATA_T;
+
+/******************************
+* Tx FOWRAD POC Part
+*******************************/
+typedef struct{
+ kal_int8 gain_est;
+ kal_int8 phase_est;
+} UMTS_RF_POC_TX_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_TX_DC_COMP_T;
+
+typedef struct
+{
+
+ /* TX LPF*/
+ kal_int16 tx_lpf_abb_rsel;
+ kal_int16 tx_lpf_abb_csel_1;
+ kal_int16 tx_lpf_abb_csel_2;
+
+ /* TX RCF*/
+ kal_int16 tx_rcf_rsel;
+ kal_int16 tx_rcf_csel_4a;
+ kal_int16 tx_rcf_csel_1b;
+ kal_int16 tx_rcf_csel_2a;
+
+ /* TX CDCOC */
+ /*
+ Trinity TX Calibrations Table V1.1 Draft.xlsx
+ 1) Coarse DC offset compensator located in DAC IP (modem). Compensation changes with # of slices (gain word).
+ 2) Requires recalibration per RAT because of changes in R used in ABB. RAT's using same R can reuse calibration
+ 3) Requires L1 and CSD support
+
+ per ABB slice CM: 4A, 2A, 1A, 1B
+ */
+ UMTS_RF_POC_TX_DC_COMP_T tx_cdcoc[UL1D_TX_PGA_SLICE_NUM];
+
+ /* TX FIIQ/DC/DNL Linear Mode */
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_lin[UL1D_TX_PGA_SLICE_NUM];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_lin[UL1D_TX_PGA_SLICE_NUM];
+
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_dpd[UL1D_TX_PGA_SLICE_NUM];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_dpd[UL1D_TX_PGA_SLICE_NUM];
+
+ kal_int16 tx_dnl_lin_pga_a[UL1D_TX_DNL_PGA_TOTAL_NUM];
+
+ /* TX PGA Phase Step */
+ kal_int32 tx_mod_slice_phase[UL1D_TX_PGA_SLICE_NUM/*Slice: 0:4A, 1:2A, 2:1A, 3:AUX*/];
+
+ /* TX PGA Cap Tuning */
+ kal_uint32 cap_opt_a;
+ kal_uint32 tx_drv_ctunemod;
+
+ /* TX PGA BIAS: 4 calibrated BMA_CAL<7:0> codes */
+ /* 3 BMA values used for different number of PGA slices (4/2/1)*/
+ /* 1 additional BMA value used in DPD mode. The latter is never used in practice*/
+ /* A60864_TX_Programming_Guide_v1p0.docx
+ 4.3.1 PGA Bias Calibration programming
+
+ CW888: TX1_PGABIAS_BMA1_DEF[7:0]-->PGABIAS BMA4 gain lookup default-->DPD
+ CW888: TX1_PGABIAS_BMA2_DEF[7:0]-->PGABIAS BMA3 gain lookup default-->1 Slice
+ CW887: TX1_PGABIAS_BMA3_DEF[7:0]-->PGABIAS BMA2 gain lookup default-->2 Slices
+ CW887: TX1_PGABIAS_BMA4_DEF[7:0]-->PGABIAS BMA1 gain lookup default-->4 Slices
+
+ CW955: TX0_PGABIAS_BMA1_DEF[7:0]-->PGABIAS BMA4 gain lookup default-->DPD
+ CW955: TX0_PGABIAS_BMA2_DEF[7:0]-->PGABIAS BMA3 gain lookup default-->1 Slice
+ CW954: TX0_PGABIAS_BMA3_DEF[7:0]-->PGABIAS BMA2 gain lookup default-->2 Slices
+ CW954: TX0_PGABIAS_BMA4_DEF[7:0]-->PGABIAS BMA2 gain lookup default-->4 Slices
+ */
+ kal_int32 tx_pga_bias[UL1D_TX_PGA_BIAS_NUM/* Slice: 0:4A, 1:2A, 2:1A */];
+
+} UMTS_RF_POC_TX_COMP_DATA_T;
+
+typedef struct
+{
+ kal_uint32 verno;
+ UMTSBand band;
+ UMTS_RF_POC_RX_COMP_DATA_T umts_rx_comp;
+ UMTS_RF_POC_DET_COMP_DATA_T umts_det_comp;
+ UMTS_RF_POC_TX_COMP_DATA_T umts_tx_comp;
+} UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T;
+
+
+/*******************************************************************************
+** Macro define for POC default value
+*******************************************************************************/
+
+
+/*Trinity_RX_Programming_Guide_0p1_20170607 */
+/*Table 4-3 DCOC Mapping Table */
+/*Offset Voltage(V) = 0V, DCOC[5:0] = 6'b100000 */
+
+#define UMTS_RXDC_RF_I_Default (0xFFE0)
+#define UMTS_RXDC_RF_Q_Default (0xFFE0)
+#define UMTS_RXDC_Dig_I_Default (0)
+#define UMTS_RXDC_Dig_Q_Default (0)
+
+#define UMTS_RXDC_RF_IQ_Default \
+{\
+ UMTS_RXDC_RF_I_Default, UMTS_RXDC_RF_Q_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_Default \
+{\
+ UMTS_RXDC_Dig_I_Default,\
+ UMTS_RXDC_Dig_Q_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default,\
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default \
+{\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default \
+{\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+}
+
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default \
+{\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default \
+{\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+}
+
+
+
+#define UMTS_RXDC_RF_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_RF_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+#define UMTS_RX_IRR_TAP_DEFAULT \
+{ \
+ /*ANT0*/{0,0,{0,0,0,1024,0,0,0}}, \
+ /*ANT1*/{0,0,{0,0,0,1024,0,0,0}}, \
+}
+
+#define UMTS_RX_IIP2_I_DEFAULT (64)
+#define UMTS_RX_IIP2_Q_DEFAULT (64)
+#define UMTS_RX_IIP2_DEFAULT {UMTS_RX_IIP2_I_DEFAULT, UMTS_RX_IIP2_Q_DEFAULT}
+
+/*
+Manel:
+Please note that the table shows the phase change introduced by RF.
+The DFE compensation must have the opposite sign than what is shown on the table.
+*/
+
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_4_to_2 (-14 ) // 2.5x(-1)x1024/180
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_2_to_1 (-4 ) // 0.7x(-1)x1024/180
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_4_to_1 (0 ) // NOT defined
+#define UMTS_TX_LB_PHASE_SLICE_CHANGE_1_to_AUX (11 ) // -2x(-1)x1024/180
+
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_4_to_2 (-40 ) // 7x(-1)x1024/180
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_2_to_1 (-57 ) // 10x(-1)x1024/180
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_4_to_1 (0 ) // NOT defined
+#define UMTS_TX_MB_PHASE_SLICE_CHANGE_1_to_AUX (11 ) // -2x(-1)x1024/180
+
+#define UMTS_TX_PHASE_LB_4A_DEFAULT (0)
+#define UMTS_TX_PHASE_LB_2A_DEFAULT (UMTS_TX_PHASE_LB_4A_DEFAULT+UMTS_TX_LB_PHASE_SLICE_CHANGE_4_to_2)
+#define UMTS_TX_PHASE_LB_1A_DEFAULT (UMTS_TX_PHASE_LB_2A_DEFAULT+UMTS_TX_LB_PHASE_SLICE_CHANGE_2_to_1)
+#define UMTS_TX_PHASE_LB_AUX_DEFAULT (UMTS_TX_PHASE_LB_1A_DEFAULT+UMTS_TX_LB_PHASE_SLICE_CHANGE_1_to_AUX)
+
+
+#define UMTS_TX_PHASE_MB_4A_DEFAULT (0)
+#define UMTS_TX_PHASE_MB_2A_DEFAULT (UMTS_TX_PHASE_MB_4A_DEFAULT+UMTS_TX_MB_PHASE_SLICE_CHANGE_4_to_2)
+#define UMTS_TX_PHASE_MB_1A_DEFAULT (UMTS_TX_PHASE_MB_2A_DEFAULT+UMTS_TX_MB_PHASE_SLICE_CHANGE_2_to_1)
+#define UMTS_TX_PHASE_MB_AUX_DEFAULT (UMTS_TX_PHASE_MB_1A_DEFAULT+UMTS_TX_MB_PHASE_SLICE_CHANGE_1_to_AUX)
+
+
+/*95_TxDFERF_TxK_default_settings_20171027.xlsx*/
+#define UMTS_DET_IQ_PHASE_EST_HW_DEFAULT (0)/*phase_est_hw: DET_FI (S-4.10.9) POC*/
+
+#define UMTS_DET_IQ_EQLPF_I_SCALE_DEFAULT (1)/*scale_i: DET_EQLPF_I_SCALE (U2.0)*/
+
+#define UMTS_DET_IQ_EQLPF_Q_SCALE_DEFAULT (1)/*scale_q: DET_EQLPF_Q_SCALE (U2.0)*/
+
+#define UMTS_DET_IQ_EQ_COEF_DEFAULT \
+{ \
+ { 4, 4},/*coef[00]: DET_EQLPF_I_C00, DET_EQLPF_Q_C00*/ \
+ { -22, -22},/*coef[01]: DET_EQLPF_I_C01, DET_EQLPF_Q_C01*/ \
+ { 74, 74},/*coef[02]: DET_EQLPF_I_C02, DET_EQLPF_Q_C02*/ \
+ { -186, -186},/*coef[03]: DET_EQLPF_I_C03, DET_EQLPF_Q_C03*/ \
+ { 417, 417},/*coef[04]: DET_EQLPF_I_C04, DET_EQLPF_Q_C04*/ \
+ {-1021,-1021},/*coef[05]: DET_EQLPF_I_C05, DET_EQLPF_Q_C05*/ \
+ { 3513, 3513},/*coef[06]: DET_EQLPF_I_C06, DET_EQLPF_Q_C06*/ \
+ {-1010,-1010},/*coef[07]: DET_EQLPF_I_C07, DET_EQLPF_Q_C07*/ \
+ { 401, 401},/*coef[08]: DET_EQLPF_I_C08, DET_EQLPF_Q_C08*/ \
+ { -171, -171},/*coef[09]: DET_EQLPF_I_C09, DET_EQLPF_Q_C09*/ \
+ { 65, 65},/*coef[10]: DET_EQLPF_I_C10, DET_EQLPF_Q_C10*/ \
+ { -18, -18},/*coef[11]: DET_EQLPF_I_C11, DET_EQLPF_Q_C11*/ \
+ { 3, 3} /*coef[12]: DET_EQLPF_I_C12, DET_EQLPF_Q_C12*/ \
+}
+
+
+/*95_TxDFERF_TxK_default_settings_20171027.xlsx*/
+#define UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+ UMTS_DET_IQ_PHASE_EST_HW_DEFAULT, \
+ { /* fd_ad_pcb: */ \
+ UMTS_DET_IQ_EQ_COEF_DEFAULT, \
+ UMTS_DET_IQ_EQLPF_I_SCALE_DEFAULT, \
+ UMTS_DET_IQ_EQLPF_Q_SCALE_DEFAULT \
+ }
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_BNone \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B1 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B2 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B3 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B4 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B5 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B6 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B8 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B9 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B11 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B18 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_Det_Iq_MG_SC_Comp_Default_B19 \
+{ \
+ 0, \
+ UMTS_DET_IQ_PHASE_AND_EQ_COEF_DEFAULT \
+}
+
+#define UMTS_DET_IQ_MG_DFAULT_BNone \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_BNone,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_BNone,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B1 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B1,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B1,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B2 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B2,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B2,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B3 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B3,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B3,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B4 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B4,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B4,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B5 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B5,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B5,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B6 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B6,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B6,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B8 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B8,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B8,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B9 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B9,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B9,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B11 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B11,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B11,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B18 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B18,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B18,\
+},
+
+#define UMTS_DET_IQ_MG_DFAULT_B19 \
+{ /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default_B19,\
+ UMTS_Det_Iq_MG_SC_Comp_Default_B19,\
+},
+
+
+#define UMTS_DET_DC_DEFAULT {0/*DC_I*/, 0/*DC_Q*/}
+
+
+// RX
+//============================================================
+#define UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+{ \
+ UMTS_RXDC_RF_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+{ \
+ UMTS_RXDC_RF_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+{ \
+ UMTS_RXDC_Dig_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+{ \
+ UMTS_RXDC_Dig_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_IRR_HPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 1, HPM*/ \
+ { \
+ /*SC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*DC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*3C*/UMTS_RX_IRR_TAP_DEFAULT \
+ }, \
+},
+
+#define UL1D_DEFAULT_RFC_RX_IRR_LPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 1, LPM*/ \
+ { \
+ /*SC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*DC*/UMTS_RX_IRR_TAP_DEFAULT, \
+ /*3C*/UMTS_RX_IRR_TAP_DEFAULT \
+ }, \
+},
+
+
+#define UL1D_DEFAULT_RFC_RX_IIP2 \
+{ \
+ { /*RXP*/ \
+ UMTS_RX_IIP2_DEFAULT,/*ROUTE00*/ \
+ }, \
+ { /*RXD*/ \
+ UMTS_RX_IIP2_DEFAULT,/*ROUTE00*/ \
+ } \
+},
+
+
+//DET
+//============================================================
+
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_BNone \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_BNone \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B1 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B1 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B2 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B2 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B3 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B3 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B4 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B4 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B5 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B5 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B6 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B6 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B8 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B8 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B9 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B9 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B11 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B11 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B18 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B18 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_IQ_B19 \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DFAULT_B19 \
+ },
+
+#define UL1D_DEFAULT_RFC_MRX_DC \
+ { /* UL1D_DET_GAIN_STEPS = 5*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG00*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG01*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG02*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG03*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG04*/ \
+ },
+
+/* B60864A_BBBM_TABLE.xlsx */
+/* sheet: MRX0_GAIN & MRX1_GAIN */
+/* MRX Gain*/
+#define UL1D_DEFAULT_RFC_MRX_DNL \
+{ \
+ 384, /* G0: 12 dB*/ \
+ 192, /* G1: 6 dB*/ \
+ 0, /* G2: 0 dB*/ \
+ -192, /* G3: -6 dB*/ \
+ -384, /* G4: -12 dB*/ \
+},
+
+
+#define UL1D_DEFAULT_RFC_MRX_CDCOC_PGA \
+{ \
+ /* mrx_cdcoc_i */0, \
+ /* mrx_cdcoc_q */0 \
+}
+
+
+#define UL1D_DEFAULT_RFC_MRX_CDCOC \
+{ \
+ /* pga_pos_15_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA, \
+ /* pga_pos_09_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA, \
+ /* pga_pos_03_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA, \
+ /* pga_neg_03_db */UL1D_DEFAULT_RFC_MRX_CDCOC_PGA \
+},
+
+
+
+/*
+ A60827_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+ CW718[D07:D00] RG_TX1_MRX_PGA_CTUNE[7:0] = 0x3C
+ CW718[D15:D08] RG_TX1_MRX_TZA_CTUNE[7:0] = 0x18
+ CW738[D07:D00] RG_TX0_MRX_PGA_CTUNE[7:0] = 0x3C
+ CW738[D15:D08] RG_TX0_MRX_TZA_CTUNE[7:0] = 0x18
+*/
+
+#define UL1D_DEFAULT_RFC_MRX_CTUNE_PGA \
+{ \
+ /* MMRFC_MRX_PGA_TZA_BW_22P5 */0x3C,\
+ /* MMRFC_MRX_PGA_TZA_BW_67P5 */0x3C \
+},
+
+#define UL1D_DEFAULT_RFC_MRX_CTUNE_TZA \
+{ \
+ /* MMRFC_MRX_PGA_TZA_BW_22P5 */0x18,\
+ /* MMRFC_MRX_PGA_TZA_BW_67P5 */0x18 \
+},
+
+
+//TX
+//============================================================
+
+
+/*DOC : Trinity-L TX Gain Table V3.0 Released.xlsx */
+/*Sheet: Gain Tables */
+/*Table: LB & MB & HB_UHB */
+
+#define UL1D_DEFAULT_RFC_TX_DNL_PGA \
+{ \
+ 0 , /* G0 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = 0.00 dB */ \
+ -18 , /* G1 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -0.56 dB */ \
+ -37 , /* G2 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -1.16 dB */ \
+ -58 , /* G3 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -1.80 dB */ \
+ -80 , /* G4 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -2.50 dB */ \
+ -104 , /* G5 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -3.25 dB */ \
+ -131 , /* G6 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -4.08 dB */ \
+ -160 , /* G7 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -4.99 dB */ \
+ -193 , /* G8 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -6.02 dB */ \
+ -230 , /* G9 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -7.18 dB */ \
+ -273 , /* G10 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -8.52 dB */ \
+ -323 , /* G11 , A , ABB MOD LO Slice = 4, PGA Slice = 4, Gain = -10.10dB */ \
+ -366 , /* G12 , A , ABB MOD LO Slice = 2, PGA Slice = 4, Gain = -11.43dB */ \
+ -468 , /* G13 , A , ABB MOD LO Slice = 2, PGA Slice = 2, Gain = -14.62dB */ \
+ -526 , /* G14 , A , ABB MOD LO Slice = 1, PGA Slice = 4, Gain = -16.45dB */ \
+ -621 , /* G15 , A , ABB MOD LO Slice = 1, PGA Slice = 2, Gain = -19.40dB */ \
+ -734 , /* G16 , A , ABB MOD LO Slice = 1, PGA Slice = 2, Gain = -22.93dB */ \
+ -853 , /* G17 , A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -26.67dB */ \
+ -988 , /* G18 , A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -30.89dB */ \
+ -1181, /* G19 , A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -36.91dB */ \
+ -1374, /* G20 , A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -42.93dB */ \
+ -1566, /* G21 , A , ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -48.95dB */ \
+ -1759, /* G22 , AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -54.97dB */ \
+ -1952, /* G23 , AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -60.99dB */ \
+ -2144, /* G24 , AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -67.01dB */ \
+ -1759, /* G25DNL, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -54.97dB */ \
+ -1952 /* G26DNL, AUX, ABB MOD LO Slice = 1, PGA Slice = 1, Gain = -60.99dB */ \
+},
+
+#define UL1D_DEFAULT_RFC_TX_IQ_DC \
+ /*tx_iq_lin*/{{0,0}}, \
+ /*tx_dc_lin*/{{0,0}}, \
+ /*tx_iq_dpd*/{{0,0}}, \
+ /*tx_dc_dpd*/{{0,0}},
+
+#define UL1D_DEFAULT_RFC_TX_CDCOC \
+ { \
+ /*tx_cdcoc[0:MMRFC_TX_ABB_SLICE_CAL_4A ]*/{/*dc_i*/0,/*dc_q*/0}, \
+ /*tx_cdcoc[1:MMRFC_TX_ABB_SLICE_CAL_2A ]*/{/*dc_i*/0,/*dc_q*/0}, \
+ /*tx_cdcoc[2:MMRFC_TX_ABB_SLICE_CAL_1A ]*/{/*dc_i*/0,/*dc_q*/0}, \
+ /*tx_cdcoc[3:MMRFC_TX_ABB_SLICE_CAL_AUX]*/{/*dc_i*/0,/*dc_q*/0} \
+ },
+
+/* TX LPF*/
+/* ==============================================================================
+
+ A60864_TX_Programming_Guide_v1p0.docx,
+ - 3.7 Bandwidth control, Table 3 15 3G Filter Configurations: LPF_6P8M/CW719/CW739
+ - 3.7.1 ABB BW Controls, Table 3 18 ABB RC Controls: TX0_BBBM10 & TX1_BBBM10
+ Trinity_L_divider_table_v0d1_20170922_1012temporary_L1.xlsx
+ Sheet: 1RX_1TX
+ Band TX Path
+ 1 1
+ 2 1
+ 3 1
+ 4 1
+ 5 0
+ 6 0
+ 7 1
+ 8 0
+ 9 1
+ 10 1
+ 11 1
+ 12 0
+ 13 0
+ 14 0
+ 15 0
+ 17 0
+ 18 0
+ 19 0
+
+ A10787A_BBBM_TABLE.xlsx
+ sheet: TX0 & TX0_LPF
+
+
+ CW739 TX0_BBBM10 TX0_ABB_CSEL1/2[7:0] TX0_ABB_RSEL [1:0]
+ CW719 TX1_BBBM10 TX1_ABB_CSEL1/2[7:0] TX1_ABB_RSEL [1:0] --> 2 bits
+ CW890 TX1_ABBMAN1 TX1_ABB_CSEL1_M[7:0] -------------------
+ TX1_ABB_CSEL2_M[7:0] -------------------
+ CW957 TX2_ABBMAN1 TX2_ABB_CSEL1_M[7:0] -------------------
+ TX2_ABB_CSEL2_M[7:0] -------------------
+ CW891 TX1_ABBMAN2 -------------------- TX1_ABB_RSEL_M[3:0] --> 4 bits ?
+ CW958 TX2_ABBMAN2 -------------------- TX2_ABB_RSEL_M[3:0]
+
+ |Band | Path | Mode | TX0/1_ABB_CSEL1[7:0]| TX0/1_ABB_CSEL2[7:0]| TX0/1_ABB_RSEL[1:0]|
+ |-------------|---------|------------|---------------------|---------------------|--------------------|
+ |3G_FDD_Band01| 0 |LPF_6P8M | 0xB6 | 0xB6 | 0x2 |
+ |3G_FDD_Band02| 0 |LPF_6P8M | 0xB6 | 0xB6 | 0x2 |
+ |3G_FDD_Band03| 0 |LPF_6P8M | 0xB6 | 0xB6 | 0x2 |
+ |3G_FDD_Band04| 0 |LPF_6P8M | 0xB6 | 0xB6 | 0x2 |
+ |3G_FDD_Band05| 0 |LPF_6P8M | 0xB6 | 0xB6 | 0x2 |
+ |3G_FDD_Band06| 0 |LPF_6P8M | 0xB6 | 0xB6 | 0x2 |
+ |3G_FDD_Band08| 0 |LPF_6P8M | 0xB6 | 0xB6 | 0x2 |
+ |3G_FDD_Band09| 0 |NOT SUPPORT | 0xB6 | 0xB6 | 0x2 |
+ |3G_FDD_Band11| 0 |LPF_6P8M | 0xB6 | 0xB6 | 0x2 |
+ |3G_FDD_Band18| 0 |NOT SUPPORT | 0xB6 | 0xB6 | 0x2 |
+ |3G_FDD_Band19| 0 |LPF_6P8M | 0xB6 | 0xB6 | 0x2 |
+
+ ======================================================================================================*/
+
+#define UL1D_DEFAULT_RFC_TX_LPF_BNone \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B1 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B2 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B3 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B4 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B5 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B6 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B8 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B9 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B11 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B18 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B19 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xB6, \
+ /*tx_lpf_abb_csel_2*/ 0xB6,
+
+
+/* TX RCF*/
+/*
+ Rel_0914
+ A10787A_BBBM_TABLE.xlsx
+
+ |Band | Path | Mode:TX0 | RG_TX0_RCF_RSEL[7:0]|TX0_RCF_CSEL_4[7:0]| TX0_RCF_CSEL_1[7:0] | TX0_RCF_CSEL_2[7:0]|
+ |--------------|-------|-----------------|---------------------|------------------ |----------------------|---------------------|
+ |3G_FDD_Band01 | 0 | RCF_MB1_16M | 0x2A | 0x25 | 0x2C | 0x29 |
+ |3G_FDD_Band02 | 0 | RCF_MB2_16M | 0x2F | 0x29 | 0x30 | 0x2D |
+ |3G_FDD_Band03 | 0 | RCF_MB3_16M | 0x37 | 0x31 | 0x38 | 0x35 |
+ |3G_FDD_Band04 | 0 | RCF_MB3_16M | 0x37 | 0x31 | 0x38 | 0x35 |
+ |3G_FDD_Band05 | 0 | RCF_LB2_16M | 0x21 | 0x20 | 0x27 | 0x24 |
+ |3G_FDD_Band06 | 0 | RCF_LB2_16M | 0x21 | 0x20 | 0x27 | 0x24 |
+ |3G_FDD_Band08 | 0 | RCF_LB1_16M | 0x1C | 0x1F | 0x26 | 0x23 |
+ |3G_FDD_Band09 | 0 | RCF_MB3_16M | 0x37 | 0x31 | 0x38 | 0x35 |
+ |3G_FDD_Band11 | 0 | RCF_MB4_16M | 0x25 | 0x31 | 0x38 | 0x35 |
+ |3G_FDD_Band18 | 0 | RCF_LB3_16M | 0x23 | 0x22 | 0x29 | 0x26 |
+ |3G_FDD_Band19 | 0 | RCF_LB2_16M | 0x21 | 0x20 | 0x27 | 0x24 |
+*/
+
+#define UL1D_DEFAULT_RFC_TX_RCF_BNone \
+ /*tx_rcf_rsel */ 0x2A, \
+ /*tx_rcf_csel_4a */ 0x25, \
+ /*tx_rcf_csel_1b */ 0x2C, \
+ /*tx_rcf_csel_2a */ 0x29,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B1 \
+ /*tx_rcf_rsel */ 0x2A, \
+ /*tx_rcf_csel_4a */ 0x25, \
+ /*tx_rcf_csel_1b */ 0x2C, \
+ /*tx_rcf_csel_2a */ 0x29,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B2 \
+ /*tx_rcf_rsel */ 0x2F, \
+ /*tx_rcf_csel_4a */ 0x29, \
+ /*tx_rcf_csel_1b */ 0x30, \
+ /*tx_rcf_csel_2a */ 0x2D,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B3 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x31, \
+ /*tx_rcf_csel_1b */ 0x38, \
+ /*tx_rcf_csel_2a */ 0x35,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B4 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x31, \
+ /*tx_rcf_csel_1b */ 0x38, \
+ /*tx_rcf_csel_2a */ 0x35,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B5 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x20, \
+ /*tx_rcf_csel_1b */ 0x27, \
+ /*tx_rcf_csel_2a */ 0x24,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B6 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x20, \
+ /*tx_rcf_csel_1b */ 0x27, \
+ /*tx_rcf_csel_2a */ 0x24,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B8 \
+ /*tx_rcf_rsel */ 0x1C, \
+ /*tx_rcf_csel_4a */ 0x1F, \
+ /*tx_rcf_csel_1b */ 0x26, \
+ /*tx_rcf_csel_2a */ 0x23,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B9 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x31, \
+ /*tx_rcf_csel_1b */ 0x38, \
+ /*tx_rcf_csel_2a */ 0x35,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B11 \
+ /*tx_rcf_rsel */ 0x25, \
+ /*tx_rcf_csel_4a */ 0x31, \
+ /*tx_rcf_csel_1b */ 0x38, \
+ /*tx_rcf_csel_2a */ 0x35,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B18 \
+ /*tx_rcf_rsel */ 0x23, \
+ /*tx_rcf_csel_4a */ 0x22, \
+ /*tx_rcf_csel_1b */ 0x29, \
+ /*tx_rcf_csel_2a */ 0x26,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B19 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x20, \
+ /*tx_rcf_csel_1b */ 0x27, \
+ /*tx_rcf_csel_2a */ 0x24,
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_BNone \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT, \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B1 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT, \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B2 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT, \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B3 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT, \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B4 \
+{ \
+ UMTS_TX_PHASE_MB_4A_DEFAULT, \
+ UMTS_TX_PHASE_MB_2A_DEFAULT, \
+ UMTS_TX_PHASE_MB_1A_DEFAULT, \
+ UMTS_TX_PHASE_MB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B5 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B6 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B8 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B9 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B11 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B18 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B19 \
+{ \
+ UMTS_TX_PHASE_LB_4A_DEFAULT, \
+ UMTS_TX_PHASE_LB_2A_DEFAULT, \
+ UMTS_TX_PHASE_LB_1A_DEFAULT, \
+ UMTS_TX_PHASE_LB_AUX_DEFAULT \
+},
+
+
+/*
+ A10787A_BBBM_TABLE.xlsx Rel_0831
+ Sheet: TX0
+ ---------------------------------------------------------------------------
+ | | | CW726[D19~D12]: | CW726[D11~D4]: |
+ |Band | Path | RG_TX0_DRV_CTUNEMOD[7:0] | RG_TX0_PGA_CTUNE[7:0] |
+ |--------------|------|---------------------------|-----------------------|
+ |3G_FDD_Band01 | 0 | 0x0B | 0x13 |
+ |3G_FDD_Band02 | 0 | 0x0F | 0x16 |
+ |3G_FDD_Band03 | 0 | 0x15 | 0x1A |
+ |3G_FDD_Band04 | 0 | 0x16 | 0x1B |
+ |3G_FDD_Band05 | 0 | 0x11 | 0x0E |
+ |3G_FDD_Band06 | 0 | 0x11 | 0x0E |
+ |3G_FDD_Band08 | 0 | 0x0D | 0x0C |
+ |3G_FDD_Band09 | 0 | 0x15 | 0x1A |
+ |3G_FDD_Band11 | 0 | 0x37 | 0x32 |
+ |3G_FDD_Band18 | 0 | 0x0A | 0x0B |
+ |3G_FDD_Band19 | 0 | 0x11 | 0x0E |
+ ---------------------------------------------------------------------------
+*/
+
+#define UL1D_DEFAULT_RFC_TX_CAP_BNone \
+ /*cap_opt_a */0, \
+ /*tx_drv_ctunemod*/0,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B1 \
+ /*cap_opt_a */0x13, \
+ /*tx_drv_ctunemod*/0x0B,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B2 \
+ /*cap_opt_a */0x16, \
+ /*tx_drv_ctunemod*/0x0F,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B3 \
+ /*cap_opt_a */0x1A, \
+ /*tx_drv_ctunemod*/0x15,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B4 \
+ /*cap_opt_a */0x1B, \
+ /*tx_drv_ctunemod*/0x16,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B5 \
+ /*cap_opt_a */0x0E, \
+ /*tx_drv_ctunemod*/0x11,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B6 \
+ /*cap_opt_a */0x0E, \
+ /*tx_drv_ctunemod*/0x11,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B8 \
+ /*cap_opt_a */0x0C, \
+ /*tx_drv_ctunemod*/0x0D,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B9 \
+ /*cap_opt_a */0x1A, \
+ /*tx_drv_ctunemod*/0x15,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B11 \
+ /*cap_opt_a */0x32, \
+ /*tx_drv_ctunemod*/0x37,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B18 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B19 \
+ /*cap_opt_a */0x0E, \
+ /*tx_drv_ctunemod*/0x11,
+
+
+/*
+A10787A_BBBM_TABLE.xlsx
+sheet: TX0
+
+TX0_PGABIAS_BMA1_DEF[7:0] --> Slice 4
+TX0_PGABIAS_BMA2_DEF[7:0] --> Slice 2
+TX0_PGABIAS_BMA3_DEF[7:0] --> Slice 1
+
+*/
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_BNone \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0, \
+ /*BMA2 for PGA_SLICE_2A */0, \
+ /*BMA3 for PGA_SLICE_1A */0 \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B1 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x36, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B2 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x36, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B3 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x36, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B4 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x36, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B5 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x58, \
+ /*BMA2 for PGA_SLICE_2A */0x46, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B6 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x58, \
+ /*BMA2 for PGA_SLICE_2A */0x46, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B7 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B8 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x60, \
+ /*BMA2 for PGA_SLICE_2A */0x4C, \
+ /*BMA3 for PGA_SLICE_1A */0x3A \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B9 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x36, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B10 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x3A, \
+ /*BMA3 for PGA_SLICE_1A */0x4C \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B11 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x44, \
+ /*BMA2 for PGA_SLICE_2A */0x36, \
+ /*BMA3 for PGA_SLICE_1A */0x2E \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B18 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x62, \
+ /*BMA2 for PGA_SLICE_2A */0x54, \
+ /*BMA3 for PGA_SLICE_1A */0x3E \
+},
+
+#define UL1D_DEFAULT_RFC_TX_PGA_BIAS_B19 \
+{ \
+ /*BMA1 for PGA_SLICE_4A */0x58, \
+ /*BMA2 for PGA_SLICE_2A */0x46, \
+ /*BMA3 for PGA_SLICE_1A */0x36 \
+},
+
+
+#define VERNO_BNone (0),
+#define VERNO_B1 (0),
+#define VERNO_B2 (0),
+#define VERNO_B3 (0),
+#define VERNO_B4 (0),
+#define VERNO_B5 (0),
+#define VERNO_B6 (0),
+#define VERNO_B8 (0),
+#define VERNO_B9 (0),
+#define VERNO_B11 (0),
+#define VERNO_B18 (0),
+#define VERNO_B19 (0),
+
+#if IS_URF_RXDC_GXE_SUPPORT
+#define M_UL1D_DEFAULT_RFC_B(BAND_ID) \
+{ \
+ VERNO_B##BAND_ID \
+ UMTSBand##BAND_ID, \
+ { \
+ UL1D_DEFAULT_RFC_RX_IRR_HPM \
+ UL1D_DEFAULT_RFC_RX_IRR_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+ UL1D_DEFAULT_RFC_RX_IIP2 \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_MRX_CDCOC \
+ UL1D_DEFAULT_RFC_MRX_CDCOC \
+ UL1D_DEFAULT_RFC_MRX_IQ_B##BAND_ID \
+ UL1D_DEFAULT_RFC_MRX_DC \
+ UL1D_DEFAULT_RFC_MRX_DC \
+ UL1D_DEFAULT_RFC_MRX_DNL \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_PGA \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_TZA \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_TX_LPF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_RCF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_CDCOC \
+ UL1D_DEFAULT_RFC_TX_IQ_DC \
+ UL1D_DEFAULT_RFC_TX_DNL_PGA \
+ UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_CAP_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_PGA_BIAS_B##BAND_ID \
+ } \
+}
+
+#else/*IS_URF_RXDC_GXE_SUPPORT*/
+
+#define M_UL1D_DEFAULT_RFC_B(BAND_ID) \
+{ \
+ VERNO_B##BAND_ID \
+ UMTSBand##BAND_ID, \
+ { \
+ UL1D_DEFAULT_RFC_RX_IRR_HPM \
+ UL1D_DEFAULT_RFC_RX_IRR_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+ UL1D_DEFAULT_RFC_RX_IIP2 \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_MRX_CDCOC \
+ UL1D_DEFAULT_RFC_MRX_CDCOC \
+ UL1D_DEFAULT_RFC_MRX_IQ_B##BAND_ID \
+ UL1D_DEFAULT_RFC_MRX_DC \
+ UL1D_DEFAULT_RFC_MRX_DC \
+ UL1D_DEFAULT_RFC_MRX_DNL \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_PGA \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_TZA \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_TX_LPF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_RCF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_CDCOC \
+ UL1D_DEFAULT_RFC_TX_IQ_DC \
+ UL1D_DEFAULT_RFC_TX_DNL_PGA \
+ UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_CAP_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_PGA_BIAS_B##BAND_ID \
+ } \
+}
+#endif/*IS_URF_RXDC_GXE_SUPPORT*/
+
+#endif /*__UL1D_RFC_DATA_MT6186M_H__*/
+
+/* Doxygen Group End ***************************************************//**@}*/
diff --git a/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_trinitye1.h b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_trinitye1.h
new file mode 100644
index 0000000..75b5f91
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_rf_cal_poc_data_trinitye1.h
@@ -0,0 +1,1204 @@
+/******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+/*==============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================*/
+/* Doxygen Group Header ****************************************************//**
+ * @addtogroup UL1D_RF_CUSTOM_DATA
+ * @{
+ ******************************************************************************/
+/***************************************************************************//**
+ * @file ul1d_rf_cal_poc_data.h
+ * @author Neil Chung(MTK08266)
+ * @date 2015.01.26
+ * @brief UL1D RF POC SHM data header file
+ * @details Provide RF POC data structure for PCORE and L1CORE (SHM)
+ ******************************************************************************/
+
+#ifndef __UL1D_RFC_DATA_TRINITYE1_H__
+#define __UL1D_RFC_DATA_TRINITYE1_H__
+
+/*******************************************************************************
+ * #include
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "mml1_rf_cal_def.h"
+
+
+/*******************************************************************************
+ * Typedef
+ ******************************************************************************/
+/** Structure Prototypes can be seen by other files */
+typedef enum
+{
+ UMTSBandNone = 0,
+ UMTSBand1 = 1,
+ UMTSBand2 = 2,
+ UMTSBand3 = 3,
+ UMTSBand4 = 4,
+ UMTSBand5 = 5,
+ UMTSBand6 = 6,
+ UMTSBand7 = 7,
+ UMTSBand8 = 8,
+ UMTSBand9 = 9,
+ UMTSBand10 = 10,
+ UMTSBand11 = 11,
+ UMTSBand12 = 12,
+ UMTSBand13 = 13,
+ UMTSBand14 = 14,
+ UMTSBand15 = 15,
+ UMTSBand16 = 16,
+ UMTSBand17 = 17,
+ UMTSBand18 = 18,
+ UMTSBand19 = 19,
+ UMTSBand20 = 20,
+ UMTSBand21 = 21,
+ UMTSBand22 = 22,
+ UMTSBandcount
+} UMTSBand;
+
+/*******************************************************************************
+** RFC dimension define
+*******************************************************************************/
+
+#define UL1D_RXDC_TIA_GAIN_STEPS (4)
+#define UL1D_RXDC_PGA_GAIN_STEPS (7)
+
+#define UL1D_RXDC_HPM_TIA_GAIN_STEPS (UL1D_RXDC_TIA_GAIN_STEPS)
+#define UL1D_RXDC_HPM_PGA_GAIN_STEPS (UL1D_RXDC_PGA_GAIN_STEPS)
+#define UL1D_RXDC_LPM_TIA_GAIN_STEPS (UL1D_RXDC_TIA_GAIN_STEPS)
+#define UL1D_RXDC_LPM_PGA_GAIN_STEPS (UL1D_RXDC_PGA_GAIN_STEPS)
+
+#define UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX (7) /* from MMRFC_RXIRR_FILT_TAPS_NUM */
+#define UL1D_RF_RX_DC_COMP_ROUTE_MAX (1)
+#define UL1D_RF_RX_IRR_COMP_ROUTE_MAX (1)
+#define UL1D_RF_RX_IIP2_COMP_ROUTE_MAX (1)
+
+#define UL1D_RX_CBW_NUM (3 ) /* from MMRFC_UMTS_RX_CBW_NUM */
+#define UL1D_DET_FE_GAIN_STEPS (1 ) /* from MMRFC_DET_FE_GAIN_STEPS */
+#define UL1D_DET_GAIN_STEPS (5 ) /* from MMRFC_DET_GAIN_STEPS */
+#define UL1D_DET_EQLPF_TAP_NUM (13) /* from MMRFC_DET_EQLPF_TAP_NUM */
+#define UL1D_TX_PGA_TYPE_NUM (3 ) /* from MMRFC_TX_PGA_TYPE_NUM */
+#define UL1D_TX_DNL_PGA_A_GAIN_STEPS (22) /* from MMRFC_TX_DNL_PGA_A_GAIN_STEPS */
+#define UL1D_TX_DNL_PGA_B_GAIN_STEPS (0 ) /* from MMRFC_TX_DNL_PGA_B_GAIN_STEPS */
+#define UL1D_TX_DNL_PGA_AUX_GAIN_STEPS (5 ) /* from MMRFC_TX_DNL_PGA_AUX_GAIN_STEPS */
+#define UL1D_TX_PGA_SLICE_NUM (4 ) /* from MMRFC_TX_PGA_SLICE_NUM */
+#define UL1D_TX_CBW_NUM (2 ) /* from MMRFC_UMTS_TX_CBW_NUM */
+#define UL1D_TX_PGA_GAIN_STEP_NUM (10) /* from MMRFC_TX_PGA_GAIN_STEP_NUM */
+#define UL1D_TX_SUBBAND_NUM (3 ) /* from MMRFC_TX_SUBBAND_NUM */
+#define UL1D_ANT_NUM (2 ) /* from MMRFC_ANT_NUM */
+
+#define UL1D_TX_PGA_CAP_TUNING_SUBBAND_NUM (UL1D_TX_SUBBAND_NUM)/* from MMRFC_TX_PGA_CAP_TUNING_SUBBAND_NUM */
+#define UL1D_TX_DNL_PGA_TOTAL_NUM (UL1D_TX_DNL_PGA_A_GAIN_STEPS + UL1D_TX_DNL_PGA_B_GAIN_STEPS + UL1D_TX_DNL_PGA_AUX_GAIN_STEPS)
+
+#define UL1D_LB_PHASE_SLICE_CHANGE_4_to_2 (14 ) // 2.5*1024/180
+#define UL1D_LB_PHASE_SLICE_CHANGE_2_to_1 (4 ) // 0.7*1024/180
+#define UL1D_LB_PHASE_SLICE_CHANGE_4_to_1 (18 ) // 3.2*1024/180
+#define UL1D_MB_PHASE_SLICE_CHANGE_4_to_2 (11 ) // 2 *1024/180
+#define UL1D_MB_PHASE_SLICE_CHANGE_2_to_1 (-24) // -4.2*1024/180
+#define UL1D_MB_PHASE_SLICE_CHANGE_4_to_1 (-13) // -2.2*1024/180
+
+#if 0//IS_UL1D_DIMENSION_CHECK_ENABLE
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif/*IS_UL1D_DIMENSION_CHECK_ENABLE*/
+
+/******************************
+* Rx POC Part
+*******************************/
+typedef struct
+{
+ kal_int8 gain_est_hw;
+ kal_int8 phase_est_hw;
+ kal_int16 freq_dep_filt[UMTS_RFC_RXDFE_FDPM_TAPS_NUM_MAX];
+} UMTS_RF_POC_RX_IRR_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_RX_DC_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_HPM_TIA_GAIN_STEPS][UL1D_RXDC_HPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_HPM_COMP_T;
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_COMP_T rx_dc[UL1D_RXDC_LPM_TIA_GAIN_STEPS][UL1D_RXDC_LPM_PGA_GAIN_STEPS];
+} UMTS_RF_POC_RX_DC_LPM_COMP_T;
+
+typedef struct
+{
+ kal_int8 gate_bias_i;
+ kal_int8 gate_bias_q;
+} UMTS_RF_POC_RX_IIP2_COMP_T;
+
+typedef struct
+{
+ /* RX IRR */
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_hpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_IRR_COMP_T rx_irr_lpm[UL1D_RF_RX_IRR_COMP_ROUTE_MAX][UL1D_RX_CBW_NUM][UL1D_ANT_NUM];
+
+ /* RX DC */
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_rf_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_rf_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dig_dc_hpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dig_dc_lpm[UL1D_RF_RX_DC_COMP_ROUTE_MAX][UL1D_ANT_NUM];
+
+ /* RX IIP2 */
+ UMTS_RF_POC_RX_IIP2_COMP_T rx_iip2[UL1D_ANT_NUM][UL1D_RF_RX_IIP2_COMP_ROUTE_MAX];
+
+} UMTS_RF_POC_RX_COMP_DATA_T;
+
+
+/******************************
+* Tx DET POC Part
+*******************************/
+typedef struct
+{
+ kal_int32 i_part;
+ kal_int32 q_part;
+
+} UMTS_DET_EQLPF_COMP_T;
+
+typedef struct
+{
+ UMTS_DET_EQLPF_COMP_T coef[UL1D_DET_EQLPF_TAP_NUM];
+ kal_int32 scale_i;
+ kal_int32 scale_q;
+} UMTS_DET_FDADPCB_EQLPF_COMP_T;
+
+typedef struct{
+ kal_int8 gain_est_hw; //FIIQ gain
+ kal_int8 phase_est_hw; //FIIQ phase
+ UMTS_DET_FDADPCB_EQLPF_COMP_T fd_ad_pcb; //FDIQ, AD coefficient, 3G do not contain PCB information
+} UMTS_RF_POC_DET_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_DET_DC_COMP_T;
+
+typedef struct
+{
+ kal_uint32 mrx_cdcoci_sign; /* MRX coarse DC offset I channel sign */
+ kal_uint32 mrx_cdcoci_mag; /* MRX coarse DC offset I channel magnitude */
+ kal_uint32 mrx_cdcocq_sign; /* MRX coarse DC offset Q channel sign */
+ kal_uint32 mrx_cdcocq_mag; /* MRX coarse DC offset Q channel magnitude */
+}
+UMTS_RF_POC_MRX_COARSE_DC_T;
+
+typedef struct
+{
+ /* DET Coarse DCOC */
+ UMTS_RF_POC_MRX_COARSE_DC_T det_cdcoc;
+
+ /* DET IQ/DC/DNL Forward */
+ UMTS_RF_POC_DET_IQ_COMP_T det_iq_fwd[UL1D_DET_FE_GAIN_STEPS][UL1D_TX_CBW_NUM];
+ UMTS_RF_POC_DET_DC_COMP_T det_dc_fwd[UL1D_DET_GAIN_STEPS];
+ kal_int16 det_dnl_fwd[UL1D_DET_GAIN_STEPS];
+
+ kal_int16 mrx_ctune_pga[2/*MMRFC_MRX_PGA_TZA_BW_CNT*/];
+ kal_int16 mrx_ctune_tza[2/*MMRFC_MRX_PGA_TZA_BW_CNT*/];
+
+} UMTS_RF_POC_DET_COMP_DATA_T;
+
+/******************************
+* Tx FOWRAD POC Part
+*******************************/
+typedef struct{
+ kal_int8 gain_est;
+ kal_int8 phase_est;
+} UMTS_RF_POC_TX_IQ_COMP_T;
+
+typedef struct
+{
+ kal_int16 dc_i;
+ kal_int16 dc_q;
+} UMTS_RF_POC_TX_DC_COMP_T;
+
+typedef struct
+{
+
+ /* TX LPF*/
+ kal_int16 tx_lpf_abb_rsel;
+ kal_int16 tx_lpf_abb_csel_1;
+ kal_int16 tx_lpf_abb_csel_2;
+
+ /* TX RCF*/
+ kal_int16 tx_rcf_rsel;
+ kal_int16 tx_rcf_csel_4a;
+ kal_int16 tx_rcf_csel_1b;
+ kal_int16 tx_rcf_csel_2a;
+
+ /* TX FIIQ/DC/DNL Linear Mode */
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_lin[UL1D_TX_PGA_SLICE_NUM];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_lin[UL1D_TX_PGA_SLICE_NUM];
+
+ UMTS_RF_POC_TX_IQ_COMP_T tx_iq_dpd[UL1D_TX_PGA_SLICE_NUM];
+ UMTS_RF_POC_TX_DC_COMP_T tx_dc_dpd[UL1D_TX_PGA_SLICE_NUM];
+
+ kal_int16 tx_dnl_lin_pga_a[UL1D_TX_DNL_PGA_TOTAL_NUM];
+
+ /* TX PGA Phase Step */
+ kal_int32 tx_mod_slice_phase[UL1D_TX_PGA_SLICE_NUM-1/*Slice: 0:4A, 1:2A, 2:1A*/];
+
+ /* TX PGA Cap Tuning */
+ kal_uint32 cap_opt_a;
+ kal_uint32 tx_drv_ctunemod;
+
+} UMTS_RF_POC_TX_COMP_DATA_T;
+
+typedef struct
+{
+ kal_uint32 verno;
+ UMTSBand band;
+ UMTS_RF_POC_RX_COMP_DATA_T umts_rx_comp;
+ UMTS_RF_POC_DET_COMP_DATA_T umts_det_comp;
+ UMTS_RF_POC_TX_COMP_DATA_T umts_tx_comp;
+} UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T;
+
+
+/*******************************************************************************
+** Macro define for POC default value
+*******************************************************************************/
+
+
+/*Trinity_RX_Programming_Guide_0p1_20170607 */
+/*Table 4-3 DCOC Mapping Table */
+/*Offset Voltage(V) = 0V, DCOC[5:0] = 6'b100000 */
+
+#define UMTS_RXDC_RF_I_Default (0xFFE0)
+#define UMTS_RXDC_RF_Q_Default (0xFFE0)
+#define UMTS_RXDC_Dig_I_Default (0)
+#define UMTS_RXDC_Dig_Q_Default (0)
+
+#define UMTS_RXDC_RF_IQ_Default \
+{\
+ UMTS_RXDC_RF_I_Default, UMTS_RXDC_RF_Q_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_Default \
+{\
+ UMTS_RXDC_Dig_I_Default,\
+ UMTS_RXDC_Dig_Q_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default \
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_RF_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_RF_IQ_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_LPM_Default \
+{\
+ /*rx_dc[0][0]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][1]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][2]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][3]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][4]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][5]*/UMTS_RXDC_Dig_IQ_Default,\
+ /*rx_dc[0][6]*/UMTS_RXDC_Dig_IQ_Default,\
+}
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default \
+{\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_HPM_Default \
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default \
+{\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_HPM_Default \
+}
+
+
+#define UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default \
+{\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_RF_IQ_PGA_LPM_Default,\
+}
+
+#define UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default \
+{\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+ UMTS_RXDC_Dig_IQ_PGA_LPM_Default,\
+}
+
+
+
+#define UMTS_RXDC_RF_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_RF_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_RF_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_HPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_HPM_Default, \
+}, \
+}
+
+#define UMTS_RXDC_Dig_ANT_LPM_Default \
+{/*ROUTE:0*/ \
+{ /*ANT0*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+{ /*ANT1*/ \
+ UMTS_RXDC_Dig_IQ_PGA_TIA_LPM_Default, \
+}, \
+}
+
+
+#if defined(MT6763) || defined(MT6739) || defined(__MD93__)
+
+#define W_Rx_Irr_7Tap_Comp_Poc_Default \
+{ \
+ /*ANT0*/{0,0,{0,0,512,0,0,0,0}}, \
+ /*ANT1*/{0,0,{0,0,512,0,0,0,0}}, \
+}
+#elif defined(MT6295M) || defined(__MD95__)|| defined(__MD97__) || (defined __MD97P__)
+#define W_Rx_Irr_7Tap_Comp_Poc_Default \
+{ \
+ /*ANT0*/{0,0,{0,0,0,1024,0,0,0}}, \
+ /*ANT1*/{0,0,{0,0,0,1024,0,0,0}}, \
+}
+#else
+#error "un-defined BB chip"
+#endif
+
+#define M_IIP2_I_DEFAULT (64)
+#define M_IIP2_Q_DEFAULT (64)
+
+#define W_Rx_Iip2_Comp_Poc_Default {M_IIP2_I_DEFAULT, M_IIP2_Q_DEFAULT}
+
+#if defined(MT6763) || defined(MT6739) || defined(__MD93__)//IS_3G_CHIP_MT6293_SERIES
+/*93+trinity_TxDFERF_TxK_default_settings_20171013*/
+#define UMTS_Det_Iq_MG_SC_Comp_Default {0,0,{{{-4,-4},{17,17},{-45,-45},{105,105},{-257,-257},{880,880},{-254,-254},{100,100},{-42,-42},{14,14},{-3,-3},{0,0},{0,0}},9,9}}
+
+#elif defined(MT6295M) || defined(__MD95__)|| defined(__MD97__) || (defined __MD97P__)// IS_3G_CHIP_MT6295_SERIES
+/*95_TxDFERF_TxK_default_settings_20171027*/
+#define UMTS_Det_Iq_MG_SC_Comp_Default {0,0,{{{4,4},{-22,-22},{74,74},{-186,-186},{417,417},{-1021,-1021},{3513,3513},{-1010,-1010},{401,401},{-171,-171},{65,65},{-18,-18},{3,3}},1,1}}
+#else
+#error "un-defined BB chip"
+#endif
+
+#define UMTS_DET_IQ_MG_DDFAULT \
+ { /*UL1D_TX_CBW_NUM=2*/ \
+ UMTS_Det_Iq_MG_SC_Comp_Default,\
+ UMTS_Det_Iq_MG_SC_Comp_Default,\
+ },
+
+
+
+#define UMTS_DET_DC_DEFAULT {0/*DC_I*/, 0/*DC_Q*/}
+
+
+#define M_TX_PHASE_LB_4A_DEFAULT (0)
+#define M_TX_PHASE_LB_2A_DEFAULT (M_TX_PHASE_LB_4A_DEFAULT+UL1D_LB_PHASE_SLICE_CHANGE_4_to_2)/* 14*/
+#define M_TX_PHASE_LB_1A_DEFAULT (M_TX_PHASE_LB_2A_DEFAULT+UL1D_LB_PHASE_SLICE_CHANGE_2_to_1)/* 18*/
+
+#define M_TX_PHASE_MB_4A_DEFAULT (0)
+#define M_TX_PHASE_MB_2A_DEFAULT (M_TX_PHASE_MB_4A_DEFAULT+UL1D_MB_PHASE_SLICE_CHANGE_4_to_2)/* 11*/
+#define M_TX_PHASE_MB_1A_DEFAULT (M_TX_PHASE_MB_2A_DEFAULT+UL1D_MB_PHASE_SLICE_CHANGE_2_to_1)/*-13*/
+
+
+// RX
+//============================================================
+#define UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+{ \
+ UMTS_RXDC_RF_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+{ \
+ UMTS_RXDC_RF_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+{ \
+ UMTS_RXDC_Dig_ANT_HPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+{ \
+ UMTS_RXDC_Dig_ANT_LPM_Default,/*ROUTE:0*/ \
+},
+
+#define UL1D_DEFAULT_RFC_RX_IRR_HPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 1, HPM*/ \
+ { \
+ /*SC*/W_Rx_Irr_7Tap_Comp_Poc_Default, \
+ /*DC*/W_Rx_Irr_7Tap_Comp_Poc_Default, \
+ /*3C*/W_Rx_Irr_7Tap_Comp_Poc_Default \
+ }, \
+},
+
+#define UL1D_DEFAULT_RFC_RX_IRR_LPM \
+{ \
+ /*MMRFC_RX_IRR_COMP_ROUTE_MAX = 1, LPM*/ \
+ { \
+ /*SC*/W_Rx_Irr_7Tap_Comp_Poc_Default, \
+ /*DC*/W_Rx_Irr_7Tap_Comp_Poc_Default, \
+ /*3C*/W_Rx_Irr_7Tap_Comp_Poc_Default \
+ }, \
+},
+
+
+#define UL1D_DEFAULT_RFC_RX_IIP2 \
+{ \
+ { /*RXP*/ \
+ W_Rx_Iip2_Comp_Poc_Default,/*ROUTE00*/ \
+ }, \
+ { /*RXD*/ \
+ W_Rx_Iip2_Comp_Poc_Default,/*ROUTE00*/ \
+ } \
+},
+
+
+//DET
+//============================================================
+
+
+#define UL1D_DEFAULT_RFC_MRX_IQ \
+ { /* UL1D_DET_FE_GAIN_STEPS = 1 */ \
+ UMTS_DET_IQ_MG_DDFAULT \
+ },
+
+
+#define UL1D_DEFAULT_RFC_MRX_DC \
+ { /* UL1D_DET_GAIN_STEPS = 5*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG00*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG01*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG02*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG03*/ \
+ UMTS_DET_DC_DEFAULT,/*DETG04*/ \
+ },
+
+/* A60827_BBBM_TABLE_322.xlsx, */
+/* sheet: MRX1_GAIN & MRX2_GAIN */
+/* MRX Gain*/
+#define UL1D_DEFAULT_RFC_MRX_DNL \
+{ \
+ 304, /* G0*/ \
+ 112, /* G1*/ \
+ -80 , /* G2*/ \
+ -272, /* G3*/ \
+ -464, /* G4*/ \
+},
+
+
+#define UL1D_DEFAULT_RFC_MRX_CDCOC \
+{ \
+ /* mrx_cdcoci_sign*/0, \
+ /* mrx_cdcoci_mag */0, \
+ /* mrx_cdcocq_sign*/0, \
+ /* mrx_cdcocq_mag */0, \
+},
+
+
+
+/*
+ A60827_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+ CW718[D07:D00] RG_TX1_MRX_PGA_CTUNE[7:0] = 0x36
+ CW718[D15:D08] RG_TX1_MRX_TZA_CTUNE[7:0] = 0x18
+ CW738[D07:D00] RG_TX2_MRX_PGA_CTUNE[7:0] = 0x36
+ CW738[D15:D08] RG_TX2_MRX_TZA_CTUNE[7:0] = 0x18
+*/
+
+#define UL1D_DEFAULT_RFC_MRX_CTUNE_PGA \
+{ \
+ /* MMRFC_MRX_PGA_TZA_BW_22P5 */0x36,\
+ /* MMRFC_MRX_PGA_TZA_BW_67P5 */0x36 \
+},
+
+#define UL1D_DEFAULT_RFC_MRX_CTUNE_TZA \
+{ \
+ /* MMRFC_MRX_PGA_TZA_BW_22P5 */0x18,\
+ /* MMRFC_MRX_PGA_TZA_BW_67P5 */0x18 \
+},
+
+
+//TX
+//============================================================
+
+
+/*DOC : Trinity Gain Table V1.1 Draft.xlsx */
+/*Sheet: Gain Tables */
+/*Table: ULB&LB&MB */
+
+#define UL1D_DEFAULT_RFC_TX_DNL_PGA \
+{ \
+ 0, /* G0 , A , 0 dB */ \
+ -18, /* G1 , A , -0.56 dB */ \
+ -37, /* G2 , A , -1.16 dB */ \
+ -58, /* G3 , A , -1.8 dB */ \
+ -80, /* G4 , A , -2.5 dB */ \
+ -104, /* G5 , A , -3.25 dB */ \
+ -131, /* G6 , A , -4.08 dB */ \
+ -160, /* G7 , A , -4.99 dB */ \
+ -193, /* G8 , A , -6.02 dB */ \
+ -230, /* G9 , A , -7.18 dB */ \
+ -273, /* G10, A , -8.52 dB */ \
+ -323, /* G11, A , -10.1 dB */ \
+ -401, /* G12, A , -12.53 dB */ \
+ -468, /* G13, A , -14.62 dB */ \
+ -515, /* G14, B , -16.08 dB */ \
+ -621, /* G15, B , -19.4 dB */ \
+ -734, /* G16, B , -22.93 dB */ \
+ -853, /* G17, B , -26.67 dB */ \
+ -988, /* G18, B , -30.89 dB */ \
+ -1181, /* G19, B , -36.91 dB */ \
+ -1374, /* G20, B , -42.93 dB */ \
+ -1566, /* G21, B , -48.95 dB */ \
+ -1759, /* G22, AUX, -54.97 dB */ \
+ -1952, /* G23, AUX, -60.99 dB */ \
+ -2144, /* G24, AUX, -67.01 dB */ \
+ -2337, /* G25, AUX, -73.03 dB */ \
+ -2530 /* G26, AUX, -79.05 dB */ \
+},
+
+#define UL1D_DEFAULT_RFC_TX_IQ_DC \
+ /*tx_iq_lin*/{{0,0}}, \
+ /*tx_dc_lin*/{{0,0}}, \
+ /*tx_iq_dpd*/{{0,0}}, \
+ /*tx_dc_dpd*/{{0,0}},
+
+
+
+/* TX LPF*/
+/* ==============================================================================
+
+ A60827_TX_Programming_Guide.docx, 3.6.1 ABB BW Controls
+ Trinity_VCODIV_table_20170925_for_93modem
+ A60827_BBBM_TABLE_322.xlsx
+ A60827_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+
+ CW708 TX1_BBBM4 TX1_ABB_CSEL [7:0] TX1_ABB_RSEL [1:0]
+ CW728 TX2_BBBM4 TX2_ABB_CSEL [7:0] TX2_ABB_RSEL [1:0] --> 2 bits
+ CW890 TX1_ABBMAN1 TX1_ABB_CSEL1_M[7:0] -------------------
+ TX1_ABB_CSEL2_M[7:0] -------------------
+ CW957 TX2_ABBMAN1 TX2_ABB_CSEL1_M[7:0] -------------------
+ TX2_ABB_CSEL2_M[7:0] -------------------
+ CW891 TX1_ABBMAN2 -------------------- TX1_ABB_RSEL_M[3:0] --> 4 bits ?
+ CW958 TX2_ABBMAN2 -------------------- TX2_ABB_RSEL_M[3:0]
+
+ |Band | Path | Mode | TX1/2_ABB_CSEL[7:0]| TX1/2_ABB_RSEL[1:0]|
+ |-------------|---------|----------|--------------------|--------------------|
+ |3G_FDD_Band01| 1 |LPF_6P8M | 0xC6 | 0x2 |
+ |3G_FDD_Band02| 1 |LPF_6P8M | 0xC6 | 0x2 |
+ |3G_FDD_Band03| 1 |LPF_6P8M | 0xC6 | 0x2 |
+ |3G_FDD_Band04| 1 |LPF_6P8M | 0xC6 | 0x2 |
+ |3G_FDD_Band05| 2 |LPF_6P8M | 0xC6 | 0x2 |
+ |3G_FDD_Band06| 2 |LPF_6P8M | 0xC6 | 0x2 |
+ |3G_FDD_Band08| 2 |LPF_6P8M | 0xC6 | 0x2 |
+ |3G_FDD_Band09| 1 |LPF_6P8M | 0xC6 | 0x2 |
+ |3G_FDD_Band11| 1 |LPF_6P8M | 0xC6 | 0x2 |
+ |3G_FDD_Band18| 2 |LPF_6P8M | 0xC6 | 0x2 |
+ |3G_FDD_Band19| 2 |LPF_6P8M | 0xC6 | 0x2 |
+
+ =============================================================================*/
+
+#define UL1D_DEFAULT_RFC_TX_LPF_BNone \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6,\
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B1 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6, \
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B2 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6, \
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B3 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6, \
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B4 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6, \
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B5 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6, \
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B6 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6, \
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B8 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6, \
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B9 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6, \
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B11 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6, \
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B18 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6, \
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+#define UL1D_DEFAULT_RFC_TX_LPF_B19 \
+ /*tx_lpf_abb_rsel */ 0x2, \
+ /*tx_lpf_abb_csel_1*/ 0xC6, \
+ /*tx_lpf_abb_csel_2*/ 0xC6,
+
+
+
+
+/* TX RCF*/
+/*
+ A60827_BBBM_TABLE_322.xlsx
+ A60827_TX_Programming_Guide.docx, 3.6.1 ABB BW Controls
+ Trinity_VCODIV_table_20170925_for_93modem
+ A60827_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+ CW709
+ CW710
+ CW728
+ CW729
+
+ |Band | Path | Mode:TX1 | Mode:TX2 | RG_TX2_RCF_RSEL[7:0]| TX2_RCF_CSEL[7:0]| TX2_RCF_CSEL_1B[7:0] | TX2_RCF_CSEL_2A[7:0]|
+ |--------------|-------|-----------------|----------------|---------------------|------------------ |----------------------|---------------------|
+ |3G_FDD_Band01 | 1 | RCF_MB_CM1_16M | RCF_MB_CM1_16M | 0x2A | 0x1D | 0x1D | 0x1D |
+ |3G_FDD_Band02 | 1 | RCF_MB_CM2_16M | RCF_MB_CM2_16M | 0x2F | 0x20 | 0x20 | 0x20 |
+ |3G_FDD_Band03 | 1 | RCF_MB_CM3_16M | RCF_MB_CM3_16M | 0x37 | 0x22 | 0x22 | 0x22 |
+ |3G_FDD_Band04 | 1 | RCF_MB_CM3_16M | RCF_MB_CM3_16M | 0x37 | 0x22 | 0x22 | 0x22 |
+ |3G_FDD_Band05 | 2 | RCF_LB_CM2_16M | RCF_LB_CM2_16M | 0x21 | 0x19 | 0x19 | 0x19 |
+ |3G_FDD_Band06 | 2 | RCF_LB_CM2_16M | RCF_LB_CM2_16M | 0x21 | 0x19 | 0x19 | 0x19 |
+ |3G_FDD_Band08 | 2 | RCF_LB_CM1_16M | RCF_LB_CM1_16M | 0x1C | 0x14 | 0x14 | 0x14 |
+ |3G_FDD_Band09 | 1 | RCF_MB_CM3_16M | RCF_MB_CM3_16M | 0x37 | 0x22 | 0x22 | 0x22 |
+ |3G_FDD_Band11 | 1 | RCF_MB_CM4_16M | RCF_MB_CM4_16M | 0x37 | 0x23(???) | 0x24 | 0x24 |
+ |3G_FDD_Band18 | 2 | RCF_LB_CM3_16M | RCF_LB_CM3_16M | 0x24 | 0x19 | 0x19 | 0x19 |
+ |3G_FDD_Band19 | 2 | RCF_LB_CM2_16M | RCF_LB_CM2_16M | 0x21 | 0x19 | 0x19 | 0x19 |
+*/
+
+#define UL1D_DEFAULT_RFC_TX_RCF_BNone \
+ /*tx_rcf_rsel */ 0x2A, \
+ /*tx_rcf_csel_4a */ 0x1D, \
+ /*tx_rcf_csel_1b */ 0x1D, \
+ /*tx_rcf_csel_2a */ 0x1D,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B1 \
+ /*tx_rcf_rsel */ 0x2A, \
+ /*tx_rcf_csel_4a */ 0x1D, \
+ /*tx_rcf_csel_1b */ 0x1D, \
+ /*tx_rcf_csel_2a */ 0x1D,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B2 \
+ /*tx_rcf_rsel */ 0x2F, \
+ /*tx_rcf_csel_4a */ 0x20, \
+ /*tx_rcf_csel_1b */ 0x20, \
+ /*tx_rcf_csel_2a */ 0x20,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B3 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x22, \
+ /*tx_rcf_csel_1b */ 0x22, \
+ /*tx_rcf_csel_2a */ 0x22,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B4 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x22, \
+ /*tx_rcf_csel_1b */ 0x22, \
+ /*tx_rcf_csel_2a */ 0x22,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B5 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x19, \
+ /*tx_rcf_csel_1b */ 0x19, \
+ /*tx_rcf_csel_2a */ 0x19,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B6 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x19, \
+ /*tx_rcf_csel_1b */ 0x19, \
+ /*tx_rcf_csel_2a */ 0x19,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B8 \
+ /*tx_rcf_rsel */ 0x1C, \
+ /*tx_rcf_csel_4a */ 0x14, \
+ /*tx_rcf_csel_1b */ 0x14, \
+ /*tx_rcf_csel_2a */ 0x14,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B9 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x22, \
+ /*tx_rcf_csel_1b */ 0x22, \
+ /*tx_rcf_csel_2a */ 0x22,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B11 \
+ /*tx_rcf_rsel */ 0x37, \
+ /*tx_rcf_csel_4a */ 0x23, \
+ /*tx_rcf_csel_1b */ 0x24, \
+ /*tx_rcf_csel_2a */ 0x24,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B18 \
+ /*tx_rcf_rsel */ 0x24, \
+ /*tx_rcf_csel_4a */ 0x19, \
+ /*tx_rcf_csel_1b */ 0x19, \
+ /*tx_rcf_csel_2a */ 0x19,
+
+#define UL1D_DEFAULT_RFC_TX_RCF_B19 \
+ /*tx_rcf_rsel */ 0x21, \
+ /*tx_rcf_csel_4a */ 0x19, \
+ /*tx_rcf_csel_1b */ 0x19, \
+ /*tx_rcf_csel_2a */ 0x19,
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_BNone \
+{ \
+ M_TX_PHASE_MB_4A_DEFAULT, \
+ M_TX_PHASE_MB_2A_DEFAULT, \
+ M_TX_PHASE_MB_1A_DEFAULT \
+},
+
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B1 \
+{ \
+ M_TX_PHASE_MB_4A_DEFAULT, \
+ M_TX_PHASE_MB_2A_DEFAULT, \
+ M_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B2 \
+{ \
+ M_TX_PHASE_MB_4A_DEFAULT, \
+ M_TX_PHASE_MB_2A_DEFAULT, \
+ M_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B3 \
+{ \
+ M_TX_PHASE_MB_4A_DEFAULT, \
+ M_TX_PHASE_MB_2A_DEFAULT, \
+ M_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B4 \
+{ \
+ M_TX_PHASE_MB_4A_DEFAULT, \
+ M_TX_PHASE_MB_2A_DEFAULT, \
+ M_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B5 \
+{ \
+ M_TX_PHASE_LB_4A_DEFAULT, \
+ M_TX_PHASE_LB_2A_DEFAULT, \
+ M_TX_PHASE_LB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B6 \
+{ \
+ M_TX_PHASE_LB_4A_DEFAULT, \
+ M_TX_PHASE_LB_2A_DEFAULT, \
+ M_TX_PHASE_LB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B8 \
+{ \
+ M_TX_PHASE_LB_4A_DEFAULT, \
+ M_TX_PHASE_LB_2A_DEFAULT, \
+ M_TX_PHASE_LB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B9 \
+{ \
+ M_TX_PHASE_MB_4A_DEFAULT, \
+ M_TX_PHASE_MB_2A_DEFAULT, \
+ M_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B11 \
+{ \
+ M_TX_PHASE_MB_4A_DEFAULT, \
+ M_TX_PHASE_MB_2A_DEFAULT, \
+ M_TX_PHASE_MB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B18 \
+{ \
+ M_TX_PHASE_LB_4A_DEFAULT, \
+ M_TX_PHASE_LB_2A_DEFAULT, \
+ M_TX_PHASE_LB_1A_DEFAULT \
+},
+
+#define UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B19 \
+{ \
+ M_TX_PHASE_LB_4A_DEFAULT, \
+ M_TX_PHASE_LB_2A_DEFAULT, \
+ M_TX_PHASE_LB_1A_DEFAULT \
+},
+
+/*
+ A60827_3wire_CW_ver_0p1.2rfse_3wire_panel.xls_mode_value
+ ------------------------------------------------------------------------------------------------------------------------------
+ | | | CW706[D19~D12]: | CW706[D11~D4]: | CW726[D19~D12]: | CW726[D11~D4]: |
+ |Band | Path | RG_TX1_DRV_CTUNEMOD[7:0] | RG_TX1_PGA_CTUNE[7:0] | RG_TX2_DRV_CTUNEMOD[7:0] | RG_TX2_PGA_CTUNE[7:0] |
+ |--------------|------|---------------------------|-----------------------|--------------------------|-----------------------|
+ |3G_FDD_Band01 | 1 | 0x09 | 0x10 | 0x09 | 0x0F |
+ |3G_FDD_Band02 | 1 | 0x0D | 0x13 | 0x0D | 0x11 |
+ |3G_FDD_Band03 | 1 | 0x13 | 0x19 | 0x14 | 0x17 |
+ |3G_FDD_Band04 | 1 | 0x14 | 0x19 | 0x14 | 0x17 |
+ |3G_FDD_Band05 | 2 | 0x0A | 0x0B | 0x0A | 0x0B |
+ |3G_FDD_Band06 | 2 | 0x0A | 0x0B | 0x0A | 0x0B |
+ |3G_FDD_Band08 | 2 | 0x07 | 0x09 | 0x07 | 0x09 |
+ |3G_FDD_Band09 | 1 | 0x12 | 0x16 | 0x12 | 0x16 |
+ |3G_FDD_Band11 | 1 | 0x2C | 0x26 | 0x2C | 0x26 |
+ |3G_FDD_Band18 | 2 | 0x0B | 0x0D | 0x0A | 0x0B |
+ |3G_FDD_Band19 | 2 | 0x0A | 0x0B | 0x0A | 0x0B |
+ ------------------------------------------------------------------------------------------------------------------------------
+*/
+
+#define UL1D_DEFAULT_RFC_TX_CAP_BNone \
+ /*cap_opt_a */0, \
+ /*tx_drv_ctunemod*/0,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B1 \
+ /*cap_opt_a */0x10, \
+ /*tx_drv_ctunemod*/0x09,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B2 \
+ /*cap_opt_a */0x13, \
+ /*tx_drv_ctunemod*/0x0D,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B3 \
+ /*cap_opt_a */0x19, \
+ /*tx_drv_ctunemod*/0x13,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B4 \
+ /*cap_opt_a */0x19, \
+ /*tx_drv_ctunemod*/0x14,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B5 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B6 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B8 \
+ /*cap_opt_a */0x09, \
+ /*tx_drv_ctunemod*/0x07,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B9 \
+ /*cap_opt_a */0x16, \
+ /*tx_drv_ctunemod*/0x12,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B11 \
+ /*cap_opt_a */0x26, \
+ /*tx_drv_ctunemod*/0x2C,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B18 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+#define UL1D_DEFAULT_RFC_TX_CAP_B19 \
+ /*cap_opt_a */0x0B, \
+ /*tx_drv_ctunemod*/0x0A,
+
+
+#define VERNO_BNone (0),
+#define VERNO_B1 (0),
+#define VERNO_B2 (0),
+#define VERNO_B3 (0),
+#define VERNO_B4 (0),
+#define VERNO_B5 (0),
+#define VERNO_B6 (0),
+#define VERNO_B8 (0),
+#define VERNO_B9 (0),
+#define VERNO_B11 (0),
+#define VERNO_B18 (0),
+#define VERNO_B19 (0),
+
+
+#define M_UL1D_DEFAULT_RFC_B(BAND_ID) \
+{ \
+ VERNO_B##BAND_ID \
+ UMTSBand##BAND_ID, \
+ { \
+ UL1D_DEFAULT_RFC_RX_IRR_HPM \
+ UL1D_DEFAULT_RFC_RX_IRR_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_RF_LPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_HPM \
+ UL1D_DEFAULT_RFC_RX_DC_DIG_LPM \
+ UL1D_DEFAULT_RFC_RX_IIP2 \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_MRX_CDCOC \
+ UL1D_DEFAULT_RFC_MRX_IQ \
+ UL1D_DEFAULT_RFC_MRX_DC \
+ UL1D_DEFAULT_RFC_MRX_DNL \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_PGA \
+ UL1D_DEFAULT_RFC_MRX_CTUNE_TZA \
+ }, \
+ { \
+ UL1D_DEFAULT_RFC_TX_LPF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_RCF_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_IQ_DC \
+ UL1D_DEFAULT_RFC_TX_DNL_PGA \
+ UL1D_DEFAULT_RFC_TX_MOD_SLICE_PHASE_B##BAND_ID \
+ UL1D_DEFAULT_RFC_TX_CAP_B##BAND_ID \
+ } \
+}
+
+
+#endif /*__UL1D_RFC_DATA_TRINITYE1_H__*/
+
+/* Doxygen Group End ***************************************************//**@}*/
diff --git a/mcu/interface/l1/ul1/external/ul1d_rf_cid.h b/mcu/interface/l1/ul1/external/ul1d_rf_cid.h
new file mode 100644
index 0000000..7bbecf8
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_rf_cid.h
@@ -0,0 +1,1213 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1d_rf_cid.h
+ *
+ * Project:
+ * --------
+ * 3G Project Common File
+ *
+ * Description:
+ * ------------
+ * Compile option definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *------------------------------------------------------------------------------
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+ *******************************************************************************/
+
+#ifndef _UL1D_RF_CID_H_
+#define _UL1D_RF_CID_H_
+
+/*******************************************************************************
+** Define RF chip in use
+*******************************************************************************/
+
+/*-----------------------------------------------*/
+/* Use in UL1D : */
+/* ( 1) UL1D_RF_ID_MT6176 */
+/*-----------------------------------------------*/
+/*#define UL1D_RF_ID_SONY_CXA3359 0x00000001*/
+/*#define UL1D_RF_ID_MT6159B 0x00000002*/
+/*#define UL1D_RF_ID_SMARTI3G 0x00000003*/
+/*#define UL1D_RF_ID_MT6159D 0x00000005*/
+/*#define UL1D_RF_ID_MT6160 0x00000007*/
+/*#define UL1D_RF_ID_MT6162 0x00000008*/
+/*#define UL1D_RF_ID_MT6162_DUAL 0x00000009*/
+/*#define UL1D_RF_ID_ORION_FDD 0x0000000A*/
+/*#define UL1D_RF_ID_ORION_HPLUS 0x0000000B*/
+/*#define UL1D_RF_ID_MT6167 0x0000000C*/
+/*#define UL1D_RF_ID_MT6166 0x0000000D*/
+/*#define UL1D_RF_ID_MT6169 0x0000000E*/
+/*#define UL1D_RF_ID_MT6580RF(Rainier) 0x0000000F*/
+/*#define UL1D_RF_ID_MT6161 0x00000010*/
+
+#define UL1D_RF_ID_MT6176 0x00000011
+#define UL1D_RF_ID_MT6179 0x00000012
+#define UL1D_RF_ID_MT6570 0x00000013
+#define UL1D_RF_ID_MT6177L 0x00000014
+#define UL1D_RF_ID_MT6173 0x00000015
+#define UL1D_RF_ID_TRINITYE1 0x00000016
+#define UL1D_RF_ID_TRINITYL 0x00000017
+#define UL1D_RF_ID_TRINITYL_E2 0x00000018
+#define UL1D_RF_ID_TRINITY2L 0x00000019
+#define UL1D_RF_ID_COLUMBUS 0x00000020
+#define UL1D_RF_ID_COLUMBUSL 0x00000021
+
+
+#if (defined __MD97__) || (defined __MD97P__)
+#define IS_URF_MD97_TO_DO (1)
+#else
+#define IS_URF_MD97_TO_DO (0)
+#endif
+
+#ifndef UL1D_RF_ID
+ #if defined(MT6186M_UMTS_FDD)
+#define UL1D_RF_ID UL1D_RF_ID_TRINITY2L
+ #elif defined(MT6186_UMTS_FDD)
+#define UL1D_RF_ID UL1D_RF_ID_TRINITYL_E2
+ #elif defined(TRINITYL_UMTS_FDD)||defined(TRINITYL_RF)||defined(MT6185M_UMTS_FDD)
+#define UL1D_RF_ID UL1D_RF_ID_TRINITYL
+ #elif defined(TRINITYE1_UMTS_FDD)
+#define UL1D_RF_ID UL1D_RF_ID_TRINITYE1
+ #elif defined(MT6190T_UMTS_FDD)||defined(MT6190_UMTS_FDD)||defined(MT6195_UMTS_FDD)
+#define UL1D_RF_ID UL1D_RF_ID_COLUMBUS
+ #elif defined(MT6190M_UMTS_FDD)
+#define UL1D_RF_ID UL1D_RF_ID_COLUMBUSL
+ #elif defined(MT6177M_RF)
+#define UL1D_RF_ID UL1D_RF_ID_MT6173
+ #elif defined(MT6177L_RF)
+#define UL1D_RF_ID UL1D_RF_ID_MT6177L
+ #elif defined(MT6179_RF)
+#define UL1D_RF_ID UL1D_RF_ID_MT6179
+ #else
+ #error "No Valid RF Chip was defined"
+ #endif
+#else
+ #error "Unexpected RF Chip was defined"
+#endif
+
+/*.......................................................*/
+#define IS_URF_ORION_HPLUS ( 0 )
+
+#define IS_URF_MT6176 ( 0 )
+#define IS_URF_MT6179 ( 0 )
+#define IS_URF_MT6177L ( UL1D_RF_ID==UL1D_RF_ID_MT6177L )
+#define IS_URF_MT6173 ( UL1D_RF_ID==UL1D_RF_ID_MT6173 )
+#define IS_URF_TRINITYE1 (( UL1D_RF_ID==UL1D_RF_ID_TRINITYE1)||( UL1D_RF_ID==UL1D_RF_ID_TRINITYL)||(UL1D_RF_ID==UL1D_RF_ID_TRINITYL_E2))
+#define IS_URF_TRINITY_L (( UL1D_RF_ID==UL1D_RF_ID_TRINITYL )||(UL1D_RF_ID==UL1D_RF_ID_TRINITYL_E2))
+#define IS_URF_TRINITY_L_E2 ( UL1D_RF_ID==UL1D_RF_ID_TRINITYL_E2)
+#define IS_URF_TRINITY_2L ( UL1D_RF_ID==UL1D_RF_ID_TRINITY2L )
+#define IS_URF_COLUMBUS ( UL1D_RF_ID==UL1D_RF_ID_COLUMBUS)||( UL1D_RF_ID==UL1D_RF_ID_COLUMBUSL)
+
+
+#if IS_URF_MT6177L
+#define IS_URF_MT6177L_RX ( 1 )
+#define IS_URF_MT6177L_RX_ADVANCE ( 1 )
+#define IS_URF_MT6177L_RX_POC ( 1 )
+#define IS_URF_MT6177L_RX_REFINE ( 0 )
+#define IS_URF_MT6177L_DUMP_SUPPORT ( 0 )
+#define IS_URF_MT6177L_RFC ( 1 )
+#define IS_MT6177L_PHONE_CALL_RX ( 0 )
+#define IS_MT6177L_RX_POC_DEBUG ( 0 )
+#elif IS_URF_MT6173
+#define IS_URF_MT6173_RX ( 1 )
+#define IS_URF_MT6173_RFC ( 1 )
+#define IS_URF_MT6173_RX_POC ( 1 )
+#define IS_MT6173_RX_POC_DEBUG ( 0 )
+#define IS_URF_MT6173_RX_REFINE ( 0 )
+#define IS_URF_MT6173_RX_ADVANCED ( 1 )
+#define IS_MT6173_PHONE_CALL_RX ( 0 )
+#define IS_URF_MT6173_DUMP_SUPPORT ( 0 )
+#define IS_URF_MT6173_DET_ALWAYS_ON defined(__IS_MT6177M_CODE_DOMAIN_POWER_IMPROVE__)
+#elif IS_URF_TRINITYE1
+#define IS_URF_TRINITYE1_RX ( 1 )
+#define IS_URF_TRINITYE1_RX_REFINE ( 0 )
+#define IS_URF_TRINITYE1_RX_ADVANCED ( 1 )
+#define IS_TRINITYE1_PHONE_CALL_RX ( 0 )
+#define IS_URF_TRINITYE1_DUMP_SUPPORT ( 0 )
+#define IS_URF_TRINITY_TX_DEBUG ( 0 )
+#define IS_URF_TRINITYE1_RFC ( 1 )
+#define IS_URF_TRINITYE1_RFC_TBD ( 1 )
+#define IS_URF_DIMENSION_CHECK_EN ( 1 )
+#define IS_URF_POC_CW_CHECK_EN ( 0 )
+#elif IS_URF_TRINITY_2L
+#define IS_URF_TRINITY2L_RX ( 1 )
+#define IS_URF_TRINITY2L_RX_REFINE ( 0 )
+#define IS_URF_TRINITY2L_RX_ADVANCED ( 1 )
+#define IS_TRINITY2L_PHONE_CALL_RX ( 0 )
+#define IS_URF_TRINITY2L_DUMP_SUPPORT ( 0 )
+#define IS_URF_TRINITY2L_RFC_TBD ( 1 )
+#define IS_URF_TRINITY_TX_DEBUG ( 0 )
+#define IS_URF_DIMENSION_CHECK_EN ( 1 )
+#define IS_URF_POC_CW_CHECK_EN ( 0 )
+#elif IS_URF_COLUMBUS
+#define IS_URF_COLUMBUS_RX ( 1 )
+#define IS_URF_COLUMBUS_NVRAM_REMOVE ( 0 )
+#define IS_URF_COLUMBUS_TO_DO ( 1 )
+#endif
+
+#if IS_URF_COLUMBUS_TO_DO
+#define IS_URF_CDF_INTERFACE 1
+#define IS_URF_TEMPERATURE_HAL_INTERFACE 0
+#define IS_URF_HAL_INTERFACE 0
+#else
+#define IS_URF_CDF_INTERFACE 0
+#define IS_URF_TEMPERATURE_HAL_INTERFACE defined (__MMRF_RF_HAL_SEQ_GEN_SUPPORT__)
+#define IS_URF_HAL_INTERFACE defined (__MMRF_RF_HAL_SEQ_GEN_SUPPORT__)
+#endif
+
+/*.......................................................*/
+
+#define IS_URF_MT6291_DUAL_CORE_ARCH (0)
+#define IS_URF_PCORE (1) //for backward 91 code, default enable Pcore and L1core code
+#define IS_URF_L1CORE (1) //for backward 91 code, default enable Pcore and L1core code
+
+#if (defined __MD93__)
+#define IS_URF_PCORE_REMOVE_SUPPORT (0)//for PCORE Remove Task
+#else
+/*MD95 and later*/
+#define IS_URF_PCORE_REMOVE_SUPPORT (0)//for PCORE Remove Task
+#endif
+
+
+/*RXDC GxE Dimension (For Lafite(and later) + Trinty-L E2 & Trinity-2L, updated 20180913)*/
+#if defined(__MD95__)
+
+#if defined(MT3967)||defined(MT6295M)
+#define IS_URF_RXDC_GXE_SUPPORT (0)
+#else
+#if (( UL1D_RF_ID==UL1D_RF_ID_TRINITYE1)||( UL1D_RF_ID==UL1D_RF_ID_TRINITYL))
+#define IS_URF_RXDC_GXE_SUPPORT (0)
+#else
+#define IS_URF_RXDC_GXE_SUPPORT (1)
+#endif
+#endif/*MT3967 or MT6295M*/
+
+#endif/*__MD95__*/
+
+
+/*.......................................................*/
+
+/*******************************************************************************
+** META HWTPC test item usage
+*******************************************************************************/
+#define IS_HSPA_HWTPC 0
+
+/*******************************************************************************
+** RXD & DUAL CELL usage
+*******************************************************************************/
+#if (IS_URF_MT6176 || IS_URF_MT6179 || IS_URF_MT6177L_RX || IS_URF_MT6173_RX || IS_URF_TRINITYE1_RX || IS_URF_TRINITY2L_RX || IS_URF_COLUMBUS_RX)
+#define IS_RF_DUAL_CELL_SUPPORT 1
+#define IS_RF_RXD_SUPPORT 1
+#define TEAMPERATURE_MEAS_EN 1 /* temp disable for phone call and not port yet */
+
+/*MIPI RFFE flag*/
+#define IS_3G_MIPI_SUPPORT defined (__3G_MIPI_SUPPORT__) /* temp enable 3G MIPI by 2G make option */
+#define IS_3G_MIPI_NVRAM_FULL_SUPPORT IS_3G_MIPI_SUPPORT
+#define ENABLE_3G_TPC_SUB_BAND 1 /* subband support for MIPI 8 stage PA bias*/
+#if IS_3G_MIPI_SUPPORT
+#define IS_3G_MIPI_EXTENDED_READ_ENABLE 0
+#endif
+#define IS_3G_NEW_MIPI_FORMAT_FOR_MMRF_API (IS_3G_MIPI_SUPPORT)
+
+/*TAS Feature flag*/
+#ifdef __TAS_SUPPORT__
+ #if (defined __MD93__)
+ #define IS_3G_TAS_SUPPORT (1)
+ #define IS_3G_UTAS_SUPPORT (0)
+ #define IS_3G_GEN97_TAS_SUPPORT (0)
+ #elif (defined __MD95__)
+ #define IS_3G_TAS_SUPPORT (1)
+ #define IS_3G_UTAS_SUPPORT (1)
+ #define IS_3G_GEN97_TAS_SUPPORT (0)
+ #elif (defined __MD97__) || (defined __MD97P__)
+ #define IS_3G_TAS_SUPPORT (1)
+ #define IS_3G_UTAS_SUPPORT (1)
+ #define IS_3G_GEN97_TAS_SUPPORT (1)
+ #else
+ #error "[ERROR] Invalid MD generation"
+ #endif
+#else
+#define IS_3G_TAS_SUPPORT (0)
+#define IS_3G_UTAS_SUPPORT (0)
+#define IS_3G_GEN97_TAS_SUPPORT (0)
+#endif
+
+#define ENABLE_TAS_DEBUG_TRACE (0)
+#define IS_3G_FORCE_TX_ANT_SUPPORT IS_3G_TAS_SUPPORT
+#define IS_3G_TAS_UL1_CUSTOM_SUPPORT IS_3G_TAS_SUPPORT
+#define IS_3G_TAS_2P0_LATTER IS_3G_TAS_SUPPORT
+
+#define IS_3G_TAS_MPR_SUPPORT IS_3G_TAS_SUPPORT
+#define IS_3G_TAS_TST_SUPPORT IS_3G_TAS_SUPPORT
+#define IS_3G_TAS_INHERIT_4G_ANT IS_3G_TAS_SUPPORT
+
+/*DAT Feature flag*/
+#if (defined __MD97__) || (defined __MD97P__)
+#define IS_3G_DYNAMIC_ANTENNA_TUNING_SUPPORT 1 /*Gen97 DAT is default enable*/
+#else
+#define IS_3G_DYNAMIC_ANTENNA_TUNING_SUPPORT defined (__DYNAMIC_ANTENNA_TUNING__)
+#endif
+
+#if IS_3G_DYNAMIC_ANTENNA_TUNING_SUPPORT
+ #if (defined __MD93__)
+ #define IS_3G_UDAT_SUPPORT (0) /*(0)*/
+ #define IS_3G_GEN97_DAT_SUPPORT (0)
+ #elif (defined __MD95__)
+ #define IS_3G_UDAT_SUPPORT (1)
+ #define IS_3G_GEN97_DAT_SUPPORT (0)
+ #elif (defined __MD97__) || (defined __MD97P__)
+ #define IS_3G_UDAT_SUPPORT (1)
+ #define IS_3G_GEN97_DAT_SUPPORT (1)
+ #else
+ #error "[ERROR] Invalid MD generation"
+ #endif
+#else
+ #define IS_3G_UDAT_SUPPORT (0) /*(0)*/
+ #define IS_3G_GEN97_DAT_SUPPORT (0)
+#endif
+
+#define IS_3G_DAT_UL1_CUSTOM_SUPPORT IS_3G_DYNAMIC_ANTENNA_TUNING_SUPPORT
+#define IS_3G_DAT_RFD_CTRL_EN IS_3G_DYNAMIC_ANTENNA_TUNING_SUPPORT
+#if IS_3G_DAT_UL1_CUSTOM_SUPPORT
+#define IS_3G_RF_DAT_UT_ENABLE 0
+#else
+#define IS_3G_RF_DAT_UT_ENABLE 0
+#endif
+
+#if ((IS_3G_TAS_SUPPORT) && (IS_3G_DAT_RFD_CTRL_EN) && (!IS_3G_UDAT_SUPPORT))
+#define IS_3G_DAT_TAS_COEXIST 1
+#else
+#define IS_3G_DAT_TAS_COEXIST 0
+#endif
+
+#define IS_3G_MPR_EXTEND_SUPPORT (1)
+#define IS_3G_MPR_EXTEND_DBG_EN (0)
+
+//#define IS_RX_LPF_CURR_IN_MANUAL_MODE 1 /*For power saving purpose, MT7206 programing guide_0705.doc, 9.4.2.3 excel file*/
+//Temporary for development and bring up test. shall remove this all when stabel, paul.
+#define MT6169_TO_DO 1
+
+#define IS_3G_RSSI_ABNORMAL_DEBUG 0// 1
+#define IS_UMTS_RF_BSI_LOGGER_ENABLE 1
+#define IS_MT6176_PHONE_CALL (0)
+#if IS_URF_MT6179
+#define IS_MT6179_PHONE_CALL 0
+#endif
+#define IS_FEC_TX_RF_PA_PWR_CTRL_ENABLE 1
+
+/*POC enable ready flag*/
+#define IS_3G_POC_TX_FIIQ_DC_READY 1
+#define IS_3G_POC_RX_IQ_READY 1
+
+/* SWTP feature */
+#define IS_3G_TX_POWER_OFFSET_SUPPORT defined (__TX_POWER_OFFSET_SUPPORT__)
+#define IS_3G_SAR_TX_POWER_BACKOFF_SUPPORT defined (__SAR_TX_POWER_BACKOFF_SUPPORT__)
+
+
+#if IS_3G_TX_POWER_OFFSET_SUPPORT || IS_3G_SAR_TX_POWER_BACKOFF_SUPPORT
+#define IS_3G_SAR_TIMING_PROFILE_ENABLE 0
+#define IS_3G_RF_SAR_UT_ENABLE 0
+#define IS_3G_RF_SWTP_UT_ENABLE 0
+#define IS_3G_RF_COMMON_SAR_UT_ENABLE 0
+#else
+#define IS_3G_SAR_TIMING_PROFILE_ENABLE 0
+#define IS_3G_RF_SAR_UT_ENABLE 0
+#endif
+
+#if IS_3G_SAR_TX_POWER_BACKOFF_SUPPORT
+#define IS_3G_SAR_TX_POWER_OFFSET_CONDI_SUPPORT defined (__SAR_TX_POWER_BACKOFF_COMMON_SAR_SUPPORT__)
+#define IS_3G_SAR_TX_POWER_OFFSET_EXPANSION_SUPPORT defined (__SAR_TX_POWER_BACKOFF_SCENARIO_EXPANSION_SUPPORT__)
+#else
+#define IS_3G_SAR_TX_POWER_OFFSET_CONDI_SUPPORT 0
+#define IS_3G_SAR_TX_POWER_OFFSET_EXPANSION_SUPPORT 0
+#endif
+
+
+#define IS_3G_TX_NSFT_POWER_OFFSET_SUPPORT defined (__WCDMA_TX_NSFT_POWER_OFFSET_SUPPORT__)
+
+/*RX Power Offset feature*/
+#define IS_3G_RX_POWER_OFFSET_SUPPORT defined (__RX_POWER_OFFSET_SUPPORT__)
+/* DRDI support capability */
+#define IS_3G_DRDI_SUPPORT defined(__RF_DRDI_CAPABILITY_SUPPORT__)
+
+#define IS_3G_FDD_RX_PATH_SELECTION_SUPPORT defined(__3G_RX_PATH_SELECTION_SUPPORT__)
+
+#define IS_3G_TAS_ANTENNA_IDX_ON_TEST_SIM 0//defined(__TAS_ANTENNA_IDX_ON_TEST_SIM__)
+
+#define IS_3G_RFIC_BSI_PORT_SWTICH 0
+
+#define IS_3G_TPC9LV_OFFPOWER_SUPPORT 1
+
+#else
+#define IS_RF_DUAL_CELL_SUPPORT 0
+#define IS_RF_RXD_SUPPORT 0
+#define TEAMPERATURE_MEAS_EN 0
+#endif
+
+#define IS_PATHLOSS_EXTENTION 1
+#define IS_3G_7679_GAIN_TABLE_UPDATE 1
+#define IS_3G_RF_NCCA_SUPPORT 0
+#define IS_3G_ELNA_SUPPORT (0)//defined(__L1_EXTERNAL_LNA_SUPPORT__)
+#define IS_3G_FDD_TPC_SPLIT_ENABLE (1)
+
+#if (defined __MD93__) || (defined __MD95__)
+//#define IS_3G_ELNA_IDX_SUPPORT_GEN97_TBD (1)
+#define IS_3G_ELNA_IDX_SUPPORT (1)
+#define IS_3G_ELNA_IDX_DBG_EN (1)
+#define IS_3G_REMOVE_MIPI (1)
+#define IS_3G_VPA_SEL_BY_BAND_SUPPORT (1)
+#else
+//#define IS_3G_ELNA_IDX_SUPPORT_GEN97_TBD (0)
+#define IS_3G_ELNA_IDX_SUPPORT (0)
+#define IS_3G_ELNA_IDX_DBG_EN (0)
+#define IS_3G_REMOVE_MIPI (0)
+#define IS_3G_VPA_SEL_BY_BAND_SUPPORT (0)
+#endif
+
+#define IS_3G_TPC_VM_BPI_FROM_MMRF_SUPPORT (1)
+#define IS_3G_TPC_VM_BPI_FROM_MMRF_DBG_EN (0)
+
+#if (IS_URF_MT6173 || IS_URF_MT6177L)
+#define IS_STX_OUT_OF_LOCK_REPORT 0
+#endif
+
+
+#if defined (__FPGA__)
+#define IS_3G_RF_FPGA_L1S_BRINGUP 0
+#else
+#define IS_3G_RF_FPGA_L1S_BRINGUP 0
+#endif
+
+#define UMTS_POC_RECAL_ENABLE 0
+#define UMTS_POC_DEBUG_TRACE_ENABLE 0
+#define IS_3G_RXDFE_UPDATE_CENTROL_CONTROL 1
+#define IS_3G_FORCE_IDLE_MODE_RXD_SUPPORT 1
+
+#define IS_3G_PMIC_VS1_LOW_POWER_CTRL_SUPPORT defined(__PMIC_VS1_LOW_POWER_CTRL_SUPPORT__)
+
+#define IS_3G_RXD_FE_CONTROL_SUPPORT 1 //defined (__UMTS_FDD_RX_DIVERSITY_CONTROL_SEPARATE__)
+
+#define IS_3G_RXD_FE_CONTROL_DEBUG_TRACE 0
+
+#define IS_3G_FIXED_GAIN_DC_FOR_DATA_DUMP 0
+
+#define IS_3G_FIXED_TX_GAIN 0 // bypass TX FEC for phone call or debug, MIPI TPC DATA must be add to TX DATA manually in ul1d_custom_mipi.c
+
+#define IS_3G_HPUE_SUPPORT 1 //defined(__HPUE_FEATURE_SUPPORT__)
+
+#define IS_3G_MT6295_DFE_READY 0
+
+#define IS_3G_MT6295_RF_TEMPERATURE_WORKAROUND IS_URF_TRINITYE1
+
+#if (defined __MD95__)
+#define IS_3G_RF_VPE_TC_CHECK 1
+#else
+#define IS_3G_RF_VPE_TC_CHECK 0
+#endif/*_MD95_*/
+
+#define IS_3G_FDD_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT defined (__WCDMA_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT__)
+
+#define IS_3G_B5_AND_B19_INDICATOR_SUPPORT defined (__3G_B5_AND_B19_INDICATOR_SUPPORT__)
+
+#if (defined __MD95__)
+#define IS_3G_SUPPORT_8_BANDINDICATOR 1
+#elif (defined __MD97__) || (defined __MD97P__)
+#define IS_3G_SUPPORT_8_BANDINDICATOR (1)
+#elif (defined __MD93__)
+#define IS_3G_SUPPORT_8_BANDINDICATOR 0
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+
+#if (defined __MD93__)
+
+#define __IS_UL1D_ETM_SUPPORT__ 0
+
+#elif (defined __MD95__)
+
+ #if ( ( !defined(L1_SIM) ) && IS_3G_MIPI_SUPPORT )
+#define __IS_UL1D_ETM_SUPPORT__ 1
+ #else
+#define __IS_UL1D_ETM_SUPPORT__ 0
+ #endif // #if ( ( !defined(L1_SIM) ) && IS_3G_MIPI_SUPPORT )
+#elif (defined __MD97__)|| (defined __MD97P__)
+#define __IS_UL1D_ETM_SUPPORT__ 0
+#define __IS_UL1D_ETM_CDF_SUPPORT__ 1
+#else
+#error "[ERROR] Invalid MD generation"
+#endif // #if (defined __MD93__)
+
+#define IS_3G_RFEQ_COEF_SUBBAND_SUPPORT defined (__WCDMA_RFEQ_COEF_SUBBAND_SUPPORT__)
+
+#define IS_3G_AUTO_IQ_DUMP_SUPPORT defined (__WCDMA_RFEQ_COEF_SUBBAND_SUPPORT__)
+
+#define IS_3G_RFEQ_REAL_COEF_TEST defined (__WCDMA_RFEQ_COEF_SUBBAND_SUPPORT__)
+
+#if ((defined __MD93__) || (defined __MD95__))
+#define IS_3G_GEN97_RXDFE_RFC_API_SUPPORT 0
+#else
+#define IS_3G_GEN97_RXDFE_RFC_API_SUPPORT 1
+#endif
+
+#if (defined __MD93__) || (defined __MD95__)
+#define IS_3G_FE_CDF_SUPPORT 0
+#else
+#define IS_3G_FE_CDF_SUPPORT 1
+#endif
+
+#endif /* #ifndef _UL1D_RF_CID_H_ */
+
diff --git a/mcu/interface/l1/ul1/external/ul1d_rf_common.h b/mcu/interface/l1/ul1/external/ul1d_rf_common.h
new file mode 100644
index 0000000..603d4f8
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_rf_common.h
@@ -0,0 +1,2207 @@
+/*******************************************************************************
+* Modification Notice :
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1d_rf_common.h
+ *
+ * Project:
+ * --------
+ * 3G Project Common File
+ *
+ * Description:
+ * ------------
+ * Definition of some of customization setting not defined in ul1d_custom_rf.h
+ * And the stuff needs to be recognized by UL1D external module (wdata.c)
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
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+ *
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+ *
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+ *
+ * removed!
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+ * removed!
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+ *
+ * removed!
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+ *
+ * removed!
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+ * removed!
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+ *
+ * removed!
+ * removed!
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+ * removed!
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+ * removed!
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+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ *
+ * removed!
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+ *
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+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef UL1D_RF_COMMON_H
+#define UL1D_RF_COMMON_H
+
+#include "ul1d_rf_cid.h"
+
+#if defined (UMTS_RF_L1SIM)
+#include "umts_custom_rf_sim.h"
+#else
+#if IS_URF_PCORE
+#include "ul1d_custom_rf.h"
+#endif
+#endif/*L1_SIM*/
+
+/*******************************************************************************
+** Common setting for all RF
+*******************************************************************************/
+/* This part serves as default value of undefined macro constants in ul1d_custom_rf.h */
+/* Aim to accommodate to those difference between RF chips */
+
+#if IS_3G_REMOVE_MIPI
+#ifndef PDATA_UMTSBandNone_PR1_SetDefault
+ #define PDATA_UMTSBandNone_PR1_SetDefault 0
+ #define PDATA_UMTSBandNone_PR2_SetDefault 0
+ #define PDATA_UMTSBandNone_PR3_SetDefault 0
+ #define PDATA_UMTSBandNone_PT1_SetDefault 0
+ #define PDATA_UMTSBandNone_PT2_SetDefault 0
+ #define PDATA_UMTSBandNone_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand1_PR1_SetDefault
+ #define PDATA_UMTSBand1_PR1_SetDefault 0
+ #define PDATA_UMTSBand1_PR2_SetDefault 0
+ #define PDATA_UMTSBand1_PR3_SetDefault 0
+ #define PDATA_UMTSBand1_PT1_SetDefault 0
+ #define PDATA_UMTSBand1_PT2_SetDefault 0
+ #define PDATA_UMTSBand1_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand2_PR1_SetDefault
+ #define PDATA_UMTSBand2_PR1_SetDefault 0
+ #define PDATA_UMTSBand2_PR2_SetDefault 0
+ #define PDATA_UMTSBand2_PR3_SetDefault 0
+ #define PDATA_UMTSBand2_PT1_SetDefault 0
+ #define PDATA_UMTSBand2_PT2_SetDefault 0
+ #define PDATA_UMTSBand2_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand3_PR1_SetDefault
+ #define PDATA_UMTSBand3_PR1_SetDefault 0
+ #define PDATA_UMTSBand3_PR2_SetDefault 0
+ #define PDATA_UMTSBand3_PR3_SetDefault 0
+ #define PDATA_UMTSBand3_PT1_SetDefault 0
+ #define PDATA_UMTSBand3_PT2_SetDefault 0
+ #define PDATA_UMTSBand3_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand4_PR1_SetDefault
+ #define PDATA_UMTSBand4_PR1_SetDefault 0
+ #define PDATA_UMTSBand4_PR2_SetDefault 0
+ #define PDATA_UMTSBand4_PR3_SetDefault 0
+ #define PDATA_UMTSBand4_PT1_SetDefault 0
+ #define PDATA_UMTSBand4_PT2_SetDefault 0
+ #define PDATA_UMTSBand4_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand5_PR1_SetDefault
+ #define PDATA_UMTSBand5_PR1_SetDefault 0
+ #define PDATA_UMTSBand5_PR2_SetDefault 0
+ #define PDATA_UMTSBand5_PR3_SetDefault 0
+ #define PDATA_UMTSBand5_PT1_SetDefault 0
+ #define PDATA_UMTSBand5_PT2_SetDefault 0
+ #define PDATA_UMTSBand5_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand6_PR1_SetDefault
+ #define PDATA_UMTSBand6_PR1_SetDefault 0
+ #define PDATA_UMTSBand6_PR2_SetDefault 0
+ #define PDATA_UMTSBand6_PR3_SetDefault 0
+ #define PDATA_UMTSBand6_PT1_SetDefault 0
+ #define PDATA_UMTSBand6_PT2_SetDefault 0
+ #define PDATA_UMTSBand6_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand7_PR1_SetDefault
+ #define PDATA_UMTSBand7_PR1_SetDefault 0
+ #define PDATA_UMTSBand7_PR2_SetDefault 0
+ #define PDATA_UMTSBand7_PR3_SetDefault 0
+ #define PDATA_UMTSBand7_PT1_SetDefault 0
+ #define PDATA_UMTSBand7_PT2_SetDefault 0
+ #define PDATA_UMTSBand7_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand8_PR1_SetDefault
+ #define PDATA_UMTSBand8_PR1_SetDefault 0
+ #define PDATA_UMTSBand8_PR2_SetDefault 0
+ #define PDATA_UMTSBand8_PR3_SetDefault 0
+ #define PDATA_UMTSBand8_PT1_SetDefault 0
+ #define PDATA_UMTSBand8_PT2_SetDefault 0
+ #define PDATA_UMTSBand8_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand9_PR1_SetDefault
+ #define PDATA_UMTSBand9_PR1_SetDefault 0
+ #define PDATA_UMTSBand9_PR2_SetDefault 0
+ #define PDATA_UMTSBand9_PR3_SetDefault 0
+ #define PDATA_UMTSBand9_PT1_SetDefault 0
+ #define PDATA_UMTSBand9_PT2_SetDefault 0
+ #define PDATA_UMTSBand9_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand10_PR1_SetDefault
+ #define PDATA_UMTSBand10_PR1_SetDefault 0
+ #define PDATA_UMTSBand10_PR2_SetDefault 0
+ #define PDATA_UMTSBand10_PR3_SetDefault 0
+ #define PDATA_UMTSBand10_PT1_SetDefault 0
+ #define PDATA_UMTSBand10_PT2_SetDefault 0
+ #define PDATA_UMTSBand10_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand11_PR1_SetDefault
+ #define PDATA_UMTSBand11_PR1_SetDefault 0
+ #define PDATA_UMTSBand11_PR2_SetDefault 0
+ #define PDATA_UMTSBand11_PR3_SetDefault 0
+ #define PDATA_UMTSBand11_PT1_SetDefault 0
+ #define PDATA_UMTSBand11_PT2_SetDefault 0
+ #define PDATA_UMTSBand11_PT3_SetDefault 0
+#endif
+#ifndef PDATA_UMTSBand19_PR1_SetDefault
+ #define PDATA_UMTSBand19_PR1_SetDefault 0
+ #define PDATA_UMTSBand19_PR2_SetDefault 0
+ #define PDATA_UMTSBand19_PR3_SetDefault 0
+ #define PDATA_UMTSBand19_PT1_SetDefault 0
+ #define PDATA_UMTSBand19_PT2_SetDefault 0
+ #define PDATA_UMTSBand19_PT3_SetDefault 0
+#endif
+
+#ifndef PDATA_UMTSBand1_PR2B_SetDefault
+ #define PDATA_UMTSBand1_PR2B_SetDefault PDATA_UMTSBand1_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand1_PR3A_SetDefault
+ #define PDATA_UMTSBand1_PR3A_SetDefault PDATA_UMTSBand1_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand1_PT2B_SetDefault
+ #define PDATA_UMTSBand1_PT2B_SetDefault PDATA_UMTSBand1_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand1_PT3A_SetDefault
+ #define PDATA_UMTSBand1_PT3A_SetDefault PDATA_UMTSBand1_PT3_SetDefault
+#endif
+
+#ifndef PDATA_UMTSBand2_PR2B_SetDefault
+ #define PDATA_UMTSBand2_PR2B_SetDefault PDATA_UMTSBand2_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand2_PR3A_SetDefault
+ #define PDATA_UMTSBand2_PR3A_SetDefault PDATA_UMTSBand2_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand2_PT2B_SetDefault
+ #define PDATA_UMTSBand2_PT2B_SetDefault PDATA_UMTSBand2_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand2_PT3A_SetDefault
+ #define PDATA_UMTSBand2_PT3A_SetDefault PDATA_UMTSBand2_PT3_SetDefault
+#endif
+
+#ifndef PDATA_UMTSBand3_PR2B_SetDefault
+ #define PDATA_UMTSBand3_PR2B_SetDefault PDATA_UMTSBand3_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand3_PR3A_SetDefault
+ #define PDATA_UMTSBand3_PR3A_SetDefault PDATA_UMTSBand3_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand3_PT2B_SetDefault
+ #define PDATA_UMTSBand3_PT2B_SetDefault PDATA_UMTSBand3_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand3_PT3A_SetDefault
+ #define PDATA_UMTSBand3_PT3A_SetDefault PDATA_UMTSBand3_PT3_SetDefault
+#endif
+
+#ifndef PDATA_UMTSBand4_PR2B_SetDefault
+ #define PDATA_UMTSBand4_PR2B_SetDefault PDATA_UMTSBand4_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand4_PR3A_SetDefault
+ #define PDATA_UMTSBand4_PR3A_SetDefault PDATA_UMTSBand4_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand4_PT2B_SetDefault
+ #define PDATA_UMTSBand4_PT2B_SetDefault PDATA_UMTSBand4_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand4_PT3A_SetDefault
+ #define PDATA_UMTSBand4_PT3A_SetDefault PDATA_UMTSBand4_PT3_SetDefault
+#endif
+
+#ifndef PDATA_UMTSBand5_PR2B_SetDefault
+ #define PDATA_UMTSBand5_PR2B_SetDefault PDATA_UMTSBand5_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand5_PR3A_SetDefault
+ #define PDATA_UMTSBand5_PR3A_SetDefault PDATA_UMTSBand5_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand5_PT2B_SetDefault
+ #define PDATA_UMTSBand5_PT2B_SetDefault PDATA_UMTSBand5_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand5_PT3A_SetDefault
+ #define PDATA_UMTSBand5_PT3A_SetDefault PDATA_UMTSBand5_PT3_SetDefault
+#endif
+
+#ifndef PDATA_UMTSBand6_PR2B_SetDefault
+ #define PDATA_UMTSBand6_PR2B_SetDefault PDATA_UMTSBand6_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand6_PR3A_SetDefault
+ #define PDATA_UMTSBand6_PR3A_SetDefault PDATA_UMTSBand6_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand6_PT2B_SetDefault
+ #define PDATA_UMTSBand6_PT2B_SetDefault PDATA_UMTSBand6_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand6_PT3A_SetDefault
+ #define PDATA_UMTSBand6_PT3A_SetDefault PDATA_UMTSBand6_PT3_SetDefault
+#endif
+
+#ifndef PDATA_UMTSBand7_PR2B_SetDefault
+ #define PDATA_UMTSBand7_PR2B_SetDefault PDATA_UMTSBand7_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand7_PR3A_SetDefault
+ #define PDATA_UMTSBand7_PR3A_SetDefault PDATA_UMTSBand7_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand7_PT2B_SetDefault
+ #define PDATA_UMTSBand7_PT2B_SetDefault PDATA_UMTSBand7_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand7_PT3A_SetDefault
+ #define PDATA_UMTSBand7_PT3A_SetDefault PDATA_UMTSBand7_PT3_SetDefault
+#endif
+
+#ifndef PDATA_UMTSBand8_PR2B_SetDefault
+ #define PDATA_UMTSBand8_PR2B_SetDefault PDATA_UMTSBand8_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand8_PR3A_SetDefault
+ #define PDATA_UMTSBand8_PR3A_SetDefault PDATA_UMTSBand8_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand8_PT2B_SetDefault
+ #define PDATA_UMTSBand8_PT2B_SetDefault PDATA_UMTSBand8_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand8_PT3A_SetDefault
+ #define PDATA_UMTSBand8_PT3A_SetDefault PDATA_UMTSBand8_PT3_SetDefault
+#endif
+
+#ifndef PDATA_UMTSBand9_PR2B_SetDefault
+ #define PDATA_UMTSBand9_PR2B_SetDefault PDATA_UMTSBand9_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand9_PR3A_SetDefault
+ #define PDATA_UMTSBand9_PR3A_SetDefault PDATA_UMTSBand9_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand9_PT2B_SetDefault
+ #define PDATA_UMTSBand9_PT2B_SetDefault PDATA_UMTSBand9_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand9_PT3A_SetDefault
+ #define PDATA_UMTSBand9_PT3A_SetDefault PDATA_UMTSBand9_PT3_SetDefault
+#endif
+
+#ifndef PDATA_UMTSBand10_PR2B_SetDefault
+ #define PDATA_UMTSBand10_PR2B_SetDefault PDATA_UMTSBand10_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand10_PR3A_SetDefault
+ #define PDATA_UMTSBand10_PR3A_SetDefault PDATA_UMTSBand10_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand10_PT2B_SetDefault
+ #define PDATA_UMTSBand10_PT2B_SetDefault PDATA_UMTSBand10_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand10_PT3A_SetDefault
+ #define PDATA_UMTSBand10_PT3A_SetDefault PDATA_UMTSBand10_PT3_SetDefault
+#endif
+
+#ifndef PDATA_UMTSBand11_PR2B_SetDefault
+ #define PDATA_UMTSBand11_PR2B_SetDefault PDATA_UMTSBand11_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand11_PR3A_SetDefault
+ #define PDATA_UMTSBand11_PR3A_SetDefault PDATA_UMTSBand11_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand11_PT2B_SetDefault
+ #define PDATA_UMTSBand11_PT2B_SetDefault PDATA_UMTSBand11_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand11_PT3A_SetDefault
+ #define PDATA_UMTSBand11_PT3A_SetDefault PDATA_UMTSBand11_PT3_SetDefault
+#endif
+
+#ifndef PDATA_UMTSBand19_PR2B_SetDefault
+ #define PDATA_UMTSBand19_PR2B_SetDefault PDATA_UMTSBand19_PR2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand19_PR3A_SetDefault
+ #define PDATA_UMTSBand19_PR3A_SetDefault PDATA_UMTSBand19_PR3_SetDefault
+#endif
+#ifndef PDATA_UMTSBand19_PT2B_SetDefault
+ #define PDATA_UMTSBand19_PT2B_SetDefault PDATA_UMTSBand19_PT2_SetDefault
+#endif
+#ifndef PDATA_UMTSBand19_PT3A_SetDefault
+ #define PDATA_UMTSBand19_PT3A_SetDefault PDATA_UMTSBand19_PT3_SetDefault
+#endif
+
+#if IS_3G_RXD_FE_CONTROL_SUPPORT
+#ifndef PDATA2_UMTSBandNone_PR1_SetDefault
+ #define PDATA2_UMTSBandNone_PR1_SetDefault 0
+ #define PDATA2_UMTSBandNone_PR2_SetDefault 0
+ #define PDATA2_UMTSBandNone_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand1_PR1_SetDefault
+ #define PDATA2_UMTSBand1_PR1_SetDefault 0
+ #define PDATA2_UMTSBand1_PR2_SetDefault 0
+ #define PDATA2_UMTSBand1_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand2_PR1_SetDefault
+ #define PDATA2_UMTSBand2_PR1_SetDefault 0
+ #define PDATA2_UMTSBand2_PR2_SetDefault 0
+ #define PDATA2_UMTSBand2_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand3_PR1_SetDefault
+ #define PDATA2_UMTSBand3_PR1_SetDefault 0
+ #define PDATA2_UMTSBand3_PR2_SetDefault 0
+ #define PDATA2_UMTSBand3_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand4_PR1_SetDefault
+ #define PDATA2_UMTSBand4_PR1_SetDefault 0
+ #define PDATA2_UMTSBand4_PR2_SetDefault 0
+ #define PDATA2_UMTSBand4_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand5_PR1_SetDefault
+ #define PDATA2_UMTSBand5_PR1_SetDefault 0
+ #define PDATA2_UMTSBand5_PR2_SetDefault 0
+ #define PDATA2_UMTSBand5_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand6_PR1_SetDefault
+ #define PDATA2_UMTSBand6_PR1_SetDefault 0
+ #define PDATA2_UMTSBand6_PR2_SetDefault 0
+ #define PDATA2_UMTSBand6_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand7_PR1_SetDefault
+ #define PDATA2_UMTSBand7_PR1_SetDefault 0
+ #define PDATA2_UMTSBand7_PR2_SetDefault 0
+ #define PDATA2_UMTSBand7_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand8_PR1_SetDefault
+ #define PDATA2_UMTSBand8_PR1_SetDefault 0
+ #define PDATA2_UMTSBand8_PR2_SetDefault 0
+ #define PDATA2_UMTSBand8_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand9_PR1_SetDefault
+ #define PDATA2_UMTSBand9_PR1_SetDefault 0
+ #define PDATA2_UMTSBand9_PR2_SetDefault 0
+ #define PDATA2_UMTSBand9_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand10_PR1_SetDefault
+ #define PDATA2_UMTSBand10_PR1_SetDefault 0
+ #define PDATA2_UMTSBand10_PR2_SetDefault 0
+ #define PDATA2_UMTSBand10_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand11_PR1_SetDefault
+ #define PDATA2_UMTSBand11_PR1_SetDefault 0
+ #define PDATA2_UMTSBand11_PR2_SetDefault 0
+ #define PDATA2_UMTSBand11_PR3_SetDefault 0
+#endif
+#ifndef PDATA2_UMTSBand19_PR1_SetDefault
+ #define PDATA2_UMTSBand19_PR1_SetDefault 0
+ #define PDATA2_UMTSBand19_PR2_SetDefault 0
+ #define PDATA2_UMTSBand19_PR3_SetDefault 0
+#endif
+
+#ifndef PDATA2_UMTSBand1_PR2B_SetDefault
+ #define PDATA2_UMTSBand1_PR2B_SetDefault PDATA2_UMTSBand1_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand1_PR3A_SetDefault
+ #define PDATA2_UMTSBand1_PR3A_SetDefault PDATA2_UMTSBand1_PR3_SetDefault
+#endif
+
+#ifndef PDATA2_UMTSBand2_PR2B_SetDefault
+ #define PDATA2_UMTSBand2_PR2B_SetDefault PDATA2_UMTSBand2_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand2_PR3A_SetDefault
+ #define PDATA2_UMTSBand2_PR3A_SetDefault PDATA2_UMTSBand2_PR3_SetDefault
+#endif
+
+#ifndef PDATA2_UMTSBand3_PR2B_SetDefault
+ #define PDATA2_UMTSBand3_PR2B_SetDefault PDATA2_UMTSBand3_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand3_PR3A_SetDefault
+ #define PDATA2_UMTSBand3_PR3A_SetDefault PDATA2_UMTSBand3_PR3_SetDefault
+#endif
+
+#ifndef PDATA2_UMTSBand4_PR2B_SetDefault
+ #define PDATA2_UMTSBand4_PR2B_SetDefault PDATA2_UMTSBand4_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand4_PR3A_SetDefault
+ #define PDATA2_UMTSBand4_PR3A_SetDefault PDATA2_UMTSBand4_PR3_SetDefault
+#endif
+
+#ifndef PDATA2_UMTSBand5_PR2B_SetDefault
+ #define PDATA2_UMTSBand5_PR2B_SetDefault PDATA2_UMTSBand5_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand5_PR3A_SetDefault
+ #define PDATA2_UMTSBand5_PR3A_SetDefault PDATA2_UMTSBand5_PR3_SetDefault
+#endif
+
+#ifndef PDATA2_UMTSBand6_PR2B_SetDefault
+ #define PDATA2_UMTSBand6_PR2B_SetDefault PDATA2_UMTSBand6_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand6_PR3A_SetDefault
+ #define PDATA2_UMTSBand6_PR3A_SetDefault PDATA2_UMTSBand6_PR3_SetDefault
+#endif
+
+#ifndef PDATA2_UMTSBand7_PR2B_SetDefault
+ #define PDATA2_UMTSBand7_PR2B_SetDefault PDATA2_UMTSBand7_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand7_PR3A_SetDefault
+ #define PDATA2_UMTSBand7_PR3A_SetDefault PDATA2_UMTSBand7_PR3_SetDefault
+#endif
+
+#ifndef PDATA2_UMTSBand8_PR2B_SetDefault
+ #define PDATA2_UMTSBand8_PR2B_SetDefault PDATA2_UMTSBand8_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand8_PR3A_SetDefault
+ #define PDATA2_UMTSBand8_PR3A_SetDefault PDATA2_UMTSBand8_PR3_SetDefault
+#endif
+
+#ifndef PDATA2_UMTSBand9_PR2B_SetDefault
+ #define PDATA2_UMTSBand9_PR2B_SetDefault PDATA2_UMTSBand9_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand9_PR3A_SetDefault
+ #define PDATA2_UMTSBand9_PR3A_SetDefault PDATA2_UMTSBand9_PR3_SetDefault
+#endif
+
+#ifndef PDATA2_UMTSBand10_PR2B_SetDefault
+ #define PDATA2_UMTSBand10_PR2B_SetDefault PDATA2_UMTSBand10_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand10_PR3A_SetDefault
+ #define PDATA2_UMTSBand10_PR3A_SetDefault PDATA2_UMTSBand10_PR3_SetDefault
+#endif
+
+#ifndef PDATA2_UMTSBand11_PR2B_SetDefault
+ #define PDATA2_UMTSBand11_PR2B_SetDefault PDATA2_UMTSBand11_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand11_PR3A_SetDefault
+ #define PDATA2_UMTSBand11_PR3A_SetDefault PDATA2_UMTSBand11_PR3_SetDefault
+#endif
+
+#ifndef PDATA2_UMTSBand19_PR2B_SetDefault
+ #define PDATA2_UMTSBand19_PR2B_SetDefault PDATA2_UMTSBand19_PR2_SetDefault
+#endif
+#ifndef PDATA2_UMTSBand19_PR3A_SetDefault
+ #define PDATA2_UMTSBand19_PR3A_SetDefault PDATA2_UMTSBand19_PR3_SetDefault
+#endif
+
+#else
+//Add for RXD
+#ifndef PDATA2_BAND1_PR1
+ #define PDATA2_BAND1_PR1 0
+ #define PDATA2_BAND1_PR2 0
+ #define PDATA2_BAND1_PR3 0
+#endif
+#ifndef PDATA2_BAND2_PR1
+ #define PDATA2_BAND2_PR1 0
+ #define PDATA2_BAND2_PR2 0
+ #define PDATA2_BAND2_PR3 0
+#endif
+#ifndef PDATA2_BAND3_PR1
+ #define PDATA2_BAND3_PR1 0
+ #define PDATA2_BAND3_PR2 0
+ #define PDATA2_BAND3_PR3 0
+#endif
+#ifndef PDATA2_BAND4_PR1
+ #define PDATA2_BAND4_PR1 0
+ #define PDATA2_BAND4_PR2 0
+ #define PDATA2_BAND4_PR3 0
+#endif
+#ifndef PDATA2_BAND5_PR1
+ #define PDATA2_BAND5_PR1 0
+ #define PDATA2_BAND5_PR2 0
+ #define PDATA2_BAND5_PR3 0
+#endif
+#ifndef PDATA2_BAND6_PR1
+ #define PDATA2_BAND6_PR1 0
+ #define PDATA2_BAND6_PR2 0
+ #define PDATA2_BAND6_PR3 0
+#endif
+#ifndef PDATA2_BAND7_PR1
+ #define PDATA2_BAND7_PR1 0
+ #define PDATA2_BAND7_PR2 0
+ #define PDATA2_BAND7_PR3 0
+#endif
+#ifndef PDATA2_BAND8_PR1
+ #define PDATA2_BAND8_PR1 0
+ #define PDATA2_BAND8_PR2 0
+ #define PDATA2_BAND8_PR3 0
+#endif
+#ifndef PDATA2_BAND9_PR1
+ #define PDATA2_BAND9_PR1 0
+ #define PDATA2_BAND9_PR2 0
+ #define PDATA2_BAND9_PR3 0
+#endif
+#ifndef PDATA2_BAND10_PR1
+ #define PDATA2_BAND10_PR1 0
+ #define PDATA2_BAND10_PR2 0
+ #define PDATA2_BAND10_PR3 0
+#endif
+#ifndef PDATA2_BAND11_PR1
+ #define PDATA2_BAND11_PR1 0
+ #define PDATA2_BAND11_PR2 0
+ #define PDATA2_BAND11_PR3 0
+#endif
+#ifndef PDATA2_BAND19_PR1
+ #define PDATA2_BAND19_PR1 0
+ #define PDATA2_BAND19_PR2 0
+ #define PDATA2_BAND19_PR3 0
+#endif
+
+/* Define PDATA2_BANDx_PRx */
+#ifndef PDATA2_BAND1_PR2B
+ #define PDATA2_BAND1_PR2B PDATA2_BAND1_PR2
+#endif
+#ifndef PDATA2_BAND1_PR3A
+ #define PDATA2_BAND1_PR3A PDATA2_BAND1_PR3
+#endif
+#ifndef PDATA2_BAND2_PR2B
+ #define PDATA2_BAND2_PR2B PDATA2_BAND2_PR2
+#endif
+#ifndef PDATA2_BAND2_PR3A
+ #define PDATA2_BAND2_PR3A PDATA2_BAND2_PR3
+#endif
+#ifndef PDATA2_BAND3_PR2B
+ #define PDATA2_BAND3_PR2B PDATA2_BAND3_PR2
+#endif
+#ifndef PDATA2_BAND3_PR3A
+ #define PDATA2_BAND3_PR3A PDATA2_BAND3_PR3
+#endif
+#ifndef PDATA2_BAND4_PR2B
+ #define PDATA2_BAND4_PR2B PDATA2_BAND4_PR2
+#endif
+#ifndef PDATA2_BAND4_PR3A
+ #define PDATA2_BAND4_PR3A PDATA2_BAND4_PR3
+#endif
+#ifndef PDATA2_BAND5_PR2B
+ #define PDATA2_BAND5_PR2B PDATA2_BAND5_PR2
+#endif
+#ifndef PDATA2_BAND5_PR3A
+ #define PDATA2_BAND5_PR3A PDATA2_BAND5_PR3
+#endif
+#ifndef PDATA2_BAND6_PR2B
+ #define PDATA2_BAND6_PR2B PDATA2_BAND6_PR2
+#endif
+#ifndef PDATA2_BAND6_PR3A
+ #define PDATA2_BAND6_PR3A PDATA2_BAND6_PR3
+#endif
+#ifndef PDATA2_BAND7_PR2B
+ #define PDATA2_BAND7_PR2B PDATA2_BAND7_PR2
+#endif
+#ifndef PDATA2_BAND7_PR3A
+ #define PDATA2_BAND7_PR3A PDATA2_BAND7_PR3
+#endif
+#ifndef PDATA2_BAND8_PR2B
+ #define PDATA2_BAND8_PR2B PDATA2_BAND8_PR2
+#endif
+#ifndef PDATA2_BAND8_PR3A
+ #define PDATA2_BAND8_PR3A PDATA2_BAND8_PR3
+#endif
+#ifndef PDATA2_BAND9_PR2B
+ #define PDATA2_BAND9_PR2B PDATA2_BAND9_PR2
+#endif
+#ifndef PDATA2_BAND9_PR3A
+ #define PDATA2_BAND9_PR3A PDATA2_BAND9_PR3
+#endif
+#ifndef PDATA2_BAND10_PR2B
+ #define PDATA2_BAND10_PR2B PDATA2_BAND10_PR2
+#endif
+#ifndef PDATA2_BAND10_PR3A
+ #define PDATA2_BAND10_PR3A PDATA2_BAND10_PR3
+#endif
+#ifndef PDATA2_BAND11_PR2B
+ #define PDATA2_BAND11_PR2B PDATA2_BAND11_PR2
+#endif
+#ifndef PDATA2_BAND11_PR3A
+ #define PDATA2_BAND11_PR3A PDATA2_BAND11_PR3
+#endif
+#ifndef PDATA2_BAND19_PR2B
+ #define PDATA2_BAND19_PR2B PDATA2_BAND19_PR2
+#endif
+#ifndef PDATA2_BAND19_PR3A
+ #define PDATA2_BAND19_PR3A PDATA2_BAND19_PR3
+#endif
+#endif /*end of IS_3G_RXD_FE_CONTROL_SUPPORT*/
+
+/* Define BANDx_CHANNEL_SEL */
+#ifndef UMTSBandNone_CHANNEL_SEL_SetDefault
+ #define UMTSBandNone_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand1_CHANNEL_SEL_SetDefault
+ #define UMTSBand1_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand2_CHANNEL_SEL_SetDefault
+ #define UMTSBand2_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand3_CHANNEL_SEL_SetDefault
+ #define UMTSBand3_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand4_CHANNEL_SEL_SetDefault
+ #define UMTSBand4_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand5_CHANNEL_SEL_SetDefault
+ #define UMTSBand5_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand6_CHANNEL_SEL_SetDefault
+ #define UMTSBand6_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand8_CHANNEL_SEL_SetDefault
+ #define UMTSBand8_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand9_CHANNEL_SEL_SetDefault
+ #define UMTSBand9_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand10_CHANNEL_SEL_SetDefault
+ #define UMTSBand10_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand11_CHANNEL_SEL_SetDefault
+ #define UMTSBand11_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand19_CHANNEL_SEL_SetDefault
+ #define UMTSBand19_CHANNEL_SEL_SetDefault NON_USED_BAND
+#endif
+
+/* Define BANDx_CHANNEL2_SEL */
+#ifndef UMTSBandNone_CHANNEL2_SEL_SetDefault
+ #define UMTSBandNone_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand1_CHANNEL2_SEL_SetDefault
+ #define UMTSBand1_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand2_CHANNEL2_SEL_SetDefault
+ #define UMTSBand2_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand3_CHANNEL2_SEL_SetDefault
+ #define UMTSBand3_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand4_CHANNEL2_SEL_SetDefault
+ #define UMTSBand4_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand5_CHANNEL2_SEL_SetDefault
+ #define UMTSBand5_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand6_CHANNEL2_SEL_SetDefault
+ #define UMTSBand6_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand8_CHANNEL2_SEL_SetDefault
+ #define UMTSBand8_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand9_CHANNEL2_SEL_SetDefault
+ #define UMTSBand9_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand10_CHANNEL2_SEL_SetDefault
+ #define UMTSBand10_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand11_CHANNEL2_SEL_SetDefault
+ #define UMTSBand11_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand19_CHANNEL2_SEL_SetDefault
+ #define UMTSBand19_CHANNEL2_SEL_SetDefault NON_USED_BAND
+#endif
+
+/* Define Bandx_OUTPUT_SEL */
+#ifndef UMTSBandNone_OUTPUT_SEL_SetDefault
+ #define UMTSBandNone_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand1_OUTPUT_SEL_SetDefault
+ #define UMTSBand1_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand2_OUTPUT_SEL_SetDefault
+ #define UMTSBand2_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand3_OUTPUT_SEL_SetDefault
+ #define UMTSBand3_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand4_OUTPUT_SEL_SetDefault
+ #define UMTSBand4_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand5_OUTPUT_SEL_SetDefault
+ #define UMTSBand5_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand6_OUTPUT_SEL_SetDefault
+ #define UMTSBand6_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand8_OUTPUT_SEL_SetDefault
+ #define UMTSBand8_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand9_OUTPUT_SEL_SetDefault
+ #define UMTSBand9_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand10_OUTPUT_SEL_SetDefault
+ #define UMTSBand10_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand11_OUTPUT_SEL_SetDefault
+ #define UMTSBand11_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand19_OUTPUT_SEL_SetDefault
+ #define UMTSBand19_OUTPUT_SEL_SetDefault NON_USED_BAND
+#endif
+
+/* Define Bandx_OUTPUT_DET_SEL */
+#ifndef UMTSBandNone_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBandNone_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand1_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBand1_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand2_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBand2_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand3_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBand3_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand4_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBand4_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand5_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBand5_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand6_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBand6_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand8_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBand8_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand9_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBand9_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand10_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBand10_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand11_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBand11_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+#ifndef UMTSBand19_OUTPUT_DET_SEL_SetDefault
+ #define UMTSBand19_OUTPUT_DET_SEL_SetDefault NON_USED_BAND
+#endif
+
+#else
+//Useless after Gen97
+#endif /*IS_3G_REMOVE_MIPI*/
+
+//For MPR Setting
+#ifndef MPR_BACK_OFF_HSDPA_BAND1_SetDefault
+ #define MPR_BACK_OFF_HSDPA_BAND1_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSDPA_BAND2_SetDefault
+ #define MPR_BACK_OFF_HSDPA_BAND2_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSDPA_BAND3_SetDefault
+ #define MPR_BACK_OFF_HSDPA_BAND3_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSDPA_BAND4_SetDefault
+ #define MPR_BACK_OFF_HSDPA_BAND4_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSDPA_BAND5_SetDefault
+ #define MPR_BACK_OFF_HSDPA_BAND5_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSDPA_BAND6_SetDefault
+ #define MPR_BACK_OFF_HSDPA_BAND6_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSDPA_BAND8_SetDefault
+ #define MPR_BACK_OFF_HSDPA_BAND8_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSDPA_BAND9_SetDefault
+ #define MPR_BACK_OFF_HSDPA_BAND9_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSDPA_BAND10_SetDefault
+ #define MPR_BACK_OFF_HSDPA_BAND10_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSDPA_BAND11_SetDefault
+ #define MPR_BACK_OFF_HSDPA_BAND11_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSDPA_BAND19_SetDefault
+ #define MPR_BACK_OFF_HSDPA_BAND19_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSUPA_BAND1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND1_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSUPA_BAND2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND2_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSUPA_BAND3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND3_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSUPA_BAND4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND4_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSUPA_BAND5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND5_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSUPA_BAND6_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND6_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSUPA_BAND8_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND8_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSUPA_BAND9_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND9_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSUPA_BAND10_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND10_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSUPA_BAND11_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND11_SetDefault MPRSetting2
+#endif
+#ifndef MPR_BACK_OFF_HSUPA_BAND19_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND19_SetDefault MPRSetting2
+#endif
+
+#if IS_3G_MPR_EXTEND_SUPPORT
+
+/*SUB 1 Default*/
+#ifndef MPR_BACK_OFF_HSUPA_BAND1_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND1_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND2_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND2_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND3_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND3_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND4_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND4_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND5_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND5_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND6_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND6_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND7_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND7_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND8_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND8_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND9_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND9_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND10_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND10_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND11_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND11_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND12_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND12_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND13_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND13_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND14_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND14_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND15_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND15_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND16_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND16_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND17_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND17_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND18_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND18_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND19_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND19_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND20_SUB_1_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND20_SUB_1_SetDefault MPRSetting_SUB_0
+#endif
+//======================================================================
+
+
+//SUB 2 Default
+//======================================================================
+#ifndef MPR_BACK_OFF_HSUPA_BAND1_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND1_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND2_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND2_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND3_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND3_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND4_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND4_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND5_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND5_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND6_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND6_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND7_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND7_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND8_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND8_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND9_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND9_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND10_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND10_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND11_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND11_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND12_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND12_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND13_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND13_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND14_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND14_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND15_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND15_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND16_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND16_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND17_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND17_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND18_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND18_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND19_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND19_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND20_SUB_2_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND20_SUB_2_SetDefault MPRSetting_SUB_0
+#endif
+//======================================================================
+
+
+//SUB 3 Default
+//======================================================================
+#ifndef MPR_BACK_OFF_HSUPA_BAND1_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND1_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND2_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND2_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND3_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND3_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND4_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND4_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND5_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND5_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND6_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND6_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND7_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND7_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND8_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND8_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND9_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND9_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND10_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND10_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND11_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND11_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND12_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND12_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND13_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND13_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND14_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND14_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND15_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND15_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND16_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND16_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND17_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND17_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND18_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND18_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND19_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND19_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND20_SUB_3_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND20_SUB_3_SetDefault MPRSetting_SUB_0
+#endif
+//======================================================================
+
+
+//SUB 4 Default
+//======================================================================
+#ifndef MPR_BACK_OFF_HSUPA_BAND1_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND1_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND2_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND2_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND3_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND3_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND4_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND4_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND5_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND5_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND6_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND6_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND7_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND7_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND8_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND8_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND9_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND9_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND10_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND10_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND11_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND11_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND12_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND12_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND13_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND13_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND14_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND14_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND15_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND15_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND16_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND16_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND17_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND17_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND18_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND18_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND19_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND19_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND20_SUB_4_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND20_SUB_4_SetDefault MPRSetting_SUB_0
+#endif
+//======================================================================
+
+//SUB 5 Default
+//======================================================================
+#ifndef MPR_BACK_OFF_HSUPA_BAND1_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND1_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND2_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND2_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND3_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND3_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND4_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND4_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND5_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND5_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND6_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND6_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND7_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND7_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND8_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND8_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND9_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND9_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND10_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND10_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND11_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND11_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND12_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND12_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND13_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND13_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND14_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND14_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND15_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND15_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND16_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND16_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND17_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND17_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND18_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND18_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND19_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND19_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+
+#ifndef MPR_BACK_OFF_HSUPA_BAND20_SUB_5_SetDefault
+ #define MPR_BACK_OFF_HSUPA_BAND20_SUB_5_SetDefault MPRSetting_SUB_0
+#endif
+//======================================================================
+
+#ifndef R6_MPR_SUB_EN_SetDefault
+ #define R6_MPR_SUB_EN_SetDefault KAL_FALSE
+#endif
+
+#endif//IS_3G_MPR_EXTEND_SUPPORT
+
+/* Define RX_HIGHBAND3_INDICATOR for 4-bands users (MT6572/82) */
+#ifndef RX_HIGHBAND3_INDICATOR
+ #define RX_HIGHBAND3_INDICATOR UMTSBandNone
+#endif
+/* Define RX_LOWBAND2_INDICATOR for 3-bands (MT6290 Dongle, HW limitation) */
+#ifndef RX_LOWBAND2_INDICATOR
+ #define RX_LOWBAND2_INDICATOR UMTSBandNone
+#endif
+
+#define MPR_BACK_OFF_HSDPA_BAND7 MPRSetting2
+#define MPR_BACK_OFF_HSDPA_BAND12 MPRSetting2
+#define MPR_BACK_OFF_HSDPA_BAND13 MPRSetting2
+#define MPR_BACK_OFF_HSDPA_BAND14 MPRSetting2
+#define MPR_BACK_OFF_HSDPA_BAND15 MPRSetting2
+#define MPR_BACK_OFF_HSDPA_BAND16 MPRSetting2
+#define MPR_BACK_OFF_HSDPA_BAND17 MPRSetting2
+#define MPR_BACK_OFF_HSDPA_BAND18 MPRSetting2
+#define MPR_BACK_OFF_HSDPA_BAND20 MPRSetting2
+#define MPR_BACK_OFF_HSUPA_BAND7 MPRSetting2
+#define MPR_BACK_OFF_HSUPA_BAND12 MPRSetting2
+#define MPR_BACK_OFF_HSUPA_BAND13 MPRSetting2
+#define MPR_BACK_OFF_HSUPA_BAND14 MPRSetting2
+#define MPR_BACK_OFF_HSUPA_BAND15 MPRSetting2
+#define MPR_BACK_OFF_HSUPA_BAND16 MPRSetting2
+#define MPR_BACK_OFF_HSUPA_BAND17 MPRSetting2
+#define MPR_BACK_OFF_HSUPA_BAND18 MPRSetting2
+#define MPR_BACK_OFF_HSUPA_BAND20 MPRSetting2
+
+#ifndef ULTRA_LOW_COST_EN_SetDefault
+ #define ULTRA_LOW_COST_EN_SetDefault KAL_FALSE
+#endif
+
+#ifndef TEAMPERATURE_MEAS_EN
+ #define TEAMPERATURE_MEAS_EN KAL_FALSE
+#endif
+
+#ifndef VPA_FPWM_MODE
+ #define VPA_FPWM_MODE KAL_FALSE
+#endif
+
+#if IS_3G_ELNA_IDX_SUPPORT
+/* ------------------- RX eLNA setting -------------------- */
+#ifndef UMTSBand1_RX_eLNA_IDX_SetDefault
+ #define UMTSBand1_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand2_RX_eLNA_IDX_SetDefault
+ #define UMTSBand2_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand3_RX_eLNA_IDX_SetDefault
+ #define UMTSBand3_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand4_RX_eLNA_IDX_SetDefault
+ #define UMTSBand4_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand5_RX_eLNA_IDX_SetDefault
+ #define UMTSBand5_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand6_RX_eLNA_IDX_SetDefault
+ #define UMTSBand6_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand7_RX_eLNA_IDX_SetDefault
+ #define UMTSBand7_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand8_RX_eLNA_IDX_SetDefault
+ #define UMTSBand8_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand9_RX_eLNA_IDX_SetDefault
+ #define UMTSBand9_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand10_RX_eLNA_IDX_SetDefault
+ #define UMTSBand10_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand11_RX_eLNA_IDX_SetDefault
+ #define UMTSBand11_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand12_RX_eLNA_IDX_SetDefault
+ #define UMTSBand12_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand13_RX_eLNA_IDX_SetDefault
+ #define UMTSBand13_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand14_RX_eLNA_IDX_SetDefault
+ #define UMTSBand14_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand15_RX_eLNA_IDX_SetDefault
+ #define UMTSBand15_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand16_RX_eLNA_IDX_SetDefault
+ #define UMTSBand16_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand17_RX_eLNA_IDX_SetDefault
+ #define UMTSBand17_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand18_RX_eLNA_IDX_SetDefault
+ #define UMTSBand18_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand19_RX_eLNA_IDX_SetDefault
+ #define UMTSBand19_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand20_RX_eLNA_IDX_SetDefault
+ #define UMTSBand20_RX_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+/* ------------------- RXD eLNA setting ------------------- */
+#ifndef UMTSBand1_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand1_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand2_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand2_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand3_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand3_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand4_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand4_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand5_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand5_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand6_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand6_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand7_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand7_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand8_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand8_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand9_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand9_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand10_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand10_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand11_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand11_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand12_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand12_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand13_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand13_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand14_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand14_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand15_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand15_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand16_RXD_eLNA_IDX_SetDefault
+#define UMTSBand16_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand17_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand17_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand18_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand18_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand19_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand19_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+#ifndef UMTSBand20_RXD_eLNA_IDX_SetDefault
+ #define UMTSBand20_RXD_eLNA_IDX_SetDefault MML1_FE_ELNA_NONE
+#endif
+
+/* ------------------- RX eLNA setting -------------------- */
+#define UMTSBand1_RX_eLNA_IDX UMTSBand1_RX_eLNA_IDX_SetDefault
+#define UMTSBand2_RX_eLNA_IDX UMTSBand2_RX_eLNA_IDX_SetDefault
+#define UMTSBand3_RX_eLNA_IDX UMTSBand3_RX_eLNA_IDX_SetDefault
+#define UMTSBand4_RX_eLNA_IDX UMTSBand4_RX_eLNA_IDX_SetDefault
+#define UMTSBand5_RX_eLNA_IDX UMTSBand5_RX_eLNA_IDX_SetDefault
+#define UMTSBand6_RX_eLNA_IDX UMTSBand6_RX_eLNA_IDX_SetDefault
+#define UMTSBand7_RX_eLNA_IDX UMTSBand7_RX_eLNA_IDX_SetDefault
+#define UMTSBand8_RX_eLNA_IDX UMTSBand8_RX_eLNA_IDX_SetDefault
+#define UMTSBand9_RX_eLNA_IDX UMTSBand9_RX_eLNA_IDX_SetDefault
+#define UMTSBand10_RX_eLNA_IDX UMTSBand10_RX_eLNA_IDX_SetDefault
+#define UMTSBand11_RX_eLNA_IDX UMTSBand11_RX_eLNA_IDX_SetDefault
+#define UMTSBand12_RX_eLNA_IDX UMTSBand12_RX_eLNA_IDX_SetDefault
+#define UMTSBand13_RX_eLNA_IDX UMTSBand13_RX_eLNA_IDX_SetDefault
+#define UMTSBand14_RX_eLNA_IDX UMTSBand14_RX_eLNA_IDX_SetDefault
+#define UMTSBand15_RX_eLNA_IDX UMTSBand15_RX_eLNA_IDX_SetDefault
+#define UMTSBand16_RX_eLNA_IDX UMTSBand16_RX_eLNA_IDX_SetDefault
+#define UMTSBand17_RX_eLNA_IDX UMTSBand17_RX_eLNA_IDX_SetDefault
+#define UMTSBand18_RX_eLNA_IDX UMTSBand18_RX_eLNA_IDX_SetDefault
+#define UMTSBand19_RX_eLNA_IDX UMTSBand19_RX_eLNA_IDX_SetDefault
+#define UMTSBand20_RX_eLNA_IDX UMTSBand20_RX_eLNA_IDX_SetDefault
+
+/* ------------------- RXD eLNA setting ------------------- */
+#define UMTSBand1_RXD_eLNA_IDX UMTSBand1_RXD_eLNA_IDX_SetDefault
+#define UMTSBand2_RXD_eLNA_IDX UMTSBand2_RXD_eLNA_IDX_SetDefault
+#define UMTSBand3_RXD_eLNA_IDX UMTSBand3_RXD_eLNA_IDX_SetDefault
+#define UMTSBand4_RXD_eLNA_IDX UMTSBand4_RXD_eLNA_IDX_SetDefault
+#define UMTSBand5_RXD_eLNA_IDX UMTSBand5_RXD_eLNA_IDX_SetDefault
+#define UMTSBand6_RXD_eLNA_IDX UMTSBand6_RXD_eLNA_IDX_SetDefault
+#define UMTSBand7_RXD_eLNA_IDX UMTSBand7_RXD_eLNA_IDX_SetDefault
+#define UMTSBand8_RXD_eLNA_IDX UMTSBand8_RXD_eLNA_IDX_SetDefault
+#define UMTSBand9_RXD_eLNA_IDX UMTSBand9_RXD_eLNA_IDX_SetDefault
+#define UMTSBand10_RXD_eLNA_IDX UMTSBand10_RXD_eLNA_IDX_SetDefault
+#define UMTSBand11_RXD_eLNA_IDX UMTSBand11_RXD_eLNA_IDX_SetDefault
+#define UMTSBand12_RXD_eLNA_IDX UMTSBand12_RXD_eLNA_IDX_SetDefault
+#define UMTSBand13_RXD_eLNA_IDX UMTSBand13_RXD_eLNA_IDX_SetDefault
+#define UMTSBand14_RXD_eLNA_IDX UMTSBand14_RXD_eLNA_IDX_SetDefault
+#define UMTSBand15_RXD_eLNA_IDX UMTSBand15_RXD_eLNA_IDX_SetDefault
+#define UMTSBand16_RXD_eLNA_IDX UMTSBand16_RXD_eLNA_IDX_SetDefault
+#define UMTSBand17_RXD_eLNA_IDX UMTSBand17_RXD_eLNA_IDX_SetDefault
+#define UMTSBand18_RXD_eLNA_IDX UMTSBand18_RXD_eLNA_IDX_SetDefault
+#define UMTSBand19_RXD_eLNA_IDX UMTSBand19_RXD_eLNA_IDX_SetDefault
+#define UMTSBand20_RXD_eLNA_IDX UMTSBand20_RXD_eLNA_IDX_SetDefault
+
+#endif // IS_3G_ELNA_IDX_SUPPORT
+
+
+/*******************************************************************************
+** CA CFG INDEX DEFAULT DEFINE
+*******************************************************************************/
+#ifndef RX_CABAND_IND_00_SetDefault
+ #define RX_CABAND_IND_00_SetDefault UMTS_CA_BANDNONE
+#endif
+#ifndef RX_CABAND_IND_01_SetDefault
+ #define RX_CABAND_IND_01_SetDefault UMTS_CA_BANDNONE
+#endif
+#ifndef RX_CABAND_IND_02_SetDefault
+ #define RX_CABAND_IND_02_SetDefault UMTS_CA_BANDNONE
+#endif
+#ifndef RX_CABAND_IND_03_SetDefault
+ #define RX_CABAND_IND_03_SetDefault UMTS_CA_BANDNONE
+#endif
+#ifndef RX_CABAND_IND_04_SetDefault
+ #define RX_CABAND_IND_04_SetDefault UMTS_CA_BANDNONE
+#endif
+
+#define RX_CABAND_IND_00 RX_CABAND_IND_00_SetDefault
+#define RX_CABAND_IND_01 RX_CABAND_IND_01_SetDefault
+#define RX_CABAND_IND_02 RX_CABAND_IND_02_SetDefault
+#define RX_CABAND_IND_03 RX_CABAND_IND_03_SetDefault
+#define RX_CABAND_IND_04 RX_CABAND_IND_04_SetDefault
+
+
+#if IS_URF_PCORE
+#define PA_SECTION PA_SECTION_SetDefault
+#define TC_PR1 TC_PR1_SetDefault
+#define TC_PR2 TC_PR2_SetDefault
+#define TC_PR2B TC_PR2B_SetDefault
+#define TC_PR3 TC_PR3_SetDefault
+
+#define TC_PT1 TC_PT1_SetDefault
+#define TC_PT2 TC_PT2_SetDefault
+#define TC_PT2B TC_PT2B_SetDefault
+#define TC_PT3 TC_PT3_SetDefault
+
+#define MAX_OFFSET MAX_OFFSET_SetDefault
+#define VM_OFFSET VM_OFFSET_SetDefault
+#define VBIAS_OFFSET VBIAS_OFFSET_SetDefault
+#define DC2DC_OFFSET DC2DC_OFFSET_SetDefault
+#define VGA_OFFSET VGA_OFFSET_SetDefault
+
+#define RF_SETTING_BY_NVRAM KAL_TRUE
+#define PMU_PASETTING PMU_PASETTING_SetDefault
+#define RX_DIVERSITY_ALWAYS_ON RX_DIVERSITY_ALWAYS_ON_SetDefault
+#define PA_DIRFT_COMPENSATION PA_DIRFT_COMPENSATION_SetDefault
+#define ULTRA_LOW_COST_EN ULTRA_LOW_COST_EN_SetDefault
+#endif
+
+#define BAND1_CHANNEL_SEL UMTSBand1_CHANNEL_SEL_SetDefault
+#define BAND2_CHANNEL_SEL UMTSBand2_CHANNEL_SEL_SetDefault
+#define BAND3_CHANNEL_SEL UMTSBand3_CHANNEL_SEL_SetDefault
+#define BAND4_CHANNEL_SEL UMTSBand4_CHANNEL_SEL_SetDefault
+#define BAND5_CHANNEL_SEL UMTSBand5_CHANNEL_SEL_SetDefault
+#define BAND6_CHANNEL_SEL UMTSBand6_CHANNEL_SEL_SetDefault
+#define BAND8_CHANNEL_SEL UMTSBand8_CHANNEL_SEL_SetDefault
+#define BAND9_CHANNEL_SEL UMTSBand9_CHANNEL_SEL_SetDefault
+#define BAND10_CHANNEL_SEL UMTSBand10_CHANNEL_SEL_SetDefault
+#define BAND11_CHANNEL_SEL UMTSBand11_CHANNEL_SEL_SetDefault
+#define BAND19_CHANNEL_SEL UMTSBand19_CHANNEL_SEL_SetDefault
+
+#define BAND1_CHANNEL2_SEL UMTSBand1_CHANNEL2_SEL_SetDefault
+#define BAND2_CHANNEL2_SEL UMTSBand2_CHANNEL2_SEL_SetDefault
+#define BAND3_CHANNEL2_SEL UMTSBand3_CHANNEL2_SEL_SetDefault
+#define BAND4_CHANNEL2_SEL UMTSBand4_CHANNEL2_SEL_SetDefault
+#define BAND5_CHANNEL2_SEL UMTSBand5_CHANNEL2_SEL_SetDefault
+#define BAND6_CHANNEL2_SEL UMTSBand6_CHANNEL2_SEL_SetDefault
+#define BAND8_CHANNEL2_SEL UMTSBand8_CHANNEL2_SEL_SetDefault
+#define BAND9_CHANNEL2_SEL UMTSBand9_CHANNEL2_SEL_SetDefault
+#define BAND10_CHANNEL2_SEL UMTSBand10_CHANNEL2_SEL_SetDefault
+#define BAND11_CHANNEL2_SEL UMTSBand11_CHANNEL2_SEL_SetDefault
+#define BAND19_CHANNEL2_SEL UMTSBand19_CHANNEL2_SEL_SetDefault
+
+#define BAND1_OUTPUT_SEL UMTSBand1_OUTPUT_SEL_SetDefault
+#define BAND2_OUTPUT_SEL UMTSBand2_OUTPUT_SEL_SetDefault
+#define BAND3_OUTPUT_SEL UMTSBand3_OUTPUT_SEL_SetDefault
+#define BAND4_OUTPUT_SEL UMTSBand4_OUTPUT_SEL_SetDefault
+#define BAND5_OUTPUT_SEL UMTSBand5_OUTPUT_SEL_SetDefault
+#define BAND6_OUTPUT_SEL UMTSBand6_OUTPUT_SEL_SetDefault
+#define BAND8_OUTPUT_SEL UMTSBand8_OUTPUT_SEL_SetDefault
+#define BAND9_OUTPUT_SEL UMTSBand9_OUTPUT_SEL_SetDefault
+#define BAND10_OUTPUT_SEL UMTSBand10_OUTPUT_SEL_SetDefault
+#define BAND11_OUTPUT_SEL UMTSBand11_OUTPUT_SEL_SetDefault
+#define BAND19_OUTPUT_SEL UMTSBand19_OUTPUT_SEL_SetDefault
+
+#define BAND1_OUTPUT_DET_SEL UMTSBand1_OUTPUT_DET_SEL_SetDefault
+#define BAND2_OUTPUT_DET_SEL UMTSBand2_OUTPUT_DET_SEL_SetDefault
+#define BAND3_OUTPUT_DET_SEL UMTSBand3_OUTPUT_DET_SEL_SetDefault
+#define BAND4_OUTPUT_DET_SEL UMTSBand4_OUTPUT_DET_SEL_SetDefault
+#define BAND5_OUTPUT_DET_SEL UMTSBand5_OUTPUT_DET_SEL_SetDefault
+#define BAND6_OUTPUT_DET_SEL UMTSBand6_OUTPUT_DET_SEL_SetDefault
+#define BAND8_OUTPUT_DET_SEL UMTSBand8_OUTPUT_DET_SEL_SetDefault
+#define BAND9_OUTPUT_DET_SEL UMTSBand9_OUTPUT_DET_SEL_SetDefault
+#define BAND10_OUTPUT_DET_SEL UMTSBand10_OUTPUT_DET_SEL_SetDefault
+#define BAND11_OUTPUT_DET_SEL UMTSBand11_OUTPUT_DET_SEL_SetDefault
+#define BAND19_OUTPUT_DET_SEL UMTSBand19_OUTPUT_DET_SEL_SetDefault
+
+#define PDATA_BAND1_PR1 PDATA_UMTSBand1_PR1_SetDefault
+#define PDATA_BAND1_PR2 PDATA_UMTSBand1_PR2_SetDefault
+#define PDATA_BAND1_PR2B PDATA_UMTSBand1_PR2B_SetDefault
+#define PDATA_BAND1_PR3 PDATA_UMTSBand1_PR3_SetDefault
+#define PDATA_BAND1_PR3A PDATA_UMTSBand1_PR3A_SetDefault
+#define PDATA_BAND1_PT1 PDATA_UMTSBand1_PT1_SetDefault
+#define PDATA_BAND1_PT2 PDATA_UMTSBand1_PT2_SetDefault
+#define PDATA_BAND1_PT2B PDATA_UMTSBand1_PT2B_SetDefault
+#define PDATA_BAND1_PT3 PDATA_UMTSBand1_PT3_SetDefault
+#define PDATA_BAND1_PT3A PDATA_UMTSBand1_PT3A_SetDefault
+
+#define PDATA_BAND2_PR1 PDATA_UMTSBand2_PR1_SetDefault
+#define PDATA_BAND2_PR2 PDATA_UMTSBand2_PR2_SetDefault
+#define PDATA_BAND2_PR2B PDATA_UMTSBand2_PR2B_SetDefault
+#define PDATA_BAND2_PR3 PDATA_UMTSBand2_PR3_SetDefault
+#define PDATA_BAND2_PR3A PDATA_UMTSBand2_PR3A_SetDefault
+#define PDATA_BAND2_PT1 PDATA_UMTSBand2_PT1_SetDefault
+#define PDATA_BAND2_PT2 PDATA_UMTSBand2_PT2_SetDefault
+#define PDATA_BAND2_PT2B PDATA_UMTSBand2_PT2B_SetDefault
+#define PDATA_BAND2_PT3 PDATA_UMTSBand2_PT3_SetDefault
+#define PDATA_BAND2_PT3A PDATA_UMTSBand2_PT3A_SetDefault
+
+#define PDATA_BAND3_PR1 PDATA_UMTSBand3_PR1_SetDefault
+#define PDATA_BAND3_PR2 PDATA_UMTSBand3_PR2_SetDefault
+#define PDATA_BAND3_PR2B PDATA_UMTSBand3_PR2B_SetDefault
+#define PDATA_BAND3_PR3 PDATA_UMTSBand3_PR3_SetDefault
+#define PDATA_BAND3_PR3A PDATA_UMTSBand3_PR3A_SetDefault
+#define PDATA_BAND3_PT1 PDATA_UMTSBand3_PT1_SetDefault
+#define PDATA_BAND3_PT2 PDATA_UMTSBand3_PT2_SetDefault
+#define PDATA_BAND3_PT2B PDATA_UMTSBand3_PT2B_SetDefault
+#define PDATA_BAND3_PT3 PDATA_UMTSBand3_PT3_SetDefault
+#define PDATA_BAND3_PT3A PDATA_UMTSBand3_PT3A_SetDefault
+
+#define PDATA_BAND4_PR1 PDATA_UMTSBand4_PR1_SetDefault
+#define PDATA_BAND4_PR2 PDATA_UMTSBand4_PR2_SetDefault
+#define PDATA_BAND4_PR2B PDATA_UMTSBand4_PR2B_SetDefault
+#define PDATA_BAND4_PR3 PDATA_UMTSBand4_PR3_SetDefault
+#define PDATA_BAND4_PR3A PDATA_UMTSBand4_PR3A_SetDefault
+#define PDATA_BAND4_PT1 PDATA_UMTSBand4_PT1_SetDefault
+#define PDATA_BAND4_PT2 PDATA_UMTSBand4_PT2_SetDefault
+#define PDATA_BAND4_PT2B PDATA_UMTSBand4_PT2B_SetDefault
+#define PDATA_BAND4_PT3 PDATA_UMTSBand4_PT3_SetDefault
+#define PDATA_BAND4_PT3A PDATA_UMTSBand4_PT3A_SetDefault
+
+#define PDATA_BAND5_PR1 PDATA_UMTSBand5_PR1_SetDefault
+#define PDATA_BAND5_PR2 PDATA_UMTSBand5_PR2_SetDefault
+#define PDATA_BAND5_PR2B PDATA_UMTSBand5_PR2B_SetDefault
+#define PDATA_BAND5_PR3 PDATA_UMTSBand5_PR3_SetDefault
+#define PDATA_BAND5_PR3A PDATA_UMTSBand5_PR3A_SetDefault
+#define PDATA_BAND5_PT1 PDATA_UMTSBand5_PT1_SetDefault
+#define PDATA_BAND5_PT2 PDATA_UMTSBand5_PT2_SetDefault
+#define PDATA_BAND5_PT2B PDATA_UMTSBand5_PT2B_SetDefault
+#define PDATA_BAND5_PT3 PDATA_UMTSBand5_PT3_SetDefault
+#define PDATA_BAND5_PT3A PDATA_UMTSBand5_PT3A_SetDefault
+
+#define PDATA_BAND6_PR1 PDATA_UMTSBand6_PR1_SetDefault
+#define PDATA_BAND6_PR2 PDATA_UMTSBand6_PR2_SetDefault
+#define PDATA_BAND6_PR2B PDATA_UMTSBand6_PR2B_SetDefault
+#define PDATA_BAND6_PR3 PDATA_UMTSBand6_PR3_SetDefault
+#define PDATA_BAND6_PR3A PDATA_UMTSBand6_PR3A_SetDefault
+#define PDATA_BAND6_PT1 PDATA_UMTSBand6_PT1_SetDefault
+#define PDATA_BAND6_PT2 PDATA_UMTSBand6_PT2_SetDefault
+#define PDATA_BAND6_PT2B PDATA_UMTSBand6_PT2B_SetDefault
+#define PDATA_BAND6_PT3 PDATA_UMTSBand6_PT3_SetDefault
+#define PDATA_BAND6_PT3A PDATA_UMTSBand6_PT3A_SetDefault
+
+#define PDATA_BAND7_PR1 PDATA_UMTSBand7_PR1_SetDefault
+#define PDATA_BAND7_PR2 PDATA_UMTSBand7_PR2_SetDefault
+#define PDATA_BAND7_PR2B PDATA_UMTSBand7_PR2B_SetDefault
+#define PDATA_BAND7_PR3 PDATA_UMTSBand7_PR3_SetDefault
+#define PDATA_BAND7_PR3A PDATA_UMTSBand7_PR3A_SetDefault
+#define PDATA_BAND7_PT1 PDATA_UMTSBand7_PT1_SetDefault
+#define PDATA_BAND7_PT2 PDATA_UMTSBand7_PT2_SetDefault
+#define PDATA_BAND7_PT2B PDATA_UMTSBand7_PT2B_SetDefault
+#define PDATA_BAND7_PT3 PDATA_UMTSBand7_PT3_SetDefault
+#define PDATA_BAND7_PT3A PDATA_UMTSBand7_PT3A_SetDefault
+
+#define PDATA_BAND8_PR1 PDATA_UMTSBand8_PR1_SetDefault
+#define PDATA_BAND8_PR2 PDATA_UMTSBand8_PR2_SetDefault
+#define PDATA_BAND8_PR2B PDATA_UMTSBand8_PR2B_SetDefault
+#define PDATA_BAND8_PR3 PDATA_UMTSBand8_PR3_SetDefault
+#define PDATA_BAND8_PR3A PDATA_UMTSBand8_PR3A_SetDefault
+#define PDATA_BAND8_PT1 PDATA_UMTSBand8_PT1_SetDefault
+#define PDATA_BAND8_PT2 PDATA_UMTSBand8_PT2_SetDefault
+#define PDATA_BAND8_PT2B PDATA_UMTSBand8_PT2B_SetDefault
+#define PDATA_BAND8_PT3 PDATA_UMTSBand8_PT3_SetDefault
+#define PDATA_BAND8_PT3A PDATA_UMTSBand8_PT3A_SetDefault
+
+#define PDATA_BAND9_PR1 PDATA_UMTSBand9_PR1_SetDefault
+#define PDATA_BAND9_PR2 PDATA_UMTSBand9_PR2_SetDefault
+#define PDATA_BAND9_PR2B PDATA_UMTSBand9_PR2B_SetDefault
+#define PDATA_BAND9_PR3 PDATA_UMTSBand9_PR3_SetDefault
+#define PDATA_BAND9_PR3A PDATA_UMTSBand9_PR3A_SetDefault
+#define PDATA_BAND9_PT1 PDATA_UMTSBand9_PT1_SetDefault
+#define PDATA_BAND9_PT2 PDATA_UMTSBand9_PT2_SetDefault
+#define PDATA_BAND9_PT2B PDATA_UMTSBand9_PT2B_SetDefault
+#define PDATA_BAND9_PT3 PDATA_UMTSBand9_PT3_SetDefault
+#define PDATA_BAND9_PT3A PDATA_UMTSBand9_PT3A_SetDefault
+
+#define PDATA_BAND10_PR1 PDATA_UMTSBand10_PR1_SetDefault
+#define PDATA_BAND10_PR2 PDATA_UMTSBand10_PR2_SetDefault
+#define PDATA_BAND10_PR2B PDATA_UMTSBand10_PR2B_SetDefault
+#define PDATA_BAND10_PR3 PDATA_UMTSBand10_PR3_SetDefault
+#define PDATA_BAND10_PR3A PDATA_UMTSBand10_PR3A_SetDefault
+#define PDATA_BAND10_PT1 PDATA_UMTSBand10_PT1_SetDefault
+#define PDATA_BAND10_PT2 PDATA_UMTSBand10_PT2_SetDefault
+#define PDATA_BAND10_PT2B PDATA_UMTSBand10_PT2B_SetDefault
+#define PDATA_BAND10_PT3 PDATA_UMTSBand10_PT3_SetDefault
+#define PDATA_BAND10_PT3A PDATA_UMTSBand10_PT3A_SetDefault
+
+#define PDATA_BAND11_PR1 PDATA_UMTSBand11_PR1_SetDefault
+#define PDATA_BAND11_PR2 PDATA_UMTSBand11_PR2_SetDefault
+#define PDATA_BAND11_PR2B PDATA_UMTSBand11_PR2B_SetDefault
+#define PDATA_BAND11_PR3 PDATA_UMTSBand11_PR3_SetDefault
+#define PDATA_BAND11_PR3A PDATA_UMTSBand11_PR3A_SetDefault
+#define PDATA_BAND11_PT1 PDATA_UMTSBand11_PT1_SetDefault
+#define PDATA_BAND11_PT2 PDATA_UMTSBand11_PT2_SetDefault
+#define PDATA_BAND11_PT2B PDATA_UMTSBand11_PT2B_SetDefault
+#define PDATA_BAND11_PT3 PDATA_UMTSBand11_PT3_SetDefault
+#define PDATA_BAND11_PT3A PDATA_UMTSBand11_PT3A_SetDefault
+
+#define PDATA_BAND19_PR1 PDATA_UMTSBand19_PR1_SetDefault
+#define PDATA_BAND19_PR2 PDATA_UMTSBand19_PR2_SetDefault
+#define PDATA_BAND19_PR2B PDATA_UMTSBand19_PR2B_SetDefault
+#define PDATA_BAND19_PR3 PDATA_UMTSBand19_PR3_SetDefault
+#define PDATA_BAND19_PR3A PDATA_UMTSBand19_PR3A_SetDefault
+#define PDATA_BAND19_PT1 PDATA_UMTSBand19_PT1_SetDefault
+#define PDATA_BAND19_PT2 PDATA_UMTSBand19_PT2_SetDefault
+#define PDATA_BAND19_PT2B PDATA_UMTSBand19_PT2B_SetDefault
+#define PDATA_BAND19_PT3 PDATA_UMTSBand19_PT3_SetDefault
+#define PDATA_BAND19_PT3A PDATA_UMTSBand19_PT3A_SetDefault
+
+#if IS_3G_RXD_FE_CONTROL_SUPPORT
+#define PDATA2_BAND1_PR1 PDATA2_UMTSBand1_PR1_SetDefault
+#define PDATA2_BAND1_PR2 PDATA2_UMTSBand1_PR2_SetDefault
+#define PDATA2_BAND1_PR2B PDATA2_UMTSBand1_PR2B_SetDefault
+#define PDATA2_BAND1_PR3 PDATA2_UMTSBand1_PR3_SetDefault
+#define PDATA2_BAND1_PR3A PDATA2_UMTSBand1_PR3A_SetDefault
+
+#define PDATA2_BAND2_PR1 PDATA2_UMTSBand2_PR1_SetDefault
+#define PDATA2_BAND2_PR2 PDATA2_UMTSBand2_PR2_SetDefault
+#define PDATA2_BAND2_PR2B PDATA2_UMTSBand2_PR2B_SetDefault
+#define PDATA2_BAND2_PR3 PDATA2_UMTSBand2_PR3_SetDefault
+#define PDATA2_BAND2_PR3A PDATA2_UMTSBand2_PR3A_SetDefault
+
+#define PDATA2_BAND3_PR1 PDATA2_UMTSBand3_PR1_SetDefault
+#define PDATA2_BAND3_PR2 PDATA2_UMTSBand3_PR2_SetDefault
+#define PDATA2_BAND3_PR2B PDATA2_UMTSBand3_PR2B_SetDefault
+#define PDATA2_BAND3_PR3 PDATA2_UMTSBand3_PR3_SetDefault
+#define PDATA2_BAND3_PR3A PDATA2_UMTSBand3_PR3A_SetDefault
+
+#define PDATA2_BAND4_PR1 PDATA2_UMTSBand4_PR1_SetDefault
+#define PDATA2_BAND4_PR2 PDATA2_UMTSBand4_PR2_SetDefault
+#define PDATA2_BAND4_PR2B PDATA2_UMTSBand4_PR2B_SetDefault
+#define PDATA2_BAND4_PR3 PDATA2_UMTSBand4_PR3_SetDefault
+#define PDATA2_BAND4_PR3A PDATA2_UMTSBand4_PR3A_SetDefault
+
+#define PDATA2_BAND5_PR1 PDATA2_UMTSBand5_PR1_SetDefault
+#define PDATA2_BAND5_PR2 PDATA2_UMTSBand5_PR2_SetDefault
+#define PDATA2_BAND5_PR2B PDATA2_UMTSBand5_PR2B_SetDefault
+#define PDATA2_BAND5_PR3 PDATA2_UMTSBand5_PR3_SetDefault
+#define PDATA2_BAND5_PR3A PDATA2_UMTSBand5_PR3A_SetDefault
+
+#define PDATA2_BAND6_PR1 PDATA2_UMTSBand6_PR1_SetDefault
+#define PDATA2_BAND6_PR2 PDATA2_UMTSBand6_PR2_SetDefault
+#define PDATA2_BAND6_PR2B PDATA2_UMTSBand6_PR2B_SetDefault
+#define PDATA2_BAND6_PR3 PDATA2_UMTSBand6_PR3_SetDefault
+#define PDATA2_BAND6_PR3A PDATA2_UMTSBand6_PR3A_SetDefault
+
+#define PDATA2_BAND7_PR1 PDATA2_UMTSBand7_PR1_SetDefault
+#define PDATA2_BAND7_PR2 PDATA2_UMTSBand7_PR2_SetDefault
+#define PDATA2_BAND7_PR2B PDATA2_UMTSBand7_PR2B_SetDefault
+#define PDATA2_BAND7_PR3 PDATA2_UMTSBand7_PR3_SetDefault
+#define PDATA2_BAND7_PR3A PDATA2_UMTSBand7_PR3A_SetDefault
+
+#define PDATA2_BAND8_PR1 PDATA2_UMTSBand8_PR1_SetDefault
+#define PDATA2_BAND8_PR2 PDATA2_UMTSBand8_PR2_SetDefault
+#define PDATA2_BAND8_PR2B PDATA2_UMTSBand8_PR2B_SetDefault
+#define PDATA2_BAND8_PR3 PDATA2_UMTSBand8_PR3_SetDefault
+#define PDATA2_BAND8_PR3A PDATA2_UMTSBand8_PR3A_SetDefault
+
+#define PDATA2_BAND9_PR1 PDATA2_UMTSBand9_PR1_SetDefault
+#define PDATA2_BAND9_PR2 PDATA2_UMTSBand9_PR2_SetDefault
+#define PDATA2_BAND9_PR2B PDATA2_UMTSBand9_PR2B_SetDefault
+#define PDATA2_BAND9_PR3 PDATA2_UMTSBand9_PR3_SetDefault
+#define PDATA2_BAND9_PR3A PDATA2_UMTSBand9_PR3A_SetDefault
+
+#define PDATA2_BAND10_PR1 PDATA2_UMTSBand10_PR1_SetDefault
+#define PDATA2_BAND10_PR2 PDATA2_UMTSBand10_PR2_SetDefault
+#define PDATA2_BAND10_PR2B PDATA2_UMTSBand10_PR2B_SetDefault
+#define PDATA2_BAND10_PR3 PDATA2_UMTSBand10_PR3_SetDefault
+#define PDATA2_BAND10_PR3A PDATA2_UMTSBand10_PR3A_SetDefault
+
+#define PDATA2_BAND11_PR1 PDATA2_UMTSBand11_PR1_SetDefault
+#define PDATA2_BAND11_PR2 PDATA2_UMTSBand11_PR2_SetDefault
+#define PDATA2_BAND11_PR2B PDATA2_UMTSBand11_PR2B_SetDefault
+#define PDATA2_BAND11_PR3 PDATA2_UMTSBand11_PR3_SetDefault
+#define PDATA2_BAND11_PR3A PDATA2_UMTSBand11_PR3A_SetDefault
+
+#define PDATA2_BAND19_PR1 PDATA2_UMTSBand19_PR1_SetDefault
+#define PDATA2_BAND19_PR2 PDATA2_UMTSBand19_PR2_SetDefault
+#define PDATA2_BAND19_PR2B PDATA2_UMTSBand19_PR2B_SetDefault
+#define PDATA2_BAND19_PR3 PDATA2_UMTSBand19_PR3_SetDefault
+#define PDATA2_BAND19_PR3A PDATA2_UMTSBand19_PR3A_SetDefault
+#endif
+
+#define MPR_BACK_OFF_HSDPA_BAND1 MPR_BACK_OFF_HSDPA_BAND1_SetDefault
+#define MPR_BACK_OFF_HSDPA_BAND2 MPR_BACK_OFF_HSDPA_BAND2_SetDefault
+#define MPR_BACK_OFF_HSDPA_BAND3 MPR_BACK_OFF_HSDPA_BAND3_SetDefault
+#define MPR_BACK_OFF_HSDPA_BAND4 MPR_BACK_OFF_HSDPA_BAND4_SetDefault
+#define MPR_BACK_OFF_HSDPA_BAND5 MPR_BACK_OFF_HSDPA_BAND5_SetDefault
+#define MPR_BACK_OFF_HSDPA_BAND6 MPR_BACK_OFF_HSDPA_BAND6_SetDefault
+#define MPR_BACK_OFF_HSDPA_BAND8 MPR_BACK_OFF_HSDPA_BAND8_SetDefault
+#define MPR_BACK_OFF_HSDPA_BAND9 MPR_BACK_OFF_HSDPA_BAND9_SetDefault
+#define MPR_BACK_OFF_HSDPA_BAND10 MPR_BACK_OFF_HSDPA_BAND10_SetDefault
+#define MPR_BACK_OFF_HSDPA_BAND11 MPR_BACK_OFF_HSDPA_BAND11_SetDefault
+#define MPR_BACK_OFF_HSDPA_BAND19 MPR_BACK_OFF_HSDPA_BAND19_SetDefault
+#define MPR_BACK_OFF_HSUPA_BAND1 MPR_BACK_OFF_HSUPA_BAND1_SetDefault
+#define MPR_BACK_OFF_HSUPA_BAND2 MPR_BACK_OFF_HSUPA_BAND2_SetDefault
+#define MPR_BACK_OFF_HSUPA_BAND3 MPR_BACK_OFF_HSUPA_BAND3_SetDefault
+#define MPR_BACK_OFF_HSUPA_BAND4 MPR_BACK_OFF_HSUPA_BAND4_SetDefault
+#define MPR_BACK_OFF_HSUPA_BAND5 MPR_BACK_OFF_HSUPA_BAND5_SetDefault
+#define MPR_BACK_OFF_HSUPA_BAND6 MPR_BACK_OFF_HSUPA_BAND6_SetDefault
+#define MPR_BACK_OFF_HSUPA_BAND8 MPR_BACK_OFF_HSUPA_BAND8_SetDefault
+#define MPR_BACK_OFF_HSUPA_BAND9 MPR_BACK_OFF_HSUPA_BAND9_SetDefault
+#define MPR_BACK_OFF_HSUPA_BAND10 MPR_BACK_OFF_HSUPA_BAND10_SetDefault
+#define MPR_BACK_OFF_HSUPA_BAND11 MPR_BACK_OFF_HSUPA_BAND11_SetDefault
+#define MPR_BACK_OFF_HSUPA_BAND19 MPR_BACK_OFF_HSUPA_BAND19_SetDefault
+
+#if IS_3G_MPR_EXTEND_SUPPORT
+
+#define MPR_R6_B1_SUB_1 MPR_BACK_OFF_HSUPA_BAND1_SUB_1_SetDefault
+#define MPR_R6_B2_SUB_1 MPR_BACK_OFF_HSUPA_BAND2_SUB_1_SetDefault
+#define MPR_R6_B3_SUB_1 MPR_BACK_OFF_HSUPA_BAND3_SUB_1_SetDefault
+#define MPR_R6_B4_SUB_1 MPR_BACK_OFF_HSUPA_BAND4_SUB_1_SetDefault
+#define MPR_R6_B5_SUB_1 MPR_BACK_OFF_HSUPA_BAND5_SUB_1_SetDefault
+#define MPR_R6_B6_SUB_1 MPR_BACK_OFF_HSUPA_BAND6_SUB_1_SetDefault
+#define MPR_R6_B7_SUB_1 MPR_BACK_OFF_HSUPA_BAND7_SUB_1_SetDefault
+#define MPR_R6_B8_SUB_1 MPR_BACK_OFF_HSUPA_BAND8_SUB_1_SetDefault
+#define MPR_R6_B9_SUB_1 MPR_BACK_OFF_HSUPA_BAND9_SUB_1_SetDefault
+#define MPR_R6_B10_SUB_1 MPR_BACK_OFF_HSUPA_BAND10_SUB_1_SetDefault
+#define MPR_R6_B11_SUB_1 MPR_BACK_OFF_HSUPA_BAND11_SUB_1_SetDefault
+#define MPR_R6_B12_SUB_1 MPR_BACK_OFF_HSUPA_BAND12_SUB_1_SetDefault
+#define MPR_R6_B13_SUB_1 MPR_BACK_OFF_HSUPA_BAND13_SUB_1_SetDefault
+#define MPR_R6_B14_SUB_1 MPR_BACK_OFF_HSUPA_BAND14_SUB_1_SetDefault
+#define MPR_R6_B15_SUB_1 MPR_BACK_OFF_HSUPA_BAND15_SUB_1_SetDefault
+#define MPR_R6_B16_SUB_1 MPR_BACK_OFF_HSUPA_BAND16_SUB_1_SetDefault
+#define MPR_R6_B17_SUB_1 MPR_BACK_OFF_HSUPA_BAND17_SUB_1_SetDefault
+#define MPR_R6_B18_SUB_1 MPR_BACK_OFF_HSUPA_BAND18_SUB_1_SetDefault
+#define MPR_R6_B19_SUB_1 MPR_BACK_OFF_HSUPA_BAND19_SUB_1_SetDefault
+#define MPR_R6_B20_SUB_1 MPR_BACK_OFF_HSUPA_BAND20_SUB_1_SetDefault
+
+#define MPR_R6_B1_SUB_2 MPR_BACK_OFF_HSUPA_BAND1_SUB_2_SetDefault
+#define MPR_R6_B2_SUB_2 MPR_BACK_OFF_HSUPA_BAND2_SUB_2_SetDefault
+#define MPR_R6_B3_SUB_2 MPR_BACK_OFF_HSUPA_BAND3_SUB_2_SetDefault
+#define MPR_R6_B4_SUB_2 MPR_BACK_OFF_HSUPA_BAND4_SUB_2_SetDefault
+#define MPR_R6_B5_SUB_2 MPR_BACK_OFF_HSUPA_BAND5_SUB_2_SetDefault
+#define MPR_R6_B6_SUB_2 MPR_BACK_OFF_HSUPA_BAND6_SUB_2_SetDefault
+#define MPR_R6_B7_SUB_2 MPR_BACK_OFF_HSUPA_BAND7_SUB_2_SetDefault
+#define MPR_R6_B8_SUB_2 MPR_BACK_OFF_HSUPA_BAND8_SUB_2_SetDefault
+#define MPR_R6_B9_SUB_2 MPR_BACK_OFF_HSUPA_BAND9_SUB_2_SetDefault
+#define MPR_R6_B10_SUB_2 MPR_BACK_OFF_HSUPA_BAND10_SUB_2_SetDefault
+#define MPR_R6_B11_SUB_2 MPR_BACK_OFF_HSUPA_BAND11_SUB_2_SetDefault
+#define MPR_R6_B12_SUB_2 MPR_BACK_OFF_HSUPA_BAND12_SUB_2_SetDefault
+#define MPR_R6_B13_SUB_2 MPR_BACK_OFF_HSUPA_BAND13_SUB_2_SetDefault
+#define MPR_R6_B14_SUB_2 MPR_BACK_OFF_HSUPA_BAND14_SUB_2_SetDefault
+#define MPR_R6_B15_SUB_2 MPR_BACK_OFF_HSUPA_BAND15_SUB_2_SetDefault
+#define MPR_R6_B16_SUB_2 MPR_BACK_OFF_HSUPA_BAND16_SUB_2_SetDefault
+#define MPR_R6_B17_SUB_2 MPR_BACK_OFF_HSUPA_BAND17_SUB_2_SetDefault
+#define MPR_R6_B18_SUB_2 MPR_BACK_OFF_HSUPA_BAND18_SUB_2_SetDefault
+#define MPR_R6_B19_SUB_2 MPR_BACK_OFF_HSUPA_BAND19_SUB_2_SetDefault
+#define MPR_R6_B20_SUB_2 MPR_BACK_OFF_HSUPA_BAND20_SUB_2_SetDefault
+
+#define MPR_R6_B1_SUB_3 MPR_BACK_OFF_HSUPA_BAND1_SUB_3_SetDefault
+#define MPR_R6_B2_SUB_3 MPR_BACK_OFF_HSUPA_BAND2_SUB_3_SetDefault
+#define MPR_R6_B3_SUB_3 MPR_BACK_OFF_HSUPA_BAND3_SUB_3_SetDefault
+#define MPR_R6_B4_SUB_3 MPR_BACK_OFF_HSUPA_BAND4_SUB_3_SetDefault
+#define MPR_R6_B5_SUB_3 MPR_BACK_OFF_HSUPA_BAND5_SUB_3_SetDefault
+#define MPR_R6_B6_SUB_3 MPR_BACK_OFF_HSUPA_BAND6_SUB_3_SetDefault
+#define MPR_R6_B7_SUB_3 MPR_BACK_OFF_HSUPA_BAND7_SUB_3_SetDefault
+#define MPR_R6_B8_SUB_3 MPR_BACK_OFF_HSUPA_BAND8_SUB_3_SetDefault
+#define MPR_R6_B9_SUB_3 MPR_BACK_OFF_HSUPA_BAND9_SUB_3_SetDefault
+#define MPR_R6_B10_SUB_3 MPR_BACK_OFF_HSUPA_BAND10_SUB_3_SetDefault
+#define MPR_R6_B11_SUB_3 MPR_BACK_OFF_HSUPA_BAND11_SUB_3_SetDefault
+#define MPR_R6_B12_SUB_3 MPR_BACK_OFF_HSUPA_BAND12_SUB_3_SetDefault
+#define MPR_R6_B13_SUB_3 MPR_BACK_OFF_HSUPA_BAND13_SUB_3_SetDefault
+#define MPR_R6_B14_SUB_3 MPR_BACK_OFF_HSUPA_BAND14_SUB_3_SetDefault
+#define MPR_R6_B15_SUB_3 MPR_BACK_OFF_HSUPA_BAND15_SUB_3_SetDefault
+#define MPR_R6_B16_SUB_3 MPR_BACK_OFF_HSUPA_BAND16_SUB_3_SetDefault
+#define MPR_R6_B17_SUB_3 MPR_BACK_OFF_HSUPA_BAND17_SUB_3_SetDefault
+#define MPR_R6_B18_SUB_3 MPR_BACK_OFF_HSUPA_BAND18_SUB_3_SetDefault
+#define MPR_R6_B19_SUB_3 MPR_BACK_OFF_HSUPA_BAND19_SUB_3_SetDefault
+#define MPR_R6_B20_SUB_3 MPR_BACK_OFF_HSUPA_BAND20_SUB_3_SetDefault
+
+#define MPR_R6_B1_SUB_4 MPR_BACK_OFF_HSUPA_BAND1_SUB_4_SetDefault
+#define MPR_R6_B2_SUB_4 MPR_BACK_OFF_HSUPA_BAND2_SUB_4_SetDefault
+#define MPR_R6_B3_SUB_4 MPR_BACK_OFF_HSUPA_BAND3_SUB_4_SetDefault
+#define MPR_R6_B4_SUB_4 MPR_BACK_OFF_HSUPA_BAND4_SUB_4_SetDefault
+#define MPR_R6_B5_SUB_4 MPR_BACK_OFF_HSUPA_BAND5_SUB_4_SetDefault
+#define MPR_R6_B6_SUB_4 MPR_BACK_OFF_HSUPA_BAND6_SUB_4_SetDefault
+#define MPR_R6_B7_SUB_4 MPR_BACK_OFF_HSUPA_BAND7_SUB_4_SetDefault
+#define MPR_R6_B8_SUB_4 MPR_BACK_OFF_HSUPA_BAND8_SUB_4_SetDefault
+#define MPR_R6_B9_SUB_4 MPR_BACK_OFF_HSUPA_BAND9_SUB_4_SetDefault
+#define MPR_R6_B10_SUB_4 MPR_BACK_OFF_HSUPA_BAND10_SUB_4_SetDefault
+#define MPR_R6_B11_SUB_4 MPR_BACK_OFF_HSUPA_BAND11_SUB_4_SetDefault
+#define MPR_R6_B12_SUB_4 MPR_BACK_OFF_HSUPA_BAND12_SUB_4_SetDefault
+#define MPR_R6_B13_SUB_4 MPR_BACK_OFF_HSUPA_BAND13_SUB_4_SetDefault
+#define MPR_R6_B14_SUB_4 MPR_BACK_OFF_HSUPA_BAND14_SUB_4_SetDefault
+#define MPR_R6_B15_SUB_4 MPR_BACK_OFF_HSUPA_BAND15_SUB_4_SetDefault
+#define MPR_R6_B16_SUB_4 MPR_BACK_OFF_HSUPA_BAND16_SUB_4_SetDefault
+#define MPR_R6_B17_SUB_4 MPR_BACK_OFF_HSUPA_BAND17_SUB_4_SetDefault
+#define MPR_R6_B18_SUB_4 MPR_BACK_OFF_HSUPA_BAND18_SUB_4_SetDefault
+#define MPR_R6_B19_SUB_4 MPR_BACK_OFF_HSUPA_BAND19_SUB_4_SetDefault
+#define MPR_R6_B20_SUB_4 MPR_BACK_OFF_HSUPA_BAND20_SUB_4_SetDefault
+
+#define MPR_R6_B1_SUB_5 MPR_BACK_OFF_HSUPA_BAND1_SUB_5_SetDefault
+#define MPR_R6_B2_SUB_5 MPR_BACK_OFF_HSUPA_BAND2_SUB_5_SetDefault
+#define MPR_R6_B3_SUB_5 MPR_BACK_OFF_HSUPA_BAND3_SUB_5_SetDefault
+#define MPR_R6_B4_SUB_5 MPR_BACK_OFF_HSUPA_BAND4_SUB_5_SetDefault
+#define MPR_R6_B5_SUB_5 MPR_BACK_OFF_HSUPA_BAND5_SUB_5_SetDefault
+#define MPR_R6_B6_SUB_5 MPR_BACK_OFF_HSUPA_BAND6_SUB_5_SetDefault
+#define MPR_R6_B7_SUB_5 MPR_BACK_OFF_HSUPA_BAND7_SUB_5_SetDefault
+#define MPR_R6_B8_SUB_5 MPR_BACK_OFF_HSUPA_BAND8_SUB_5_SetDefault
+#define MPR_R6_B9_SUB_5 MPR_BACK_OFF_HSUPA_BAND9_SUB_5_SetDefault
+#define MPR_R6_B10_SUB_5 MPR_BACK_OFF_HSUPA_BAND10_SUB_5_SetDefault
+#define MPR_R6_B11_SUB_5 MPR_BACK_OFF_HSUPA_BAND11_SUB_5_SetDefault
+#define MPR_R6_B12_SUB_5 MPR_BACK_OFF_HSUPA_BAND12_SUB_5_SetDefault
+#define MPR_R6_B13_SUB_5 MPR_BACK_OFF_HSUPA_BAND13_SUB_5_SetDefault
+#define MPR_R6_B14_SUB_5 MPR_BACK_OFF_HSUPA_BAND14_SUB_5_SetDefault
+#define MPR_R6_B15_SUB_5 MPR_BACK_OFF_HSUPA_BAND15_SUB_5_SetDefault
+#define MPR_R6_B16_SUB_5 MPR_BACK_OFF_HSUPA_BAND16_SUB_5_SetDefault
+#define MPR_R6_B17_SUB_5 MPR_BACK_OFF_HSUPA_BAND17_SUB_5_SetDefault
+#define MPR_R6_B18_SUB_5 MPR_BACK_OFF_HSUPA_BAND18_SUB_5_SetDefault
+#define MPR_R6_B19_SUB_5 MPR_BACK_OFF_HSUPA_BAND19_SUB_5_SetDefault
+#define MPR_R6_B20_SUB_5 MPR_BACK_OFF_HSUPA_BAND20_SUB_5_SetDefault
+
+#define R6_MPR_SUB_EN R6_MPR_SUB_EN_SetDefault
+#endif
+
+
+
+#ifndef TC_PR1_2
+ #define TC_PR1_2 TC_PR1
+#endif
+#ifndef TC_PR2_2
+ #define TC_PR2_2 TC_PR2
+#endif
+#ifndef TC_PR2B_2
+ #define TC_PR2B_2 TC_PR2B
+#endif
+#ifndef TC_PR3_2
+ #define TC_PR3_2 TC_PR3
+#endif
+#ifndef TC_PR3A_2
+ #define TC_PR3A_2 TC_PR3A
+#endif
+
+//For Dual Cell
+#ifndef TC_DC_SR1
+ #define TC_DC_SR1 TC_SR2
+#endif
+#ifndef TC_DC_SR2
+ #define TC_DC_SR2 TC_SR2B
+#endif
+#ifndef TC_RXD_SR1
+ #define TC_RXD_SR1 TC_SR2B
+#endif
+#ifndef TC_RXD_SR3
+ #define TC_RXD_SR3 TC_SR3
+#endif
+
+#ifndef TC_PR3A
+ #define TC_PR3A TC_PR3+20
+#endif
+#ifndef TC_PT3A
+ #define TC_PT3A TC_PT3+20
+#endif
+#ifndef TC_PR2B
+ #define TC_PR2B TC_PR2+20
+#endif
+#ifndef TC_PT2B
+ #define TC_PT2B TC_PT2+20
+#endif
+#ifndef TC_SR2
+ #define TC_SR2 TC_SR1
+#endif
+#ifndef TC_SR2B
+ #define TC_SR2B TC_SR2
+#endif
+#ifndef TC_ST2
+ #define TC_ST2 TC_ST1
+#endif
+#ifndef TC_ST2B
+ #define TC_ST2B TC_ST2
+#endif
+#ifndef TC_ST2C
+ #define TC_ST2C TC_ST2B
+#endif
+
+#if(IS_3G_RX_POWER_OFFSET_SUPPORT)
+#define RPO_3G_ENABLE RPO_3G_ENABLE_SetDefault
+#define RPO_3G_META_ENABLE RPO_3G_META_ENABLE_SetDefault
+#endif
+
+#if IS_3G_REMOVE_MIPI
+#if (IS_3G_MIPI_SUPPORT)
+#define IS_3G_MIPI_ENABLE IS_3G_MIPI_ENABLE_SetDefault
+#define MIPI_OFFSET MIPI_OFFSET_SetDefault
+#endif
+#else
+// MIPI has been moved to CDF after Gen97.In order to make it compatible to Gen95 .
+//#define IS_3G_MIPI_ENABLE 1
+//#define MIPI_OFFSET 1
+#endif
+
+
+#if IS_URF_PCORE
+#define RX_BAND_INDICATOR_0 RX_BAND_INDICATOR_0_SetDefault
+#define RX_BAND_INDICATOR_1 RX_BAND_INDICATOR_1_SetDefault
+#define RX_BAND_INDICATOR_2 RX_BAND_INDICATOR_2_SetDefault
+#define RX_BAND_INDICATOR_3 RX_BAND_INDICATOR_3_SetDefault
+#define RX_BAND_INDICATOR_4 RX_BAND_INDICATOR_4_SetDefault
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+#define RX_BAND_INDICATOR_5 RX_BAND_INDICATOR_5_SetDefault
+#define RX_BAND_INDICATOR_6 RX_BAND_INDICATOR_6_SetDefault
+#define RX_BAND_INDICATOR_7 RX_BAND_INDICATOR_7_SetDefault
+#endif
+#endif
+
+#ifndef BAND5_AND_BAND6_INDICATOR_SetDefault
+#define BAND5_AND_BAND6_INDICATOR_SetDefault 0
+#endif
+#define BAND5_AND_BAND6_INDICATOR BAND5_AND_BAND6_INDICATOR_SetDefault
+
+#if IS_3G_B5_AND_B19_INDICATOR_SUPPORT
+#ifndef BAND5_AND_BAND19_INDICATOR_SetDefault
+#define BAND5_AND_BAND19_INDICATOR_SetDefault 0
+#endif
+#ifndef DISABLE_B5_INDICATOR_SetDefault
+#define DISABLE_B5_INDICATOR 0
+#endif
+#define BAND5_AND_BAND19_INDICATOR BAND5_AND_BAND19_INDICATOR_SetDefault
+#define DISABLE_B5_INDICATOR DISABLE_B5_INDICATOR_SetDefault
+#endif
+
+
+/*---------------------------------------------------------------------------*/
+
+#endif /* End of #ifndef UL1D_RF_COMMON_H */
+
diff --git a/mcu/interface/l1/ul1/external/ul1d_rf_public.h b/mcu/interface/l1/ul1/external/ul1d_rf_public.h
new file mode 100644
index 0000000..3bfcbde
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/ul1d_rf_public.h
@@ -0,0 +1,5179 @@
+/*******************************************************************************
+* Modification Notice :
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1d_rf_public.h
+ *
+ * Project:
+ * --------
+ * 3G Project Common File
+ *
+ * Description:
+ * ------------
+ * Definition of some of customization setting not defined in ul1d_custom_rf.h
+ * And the stuff needs to be recognized by UL1D external module (wdata.c)
+ * Also some of data structure, global data, global function prototypes to be used
+ * by inter-category module (e.g. NVRAM)
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef UL1D_RF_PUBLIC_H
+#define UL1D_RF_PUBLIC_H
+
+
+/*******************************************************************************
+** Includes
+*******************************************************************************/
+#include "ul1d_rf_cid.h"
+#include "hal_ul1_struct.h" //To use the band/freqToband common query functions
+#include "ul1d_rf_cal_poc_data.h"
+#include "mmrf_cc_global.h"
+#include "mml1_rf_global.h"
+#include "mml1_rf_public.h"
+#if IS_URF_MT6177L_RX_REFINE||IS_URF_MT6173_RX_REFINE
+#include "wrdep.h"
+#endif
+#include "mml1_dpd_def.h"
+
+#if IS_3G_ELNA_IDX_SUPPORT
+#include "mml1_fe_public.h"
+#endif
+
+#if IS_3G_TAS_INHERIT_4G_ANT
+//#include "el1d_rf_public.h"
+#include "el1d_rf_band.h"
+#endif
+
+#if IS_3G_SAR_TX_POWER_OFFSET_CONDI_SUPPORT
+#include "mml1_custom_drdi.h"
+#endif
+
+/*******************************************************************************
+** Setting for specific RF
+*******************************************************************************/
+#if IS_URF_COLUMBUS
+#define TX_CAL_SETTLING_TIME (95) /*including STX setting time*/
+#define TX_BURST_SETTLING_TIME (9) /*including TX LDO setting time*/
+#define TX_SLEEP_ENTER_TIME (1) /*including RX LDO setting time*/
+#define TX_ST1_CW_SEND_TIME (5) /*18CWs. (46T + 17T*18CWs + 17T)/75MHz = 6.84*/
+#define TX_ST2_CW_SEND_TIME (2) /*2CWs. (46T + 17T* 2CWs + 1T)/75MHz = 1.08*/
+#define TX_ST3_CW_SEND_TIME (2) /*2CWs. (46T + 17T* 2CWs + 1T)/75MHz = 1.08*/
+
+#define TC_ST1 MICROSECOND_TO_CHIP( TX_CAL_SETTLING_TIME + TX_BURST_SETTLING_TIME + TX_ST1_CW_SEND_TIME + TX_ST2_CW_SEND_TIME)
+#define TC_ST2 MICROSECOND_TO_CHIP( TX_BURST_SETTLING_TIME + TX_ST2_CW_SEND_TIME)
+#define TC_ST3 MICROSECOND_TO_CHIP( TX_SLEEP_ENTER_TIME + TX_ST3_CW_SEND_TIME)
+#define TC_ST1_UCNT US2UCNT( TX_CAL_SETTLING_TIME + TX_BURST_SETTLING_TIME + TX_ST1_CW_SEND_TIME + TX_ST2_CW_SEND_TIME)
+#define TC_ST2_UCNT US2UCNT( TX_BURST_SETTLING_TIME + TX_ST2_CW_SEND_TIME)
+#define TC_ST3_UCNT US2UCNT( TX_SLEEP_ENTER_TIME + TX_ST3_CW_SEND_TIME)
+
+#elif IS_URF_TRINITYE1||IS_URF_TRINITY_2L
+/*****************************************
+MT6293 BSI Module clock: 75MHz
+MT6293 BSI 4-wire clock: 150/2MHz = 75MHz, 1CW=17T
+BSI Event Latency = {(BSI HW lentacy [46T]) + (4-wire CW length [17T])*CW_NUM + (IDLE_CNT [1T])*(CW_NUM-1)}/75MHz
+******************************************/
+
+//#define UBSI_SEARCH_TIME (0) /*3G BSI search time: 0 for MT6293, no need to search event_idx in BSI data pool*/
+
+#define TX_CAL_SETTLING_TIME (95) /*including STX setting time*/
+#define TX_BURST_SETTLING_TIME (10) /*including TX LDO setting time*/
+#define TX_SLEEP_ENTER_TIME (1) /*including RX LDO setting time*/
+#define TX_ST1_CW_SEND_TIME (6) /*20CWs. (46T + 17T*20CWs + 19T)/75MHz = 5.7*/
+#define TX_ST2_CW_SEND_TIME (2) /*2CWs. (46T + 17T* 2CWs + 1T)/75MHz = 1.08*/
+#define TX_ST3_CW_SEND_TIME (2) /*2CWs. (46T + 17T* 2CWs + 1T)/75MHz = 1.08*/
+
+#define TC_ST1 MICROSECOND_TO_CHIP( TX_CAL_SETTLING_TIME + TX_ST1_CW_SEND_TIME + TX_ST2_CW_SEND_TIME)
+#define TC_ST2 MICROSECOND_TO_CHIP( TX_BURST_SETTLING_TIME + TX_ST2_CW_SEND_TIME)
+#define TC_ST3 MICROSECOND_TO_CHIP( TX_SLEEP_ENTER_TIME + TX_ST3_CW_SEND_TIME)
+#else
+#define UBSI_SEARCH_TIME (6) /*3G BSI search time for 472 CW depth at 80MHz CLK*/
+
+#if defined(L1_SIM)
+#define TX_CAL_SETTLING_TIME (102+10+10) /*including STX setting time, add 10us for xL1sim 0.5us/CW Usim handling*/
+#else
+#define TX_CAL_SETTLING_TIME (102) /*including STX setting time*/
+#endif
+#define TX_BURST_SETTLING_TIME (20) /*including TX LDO setting time*/
+#define TX_SLEEP_ENTER_TIME (1) /*including RX LDO setting time*/
+#define TX_ST1_CW_SEND_TIME (10) /*22CWs. 0.41us/CW (include BSI_W to BSI_TOP time) over 5 wire BSI at 60.6MHz CLK (AP CLK)*/
+#define TX_ST2_CW_SEND_TIME (3) /*5CWs. 0.41us/CW (include BSI_W to BSI_TOP time) over 5 wire BSI at 60.6MHz CLK (AP CLK)*/
+
+#define TC_ST1 MICROSECOND_TO_CHIP( TX_CAL_SETTLING_TIME + TX_BURST_SETTLING_TIME + 2*UBSI_SEARCH_TIME + TX_ST1_CW_SEND_TIME + TX_ST2_CW_SEND_TIME)
+#define TC_ST2 MICROSECOND_TO_CHIP( TX_BURST_SETTLING_TIME + UBSI_SEARCH_TIME + TX_ST2_CW_SEND_TIME)
+#define TC_ST3 MICROSECOND_TO_CHIP( TX_SLEEP_ENTER_TIME )
+#endif
+
+#if IS_URF_MT6177L_RX
+/* RX Timing */
+#if IS_MT6177L_PHONE_CALL_RX
+/*Use MT6179 timing*/
+#define RX_CAL_SETTLING_TIME (140) /*including SRX setting time*/
+#else
+/*Use Table 1-6 FDD SRX settling time, in MT6177L_SRX_L1_Programming_Guide*/
+#define RX_CAL_SETTLING_TIME (125) /*including SRX setting time*/
+#endif
+
+/*Use Figure 2-6 FDD/C2K Warm-up and Burst Mode, in MT6177L_E2MP_RX_L1_Programming_Guide*/
+#define RX_BURST_SETTLING_TIME (20) /*including RX LDO setting time*/
+#define RX_SLEEP_ENTER_TIME (20) /*including RX LDO setting time*/
+
+#define RX_SR1_CW_SEND_TIME (5) /*17CWs. (46T + 17T*17CWs + 16T)/75MHz = 4.68*/
+#define RX_SR2_CW_SEND_TIME (1) /*1CWs. (46T + 17T* 1CWs + 0T)/75MHz = 0.840*/
+#define UBSI_PENDDING_STR1 (RX_SR1_CW_SEND_TIME)
+#define UBSI_PENDDING_STR2 (RX_SR2_CW_SEND_TIME + TX_ST2_CW_SEND_TIME)
+
+#elif IS_URF_MT6173_RX
+/* RX Timing */
+#if IS_MT6173_PHONE_CALL_RX
+/*Use MT6179 timing*/
+#define RX_CAL_SETTLING_TIME (140) /*including SRX setting time*/
+#else
+/*Use Table 1-6 FDD SRX settling time, in MT6173_SRX_L1_Programming_Guide*/
+#define RX_CAL_SETTLING_TIME (125) /*including SRX setting time*/
+#endif
+
+/*Use Figure 2-6 FDD/C2K Warm-up and Burst Mode, in MT6173_E2MP_RX_Digital_document_V0p2_B60829*/
+#define RX_BURST_SETTLING_TIME (20) /*including RX LDO setting time*/
+#define RX_SLEEP_ENTER_TIME (20) /*including RX LDO setting time*/
+
+#define RX_SR1_CW_SEND_TIME (5) /*16CWs. (46T + 17T*16CWs + 15T)/75MHz = 4.44*/
+#define RX_SR2_CW_SEND_TIME (1) /*1CWs. (46T + 17T* 1CWs + 0T)/75MHz = 0.840*/
+#define UBSI_PENDDING_STR1 (RX_SR1_CW_SEND_TIME)
+#define UBSI_PENDDING_STR2 (RX_SR2_CW_SEND_TIME + TX_ST2_CW_SEND_TIME)
+
+#elif IS_URF_TRINITYE1_RX
+/* RX Timing */
+#if IS_TRINITYE1_PHONE_CALL_RX
+/*Use MT6179 timing*/
+#define RX_CAL_SETTLING_TIME (140) /*including SRX setting time*/
+#else
+/*Use Table 1-6 FDD SRX settling time, in MT6173_SRX_L1_Programming_Guide*/
+#define RX_CAL_SETTLING_TIME (95) /*including SRX setting time*/
+#endif
+
+/*Use Figure 2-5 FDD/C2K Warm-up and Burst Mode in Trinity_RX_Programming_Guide_0p1_20170607.docx*/
+#define RX_BURST_SETTLING_TIME (20) /*including RX LDO setting time*/
+#define RX_SLEEP_ENTER_TIME (20) /*including RX LDO setting time*/
+
+#define RX_SR1_CW_SEND_TIME (4) /*10CWs. (46T + 17T*10CWs + 10T)/75MHz = 3.01*/
+#define RX_SR2_CW_SEND_TIME (1) /*1CWs. (46T + 17T* 1CWs + 0T)/75MHz = 0.84*/
+#define UBSI_PENDDING_STR1 (RX_SR1_CW_SEND_TIME)
+#define UBSI_PENDDING_STR2 (RX_SR2_CW_SEND_TIME + TX_ST2_CW_SEND_TIME)
+
+#elif IS_URF_TRINITY2L_RX
+/* RX Timing */
+#if IS_TRINITY2L_PHONE_CALL_RX
+/*Use MT6179 timing*/
+#define RX_CAL_SETTLING_TIME (140) /*including SRX setting time*/
+#else
+/*Use Table 1-6 FDD SRX settling time, in MT6173_SRX_L1_Programming_Guide*/
+#define RX_CAL_SETTLING_TIME (95) /*including SRX setting time*/
+#endif
+
+/*Use Figure 2-5 FDD/C2K Warm-up and Burst Mode in Trinity_RX_Programming_Guide_0p1_20170607.docx*/
+#define RX_BURST_SETTLING_TIME (20) /*including RX LDO setting time*/
+#define RX_SLEEP_ENTER_TIME (20) /*including RX LDO setting time*/
+
+#define RX_SR1_CW_SEND_TIME (4) /*10CWs. (46T + 17T*10CWs + 10T)/75MHz = 3.01*/
+#define RX_SR2_CW_SEND_TIME (1) /*1CWs. (46T + 17T* 1CWs + 0T)/75MHz = 0.84*/
+#define UBSI_PENDDING_STR1 (RX_SR1_CW_SEND_TIME)
+#define UBSI_PENDDING_STR2 (RX_SR2_CW_SEND_TIME + TX_ST2_CW_SEND_TIME)
+
+#elif IS_URF_COLUMBUS_RX
+#define RX_CAL_SETTLING_TIME (95) /*including SRX setting time*/
+#define RX_BURST_SETTLING_TIME (15) /*including RX LDO setting time*/
+#define RX_SLEEP_ENTER_TIME (1) /*including RX LDO setting time*/
+
+#define RX_SR1_CW_SEND_TIME (1) /*17CWs. 17CW*50ns = 0.85us*/
+#define RX_SR2_CW_SEND_TIME (0) /* 1CWs. 1CW*50ns = 0.05us*/
+#define UBSI_PENDDING_STR1 (RX_SR1_CW_SEND_TIME)
+#define UBSI_PENDDING_STR2 (RX_SR2_CW_SEND_TIME + TX_ST2_CW_SEND_TIME)
+
+#else
+/* RX Timing */
+
+#define RX_CAL_SETTLING_TIME (125) /*including SRX setting time*/
+#define RX_BURST_SETTLING_TIME (20) /*including RX LDO setting time*/
+#define RX_SLEEP_ENTER_TIME (20) /*including RX LDO setting time*/
+
+#define RX_SR1_CW_SEND_TIME (4) /*14CWs. 0.26us/CW over 5 wire BSI at 60MHz CLK*/
+#define RX_SR2_CW_SEND_TIME (2) /*7CWs. 0.26us/CW over 5 wire BSI at 60MHz CLK*/
+#define UBSI_PENDDING_STR1 (2*(UBSI_SEARCH_TIME + RX_SR1_CW_SEND_TIME)) /*20us*/
+#define UBSI_PENDDING_STR2 (2*(UBSI_SEARCH_TIME + RX_SR2_CW_SEND_TIME) + (UBSI_SEARCH_TIME + TX_ST2_CW_SEND_TIME)) /*23us*/
+#endif
+
+#if IS_MT6177L_PHONE_CALL_RX || IS_MT6173_PHONE_CALL_RX || IS_TRINITYE1_PHONE_CALL_RX || IS_URF_TRINITYE1_RX || IS_TRINITY2L_PHONE_CALL_RX || IS_URF_TRINITY2L_RX || IS_URF_COLUMBUS
+/*Use MT6179 timing*/
+#define TC_SR1 MICROSECOND_TO_CHIP( RX_CAL_SETTLING_TIME + RX_BURST_SETTLING_TIME + UBSI_PENDDING_STR1 + UBSI_PENDDING_STR2 )
+#define TC_SR2 MICROSECOND_TO_CHIP( RX_BURST_SETTLING_TIME + UBSI_PENDDING_STR2 )
+#define TC_SR3 MICROSECOND_TO_CHIP( RX_SLEEP_ENTER_TIME )
+#define TC_SR1_UCNT US2UCNT( RX_CAL_SETTLING_TIME + RX_BURST_SETTLING_TIME + UBSI_PENDDING_STR1 + UBSI_PENDDING_STR2 )
+#define TC_SR2_UCNT US2UCNT( RX_BURST_SETTLING_TIME + UBSI_PENDDING_STR2 )
+#define TC_SR3_UCNT US2UCNT( RX_SLEEP_ENTER_TIME )
+#else
+/*Remove RX_BURST_SETTLING_TIME from TC_SR1 */
+/*Since in Table 1-6 FDD SRX settling time of MT6177L_SRX_L1_Programming_Guide*/
+/*FDD SRX settling time Can be overlapped by Burst for FDD RX Warm-up mode */
+#define TC_SR1 MICROSECOND_TO_CHIP( RX_CAL_SETTLING_TIME + UBSI_PENDDING_STR1 + UBSI_PENDDING_STR2 )
+#define TC_SR2 MICROSECOND_TO_CHIP( RX_BURST_SETTLING_TIME + UBSI_PENDDING_STR2 )
+#define TC_SR3 MICROSECOND_TO_CHIP( RX_SLEEP_ENTER_TIME )
+#endif
+
+/*MT6169*/
+#if IS_URF_COLUMBUS
+#define END_BOUNDARY_OFFSET_UCNT (83200)//4*256/3.84*312
+#define TC_DC_SR1_UCNT (END_BOUNDARY_OFFSET_UCNT) // Align FEC off time at symbol 1. MUST ahead to TC_DC_SR2.
+#define TC_DC_SR2_UCNT (TC_SR1_UCNT) //DC RX SRX on timing(SR1).
+#define TC_DC_SR2B_UCNT (TC_SR2_UCNT) //DC RX on timing(SR2).
+#endif
+
+#define END_BOUNDARY_OFFSET (4*256)
+ /* BSI Event timing RXCAL & TXCAL, [Paul] only use it in ORION_FDD*/
+#define TC_SR1_CAL MICROSECOND_TO_CHIP(610) // "RX cal timing"+"BSI send time length"+"reserved timing margin" =550us + 10us +10us + 40us (for RXDFE active wait + IQ settling time)
+#define TC_SR2_CAL MICROSECOND_TO_CHIP(10) //"reserved BSI event send time(about for 10 events)"
+#define TC_ST_CAL MICROSECOND_TO_CHIP(0) //"reserved BSI event send time(about for 10 events)"
+
+/*to do, check DC, RXD timing*/
+/* BSI Event timing for Dual cell & RXD reconfig */
+#if MT6169_TO_DO
+#define TC_DC_SR1 (END_BOUNDARY_OFFSET) // Align FEC off time at symbol 1. MUST ahead to TC_DC_SR2.
+#define TC_DC_SR2 (TC_SR1) //DC RX SRX on timing(SR1).
+#define TC_DC_SR2B (TC_SR2) //DC RX on timing(SR2).
+#define TC_RXD_SR1 MICROSECOND_TO_CHIP(25) //doesn't matter, no RXD reconfiguration event @ MT6583
+#define TC_RXD_SR3 MICROSECOND_TO_CHIP(20) //doesn't matter, No RXD reconfiguration event @ MT6583
+#endif
+
+/*--------------------------------------------------------*/
+/* TRX IO Setting Define */
+/*--------------------------------------------------------*/
+#define UL1_RX_LNA_PORT_SELECT_SHIFT (5)
+#if IS_URF_MT6179||IS_URF_MT6177L_RX
+#define UL1_RX_LNA_PORT_P0 (0x1 << (UL1_RX_LNA_PORT_SELECT_SHIFT)) /*NonUsed*/
+#define UL1_RX_LNA_PORT_P1 (0x2 << (UL1_RX_LNA_PORT_SELECT_SHIFT))
+#define UL1_RX_LNA_PORT_P2 (0x3 << (UL1_RX_LNA_PORT_SELECT_SHIFT))
+#define UL1_RX_LNA_PORT_P3 (0x4 << (UL1_RX_LNA_PORT_SELECT_SHIFT))
+#define UL1_RX_LNA_PORT_P4 (0x5 << (UL1_RX_LNA_PORT_SELECT_SHIFT))
+#define UL1_RX_LNA_PORT_P5 (0x6 << (UL1_RX_LNA_PORT_SELECT_SHIFT))
+#define UL1_RX_LNA_PORT_P6 (0x7 << (UL1_RX_LNA_PORT_SELECT_SHIFT))
+#define UL1_RX_LNA_PORT_P7 (0x8 << (UL1_RX_LNA_PORT_SELECT_SHIFT))
+#else // MT6176
+#define UL1_RX_LNA_PORT_P0 (0x1 << (UL1_RX_LNA_PORT_SELECT_SHIFT + 0)) /*NonUsed*/
+#define UL1_RX_LNA_PORT_P1 (0x1 << (UL1_RX_LNA_PORT_SELECT_SHIFT + 1))
+#define UL1_RX_LNA_PORT_P2 (0x1 << (UL1_RX_LNA_PORT_SELECT_SHIFT + 2))
+#define UL1_RX_LNA_PORT_P3 (0x1 << (UL1_RX_LNA_PORT_SELECT_SHIFT + 3))
+#define UL1_RX_LNA_PORT_P4 (0x1 << (UL1_RX_LNA_PORT_SELECT_SHIFT + 4))
+#endif
+
+#define UL1_RX_LNA_GROUP_SELECT_SHIFT (0)
+#define UL1_RX_LNA_GROUP_G1 (0x1 << (UL1_RX_LNA_GROUP_SELECT_SHIFT + 0))
+#define UL1_RX_LNA_GROUP_G2 (0x1 << (UL1_RX_LNA_GROUP_SELECT_SHIFT + 1))
+#define UL1_RX_LNA_GROUP_G3 (0x1 << (UL1_RX_LNA_GROUP_SELECT_SHIFT + 2))
+#define UL1_RX_LNA_GROUP_G4 (0x1 << (UL1_RX_LNA_GROUP_SELECT_SHIFT + 3))
+
+#if (!IS_URF_MT6179)
+/** Tx Port selection */
+#define UL1_TX_BSEL_LB_SHIFT (0)
+#define UL1_TX_BSEL_MB_SHIFT (5)
+#define UL1_TX_BSEL_HB_SHIFT (10)
+#endif
+
+#if IS_URF_MT6179||IS_URF_MT6177L_RX
+#define M_UNPACK_LNA_PORT_VALUE(x) ((x >> UL1_RX_LNA_PORT_SELECT_SHIFT) & 0xF)
+#else // MT6176
+#define M_UNPACK_LNA_PORT_VALUE(x) ((x >> UL1_RX_LNA_PORT_SELECT_SHIFT) & 0x3F)
+#endif
+
+#define M_UNPACK_LNA_GROUP_VALUE(x) ((x >> UL1_RX_LNA_GROUP_SELECT_SHIFT) & 0xF)
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if IS_URF_TRINITY_2L
+/* RF RX IO port setting */
+/* Refer to 3.1 in "TrinityL_RX_Programming_Guide_0p1_20171207.docx" */
+typedef enum
+{
+ LNA_RX_PMHB1,
+ LNA_RX_PMHB2,
+ LNA_RX_PMHB3,
+ LNA_RX_PMHB4,
+ LNA_RX_PMHB5,
+ LNA_RX_PMHB6,
+ LNA_RX_PMHB7,
+ LNA_RX_PMHB8,
+ LNA_RX_PLB1,
+ LNA_RX_PLB2,
+ LNA_RX_PLB3,
+ LNA_RX_PLB4,
+ LNA_RX_PLB5,
+ LNA_RX_PLAAUHB1,
+ LNA_RX_PLAAUHB2,
+ LNA_MAIN_NONUSED,
+}UL1_RF_RX_IO_E;
+
+/* RF RXD IO port setting */
+/* Refer to 3.1 in "TrinityL_RX_Programming_Guide_0p1_20171207.docx" */
+typedef enum
+{
+ LNA_RX_DMHB1,
+ LNA_RX_DMHB2,
+ LNA_RX_DMHB3,
+ LNA_RX_DMHB4,
+ LNA_RX_DMHB5,
+ LNA_RX_DMHB6,
+ LNA_RX_DMHB7,
+ LNA_RX_DMHB8,
+ LNA_RX_DLB1,
+ LNA_RX_DLB2,
+ LNA_RX_DLB3,
+ LNA_RX_DLB4,
+ LNA_RX_DLB5,
+ LNA_RX_DLAAUHB1,
+ LNA_RX_DLAAUHB2,
+ LNA_RXD_NONUSED,
+}UL1_RF_RXD_IO_E;
+
+#define NON_USED_BAND (15)//(LNA_RXD_NONUSED)
+
+#elif IS_URF_TRINITY_L
+/* RF RX IO port setting */
+/* Refer to 3.1 in "TrinityL_RX_Programming_Guide_0p1_20171207.docx" */
+typedef enum
+{
+ LNA_RX_PMHB1,
+ LNA_RX_PMHB2,
+ LNA_RX_PMHB3,
+ LNA_RX_PMHB4,
+ LNA_RX_PMHB5,
+ LNA_RX_PMHB6,
+ LNA_RX_PMHB7,
+ LNA_RX_PMHB8,
+ LNA_RX_PLB1,
+ LNA_RX_PLB2,
+ LNA_RX_PLB3,
+ LNA_RX_PLB4,
+ LNA_RX_PLB5,
+ LNA_RX_PLAAUHB1,
+ LNA_RX_PLAAUHB2,
+ LNA_MAIN_NONUSED,
+}UL1_RF_RX_IO_E;
+
+/* RF RXD IO port setting */
+/* Refer to 3.1 in "TrinityL_RX_Programming_Guide_0p1_20171207.docx" */
+typedef enum
+{
+ LNA_RX_DMHB1,
+ LNA_RX_DMHB2,
+ LNA_RX_DMHB3,
+ LNA_RX_DMHB4,
+ LNA_RX_DMHB5,
+ LNA_RX_DMHB6,
+ LNA_RX_DMHB7,
+ LNA_RX_DMHB8,
+ LNA_RX_DLB1,
+ LNA_RX_DLB2,
+ LNA_RX_DLB3,
+ LNA_RX_DLB4,
+ LNA_RX_DLB5,
+ LNA_RX_DLAAUHB1,
+ LNA_RX_DLAAUHB2,
+ LNA_RXD_NONUSED,
+}UL1_RF_RXD_IO_E;
+
+#define NON_USED_BAND (15)//(LNA_RXD_NONUSED)
+
+#elif IS_URF_TRINITYE1
+/* RF RX IO port setting */
+/* Refer to 3.1 in "Trinity_RX_Programming_Guide_0p1_20170607.docx" */
+typedef enum
+{
+ LNA_RX_PMHB1,
+ LNA_RX_PMHB2,
+ LNA_RX_PMHB3,
+ LNA_RX_PMHB4,
+ LNA_RX_PMHB5,
+ LNA_RX_PMHB6,
+ LNA_RX_PMHB7,
+ LNA_RX_PMHB8,
+ LNA_RX_PMHB9,
+ LNA_RX_PMHB10,
+ LNA_RX_PLAAUHB1,
+ LNA_RX_PLAAUHB2,
+ LNA_RX_PLB1,
+ LNA_RX_PLB2,
+ LNA_RX_PLB3,
+ LNA_RX_PLB4,
+ LNA_RX_PLB5,
+ LNA_RX_PLB6,
+ LNA_MAIN_NONUSED,
+}UL1_RF_RX_IO_E;
+
+/* RF RXD IO port setting */
+/* Refer to 3.1 in "Trinity_RX_Programming_Guide_0p1_20170607.docx" */
+typedef enum
+{
+ LNA_RX_DMHB1,
+ LNA_RX_DMHB2,
+ LNA_RX_DMHB3,
+ LNA_RX_DMHB4,
+ LNA_RX_DMHB5,
+ LNA_RX_DMHB6,
+ LNA_RX_DMHB7,
+ LNA_RX_DMHB8,
+ LNA_RX_DMHB9,
+ LNA_RX_DMHB10,
+ LNA_RX_DLAAUHB1,
+ LNA_RX_DLAAUHB2,
+ LNA_RX_DLB1,
+ LNA_RX_DLB2,
+ LNA_RX_DLB3,
+ LNA_RX_DLB4,
+ LNA_RXD_NONUSED,
+}UL1_RF_RXD_IO_E;
+
+#define NON_USED_BAND (18)//(LNA_RXD_NONUSED)
+
+#elif IS_URF_MT6173_RX
+/* RF RX IO port setting */
+/* "Refer to 3.1.1 in "MT6173_E2_RX_3WirePG_V3p0.docx"*/
+typedef enum
+{
+ LNA_PRX1,
+ LNA_PRX2,
+ LNA_PRX3,
+ LNA_PRX4,
+ LNA_PRX5,
+ LNA_PRX6,
+ LNA_PRX7,
+ LNA_PRX8,
+ LNA_PRX9,
+ LNA_PRX10,
+ LNA_MAIN_NONUSED,
+}UL1_RF_RX_IO_E;
+
+/* RF RXD IO port setting */
+/* "Refer to 3.1.2 in "MT6173_E2_RX_3WirePG_V3p0.docx"*/
+typedef enum
+{
+ LNA_DRX1,
+ LNA_DRX2,
+ LNA_DRX3,
+ LNA_DRX4,
+ LNA_DRX5,
+ LNA_DRX6,
+ LNA_DRX7,
+ LNA_DRX8,
+ LNA_DRX9,
+ LNA_DRX10,
+ LNA_RXD_NONUSED,
+}UL1_RF_RXD_IO_E;
+
+#define NON_USED_BAND (10)
+#elif IS_URF_MT6177L_RX
+// Move to Wrdep
+
+typedef enum
+{
+ LNA_PRX1,
+ LNA_PRX2,
+ LNA_PRX3,
+ LNA_PRX4,
+ LNA_PRX5,
+ LNA_PRX6,
+ LNA_PRX7,
+ LNA_PRX8,
+ LNA_PRX9,
+ LNA_PRX10,
+ LNA_PRX11,
+ LNA_PRX12,
+ LNA_PRX13,
+ LNA_PRX14,
+ LNA_LAAP1,
+ LNA_MAIN_NONUSED,
+}UL1_RF_RX_IO_E;
+
+
+typedef enum
+{
+ LNA_DRX1,
+ LNA_DRX2,
+ LNA_DRX3,
+ LNA_DRX4,
+ LNA_DRX5,
+ LNA_DRX6,
+ LNA_DRX7,
+ LNA_DRX8,
+ LNA_DRX9,
+ LNA_DRX10,
+ LNA_DRX11,
+ LNA_DRX12,
+ LNA_DRX13,
+ LNA_DRX14,
+ LNA_LAAD1,
+ LNA_RXD_NONUSED,
+}UL1_RF_RXD_IO_E;
+
+
+#define NON_USED_BAND (15)//(LNA_RXD_NONUSED)
+
+#else
+
+#define NON_USED_BAND (0xFF)
+
+typedef enum
+{
+#if (IS_URF_MT6179 || IS_URF_ORION_HPLUS)
+ LNA_PRX1,
+ LNA_PRX2,
+ LNA_PRX3,
+ LNA_PRX4,
+ LNA_PRX5,
+ LNA_PRX6,
+ LNA_PRX7,
+ LNA_PRX8,
+ LNA_PRX9,
+ LNA_PRX10,
+ LNA_PRX11,
+ LNA_PRX12,
+ LNA_PRX13,
+ LNA_PRX14,
+ LNA_PRX15,
+ LNA_PRX16,
+ LNA_PRX17,
+ LNA_PRX18,
+ LNA_PRX19,
+ LNA_PRX20,
+ LNA_PRX21,
+ LNA_PRX22,
+#else // MT6176
+ LNA_PRX1 = (UL1_RX_LNA_GROUP_G4 | UL1_RX_LNA_PORT_P1),
+ LNA_PRX2 = (UL1_RX_LNA_GROUP_G4 | UL1_RX_LNA_PORT_P2),
+ LNA_PRX3 = (UL1_RX_LNA_GROUP_G4 | UL1_RX_LNA_PORT_P3),
+
+ LNA_PRX4 = (UL1_RX_LNA_GROUP_G3 | UL1_RX_LNA_PORT_P1),
+ LNA_PRX5 = (UL1_RX_LNA_GROUP_G3 | UL1_RX_LNA_PORT_P2),
+ LNA_PRX6 = (UL1_RX_LNA_GROUP_G3 | UL1_RX_LNA_PORT_P3),
+ LNA_PRX7 = (UL1_RX_LNA_GROUP_G3 | UL1_RX_LNA_PORT_P4),
+
+ LNA_PRX8 = (UL1_RX_LNA_GROUP_G2 | UL1_RX_LNA_PORT_P1),
+ LNA_PRX9 = (UL1_RX_LNA_GROUP_G2 | UL1_RX_LNA_PORT_P2),
+ LNA_PRX10 = (UL1_RX_LNA_GROUP_G2 | UL1_RX_LNA_PORT_P3),
+ LNA_PRX11 = (UL1_RX_LNA_GROUP_G2 | UL1_RX_LNA_PORT_P4),
+
+ LNA_PRX12 = (UL1_RX_LNA_GROUP_G1 | UL1_RX_LNA_PORT_P1),
+ LNA_PRX13 = (UL1_RX_LNA_GROUP_G1 | UL1_RX_LNA_PORT_P2),
+ LNA_PRX14 = (UL1_RX_LNA_GROUP_G1 | UL1_RX_LNA_PORT_P3),
+#endif
+ LNA_MAIN_NONUSED = NON_USED_BAND,
+}UL1_RF_RX_IO_E;
+
+typedef enum
+{
+#if (IS_URF_MT6179 || IS_URF_ORION_HPLUS)
+ LNA_DRX1,
+ LNA_DRX2,
+ LNA_DRX3,
+ LNA_DRX4,
+ LNA_DRX5,
+ LNA_DRX6,
+ LNA_DRX7,
+ LNA_DRX8,
+ LNA_DRX9,
+ LNA_DRX10,
+ LNA_DRX11,
+ LNA_DRX12,
+ LNA_DRX13,
+ LNA_DRX14,
+ LNA_DRX15,
+ LNA_DRX16,
+ LNA_DRX17,
+ LNA_DRX18,
+ LNA_DRX19,
+ LNA_DRX20,
+ LNA_DRX21,
+ LNA_DRX22,
+#else // MT6176
+ LNA_DRX1 = LNA_PRX1 ,
+ LNA_DRX2 = LNA_PRX2 ,
+ LNA_DRX3 = LNA_PRX3 ,
+
+ LNA_DRX4 = LNA_PRX4 ,
+ LNA_DRX5 = LNA_PRX5,
+ LNA_DRX6 = LNA_PRX6 ,
+ LNA_DRX7 = LNA_PRX7 ,
+
+ LNA_DRX8 = LNA_PRX8 ,
+ LNA_DRX9 = LNA_PRX9 ,
+ LNA_DRX10 = LNA_PRX10,
+ LNA_DRX11 = LNA_PRX11,
+
+ LNA_DRX12 = LNA_PRX12,
+ LNA_DRX13 = LNA_PRX13,
+ LNA_DRX14 = LNA_PRX14,
+#endif
+ LNA_RXD_NONUSED = NON_USED_BAND,
+}UL1_RF_RXD_IO_E;
+
+#endif/*IS_URF_MT6177L_RX*/
+
+/** Tx Port selection */
+#if IS_URF_TRINITYE1
+#if IS_URF_TRINITY_L
+typedef enum
+{
+ UL1_TX1_LB1,
+ UL1_TX1_LOAD,
+ UL1_TX1_MB1,
+ UL1_TX1_MB2, //new for Trinity_L
+ UL1_TX1_OFF,
+ UL1_TX0_HB1,
+ UL1_TX0_LB1,
+ UL1_TX0_LB2,
+ UL1_TX0_LOAD,
+ UL1_TX0_MB1,
+ UL1_TX0_MB2,
+ UL1_TX0_OFF,
+ UL1_TX_IO_NONUSED,
+}UL1_RF_TX_IO_E;
+
+#else
+typedef enum
+{
+ UL1_TX1_HB1,
+ UL1_TX1_HB2,
+ UL1_TX1_LB1,
+ UL1_TX1_LM1,
+ UL1_TX1_LM2,
+ UL1_TX1_MB1,
+ UL1_TX1_ULB,
+ UL1_TX2_HB1,
+ UL1_TX2_HB2,
+ UL1_TX2_LB1,
+ UL1_TX2_LM1,
+ UL1_TX2_LM2,
+ UL1_TX2_MB1,
+ UL1_TX_IO_NONUSED,
+}UL1_RF_TX_IO_E;
+#endif
+#elif IS_URF_TRINITY_2L
+typedef enum
+{
+ UL1_TX0_HB1,
+ UL1_TX0_LB1,
+ UL1_TX0_LB2,
+ UL1_TX0_LOAD,
+ UL1_TX0_MB1,
+ UL1_TX0_MB2,
+ UL1_TX0_OFF,
+ UL1_TX_IO_NONUSED,
+}UL1_RF_TX_IO_E;
+
+#elif IS_URF_MT6173
+typedef enum
+{
+ UL1_TX_LB1,
+ UL1_TX_LB2,
+ //UL1_TX_LB3,
+ //UL1_TX_LB4,
+ UL1_TX_MB1,
+ UL1_TX_MB2,
+ //UL1_TX_MB3,
+ UL1_TX_HB1,
+ UL1_TX_HB2,
+ //UL1_TX_UHB,
+ UL1_TX_IO_NONUSED,
+}UL1_RF_TX_IO_E;
+
+#elif IS_URF_MT6177L
+typedef enum
+{
+ UL1_TX_LB1,
+ UL1_TX_LB2,
+ UL1_TX_LB3,
+ UL1_TX_LB4,
+ UL1_TX_MB1,
+ UL1_TX_MB2,
+ UL1_TX_MB3,
+ UL1_TX_HB1,
+ UL1_TX_HB2,
+ UL1_TX_UHB,
+ UL1_TX_IO_NONUSED,
+}UL1_RF_TX_IO_E;
+
+#elif (IS_URF_MT6179 || IS_URF_ORION_HPLUS)
+typedef enum
+{
+ UL1_TX0_LB1,
+ UL1_TX0_LB2,
+ UL1_TX0_LB3,
+ UL1_TX0_LB4,
+ UL1_TX0_MB1,
+ UL1_TX0_MB2,
+ UL1_TX0_MB3,
+ UL1_TX0_HB1,
+ UL1_TX0_HB2,
+ UL1_TX0_UHB,
+
+ UL1_TX1_LB1,
+ UL1_TX1_LB2,
+ UL1_TX1_MB,
+ UL1_TX1_HB,
+ UL1_TX1_UHB,
+
+ UL1_TX_IO_NONUSED,
+}UL1_RF_TX_IO_E;
+#else
+typedef enum
+{
+ TX_HB1 = (0x1 << (UL1_TX_BSEL_HB_SHIFT + 0)),
+ TX_HB2 = (0x1 << (UL1_TX_BSEL_HB_SHIFT + 1)),
+
+ TX_MB1 = (0x1 << (UL1_TX_BSEL_MB_SHIFT + 0)),
+ TX_MB2 = (0x1 << (UL1_TX_BSEL_MB_SHIFT + 1)),
+ TX_MB3 = (0x1 << (UL1_TX_BSEL_MB_SHIFT + 2)),
+ TX_MB4 = (0x1 << (UL1_TX_BSEL_MB_SHIFT + 3)),
+
+ TX_LB1 = (0x1 << (UL1_TX_BSEL_LB_SHIFT + 0)),
+ TX_LB2 = (0x1 << (UL1_TX_BSEL_LB_SHIFT + 1)),
+ TX_LB3 = (0x1 << (UL1_TX_BSEL_LB_SHIFT + 2)),
+ TX_LB4 = (0x1 << (UL1_TX_BSEL_LB_SHIFT + 3)),
+
+ TX_IO_NONUSED = NON_USED_BAND,
+}UL1_RF_TX_IO_E;
+#endif //end of IS_URF_MT6179
+
+
+/*MT6169*/ #define TX_NULL_BAND NON_USED_BAND
+
+/** Tx DET Port selection */
+typedef enum
+{
+ TX_DET_IO_PORT1 = 0,
+ TX_DET_IO_PORT2 = 1,
+ TX_DET_IO_NON_USED_PORT = 0xFFFF,
+}UL1_RF_TX_DET_IO_E;
+
+//MT6293: use MML1 definition
+/** RFIC BSI ISB port definition*/
+typedef enum
+{
+#if IS_3G_RFIC_BSI_PORT_SWTICH
+ UL1D_RF_RFIC1 = 0x0002,
+ UL1D_RF_PMIC = 0x0001,
+ UL1D_RF_RFIC2 = 0x0000,
+#else
+ UL1D_RF_RFIC1 = 0x0000,
+ UL1D_RF_PMIC = 0x0001,
+ UL1D_RF_RFIC2 = 0x0002,
+#endif
+ UL1D_RF_PORT_CNT,
+}UL1D_RF_BSI_PORT_T;
+
+typedef enum
+{
+ RF_DBG_TRC_DISABLE,
+ RF_DBG_TRC_ENABLE,
+ RF_DBG_TRC_DUMP_IN_ST3,
+ RF_DBG_TRC_DUMP_IN_SR3
+} RF_DBG_TRC_E;
+
+
+/*MT6169*/ /*For RX LNA path mapping*/
+/*MT6169*/ #define LNA_HB_1 (0)
+/*MT6169*/ #define LNA_HB_2 (1)
+/*MT6169*/ #define LNA_HB_3 (2)
+/*MT6169*/ #define LNA_MB_1 (3)
+/*MT6169*/ #define LNA_MB_2 (4)
+/*MT6169*/ #define LNA_LB_1 (5)
+/*MT6169*/ #define LNA_LB_2 (6)
+/*MT6169*/ #define LNA_LB_3 (7)
+/*MT6169*/ /*Start from MT6169, use 0xFF(max) to make all projects in the future aligned with the same value, for customer's comprehension*/
+/*MT6169*/
+/*MT6169*/ /*For RXD LNA path mapping*/
+/*MT6169*/ #define LNA_RXD_HB_1 (0)
+/*MT6169*/ #define LNA_RXD_HB_2 (1)
+/*MT6169*/ #define LNA_RXD_HB_3 (2)
+/*MT6169*/ #define LNA_RXD_MB_1 (3)
+/*MT6169*/ #define LNA_RXD_MB_2 (4)
+/*MT6169*/ #define LNA_RXD_LB_1 (5)
+/*MT6169*/ #define LNA_RXD_LB_2 (6)
+/*MT6169*/ #define LNA_RXD_LB_3 (7)
+/*MT6169*/ #define LNA_RXD_NON_USED_BAND (NON_USED_BAND)
+/*MT6169*/
+ /*CW68: IOTX Table 11-5*/
+#define TX_HB_1 (0)
+#define TX_HB_2 (1)
+#define TX_MB_1 (2)
+#define TX_MB_2 (3)
+#define TX_MB_3 (4)
+#define TX_MB_4 (5)
+#define TX_LB_1 (6)
+#define TX_LB_2 (7)
+#define TX_LB_3 (8)
+#define TX_LB_4 (9)
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/*MT6169*/
+/*MT6169*/ /* PA mode Setting */ /*MT6166 PORTING NOT READY*///(start)
+/*MT6169*/ #define NUMBER_OF_VGA_DAC 10
+/*MT6169*/ #define VM_H 0
+/*MT6169*/ #define VM_M 1
+/*MT6169*/ #define VM_L 3
+/*MT6169*/ #define DC2DC_H 1
+/*MT6169*/ #define DC2DC_M 1
+/*MT6169*/ #define DC2DC_L 0
+/*MT6169*/ #define NUMBER_OF_CALI_DATA_ELEMENT 4
+/*MT6169*/ /*MT6167 PORTING NOT READY*///(End)
+/*MT6169*/ /*--------------------------------------------------------*/
+/*MT6169*/ /* Crystal solution parameter definition */
+/*MT6169*/ /*--------------------------------------------------------*/
+/*MT6169*/ #define CRYSTAL_CAPID_MAX 255
+/*MT6169*/
+////////////////////////////////////////////////////////////////////////////////
+
+/*===============================================================================================*/
+
+
+/*******************************************************************************
+** New BPI data type
+*******************************************************************************/
+typedef kal_uint32 BPI_data_type;
+
+/*******************************************************************************
+** META Factory Calibration and 3G RF tool usage
+*******************************************************************************/
+#if !defined(IS_R6_DCXO_SUPPORT)
+#define IS_R6_DCXO_SUPPORT 0
+#endif
+
+
+/*******************************************************************************
+** Constants
+*******************************************************************************/
+#define UMTS_RF_AFC_NOFFSET 0x00000
+#define CAL_TEMP_SECTION 8
+#define CAL_UARFCN_SECTION 15
+#define CAL_PWR_DETECTOR_SECTION 32
+#if IS_PATHLOSS_EXTENTION
+ #if IS_URF_COLUMBUS_RX
+ #define UL1_LNA_MODE_NUM (8)
+ #else
+ #define UL1_LNA_MODE_NUM (7)
+ #endif
+#endif
+
+#define UL1D_RF_CUSTOM_BAND (1+MAX_SUPPORTED_BAND_INDEX)
+
+#if !defined(NUMBER_OF_VGA_DAC)
+#define NUMBER_OF_VGA_DAC 96
+#endif
+
+#define UMTS_RF_CA_BAND_ROUTE_LUT_IDX_MAX 5
+#define UMTS_RF_CA_BAND_ROUTE_LUT_IDX_NONE 0xFF
+#define UMTS_RF_CA_OPT_FE_SET_LUT_IDX_MAX 5
+
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+#define MAX_SUPPORTED_BAND_INDEX (8)
+#else
+#define MAX_SUPPORTED_BAND_INDEX (5)
+#endif
+
+#define MAX_NUMBER_OF_RX_SUBBLOCK (2) // for 3C-HSDPA case
+#define MAX_NUMBER_CARRIER_OF_A_RX_SUBBLOCK (3) // for 3C-HSDPA case
+#define MAX_NUMBER_OF_TX_SUBBLOCK (1) // for DC-HSUPA case
+#define MAX_NUMBER_CARRIER_OF_A_TX_SUBBLOCK (2) // for DC-HSUPA case
+
+#define MAX_NUMBER_OF_RX_SYNTH (MAX_NUMBER_OF_RX_SUBBLOCK) //for DB-HSDPA case
+#define MAX_NUMBER_OF_TX_SYNTH (MAX_NUMBER_OF_TX_SUBBLOCK) //for DB-HSDPA case
+
+#define UMTS_CA_1ST_SHIFT (8)
+#define UMTS_CA_BAND_MASK (0xFF)
+#define UMTS_CA_2ND_SHIFT (0)
+
+#define UMTS_RF_CA_FE_NUM_MAX 5
+#define UMTS_RF_CA_BAND_NUM_MAX (UMTS_RF_CA_FE_NUM_MAX * 2) /* 10 */
+#define UMTS_RF_FRONT_END_NUM_MAX (MAX_SUPPORTED_BAND_INDEX + UMTS_RF_CA_FE_NUM_MAX) /* 10 */
+
+#define UMTS_USAGE_TBL_SIZE_MAX (MAX_SUPPORTED_BAND_INDEX + UMTS_RF_CA_BAND_NUM_MAX) /* 15 */
+#define UMTS_ROUTE_TBL_SIZE_MAX (MAX_SUPPORTED_BAND_INDEX + 2*UMTS_RF_CA_BAND_NUM_MAX) /* 25 */
+
+#define UMTS_RF_DC_TBL_SIZE (UMTS_ROUTE_TBL_SIZE_MAX + 1)
+#define UMTS_AGC_PATHLOSS_TBL_SIZE (UMTS_ROUTE_TBL_SIZE_MAX + 1)
+#define UMTS_MIPI_RX_TBL_SIZE (UMTS_USAGE_TBL_SIZE_MAX + 1)
+
+#define UMTS_FE_RXBASE_TBL_SIZE_MAX (UMTS_USAGE_TBL_SIZE_MAX)
+#define UMTS_FE_TXBASE_TBL_SIZE_MAX (UMTS_RF_FRONT_END_NUM_MAX)
+
+#define TBL_IDX_MIPI_DEFAULT 0xFFFF
+
+#define TBL_IDX_FOR_RX_BAND_INDICATOR_0 0
+#define TBL_IDX_FOR_RX_BAND_INDICATOR_1 1
+#define TBL_IDX_FOR_RX_BAND_INDICATOR_2 2
+#define TBL_IDX_FOR_RX_BAND_INDICATOR_3 3
+#define TBL_IDX_FOR_RX_BAND_INDICATOR_4 4
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+#define TBL_IDX_FOR_RX_BAND_INDICATOR_5 5
+#define TBL_IDX_FOR_RX_BAND_INDICATOR_6 6
+#define TBL_IDX_FOR_RX_BAND_INDICATOR_7 7
+#endif
+
+#if IS_3G_FDD_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+#define FREQ_INVALID 0xFFFF
+#endif
+
+/*******************************************************************************
+ * CA related
+ ******************************************************************************/
+#define UMTS_RF_CA_MAX_CC_NUM 3
+#define UMTS_RF_CA_VCO_DIV_SET_NUM 3 // [0]: RxPCC; [1]: RxSCC [2]: TxPCC
+#define UMTS_RF_CA_VCO_SET_RXPCC 0
+#define UMTS_RF_CA_VCO_SET_RXSCC 1
+#define UMTS_RF_CA_VCO_SET_TXPCC 2
+
+#define UMTS_RF_RX_VCO_DIV_SET_NUM 1
+#define UMTS_RF_RX_VCO_DIV_SET_1ST 0
+#define UMTS_RF_RX_VCO_DIV_SET_2ND 1
+#define UMTS_RF_RX_VCO_DIV_SET_3RD 2
+
+#define UMTS_RF_TX_VCO_DIV_SET_NUM 2
+#define UMTS_RF_TX_VCO_DIV_SET_1ST 0
+#define UMTS_RF_TX_VCO_DIV_SET_2ND 1
+
+#define UMTS_RF_BAND_NUM_MAX UMTSBandcount
+
+#if IS_3G_DAT_UL1_CUSTOM_SUPPORT
+/*******************************************************************************
+ * TAS definition
+ ******************************************************************************/
+#define UMTS_DAT_SCENARIO_DEFAULT (-1)
+#define UMTS_DAT_MAX_STATE_NUM 8
+#define UMTS_DAT_MAX_CAT_A_ROUTE_NUM 10
+#define UMTS_DAT_MAX_CAT_B_ROUTE_NUM 40
+#define UMTS_DAT_MAX_FE_ROUTE_NUM MAX_SUPPORTED_BAND_INDEX
+#define UMTS_DAT_MIPI_TABLE_NULL (0xFF)
+#define UMTS_DAT_FE_NULL (0xFF)
+#define UMTS_RF_UDAT_MAX_SPLIT_BAND_NUM 5
+
+#define UMTSBandNone_DAT_STATE_NUM_SetDefault 0
+#define UMTSBandNone_DAT_STATE0_CAT_A_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE0_CAT_B_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE1_CAT_A_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE1_CAT_B_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE2_CAT_A_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE2_CAT_B_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE3_CAT_A_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE3_CAT_B_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE4_CAT_A_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE4_CAT_B_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE5_CAT_A_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE5_CAT_B_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE6_CAT_A_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE6_CAT_B_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE7_CAT_A_ROUTE_SetDefault UMTS_DAT_FE_NULL
+#define UMTSBandNone_DAT_STATE7_CAT_B_ROUTE_SetDefault UMTS_DAT_FE_NULL
+
+#define UMTS_DAT_FEATURE_ENABLE(s) UMTS_DAT_FEATURE_ENABLE_##s
+
+#define UMTS_MIPI_DAT_EVENT(rt,s) UMTS_##rt##_MIPI_EVENT_##s
+#define UMTS_MIPI_DAT_DATA(rt,s) UMTS_##rt##_MIPI_DATA_##s
+
+#if IS_3G_UDAT_SUPPORT
+#define M_UMTS_SB_FE_DAT_SETTING(b,s) \
+{ \
+ b/*usage*/, \
+ { \
+ {/*state 0*/ b##_##DAT_SPLIT_NUM##_##s, \
+ { \
+ {/*split part 1*/ b##_##DAT_SPLIT_PART1_DL_END##_##s, b##_##DAT_SPLIT_PART1_STATE0_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART1_STATE0_TUNER_CONFIG##_##s}, \
+ {/*split part 2*/ b##_##DAT_SPLIT_PART2_DL_END##_##s, b##_##DAT_SPLIT_PART2_STATE0_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART2_STATE0_TUNER_CONFIG##_##s}, \
+ {/*split part 3*/ b##_##DAT_SPLIT_PART3_DL_END##_##s, b##_##DAT_SPLIT_PART3_STATE0_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART3_STATE0_TUNER_CONFIG##_##s}, \
+ {/*split part 4*/ b##_##DAT_SPLIT_PART4_DL_END##_##s, b##_##DAT_SPLIT_PART4_STATE0_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART4_STATE0_TUNER_CONFIG##_##s}, \
+ {/*split part 5*/ b##_##DAT_SPLIT_PART5_DL_END##_##s, b##_##DAT_SPLIT_PART5_STATE0_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART5_STATE0_TUNER_CONFIG##_##s} \
+ } \
+ }, \
+ {/*state 1*/ b##_##DAT_SPLIT_NUM##_##s, \
+ { \
+ {/*split part 1*/ b##_##DAT_SPLIT_PART1_DL_END##_##s, b##_##DAT_SPLIT_PART1_STATE1_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART1_STATE1_TUNER_CONFIG##_##s}, \
+ {/*split part 2*/ b##_##DAT_SPLIT_PART2_DL_END##_##s, b##_##DAT_SPLIT_PART2_STATE1_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART2_STATE1_TUNER_CONFIG##_##s}, \
+ {/*split part 3*/ b##_##DAT_SPLIT_PART3_DL_END##_##s, b##_##DAT_SPLIT_PART3_STATE1_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART3_STATE1_TUNER_CONFIG##_##s}, \
+ {/*split part 4*/ b##_##DAT_SPLIT_PART4_DL_END##_##s, b##_##DAT_SPLIT_PART4_STATE1_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART4_STATE1_TUNER_CONFIG##_##s}, \
+ {/*split part 5*/ b##_##DAT_SPLIT_PART5_DL_END##_##s, b##_##DAT_SPLIT_PART5_STATE1_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART5_STATE1_TUNER_CONFIG##_##s} \
+ } \
+ }, \
+ {/*state 2*/ b##_##DAT_SPLIT_NUM##_##s, \
+ { \
+ {/*split part 1*/ b##_##DAT_SPLIT_PART1_DL_END##_##s, b##_##DAT_SPLIT_PART1_STATE2_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART1_STATE2_TUNER_CONFIG##_##s}, \
+ {/*split part 2*/ b##_##DAT_SPLIT_PART2_DL_END##_##s, b##_##DAT_SPLIT_PART2_STATE2_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART2_STATE2_TUNER_CONFIG##_##s}, \
+ {/*split part 3*/ b##_##DAT_SPLIT_PART3_DL_END##_##s, b##_##DAT_SPLIT_PART3_STATE2_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART3_STATE2_TUNER_CONFIG##_##s}, \
+ {/*split part 4*/ b##_##DAT_SPLIT_PART4_DL_END##_##s, b##_##DAT_SPLIT_PART4_STATE2_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART4_STATE2_TUNER_CONFIG##_##s}, \
+ {/*split part 5*/ b##_##DAT_SPLIT_PART5_DL_END##_##s, b##_##DAT_SPLIT_PART5_STATE2_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART5_STATE2_TUNER_CONFIG##_##s} \
+ } \
+ }, \
+ {/*state 3*/ b##_##DAT_SPLIT_NUM##_##s, \
+ { \
+ {/*split part 1*/ b##_##DAT_SPLIT_PART1_DL_END##_##s, b##_##DAT_SPLIT_PART1_STATE3_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART1_STATE3_TUNER_CONFIG##_##s}, \
+ {/*split part 2*/ b##_##DAT_SPLIT_PART2_DL_END##_##s, b##_##DAT_SPLIT_PART2_STATE3_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART2_STATE3_TUNER_CONFIG##_##s}, \
+ {/*split part 3*/ b##_##DAT_SPLIT_PART3_DL_END##_##s, b##_##DAT_SPLIT_PART3_STATE3_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART3_STATE3_TUNER_CONFIG##_##s}, \
+ {/*split part 4*/ b##_##DAT_SPLIT_PART4_DL_END##_##s, b##_##DAT_SPLIT_PART4_STATE3_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART4_STATE3_TUNER_CONFIG##_##s}, \
+ {/*split part 5*/ b##_##DAT_SPLIT_PART5_DL_END##_##s, b##_##DAT_SPLIT_PART5_STATE3_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART5_STATE3_TUNER_CONFIG##_##s} \
+ } \
+ }, \
+ {/*state 4*/ b##_##DAT_SPLIT_NUM##_##s, \
+ { \
+ {/*split part 1*/ b##_##DAT_SPLIT_PART1_DL_END##_##s, b##_##DAT_SPLIT_PART1_STATE4_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART1_STATE4_TUNER_CONFIG##_##s}, \
+ {/*split part 2*/ b##_##DAT_SPLIT_PART2_DL_END##_##s, b##_##DAT_SPLIT_PART2_STATE4_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART2_STATE4_TUNER_CONFIG##_##s}, \
+ {/*split part 3*/ b##_##DAT_SPLIT_PART3_DL_END##_##s, b##_##DAT_SPLIT_PART3_STATE4_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART3_STATE4_TUNER_CONFIG##_##s}, \
+ {/*split part 4*/ b##_##DAT_SPLIT_PART4_DL_END##_##s, b##_##DAT_SPLIT_PART4_STATE4_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART4_STATE4_TUNER_CONFIG##_##s}, \
+ {/*split part 5*/ b##_##DAT_SPLIT_PART5_DL_END##_##s, b##_##DAT_SPLIT_PART5_STATE4_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART5_STATE4_TUNER_CONFIG##_##s} \
+ } \
+ }, \
+ {/*state 5*/ b##_##DAT_SPLIT_NUM##_##s, \
+ { \
+ {/*split part 1*/ b##_##DAT_SPLIT_PART1_DL_END##_##s, b##_##DAT_SPLIT_PART1_STATE5_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART1_STATE5_TUNER_CONFIG##_##s}, \
+ {/*split part 2*/ b##_##DAT_SPLIT_PART2_DL_END##_##s, b##_##DAT_SPLIT_PART2_STATE5_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART2_STATE5_TUNER_CONFIG##_##s}, \
+ {/*split part 3*/ b##_##DAT_SPLIT_PART3_DL_END##_##s, b##_##DAT_SPLIT_PART3_STATE5_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART3_STATE5_TUNER_CONFIG##_##s}, \
+ {/*split part 4*/ b##_##DAT_SPLIT_PART4_DL_END##_##s, b##_##DAT_SPLIT_PART4_STATE5_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART4_STATE5_TUNER_CONFIG##_##s}, \
+ {/*split part 5*/ b##_##DAT_SPLIT_PART5_DL_END##_##s, b##_##DAT_SPLIT_PART5_STATE5_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART5_STATE5_TUNER_CONFIG##_##s} \
+ } \
+ }, \
+ {/*state 6*/ b##_##DAT_SPLIT_NUM##_##s, \
+ { \
+ {/*split part 1*/ b##_##DAT_SPLIT_PART1_DL_END##_##s, b##_##DAT_SPLIT_PART1_STATE6_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART1_STATE6_TUNER_CONFIG##_##s}, \
+ {/*split part 2*/ b##_##DAT_SPLIT_PART2_DL_END##_##s, b##_##DAT_SPLIT_PART2_STATE6_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART2_STATE6_TUNER_CONFIG##_##s}, \
+ {/*split part 3*/ b##_##DAT_SPLIT_PART3_DL_END##_##s, b##_##DAT_SPLIT_PART3_STATE6_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART3_STATE6_TUNER_CONFIG##_##s}, \
+ {/*split part 4*/ b##_##DAT_SPLIT_PART4_DL_END##_##s, b##_##DAT_SPLIT_PART4_STATE6_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART4_STATE6_TUNER_CONFIG##_##s}, \
+ {/*split part 5*/ b##_##DAT_SPLIT_PART5_DL_END##_##s, b##_##DAT_SPLIT_PART5_STATE6_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART5_STATE6_TUNER_CONFIG##_##s} \
+ } \
+ }, \
+ {/*state 7*/ b##_##DAT_SPLIT_NUM##_##s, \
+ { \
+ {/*split part 1*/ b##_##DAT_SPLIT_PART1_DL_END##_##s, b##_##DAT_SPLIT_PART1_STATE7_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART1_STATE7_TUNER_CONFIG##_##s}, \
+ {/*split part 2*/ b##_##DAT_SPLIT_PART2_DL_END##_##s, b##_##DAT_SPLIT_PART2_STATE7_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART2_STATE7_TUNER_CONFIG##_##s}, \
+ {/*split part 3*/ b##_##DAT_SPLIT_PART3_DL_END##_##s, b##_##DAT_SPLIT_PART3_STATE7_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART3_STATE7_TUNER_CONFIG##_##s}, \
+ {/*split part 4*/ b##_##DAT_SPLIT_PART4_DL_END##_##s, b##_##DAT_SPLIT_PART4_STATE7_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART4_STATE7_TUNER_CONFIG##_##s}, \
+ {/*split part 5*/ b##_##DAT_SPLIT_PART5_DL_END##_##s, b##_##DAT_SPLIT_PART5_STATE7_SWITCH_CONFIG##_##s, b##_##DAT_SPLIT_PART5_STATE7_TUNER_CONFIG##_##s} \
+ } \
+ } \
+ } \
+}
+
+#else
+
+#define M_UMTS_SB_FE_DAT_SETTING(b,s) \
+{ \
+ b/*usage*/, \
+ { /*split part1*/ \
+ { /*tas route state 0*/ b##_##DAT_STATE0_CAT_A_CONFIG##_##s, b##_##DAT_STATE0_CAT_B_CONFIG##_##s}, \
+ { /*tas route state 1*/ b##_##DAT_STATE1_CAT_A_CONFIG##_##s, b##_##DAT_STATE1_CAT_B_CONFIG##_##s}, \
+ { /*tas route state 2*/ b##_##DAT_STATE2_CAT_A_CONFIG##_##s, b##_##DAT_STATE2_CAT_B_CONFIG##_##s}, \
+ { /*tas route state 3*/ b##_##DAT_STATE3_CAT_A_CONFIG##_##s, b##_##DAT_STATE3_CAT_B_CONFIG##_##s}, \
+ { /*tas route state 4*/ b##_##DAT_STATE4_CAT_A_CONFIG##_##s, b##_##DAT_STATE4_CAT_B_CONFIG##_##s}, \
+ { /*tas route state 5*/ b##_##DAT_STATE5_CAT_A_CONFIG##_##s, b##_##DAT_STATE5_CAT_B_CONFIG##_##s}, \
+ { /*tas route state 6*/ b##_##DAT_STATE6_CAT_A_CONFIG##_##s, b##_##DAT_STATE6_CAT_B_CONFIG##_##s}, \
+ { /*tas route state 7*/ b##_##DAT_STATE7_CAT_A_CONFIG##_##s, b##_##DAT_STATE7_CAT_B_CONFIG##_##s}, \
+ }, \
+}
+#endif
+
+#define UMTS_SB_DAT_CONFIGURE(band_ind,s) M_UMTS_SB_FE_DAT_SETTING(band_ind,s)
+#endif
+
+#if IS_3G_TAS_UL1_CUSTOM_SUPPORT
+/*******************************************************************************
+ * TAS definition
+ ******************************************************************************/
+// Transmit Antenna Selection Feature
+#define UMTS_RF_TAS_SET_NUM 15 //How many selection sets for each band
+#define UMTS_RF_TAS_BAND_NUM (UMTS_RF_CA_FE_NUM_MAX)
+#define UMTS_RF_TAS_TOTAL_NUM (UMTS_RF_TAS_BAND_NUM*UMTS_RF_TAS_SET_NUM)
+
+#define UMTS_TAS_MAX_STATE_NUM 8
+#define UMTS_TAS_MAX_CAT_A_ROUTE_NUM 10
+#define UMTS_TAS_MAX_CAT_B_ROUTE_NUM 10
+#define UMTS_TAS_MAX_CAT_C_ROUTE_NUM 10
+#define UMTS_TAS_MAX_FE_ROUTE_NUM MAX_SUPPORTED_BAND_INDEX
+
+#define UMTS_TAS_DISBLE (UMTS_TAS_DISABLE)
+
+#if IS_3G_TAS_INHERIT_4G_ANT
+#define UMTS_TAS_INHERIT_LTE_BAND(band) {band}
+#define UMTS_TAS_INHERIT_LTE_BAND_END {LTE_BandNone}
+#define UMTS_TAS_INHERIT_LTE_BAND_MAX_NUM LTE_Band_Supported_Max //0xFF
+
+#define UMTS_TAS_INHERIT_LTE_BAND_BITMAP_NUM 8 /* 256/32 = 8 words */
+
+#define M_UMTS_TAS_INHERIT_LTE_ANT(b,s) UMTS_TAS_INHERIT_LTE_ANT_##b##_##s
+#define UMTS_TAS_INHERIT_LTE_ANT_CONFIGURE(band_ind,s) M_UMTS_TAS_INHERIT_LTE_ANT(band_ind,s)
+
+#endif
+
+#define UMTS_TAS_VERSION(s) UMTS_TAS_VERSION_##s
+#define UMTS_TAS_FORCE_ENABLE(s) UMTS_TAS_FORCE_ENABLE_##s
+#define UMTS_TAS_FORCE_INIT_SETTING(s) UMTS_TAS_FORCE_INIT_SETTING_##s
+#define UMTS_TAS_ICS_INIT_ANT_STATE(s) UMTS_TAS_ICS_INIT_ANT_STATE_##s
+#define UMTS_TAS_ENABLE_ON_REAL_SIM(s) UMTS_TAS_ENABLE_ON_REAL_SIM_##s
+#define UMTS_TAS_ENABLE_ON_TEST_SIM(s) UMTS_TAS_ENABLE_ON_TEST_SIM_##s
+
+#define UMTS_MIPI_TAS_EVENT(rt,s) UMTS_##rt##_MIPI_EVENT_##s
+#define UMTS_MIPI_TAS_DATA(rt,s) UMTS_##rt##_MIPI_DATA_##s
+
+#if IS_3G_UTAS_SUPPORT
+#define UMTS_RF_UTAS_RF_PATH_NUM 2
+#define UMTS_RF_UTAS_MAX_SPLIT_BAND_NUM 5
+#define UMTS_RF_UTAS_SPLIT_BAND_NULL 0xFF
+
+#if IS_3G_GEN97_TAS_SUPPORT
+#define M_UMTS_SB_FE_TAS_SETTING(b,s) \
+{ \
+ b/*usage*/, \
+ /*calibration*/ b##_##TAS_CALIBRATION_INIT_SETTING##_##s, \
+ { \
+ b##_##TAS_ANT0_RSCP_BIAS##_##s, b##_##TAS_ANT1_RSCP_BIAS##_##s, \
+ b##_##TAS_ANT2_RSCP_BIAS##_##s, b##_##TAS_ANT3_RSCP_BIAS##_##s, \
+ b##_##TAS_ANT4_RSCP_BIAS##_##s, b##_##TAS_ANT5_RSCP_BIAS##_##s, \
+ b##_##TAS_ANT6_RSCP_BIAS##_##s, b##_##TAS_ANT7_RSCP_BIAS##_##s, \
+ b##_##TAS_ANT8_RSCP_BIAS##_##s, b##_##TAS_ANT9_RSCP_BIAS##_##s, \
+ b##_##TAS_ANT10_RSCP_BIAS##_##s,b##_##TAS_ANT11_RSCP_BIAS##_##s, \
+ } \
+}
+#else
+#define M_UMTS_SB_FE_TAS_SETTING(b,s) \
+{ \
+ b/*usage*/, \
+ { \
+ { /*real sim*/ b##_##TAS_REAL_SIM_TAS_ENABLE##_##s, b##_##TAS_REAL_SIM_INIT_SETTING##_##s }, \
+ { /*test sim*/ b##_##TAS_TEST_SIM_TAS_ENABLE##_##s, b##_##TAS_TEST_SIM_INIT_SETTING##_##s }, \
+ }, \
+ /*calibration*/ b##_##TAS_CALIBRATION_INIT_SETTING##_##s, \
+ /*layout group*/ b##_##TAS_ANT_LAYOUT_GROUP##_##s, \
+ { \
+ b##_##TAS_ANT0_RSCP_BIAS##_##s, b##_##TAS_ANT1_RSCP_BIAS##_##s, \
+ b##_##TAS_ANT2_RSCP_BIAS##_##s, b##_##TAS_ANT3_RSCP_BIAS##_##s, \
+ b##_##TAS_ANT4_RSCP_BIAS##_##s, b##_##TAS_ANT5_RSCP_BIAS##_##s, \
+ b##_##TAS_ANT6_RSCP_BIAS##_##s, \
+ }, \
+ { /*split part setting*/ \
+ /*split band num*/ b##_##TAS_SPLIT_NUM##_##s, \
+ { \
+ { /*split part 1*/ b##_##TAS_SPLIT_PART1_DL_END##_##s, b##_##TAS_SPLIT_PART1_TUNER_SETTING##_##s}, \
+ { /*split part 2*/ b##_##TAS_SPLIT_PART2_DL_END##_##s, b##_##TAS_SPLIT_PART2_TUNER_SETTING##_##s}, \
+ { /*split part 3*/ b##_##TAS_SPLIT_PART3_DL_END##_##s, b##_##TAS_SPLIT_PART3_TUNER_SETTING##_##s}, \
+ { /*split part 4*/ b##_##TAS_SPLIT_PART4_DL_END##_##s, b##_##TAS_SPLIT_PART4_TUNER_SETTING##_##s}, \
+ { /*split part 5*/ b##_##TAS_SPLIT_PART5_DL_END##_##s, b##_##TAS_SPLIT_PART5_TUNER_SETTING##_##s}, \
+ }, \
+ }, \
+}
+#endif
+
+#define UMTS_SB_TAS_CONFIGURE(band_ind,s) M_UMTS_SB_FE_TAS_SETTING(band_ind,s)
+
+#if IS_3G_TAS_TST_SUPPORT
+#define UMTS_TAS_TST_ENABLE_BY_RAT(s) (UMTS_TAS_TST_CONFIG_ENABLE_##s)
+
+#define M_UMTS_SB_FE_TAS_TST_SETTING(b,s) \
+{ \
+ b/*usage*/, \
+ b##_##TAS_TST_BY_ROUTE_ENABLE##_##s, \
+ {(b##_##TAS_TST_STATE0_ENABLE##_##s),(b##_##TAS_TST_STATE1_ENABLE##_##s), \
+ (b##_##TAS_TST_STATE2_ENABLE##_##s), (b##_##TAS_TST_STATE3_ENABLE##_##s), \
+ (b##_##TAS_TST_STATE4_ENABLE##_##s), (b##_##TAS_TST_STATE5_ENABLE##_##s), \
+ (b##_##TAS_TST_STATE6_ENABLE##_##s), (b##_##TAS_TST_STATE7_ENABLE##_##s), \
+ (b##_##TAS_TST_STATE8_ENABLE##_##s), (b##_##TAS_TST_STATE9_ENABLE##_##s), \
+ (b##_##TAS_TST_STATE10_ENABLE##_##s),(b##_##TAS_TST_STATE11_ENABLE##_##s), \
+ (b##_##TAS_TST_STATE12_ENABLE##_##s),(b##_##TAS_TST_STATE13_ENABLE##_##s), \
+ (b##_##TAS_TST_STATE14_ENABLE##_##s),(b##_##TAS_TST_STATE15_ENABLE##_##s), \
+ (b##_##TAS_TST_STATE16_ENABLE##_##s),(b##_##TAS_TST_STATE17_ENABLE##_##s), \
+ (b##_##TAS_TST_STATE18_ENABLE##_##s),(b##_##TAS_TST_STATE19_ENABLE##_##s), \
+ (b##_##TAS_TST_STATE20_ENABLE##_##s),(b##_##TAS_TST_STATE21_ENABLE##_##s), \
+ (b##_##TAS_TST_STATE22_ENABLE##_##s),(b##_##TAS_TST_STATE23_ENABLE##_##s)} \
+}
+
+#define UMTS_SB_TAS_TST_CONFIGURE(band_ind,s) M_UMTS_SB_FE_TAS_TST_SETTING(band_ind,s)
+#endif /*IS_3G_TAS_TST_SUPPORT*/
+
+#else /*IS_3G_UTAS_SUPPORT*/
+#define M_UMTS_SB_FE_TAS_SETTING(b,s) \
+{ \
+ b/*usage*/, \
+ b##_##TAS_STATE_NUM##_##s, \
+ { \
+ { /*real sim*/ b##_##TAS_REAL_SIM_BY_ROUTE_TAS_ENABLE##_##s, b##_##TAS_REAL_SIM_BY_ROUTE_INIT_SETTING##_##s }, \
+ { /*test sim*/ b##_##TAS_TEST_SIM_BY_ROUTE_TAS_ENABLE##_##s, b##_##TAS_TEST_SIM_BY_ROUTE_INIT_SETTING##_##s }, \
+ }, \
+ { /*split part1*/ \
+ { /*tas route state 0*/ b##_##TAS_STATE0_CAT_A_ROUTE##_##s, b##_##TAS_STATE0_CAT_B_ROUTE##_##s, b##_##TAS_STATE0_CAT_C_ROUTE##_##s }, \
+ { /*tas route state 1*/ b##_##TAS_STATE1_CAT_A_ROUTE##_##s, b##_##TAS_STATE1_CAT_B_ROUTE##_##s, b##_##TAS_STATE1_CAT_C_ROUTE##_##s }, \
+ { /*tas route state 2*/ b##_##TAS_STATE2_CAT_A_ROUTE##_##s, b##_##TAS_STATE2_CAT_B_ROUTE##_##s, b##_##TAS_STATE2_CAT_C_ROUTE##_##s }, \
+ { /*tas route state 3*/ b##_##TAS_STATE3_CAT_A_ROUTE##_##s, b##_##TAS_STATE3_CAT_B_ROUTE##_##s, b##_##TAS_STATE3_CAT_C_ROUTE##_##s }, \
+ { /*tas route state 4*/ b##_##TAS_STATE4_CAT_A_ROUTE##_##s, b##_##TAS_STATE4_CAT_B_ROUTE##_##s, b##_##TAS_STATE4_CAT_C_ROUTE##_##s }, \
+ { /*tas route state 5*/ b##_##TAS_STATE5_CAT_A_ROUTE##_##s, b##_##TAS_STATE5_CAT_B_ROUTE##_##s, b##_##TAS_STATE5_CAT_C_ROUTE##_##s }, \
+ { /*tas route state 6*/ b##_##TAS_STATE6_CAT_A_ROUTE##_##s, b##_##TAS_STATE6_CAT_B_ROUTE##_##s, b##_##TAS_STATE6_CAT_C_ROUTE##_##s }, \
+ { /*tas route state 7*/ b##_##TAS_STATE7_CAT_A_ROUTE##_##s, b##_##TAS_STATE7_CAT_B_ROUTE##_##s, b##_##TAS_STATE7_CAT_C_ROUTE##_##s }, \
+ }, \
+}
+
+#define UMTS_SB_TAS_CONFIGURE(band_ind,s) M_UMTS_SB_FE_TAS_SETTING(band_ind,s)
+
+#if IS_3G_TAS_TST_SUPPORT
+#define UMTS_TAS_TST_ENABLE_BY_RAT(s) (UMTS_TAS_TST_CONFIG_ENABLE_##s)
+
+#define M_UMTS_SB_FE_TAS_TST_SETTING(b,s) \
+{ \
+ b/*usage*/, \
+ b##_##TAS_TST_BY_ROUTE_ENABLE##_##s, \
+ ((b##_##TAS_TST_STATE0_ENABLE##_##s)<<UMTS_TAS_STATE0)|((b##_##TAS_TST_STATE1_ENABLE##_##s)<<UMTS_TAS_STATE1)| \
+ ((b##_##TAS_TST_STATE2_ENABLE##_##s)<<UMTS_TAS_STATE2)|((b##_##TAS_TST_STATE3_ENABLE##_##s)<<UMTS_TAS_STATE3)| \
+ ((b##_##TAS_TST_STATE4_ENABLE##_##s)<<UMTS_TAS_STATE4)|((b##_##TAS_TST_STATE5_ENABLE##_##s)<<UMTS_TAS_STATE5)| \
+ ((b##_##TAS_TST_STATE6_ENABLE##_##s)<<UMTS_TAS_STATE6)|((b##_##TAS_TST_STATE7_ENABLE##_##s)<<UMTS_TAS_STATE7) \
+}
+
+#define UMTS_SB_TAS_TST_CONFIGURE(band_ind,s) M_UMTS_SB_FE_TAS_TST_SETTING(band_ind,s)
+#endif /*IS_3G_TAS_TST_SUPPORT*/
+
+#endif /*IS_3G_UTAS_SUPPORT*/
+
+#endif
+
+#if IS_3G_UDAT_SUPPORT && IS_3G_UTAS_SUPPORT
+#define UMTS_RF_UANT_CON_NUM 2
+#elif IS_3G_UTAS_SUPPORT
+#define UMTS_RF_UANT_CON_NUM 1
+#else
+#define UMTS_RF_UANT_CON_NUM 0
+#endif
+
+#if IS_3G_GEN97_TAS_SUPPORT || IS_3G_GEN97_DAT_SUPPORT
+#define UMTS_RF_UANT_SPLIT_BAND_NULL 0xFF
+#endif
+
+#if IS_3G_FDD_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+#define M_UMTS_RF_INTERFERE_CHECK_SETTING(s) \
+( \
+ ((UMTS_INTERFERENCE_FREQ_TABLE0_ENABLE_##s)<<0)|((UMTS_INTERFERENCE_FREQ_TABLE1_ENABLE_##s)<<1)| \
+ ((UMTS_INTERFERENCE_FREQ_TABLE2_ENABLE_##s)<<2)|((UMTS_INTERFERENCE_FREQ_TABLE3_ENABLE_##s)<<3)| \
+ ((UMTS_INTERFERENCE_FREQ_TABLE4_ENABLE_##s)<<4)|((UMTS_INTERFERENCE_FREQ_TABLE5_ENABLE_##s)<<5)| \
+ ((UMTS_INTERFERENCE_FREQ_TABLE6_ENABLE_##s)<<6)|((UMTS_INTERFERENCE_FREQ_TABLE7_ENABLE_##s)<<7) \
+)
+
+#define UMTS_RF_INTERFERE_CHECK_CONFIGURE(s) M_UMTS_RF_INTERFERE_CHECK_SETTING(s)
+#endif
+
+/*******************************************************************************
+ * DPD define
+ ******************************************************************************/
+#define UL1_DPD_MAX_PA_LEVEL_NUM 8
+#define UL1_DPD_MAX_PGA_NUM_PER_PA 1
+#define UL1_DPD_MAX_AM_LUT_GAIN_NUM (UL1_DPD_MAX_PA_LEVEL_NUM * UL1_DPD_MAX_PGA_NUM_PER_PA) /* PA*PGA gain combination */
+#define UL1_DPD_MAX_PM_LUT_GAIN_NUM UL1_DPD_MAX_AM_LUT_GAIN_NUM /* Align AM */
+#define UL1D_DPD_MAX_PA_MODE_NUM 3
+#define UL1D_DPD_MAX_PA_HYST_NUM (UL1D_DPD_MAX_PA_MODE_NUM - 1)
+
+/*******************************************************************************
+** Macro define
+*******************************************************************************/
+#define M_UMTS_AGC_PATHLOSS_DEFAULT(x) &AGC_PATHLOSS_##x##_SetDefault
+#define M_UMTS_RX_PATHLOSS_DEFAULT(x) M_UMTS_AGC_PATHLOSS_DEFAULT(x)
+
+#define M_UMTS_AGC_PATHLOSS_RXXD_DEFAULT(x) &AGC_PATHLOSS_RXD_##x##_SetDefault
+#define M_UMTS_RX_PATHLOSS_RXD_DEFAULT(x) M_UMTS_AGC_PATHLOSS_RXXD_DEFAULT(x)
+
+#define M_UMTS_RAMPDATA_DEFAULT(x) &RampData_##x##_SetDefault
+#define M_UMTS_TX_RAMPDATA_DEFAULT(x) M_UMTS_RAMPDATA_DEFAULT(x)
+
+#define M_UMTS_PA_OCTLEV_DATA_DEFAULT(x) &PaOctLevData_##x##_SetDefault
+#define M_UMTS_TX_PA_OCTLEV_DATA_DEFAULT(x) M_UMTS_PA_OCTLEV_DATA_DEFAULT(x)
+
+#define M_UMTS_PA_DRIFT_COMP_DATA_DEFAULT(x) &PaDriftCompData_##x##_SetDefault
+#define M_UMTS_TX_PA_DRIFT_COMP_DATA_DEFAULT(x) M_UMTS_PA_DRIFT_COMP_DATA_DEFAULT(x)
+
+#define M_UMTS_RACH_TEMP_COMP_DATA_DEFAULT(x) &RACH_temperature_compensation_##x##_SetDefault
+#define M_UMTS_TX_RACH_TEMP_COMP_DATA_DEFAULT(x) M_UMTS_RACH_TEMP_COMP_DATA_DEFAULT(x)
+
+#define M_UMTS_DPD_RAMPDATA_DEFAULT(x) &DPD_RampData_##x##_SetDefault
+#define M_UMTS_DPD_TX_RAMPDATA_DEFAULT(x) M_UMTS_DPD_RAMPDATA_DEFAULT(x)
+
+#define M_UMTS_DPD_PA_OCTLEV_DATA_DEFAULT(x) &DPD_PaOctLevData_##x##_SetDefault
+#define M_UMTS_DPD_TX_PA_OCTLEV_DATA_DEFAULT(x) M_UMTS_DPD_PA_OCTLEV_DATA_DEFAULT(x)
+
+
+/*********************************************************************************/
+#define M_UMTS_AGC_PATHLOSS(x, sET) &AGC_PATHLOSS_##x##_##sET
+#define M_UMTS_RX_AGC_PATHLOSS(x, sET) M_UMTS_AGC_PATHLOSS(x, sET)
+
+#define M_UMTS_AGC_PATHLOSS_RXD(x,sET) &AGC_PATHLOSS_RXD_##x##_##sET
+#define M_UMTS_RX_AGC_PATHLOSS_RXD(x,sET) M_UMTS_AGC_PATHLOSS_RXD(x,sET)
+
+#define M_UMTS_RAMPDATA(x,sET) &RampData_##x##_##sET
+#define M_UMTS_TX_RAMPDATA(x,sET) M_UMTS_RAMPDATA(x,sET)
+
+#define M_UMTS_PA_OCTLEV_DATA(x,sET) &PaOctLevData_##x##_##sET
+#define M_UMTS_TX_PA_OCTLEV_DATA(x,sET) M_UMTS_PA_OCTLEV_DATA(x,sET)
+
+#define M_UMTS_PA_DRIFT_COMP_DATA(x,sET) &PaDriftCompData_##x##_##sET
+#define M_UMTS_TX_PA_DRIFT_COMP_DATA(x,sET) M_UMTS_PA_DRIFT_COMP_DATA(x,sET)
+
+#define M_UMTS_RACH_TEMP_COMP_DATA(x,sET) &RACH_temperature_compensation_##x##_##sET
+#define M_UMTS_TX_RACH_TEMP_COMP_DATA(x,sET) M_UMTS_RACH_TEMP_COMP_DATA(x,sET)
+
+#define UMTS_SB_DEFAULT (0xFFFF)
+
+#define M_UMTS_CA_BAND(x, y) ((x << UMTS_CA_1ST_SHIFT) | (y << UMTS_CA_2ND_SHIFT))
+
+#define M_UMTS_DPD_RAMPDATA(x,sET) &DPD_RampData_##x##_##sET
+#define M_UMTS_DPD_TX_RAMPDATA(x,sET) M_UMTS_DPD_RAMPDATA(x,sET)
+
+#define M_UMTS_DPD_PA_OCTLEV_DATA(x,sET) &DPD_PaOctLevData_##x##_##sET
+#define M_UMTS_DPD_TX_PA_OCTLEV_DATA(x,sET) M_UMTS_DPD_PA_OCTLEV_DATA(x,sET)
+
+#define M_UMTS_DPD_COMMON_CTRL_DATA_TEMP(x,sET) &DPD_CommonCtrlData_##x##_##sET
+#define M_UMTS_DPD_COMMON_CTRL_DATA(x,sET) M_UMTS_DPD_COMMON_CTRL_DATA_TEMP(x,sET)
+
+/*===============================================================================*/
+#if IS_3G_REMOVE_MIPI
+#define M_UMTS_Band_PDATA_PR1(b) PDATA_##b##_PR1_##SetDefault
+#define M_UMTS_PDATA_PR1(b) M_UMTS_Band_PDATA_PR1(b)
+
+#define M_UMTS_Band_PDATA_PR2(b) PDATA_##b##_PR2_##SetDefault
+#define M_UMTS_PDATA_PR2(b) M_UMTS_Band_PDATA_PR2(b)
+
+#define M_UMTS_Band_PDATA_PR3(b) PDATA_##b##_PR3_##SetDefault
+#define M_UMTS_PDATA_PR3(b) M_UMTS_Band_PDATA_PR3(b)
+
+#if IS_3G_RXD_FE_CONTROL_SUPPORT
+#define M_UMTS_Band_PDATA2_PR1(b) PDATA2_##b##_PR1_##SetDefault
+#define M_UMTS_PDATA2_PR1(b) M_UMTS_Band_PDATA2_PR1(b)
+
+#define M_UMTS_Band_PDATA2_PR2(b) PDATA2_##b##_PR2_##SetDefault
+#define M_UMTS_PDATA2_PR2(b) M_UMTS_Band_PDATA2_PR2(b)
+
+#define M_UMTS_Band_PDATA2_PR3(b) PDATA2_##b##_PR3_##SetDefault
+#define M_UMTS_PDATA2_PR3(b) M_UMTS_Band_PDATA2_PR3(b)
+#endif
+
+#define M_UMTS_Band_PDATA_PT1(b) PDATA_##b##_PT1_##SetDefault
+#define M_UMTS_PDATA_PT1(b) M_UMTS_Band_PDATA_PT1(b)
+
+#define M_UMTS_Band_PDATA_PT2(b) PDATA_##b##_PT2_##SetDefault
+#define M_UMTS_PDATA_PT2(b) M_UMTS_Band_PDATA_PT2(b)
+
+#define M_UMTS_Band_PDATA_PT3(b) PDATA_##b##_PT3_##SetDefault
+#define M_UMTS_PDATA_PT3(b) M_UMTS_Band_PDATA_PT3(b)
+
+#define M_UMTS_Band_RX_IO(b) b##_CHANNEL_SEL_##SetDefault
+#define M_UMTS_RX_IO(b) M_UMTS_Band_RX_IO(b)
+
+#define M_UMTS_Band_RXD_IO(b) b##_CHANNEL2_SEL_##SetDefault
+#define M_UMTS_RXD_IO(b) M_UMTS_Band_RXD_IO(b)
+
+#define M_UMTS_Band_TX_IO(b) b##_OUTPUT_SEL_##SetDefault
+#define M_UMTS_TX_IO(b) M_UMTS_Band_TX_IO(b)
+
+#define M_UMTS_Band_TX_DET_IO(b) b##_OUTPUT_DET_SEL_##SetDefault
+#define M_UMTS_TX_DET_IO(b) M_UMTS_Band_TX_DET_IO(b)
+/*===============================================================================*/
+
+#if IS_3G_RXD_FE_CONTROL_SUPPORT
+#define M_UMTS_RF_RX_PDATABASE(b) \
+{ b, \
+ {M_UMTS_PDATA_PR1(b), M_UMTS_PDATA_PR2(b), M_UMTS_PDATA_PR2(b), M_UMTS_PDATA_PR3(b), M_UMTS_PDATA_PR3(b)\
+ }, \
+ {M_UMTS_PDATA2_PR1(b), M_UMTS_PDATA2_PR2(b), M_UMTS_PDATA2_PR2(b), M_UMTS_PDATA2_PR3(b), M_UMTS_PDATA2_PR3(b)\
+ } \
+}
+#else
+#define M_UMTS_RF_RX_PDATABASE(b) \
+{ b, \
+ {M_UMTS_PDATA_PR1(b), M_UMTS_PDATA_PR2(b), M_UMTS_PDATA_PR2(b), M_UMTS_PDATA_PR3(b), M_UMTS_PDATA_PR3(b)\
+ } \
+}
+#endif
+
+#define M_UMTS_RF_TX_PDATABASE(b) \
+{ b, \
+ {M_UMTS_PDATA_PT1(b), M_UMTS_PDATA_PT2(b), M_UMTS_PDATA_PT2(b), M_UMTS_PDATA_PT3(b), M_UMTS_PDATA_PT3(b)\
+ } \
+}
+
+#define M_UMTS_RF_RXIOBASE(b) \
+{ b, {(M_UMTS_RX_IO(b)), (M_UMTS_RXD_IO(b))} \
+}
+
+#define M_UMTS_RF_TXIOBASE(b) \
+{ b, {(M_UMTS_TX_IO(b)), (M_UMTS_TX_DET_IO(b))} \
+}
+#else
+//Useless after Gen97
+#endif/*IS_3G_REMOVE_MIPI*/
+
+
+#if IS_3G_REMOVE_MIPI
+/*===============================================================================*/
+#if IS_URF_MT6177L || IS_URF_MT6173 ||IS_URF_TRINITYE1||IS_URF_TRINITY_2L // remove tx det io referenced in ul1d_custom_rf.c
+
+#if IS_3G_RXD_FE_CONTROL_SUPPORT
+#define UMTS_SB_FE_ROUTE_SETTING(x, y, z) \
+{ x, 1, \
+ { { x, \
+ { \
+/*RX IO */ { x##_CHANNEL_SEL_##z, x##_CHANNEL2_SEL_##z }, \
+/*RX BPI */ { PDATA_##x##_PR1_##z, PDATA_##x##_PR2_##z, PDATA_##x##_PR2_##z, PDATA_##x##_PR3_##z, PDATA_##x##_PR3_##z }, \
+/*RX2 BPI*/ { PDATA2_##x##_PR1_##z, PDATA2_##x##_PR2_##z, PDATA2_##x##_PR2_##z, PDATA2_##x##_PR3_##z, PDATA2_##x##_PR3_##z }, \
+/*RX MIPI*/ y \
+ }, \
+ { \
+/*TX IO */ { x##_OUTPUT_SEL_##z, TX_DET_IO_NON_USED_PORT }, \
+/*TX BPI */ { PDATA_##x##_PT1_##z, PDATA_##x##_PT2_##z, PDATA_##x##_PT2_##z, PDATA_##x##_PT3_##z, PDATA_##x##_PT3_##z }, \
+/*TX MIPI*/ y \
+ }, \
+ }, \
+ { UMTSBandNone, { {0,0}, {0,0,0}, {0,0,0}, 0 }, \
+ { {0 }, {0,0,0}, 0 } \
+ } \
+ } \
+}
+#else
+#define UMTS_SB_FE_ROUTE_SETTING(x, y, z) \
+{ x, 1, \
+ { { x, \
+ { \
+/*RX IO */ { x##_CHANNEL_SEL_##z, x##_CHANNEL2_SEL_##z }, \
+/*RX BPI */ { PDATA_##x##_PR1_##z, PDATA_##x##_PR2_##z, PDATA_##x##_PR2_##z, PDATA_##x##_PR3_##z, PDATA_##x##_PR3_##z }, \
+/*RX MIPI*/ y \
+ }, \
+ { \
+/*TX IO */ { x##_OUTPUT_SEL_##z, TX_DET_IO_NON_USED_PORT }, \
+/*TX BPI */ { PDATA_##x##_PT1_##z, PDATA_##x##_PT2_##z, PDATA_##x##_PT2_##z, PDATA_##x##_PT3_##z, PDATA_##x##_PT3_##z }, \
+/*TX MIPI*/ y \
+ }, \
+ }, \
+ { UMTSBandNone, { {0,0}, {0,0,0}, 0 }, \
+ { {0 }, {0,0,0}, 0 } \
+ } \
+ } \
+}
+#endif
+
+#endif/*IS_URF_TRINITYE1*/
+
+#define UMTS_SB_FE_PRE_SETTING(x, y, z) \
+ UMTS_SB_FE_ROUTE_SETTING(x, y, z)
+#define UMTS_SB_FE_SETTING(band_ind, sET) \
+ UMTS_SB_FE_PRE_SETTING(band_ind##_##sET, TBL_IDX_FOR_##band_ind, sET )
+
+#if IS_3G_RXD_FE_CONTROL_SUPPORT
+#define UMTS_CA_FE_ROUTE_SETTING(x, z) \
+{ \
+ x, x##_CCNUM_##z, \
+ { { x##_CC0_##z, \
+ { \
+/*RX IO */ { x##_CC0_CHANNEL_SEL_##z, x##_CC0_CHANNEL2_SEL_##z }, \
+/*RX BPI */ { x##_CC0_PDATA_PR1_##z, x##_CC0_PDATA_PR2_##z, x##_CC0_PDATA_PR2_##z, x##_CC0_PDATA_PR3_##z, x##_CC0_PDATA_PR3_##z }, \
+/*RX2 BPI*/ { x##_CC0_PDATA2_PR1_##z, x##_CC0_PDATA2_PR2_##z, x##_CC0_PDATA2_PR2_##z, x##_CC0_PDATA2_PR3_##z, x##_CC0_PDATA2_PR3_##z }, \
+/*RX MIPI*/ x##_CC0_RX_MIPI_TBL_IDX_##z \
+ }, \
+ { \
+/*TX IO */ { x##_CC0_OUTPUT_SEL_##z, x##_CC0_OUTPUT_DET_SEL_##z }, \
+/*TX BPI */ { x##_CC0_PDATA_PT1_##z, x##_CC0_PDATA_PT2_##z, x##_CC0_PDATA_PT2_##z, x##_CC0_PDATA_PT3_##z, x##_CC0_PDATA_PT3_##z }, \
+/*TX MIPI*/ x##_CC0_TX_MIPI_TBL_IDX_##z \
+ } \
+ }, \
+ { x##_CC1_##z, \
+ { \
+/*RX IO */ { x##_CC1_CHANNEL_SEL_##z, x##_CC1_CHANNEL2_SEL_##z }, \
+/*RX BPI */ { x##_CC1_PDATA_PR1_##z, x##_CC1_PDATA_PR2_##z, x##_CC1_PDATA_PR2_##z, x##_CC1_PDATA_PR3_##z, x##_CC1_PDATA_PR3_##z }, \
+/*RX2 BPI*/ { x##_CC1_PDATA2_PR1_##z, x##_CC1_PDATA2_PR2_##z, x##_CC1_PDATA2_PR2_##z, x##_CC1_PDATA2_PR3_##z, x##_CC1_PDATA2_PR3_##z }, \
+/*RX MIPI*/ x##_CC1_RX_MIPI_TBL_IDX_##z \
+ }, \
+ { \
+/*TX IO */ { x##_CC1_OUTPUT_SEL_##z, x##_CC1_OUTPUT_DET_SEL_##z }, \
+/*TX BPI */ { x##_CC1_PDATA_PT1_##z, x##_CC1_PDATA_PT2_##z, x##_CC1_PDATA_PT2_##z, x##_CC1_PDATA_PT3_##z, x##_CC1_PDATA_PT3_##z}, \
+/*TX MIPI*/ x##_CC1_TX_MIPI_TBL_IDX_##z \
+ } \
+ } \
+ } \
+}
+#else
+#define UMTS_CA_FE_ROUTE_SETTING(x, z) \
+{ \
+ x, x##_CCNUM_##z, \
+ { { x##_CC0_##z, \
+ { \
+/*RX IO */ { x##_CC0_CHANNEL_SEL_##z, x##_CC0_CHANNEL2_SEL_##z }, \
+/*RX BPI */ { x##_CC0_PDATA_PR1_##z, x##_CC0_PDATA_PR2_##z, x##_CC0_PDATA_PR2_##z, x##_CC0_PDATA_PR3_##z, x##_CC0_PDATA_PR3_##z }, \
+/*RX MIPI*/ x##_CC0_RX_MIPI_TBL_IDX_##z \
+ }, \
+ { \
+/*TX IO */ { x##_CC0_OUTPUT_SEL_##z, x##_CC0_OUTPUT_DET_SEL_##z }, \
+/*TX BPI */ { x##_CC0_PDATA_PT1_##z, x##_CC0_PDATA_PT2_##z, x##_CC0_PDATA_PT2_##z, x##_CC0_PDATA_PT3_##z, x##_CC0_PDATA_PT3_##z }, \
+/*TX MIPI*/ x##_CC0_TX_MIPI_TBL_IDX_##z \
+ } \
+ }, \
+ { x##_CC1_##z, \
+ { \
+/*RX IO */ { x##_CC1_CHANNEL_SEL_##z, x##_CC1_CHANNEL2_SEL_##z }, \
+/*RX BPI */ { x##_CC1_PDATA_PR1_##z, x##_CC1_PDATA_PR2_##z, x##_CC1_PDATA_PR2_##z, x##_CC1_PDATA_PR3_##z, x##_CC1_PDATA_PR3_##z }, \
+/*RX MIPI*/ x##_CC1_RX_MIPI_TBL_IDX_##z \
+ }, \
+ { \
+/*TX IO */ { x##_CC1_OUTPUT_SEL_##z, x##_CC1_OUTPUT_DET_SEL_##z }, \
+/*TX BPI */ { x##_CC1_PDATA_PT1_##z, x##_CC1_PDATA_PT2_##z, x##_CC1_PDATA_PT2_##z, x##_CC1_PDATA_PT3_##z, x##_CC1_PDATA_PT3_##z}, \
+/*TX MIPI*/ x##_CC1_TX_MIPI_TBL_IDX_##z \
+ } \
+ } \
+ } \
+}
+#endif
+
+#define UMTS_CA_FE_PRE_SETTING(x, z) \
+ UMTS_CA_FE_ROUTE_SETTING(x, z)
+#define UMTS_CA_FE_SETTING(ca_band_ind, sET) \
+ UMTS_CA_FE_PRE_SETTING(ca_band_ind##_##sET, sET )
+
+#if IS_3G_RXD_FE_CONTROL_SUPPORT
+#define UMTS_CA_COMPARE_RX_FE_SETTING( src, dst ) \
+ src->rx_cfg.rxIodata.rxio == dst->rx_cfg.rxIodata.rxio && \
+ src->rx_cfg.rxIodata.rxdio == dst->rx_cfg.rxIodata.rxdio && \
+ src->rx_cfg.rxPdata.pr1 == dst->rx_cfg.rxPdata.pr1 && \
+ src->rx_cfg.rxPdata.pr2 == dst->rx_cfg.rxPdata.pr2 && \
+ src->rx_cfg.rxPdata.pr2b == dst->rx_cfg.rxPdata.pr2b && \
+ src->rx_cfg.rxPdata.pr3 == dst->rx_cfg.rxPdata.pr3 && \
+ src->rx_cfg.rxPdata.pr3a == dst->rx_cfg.rxPdata.pr3a && \
+ src->rx_cfg.rxPdata2.pr1 == dst->rx_cfg.rxPdata2.pr1 && \
+ src->rx_cfg.rxPdata2.pr2 == dst->rx_cfg.rxPdata2.pr2 && \
+ src->rx_cfg.rxPdata2.pr2b == dst->rx_cfg.rxPdata2.pr2b && \
+ src->rx_cfg.rxPdata2.pr3 == dst->rx_cfg.rxPdata2.pr3 && \
+ src->rx_cfg.rxPdata2.pr3a == dst->rx_cfg.rxPdata2.pr3a && \
+ src->rx_cfg.rxMipiTblIdx == dst->rx_cfg.rxMipiTblIdx
+#else
+#define UMTS_CA_COMPARE_RX_FE_SETTING( src, dst ) \
+ src->rx_cfg.rxIodata.rxio == dst->rx_cfg.rxIodata.rxio && \
+ src->rx_cfg.rxIodata.rxdio == dst->rx_cfg.rxIodata.rxdio && \
+ src->rx_cfg.rxPdata.pr1 == dst->rx_cfg.rxPdata.pr1 && \
+ src->rx_cfg.rxPdata.pr2 == dst->rx_cfg.rxPdata.pr2 && \
+ src->rx_cfg.rxPdata.pr2b == dst->rx_cfg.rxPdata.pr2b && \
+ src->rx_cfg.rxPdata.pr3 == dst->rx_cfg.rxPdata.pr3 && \
+ src->rx_cfg.rxPdata.pr3a == dst->rx_cfg.rxPdata.pr3a && \
+ src->rx_cfg.rxMipiTblIdx == dst->rx_cfg.rxMipiTblIdx
+#endif
+
+#define UMTS_CA_COMPARE_TX_FE_SETTING( src, dst ) \
+ src->tx_cfg.txIodata.txio == dst->tx_cfg.txIodata.txio && \
+ src->tx_cfg.txPdata.pt1 == dst->tx_cfg.txPdata.pt1 && \
+ src->tx_cfg.txPdata.pt2 == dst->tx_cfg.txPdata.pt2 && \
+ src->tx_cfg.txPdata.pt2b == dst->tx_cfg.txPdata.pt2b && \
+ src->tx_cfg.txPdata.pt3 == dst->tx_cfg.txPdata.pt3 && \
+ src->tx_cfg.txPdata.pt3a == dst->tx_cfg.txPdata.pt3a && \
+ src->tx_cfg.txMipiTblIdx == dst->tx_cfg.txMipiTblIdx
+
+#else
+//Useless after Gen97
+#endif/*IS_3G_REMOVE_MIPI*/
+
+#if (IS_3G_TAS_SUPPORT)
+#define M_UMTS_TAS_BPI(value, mask, bpiData) (((value)&(mask))|(bpiData))
+
+#define UL1D_TAS_BPI_PIN_GEN(var1, var2, var3, sET) ( ((UMTS_TAS_BPI_PIN_1_##sET==UMTS_TAS_BPI_PIN_NULL_##sET)?0:((var1)<< UMTS_TAS_BPI_PIN_1_##sET))|\
+ ((UMTS_TAS_BPI_PIN_2_##sET==UMTS_TAS_BPI_PIN_NULL_##sET)?0:((var2)<< UMTS_TAS_BPI_PIN_2_##sET))|\
+ ((UMTS_TAS_BPI_PIN_3_##sET==UMTS_TAS_BPI_PIN_NULL_##sET)?0:((var3)<< UMTS_TAS_BPI_PIN_3_##sET)) )
+
+#endif/*IS_3G_TAS_SUPPORT*/
+
+// Power on CAL
+#define UMTS_Band_PWRON_CAL_DATA(b) b##_PWRON_CAL_DATA
+#define UMTS_PWRON_CAL_DATA(b) UMTS_Band_PWRON_CAL_DATA(b)
+
+#if IS_3G_SAR_TX_POWER_BACKOFF_SUPPORT
+#define SAR_3G_TABLE_NUM MML1_RF_SAR_TABLE_SCENARIO_NUM
+#define UMTS_Band_SAR_BACKOFF(b, sET) &SARBackoffData_##b##_##sET
+#define M_UMTS_SAR_BACKOFF(b, sET) UMTS_Band_SAR_BACKOFF(b, sET)
+ #if IS_3G_SAR_TX_POWER_OFFSET_CONDI_SUPPORT
+#define TPO_3G_TABLE_TYPE_NUM MML1_CUSTOM_TOTAL_SAR_TABLE_TYPE_NUM
+
+#define UMTS_Band_SAR_BACKOFF_DATA_CONDI(b, t) &SARBackoffData_##b##_##t
+#define M_UMTS_SAR_BACKOFF_DATA_CONDI(b, t) UMTS_Band_SAR_BACKOFF_DATA_CONDI(b, t)
+
+#define UMTS_Band_SAR_BACKOFF_DATA_TABLE_CONDI(t) {U_SAR_BACKOFF_TABLE_CONDI_##t}
+
+#define M_UMTS_SAR_BACKOFF_DATA_TABLE_CONDI(type) \
+{ \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBandNone, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand1, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand2, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand3, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand4, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand5, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand6, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand7, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand8, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand9, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand10, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand11, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand12, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand13, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand14, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand15, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand16, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand17, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand18, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand19, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand20, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand21, type), \
+ M_UMTS_SAR_BACKOFF_DATA_CONDI(UMTSBand22, type), \
+}
+ #endif /* IS_3G_SAR_TX_POWER_OFFSET_CONDI_SUPPORT */
+#endif
+
+
+#if IS_3G_TX_POWER_OFFSET_SUPPORT
+//#define TPO_3G_TABLE_NUM TPO_MML1_TABLE_NUM
+#define TPO_3G_TABLE_NUM MML1_RF_SWTP_TABLE_SCENARIO_NUM
+#define UMTS_Band_TX_PWR_OFFSET(b, sET) &TxPowerOffsetData_##b##_##sET
+#define M_UMTS_TX_PWR_OFFSET(b, sET) UMTS_Band_TX_PWR_OFFSET(b, sET)
+#endif
+
+#if IS_3G_TX_NSFT_POWER_OFFSET_SUPPORT
+#define UMTS_Band_TX_NSFT_PWR_OFFSET(b, sET) &TxNsftPowerOffsetData_##b##_##sET
+#define M_UMTS_TX_NSFT_PWR_OFFSET(b, sET) UMTS_Band_TX_NSFT_PWR_OFFSET(b, sET)
+#endif
+
+#if (IS_3G_RX_POWER_OFFSET_SUPPORT)
+#define UMTS_Band_RX_PWR_OFFSET(b, sET) &RxPowerOffsetData_##b##_##sET
+#define M_UMTS_RX_PWR_OFFSET(b, sET) UMTS_Band_RX_PWR_OFFSET(b,sET)
+#endif
+
+#if (IS_3G_VPA_SEL_BY_BAND_SUPPORT)
+#define M_UMTS_VPA_SRC_SEL(x,sET) &UMTS_VPA_SOURCE_##x##_##sET
+#define M_UMTS_VPA_SRC(x,sET) M_UMTS_VPA_SRC_SEL(x,sET)
+#endif/*IS_3G_VPA_SEL_BY_BAND_SUPPORT*/
+
+#if IS_3G_RFEQ_COEF_SUBBAND_SUPPORT
+#define UMTS_Band_RFEQ_COEF(b, sET) &UMTS_RFEQ_COEF_##b##_##sET
+#define M_UMTS_RFEQ_COEF(b, sET) UMTS_Band_RFEQ_COEF(b, sET)
+#endif
+
+#if IS_3G_RFEQ_REAL_COEF_TEST
+#define UMTS_Band_REAL_RFEQ_COEF(b, sET) &UMTS_RFEQ_REAL_COEF_##b##_##sET
+#define M_UMTS_REAL_RFEQ_COEF(b, sET) UMTS_Band_REAL_RFEQ_COEF(b, sET)
+#endif
+
+/*******************************************************************************
+** Typedefs
+*******************************************************************************/
+typedef struct {
+ kal_uint32 capability;
+ kal_uint32 band_support;
+ kal_uint32 rxd_band_support;
+ kal_uint32 padrift_band_support;
+ kal_uint32 wcdma_dpd_band_support;
+} UMTS_MsCapabilityEx;
+
+#if IS_URF_COLUMBUS_RX
+typedef struct
+{
+ kal_uint16 max_uarfcn;
+#if IS_PATHLOSS_EXTENTION
+ kal_int16 path_loss_HPM[UL1_LNA_MODE_NUM];
+ kal_int16 path_loss_LPM[UL1_LNA_MODE_NUM];
+ kal_int16 path_loss_TKM[UL1_LNA_MODE_NUM];
+#else
+ kal_int8 path_loss_H;
+ kal_int8 path_loss_M;
+ kal_int8 path_loss_L;
+ kal_int8 path_loss_LPM_offset;
+#endif
+} U_sAGCGAINOFFSET;
+
+typedef struct
+{
+ kal_int16 temper_offset[CAL_TEMP_SECTION];
+ U_sAGCGAINOFFSET gain_of_uarfcn[CAL_UARFCN_SECTION];
+} U_sTEMPAGCOFFSET;
+
+#else
+typedef struct
+{
+ kal_uint16 max_uarfcn;
+#if IS_PATHLOSS_EXTENTION
+ kal_int16 path_loss_HPM[UL1_LNA_MODE_NUM];
+ kal_int16 path_loss_LPM[UL1_LNA_MODE_NUM];
+#else
+ kal_int8 path_loss_H;
+ kal_int8 path_loss_M;
+ kal_int8 path_loss_L;
+ kal_int8 path_loss_LPM_offset;
+#endif
+} U_sAGCGAINOFFSET;
+
+typedef struct
+{
+ kal_int8 temper_offset[CAL_TEMP_SECTION];
+ U_sAGCGAINOFFSET gain_of_uarfcn[CAL_UARFCN_SECTION];
+} U_sTEMPAGCOFFSET;
+#endif
+
+typedef struct
+{
+ kal_uint16 level_0;
+ kal_uint16 level_1;
+} U_sDC2DC;
+
+typedef struct
+{
+ kal_uint16 start;
+ kal_uint16 end;
+} U_sHYSTERESISDATA;
+
+typedef struct
+{
+ kal_uint16 max_uarfcn;
+ kal_int16 pwr_offset_dB; /* unit: 1/32 dB, range: -8 ~ +7 dB */
+ kal_int16 pwr_offset_txdac;
+} U_sARFCN_SECTION;
+
+#if IS_3G_FDD_RX_PATH_SELECTION_SUPPORT
+typedef enum
+{
+ ANT_RX_MAIN_ONLY = 0,
+ ANT_RX_RXD_ONLY = 1,
+ ANT_RX_BOTH = 2,
+ ANT_RESUME_DEFAULT = 3
+}ANT_SEL_TYPE;
+
+typedef struct
+{
+ kal_bool rx_path_selection_enable;
+ ANT_SEL_TYPE rx_path_type;
+} U_sRxPathSelection;
+#endif
+
+typedef struct
+{
+ kal_uint8 pwr_dt_thr;
+ kal_uint8 pwr_dt_section;
+ kal_uint16 pwr_dt_dac[ CAL_PWR_DETECTOR_SECTION ];
+ kal_int16 pwr_dt_value[ CAL_PWR_DETECTOR_SECTION ]; //bit0~4 is used for fractions
+ U_sARFCN_SECTION pwr_dt_comp_by_subband[ CAL_UARFCN_SECTION ];
+ kal_int16 pwr_dt_comp_by_temperature[8][2]; //[0]:slope, [1]:offset
+} U_sPWTDTDATA;
+
+typedef struct
+{
+ kal_uint16 dc2dc_level;
+ kal_uint16 vbias_dac;
+ kal_uint8 vm1;
+ kal_uint8 vm2;
+} U_sPADATA;
+
+typedef struct
+{
+ U_sPADATA pa_data;
+ kal_uint16 vga_dac[NUMBER_OF_VGA_DAC];
+ U_sARFCN_SECTION vga_comp_by_subband[ CAL_UARFCN_SECTION ];
+ kal_int16 vga_comp_by_temperature[8][2]; //[0]:slope, [1]:offset
+} U_sTXPOWERDATA;
+
+typedef struct
+{
+ kal_int16 vga_comp_by_temperature[8][2]; //[0]:slope, [1]:offset
+} U_sRACHCOMP;
+
+
+typedef struct
+{
+ U_sRACHCOMP power_dac[3];
+} U_sPARACHTMCOMPDATA;
+
+
+typedef struct
+{
+ kal_uint16 initDac;
+ kal_int32 slope;
+} U_sAFCDACDATA;
+
+typedef struct
+{
+ kal_int32 cap_id;
+} U_sAFCCAPDATA;
+
+
+typedef struct
+{
+ U_sDC2DC pa_dc2dc;
+ U_sTXPOWERDATA power_dac[3]; //0:PA high mode, 1:PA mid mode, 2:PA low mode (use 0&1 if only 2 mode)
+ U_sHYSTERESISDATA tx_hysteresis[2];
+ U_sPWTDTDATA pwr_dt_data;
+} U_sRAMPDATA;
+
+typedef struct
+{
+ kal_uint8 pa_mode; // 2 bits
+ kal_int8 prf; // 8 bits
+ kal_uint8 dc2dc_lvl; // 5 bits // MT6589, MT6582: 6 bits
+ kal_uint8 vm1; // 1 bit
+ kal_uint8 vm2; // 1 bit
+ kal_uint16 vbias_dac; // 10 bits
+ kal_uint16 pa_gain; // 9 bits
+} U_sPMULEVHANDLE;
+
+typedef struct
+{
+ /* octlev_num_section accounts for recording the number of sections that defined by user
+ * To keep the design simple, we only allow user to use consecutive regions
+ *
+ * The two control parameters pa_phase_compensation[] and pmu_level_handle[] belong to BB TX HW
+ * funtionality and all relates to PA, though PA phase compensation only has three modes
+ * PD coupler loss by PA modes stored in power_dac[]->vga_dac[9]
+ */
+ kal_uint8 octlev_num_section;
+ kal_uint8 reserved_byte; // Use ARM compiler padding byte to store power backoff value configured by META user in Factory Mode calibration
+ kal_uint32 pa_phase_compensation[3]; // 0: PA high mode, 1: PA mid mode
+ U_sPMULEVHANDLE pmu_level_handle[8];
+ kal_uint16 pa_gain_g12a;
+ kal_uint16 pa_gain_g12b;
+} U_sPAOCTLVLSETTING;
+
+typedef struct
+{
+ kal_uint8 lut[UL1_DPD_MAX_AM_LUT_GAIN_NUM][MMDPD_MAX_AM_LUT_PWR_NUM];
+
+} U_sDPD_AMLUT_SUBBAND;
+
+typedef struct
+{
+ MMDPD_AMLUT_SUBBAND_T am_lut_subband[CAL_UARFCN_SECTION];
+
+} U_sDPD_AMLUT_PERBAND;
+
+typedef struct
+{
+ kal_int8 lut[UL1_DPD_MAX_PM_LUT_GAIN_NUM][MMDPD_MAX_PM_LUT_PWR_NUM];
+
+} U_sDPD_PMLUT_SUBBAND;
+
+typedef struct
+{
+ MMDPD_PMLUT_SUBBAND_T pm_lut_subband[CAL_UARFCN_SECTION];
+
+} U_sDPD_PMLUT_PERBAND;
+
+typedef struct
+{
+ /*DPD Normal Mode enable Flag*/
+ DPD_ENABLE_E dpd_normal_enable;
+ /* The delta term add to pa_idx_th, value from custom file */
+ kal_int16 d_tar_th_dpd;
+
+} U_sDPD_COMMON_CTRL;
+
+typedef struct
+{
+ kal_uint32 reserved0;
+}U_PCFE_CUSTOM_PARA_T;
+
+typedef struct
+{
+ kal_int16 dpd_apt_temperature_th_by_rfic[2]; // for 2 RFIC
+}U_DPD_OTFC_CUSTOM_PARA_T;
+
+typedef struct
+{
+ U_DPD_OTFC_CUSTOM_PARA_T dpd_otfc_custom;
+ U_PCFE_CUSTOM_PARA_T pcfe_custom;
+
+ /* PCFE power threshold form DPD mode to linear mode*/
+ kal_int16 pcfe_mode_th_d2l;
+
+ /* PCFE power threshold form linear mode to DPD mode*/
+ kal_int16 pcfe_mode_th_l2d;
+
+}U_UL1D_PCFE_DPD_OTFC_CUSTOM_PARA_T;
+
+#if IS_URF_TRINITYE1||IS_URF_TRINITY_2L
+#if IS_URF_TRINITY_2L
+typedef enum
+{
+ STX_PATH_0 = 0,//TX0
+ STX_PATH_COUNT,
+} STX_SEL_T;
+#else
+typedef enum
+{
+#if IS_URF_TRINITY_L
+ STX_PATH_0 = 0,//TX0
+#endif
+ STX_PATH_1 = 1,//TX1
+ STX_PATH_2, //TX2
+ STX_PATH_COUNT,
+} STX_SEL_T;
+#endif
+typedef struct
+{
+ UMTSBand band;
+ STX_SEL_T stx_path_idx;
+} UMTS_RF_STX_PATH_TABLE_T;
+
+#endif
+
+typedef enum
+{
+ ET_SW_MODE=0,
+ DPD_SW_MODE=1,
+ APT_SW_MODE=2,
+ PCFE_OP_MODE_CNT
+} SW_MODE_E;
+
+typedef struct
+{
+ kal_bool op_mode_force_en;
+ SW_MODE_E op_mode_force_mode;
+}U_PCFE_NONCUSTOM_PARA_T;
+
+typedef struct
+{
+ kal_bool en_dpd_am_track;
+ kal_bool en_dpd_pm_track;
+ kal_bool en_force_dpd_default_lut;
+ kal_bool en_dpd_coarse_tde;
+ kal_bool en_dpd_fine_tde;
+}U_DPD_OTFC_NONCUSTOM_PARA_T;
+
+typedef struct
+{
+ U_DPD_OTFC_NONCUSTOM_PARA_T dpd_otfc;
+ U_PCFE_NONCUSTOM_PARA_T pcfe;
+}U_Ul1D_PCFE_DPD_OTFC_NONCUSTOM_PARA_T;
+
+typedef struct
+{
+ /* This flag will be set to TRUE if DPD PA and DPD factory cal done */
+ kal_bool dpd_cal_done;
+
+ /* PA index selction threshold */
+ kal_int16 pa_idx_th[CAL_UARFCN_SECTION][UL1_DPD_MAX_PA_LEVEL_NUM];
+
+ /* From DPD FXP, for gain norm calculation */
+ kal_int16 f_db[CAL_UARFCN_SECTION][UL1_DPD_MAX_PA_LEVEL_NUM];
+
+ /* This value comes from DPD lab calibration */
+ kal_int16 dpd_tr[CAL_UARFCN_SECTION];
+
+ /* The temperature during DPD factory calibration */
+ kal_int8 tempe_fc[CAL_UARFCN_SECTION];
+
+} U_sDPD_COMMON_CAL;
+
+typedef struct
+{
+ U_sRAMPDATA wcdma_dpd_ramp_data;
+ U_sPAOCTLVLSETTING wcdma_dpd_pa_oct_lev_tbl;
+ U_sDPD_COMMON_CAL wcdma_dpd_common_cal;
+ U_sDPD_AMLUT_PERBAND wcdma_dpd_am_lut_perband;
+ U_sDPD_PMLUT_PERBAND wcdma_dpd_pm_lut_perband;
+
+} U_sDPD_GROUP_CAL;
+
+typedef struct
+{
+ U_sDPD_COMMON_CTRL wcdma_dpd_common_ctrl;
+ U_sDPD_GROUP_CAL wcdma_dpd_group_cal;
+
+} U_sDPD_GROUP_ALL;
+
+typedef struct
+{
+ U_sRAMPDATA *p_wcdma_dpd_ramp_data;
+ U_sPAOCTLVLSETTING *p_wcdma_dpd_pa_oct_lev_tbl;
+ U_sDPD_COMMON_CTRL *p_wcdma_dpd_common_ctrl;
+ U_sDPD_COMMON_CAL *p_wcdma_dpd_common_cal;
+ U_sDPD_AMLUT_PERBAND *p_wcdma_dpd_am_lut_perband;
+ U_sDPD_PMLUT_PERBAND *p_wcdma_dpd_pm_lut_perband;
+
+} U_sDPD_GROUP_ADDR;
+
+// Start for ADAPT IOT AMR workaround
+typedef struct
+{
+ kal_bool ADAPT_Customized;
+ kal_bool reserved1;
+ kal_bool reserved2;
+ kal_bool reserved3;
+} U_sUl1IotCustomSupportStruct;
+// End for ADAPT IOT AMR workaround
+
+#if IS_HSPA_HWTPC
+ #ifdef __HSDPA_SUPPORT__
+typedef struct
+{
+ kal_uint8 pseudo_hscch[5];
+ kal_uint8 pseudo_hdsch[5];
+ kal_uint16 beta_hs_p[15];
+ kal_uint16 beta_hs_q[15];
+} META_HWTPC_HSDPA_FRAME_INFO;
+ #endif
+
+ #ifdef __HSUPA_SUPPORT__
+typedef struct
+{
+ kal_uint8 edch_enable[5];
+ kal_uint8 is_new_tx[5];
+ kal_uint8 etfci[5];
+ kal_uint8 beta_ed_num[5];
+ kal_uint16 beta_ed0_sf[5];
+ kal_uint16 beta_ed1_sf[5];
+ kal_uint16 beta_ed2_sf[5];
+ kal_uint16 beta_ed3_sf[5];
+ kal_uint16 beta_ec[5];
+ kal_uint16 beta_ed_x_beta_c_0[5];
+ kal_uint16 beta_ed_x_beta_c_1[5];
+ kal_uint16 beta_ed_x_beta_c_2[5];
+ kal_uint16 beta_ed_x_beta_c_3[5];
+ kal_uint8 delta_harq[5];
+} META_HWTPC_HSUPA_FRAME_INFO;
+ #endif
+#endif // #if IS_HSPA_HWTPC
+
+typedef struct
+{
+ /*input*/
+ kal_uint8 tpc_step;
+ kal_uint8 itp;
+ kal_uint8 rpp;
+ kal_uint8 fmt_idx;
+ kal_uint8 dl_frame_type;
+ kal_uint16 slot_mask;
+ kal_int8 tpc_cmd[15];
+ kal_uint8 beta_c;
+ kal_uint8 beta_d;
+#if IS_HSPA_HWTPC
+ // Above is R99 original used
+ kal_uint32 normcon;
+ kal_int16 net_maxpow;
+ kal_int16 net_minpow;
+
+ #ifdef __HSDPA_SUPPORT__
+ META_HWTPC_HSDPA_FRAME_INFO hsdpa;
+ #endif
+ #ifdef __HSUPA_SUPPORT__
+ META_HWTPC_HSUPA_FRAME_INFO hsupa;
+ #endif
+#endif // #if IS_HSPA_HWTPC
+} META_HWTPC_FRAME_INFO;
+
+typedef struct
+{
+ kal_int16 pa_drift_comp_w_table[6][2];
+ kal_int16 pa_drift_comp_h_table[6][4];
+} U_sPADRIFTSETTING;
+
+typedef enum
+{
+ MPRSetting0 = 0,
+ MPRSetting1 = 1,
+ MPRSetting2 = 2,
+ MPRSetting3 = 3,
+ MPRSetting4 = 4,
+ MPRSettingCount
+} MPR_Setting;
+
+
+#if IS_3G_MPR_EXTEND_SUPPORT
+typedef enum
+{
+ MPRSetting_SUB_0 = 0,
+ MPRSetting_SUB_1 = 1,
+ MPRSetting_SUB_2 = 2,
+ MPRSetting_SUB_3 = 3,
+ MPRSetting_SUB_4 = 4,
+ MPRSetting_SUB_5 = 5,
+ MPRSetting_SUB_6 = 6,
+ MPRSetting_SUB_7 = 7,
+ MPRSetting_SUB_8 = 8,
+ MPRSetting_SUB_Count
+} MPR_Setting_SUB;
+#endif
+
+typedef enum
+{
+ UL1D_DATABASE_RXIO = 0,
+ UL1D_DATABASE_TXIO = 1,
+ UL1D_DATABASE_RX_PDATA = 2,
+ UL1D_DATABASE_TX_PDATA = 3,
+ UL1D_DATABASE_CONUT,
+ UL1D_DATABASE_INVALID = 0xFFFE,
+} UL1D_DATABASE_TYPE_E;
+
+/* CA Band definition */
+typedef enum
+{
+ UMTS_CA_BANDNONE = M_UMTS_CA_BAND(UMTSBandNone, UMTSBandNone),
+ UMTS_CA_B1_B5 = M_UMTS_CA_BAND(UMTSBand1, UMTSBand5),
+ UMTS_CA_B1_B8 = M_UMTS_CA_BAND(UMTSBand1, UMTSBand8),
+ UMTS_CA_B1_B11 = M_UMTS_CA_BAND(UMTSBand1, UMTSBand11),
+ UMTS_CA_B2_B4 = M_UMTS_CA_BAND(UMTSBand2, UMTSBand4),
+ UMTS_CA_B2_B5 = M_UMTS_CA_BAND(UMTSBand2, UMTSBand5),
+ /* Switch PCC and SCC*/
+ UMTS_CA_B5_B1 = M_UMTS_CA_BAND(UMTSBand5, UMTSBand1),
+ UMTS_CA_B8_B1 = M_UMTS_CA_BAND(UMTSBand8, UMTSBand1),
+ UMTS_CA_B11_B1 = M_UMTS_CA_BAND(UMTSBand11, UMTSBand1),
+ UMTS_CA_B4_B2 = M_UMTS_CA_BAND(UMTSBand4, UMTSBand2),
+ UMTS_CA_B5_B2 = M_UMTS_CA_BAND(UMTSBand5, UMTSBand2),
+}UMTSCaBand;
+
+typedef enum
+{
+ UMTS_Route0 = 0,
+ UMTS_Route1 = 1,
+ UMTS_Route2 = 2,
+ UMTS_Route3 = 3,
+ UMTS_Route4 = 4,
+ UMTS_Route5 = 5,
+ UMTS_Route6 = 6,
+ UMTS_Route7 = 7,
+ UMTS_Route8 = 8,
+ UMTS_Route9 = 9,
+ UMTS_Route10 = 10,
+ UMTS_Route11 = 11,
+ UMTS_Route12 = 12,
+ UMTS_Route13 = 13,
+ UMTS_Route14 = 14,
+ UMTS_Route15 = 15,
+ UMTS_Route16 = 16,
+ UMTS_Route17 = 17,
+ UMTS_Route18 = 18,
+ UMTS_Route19 = 19,
+ UMTS_Route20 = 20,
+ UMTS_Route21 = 21,
+ UMTS_Route22 = 22,
+ UMTS_Route23 = 23,
+ UMTS_Route24 = 24,
+ UMTS_Routecount,
+ UMTS_RouteMax = 0xFF,
+} UMTS_Route;
+
+typedef struct
+{
+ kal_uint32 single_band_ca_list;
+ kal_uint32 dual_band_ca_list;
+} CA_RF_BAND_CAPABILITY_T;
+
+#if IS_3G_RX_POWER_OFFSET_SUPPORT
+typedef struct
+{
+ kal_bool RPO_enable;
+ kal_bool RPO_meta_enable;
+}U_sUl1dMetaRxPowerOffsetSetting;
+
+typedef struct
+{
+ kal_uint16 max_uarfcn;
+ kal_int16 pwr_offset_dB[2]; /*index0:Main, index1:Div*/
+} U_sSUBBAND_SECTION_RPO;
+
+typedef struct
+{
+ U_sSUBBAND_SECTION_RPO subband_power_offset[CAL_UARFCN_SECTION];
+} U_sRXPOWEROFFSETDATA;
+#endif
+
+
+#if (IS_3G_VPA_SEL_BY_BAND_SUPPORT)
+/* from mml1_rf_public.h
+#define VPA_SOURCE_NOT_SUPPORTED 0
+#define VPA_SOURCE_HW_VAPC 1
+#define VPA_SOURCE_HW_PMIC 2 //PMIC VPA1
+#define VPA_SOURCE_HW_ETM_SW_APT 3
+#define VPA_SOURCE_HW_ETM_SW_ET 4
+#define VPA_SOURCE_HW_PMIC2 5 //PMIC VPA2
+#define VPA_SOURCE_HW_V_BATTERY 6
+#define VPA_SOURCE_HW_EXT_VPA 7 // external VPA
+#define VPA_SOURCE_HW_PMIC1_ETM0 8
+*/
+
+typedef enum
+{
+ UMTS_VPA_SOURCE_INVALID = VPA_SOURCE_NOT_SUPPORTED,
+ UMTS_VPA_SOURCE_HW_VAPC = VPA_SOURCE_HW_VAPC,
+ UMTS_VPA_SOURCE_HW_PMIC = VPA_SOURCE_HW_PMIC,
+ UMTS_VPA_SOURCE_HW_ETM_0 = VPA_SOURCE_HW_ETM_0,
+ UMTS_VPA_SOURCE_HW_ETM_1 = VPA_SOURCE_HW_ETM_1,
+ UMTS_VPA_SOURCE_HW_PMIC2 = VPA_SOURCE_HW_PMIC2,
+ UMTS_VPA_SOURCE_HW_VBAT = VPA_SOURCE_HW_V_BATTERY,
+#if IS_3G_HPUE_SUPPORT
+ UMTS_VPA_SOURCE_HW_EXT_VPA = VPA_SOURCE_HW_EXT_VPA,
+#endif
+ UMTS_VPA_SOURCE_HW_PMIC1_ETM_0 = VPA_SOURCE_HW_PMIC1_ETM_0
+}
+UMTS_VPA_SOURCE_TYPE;
+
+typedef struct
+{
+ UMTS_VPA_SOURCE_TYPE vpaSel;
+}
+ul1vpa_sel_T;
+
+#endif/*IS_3G_VPA_SEL_BY_BAND_SUPPORT*/
+
+#if IS_3G_RFEQ_COEF_SUBBAND_SUPPORT
+#define RFEQ_SUBBAND_NUM 15
+#define RFEQ_ANT_NUM 2
+#define RFEQ_MAX_TAP_NUM 7
+
+typedef struct
+{
+ kal_uint16 max_uarfcn;
+ kal_bool rfeq_enable[RFEQ_ANT_NUM];
+ kal_bool rfeq_enable_sec_carrier[RFEQ_ANT_NUM];
+ kal_int16 rfeq_coef_real[RFEQ_ANT_NUM][RFEQ_MAX_TAP_NUM];
+ kal_int16 rfeq_coef_imag[RFEQ_ANT_NUM][RFEQ_MAX_TAP_NUM];
+} hs_dsch_rfeq_info_T;
+
+typedef struct
+{
+ hs_dsch_rfeq_info_T rfeq_coef_subband[RFEQ_SUBBAND_NUM]; //16 subband
+} hs_dsch_rfeq_info_band_T;
+#endif
+
+#if IS_3G_RFEQ_REAL_COEF_TEST
+#define REAL_RFEQ_SUBBAND_NUM 15
+#define REAL_RFEQ_ANT_NUM 2
+#define REAL_RFEQ_MAX_TAP_NUM 14
+
+#define COMPLEX_RFEQ_SUBBAND_NUM 15
+#define COMPLEX_RFEQ_ANT_NUM 2
+#define COMPLEX_RFEQ_MAX_TAP_NUM 7
+
+typedef struct
+{
+ kal_uint32 max_center_freq_100khz; /*100kHz, same to mipi setting*/
+ kal_bool real_rfeq_custom_enable[REAL_RFEQ_ANT_NUM];
+ kal_uint32 filter_taps[REAL_RFEQ_ANT_NUM][REAL_RFEQ_MAX_TAP_NUM];
+} URXDFE_REAL_RFEQ_CUSTOM_T;
+
+typedef struct
+{
+ kal_uint32 max_center_freq_100khz; /*100kHz, same to mipi setting*/
+ kal_bool complex_rfeq_custom_enable[COMPLEX_RFEQ_ANT_NUM];
+ kal_uint32 complex_coef_i[COMPLEX_RFEQ_ANT_NUM][COMPLEX_RFEQ_MAX_TAP_NUM];
+ kal_uint32 complex_coef_q[COMPLEX_RFEQ_ANT_NUM][COMPLEX_RFEQ_MAX_TAP_NUM];
+} URXDFE_COMPLEX_RFEQ_CUSTOM_T;
+
+typedef struct
+{
+ URXDFE_REAL_RFEQ_CUSTOM_T real_rfeq_band[REAL_RFEQ_SUBBAND_NUM];
+ URXDFE_COMPLEX_RFEQ_CUSTOM_T complex_rfeq_band[COMPLEX_RFEQ_SUBBAND_NUM];
+} URXDFE_REAL_RFEQ_CUSTOM_BAND_T;
+#endif
+
+/*******************************************************************************
+** RF Customization usage
+*******************************************************************************/
+
+/*******************************************************************************
+** Macros and constants
+*******************************************************************************/
+#if defined(__UMTS_R8__)
+ //For R8 project use internal definition.
+#else
+#define CAL_RX_ACT_DLY 5 //CAL_RX_ACT_DLY*64 samples = CAL_RX_ACT_DLY*38 chips
+#define CAL_RX_DC_LEN 4 //0~7, 1<<(4+CAL_RX_DC_LEN) samples = (1<<(4+CAL_RX_DC_LEN))*0.6 chips
+#define CAL_RX_DC_STL_TIME 30 //CAL_RX_DC_STL_TIME asmples = CAL_RX_DC_STL_TIME/2 chips
+#define CAL_RX_IQ_LEN 7 //0~8, 1<<(4+CAL_RX_IQ_LEN) samples = 1<<(3+CAL_RX_IQ_LEN) chips
+
+//Sample to Chip = Samples * (3.84MHz/6.5MHz=0.59077)
+#define CAL_RX_IDLE_IN_CHIP 1 //chips
+#define CAL_RX_ACT_DLY_IN_CHIP 190 //CAL_RX_ACT_DLY*(64)*0.59077 chips
+#define CAL_RX_DC_LEN_IN_CHIP 152 //(1<<(4+CAL_RX_DC_LEN))*0.59077 chips
+#define CAL_RX_DC_STL_TIME_IN_CHIP 18 //CAL_RX_DC_STL_TIME*0.59077 chips
+#define CAL_RX_IQ_LEN_IN_CHIP 1210 //(1<<(4+CAL_RX_IQ_LEN))*0.59077 chips
+
+#define RXCAL_TTG_DIS_GUARD_TIME 30 //Chips ~=7.8us
+#define RXCAL_MODE_CHANGE_GUARD_TIME 20 //Chips ~=5.2us
+#define RXCAL_TOTAL_TIME (CAL_RX_IDLE_IN_CHIP + CAL_RX_ACT_DLY_IN_CHIP + CAL_RX_DC_LEN_IN_CHIP + CAL_RX_DC_STL_TIME_IN_CHIP + CAL_RX_IQ_LEN_IN_CHIP + RXCAL_TTG_DIS_GUARD_TIME)
+#define RXCAL_EVENT_SHIFT_TIME0 (RXCAL_TOTAL_TIME+RXCAL_MODE_CHANGE_GUARD_TIME+RXCAL_TOTAL_TIME+TC_SR2B)
+#define RXCAL_EVENT_SHIFT_TIME1 (RXCAL_TOTAL_TIME+TC_SR2B)
+
+#define RXCAL_EVENT_SHIFT_TIME (RXCAL_TOTAL_TIME+RXCAL_MODE_CHANGE_GUARD_TIME+RXCAL_TOTAL_TIME+TC_SR2B)
+#endif //__UMTS_R8__
+
+#if 1//MT6293 format update
+#define U_PWRRES 32 // resolution 1/32, 0.03125 dB
+#define U_GAINLOSS( n ) ((kal_int16)((n)*U_PWRRES))
+#else
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#define UMTS_TABLE_END 0 // Use this value ater the end of UARFCN weight
+#define MICROSECOND_TO_CHIP(x) ((kal_int32)((x)*3.84))
+#define CHIP_TO_UCNT(x) ((kal_int32)((x)*81.25))
+
+#if !defined(UMTS_RF_TYPE)
+#define UMTS_RF_TYPE 2
+#endif
+
+#if defined(__UMTS_R8__)
+#define UMTS_RF_MAX_PA_SECTIONS (3)
+#define UMTS_RF_RX_START_TIMING_ARRAY_LENGTH (6)
+#define UMTS_RF_RX_END_TIMING_ARRAY_LENGTH (3)
+#define UMTS_RF_TX_START_TIMING_ARRAY_LENGTH (7)
+#define UMTS_RF_TX_END_TIMING_ARRAY_LENGTH (3)
+#define UMTS_RF_BPI_DATA_TABLE_NUM_OF_BANDS (11)
+#define UMTS_RF_BPI_DATA_TABLE_NUM_OF_WINDOWS (2)
+#define UMTS_RF_BPI_DATA_TABLE_NUM_OF_EVENTS (5)
+#define UMTS_RF_BPI_DATA2_TABLE_NUM_OF_EVENTS (5)
+#else
+#define UMTS_RF_MAX_PA_SECTIONS (3)
+#define UMTS_RF_RX_START_TIMING_ARRAY_LENGTH (6)
+#define UMTS_RF_RX_END_TIMING_ARRAY_LENGTH (3)
+#define UMTS_RF_TX_START_TIMING_ARRAY_LENGTH (8)
+#define UMTS_RF_TX_END_TIMING_ARRAY_LENGTH (5)
+#define UMTS_RF_BPI_DATA_TABLE_NUM_OF_BANDS (11)
+#define UMTS_RF_BPI_DATA_TABLE_NUM_OF_WINDOWS (2)
+#define UMTS_RF_BPI_DATA_TABLE_NUM_OF_EVENTS (5)
+#endif
+
+/*******************************************************************************
+** Typedefs
+*******************************************************************************/
+typedef struct
+{
+ kal_uint16 maxOffset;
+ kal_uint16 vmOffset;
+ kal_uint16 vbiasOffset;
+ kal_uint16 dc2dcOffset;
+ kal_uint16 vgaOffset;
+}U_sUl1dRfPaControlTiming;
+
+typedef struct
+{
+ /* RX window start timing */
+ kal_int16 xTC_PR1;
+ kal_int16 xTC_PR2;
+ kal_int16 xTC_PR2B;
+
+ /* RX window end timing */
+ kal_int16 xTC_PR3;
+ kal_int16 xTC_PR3A;
+
+ /* TX window start timing */
+ kal_int16 xTC_PT1;
+ kal_int16 xTC_PT2;
+ kal_int16 xTC_PT2B;
+
+ /* TX window end timing */
+ kal_int16 xTC_PT3;
+ kal_int16 xTC_PT3A;
+}U_sUl1dRfBsiBpiTiming;
+
+typedef struct
+{
+ UL1_RF_RX_IO_E rxio;
+ UL1_RF_RXD_IO_E rxdio;
+}UMTS_RX_IODATA_T;
+
+typedef struct
+{
+ BPI_data_type pr1;
+ BPI_data_type pr2;
+ BPI_data_type pr2b;
+ BPI_data_type pr3;
+ BPI_data_type pr3a;
+}UMTS_RX_PDATA_T;
+
+typedef struct
+{
+ UL1_RF_TX_IO_E txio;
+ UL1_RF_TX_DET_IO_E txdetio;
+}UMTS_TX_IODATA_T;
+
+typedef struct
+{
+ BPI_data_type pt1;
+ BPI_data_type pt2;
+ BPI_data_type pt2b;
+ BPI_data_type pt3;
+ BPI_data_type pt3a;
+}UMTS_TX_PDATA_T;
+
+typedef struct
+{
+ UMTSBand bandIdx;
+ UMTS_RX_PDATA_T rxPdata;
+ #if IS_3G_RXD_FE_CONTROL_SUPPORT
+ UMTS_RX_PDATA_T rxPdata2;
+ #endif
+}UMTS_RX_PDATABASE_T;
+
+typedef struct
+{
+ UMTSBand bandIdx;
+ UMTS_TX_PDATA_T txPdata;
+}UMTS_TX_PDATABASE_T;
+
+typedef struct
+{
+ UMTSBand bandIdx;
+ UMTS_RX_IODATA_T rxIodata;
+}UMTS_RXIOBASE_T;
+
+typedef struct
+{
+ UMTSBand bandIdx;
+ UMTS_TX_IODATA_T txIodata;
+}UMTS_TXIOBASE_T;
+
+typedef struct
+{
+ UMTS_RX_PDATABASE_T rxBpi[UMTS_FE_RXBASE_TBL_SIZE_MAX];
+ UMTS_TX_PDATABASE_T txBpi[UMTS_FE_TXBASE_TBL_SIZE_MAX];
+}U_sUl1dRfBpiData;
+
+#if IS_3G_GEN97_TAS_SUPPORT || IS_3G_GEN97_DAT_SUPPORT
+typedef struct
+{
+ MMRFD_ANT_FE_SWITCH_DATA_T ant_switch_setting;
+ MMRFD_ANT_FE_TUNER_DATA_T ant_tuner_setting;
+}UMTS_RF_ANT_FE_SETTING_T;
+
+typedef struct
+{
+ MMRFD_ANT_HW_SETTING_VALID_T *ant_config_valid[MMRFD_ANT_DIE_NUM];
+ MMRFD_CUSTOM_ANT_BPI_SETTING_T *ant_bpi_setting[MMRFD_ANT_DIE_NUM];
+ MMRFD_ANT_FE_MIPI_CONFIG_TBL_T **ant_mipi_config;
+ kal_int32 utime;
+}UMTS_RF_ANT_NODE_CALC_INPUT_T;
+#endif
+
+typedef enum
+{
+ UL1_ANTENNA_0, /* Main antenna */
+ UL1_ANTENNA_1, /* Diversity antenna */
+ UL1_ANTENNA_2, /* Auxiliary antenna */
+ #if IS_3G_UTAS_SUPPORT
+ UL1_ANTENNA_3,
+ UL1_ANTENNA_4,
+ UL1_ANTENNA_5,
+ UL1_ANTENNA_6,
+ UL1_ANTENNA_7,
+ UL1_ANTENNA_8,
+ UL1_ANTENNA_9,
+ UL1_ANTENNA_10,
+ UL1_ANTENNA_11,
+ #endif
+ UL1_ANTENNA_NUM
+}
+ul1_antenna_idx_E;
+
+#if IS_3G_TAS_SUPPORT
+typedef struct
+{
+ /* Band 1 TAS BPI data */
+ BPI_data_type xPDATA_BAND1_TAS1;
+ BPI_data_type xPDATA_BAND1_TAS2;
+ BPI_data_type xPDATA_BAND1_TAS3;
+
+ /* Band 2 TAS BPI data */
+ BPI_data_type xPDATA_BAND2_TAS1;
+ BPI_data_type xPDATA_BAND2_TAS2;
+ BPI_data_type xPDATA_BAND2_TAS3;
+
+ /* Band 3 TAS BPI data */
+ BPI_data_type xPDATA_BAND3_TAS1;
+ BPI_data_type xPDATA_BAND3_TAS2;
+ BPI_data_type xPDATA_BAND3_TAS3;
+
+ /* Band 4 TAS BPI data */
+ BPI_data_type xPDATA_BAND4_TAS1;
+ BPI_data_type xPDATA_BAND4_TAS2;
+ BPI_data_type xPDATA_BAND4_TAS3;
+
+ /* Band 5 TAS BPI data */
+ BPI_data_type xPDATA_BAND5_TAS1;
+ BPI_data_type xPDATA_BAND5_TAS2;
+ BPI_data_type xPDATA_BAND5_TAS3;
+
+ /* Band 6 TAS BPI data */
+ BPI_data_type xPDATA_BAND6_TAS1;
+ BPI_data_type xPDATA_BAND6_TAS2;
+ BPI_data_type xPDATA_BAND6_TAS3;
+
+ /* Band 7 TAS BPI data */
+ BPI_data_type xPDATA_BAND7_TAS1;
+ BPI_data_type xPDATA_BAND7_TAS2;
+ BPI_data_type xPDATA_BAND7_TAS3;
+
+ /* Band 8 TAS BPI data */
+ BPI_data_type xPDATA_BAND8_TAS1;
+ BPI_data_type xPDATA_BAND8_TAS2;
+ BPI_data_type xPDATA_BAND8_TAS3;
+
+ /* Band 9 TAS BPI data */
+ BPI_data_type xPDATA_BAND9_TAS1;
+ BPI_data_type xPDATA_BAND9_TAS2;
+ BPI_data_type xPDATA_BAND9_TAS3;
+
+ /* Band 10 TAS BPI data */
+ BPI_data_type xPDATA_BAND10_TAS1;
+ BPI_data_type xPDATA_BAND10_TAS2;
+ BPI_data_type xPDATA_BAND10_TAS3;
+
+ /* Band 11 TAS BPI data */
+ BPI_data_type xPDATA_BAND11_TAS1;
+ BPI_data_type xPDATA_BAND11_TAS2;
+ BPI_data_type xPDATA_BAND11_TAS3;
+
+ /* Band 19 TAS BPI data */
+ BPI_data_type xPDATA_BAND19_TAS1;
+ BPI_data_type xPDATA_BAND19_TAS2;
+ BPI_data_type xPDATA_BAND19_TAS3;
+}U_sUl1dRfTasBpiData;
+
+typedef struct
+{
+ BPI_data_type umtsTasMask;
+ U_sUl1dRfTasBpiData umtsTasPdata;
+}U_sUl1dRfTasData;
+
+typedef enum
+{
+ TAS_TYPE_0, /* TAS Disable */
+ TAS_TYPE_1, /* TAS with Rx Diversity support */
+ TAS_TYPE_2, /* TAS WITHOUT Rx Diversity support */
+} ul1_tas_type_E;
+
+typedef enum
+{
+ BY_BAND_TAS_TYPE_0 = TAS_TYPE_0,/* TAS Disable */
+ BY_BAND_TAS_TYPE_1 = TAS_TYPE_1,/* TAS with Rx Diversity support */
+ BY_BAND_TAS_TYPE_2 = TAS_TYPE_2,/* TAS WITHOUT Rx Diversity support */
+ BY_BAND_TAS_TYPE_Default /* Set TAS type as tas_default_type for each band */
+} ul1_tas_type_by_band_E;
+
+typedef struct
+{
+ kal_int16 rscp_diff_thd_po; /* RSCP difference threshold */
+ kal_int16 rscp_diff_thd_cb; /* Diversity to main RSCP difference threshold J2 (RSCP CB) */
+ kal_int16 rscp_diff_thd_txp; /* Diversity to main RSCP difference threshold J3 (TXP) */
+ kal_int16 rscp_cb_thd; /* RSCP drop threshold */
+ kal_int8 txp_cb_thd; /* Transmit power increase threshold during check-back */
+ kal_uint8 n_ms_cb; /* Check-back period for RSCP, TXP (in measurement slots, MS) */
+ kal_int8 u_htp; /* High transmit power offset */
+ kal_uint8 htp_thd; /* High transmit power ratio threshold (in percentage, %) */
+ kal_int8 tpc_inc_thd; /* Transmit power increase threshold */
+ kal_uint8 n_ms_sb; /* Monitoring duration for switch-back check (in measurement slots, MS) */
+ kal_int16 rscp_inc_thd; /* Increase received power threshold after CAS performed */
+ kal_int16 rscp_sda_thd; /* The increased amount for RSCP check-back threshold duer to user sda */
+ kal_int8 txp_sda_thd; /* The increased amount for TXP check-back threshold duer to user sda */
+ kal_int16 rscp_periodic_cb_thd; /* RSCP threshold for counting the active timer under worse channel */
+} UMTS_TAS_Type1_Params_T;
+
+typedef struct
+{
+ //kal_uint16 t_thd1_j; /* Periodic check timer threshold (in frames) */
+ kal_int16 rscp_abs_thd_cb; /* RSCP abs cb threshold */
+ kal_int16 rscp_abs_thd_txp; /* RSCP abs txp threshold */
+ kal_int16 rscp_cb_thd; /* RSCP drop threshold */
+ kal_int8 txp_cb_thd; /* Transmit power increase threshold during check-back */
+ kal_uint8 n_ms_cb; /* Check-back period for RSCP, TXP (in measurement slots, MS) */
+ kal_int8 u_htp; /* High transmit power offset */
+ kal_uint8 htp_thd; /* High transmit power ratio threshold (in percentage, %) */
+ kal_int16 rscp_inc_thd; /* RSCP inc threshold for dedicated mode */
+ kal_int8 tpc_inc_thd; /* Transmit power increase threshold */
+ kal_uint8 n_ms_sb; /* Monitoring duration for switch-back check (in measurement slots, MS) */
+ kal_int16 rscp_thd_idle; /* RSCP threshold for IDLE mode */
+ kal_int16 rscp_inc_thd_idle; /* RSCP inc threshold for IDLE mode */
+ kal_int16 ecno_thd; /* EcNo threshold */
+} UMTS_TAS_Type2_Params_T;
+
+typedef struct {
+ ul1_tas_type_by_band_E xBand1_TAS_TYPE;
+ ul1_tas_type_by_band_E xBand2_TAS_TYPE;
+ ul1_tas_type_by_band_E xBand3_TAS_TYPE;
+ ul1_tas_type_by_band_E xBand4_TAS_TYPE;
+ ul1_tas_type_by_band_E xBand5_TAS_TYPE;
+ ul1_tas_type_by_band_E xBand6_TAS_TYPE;
+ ul1_tas_type_by_band_E xBand8_TAS_TYPE;
+ ul1_tas_type_by_band_E xBand9_TAS_TYPE;
+ ul1_tas_type_by_band_E xBand10_TAS_TYPE;
+ ul1_tas_type_by_band_E xBand11_TAS_TYPE;
+ ul1_tas_type_by_band_E xBand19_TAS_TYPE;
+} UMTS_TAS_Type_By_Band_T;
+
+typedef struct
+{
+ kal_bool umts_tas_enable;
+ kal_bool umts_tas_support_on_test_sim;
+ ul1_antenna_idx_E umts_tas_default_main_antenna;
+ ul1_tas_type_E umts_tas_default_type;
+ UMTS_TAS_Type_By_Band_T umts_tas_type_by_band;
+#if IS_3G_FORCE_TX_ANT_SUPPORT
+ kal_bool umts_tas_force_tx_ant_enable;
+ ul1_antenna_idx_E umts_tas_force_tx_ant_index;
+#endif/* IS_3G_FORCE_TX_ANT_SUPPORT */
+} UMTS_TAS_Configuration_T;
+
+#if IS_3G_TAS_UL1_CUSTOM_SUPPORT
+typedef struct
+{
+ kal_uint16 TASEna;
+ kal_uint16 TASWithTestSimEna;
+ kal_uint32 TASMask; //0~31
+ kal_uint16 TASInitAnt;
+ kal_uint16 ForceAntEna;
+ kal_uint16 ForceAntIndex;
+ UMTSBand TASBand[UMTS_RF_TAS_BAND_NUM];
+}UMTS_RF_TAS_BAND_IND_T;
+
+//TAS feature
+typedef struct
+{
+ kal_int16 ENB_SM; // Enable of antenna-switch metric function
+ kal_int16 N_MS_j_hys; // MS, Hysteresis duration control for leaving normal state
+ kal_int16 N_MS_SM_fadeout; // MS, The timer duration for antenna-switching metric fadeout protection
+ kal_int16 PHI_bound; // dB, Up/low bound for applying antenna-switching metric as threshold
+ kal_int16 PHI_01_default; // dB, Antenna-switching metric default value from ant. 0 to ant. 1
+ kal_int16 PHI_10_default; // dB, Antenna-switching metric default value from ant. 1 to ant. 0
+ kal_int16 ENB_DB; // Enable of dynamic barrier control function
+ kal_int16 DELTA_DB_fail_step_RSRP; // dB, The increased amount for RSRP barrier for a fail pre-switch
+ kal_int16 DELTA_DB_fail_step_TXP; // dB, The increased amount for TX power barrier for a fail pre-switch
+ kal_int16 N_MS_DB_relax; // MS, The timer duration to relax the dynamic barrier
+ kal_int16 DELTA_DB_TO_step; // dB, RSRP/TXP: The decreased barrier when per timer is reached
+ kal_int16 DELTA_DB_bound_RSRP; // dB, The upper bound of the extra-threshold Delta_RSRP_DB
+ kal_int16 DELTA_DB_bound_TXP; // dB, The upper bound of the extra-threshold Delta_TXP_DB
+ // Naming for customer, Naming for MTK internal, Unit, Description
+ kal_int16 RSRP_diff_thd; //RSRP_diff_thd_PO, dB, RSRP difference threshold to trigger TAS, defined as the RSRP value difference from diversity to main antennas
+ kal_int16 RSRP_diff_thd_TXP;
+ kal_int16 RSRP_diff_thd_CB;
+ kal_int16 RSRP_thd_connect_EN; // RSRP_diff_thd_xxx are connected or not
+ kal_int16 RSRP_cb_drop_thd; // RSRP_CB_thd, dB, RSRP drop threshold to trigger TAS when check back, defined as the RSRP value difference from current value to its previous one
+ kal_int16 TXP_cb_inc_thd; // TXP_CB_thd, dB, Transmit power (TXP) increase threshold to trigger TAS when check back, defined as the TXP value difference from current value to its previous one
+ kal_int16 nMS_cb; // N_MS_CB, MS, The look/check back period (for RSRP and TXP change monitoring), using measurement slot (MS) as the unit
+ kal_int16 HTP_level; // M_THP, dB, The high transmit power (HTP) level, defined as the ratio (in dB) to UE's maximum transmit power
+ kal_int16 HTP_ratio_thd; // HTP_thd, %, A HTP is recognized when the percentage using TXP (within a measurement slot) greater than HTP_level is higher than the ratio threshold
+ kal_int16 TXP_inc_thd_sb; // TPC_inc_thd1, dB, TXP increase threshold when switch to the diversity antenna, for which exceeding the threshold would be recognized as a fail antenna switch
+ kal_int16 nMS_sb; // N_MS_SB, MS, The monitoring duration for switch-back check, using measurement slot (MS) as the unit
+
+}UMTS_RF_TAS_OTHER;
+
+typedef struct
+{
+ UMTS_RF_TAS_BAND_IND_T TASBandInd;
+ kal_uint32 TASRfDatabase[UMTS_RF_TAS_TOTAL_NUM];
+}UMTS_RF_TAS_PARAMETER;
+
+typedef enum
+{
+ UMTS_TAS_VER_1_0 = 0,
+ UMTS_TAS_VER_1_5 = 1,
+ UMTS_TAS_VER_2_0 = 2,
+ UMTS_MAX_TAS_VER_NUM,
+}UMTS_CUSTOM_TAS_VER_E;
+
+typedef enum
+{
+ UMTS_TAS_ANT_NA = 0,
+ UMTS_TAS_ANT1 = 1,
+ UMTS_TAS_ANT2 = 2,
+ UMTS_TAS_ANT3 = 3,
+ UMTS_TAS_ANT4 = 4,
+ UMTS_MAX_TAS_ANT_NUM,
+}UMTS_CUSTOM_TAS_ANT_E;
+
+typedef enum
+{
+ UMTS_TAS_DPDT_NA = 0,
+ UMTS_TAS_DPDT1 = 1,
+ UMTS_TAS_DPDT2 = 2,
+ UMTS_MAX_TAS_DPDT_NUM,
+}UMTS_CUSTOM_TAS_DPDT_E;
+
+typedef enum
+{
+ UMTS_TAS_MIPI_TABLE_ROUTE0,
+ UMTS_TAS_MIPI_TABLE_ROUTE1,
+ UMTS_TAS_MIPI_TABLE_ROUTE2,
+ UMTS_TAS_MIPI_TABLE_ROUTE3,
+ UMTS_TAS_MIPI_TABLE_ROUTE4,
+ UMTS_TAS_MIPI_TABLE_ROUTE5,
+ UMTS_TAS_MIPI_TABLE_ROUTE6,
+ UMTS_TAS_MIPI_TABLE_ROUTE7,
+ UMTS_TAS_MIPI_TABLE_ROUTE8,
+ UMTS_TAS_MIPI_TABLE_ROUTE9,
+ UMTS_TAS_MIPI_TABLE_NULL,
+}UMTS_CUSTOM_TAS_MIPI_TBL_IDX_E;
+
+typedef enum
+{
+ UMTS_TAS_FE_ROUTE0,
+ UMTS_TAS_FE_ROUTE1,
+ UMTS_TAS_FE_ROUTE2,
+ UMTS_TAS_FE_ROUTE3,
+ UMTS_TAS_FE_ROUTE4,
+ UMTS_TAS_FE_ROUTE5,
+ UMTS_TAS_FE_ROUTE6,
+ UMTS_TAS_FE_ROUTE7,
+ UMTS_TAS_FE_ROUTE8,
+ UMTS_TAS_FE_ROUTE9,
+ UMTS_TAS_FE_NULL,
+}UMTS_CUSTOM_TAS_FE_ROUTE_IDX_E;
+
+typedef enum
+{
+ UMTS_TAS_DISABLE,
+ UMTS_TAS_ENABLE,
+}UMTS_CUSTOM_TAS_SWITCH_E;
+
+#if IS_3G_UTAS_SUPPORT
+typedef enum
+{
+ UMTS_TAS_STATE0 = MMRFD_TAS_STATE0,
+ UMTS_TAS_STATE1,
+ UMTS_TAS_STATE2,
+ UMTS_TAS_STATE3,
+ UMTS_TAS_STATE4,
+ UMTS_TAS_STATE5,
+ UMTS_TAS_STATE6,
+ UMTS_TAS_STATE7,
+ UMTS_TAS_STATE8,
+ UMTS_TAS_STATE9,
+ UMTS_TAS_STATE10,
+ UMTS_TAS_STATE11,
+ UMTS_TAS_STATE12,
+ UMTS_TAS_STATE13,
+ UMTS_TAS_STATE14,
+ UMTS_TAS_STATE15,
+ UMTS_TAS_STATE16,
+ UMTS_TAS_STATE17,
+ UMTS_TAS_STATE18,
+ UMTS_TAS_STATE19,
+ UMTS_TAS_STATE20,
+ UMTS_TAS_STATE21,
+ UMTS_TAS_STATE22,
+ UMTS_TAS_STATE23,
+ UMTS_TAS_STATE_NUM = MMRFD_TAS_STATE_NUM, //24
+ UMTS_TAS_STATE_NULL = MMRFD_ANT_INVALID_PATTERN
+}UMTS_CUSTOM_TAS_STATE_E;
+#else
+typedef enum
+{
+ UMTS_TAS_STATE0,
+ UMTS_TAS_STATE1,
+ UMTS_TAS_STATE2,
+ UMTS_TAS_STATE3,
+ UMTS_TAS_STATE4,
+ UMTS_TAS_STATE5,
+ UMTS_TAS_STATE6,
+ UMTS_TAS_STATE7,
+ UMTS_TAS_STATE_NULL,
+}UMTS_CUSTOM_TAS_STATE_E;
+#endif
+
+#if IS_3G_TAS_INHERIT_4G_ANT
+typedef struct
+{
+ LTE_Band inherit_lte_band;
+}UMTS_CUSTOM_TAS_INHERIT_LTE_BAND_T;
+
+typedef struct
+{
+ kal_uint32 inherit_lte_band_bitmap[UMTS_TAS_INHERIT_LTE_BAND_BITMAP_NUM];
+}UMTS_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_T;
+
+typedef struct
+{
+ UMTS_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_T inherit_lte_band_bitmap_route[UMTS_TAS_MAX_FE_ROUTE_NUM];
+}UMTS_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T;
+#endif
+
+typedef struct
+{
+ UMTS_CUSTOM_TAS_SWITCH_E tas_enable;
+ UMTS_CUSTOM_TAS_STATE_E tas_state;
+}UMTS_CUSTOM_TAS_FEATURE_OPTION_T;
+
+typedef struct
+{
+ kal_uint32 cat_a_route_num;
+ kal_uint32 cat_b_route_num;
+ kal_uint32 cat_c_route_num;
+}UMTS_CUSTOM_TAS_FE_ROUTE_MAP_T;
+
+#if IS_3G_UTAS_SUPPORT
+typedef struct
+{
+ UMTS_CUSTOM_TAS_FEATURE_OPTION_T force_mode_tas_feature;
+ UMTS_CUSTOM_TAS_STATE_E tas_ics_init_ant_state;
+ UMTS_CUSTOM_TAS_SWITCH_E tas_enable_on_real_sim;
+ UMTS_CUSTOM_TAS_SWITCH_E tas_enable_on_test_sim;
+}UMTS_CUSTOM_TAS_FEATURE_BY_RAT_T;
+#else
+typedef struct
+{
+ UMTS_CUSTOM_TAS_VER_E tas_version;
+ UMTS_CUSTOM_TAS_FEATURE_OPTION_T force_mode_tas_feature;
+ UMTS_CUSTOM_TAS_STATE_E tas_ics_init_ant_state;
+ UMTS_CUSTOM_TAS_SWITCH_E tas_enable_on_real_sim;
+ UMTS_CUSTOM_TAS_SWITCH_E tas_enable_on_test_sim;
+}UMTS_CUSTOM_TAS_FEATURE_BY_RAT_T;
+#endif
+
+typedef struct
+{
+ UMTS_CUSTOM_TAS_FEATURE_OPTION_T real_sim_tas_feature;
+ UMTS_CUSTOM_TAS_FEATURE_OPTION_T test_sim_tas_feature;
+}UMTS_CUSTOM_TAS_FEATURE_ENABLE_T;
+
+
+#if IS_3G_UTAS_SUPPORT
+typedef enum
+{
+ UMTS_TAS_LAYOUT_GROUP_INDEX0 = 0,
+ UMTS_TAS_LAYOUT_GROUP_INDEX1,
+ UMTS_TAS_LAYOUT_GROUP_INDEX2,
+ UMTS_TAS_LAYOUT_GROUP_INDEX3,
+ UMTS_TAS_LAYOUT_GROUP_INDEX4,
+ UMTS_TAS_LAYOUT_GROUP_INDEX5,
+ UMTS_TAS_LAYOUT_GROUP_INDEX6,
+ UMTS_TAS_LAYOUT_GROUP_INDEX7,
+ UMTS_TAS_LAYOUT_GROUP_INDEX8,
+ UMTS_TAS_LAYOUT_GROUP_INDEX9,
+ UMTS_TAS_LAYOUT_GROUP_NUM = MMRFD_TAS_MAX_HW_GROUP_NUM, //10
+ UMTS_TAS_LAYOUT_GROUP_NULL = MMRFD_ANT_INVALID_PATTERN
+}UMTS_RF_UTAS_LAYOUT_GROUP_INDEX_E;
+
+#if IS_3G_GEN97_TAS_SUPPORT
+typedef struct
+{
+ UMTSBand usage;
+ UMTS_CUSTOM_TAS_FEATURE_ENABLE_T tas_feature_enable;
+ UMTS_CUSTOM_TAS_STATE_E tas_cal_init_state;
+ kal_int8 rscp_bias[UL1_ANTENNA_NUM];
+}UMTS_CUSTOM_SPLIT_TAS_SETTING_T;
+
+typedef struct
+{
+ UMTSBand usage;
+ UMTS_CUSTOM_TAS_STATE_E tas_cal_init_state;
+ kal_int8 rscp_bias[UL1_ANTENNA_NUM];
+}UMTS_CUSTOM_SPLIT_TAS_SETTING_DATA_T;
+
+typedef struct
+{
+ UMTS_CUSTOM_SPLIT_TAS_SETTING_DATA_T UMTS_tas_fe_route_db[UMTS_TAS_MAX_FE_ROUTE_NUM];
+}UMTS_CUSTOM_TAS_FE_ROUTE_DATA_T;
+
+
+#else /*Gen95*/
+typedef struct
+{
+ kal_uint16 mipi_subband_freq;
+ MMRFD_ANT_TUNER_CONFIG_SETTING_IDX_E tuner_control_setting_idx;
+}UMTS_CUSTOM_SPLIT_ANT_FE_T;
+
+typedef struct
+{
+ kal_uint8 tas_split_band_num;
+ UMTS_CUSTOM_SPLIT_ANT_FE_T split_ant_setting[UMTS_RF_UTAS_MAX_SPLIT_BAND_NUM];
+}UMTS_CUSTOM_SPLIT_PART_SETTING_T;
+
+typedef struct
+{
+ UMTSBand usage;
+ UMTS_CUSTOM_TAS_FEATURE_ENABLE_T tas_feature_enable;
+ UMTS_CUSTOM_TAS_STATE_E tas_cal_init_state;
+ UMTS_RF_UTAS_LAYOUT_GROUP_INDEX_E tas_ant_layout_group;
+ kal_int8 rscp_bias[UL1_ANTENNA_NUM];
+ UMTS_CUSTOM_SPLIT_PART_SETTING_T tas_split_part_setting;
+}UMTS_CUSTOM_SPLIT_TAS_SETTING_T;
+#endif
+
+#else /*IS_3G_UTAS_SUPPORT*/
+typedef struct
+{
+ UMTSBand usage;
+ kal_uint32 tas_state_num;
+ UMTS_CUSTOM_TAS_FEATURE_ENABLE_T tas_feature_enable;
+ UMTS_CUSTOM_TAS_FE_ROUTE_MAP_T tas_fe_setting[UMTS_TAS_MAX_STATE_NUM];
+}UMTS_CUSTOM_SPLIT_TAS_SETTING_T;
+#endif
+
+typedef struct
+{
+ kal_bool is_tas_real_sim_en;
+ kal_bool is_tas_test_sim_en;
+}UMTS_CUSTOM_TAS_SIM_EN_T;
+
+typedef struct
+{
+ UMTS_CUSTOM_SPLIT_TAS_SETTING_T UMTS_tas_fe_route_db[UMTS_TAS_MAX_FE_ROUTE_NUM];
+}UMTS_CUSTOM_TAS_FE_ROUTE_DATABASE_T;
+
+typedef struct
+{
+ kal_uint32 bpi_mask;
+ kal_uint32 bpi_value;
+ UMTS_CUSTOM_TAS_MIPI_TBL_IDX_E tas_mipi_table_index;
+}UMTS_CUSTOM_TAS_FE_SETTING_T;
+
+typedef struct
+{
+ UMTS_CUSTOM_TAS_FE_SETTING_T tas_cat_a_fe_route[UMTS_TAS_MAX_CAT_A_ROUTE_NUM];
+}UMTS_CUSTOM_TAS_FE_CAT_A_T;
+
+typedef struct
+{
+ UMTS_CUSTOM_TAS_FE_SETTING_T tas_cat_b_fe_route[UMTS_TAS_MAX_CAT_B_ROUTE_NUM];
+}UMTS_CUSTOM_TAS_FE_CAT_B_T;
+
+typedef struct
+{
+ UMTS_CUSTOM_TAS_FE_SETTING_T tas_cat_c_fe_route[UMTS_TAS_MAX_CAT_C_ROUTE_NUM];
+}UMTS_CUSTOM_TAS_FE_CAT_C_T;
+
+typedef struct
+{
+ UMTS_CUSTOM_TAS_FE_CAT_A_T tas_cat_a_fe_db;
+ UMTS_CUSTOM_TAS_FE_CAT_B_T tas_cat_b_fe_db;
+ UMTS_CUSTOM_TAS_FE_CAT_C_T tas_cat_c_fe_db;
+}UMTS_CUSTOM_TAS_FE_DATABASE_T;
+
+#endif
+
+#if IS_3G_TAS_TST_SUPPORT
+typedef enum
+{
+ UMTS_TAS_VER_1_0_STATE_MAX = 2, // only DPDT swap for non UL-CA case
+ UMTS_TAS_VER_1_5_STATE_MAX = 4, // only DPDT swap(take dual DPDT into consideration for UL-CA case)
+ UMTS_TAS_VER_2_0_STATE_MAX = 4, // DPDT swap and M/M' swap for non UL-CA case
+ UMTS_TAS_VER_2_5_STATE_MAX = 8, // DPDT swap and M/M' swap for UL-CA case
+}UMTS_CUSTOM_TAS_STATE_MAX_E;
+
+typedef enum
+{
+ UMTS_TAS_TST_DISABLE,
+ UMTS_TAS_TST_ENABLE,
+}UMTS_CUSTOM_TAS_ST_SWITCH_E;
+
+#if IS_3G_UTAS_SUPPORT
+typedef struct
+{
+ UMTSBand usage;
+ UMTS_CUSTOM_TAS_ST_SWITCH_E tas_tst_enable_by_route;
+ UMTS_CUSTOM_TAS_ST_SWITCH_E tas_tst_state_status[UMTS_TAS_STATE_NUM];
+}UMTS_CUSTOM_SPLIT_TAS_TST_SETTING_T;
+
+#else
+typedef struct
+{
+ UMTSBand usage;
+ UMTS_CUSTOM_TAS_ST_SWITCH_E tas_tst_enable_by_route;
+ kal_uint16 tas_tst_state_status;
+}UMTS_CUSTOM_SPLIT_TAS_TST_SETTING_T;
+#endif/*IS_3G_UTAS_SUPPORT*/
+
+typedef struct
+{
+ UMTS_CUSTOM_TAS_ST_SWITCH_E tas_tst_enable;
+ UMTS_CUSTOM_SPLIT_TAS_TST_SETTING_T UMTS_tas_tst_fe_route_db[UMTS_TAS_MAX_FE_ROUTE_NUM];
+}UMTS_CUSTOM_TAS_TST_FE_ROUTE_DATABASE_T;
+#endif/*IS_3G_TAS_TST_SUPPORT*/
+#endif/*IS_3G_TAS_SUPPORT*/
+
+#if IS_3G_UTAS_SUPPORT
+
+#if IS_3G_GEN97_TAS_SUPPORT
+typedef struct
+{
+ const kal_uint32 *schemeTable_p; //Ant scheme table start address
+ kal_uint8 antStateNum; //number of state in scheme table
+}UMTS_RF_UTAS_SCHEME_INFO_T;
+
+typedef struct
+{
+ kal_uint8 rxPathValidCnt; //number of RX path.
+ MMRFD_ANT_PORT_E rxPathMap[UMTS_RF_UTAS_RF_PATH_NUM]; //mapping between RX path and ANT_port. [0]:ANT_Port of PRX. [1]:ANT_Port of DRX1.
+ MMRFD_ANT_PORT_E txPathMap; //mapping between TX path and ANT_port. ANT_Port of TX.
+ kal_uint16 antCapability; //bit_0: ANT_0, bit_1: ANT_1, bit_2: ANT_2, bit_3: ANT_3. 1=this ANT can be use for serving band.
+}UMTS_RF_UTAS_RF_PATH_MAP_T;
+
+#else
+typedef struct
+{
+ kal_uint16 *schemeTable_p; //Ant scheme table start address
+ kal_uint8 antStateNum; //number of state in scheme table
+ MMRFD_ANT_INDEX_TYPE_E co_structure_type; //Co-structure antenna identification
+}UMTS_RF_UTAS_SCHEME_INFO_T;
+
+typedef struct
+{
+ kal_uint8 rxPathValidCnt; //number of RX path.
+ MMRFD_ANT_PORT_E rxPathMap[UMTS_RF_UTAS_RF_PATH_NUM]; //mapping between RX path and ANT_port. [0]:ANT_Port of PRX. [1]:ANT_Port of DRX1.
+ MMRFD_ANT_PORT_E txPathMap; //mapping between TX path and ANT_port. ANT_Port of TX.
+ kal_uint8 antCapability; //bit_0: ANT_0, bit_1: ANT_1, bit_2: ANT_2, bit_3: ANT_3. 1=this ANT can be use for serving band.
+}UMTS_RF_UTAS_RF_PATH_MAP_T;
+#endif
+
+typedef struct
+{
+ UMTS_RF_UTAS_SCHEME_INFO_T schemeTable; //Antenna scheme table
+ UMTS_RF_UTAS_RF_PATH_MAP_T rfPathMap; //RF path mapping
+}UMTS_RF_UTAS_ANT_HW_STRUCTURE_T;
+
+typedef struct
+{
+ kal_bool rat_enable;
+ kal_bool band_enable;
+ UMTS_CUSTOM_TAS_STATE_E init_state;
+}UMTS_RF_UTAS_SIM_CONTROL_T;
+
+typedef struct
+{
+ kal_bool force_tas_enable;
+ UMTS_CUSTOM_TAS_STATE_E force_tas_state;
+}UMTS_RF_UTAS_FORCE_TAS_CONTROL_T;
+
+typedef struct
+{
+ UMTS_RF_UTAS_SIM_CONTROL_T test_sim_parameter;
+ UMTS_RF_UTAS_SIM_CONTROL_T real_sim_parameter;
+ UMTS_RF_UTAS_FORCE_TAS_CONTROL_T force_tas_parameter;
+}UMTS_RF_UTAS_CONTROL_PARAMETER_T;
+
+typedef struct
+{
+ UMTS_RF_UTAS_ANT_HW_STRUCTURE_T antHwStruct;
+ UMTS_RF_UTAS_CONTROL_PARAMETER_T controlParameter;
+}UMTS_RF_UTAS_CUSTOM_INFO_T;
+#endif
+
+
+#if (IS_3G_TX_POWER_OFFSET_SUPPORT || IS_3G_SAR_TX_POWER_BACKOFF_SUPPORT || IS_3G_TX_NSFT_POWER_OFFSET_SUPPORT)
+typedef struct
+{
+ kal_uint16 max_uarfcn;
+ kal_int16 pwr_offset_dB[UL1_ANTENNA_NUM][3]; /* [Ant Dimension][Mode 0/1/2 R99/HSDPA/HSUPA] ; unit: 1/8 dB, range: -8 ~ +7 dB */
+} U_sSUBBAND_SECTION;
+#endif
+
+#if IS_3G_SAR_TX_POWER_BACKOFF_SUPPORT
+typedef struct
+{
+ U_sSUBBAND_SECTION subband_power_offset;
+} U_sSARBackoffTABLE;
+
+typedef struct
+{
+ U_sSARBackoffTABLE table[SAR_3G_TABLE_NUM];
+} U_sSARBackoffDATA;
+#endif /* IS_3G_TX_POWER_OFFSET_SUPPORT */
+
+
+#if IS_3G_TX_POWER_OFFSET_SUPPORT
+typedef struct
+{
+ U_sSUBBAND_SECTION subband_power_offset[CAL_UARFCN_SECTION];
+} U_sTXPOWEROFFSETTABLE;
+
+typedef struct
+{
+ U_sTXPOWEROFFSETTABLE table[TPO_3G_TABLE_NUM];
+} U_sTXPOWEROFFSETDATA;
+#endif /* IS_3G_TX_POWER_OFFSET_SUPPORT */
+
+#if IS_3G_TX_NSFT_POWER_OFFSET_SUPPORT
+typedef struct
+{
+ kal_int16 nsft_pwr_offset;
+} U_sTXNSFTPOWEROFFSETDATA;
+
+typedef struct
+{
+ U_sTXNSFTPOWEROFFSETDATA nsftTpoTable[UL1D_RF_CUSTOM_BAND];
+} U_sTXNSFTPOWEROFFSETDATA_ALLBAND;
+#endif
+
+#if (IS_3G_TAS_ANTENNA_IDX_ON_TEST_SIM)
+typedef struct {
+ ul1_antenna_idx_E xBand1_TAS_ANT_IDX;
+ ul1_antenna_idx_E xBand2_TAS_ANT_IDX;
+ ul1_antenna_idx_E xBand3_TAS_ANT_IDX;
+ ul1_antenna_idx_E xBand4_TAS_ANT_IDX;
+ ul1_antenna_idx_E xBand5_TAS_ANT_IDX;
+ ul1_antenna_idx_E xBand6_TAS_ANT_IDX;
+ ul1_antenna_idx_E xBand8_TAS_ANT_IDX;
+ ul1_antenna_idx_E xBand9_TAS_ANT_IDX;
+ ul1_antenna_idx_E xBand10_TAS_ANT_IDX;
+ ul1_antenna_idx_E xBand11_TAS_ANT_IDX;
+ ul1_antenna_idx_E xBand19_TAS_ANT_IDX;
+} UMTS_TAS_ANT_IDX_T;
+#endif
+
+#if (IS_3G_DAT_UL1_CUSTOM_SUPPORT || IS_3G_TAS_UL1_CUSTOM_SUPPORT)
+typedef enum
+{
+ CAT_A = 0,
+ CAT_B = 1,
+ #if !IS_3G_UTAS_SUPPORT
+ CAT_C = 2,
+ #endif
+ CAT_CNT,
+}UMTS_CUSTOM_TAS_CAT_E;
+#endif
+
+#if IS_3G_DAT_UL1_CUSTOM_SUPPORT
+typedef enum
+{
+ UMTS_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX0,
+ UMTS_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX1,
+ UMTS_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX2,
+ UMTS_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX3,
+ UMTS_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX4,
+ UMTS_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX5,
+ UMTS_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX6,
+ UMTS_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX7,
+ UMTS_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX8,
+ UMTS_DAT_CAT_A_MIPI_TABLE_CONFIG_IDX9,
+ UMTS_DAT_CAT_A_MIPI_TABLE_NULL = UMTS_DAT_MIPI_TABLE_NULL,
+}UMTS_CUSTOM_DAT_CAT_A_MIPI_TBL_IDX_E;
+
+
+typedef enum
+{
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX0,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX1,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX2,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX3,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX4,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX5,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX6,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX7,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX8,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX9,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX10,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX11,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX12,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX13,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX14,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX15,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX16,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX17,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX18,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX19,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX20,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX21,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX22,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX23,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX24,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX25,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX26,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX27,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX28,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX29,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX30,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX31,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX32,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX33,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX34,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX35,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX36,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX37,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX38,
+ UMTS_DAT_CAT_B_MIPI_TABLE_CONFIG_IDX39,
+ UMTS_DAT_CAT_B_MIPI_TABLE_NULL = UMTS_DAT_MIPI_TABLE_NULL,
+}UMTS_CUSTOM_DAT_CAT_B_MIPI_TBL_IDX_E;
+
+typedef enum
+{
+ UMTS_DAT_CAT_A_CONFIG_IDX0,
+ UMTS_DAT_CAT_A_CONFIG_IDX1,
+ UMTS_DAT_CAT_A_CONFIG_IDX2,
+ UMTS_DAT_CAT_A_CONFIG_IDX3,
+ UMTS_DAT_CAT_A_CONFIG_IDX4,
+ UMTS_DAT_CAT_A_CONFIG_IDX5,
+ UMTS_DAT_CAT_A_CONFIG_IDX6,
+ UMTS_DAT_CAT_A_CONFIG_IDX7,
+ UMTS_DAT_CAT_A_CONFIG_IDX8,
+ UMTS_DAT_CAT_A_CONFIG_IDX9,
+ UMTS_DAT_CAT_A_NULL = UMTS_DAT_FE_NULL,
+}UMTS_CUSTOM_DAT_CAT_A_IDX_E;
+
+typedef enum
+{
+ UMTS_DAT_CAT_B_CONFIG_IDX0,
+ UMTS_DAT_CAT_B_CONFIG_IDX1,
+ UMTS_DAT_CAT_B_CONFIG_IDX2,
+ UMTS_DAT_CAT_B_CONFIG_IDX3,
+ UMTS_DAT_CAT_B_CONFIG_IDX4,
+ UMTS_DAT_CAT_B_CONFIG_IDX5,
+ UMTS_DAT_CAT_B_CONFIG_IDX6,
+ UMTS_DAT_CAT_B_CONFIG_IDX7,
+ UMTS_DAT_CAT_B_CONFIG_IDX8,
+ UMTS_DAT_CAT_B_CONFIG_IDX9,
+ UMTS_DAT_CAT_B_CONFIG_IDX10,
+ UMTS_DAT_CAT_B_CONFIG_IDX11,
+ UMTS_DAT_CAT_B_CONFIG_IDX12,
+ UMTS_DAT_CAT_B_CONFIG_IDX13,
+ UMTS_DAT_CAT_B_CONFIG_IDX14,
+ UMTS_DAT_CAT_B_CONFIG_IDX15,
+ UMTS_DAT_CAT_B_CONFIG_IDX16,
+ UMTS_DAT_CAT_B_CONFIG_IDX17,
+ UMTS_DAT_CAT_B_CONFIG_IDX18,
+ UMTS_DAT_CAT_B_CONFIG_IDX19,
+ UMTS_DAT_CAT_B_CONFIG_IDX20,
+ UMTS_DAT_CAT_B_CONFIG_IDX21,
+ UMTS_DAT_CAT_B_CONFIG_IDX22,
+ UMTS_DAT_CAT_B_CONFIG_IDX23,
+ UMTS_DAT_CAT_B_CONFIG_IDX24,
+ UMTS_DAT_CAT_B_CONFIG_IDX25,
+ UMTS_DAT_CAT_B_CONFIG_IDX26,
+ UMTS_DAT_CAT_B_CONFIG_IDX27,
+ UMTS_DAT_CAT_B_CONFIG_IDX28,
+ UMTS_DAT_CAT_B_CONFIG_IDX29,
+ UMTS_DAT_CAT_B_CONFIG_IDX30,
+ UMTS_DAT_CAT_B_CONFIG_IDX31,
+ UMTS_DAT_CAT_B_CONFIG_IDX32,
+ UMTS_DAT_CAT_B_CONFIG_IDX33,
+ UMTS_DAT_CAT_B_CONFIG_IDX34,
+ UMTS_DAT_CAT_B_CONFIG_IDX35,
+ UMTS_DAT_CAT_B_CONFIG_IDX36,
+ UMTS_DAT_CAT_B_CONFIG_IDX37,
+ UMTS_DAT_CAT_B_CONFIG_IDX38,
+ UMTS_DAT_CAT_B_CONFIG_IDX39,
+ UMTS_DAT_CAT_B_NULL = UMTS_DAT_FE_NULL,
+}UMTS_CUSTOM_DAT_CAT_B_IDX_E;
+
+
+typedef enum
+{
+ UMTS_DAT_STATE0,
+ UMTS_DAT_STATE1,
+ UMTS_DAT_STATE2,
+ UMTS_DAT_STATE3,
+ UMTS_DAT_STATE4,
+ UMTS_DAT_STATE5,
+ UMTS_DAT_STATE6,
+ UMTS_DAT_STATE7,
+ UMTS_DAT_STATE_NULL,
+}UMTS_CUSTOM_DAT_STATE_E;
+
+
+typedef struct
+{
+ kal_bool feature_enable;
+ kal_int16 ap_scenario;
+}UMTS_CUSTOM_DAT_FEATURE_BY_RAT_T;
+
+#if IS_3G_UDAT_SUPPORT
+
+#if !IS_3G_GEN97_DAT_SUPPORT
+typedef struct
+{
+ kal_uint16 mipi_subband_freq;
+ MMRFD_CUSTOM_ANT_SWITCH_IDX_E switch_config_idx;
+ MMRFD_CUSTOM_ANT_TUNER_IDX_E tuner_config_idx;
+}UMTS_CUSTOM_DAT_SPLIT_ANT_FE_T;
+
+typedef struct
+{
+ kal_uint8 dat_split_band_num;
+ UMTS_CUSTOM_DAT_SPLIT_ANT_FE_T split_ant_setting[UMTS_RF_UDAT_MAX_SPLIT_BAND_NUM];
+}UMTS_CUSTOM_DAT_FE_ROUTE_MAP_T;
+#endif
+
+#else
+typedef struct
+{
+ kal_uint32 cat_a_route_num;
+ kal_uint32 cat_b_route_num;
+}UMTS_CUSTOM_DAT_FE_ROUTE_MAP_T;
+#endif
+
+#if !IS_3G_GEN97_DAT_SUPPORT
+typedef struct
+{
+ UMTSBand usage;
+ UMTS_CUSTOM_DAT_FE_ROUTE_MAP_T dat_fe_setting[UMTS_DAT_MAX_STATE_NUM];
+}UMTS_CUSTOM_DAT_ROUTE_SETTING_T;
+
+typedef struct
+{
+ UMTS_CUSTOM_DAT_ROUTE_SETTING_T UMTS_dat_fe_route_db[UMTS_DAT_MAX_FE_ROUTE_NUM];
+}UMTS_CUSTOM_DAT_FE_ROUTE_DATABASE_T;
+#endif
+
+typedef struct
+{
+ kal_uint32 bpi_mask;
+ kal_uint32 bpi_value;
+ UMTS_CUSTOM_DAT_CAT_A_MIPI_TBL_IDX_E dat_mipi_table_index;
+}UMTS_CUSTOM_DAT_CAT_A_FE_SETTING_T;
+
+typedef struct
+{
+ kal_uint32 bpi_mask;
+ kal_uint32 bpi_value;
+ UMTS_CUSTOM_DAT_CAT_B_MIPI_TBL_IDX_E dat_mipi_table_index;
+}UMTS_CUSTOM_DAT_CAT_B_FE_SETTING_T;
+
+typedef struct
+{
+ UMTS_CUSTOM_DAT_CAT_A_FE_SETTING_T dat_cat_a_fe_route[UMTS_DAT_MAX_CAT_A_ROUTE_NUM];
+}UMTS_CUSTOM_DAT_FE_CAT_A_T;
+
+typedef struct
+{
+ UMTS_CUSTOM_DAT_CAT_B_FE_SETTING_T dat_cat_b_fe_route[UMTS_DAT_MAX_CAT_B_ROUTE_NUM];
+}UMTS_CUSTOM_DAT_FE_CAT_B_T;
+
+
+typedef struct
+{
+ UMTS_CUSTOM_DAT_FE_CAT_A_T dat_cat_a_fe_db;
+ UMTS_CUSTOM_DAT_FE_CAT_B_T dat_cat_b_fe_db;
+}UMTS_CUSTOM_DAT_FE_DATABASE_T;
+#endif
+
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+typedef struct
+{
+ UMTSBand BandIndicator[MAX_SUPPORTED_BAND_INDEX];
+}U_sUl1dRfBandIndicator;
+#else
+typedef struct
+{
+ UMTSBand HB1;
+ UMTSBand HB2;
+ UMTSBand HB3;
+ UMTSBand LB1;
+ UMTSBand LB2;
+}U_sUl1dRfBandIndicator;
+#endif
+
+typedef struct
+{
+ UMTS_RXIOBASE_T rxLnaSel[UMTS_FE_RXBASE_TBL_SIZE_MAX];
+}U_sUl1dRfRxLnaPortSel;
+
+typedef struct
+{
+ UMTS_TXIOBASE_T txPathSel[UMTS_FE_TXBASE_TBL_SIZE_MAX];
+}U_sUl1dRfTxPathSel;
+
+typedef struct
+{
+ kal_uint32 Rx_Main_Path_Onoff;
+ kal_uint32 Rx_Diversity_Path_Onoff;
+}U_sUl1dRxdPathSetting;
+
+#if defined (__UL1_HS_PLUS_PLATFORM__)
+typedef struct
+{
+ MPR_Setting HSDPA_MprBackOff[20];
+ MPR_Setting HSUPA_MprBackOff[20];
+ #if IS_3G_MPR_EXTEND_SUPPORT
+ MPR_Setting_SUB HSUPA_MprBackOff_SUB[20][5];
+ kal_bool isR6MprSubEn;
+ #endif
+}U_sUl1dMprBackOff;
+#endif
+
+#if IS_3G_MIPI_SUPPORT
+typedef struct
+{
+ kal_bool is3gMipiEn;
+ kal_uint16 mipiOffset;
+}U_sUl1dRfMipiSetting;
+#endif
+
+typedef struct
+{
+ /* PCFE and DPD OTFC non-custom parameters */
+ U_Ul1D_PCFE_DPD_OTFC_NONCUSTOM_PARA_T pcfe_dpdotfc_noncustom_para;
+
+ /* PCFE and DPD OTFC custom parameters */
+ U_UL1D_PCFE_DPD_OTFC_CUSTOM_PARA_T pcfe_dpdotfc_custom_para;
+
+} U_sUl1dDpdCustomInputData;
+
+#if IS_3G_ELNA_IDX_SUPPORT
+typedef struct
+{
+ MML1_FE_ELNA_ROUTE_E RxElnaIdx[20];
+ MML1_FE_ELNA_ROUTE_E RxdElnaIdx[20];
+}UMTS_CUSTOM_ELNA_IDX_T;
+
+typedef struct
+{
+ MML1_FE_ELNA_ROUTE_E elna_idx_main;
+ MML1_FE_ELNA_ROUTE_E elna_idx_div;
+}UMTS_ELNA_IDX_T;
+
+#endif
+
+#if IS_3G_FDD_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+#define UMTS_RF_INTERFERE_FREQ_SET_NUM 8 // the maximum number of frequency intervals supported per group
+#define UMTS_RF_INTERFERE_FREQ_TABLE_NUM 8 // the maximum number of HW components supported
+
+typedef enum
+{
+ UMTS_RF_INTERFERE_CHECK_DISABLE,
+ UMTS_RF_INTERFERE_CHECK_ENABLE,
+}UMTS_CUSTOM_INTERFERE_CHECK_SWITCH_E;
+
+typedef struct
+{
+ kal_uint16 freq_start;
+ kal_uint16 freq_end;
+}UMTS_RF_INTERFERENCE_FREQUENCY_SET_T;
+
+typedef struct
+{
+ UMTS_RF_INTERFERENCE_FREQUENCY_SET_T freq_groupA[UMTS_RF_INTERFERE_FREQ_SET_NUM];
+ UMTS_RF_INTERFERENCE_FREQUENCY_SET_T freq_groupB[UMTS_RF_INTERFERE_FREQ_SET_NUM];
+}UMTS_RF_INTERFERENCE_FREQUENCY_TABLE_T;
+
+typedef struct
+{
+ UMTS_RF_INTERFERENCE_FREQUENCY_TABLE_T freq_table[UMTS_RF_INTERFERE_FREQ_TABLE_NUM];
+ kal_uint8 bitmap;
+}UMTS_RF_INTERFERENCE_FREQUENCY_T;
+#endif
+
+/********************************************************************
+** CA structure declaration
+*********************************************************************/
+
+typedef struct
+{
+ UMTSCaBand CA_IND_0;
+ UMTSCaBand CA_IND_1;
+ UMTSCaBand CA_IND_2;
+ UMTSCaBand CA_IND_3;
+ UMTSCaBand CA_IND_4;
+}U_sUl1dRfCaBandIndicator;
+
+typedef struct
+{
+ kal_uint16 cc_cnt;
+ UMTSBand cc_band[MAX_NUMBER_OF_RX_SUBBLOCK];
+}UMTS_CA_CFG_T;
+
+typedef struct
+{
+ UMTS_RX_IODATA_T rxIodata;
+ UMTS_RX_PDATA_T rxPdata;
+ #if IS_3G_RXD_FE_CONTROL_SUPPORT
+ UMTS_RX_PDATA_T rxPdata2;
+ #endif
+ UMTS_Route rxMipiTblIdx;
+}UMTS_FE_RX_ROUTE_T;
+
+typedef struct
+{
+ UMTS_TX_IODATA_T txIodata;
+ UMTS_TX_PDATA_T txPdata;
+ UMTS_Route txMipiTblIdx;
+}UMTS_FE_TX_ROUTE_T;
+
+typedef struct
+{
+ UMTSBand band;
+ UMTS_FE_RX_ROUTE_T rx_cfg;
+ UMTS_FE_TX_ROUTE_T tx_cfg;
+}U_sUl1dRfFeRouteSetting;
+
+typedef struct
+{
+ kal_uint32 band; //TBD: how about CA_BAND_IND?
+ kal_uint8 cc_cnt;
+ U_sUl1dRfFeRouteSetting cc_fe_route[MAX_NUMBER_OF_RX_SUBBLOCK];
+}UMTS_FE_ROUTE_TABLE_T;
+
+typedef struct
+{
+ UMTS_Route rx_tbl_idx[MAX_NUMBER_OF_RX_SUBBLOCK];
+ UMTS_Route tx_tbl_idx[MAX_NUMBER_OF_TX_SUBBLOCK];
+}UMTS_USAGE_ELM_T;
+
+typedef union
+{
+ UMTS_RXIOBASE_T rxio;
+ UMTS_TXIOBASE_T txio;
+ UMTS_RX_PDATABASE_T rxbpi;
+ UMTS_TX_PDATABASE_T txbpi;
+}UMTS_DATABASE_U;
+
+typedef struct
+{
+ UMTS_CA_CFG_T usage;
+ UMTS_USAGE_ELM_T iobase;
+ UMTS_USAGE_ELM_T pdatabase;
+ UMTS_USAGE_ELM_T mipibase;
+}UMTS_FE_USAGE_T;
+
+typedef struct
+{
+ void *database_ptr;
+ kal_uint16 database_elm_size;
+ kal_uint16 database_ttl_size;
+ kal_uint16 (*database_handler)( kal_uint16 handle, void *src, void *dst );
+} UL1D_DATABASE_HANDLER_T;
+
+
+#if IS_3G_REMOVE_MIPI
+typedef struct
+{
+ /* Start pattern to be recognized by Modem Bin Update Tool */
+ kal_uint32 startPattern;
+
+ /* RF and parameter structure version */
+ kal_uint8 structVersion; // record structure version for tool once we add more parameters to be customized in the future
+ kal_uint8 rfType; // needed? To distinguish O3, OH and furhter 3G RF chips
+ kal_uint8 isDataUpdate; // default FALSE, will be update to be TRUE after tool update parameters
+ #if defined (__UL1_HS_PLUS_PLATFORM__)
+ kal_bool umtsRfSettingByNVRAM; // default True. if the value is False, than Single SW for Multiple HW scheme will be applied.
+ #endif
+
+ /* Timing of PA control */
+ U_sUl1dRfPaControlTiming umtsRfPaControlTimingOffset;
+
+ /* RF T/RX timing offset */
+ U_sUl1dRfBsiBpiTiming umtsBsiBpiTiming;
+
+ /* BPI data allocation */
+ U_sUl1dRfBpiData umtsPdata;
+
+ /* RF Hign-band and Low-band indicator */
+ U_sUl1dRfBandIndicator umtsBandIndicator;
+
+ /* RX LNA port selection */
+ U_sUl1dRfRxLnaPortSel umtsRxLnaPortSel;
+
+ /* TX output path selection */
+ U_sUl1dRfTxPathSel umtsTxPathSel;
+
+ /* PMU VPA control disable/enable */
+ kal_bool xPMU_PA_CONTROL;
+
+#if defined (__UL1_HS_PLUS_PLATFORM__)
+ /* PMU VPA control disable/enable */
+ U_sUl1dMprBackOff umtsMprBackOff;
+#endif
+
+ /* RxD support bit map*/
+ kal_bool umtsRxDAlwaysOn;
+
+ /* Tx PA dirft compensation bit map*/
+ kal_uint32 umtsPADriftCompensation;
+
+ /*MT6320, Vrf18 Bulk=>LOD solution*/
+ kal_bool ultra_low_cost_solution;
+
+ /*MT6167, temperature measurement enable*/
+ kal_bool customer_TM_enable;
+
+ /* Baseband Idle Mode RXD Feature enable */
+ kal_bool umtsIdleModeRxDOn;
+
+ /* End pattern to be recognized by Modem Bin Update Tool */
+
+ /* VPA Mode Setting */
+ kal_bool vpa_fpwm_mode;
+
+ /* PA Section */
+ kal_uint8 pa_section;
+
+#if IS_3G_MIPI_SUPPORT
+ U_sUl1dRfMipiSetting umtsRfMipiSetting;
+#endif
+
+ /* RF CA Band indicator */
+ U_sUl1dRfCaBandIndicator umtsCaBandIndicator;
+
+ /* CA RF FE usage table */
+ UMTS_FE_USAGE_T umtsCaFrontEndUsageLut[UMTS_RF_FRONT_END_NUM_MAX];
+
+#if IS_3G_FDD_RX_PATH_SELECTION_SUPPORT
+ U_sRxPathSelection umtsRxPathSelection;
+#endif
+ kal_bool band5_and_band6_indicator;
+#if IS_3G_B5_AND_B19_INDICATOR_SUPPORT
+ kal_bool band5_and_band19_indicator;
+ kal_bool disable_band5_indicator;
+#endif
+
+#if IS_3G_RX_POWER_OFFSET_SUPPORT
+ U_sUl1dMetaRxPowerOffsetSetting umtsRxPowerOffsetSetting;
+#endif
+
+ /* End pattern to be recognized by Modem Bin Update Tool */
+ kal_uint32 endPattern;
+
+}U_sUl1dRfCustomInputData;
+#else
+typedef struct
+{
+ /* Start pattern to be recognized by Modem Bin Update Tool */
+ kal_uint32 startPattern;
+
+ /* RF and parameter structure version */
+ kal_uint8 structVersion; // record structure version for tool once we add more parameters to be customized in the future
+ kal_uint8 rfType; // needed? To distinguish O3, OH and furhter 3G RF chips
+ kal_uint8 isDataUpdate; // default FALSE, will be update to be TRUE after tool update parameters
+ #if defined (__UL1_HS_PLUS_PLATFORM__)
+ kal_bool umtsRfSettingByNVRAM; // default True. if the value is False, than Single SW for Multiple HW scheme will be applied.
+ #endif
+
+ /* Timing of PA control */
+ U_sUl1dRfPaControlTiming umtsRfPaControlTimingOffset;
+
+ /* RF T/RX timing offset */
+ U_sUl1dRfBsiBpiTiming umtsBsiBpiTiming;
+
+ /* BPI data allocation */
+ //U_sUl1dRfBpiData umtsPdata;
+
+ /* RF Hign-band and Low-band indicator */
+ U_sUl1dRfBandIndicator umtsBandIndicator;
+
+ /* RX LNA port selection */
+ //U_sUl1dRfRxLnaPortSel umtsRxLnaPortSel;
+
+ /* TX output path selection */
+ //U_sUl1dRfTxPathSel umtsTxPathSel;
+
+ /* PMU VPA control disable/enable */
+ kal_bool xPMU_PA_CONTROL;
+
+#if defined (__UL1_HS_PLUS_PLATFORM__)
+ /* PMU VPA control disable/enable */
+ U_sUl1dMprBackOff umtsMprBackOff;
+#endif
+
+ /* RxD support bit map*/
+ kal_bool umtsRxDAlwaysOn;
+
+ /* Tx PA dirft compensation bit map*/
+ kal_uint32 umtsPADriftCompensation;
+
+ /*MT6320, Vrf18 Bulk=>LOD solution*/
+ kal_bool ultra_low_cost_solution;
+
+ /*MT6167, temperature measurement enable*/
+ kal_bool customer_TM_enable;
+
+ /* Baseband Idle Mode RXD Feature enable */
+ kal_bool umtsIdleModeRxDOn;
+
+ /* End pattern to be recognized by Modem Bin Update Tool */
+
+ /* VPA Mode Setting */
+ kal_bool vpa_fpwm_mode;
+
+ /* PA Section */
+ kal_uint8 pa_section;
+
+#if IS_3G_MIPI_SUPPORT
+ // U_sUl1dRfMipiSetting umtsRfMipiSetting;
+#endif
+
+ /* RF CA Band indicator */
+ U_sUl1dRfCaBandIndicator umtsCaBandIndicator;
+
+ /* CA RF FE usage table */
+ //UMTS_FE_USAGE_T umtsCaFrontEndUsageLut[UMTS_RF_FRONT_END_NUM_MAX];
+
+#if IS_3G_FDD_RX_PATH_SELECTION_SUPPORT
+ U_sRxPathSelection umtsRxPathSelection;
+#endif
+
+ kal_bool band5_and_band6_indicator;
+#if IS_3G_B5_AND_B19_INDICATOR_SUPPORT
+ kal_bool band5_and_band19_indicator;
+ kal_bool disable_band5_indicator;
+#endif
+
+#if IS_3G_RX_POWER_OFFSET_SUPPORT
+ U_sUl1dMetaRxPowerOffsetSetting umtsRxPowerOffsetSetting;
+#endif
+
+ /* End pattern to be recognized by Modem Bin Update Tool */
+ kal_uint32 endPattern;
+
+}U_sUl1dRfCustomInputData;
+
+
+#endif
+
+/*=========================================================*/
+//
+// CA Route Table SETTING
+//
+/*=========================================================*/
+/** UMTS RF Rx VCO-Divider set element template */
+typedef struct
+{
+ kal_uint8 vco; ///< VCO index: 1: VCO1; 2: VCO2; 3: VCO31 or VCO32, and NULL (0xFF). DCO index: 0:DCOH, 1:DCOL
+ kal_uint8 div; ///< Divider: 2, 4, 6, 8, 10, 3, and NULL (0xFF)
+} UMTS_RF_VCO_DIV_SEL_T;
+
+/** UMTS RF Rx VCO-Divider selection table */
+typedef struct
+{
+ UMTSBand band;
+ UMTS_RF_VCO_DIV_SEL_T vco_div_set[UMTS_RF_RX_VCO_DIV_SET_NUM];
+} UMTS_RF_RX_VCO_DIV_TABLE_T;
+
+/** UMTS RF Tx VCO-Divider selection table
+ */
+typedef struct
+{
+ UMTSBand band;
+ UMTS_RF_VCO_DIV_SEL_T vco_div_set[UMTS_RF_TX_VCO_DIV_SET_NUM];
+} UMTS_RF_TX_VCO_DIV_TABLE_T;
+
+/** UMTS RF CA VCO-Divider selection table
+ */
+typedef struct
+{
+ UMTSBand band[UMTS_RF_CA_MAX_CC_NUM]; // 0: PCC, 1: SCC
+ UMTS_RF_VCO_DIV_SEL_T vco_div_set[UMTS_RF_CA_VCO_DIV_SET_NUM]; // 0: RxPCC, 1: RxSCC, 2: TxPCC
+} UMTS_RF_CA_VCO_DIV_TABLE_T;
+
+typedef struct
+{
+ UMTSBand band;
+ UMTS_FE_RX_ROUTE_T rx_cfg;
+ UMTS_RF_VCO_DIV_SEL_T rx_vco_div;
+ kal_uint8 srx;
+ UMTS_Route comp_rroute;
+ kal_uint8 rx_irr_comp_idx;
+ kal_uint8 rx_dc_comp_idx;
+ kal_uint8 rx_rfic_sel;
+}UMTS_RX_ROUTE_TABLE_T;
+
+typedef struct
+{
+ UMTSBand band;
+ UMTS_FE_TX_ROUTE_T tx_cfg;
+ UMTS_RF_VCO_DIV_SEL_T tx_vco_div;
+ kal_uint8 stx;
+ UMTS_Route comp_troute;
+ kal_uint8 tx_rfic_sel;
+}UMTS_TX_ROUTE_TABLE_T;
+
+typedef struct
+{
+ UMTS_CA_CFG_T usage;
+ UMTS_Route rx_cc_route_idx[MAX_NUMBER_OF_RX_SUBBLOCK];
+ UMTS_Route tx_cc_route_idx;
+ kal_uint8 rx_iip2_comp_idx[MAX_NUMBER_OF_RX_SUBBLOCK];
+}UMTS_USAGE_DES_T;
+
+typedef UMTS_Route UMTS_RX_COMP_ROUTE_TABLE_T;
+typedef UMTS_Route UMTS_TX_COMP_ROUTE_TABLE_T;
+
+typedef struct
+{
+ UMTS_FE_ROUTE_TABLE_T *fe_rt;
+ UMTS_RX_ROUTE_TABLE_T *rx_rt;
+ UMTS_TX_ROUTE_TABLE_T *tx_rt;
+ UMTS_RX_COMP_ROUTE_TABLE_T *rcmp_rt;
+ UMTS_TX_COMP_ROUTE_TABLE_T *tcmp_rt;
+ UMTS_USAGE_DES_T *ug_rt;
+}UMTS_TBL_MAP_T;
+
+#if UMTS_POC_RECAL_ENABLE
+typedef struct
+{
+ UMTS_RF_POC_RECAL_DATA_T umts_debug_result_recal[MAX_SUPPORTED_BAND_INDEX];
+}UMTS_RECAL_DEBUG_T;
+
+typedef struct
+{
+ kal_bool isTxDetRecal;
+ kal_uint32 txDetRecalIdx;
+}UMTS_RECAL_TXDET_INFO_T;
+#endif
+/******************************
+* R/Tx/DET POC cal data
+*******************************/
+typedef struct
+{
+ kal_uint32 verno[MAX_SUPPORTED_BAND_INDEX];
+ UMTS_RF_POC_RX_COMP_DATA_T umts_rx_comp[MAX_SUPPORTED_BAND_INDEX];
+ UMTS_RF_POC_DET_COMP_DATA_T umts_det_comp[MAX_SUPPORTED_BAND_INDEX];
+ UMTS_RF_POC_TX_COMP_DATA_T umts_tx_comp[MAX_SUPPORTED_BAND_INDEX];
+} UMTS_RF_POWER_ON_CAL_DATA_T;
+
+/** FEC AGC DC Table
+ */
+#define SRAM_BYTE_128_ALIGN (128)
+#define SRAM_PADDIND_TO_128_ALIGN(x) ((((x)%SRAM_BYTE_128_ALIGN)==0)?SRAM_BYTE_128_ALIGN:(SRAM_BYTE_128_ALIGN - ((x)%SRAM_BYTE_128_ALIGN)))
+
+typedef struct
+{
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_rf_dc_hpm[UL1D_ANT_NUM]; //RF DC for HPM
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_rf_dc_lpm[UL1D_ANT_NUM]; //RF DC for LPM
+ UMTS_RF_POC_RX_DC_HPM_COMP_T rx_dig_dc_hpm[UL1D_ANT_NUM]; //Digital DC for HPM
+ UMTS_RF_POC_RX_DC_LPM_COMP_T rx_dig_dc_lpm[UL1D_ANT_NUM]; //Digital DC for LPM
+}UL1D_RXAGC_RF_POC_RX_DC_COMP_PER_ROUTE_T;
+
+typedef struct
+{
+ UL1D_RXAGC_RF_POC_RX_DC_COMP_PER_ROUTE_T dc_part;
+ kal_uint8 ready_bit; // for FEC/L1core do checksum
+}UL1D_RF_RXAGC_DC_TABLE_T;
+
+//calibration data for a CC
+typedef struct
+{
+ UL1D_RF_RXAGC_DC_TABLE_T dc_table;
+ kal_uint8 padding_to_128_bytes[SRAM_PADDIND_TO_128_ALIGN(sizeof(UL1D_RF_RXAGC_DC_TABLE_T))];
+}UL1D_RF_RXAGC_DC_TABLE_L1_EMI_T;
+
+/*******************************************************************************
+** Global data for RF customization and META Factory Calibration
+*******************************************************************************/
+extern U_sUl1dRfCustomInputData *UMTS_RF_CUSTOM_INPUT_DATA_ptr;
+extern U_sAFCDACDATA *U_AFC_DAC_ptr;
+extern U_sAFCCAPDATA *U_AFC_CAP_ptr;
+extern kal_uint16 *U_TEMP_DAC_ptr;
+
+#if IS_3G_ELNA_IDX_SUPPORT
+extern UMTS_CUSTOM_ELNA_IDX_T *UMTS_ELNA_IDX_LUT_ptr;
+extern UMTS_CUSTOM_ELNA_IDX_T UMTS_ELNA_IDX_LUT_PCORE;
+#endif
+
+#if (IS_3G_TAS_ANTENNA_IDX_ON_TEST_SIM)
+extern UMTS_TAS_ANT_IDX_T* UMTS_TAS_ANT_IDX_ptr;
+extern UMTS_TAS_ANT_IDX_T UMTS_TAS_ANT_IDX_by_band;
+#endif
+
+#ifdef __MTK_TARGET__
+#if IS_3G_SAR_TX_POWER_OFFSET_CONDI_SUPPORT
+extern U_sSARBackoffDATA UMTS_SAR_BACKOFF_TABLE_BACKUP[UL1D_RF_CUSTOM_BAND];
+#endif
+#endif
+
+#if IS_3G_SAR_TX_POWER_BACKOFF_SUPPORT
+extern U_sSARBackoffDATA* UMTS_SAR_BACKOFF_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+
+#if IS_3G_TX_POWER_OFFSET_SUPPORT
+extern U_sTXPOWEROFFSETDATA* UMTS_TX_POWER_OFFSET_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if IS_3G_TX_NSFT_POWER_OFFSET_SUPPORT
+extern U_sTXNSFTPOWEROFFSETDATA_ALLBAND* UMTS_TX_NSFT_POWER_OFFSET_ptr;
+#endif
+
+#if (IS_3G_RX_POWER_OFFSET_SUPPORT)
+extern U_sRXPOWEROFFSETDATA* UMTS_RX_POWER_OFFSET_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+
+#if (IS_3G_VPA_SEL_BY_BAND_SUPPORT)
+extern UMTS_VPA_SOURCE_TYPE* UMTS_VPA_SRC_SEL_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if IS_3G_RFEQ_COEF_SUBBAND_SUPPORT
+extern hs_dsch_rfeq_info_band_T* UMTS_RFEQ_COEF_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if IS_3G_RFEQ_REAL_COEF_TEST
+extern URXDFE_REAL_RFEQ_CUSTOM_BAND_T* UMTS_RFEQ_REAL_COEF_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if IS_3G_RF_NCCA_SUPPORT
+extern U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_TABLE[UMTS_AGC_PATHLOSS_TBL_SIZE];
+#else
+extern U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+extern U_sRAMPDATA *UMTS_RampData[UL1D_RF_CUSTOM_BAND];
+extern U_sPAOCTLVLSETTING *U_PA_OCTLEV_TABLE[UL1D_RF_CUSTOM_BAND];
+extern U_sPARACHTMCOMPDATA *U_PA_RACH_COMP_TABLE[UL1D_RF_CUSTOM_BAND];
+#if IS_3G_RF_NCCA_SUPPORT
+extern U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_RXD_TABLE[UMTS_AGC_PATHLOSS_TBL_SIZE]; //RXD path loss
+#else
+extern U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_RXD_TABLE[UL1D_RF_CUSTOM_BAND]; //RXD path loss
+#endif
+extern U_sPADRIFTSETTING *U_PA_DRIFT_TABLE[];
+
+extern UMTS_RF_POWER_ON_CAL_DATA_T *U_POC_CAL_DATA_ptr;
+
+#if __IS_UL1D_DPD_SUPPORT__
+extern U_sDPD_GROUP_ALL *p_U_DPD_GROUP_TABLE[UL1D_RF_CUSTOM_BAND];
+extern U_sDPD_GROUP_ALL* U_DPD_GROUP_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+extern U_sUl1dDpdCustomInputData *UMTS_DPD_CUSTOM_INPUT_DATA_ptr;
+extern U_sUl1dDpdCustomInputData *UMTS_DPD_CUSTOM_INPUT_DATA_PCORE_ptr;
+extern U_sUl1dDpdCustomInputData UMTS_DPD_CUSTOM_INPUT_DATA_PCORE;
+extern DPD_ENABLE_E *UMTS_DPD_ENABLE_ptr;
+extern DPD_ENABLE_E *UMTS_DPD_ENABLE_PCORE_ptr;
+extern DPD_ENABLE_E UMTS_DPD_ENABLE_PCORE;
+#endif
+
+extern const U_sDPD_COMMON_CTRL* UMTS_DPD_CommonCtrlData_SetDefault[UL1D_RF_CUSTOM_BAND];
+extern const U_UL1D_PCFE_DPD_OTFC_CUSTOM_PARA_T ul1d_pcfe_dpd_otfc_custom_para_SetDefault;
+
+#if IS_URF_PCORE
+extern kal_bool is_band5_and_band6_indicator;
+#if IS_3G_B5_AND_B19_INDICATOR_SUPPORT
+extern kal_bool is_band5_and_band19_indicator;
+extern kal_bool is_disable_band5_indicator;
+#endif
+extern kal_uint8 ul1d_BandInfo[MAX_SUPPORTED_BAND_INDEX];
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+extern kal_uint32 band_info_debug;
+#endif
+extern kal_uint32 ul1d_CaBandInfo[UMTS_RF_CA_FE_NUM_MAX];
+extern UMTS_FE_ROUTE_TABLE_T UMTS_FE_ROUTE_TBL[UMTS_RF_FRONT_END_NUM_MAX];
+
+/*this may move to Pcore interface head file*/
+extern U_sUl1dRfCustomInputData *UMTS_RF_CUSTOM_INPUT_DATA_PCORE_ptr;
+extern U_sUl1dRfCustomInputData UMTS_RF_CUSTOM_INPUT_DATA_PCORE;
+
+/* const variable as default calibration data in Pcore */
+#if IS_3G_RF_NCCA_SUPPORT
+extern const U_sTEMPAGCOFFSET* const U_AGC_PATHLOSS_TABLE_SetDefault[UMTS_AGC_PATHLOSS_TBL_SIZE];
+#else
+extern const U_sTEMPAGCOFFSET* const U_AGC_PATHLOSS_TABLE_SetDefault[UL1D_RF_CUSTOM_BAND];
+#endif
+extern const U_sRAMPDATA* const UMTS_RampData_SetDefault[UL1D_RF_CUSTOM_BAND];
+extern const U_sPAOCTLVLSETTING* const U_PA_OCTLEV_TABLE_SetDefault[UL1D_RF_CUSTOM_BAND];
+extern const U_sPARACHTMCOMPDATA* const U_PA_RACH_COMP_TABLE_SetDefault[UL1D_RF_CUSTOM_BAND];
+#if IS_3G_RF_NCCA_SUPPORT
+extern const U_sTEMPAGCOFFSET* const U_AGC_PATHLOSS_RXD_TABLE_SetDefault[UMTS_AGC_PATHLOSS_TBL_SIZE]; //RXD path loss
+#else
+extern const U_sTEMPAGCOFFSET* const U_AGC_PATHLOSS_RXD_TABLE_SetDefault[UL1D_RF_CUSTOM_BAND]; //RXD path loss
+#endif
+extern const U_sPADRIFTSETTING* const U_PA_DRIFT_TABLE_SetDefault[];
+extern const U_sAFCDACDATA U_AFC_DAC_SetDefault;
+extern const U_sAFCCAPDATA U_AFC_CAP_SetDefault;
+extern const kal_uint16 U_TEMP_DAC_SetDefault[CAL_TEMP_SECTION];
+extern const UMTS_FE_ROUTE_TABLE_T UMTS_FE_ROUTE_TBL_SetDefault[UMTS_RF_FRONT_END_NUM_MAX];
+#if IS_3G_TAS_SUPPORT
+extern UMTS_TAS_Configuration_T UMTS_TAS_Configuration_Table_SetDefault;
+#endif/*IS_3G_TAS_SUPPORT*/
+
+#if (IS_3G_TAS_ANTENNA_IDX_ON_TEST_SIM)
+extern UMTS_TAS_ANT_IDX_T *UMTS_TAS_ANT_IDX_PCORE_ptr;
+#endif
+
+#if IS_3G_SAR_TX_POWER_BACKOFF_SUPPORT
+extern const U_sSARBackoffDATA* const U_SAR_BACKOFF_TABLE_SetDefault[];
+extern U_sSARBackoffDATA* UMTS_SAR_BACKOFF_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+
+#if IS_3G_TX_POWER_OFFSET_SUPPORT
+extern const U_sTXPOWEROFFSETDATA* const U_TX_POWER_OFFSET_TABLE_SetDefault[];
+extern U_sTXPOWEROFFSETDATA* UMTS_TX_POWER_OFFSET_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if IS_3G_TX_NSFT_POWER_OFFSET_SUPPORT
+extern const U_sTXNSFTPOWEROFFSETDATA* const U_TX_NSFT_POWER_OFFSET_TABLE_SetDefault[];
+extern U_sTXNSFTPOWEROFFSETDATA_ALLBAND* UMTS_TX_NSFT_POWER_OFFSET_PCORE_ptr;
+#endif
+
+#if(IS_3G_RX_POWER_OFFSET_SUPPORT)
+extern const U_sRXPOWEROFFSETDATA* const U_RX_POWER_OFFSET_TABLE_SetDefault[];
+extern U_sRXPOWEROFFSETDATA* UMTS_RX_POWER_OFFSET_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if (IS_3G_VPA_SEL_BY_BAND_SUPPORT)
+extern const UMTS_VPA_SOURCE_TYPE* const UMTS_VPA_SRC_SEL_TABLE_SetDefault[];
+extern UMTS_VPA_SOURCE_TYPE* UMTS_VPA_SRC_SEL_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if IS_3G_RFEQ_COEF_SUBBAND_SUPPORT
+extern const hs_dsch_rfeq_info_band_T* const UMTS_RFEQ_COEF_TABLE_SetDefault[];
+extern hs_dsch_rfeq_info_band_T* UMTS_RFEQ_COEF_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if IS_3G_RFEQ_REAL_COEF_TEST
+extern const URXDFE_REAL_RFEQ_CUSTOM_BAND_T* const UMTS_RFEQ_REAL_COEF_TABLE_SetDefault[];
+extern URXDFE_REAL_RFEQ_CUSTOM_BAND_T* UMTS_RFEQ_REAL_COEF_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if IS_URF_PCORE_REMOVE_SUPPORT
+#else
+
+/* Pcore global table pointer extern */
+#if IS_3G_RF_NCCA_SUPPORT
+extern U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_PCORE_TABLE[UMTS_AGC_PATHLOSS_TBL_SIZE];
+extern U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_RXD_PCORE_TABLE[UMTS_AGC_PATHLOSS_TBL_SIZE];
+#else
+extern U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+extern U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_RXD_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+extern U_sRAMPDATA *UMTS_RampData_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+extern U_sPAOCTLVLSETTING *U_PA_OCTLEV_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+extern U_sPARACHTMCOMPDATA *U_PA_RACH_COMP_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+extern U_sPADRIFTSETTING *U_PA_DRIFT_PCORE_TABLE[UL1D_RF_CUSTOM_BAND];
+extern U_sAFCDACDATA *U_AFC_DAC_PCORE_ptr;
+extern U_sAFCCAPDATA *U_AFC_CAP_PCORE_ptr;
+extern kal_uint16 *U_TEMP_DAC_PCORE_TABLE;
+extern UMTS_RF_POWER_ON_CAL_DATA_T *U_POC_CAL_DATA_PCORE_ptr;
+#endif /*IS_URF_PCORE_REMOVE_SUPPORT*/
+
+extern const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T *UMTS_PWRON_CAL_DATA_PTR[UL1D_RF_CUSTOM_BAND];
+#endif //IS_URF_PCORE
+
+// Start for ADAPT IOT AMR workaround
+//extern kal_bool UL1_IS_ADAPT_IOT_CUSTOMIZATION; //remove for gcc build error
+// End for ADAPT IOT AMR workaround
+extern kal_uint32 UL1D_DCXO_CAPID;
+extern kal_bool UL1D_Set_CAPID;
+
+/*******************************************************************************
+** Global Function Prototypes for RF customization and META Factory Calibration
+*******************************************************************************/
+// for RAC and L4 to recognize this FDD HW band support query API
+extern void UL1D_UeBandCapability(kal_uint16 *ue_cap);
+extern void UL1D_UeBandCapabilityEx(kal_uint32 *ue_cap);
+extern void UL1D_UeCaBandCapability(CA_RF_BAND_CAPABILITY_T *ue_cap, kal_uint8 report_index);
+extern void UL1TST_MsCapability(UMTS_MsCapabilityEx *ms_cap);
+extern void UL1D_RF_SetTempDac(void* table);
+extern void UL1D_RF_SetPathLossTable(UMTSBand rf_band, void* table);
+extern void UL1D_RF_SetTxDacData(UMTSBand rf_band, void* table );
+#if (defined __MD97__) || (defined __MD97P__)
+extern void UL1D_RF_SetPaApcDac(UMTSBand rf_band, kal_int16 prf, kal_uint8 pa_mode, kal_uint8 vm1, kal_uint8 vm2, kal_uint16 dc2dc_level, kal_uint16 vbias_dac, kal_uint16 apc_dac);
+#elif (defined __MD95__)
+extern void UL1D_RF_SetPaApcDac(UMTSBand rf_band, kal_uint16 idx, kal_uint8 pa_mode, kal_uint8 vm1, kal_uint8 vm2, kal_uint16 dc2dc_level, kal_uint16 vbias_dac, kal_uint16 apc_dac);
+#else
+#error "[ERROR] Invalid MD generation"
+#endif
+extern void UL1D_RF_GetImmediateBSI(kal_uint32 bsi_isb_port, kal_uint32 bsi_addr, kal_uint32 *bsi_data);
+extern void UL1D_RF_SetTxPaOctLevData(UMTSBand rf_band, void* table);
+extern void UL1D_RF_GetPwrDetMeas(kal_uint16 txpwr_set_idx, kal_int16 *txpwr_meas);
+extern void UL1D_RF_SetTxPrachTmCompData(UMTSBand rf_band, void* table);
+extern void UL1D_RF_SetAfcDac(void* table);
+extern void UL1D_RF_SetAfcCap(void* table);
+extern UMTSBand L1_RxUARFCNToFrequencyBand( kal_uint16 uarfcn, kal_bool is_band6_considered );
+extern kal_bool FDD_UL1D_RxMultiCarrier_Check(kal_uint16 *uarfcn_list, kal_uint8 num_uarfcn);
+extern kal_bool FDD_UL1D_TxMultiCarrier_Check(kal_uint16 *uarfcn_list, kal_uint8 num_uarfcn);
+extern kal_uint8 UL1D_RF_CalDataGetBand(UMTSBand rf_band_in_question, kal_bool nvram_init);
+extern kal_uint8 UL1D_RF_UMTSBandToHLB(UMTSBand rf_band);
+extern kal_uint16 UL1D_RF_UL_UARFCN_To_DL_UARFCN(UMTSBand band, kal_uint16 ul_uarfcn);
+
+#if __IS_UL1D_DPD_SUPPORT__
+extern kal_uint32 UL1D_RF_GET_DPD_SUPPORT_BAND( void );
+#endif
+
+#if defined(__UMTS_R8__)
+
+extern void UL1D_RF_SetPathLossRxdTable( UMTSBand rf_band, void* table );
+extern kal_uint8 UL1D_RF_GetCurrRxDLnaStatus(void);
+extern void UL1D_RF_SetTxPaDriftData(UMTSBand rf_band, void* table);
+extern void UL1D_RF_SetRxBandwidth(kal_bool is_5mhz);
+
+//just for META link, UL1 define this function as dummy macro
+#define UL1D_RF_SetPwrCtrlMode(x)
+#else
+extern void UL1D_RF_SetPwrCtrlMode(kal_uint8 mode);
+#endif
+
+#if !IS_HSPA_HWTPC
+extern void UL1D_Meta_HWTPC_Config(kal_uint8 pc_algo, kal_uint8 tpc_used_frame, kal_int16 pini, META_HWTPC_FRAME_INFO* info);
+#else
+extern void UL1D_Meta_HWTPC_Config(META_HWTPC_INFO *info, META_HWTPC_FRAME_INFO* f_info);
+#endif
+extern kal_bool UL1TST_GET_BIT_COUNT(kal_uint32* total_bits, kal_uint32* error_bits);
+extern kal_int8 UL1D_RF_Replace_Gain_Table_for_Cal(kal_uint32 action);
+extern kal_uint8 UL1D_RF_GetCurrRxLnaStatus(void);
+extern kal_uint32 UL1D_RF_GetID(void);
+extern kal_uint32 UL1TST_CAPID_MAX(void);
+extern void UL1D_RF_SetCrystalCap(kal_uint32 cap_no);
+
+extern void UL1T_InitCustomInputData(void);
+extern void UL1T_InitPowerOnCalData(void);
+extern unsigned long UL1D_RF_GetRxDCOC_CW151(void);
+
+extern void UL1D_RF_UpdateNVRAMToSHM(UMTS_RF_POWER_ON_CAL_DATA_T* p_poc_shm,kal_uint8 band_idx,UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T* table);
+
+extern void UL1D_RF_CA_CustomData_Update( U_sUl1dRfCustomInputData *dst );
+extern void UL1D_RF_DynamicSetRfBandSupport( U_sUl1dRfCustomInputData *dst );
+extern void UL1D_RF_UpdateDatabaseTable( void );
+extern void UL1T_InitCalibrationData( void );
+extern void nvram_init_uL1_mipiData(void);
+extern void UL1D_RF_SetPowerOnCalData_ByDefaultCustom( UMTSBand rf_band, const void* table );
+
+#if IS_3G_FDD_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+extern void UL1D_RF_Get_Interference_Freq_Table(UMTS_RF_INTERFERENCE_FREQUENCY_T *ul1d_interference_frequency_table);
+#endif
+
+#if IS_3G_FDD_RX_PATH_SELECTION_SUPPORT
+extern U_sUl1dRfCustomInputData* UL1D_RF_ANT_SEL(ANT_SEL_TYPE antsel );
+extern ANT_SEL_TYPE UL1D_RF_ANT_QUERY(void);
+#endif
+
+
+#if IS_3G_SAR_TX_POWER_BACKOFF_SUPPORT
+extern void nvram_init_uL1_SARBackoffData(void);
+#endif
+
+
+#if IS_3G_TX_POWER_OFFSET_SUPPORT
+extern void UL1D_RF_SetTpoData(kal_uint32 LID, kal_uint8 *buffer );
+extern void nvram_init_uL1_TpoData(void);
+#endif
+
+#if IS_3G_TX_NSFT_POWER_OFFSET_SUPPORT
+extern void UL1D_RF_SetNsftTpoData(kal_uint32 LID, kal_uint8 *buffer );
+extern void nvram_init_uL1_nsftTpoData(void);
+#endif
+
+#if IS_3G_RX_POWER_OFFSET_SUPPORT
+extern void nvram_init_uL1_RpoData(void);
+#endif
+
+#if (IS_3G_VPA_SEL_BY_BAND_SUPPORT)
+extern void nvram_init_uL1_vpaSrcSel(void);
+#endif/*IS_3G_VPA_SEL_BY_BAND_SUPPORT*/
+
+#if IS_3G_DAT_UL1_CUSTOM_SUPPORT
+extern void nvram_init_uL1_datFeatureByRat(void);
+#if !IS_3G_GEN97_DAT_SUPPORT
+extern void nvram_init_uL1_datFeatureByRoute(void);
+extern void nvram_init_uL1_datFeDb(void);
+extern void nvram_init_uL1_mipiDatAEvent(void);
+extern void nvram_init_uL1_mipiDatAData(void);
+extern void nvram_init_uL1_mipiDatBEvent(void);
+extern void nvram_init_uL1_mipiDatBData(void);
+#endif
+#if !IS_3G_UDAT_SUPPORT
+extern const UMTS_CUSTOM_DAT_FE_CAT_A_T UMTS_DAT_CAT_A_DATABASE_SetDefault;
+extern const UMTS_CUSTOM_DAT_FE_CAT_B_T UMTS_DAT_CAT_B_DATABASE_SetDefault;
+extern UMTS_CUSTOM_DAT_FE_DATABASE_T UMTS_DAT_FE_DATABASE_SetDefault;
+#endif
+#if !IS_3G_GEN97_DAT_SUPPORT
+extern const UMTS_CUSTOM_DAT_FE_ROUTE_DATABASE_T UMTS_DAT_FE_ROUTE_DATABASE_SetDefault;
+#endif
+extern UMTS_CUSTOM_DAT_FEATURE_BY_RAT_T UMTS_DAT_FEATURE_BY_RAT_SetDefault;
+
+#if !IS_3G_UDAT_SUPPORT
+extern UMTS_CUSTOM_DAT_FE_DATABASE_T *UMTS_DAT_FE_DATABASE_TABLE_ptr;
+#endif
+#if !IS_3G_GEN97_DAT_SUPPORT
+extern UMTS_CUSTOM_DAT_FE_ROUTE_DATABASE_T *UMTS_DAT_FE_ROUTE_TABLE_ptr;
+#endif
+extern UMTS_CUSTOM_DAT_FEATURE_BY_RAT_T *UMTS_DAT_FEATURE_BY_RAT_ptr;
+
+#if !IS_3G_UDAT_SUPPORT
+extern UMTS_CUSTOM_DAT_FE_DATABASE_T *UMTS_DAT_FE_DATABASE_PCORE_ptr;
+#endif
+#if !IS_3G_GEN97_DAT_SUPPORT
+extern UMTS_CUSTOM_DAT_FE_ROUTE_DATABASE_T *UMTS_DAT_FE_ROUTE_DATABASE_PCORE_ptr;
+#endif
+extern UMTS_CUSTOM_DAT_FEATURE_BY_RAT_T *UMTS_DAT_FEATURE_BY_RAT_PCORE_ptr;
+#endif
+
+#if IS_3G_TAS_UL1_CUSTOM_SUPPORT
+extern void nvram_init_uL1_tasFeatureByRat(void);
+extern void nvram_init_uL1_tasFeatureByRoute(void);
+extern void nvram_init_uL1_tasFeDb(void);
+extern void nvram_init_uL1_mipiTasAEvent(void);
+extern void nvram_init_uL1_mipiTasAData(void);
+extern void nvram_init_uL1_mipiTasBEvent(void);
+extern void nvram_init_uL1_mipiTasBData(void);
+extern void nvram_init_uL1_mipiTasCEvent(void);
+extern void nvram_init_uL1_mipiTasCData(void);
+#if !IS_3G_UTAS_SUPPORT
+extern const UMTS_CUSTOM_TAS_FE_CAT_A_T UMTS_TAS_CAT_A_DATABASE_SetDefault;
+extern const UMTS_CUSTOM_TAS_FE_CAT_B_T UMTS_TAS_CAT_B_DATABASE_SetDefault;
+extern const UMTS_CUSTOM_TAS_FE_CAT_C_T UMTS_TAS_CAT_C_DATABASE_SetDefault;
+extern UMTS_CUSTOM_TAS_FE_DATABASE_T UMTS_TAS_FE_DATABASE_SetDefault;
+#endif
+
+#if IS_3G_GEN97_TAS_SUPPORT
+extern const UMTS_CUSTOM_TAS_FE_ROUTE_DATA_T UMTS_TAS_FE_ROUTE_DATABASE_SetDefault;
+#else
+extern const UMTS_CUSTOM_TAS_FE_ROUTE_DATABASE_T UMTS_TAS_FE_ROUTE_DATABASE_SetDefault;
+#endif
+
+extern UMTS_CUSTOM_TAS_FEATURE_BY_RAT_T UMTS_TAS_FEATURE_BY_RAT_SetDefault;
+#if !IS_3G_UTAS_SUPPORT
+extern UMTS_CUSTOM_TAS_FE_DATABASE_T *UMTS_TAS_FE_DATABASE_TABLE_ptr;
+#endif
+extern UMTS_CUSTOM_TAS_FE_ROUTE_DATABASE_T *UMTS_TAS_FE_ROUTE_TABLE_ptr;
+extern UMTS_CUSTOM_TAS_FEATURE_BY_RAT_T *UMTS_TAS_FEATURE_BY_RAT_ptr;
+#if !IS_3G_UTAS_SUPPORT
+extern UMTS_CUSTOM_TAS_FE_DATABASE_T *UMTS_TAS_FE_DATABASE_PCORE_ptr;
+#endif
+
+#if IS_3G_GEN97_TAS_SUPPORT
+ extern UMTS_CUSTOM_TAS_FE_ROUTE_DATA_T *UMTS_TAS_FE_ROUTE_DATABASE_PCORE_ptr;
+ extern UMTS_CUSTOM_TAS_FE_ROUTE_DATA_T *UMTS_TAS_FE_ROUTE_DATA_TABLE_ptr;
+ extern UMTS_CUSTOM_TAS_FE_ROUTE_DATABASE_T UMTS_TAS_FE_ROUTE_TABLE;
+#else
+ extern UMTS_CUSTOM_TAS_FE_ROUTE_DATABASE_T *UMTS_TAS_FE_ROUTE_DATABASE_PCORE_ptr;
+#endif
+
+extern UMTS_CUSTOM_TAS_FEATURE_BY_RAT_T *UMTS_TAS_FEATURE_BY_RAT_PCORE_ptr;
+#if IS_3G_TAS_TST_SUPPORT
+extern const UMTS_CUSTOM_TAS_TST_FE_ROUTE_DATABASE_T UMTS_TAS_TST_FE_ROUTE_DATABASE_SetDefault;
+extern UMTS_CUSTOM_TAS_TST_FE_ROUTE_DATABASE_T UMTS_TAS_TST_FE_ROUTE_DATABASE_PCORE;
+extern UMTS_CUSTOM_TAS_TST_FE_ROUTE_DATABASE_T *UMTS_TAS_TST_FE_ROUTE_DATABASE_PCORE_ptr;
+extern UMTS_CUSTOM_TAS_TST_FE_ROUTE_DATABASE_T *UMTS_TAS_TST_FE_ROUTE_DATABASE_ptr;
+#endif
+#if IS_3G_TAS_INHERIT_4G_ANT
+kal_bool UL1D_RF_TAS_QUERY_INHERIT_LTE_ANT(LTE_Band lteBand, UMTSBand wcdmaBand, UMTS_CUSTOM_TAS_STATE_E tasState);
+
+extern void nvram_init_uL1_tasInheritLteAnt(void);
+extern void ul1d_rf_tas_inherit_lte_transform_bitmap(const UMTS_CUSTOM_TAS_INHERIT_LTE_BAND_T *src_p, UMTS_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_T *dst_p);
+
+extern const UMTS_CUSTOM_TAS_INHERIT_LTE_BAND_T* const UMTS_TAS_INHERIT_LTE_ANT_TABLE_SetDefault[];
+extern UMTS_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T *UMTS_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_PCORE_ptr;
+
+extern UMTS_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T *UMTS_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_ptr;
+#endif
+#endif
+
+#if IS_3G_UTAS_SUPPORT
+void UL1D_RF_UTAS_Get_Custom_Information(UMTSBand band, UMTS_RF_UTAS_CUSTOM_INFO_T *customInfo_p);
+kal_int8 UL1D_Query_RSCP_Bias_By_Band_and_Ant( MMRFD_ANT_INDEX_TYPE_E ant_idx , UMTSBand band);
+#endif
+
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBandNone_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand1_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand2_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand3_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand4_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand5_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand6_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand7_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand8_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand9_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand10_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand11_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_UMTSBand19_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBandNone_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand1_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand2_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand3_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand4_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand5_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand6_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand7_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand8_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand9_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand10_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand11_SetDefault;
+extern const U_sTEMPAGCOFFSET AGC_PATHLOSS_RXD_UMTSBand19_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBandNone_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand1_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand2_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand3_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand4_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand5_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand6_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand7_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand8_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand9_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand10_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand11_SetDefault;
+extern const U_sRAMPDATA RampData_UMTSBand19_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBandNone_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand1_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand2_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand3_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand4_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand5_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand6_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand7_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand8_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand9_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand10_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand11_SetDefault;
+extern const U_sPAOCTLVLSETTING PaOctLevData_UMTSBand19_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBandNone_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand1_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand2_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand3_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand4_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand5_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand6_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand7_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand8_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand9_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand10_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand11_SetDefault;
+extern const U_sPADRIFTSETTING PaDriftCompData_UMTSBand19_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBandNone_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand1_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand2_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand3_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand4_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand5_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand6_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand7_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand8_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand9_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand10_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand11_SetDefault;
+extern const U_sPARACHTMCOMPDATA RACH_temperature_compensation_UMTSBand19_SetDefault;
+
+#if IS_3G_FDD_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+extern UMTS_RF_INTERFERENCE_FREQUENCY_T UMTS_RF_INTERFERENCE_FREQUENCY_PCORE;
+extern UMTS_RF_INTERFERENCE_FREQUENCY_T *UMTS_RF_INTERFERENCE_FREQUENCY_PCORE_ptr;
+extern UMTS_RF_INTERFERENCE_FREQUENCY_T *UMTS_RF_INTERFERENCE_FREQUENCY_ptr;
+#endif
+
+#if IS_3G_RF_FPGA_L1S_BRINGUP
+extern void UL1D_MMRF_PcoreUpdate2SHM_ByDefaultCustom(void);
+extern void UL1D_MMRF_PCoreSHMDataInit(void);
+#endif
+
+extern const U_sRAMPDATA DPD_RampData_UMTSBandNone_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand1_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand2_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand3_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand4_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand5_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand6_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand7_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand8_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand9_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand10_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand11_SetDefault;
+extern const U_sRAMPDATA DPD_RampData_UMTSBand19_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBandNone_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand1_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand2_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand3_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand4_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand5_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand6_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand7_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand8_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand9_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand10_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand11_SetDefault;
+extern const U_sPAOCTLVLSETTING DPD_PaOctLevData_UMTSBand19_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBandNone_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand1_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand2_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand3_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand4_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand5_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand6_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand7_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand8_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand9_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand10_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand11_SetDefault;
+extern const U_sDPD_COMMON_CTRL DPD_CommonCtrlData_UMTSBand19_SetDefault;
+#if __IS_UL1D_DPD_SUPPORT__
+void nvram_init_uL1_dpdData(void);
+#endif
+
+#if __IS_UL1D_ETM_SUPPORT__
+extern void nvram_init_uL1_mipiEtmData(void);
+#endif // #if __IS_UL1D_ETM_SUPPORT__
+
+#if IS_3G_RFEQ_COEF_SUBBAND_SUPPORT
+extern void nvram_init_uL1_rfeqCoefData(void);
+#endif
+
+#if (IS_3G_RFEQ_REAL_COEF_TEST)
+extern void nvram_init_uL1_rfeqRealCoefCustom(void);
+#endif
+
+#endif /* End of #ifndef UL1D_RF_PUBLIC_H */
+
diff --git a/mcu/interface/l1/ul1/external/wdata.c b/mcu/interface/l1/ul1/external/wdata.c
new file mode 100644
index 0000000..7fe043d
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/wdata.c
@@ -0,0 +1,1145 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * wdata.c
+ *
+ * Project:
+ * --------
+ * MT6268
+ *
+ * Description:
+ * ------------
+ * Variables/Arrays for customer to make their own configurations.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *----------------------------------------------------------------------------
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+ *----------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*===============================================================================*/
+#include "kal_general_types.h"
+
+#include "ul1d_rf_public.h"
+#include "ul1d_rf_common.h"
+#include "ul1d_rf_cid.h"
+#include "ul1cal.h"
+#include "mml1_dpd_def.h"
+/*===============================================================================*/
+
+#if defined(__MTK_TARGET__)
+
+#define __ATTRIBUTE_SECTION__(_s) __attribute__ ((section(#_s)))
+#define __ATTRIBUTE_ALIGNED__(_a) __attribute__ ((aligned((_a))))
+#define __ATTRIBUTE_ZI__ __attribute__ ((zero_init))
+
+#else
+
+#define __ATTRIBUTE_SECTION__(_s)
+#define __ATTRIBUTE_ALIGNED__(_a)
+#define __ATTRIBUTE_ZI__
+
+#endif
+
+#define __SECTION_INTSRAM_RODATA__ //Removed due to AutoTCM __ATTRIBUTE_SECTION__(INTSRAM_RODATA)
+/* #define __SECTION_INTSRAM_ROCODE__ //Removed due to AutoTCM __ATTRIBUTE_SECTION__(INTSRAM_ROCODE) */ /* remove after tk6291 */
+#define __SECTION_INTSRAM_ZI__ //Removed due to AutoTCM __ATTRIBUTE_SECTION__(INTSRAM_ZI)
+#define __SECTION_INTSRAM_RW__ //Removed due to AutoTCM __ATTRIBUTE_SECTION__(INTSRAM_RW)
+
+#define __SECTION_NONCACHEDZI__ __ATTRIBUTE_SECTION__(NONCACHEDZI) __ATTRIBUTE_ZI__
+#define __SECTION_NONCACHEDRW__ __ATTRIBUTE_SECTION__(NONCACHEDRW)
+
+#define __SECTION_DYNAMICCACHEABLEZI_C__ __ATTRIBUTE_SECTION__(DYNAMICCACHEABLEZI_C) __ATTRIBUTE_ZI__
+
+
+#define MAX_DIST(m,n) (((m)>(n))?(m):(n))
+#define MIN_DIST(m,n) (((m)<(n))?(m):(n))
+
+//BPI timing default invalid zero definition for l1core. MUST to be defined in ul1d_custom_rf.h in pcore
+#ifndef TC_PR1
+#define TC_PR1 0
+#endif
+#ifndef TC_PR2
+#define TC_PR2 0
+#endif
+#ifndef TC_PR3
+#define TC_PR3 0
+#endif
+#ifndef TC_PT1
+#define TC_PT1 0
+#endif
+#ifndef TC_PT2
+#define TC_PT2 0
+#endif
+#ifndef TC_PT3
+#define TC_PT3 0
+#endif
+
+kal_uint16 max_offset = 0; /*MAX_OFFSET*/
+__SECTION_INTSRAM_RW__
+kal_uint16 vm_offset = 0; /*(MAX_OFFSET - VM_OFFSET)*/
+kal_uint16 vbias_offset = 0; /*(MAX_OFFSET - VBIAS_OFFSET)*/
+kal_uint16 dc2dc_offset = 0; /*(MAX_OFFSET - DC2DC_OFFSET)*/
+kal_uint16 vga_offset = 0; /*(MAX_OFFSET - VGA_OFFSET)*/
+
+#ifdef __GNUC__ //These are GCC specific pragmas
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wtautological-compare"
+#endif
+/*Notes: due to use SR(T)1,PR(T)1,SR(T)3,PR(T)3 for max and min distance calculating, which is
+ used for the RF timer setting, so must make sure the SR1,PR1 must larger than other
+ event timing, and PT1,ST1 is smaller than other event timing, even in ul1d_custom_rf.h
+ you can set like SR2>SR1 */
+#define MAX_RX_START_OFFSET MAX_DIST(TC_SR1, TC_PR1)
+#define MAX_TX_START_OFFSET MAX_DIST(TC_ST1, TC_PT1)
+#define MAX_RX_END_OFFSET MAX_DIST(TC_SR3, TC_PR3A)
+#define MAX_TX_END_OFFSET MAX_DIST(TC_ST3, TC_PT3A)
+#define MIN_RX_END_OFFSET MIN_DIST(TC_SR3, TC_PR3)
+#define MIN_TX_END_OFFSET MIN_DIST(TC_ST3, TC_PT3)
+
+#define MAX_MODE_START_OFFSET MAX_DIST(TC_SR2B, TC_ST2C)
+
+kal_int16 max_rx_start_offset = MAX_RX_START_OFFSET;
+kal_int16 max_tx_start_offset = MAX_TX_START_OFFSET;
+
+kal_int16 max_txcal_start_offset = TC_ST_CAL;
+
+kal_int16 max_rx_end_offset = MAX_RX_END_OFFSET;
+kal_int16 max_tx_end_offset = MAX_TX_END_OFFSET;
+
+kal_int16 min_rx_end_offset = MIN_RX_END_OFFSET;
+
+kal_int16 min_tx_end_offset = MIN_TX_END_OFFSET;
+
+kal_uint8 max_rx_end_reg_idx;
+kal_int16 min_rx_off_evt_cancel_margin;
+
+//Add for R8 to support RXD and Dual cell
+kal_int16 max_rx_dc_reconfig_offset = TC_DC_SR1;
+kal_int16 max_rxd_start_offset = MAX_DIST(TC_RXD_SR1, TC_PR1_2);
+kal_int16 min_rxd_end_offset = MIN_DIST(TC_RXD_SR3, TC_PR3_2);
+//kal_int16 max_rxd_start_offset = MAX_DIST(TC_RXD_SR1, TC_PR1);
+//kal_int16 min_rxd_end_offset = MIN_DIST(TC_RXD_SR3, TC_PR3)
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#if IS_3G_MIPI_SUPPORT
+kal_uint16 ul1_mipi_offset = 0; /*(MAX_OFFSET - MIPI_OFFSET)*/
+kal_bool is_3g_mipi_enable = KAL_TRUE;
+#endif
+
+kal_bool is_3g_pga_ab_k_enable = KAL_TRUE;
+
+kal_uint8 pa_section = 3;
+
+#if IS_URF_COLUMBUS
+kal_int32 UMTS_RX_TQ_UCNT_TABLE[3] =
+{
+ -TC_SR1_UCNT,
+ -TC_SR2_UCNT,
+ TC_SR3_UCNT
+};
+
+kal_int32 UMTS_TX_TQ_UCNT_TABLE[3] =
+{
+ -TC_ST1_UCNT,
+ -TC_ST2_UCNT,
+ TC_ST3_UCNT
+};
+
+kal_int32 UMTS_RX_OFF2ON_TQ_UCNT_TABLE[3] =
+{
+ -TC_DC_SR1_UCNT,
+ -TC_DC_SR2_UCNT,
+ -TC_DC_SR2B_UCNT,
+};
+#endif
+
+kal_int16 UMTS_RX_START_TQ_TABLE[6] =
+{
+ /* TQ_SLOT_BEGIN(i) + */ -TC_SR1,
+ /* TQ_SLOT_BEGIN(i) + */ -TC_SR2,
+ /* TQ_SLOT_BEGIN(i) + */ -TC_SR2B,
+ /* TQ_SLOT_BEGIN(i) + */ -TC_PR1,
+ /* TQ_SLOT_BEGIN(i) + */ -TC_PR2,
+ /* TQ_SLOT_BEGIN(i) + */ -TC_PR2B
+};
+
+
+kal_int16 UMTS_RX_END_TQ_TABLE[3] =
+{
+ /* TQ_SLOT_BEGIN(i) + */ TC_SR3,
+ /* TQ_SLOT_BEGIN(i) + */ TC_PR3,
+ /* TQ_SLOT_BEGIN(i) + */ TC_PR3A
+};
+
+
+kal_int16 UMTS_TX_START_TQ_TABLE[7] =
+{
+ /* TQ_SLOT_BEGIN(i) + */ -TC_ST1,
+ /* TQ_SLOT_BEGIN(i) + */ -TC_ST2,
+ /* TQ_SLOT_BEGIN(i) + */ -TC_ST2B,
+ /* TQ_SLOT_BEGIN(i) + */ -TC_ST2C,
+ /* TQ_SLOT_BEGIN(i) + */ -TC_PT1,
+ /* TQ_SLOT_BEGIN(i) + */ -TC_PT2,
+ /* TQ_SLOT_BEGIN(i) + */ -TC_PT2B
+};
+
+kal_int16 UMTS_TX_END_TQ_TABLE[3] =
+{
+ /* TQ_SLOT_BEGIN(i) + */ TC_ST3,
+ /* TQ_SLOT_BEGIN(i) + */ TC_PT3,
+ /* TQ_SLOT_BEGIN(i) + */ TC_PT3A
+};
+
+//Add following table to support RXD and Dual Cell
+kal_int16 UMTS_RX_OFF2ON_TQ_TABLE[3] =
+{
+ -TC_DC_SR1,
+ -TC_DC_SR2,
+ -TC_DC_SR2B,
+};
+
+#if IS_RF_RXD_SUPPORT
+kal_int16 UMTS_RXD_START_TQ_TABLE[7] =
+{
+ -TC_RXD_SR1,
+ -TC_PR1,
+ -TC_PR2,
+ -TC_PR2B,
+ -TC_PR1_2,
+ -TC_PR2_2,
+ -TC_PR2B_2
+};
+
+kal_int16 UMTS_RXD_END_TQ_TABLE[5] =
+{
+ TC_RXD_SR3,
+ TC_PR3,
+ TC_PR3A,
+ TC_PR3_2,
+ TC_PR3A_2
+};
+#endif
+
+
+#if IS_3G_REMOVE_MIPI
+//Notes: UMTS_PDATA_TABLE is used to determine which pin is for Rx and which pin is for Tx
+// so can't put other data except BPI here
+BPI_data_type UMTS_PDATA_TABLE[UL1D_RF_CUSTOM_BAND][2][5] =
+{ /* FrequencyBand0 */
+ { { PDATA_BAND1_PR1, PDATA_BAND1_PR2, PDATA_BAND1_PR2B, PDATA_BAND1_PR3, PDATA_BAND1_PR3A } , /* RX */
+ { PDATA_BAND1_PT1, PDATA_BAND1_PT2, PDATA_BAND1_PT2B, PDATA_BAND1_PT3, PDATA_BAND1_PT3A } , /* TX */
+ }, /* FrequencyBand1 */
+ { { PDATA_BAND1_PR1, PDATA_BAND1_PR2, PDATA_BAND1_PR2B, PDATA_BAND1_PR3, PDATA_BAND1_PR3A } , /* RX */
+ { PDATA_BAND1_PT1, PDATA_BAND1_PT2, PDATA_BAND1_PT2B, PDATA_BAND1_PT3, PDATA_BAND1_PT3A } , /* TX */
+ }, /* FrequencyBand2 */
+ { { PDATA_BAND2_PR1, PDATA_BAND2_PR2, PDATA_BAND2_PR2B, PDATA_BAND2_PR3, PDATA_BAND2_PR3A } , /* RX */
+ { PDATA_BAND2_PT1, PDATA_BAND2_PT2, PDATA_BAND2_PT2B, PDATA_BAND2_PT3, PDATA_BAND2_PT3A } , /* TX */
+ }, /* FrequencyBand4 */
+ { { PDATA_BAND4_PR1, PDATA_BAND4_PR2, PDATA_BAND4_PR2B, PDATA_BAND4_PR3, PDATA_BAND4_PR3A } , /* RX */
+ { PDATA_BAND4_PT1, PDATA_BAND4_PT2, PDATA_BAND4_PT2B, PDATA_BAND4_PT3, PDATA_BAND4_PT3A } , /* TX */
+ }, /* FrequencyBand5 */
+ { { PDATA_BAND5_PR1, PDATA_BAND5_PR2, PDATA_BAND5_PR2B, PDATA_BAND5_PR3, PDATA_BAND5_PR3A } , /* RX */
+ { PDATA_BAND5_PT1, PDATA_BAND5_PT2, PDATA_BAND5_PT2B, PDATA_BAND5_PT3, PDATA_BAND5_PT3A } , /* TX */
+ }, /* FrequencyBand8 */
+ { { PDATA_BAND8_PR1, PDATA_BAND8_PR2, PDATA_BAND8_PR2B, PDATA_BAND8_PR3, PDATA_BAND8_PR3A } , /* RX */
+ { PDATA_BAND8_PT1, PDATA_BAND8_PT2, PDATA_BAND8_PT2B, PDATA_BAND8_PT3, PDATA_BAND8_PT3A } , /* TX */
+ },
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ { { PDATA_BAND6_PR1, PDATA_BAND6_PR2, PDATA_BAND6_PR2B, PDATA_BAND6_PR3, PDATA_BAND6_PR3A } , /* RX */
+ { PDATA_BAND6_PT1, PDATA_BAND6_PT2, PDATA_BAND6_PT2B, PDATA_BAND6_PT3, PDATA_BAND6_PT3A } , /* TX */
+ },
+ { { PDATA_BAND11_PR1, PDATA_BAND11_PR2, PDATA_BAND11_PR2B, PDATA_BAND11_PR3, PDATA_BAND11_PR3A } , /* RX */
+ { PDATA_BAND11_PT1, PDATA_BAND11_PT2, PDATA_BAND11_PT2B, PDATA_BAND11_PT3, PDATA_BAND11_PT3A } , /* TX */
+ },
+ { { PDATA_BAND19_PR1, PDATA_BAND19_PR2, PDATA_BAND19_PR2B, PDATA_BAND19_PR3, PDATA_BAND19_PR3A } , /* RX */
+ { PDATA_BAND19_PT1, PDATA_BAND19_PT2, PDATA_BAND19_PT2B, PDATA_BAND19_PT3, PDATA_BAND19_PT3A } , /* TX */
+ },
+#endif
+};
+
+BPI_data_type UMTS_PDATA_TABLE_H[UL1D_RF_CUSTOM_BAND][2][5] =
+{ /* FrequencyBand0 */
+ { { 0, 0, 0, 0, 0 } , /* RX */
+ { 0, 0, 0, 0, 0 } , /* TX */
+ }, /* FrequencyBand1 */
+ { { 0, 0, 0, 0, 0 } , /* RX */
+ { 0, 0, 0, 0, 0 } , /* TX */
+ }, /* FrequencyBand2 */
+ { { 0, 0, 0, 0, 0 } , /* RX */
+ { 0, 0, 0, 0, 0 } , /* TX */
+ }, /* FrequencyBand4 */
+ { { 0, 0, 0, 0, 0 } , /* RX */
+ { 0, 0, 0, 0, 0 } , /* TX */
+ }, /* FrequencyBand5 */
+ { { 0, 0, 0, 0, 0 } , /* RX */
+ { 0, 0, 0, 0, 0 } , /* TX */
+ }, /* FrequencyBand8 */
+ { { 0, 0, 0, 0, 0 } , /* RX */
+ { 0, 0, 0, 0, 0 } , /* TX */
+ },
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ { { 0, 0, 0, 0, 0 } , /* RX */
+ { 0, 0, 0, 0, 0 } , /* TX */
+ },
+ { { 0, 0, 0, 0, 0 } , /* RX */
+ { 0, 0, 0, 0, 0 } , /* TX */
+ },
+ { { 0, 0, 0, 0, 0 } , /* RX */
+ { 0, 0, 0, 0, 0 } , /* TX */
+ },
+#endif
+};
+
+
+//Notes: UMTS_PDATA2_TABLE is used to determine which pin is for RXD
+// so can't put other data except BPI here
+
+BPI_data_type UMTS_PDATA2_RX_TABLE[UL1D_RF_CUSTOM_BAND][5] =
+{ /* FrequencyBand0 */
+ { PDATA2_BAND1_PR1, PDATA2_BAND1_PR2, PDATA2_BAND1_PR2B, PDATA2_BAND1_PR3, PDATA2_BAND1_PR3A } , /* RX */
+ /* FrequencyBand1 */
+ { PDATA2_BAND1_PR1, PDATA2_BAND1_PR2, PDATA2_BAND1_PR2B, PDATA2_BAND1_PR3, PDATA2_BAND1_PR3A } , /* RX */
+ /* FrequencyBand2 */
+ { PDATA2_BAND2_PR1, PDATA2_BAND2_PR2, PDATA2_BAND2_PR2B, PDATA2_BAND2_PR3, PDATA2_BAND2_PR3A } , /* RX */
+ /* FrequencyBand4 */
+ { PDATA2_BAND4_PR1, PDATA2_BAND4_PR2, PDATA2_BAND4_PR2B, PDATA2_BAND4_PR3, PDATA2_BAND4_PR3A } , /* RX */
+ /* FrequencyBand5 */
+ { PDATA2_BAND5_PR1, PDATA2_BAND5_PR2, PDATA2_BAND5_PR2B, PDATA2_BAND5_PR3, PDATA2_BAND5_PR3A } , /* RX */
+ /* FrequencyBand8 */
+ { PDATA2_BAND8_PR1, PDATA2_BAND8_PR2, PDATA2_BAND8_PR2B, PDATA2_BAND8_PR3, PDATA2_BAND8_PR3A } , /* RX */
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ { PDATA2_BAND6_PR1, PDATA2_BAND6_PR2, PDATA2_BAND6_PR2B, PDATA2_BAND6_PR3, PDATA2_BAND6_PR3A } , /* RX */
+ { PDATA2_BAND11_PR1, PDATA2_BAND11_PR2, PDATA2_BAND11_PR2B, PDATA2_BAND11_PR3, PDATA2_BAND11_PR3A } , /* RX */
+ { PDATA2_BAND19_PR1, PDATA2_BAND19_PR2, PDATA2_BAND19_PR2B, PDATA2_BAND19_PR3, PDATA2_BAND19_PR3A } , /* RX */
+#endif
+};
+
+BPI_data_type UMTS_PDATA2_RX_TABLE_H[UL1D_RF_CUSTOM_BAND][5] =
+{ /* FrequencyBand0 */
+ { 0, 0, 0, 0, 0 } , /* RX */
+ /* FrequencyBand1 */
+ { 0, 0, 0, 0, 0 } , /* RX */
+ /* FrequencyBand2 */
+ { 0, 0, 0, 0, 0 } , /* RX */
+ /* FrequencyBand4 */
+ { 0, 0, 0, 0, 0 } , /* RX */
+ /* FrequencyBand5 */
+ { 0, 0, 0, 0, 0 } , /* RX */
+ /* FrequencyBand8 */
+ { 0, 0, 0, 0, 0 } , /* RX */
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ /* FrequencyBand8 */
+ { 0, 0, 0, 0, 0 } , /* RX */
+ /* FrequencyBand8 */
+ { 0, 0, 0, 0, 0 } , /* RX */
+ /* FrequencyBand8 */
+ { 0, 0, 0, 0, 0 } , /* RX */
+#endif/*IS_3G_SUPPORT_8_BANDINDICATOR*/
+};
+#else
+//Useless after Gen97
+#endif
+
+#if (IS_3G_TAS_ANTENNA_IDX_ON_TEST_SIM)
+UMTS_TAS_ANT_IDX_T UMTS_TAS_ANT_IDX_by_band;
+#endif
+
+kal_uint8 DC2DC[3/*pa_mode*/] =
+{
+ DC2DC_H,
+ DC2DC_M,
+ DC2DC_L
+};
+
+kal_uint8 VM_data[3/*pa_mode*/] =
+{
+ VM_H,
+ VM_M,
+ VM_L
+};
+
+#if IS_3G_REMOVE_MIPI
+/* mtk02653: For checking the notch tuning scenario (cases) */
+/* and also checking whether wrong customer setting exists. */
+UL1_RF_RX_IO_E band1_ch_sel = BAND1_CHANNEL_SEL;
+UL1_RF_RX_IO_E band2_ch_sel = BAND2_CHANNEL_SEL;
+UL1_RF_RX_IO_E band3_ch_sel = BAND3_CHANNEL_SEL;
+UL1_RF_RX_IO_E band4_ch_sel = BAND4_CHANNEL_SEL;
+
+UL1_RF_RX_IO_E band5_ch_sel = BAND5_CHANNEL_SEL;
+UL1_RF_RX_IO_E band6_ch_sel = BAND6_CHANNEL_SEL;
+UL1_RF_RX_IO_E band8_ch_sel = BAND8_CHANNEL_SEL;
+UL1_RF_RX_IO_E band9_ch_sel = BAND9_CHANNEL_SEL;
+UL1_RF_RX_IO_E band10_ch_sel = BAND10_CHANNEL_SEL;
+UL1_RF_RX_IO_E band11_ch_sel = BAND10_CHANNEL_SEL;
+UL1_RF_RX_IO_E band19_ch_sel = BAND19_CHANNEL_SEL;
+
+#if IS_RF_RXD_SUPPORT
+UL1_RF_RXD_IO_E band1_ch2_sel = BAND1_CHANNEL2_SEL;
+UL1_RF_RXD_IO_E band2_ch2_sel = BAND2_CHANNEL2_SEL;
+UL1_RF_RXD_IO_E band3_ch2_sel = BAND3_CHANNEL2_SEL;
+UL1_RF_RXD_IO_E band4_ch2_sel = BAND4_CHANNEL2_SEL;
+UL1_RF_RXD_IO_E band5_ch2_sel = BAND5_CHANNEL2_SEL;
+UL1_RF_RXD_IO_E band6_ch2_sel = BAND6_CHANNEL2_SEL;
+UL1_RF_RXD_IO_E band8_ch2_sel = BAND8_CHANNEL2_SEL;
+UL1_RF_RXD_IO_E band9_ch2_sel = BAND9_CHANNEL2_SEL;
+UL1_RF_RXD_IO_E band10_ch2_sel = BAND10_CHANNEL2_SEL;
+UL1_RF_RXD_IO_E band11_ch2_sel = BAND11_CHANNEL2_SEL;
+UL1_RF_RXD_IO_E band19_ch2_sel = BAND19_CHANNEL2_SEL;
+#endif
+#else
+//Useless after Gen97
+#endif
+
+kal_bool pmu_pasetting = KAL_TRUE;
+kal_bool ultra_low_cost= KAL_FALSE;
+kal_bool TM_enable = TEAMPERATURE_MEAS_EN;
+kal_bool VPA_mode_setting = KAL_FALSE;
+
+#if defined (__UMTS_R8__)
+/** [20130429 LY] replace 0xFFFFFFFF by custom setting to avoid false alarm of cal. data download */
+//Should be quered by Band, customize in rf_custim.h to indicate support of RXD
+kal_uint32 rxd_support_mask = 0x0;
+
+kal_uint32 rx_diversity_always_on = KAL_FALSE;
+kal_uint32 pa_dirft_bitmap = 0x0;
+#endif
+
+kal_bool is_band5_and_band6_indicator = KAL_FALSE;
+#if IS_3G_B5_AND_B19_INDICATOR_SUPPORT
+kal_bool is_band5_and_band19_indicator = KAL_FALSE;
+kal_bool is_disable_band5_indicator = KAL_FALSE;
+#endif
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+kal_uint8 ul1d_BandInfo[MAX_SUPPORTED_BAND_INDEX] ={ UMTSBand1,
+ UMTSBand2,
+ UMTSBand4,
+ UMTSBand5,
+ UMTSBand8,
+ UMTSBandNone,
+ UMTSBandNone,
+ UMTSBandNone};
+kal_uint32 band_info_debug = 0;
+#else
+kal_uint8 ul1d_BandInfo[5] ={ UMTSBand1,
+ UMTSBand2,
+ UMTSBand4,
+ UMTSBand5,
+ UMTSBand8};
+#endif // IS_3G_SUPPORT_8_BANDINDICATOR
+
+kal_uint32 ul1d_CaBandInfo[UMTS_RF_CA_FE_NUM_MAX] = {0};
+UMTS_FE_ROUTE_TABLE_T UMTS_FE_ROUTE_TBL[UMTS_RF_FRONT_END_NUM_MAX] =
+{
+ {0, 0, {{0}}}
+};
+
+UMTS_RX_ROUTE_TABLE_T UMTS_RX_ROUTE_TBL[UMTS_ROUTE_TBL_SIZE_MAX] =
+{
+ {0, {{0}}, {0}, 0, 0, 0, 0}
+};
+
+UMTS_TX_ROUTE_TABLE_T UMTS_TX_ROUTE_TBL[UMTS_ROUTE_TBL_SIZE_MAX] =
+{
+ {0, {{0}}, {0}, 0, 0}
+};
+
+UMTS_RX_COMP_ROUTE_TABLE_T UMTS_RX_COMP_ROUTE_TBL[UMTS_ROUTE_TBL_SIZE_MAX] = {0};
+UMTS_TX_COMP_ROUTE_TABLE_T UMTS_TX_COMP_ROUTE_TBL[UMTS_ROUTE_TBL_SIZE_MAX] = {0};
+
+UMTS_USAGE_DES_T UMTS_USAGE_TBL[UMTS_USAGE_TBL_SIZE_MAX] =
+{
+ {{0}, {0}, 0, {0}}
+};
+
+#if IS_3G_REMOVE_MIPI
+UL1_RF_TX_IO_E band_output_sel[20]={TX_NULL_BAND,
+ BAND1_OUTPUT_SEL,
+ BAND2_OUTPUT_SEL,
+ BAND3_OUTPUT_SEL,
+ BAND4_OUTPUT_SEL,
+ BAND5_OUTPUT_SEL,
+ BAND6_OUTPUT_SEL,
+ TX_NULL_BAND,
+ BAND8_OUTPUT_SEL,
+ BAND9_OUTPUT_SEL,
+ BAND10_OUTPUT_SEL,
+ BAND11_OUTPUT_SEL,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ BAND19_OUTPUT_SEL};
+
+UL1_RF_TX_DET_IO_E band_output_det_sel[20]={TX_NULL_BAND,
+ BAND1_OUTPUT_DET_SEL,
+ BAND2_OUTPUT_DET_SEL,
+ BAND3_OUTPUT_DET_SEL,
+ BAND4_OUTPUT_DET_SEL,
+ BAND5_OUTPUT_DET_SEL,
+ BAND6_OUTPUT_DET_SEL,
+ TX_NULL_BAND,
+ BAND8_OUTPUT_DET_SEL,
+ BAND9_OUTPUT_DET_SEL,
+ BAND10_OUTPUT_DET_SEL,
+ BAND11_OUTPUT_DET_SEL,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ TX_NULL_BAND,
+ BAND19_OUTPUT_DET_SEL};
+
+#else
+//Useless after Gen97
+#endif
+
+kal_bool is_rf_setting_by_nvram = KAL_TRUE;
+kal_bool is_rfic_bsi_port_swap = KAL_FALSE;
+
+#if IS_3G_GEN97_TAS_SUPPORT
+UMTS_CUSTOM_TAS_FE_ROUTE_DATABASE_T UMTS_TAS_FE_ROUTE_TABLE = {{{0}}};
+#endif
+
+/* mtk02653: */
+/* Pre-processing compiler option concerning to supported RF band mode */
+/* to see if there is any wrong customer configurations. */
+
+#if IS_PCORE_HANDLE
+/*------------- Single Software Load for Multiple Components Compatible -------------*/
+kal_uint8 ul1custom_debug_enable = UL1CUSTOM_DEBUG_ENABLE;
+kal_uint8 ul1custom_gpio_set_nums = UL1CUSTOM_GPIO_SET_NUMS;
+kal_uint8 ul1custom_adc_set_nums = UL1CUSTOM_ADC_SET_NUMS;
+kal_uint8 ul1custom_nvram_barcode_set_nums = UL1CUSTOM_NVRAM_BARCODE_SET_NUMS;
+kal_uint8 ul1custom_gpio_nums_in_calc = UL1CUSTOM_GPIO_NUMS_IN_CALC;
+kal_uint8 ul1custom_ADC_nums_in_calc = UL1CUSTOM_ADC_NUMS_IN_CALC;
+kal_uint8 ul1custom_nvram_barcode_nums_in_calc = UL1CUSTOM_NVRAM_BARCODE_NUMS_IN_CALC;
+kal_uint8 ul1custom_first_index = UL1CUSTOM_FIRST_INDEX;
+kal_uint8 ul1custom_second_index = UL1CUSTOM_SECOND_INDEX;
+kal_uint8 ul1custom_third_index = UL1CUSTOM_THIRD_INDEX;
+kal_uint8 ul1custom_first_index_base = UL1CUSTOM_FIRST_INDEX_BASE;
+kal_uint8 ul1custom_gpio_num_of_detect_pins_in_use = UL1CUSTOM_GPIO_NUM_OF_DETECT_PINS_IN_USE;
+kal_uint8 ul1custom_adc_level_total = UL1CUSTOM_ADC_LEVEL_TOTAL;
+kal_uint8 ul1custom_barcode_read_digit_num = UL1CUSTOM_BARCODE_READ_DIGIT_NUM;
+kal_uint8 ul1custom_barcode_digit_value_1 = UL1CUSTOM_BARCODE_DIGIT_VALUE_1;
+kal_uint8 ul1custom_barcode_digit_value_2 = UL1CUSTOM_BARCODE_DIGIT_VALUE_2;
+kal_uint8 ul1custom_barcode_digit_value_3 = UL1CUSTOM_BARCODE_DIGIT_VALUE_3;
+kal_uint8 ul1custom_max_rf_support_band_num = UL1CUSTOM_MAX_RF_SUPPORT_BAND_NUM;
+kal_uint8 ul1custom_adc_calibrate_enable = UL1CUSTOM_ADC_CALIBARTE_ENABLE;
+kal_uint8 ul1custom_adc_bits = UL1CUSTOM_ADC_BITS;
+kal_uint16 ul1custom_adc_meas_count_2_order = UL1CUSTOM_ADC_MEAS_COUNT_2_ORDER;
+kal_uint16 ul1custom_total_set_nums = UL1CUSTOM_TOTAL_SET_NUMS;
+kal_uint32 ul1custom_adc_max_input_voltage = UL1CUSTOM_ADC_MAX_INPUT_VOLTAGE;
+/*------------- Single Software Load for Multiple Components Compatible -------------*/
+#else
+/*------------- Single Software Load for Multiple Components Compatible -------------*/
+kal_uint8 ul1custom_debug_enable = 0;
+kal_uint8 ul1custom_gpio_set_nums = 0;
+kal_uint8 ul1custom_adc_set_nums = 0;
+kal_uint8 ul1custom_nvram_barcode_set_nums = 0;
+kal_uint8 ul1custom_gpio_nums_in_calc = 0;
+kal_uint8 ul1custom_ADC_nums_in_calc = 0;
+kal_uint8 ul1custom_nvram_barcode_nums_in_calc = 0;
+kal_uint8 ul1custom_first_index = 0;
+kal_uint8 ul1custom_second_index = 0;
+kal_uint8 ul1custom_third_index = 0;
+kal_uint8 ul1custom_first_index_base = 0;
+kal_uint8 ul1custom_gpio_num_of_detect_pins_in_use = 0;
+kal_uint8 ul1custom_adc_level_total = 0;
+kal_uint8 ul1custom_barcode_read_digit_num = 0;
+kal_uint8 ul1custom_barcode_digit_value_1 = 0;
+kal_uint8 ul1custom_barcode_digit_value_2 = 0;
+kal_uint8 ul1custom_barcode_digit_value_3 = 0;
+kal_uint8 ul1custom_max_rf_support_band_num = 0;
+kal_uint8 ul1custom_adc_calibrate_enable = 0;
+kal_uint8 ul1custom_adc_bits = 0;
+kal_uint16 ul1custom_adc_meas_count_2_order = 0;
+kal_uint16 ul1custom_total_set_nums = 0;
+kal_uint32 ul1custom_adc_max_input_voltage = 0;
+/*------------- Single Software Load for Multiple Components Compatible -------------*/
+#endif
+
+kal_int32 pd_threshold = ((-5)<<5); // Power detection threshold
+
+/** DCXO/VCTCXO switch by difinition of AFC_VCXO, but need to be updated by MMRF API query*/
+#if defined (AFC_VCXO)
+kal_bool ul1d_afc_vcxo_support = KAL_TRUE;
+#else
+kal_bool ul1d_afc_vcxo_support = KAL_FALSE;
+#endif
+
+
+/*********************************************************************/
+/** Custom RF Timing **/
+/*********************************************************************/
+
+kal_int16 ddpc_trigger_offset = (-7);
+kal_int16 meas_sample_offset_5M = (-9);
+kal_int16 wait_sample_offset_5M = (34);
+kal_int16 meas_sample_offset_10M = (0);
+kal_int16 wait_sample_offset_10M = (0);
+kal_int16 adc_off_offset_0 = (3);
+kal_int16 adc_off_offset_1 = (2);
+kal_int16 adc_off_offset_2 = (2);
+
+kal_uint32 tri_sw_lm1 = 50;
+kal_uint32 tri_sw_et1 = 50;
+kal_uint32 tri_sw_dpd = 50;
+kal_uint32 tri_sw_lm2 = 50;
+kal_uint32 tri_sw_et2 = 50;
+
+/*********************************************************************/
+/** Custom RF Data Pointer Structure Declare **/
+/*********************************************************************/
+U_sUl1dRfCustomInputData *UMTS_RF_CUSTOM_INPUT_DATA_ptr;
+
+#if IS_3G_ELNA_IDX_SUPPORT
+UMTS_CUSTOM_ELNA_IDX_T *UMTS_ELNA_IDX_LUT_ptr;
+#endif/*IS_3G_ELNA_IDX_SUPPORT*/
+
+#if IS_3G_FDD_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+UMTS_RF_INTERFERENCE_FREQUENCY_T *UMTS_RF_INTERFERENCE_FREQUENCY_ptr;
+#endif/*IS_3G_FDD_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT*/
+
+#if IS_3G_SAR_TX_POWER_OFFSET_CONDI_SUPPORT
+U_sSARBackoffDATA UMTS_SAR_BACKOFF_TABLE_BACKUP[UL1D_RF_CUSTOM_BAND];
+kal_uint32 TPO_3G_TOTAL_TYPE_NUM = TPO_3G_TABLE_TYPE_NUM;
+#endif
+
+#if IS_3G_SAR_TX_POWER_BACKOFF_SUPPORT
+U_sSARBackoffDATA *UMTS_SAR_BACKOFF_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if IS_3G_TX_POWER_OFFSET_SUPPORT
+U_sTXPOWEROFFSETDATA *UMTS_TX_POWER_OFFSET_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if IS_3G_TX_NSFT_POWER_OFFSET_SUPPORT
+U_sTXNSFTPOWEROFFSETDATA_ALLBAND *UMTS_TX_NSFT_POWER_OFFSET_ptr;
+#endif
+
+#if(IS_3G_RX_POWER_OFFSET_SUPPORT)
+U_sRXPOWEROFFSETDATA *UMTS_RX_POWER_OFFSET_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+#if (IS_3G_VPA_SEL_BY_BAND_SUPPORT)
+UMTS_VPA_SOURCE_TYPE * UMTS_VPA_SRC_SEL_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+/*********************************************************************/
+/** Calibration Data Pointer Structure Declare**/
+/*********************************************************************/
+#if IS_3G_RF_NCCA_SUPPORT
+U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_TABLE[UMTS_AGC_PATHLOSS_TBL_SIZE];
+U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_RXD_TABLE[UMTS_AGC_PATHLOSS_TBL_SIZE]; //RXD path loss
+#else
+U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_TABLE[UL1D_RF_CUSTOM_BAND];
+U_sTEMPAGCOFFSET *U_AGC_PATHLOSS_RXD_TABLE[UL1D_RF_CUSTOM_BAND]; //RXD path loss
+#endif
+U_sRAMPDATA *UMTS_RampData[UL1D_RF_CUSTOM_BAND];
+U_sPAOCTLVLSETTING *U_PA_OCTLEV_TABLE[UL1D_RF_CUSTOM_BAND];
+U_sPARACHTMCOMPDATA *U_PA_RACH_COMP_TABLE[UL1D_RF_CUSTOM_BAND];
+U_sPADRIFTSETTING *U_PA_DRIFT_TABLE[UL1D_RF_CUSTOM_BAND];
+
+#if __IS_UL1D_DPD_SUPPORT__
+U_sDPD_GROUP_ALL *p_U_DPD_GROUP_TABLE[UL1D_RF_CUSTOM_BAND];
+U_sUl1dDpdCustomInputData *UMTS_DPD_CUSTOM_INPUT_DATA_ptr;
+DPD_ENABLE_E *UMTS_DPD_ENABLE_ptr;
+#endif
+
+U_sAFCDACDATA *U_AFC_DAC_ptr;
+U_sAFCCAPDATA *U_AFC_CAP_ptr;
+kal_uint16 *U_TEMP_DAC_ptr;
+
+UMTS_RF_POWER_ON_CAL_DATA_T *U_POC_CAL_DATA_ptr = NULL;
+
+#if IS_3G_TAS_UL1_CUSTOM_SUPPORT
+#if !IS_3G_UTAS_SUPPORT
+UMTS_CUSTOM_TAS_FE_DATABASE_T *UMTS_TAS_FE_DATABASE_TABLE_ptr = NULL;
+#endif
+UMTS_CUSTOM_TAS_FE_ROUTE_DATABASE_T *UMTS_TAS_FE_ROUTE_TABLE_ptr = &UMTS_TAS_FE_ROUTE_TABLE;
+UMTS_CUSTOM_TAS_FEATURE_BY_RAT_T *UMTS_TAS_FEATURE_BY_RAT_ptr = NULL;
+
+#if IS_3G_GEN97_TAS_SUPPORT
+UMTS_CUSTOM_TAS_FE_ROUTE_DATA_T *UMTS_TAS_FE_ROUTE_DATA_TABLE_ptr = NULL; //Gen97 NVRAM+Custom
+#endif
+
+#if IS_3G_TAS_TST_SUPPORT
+UMTS_CUSTOM_TAS_TST_FE_ROUTE_DATABASE_T *UMTS_TAS_TST_FE_ROUTE_DATABASE_ptr = NULL;
+#endif
+#if IS_3G_TAS_INHERIT_4G_ANT
+UMTS_CUSTOM_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_T *UMTS_TAS_INHERIT_LTE_BAND_BITMAP_TABLE_ptr=NULL;
+#endif
+#endif
+
+#if IS_3G_DAT_UL1_CUSTOM_SUPPORT
+#if !IS_3G_UDAT_SUPPORT
+UMTS_CUSTOM_DAT_FE_DATABASE_T *UMTS_DAT_FE_DATABASE_TABLE_ptr = NULL;
+#endif
+#if !IS_3G_GEN97_DAT_SUPPORT
+UMTS_CUSTOM_DAT_FE_ROUTE_DATABASE_T *UMTS_DAT_FE_ROUTE_TABLE_ptr = NULL;
+#endif
+UMTS_CUSTOM_DAT_FEATURE_BY_RAT_T *UMTS_DAT_FEATURE_BY_RAT_ptr = NULL;
+#endif
+
+#if IS_3G_RFEQ_COEF_SUBBAND_SUPPORT
+hs_dsch_rfeq_info_band_T *UMTS_RFEQ_COEF_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
+#if IS_3G_RFEQ_REAL_COEF_TEST
+URXDFE_REAL_RFEQ_CUSTOM_BAND_T *UMTS_RFEQ_REAL_COEF_TABLE[UL1D_RF_CUSTOM_BAND];
+#endif
+
diff --git a/mcu/interface/l1/ul1/external/wdata.h b/mcu/interface/l1/ul1/external/wdata.h
new file mode 100644
index 0000000..9a1e4a6
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/wdata.h
@@ -0,0 +1,377 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * wdata.h
+ *
+ * Project:
+ * --------
+ * MT6268
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *----------------------------------------------------------------------------
+ * removed!
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+ *
+ *
+ *----------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _UL1D_DATA_H_
+#define _UL1D_DATA_H_
+
+/*===============================================================================*/
+#include "kal_general_types.h"
+#include "ul1d_cid.h"
+#include "ul1d_rf_public.h"
+/*===============================================================================*/
+extern kal_int16 max_rx_start_offset;
+extern kal_int16 max_tx_start_offset;
+extern kal_int16 max_txcal_start_offset;
+extern kal_int16 min_rx_end_offset;
+extern kal_int16 min_tx_end_offset;
+
+extern kal_int16 max_rx_end_offset;
+extern kal_int16 max_tx_end_offset;
+
+extern kal_uint8 max_rx_end_reg_idx;
+extern kal_int16 min_rx_off_evt_cancel_margin;
+
+//Add for Support RXD and Dual Cell
+extern kal_int16 max_rx_dc_reconfig_offset;
+extern kal_int16 UMTS_RX_OFF2ON_TQ_TABLE[3];
+
+extern kal_int16 max_rxd_start_offset;
+extern kal_int16 min_rxd_end_offset;
+extern kal_int16 UMTS_RXD_START_TQ_TABLE[7];
+extern kal_int16 UMTS_RXD_END_TQ_TABLE[5];
+extern kal_uint32 rxd_support_mask;
+extern kal_uint32 rx_diversity_always_on;
+extern kal_uint32 pa_dirft_bitmap;
+extern kal_uint16 mpr_backoff_by_service[2];
+extern kal_bool is_rf_setting_by_nvram;
+extern kal_bool is_rfic_bsi_port_swap;
+
+extern kal_uint16 max_offset;
+extern kal_uint16 vm_offset;
+extern kal_uint16 vbias_offset;
+extern kal_uint16 dc2dc_offset;
+extern kal_uint16 vga_offset;
+#if IS_3G_MIPI_SUPPORT
+extern kal_uint16 ul1_mipi_offset;
+extern kal_bool is_3g_mipi_enable;
+#endif
+
+extern kal_bool is_3g_pga_ab_k_enable;
+
+extern kal_bool VPA_mode_setting;
+extern kal_uint8 pa_section;
+extern kal_uint8 DC2DC[3/*pa_mode*/];
+extern kal_uint8 VM_data[3/*pa_mode*/] ;
+
+extern kal_int16 UMTS_RX_START_TQ_TABLE[6];
+extern kal_int16 UMTS_RX_END_TQ_TABLE[3];
+
+extern kal_int16 UMTS_TX_START_TQ_TABLE[7];
+extern kal_int16 UMTS_TX_END_TQ_TABLE[3];
+
+
+extern BPI_data_type UMTS_PDATA_TABLE[UL1D_RF_CUSTOM_BAND][2][5];
+extern BPI_data_type UMTS_PDATA_TABLE_H[UL1D_RF_CUSTOM_BAND][2][5];
+extern BPI_data_type UMTS_PDATA2_RX_TABLE[UL1D_RF_CUSTOM_BAND][5];
+extern BPI_data_type UMTS_PDATA2_RX_TABLE_H[UL1D_RF_CUSTOM_BAND][5];
+
+#if IS_URF_COLUMBUS
+extern kal_int32 UMTS_RX_TQ_UCNT_TABLE[3];
+extern kal_int32 UMTS_TX_TQ_UCNT_TABLE[3];
+extern kal_int32 UMTS_RX_OFF2ON_TQ_UCNT_TABLE[3];
+#endif
+
+/*------------- Single Software Load for Multiple Components Compatible -------------*/
+extern kal_uint8 ul1custom_debug_enable;
+extern kal_uint8 ul1custom_gpio_set_nums;
+extern kal_uint8 ul1custom_adc_set_nums;
+extern kal_uint8 ul1custom_nvram_barcode_set_nums;
+extern kal_uint8 ul1custom_gpio_nums_in_calc;
+extern kal_uint8 ul1custom_ADC_nums_in_calc;
+extern kal_uint8 ul1custom_nvram_barcode_nums_in_calc;
+extern kal_uint8 ul1custom_first_index;
+extern kal_uint8 ul1custom_second_index;
+extern kal_uint8 ul1custom_third_index;
+extern kal_uint8 ul1custom_first_index_base;
+extern kal_uint8 ul1custom_gpio_num_of_detect_pins_in_use;
+extern kal_uint8 ul1custom_adc_level_total;
+extern kal_uint8 ul1custom_barcode_read_digit_num;
+extern kal_uint8 ul1custom_barcode_digit_value_1;
+extern kal_uint8 ul1custom_barcode_digit_value_2;
+extern kal_uint8 ul1custom_barcode_digit_value_3;
+extern kal_uint8 ul1custom_max_rf_support_band_num;
+extern kal_uint8 ul1custom_adc_calibrate_enable;
+extern kal_uint8 ul1custom_adc_bits;
+extern kal_uint16 ul1custom_adc_meas_count_2_order;
+extern kal_uint16 ul1custom_total_set_nums;
+extern kal_uint32 ul1custom_adc_max_input_voltage;
+/*------------- Single Software Load for Multiple Components Compatible -------------*/
+
+extern kal_bool ul1d_afc_vcxo_support;
+extern kal_int32 pd_threshold;
+
+extern kal_int16 ddpc_trigger_offset;
+extern kal_int16 meas_sample_offset_5M;
+extern kal_int16 wait_sample_offset_5M;
+extern kal_int16 meas_sample_offset_10M;
+extern kal_int16 wait_sample_offset_10M;
+extern kal_int16 adc_off_offset_0;
+extern kal_int16 adc_off_offset_1;
+extern kal_int16 adc_off_offset_2;
+
+extern kal_uint32 tri_sw_lm1;
+extern kal_uint32 tri_sw_et1;
+extern kal_uint32 tri_sw_dpd;
+extern kal_uint32 tri_sw_lm2;
+extern kal_uint32 tri_sw_et2;
+
+#endif /* End of #ifndef _UL1D_DATA_H_ */
+
diff --git a/mcu/interface/l1/ul1/external/wdata_pcore.c b/mcu/interface/l1/ul1/external/wdata_pcore.c
new file mode 100644
index 0000000..51b6a09
--- /dev/null
+++ b/mcu/interface/l1/ul1/external/wdata_pcore.c
@@ -0,0 +1,1872 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * wdata.c
+ *
+ * Project:
+ * --------
+ * MT6268
+ *
+ * Description:
+ * ------------
+ * Variables/Arrays for customer to make their own configurations.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *----------------------------------------------------------------------------
+ * removed!
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+ *
+ *----------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*===============================================================================*/
+
+#include "kal_general_types.h"
+
+#include "mml1_dpd_def.h"
+#include "ul1d_rf_public.h"
+#include "ul1d_rf_common.h"
+#include "ul1d_rf_cid.h"
+#include "ul1cal.h"
+
+#if defined(L1_SIM)
+#include "SymWrap.h"
+#endif
+
+#if defined (UMTS_RF_L1SIM)
+#include "umts_custom_rf_sim.h"
+#else
+#if (IS_3G_MIPI_SUPPORT)
+#include "ul1d_custom_mipi.h"
+#endif
+
+#include "ul1d_custom_rf.h"
+#include "wcustomdata.h"
+#include "ul1d_custom_rf_ca.h"
+#if IS_3G_TAS_UL1_CUSTOM_SUPPORT
+#include "ul1d_custom_rf_tas.h"
+#endif
+
+#if IS_3G_DAT_UL1_CUSTOM_SUPPORT
+#include "ul1d_custom_rf_dat.h"
+#endif
+#include "ul1d_rf_cal_poc_data.h"
+
+#if __IS_UL1D_DPD_SUPPORT__
+#include "ul1d_custom_rf_dpd.h"
+#endif
+#endif/*defined(L1_SIM)*/
+
+/*===============================================================================*/
+
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if IS_3G_REMOVE_MIPI
+UMTS_FE_ROUTE_TABLE_T UMTS_FRONT_END_ROUTE_TABLE_PCORE[] =
+{
+ /* Single Band FE Route Table */
+ UMTS_SB_FE_SETTING(RX_BAND_INDICATOR_0, SetDefault),
+ UMTS_SB_FE_SETTING(RX_BAND_INDICATOR_1, SetDefault),
+ UMTS_SB_FE_SETTING(RX_BAND_INDICATOR_2, SetDefault),
+ UMTS_SB_FE_SETTING(RX_BAND_INDICATOR_3, SetDefault),
+ UMTS_SB_FE_SETTING(RX_BAND_INDICATOR_4, SetDefault),
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ UMTS_SB_FE_SETTING(RX_BAND_INDICATOR_5, SetDefault),
+ UMTS_SB_FE_SETTING(RX_BAND_INDICATOR_6, SetDefault),
+ UMTS_SB_FE_SETTING(RX_BAND_INDICATOR_7, SetDefault),
+#endif
+ /* CA Band FE Route Table*/
+ UMTS_CA_FE_SETTING(RX_CABAND_IND_00, SetDefault),
+ UMTS_CA_FE_SETTING(RX_CABAND_IND_01, SetDefault),
+ UMTS_CA_FE_SETTING(RX_CABAND_IND_02, SetDefault),
+ UMTS_CA_FE_SETTING(RX_CABAND_IND_03, SetDefault),
+ UMTS_CA_FE_SETTING(RX_CABAND_IND_04, SetDefault),
+};
+#else
+//Useless after Gen97
+#endif/*IS_3G_REMOVE_MIPI*/
+
+//kevin phase3 for COSIM RF
+/* To fit the case once user who does not use Modem Bin Update tool but modifies makefile/ul1d_custom_rf.h band setting and rebuild */
+#if IS_3G_REMOVE_MIPI
+U_sUl1dRfCustomInputData UMTS_RF_CUSTOM_INPUT_DATA_PCORE =
+{
+ /* Start Pattern */
+ 0x1234ABCD,
+
+ /* Structure Version */
+ 1,
+
+ /* RF Type */
+ UMTS_RF_TYPE,
+
+ /* isDataUpdate */
+ 1,
+
+#if defined (__UL1_HS_PLUS_PLATFORM__)
+ /* proityOfNvramInCustomization */
+ RF_SETTING_BY_NVRAM,
+#endif
+
+ /* umtsRfPaControlTimingOffset */
+ {
+ MAX_OFFSET,
+ VM_OFFSET,
+ VBIAS_OFFSET,
+ DC2DC_OFFSET,
+ VGA_OFFSET
+ },
+
+ /* umtsBsiBpiTiming */
+ {
+ /* RX window end timing */
+ -TC_PR1,
+ -TC_PR2,
+ -TC_PR2B,
+
+ /* RX window end timing */
+ TC_PR3,
+ TC_PR3A,
+
+ /* TX window start timing */
+ -TC_PT1,
+ -TC_PT2,
+ -TC_PT2B,
+
+ /* TX window end timing */
+ TC_PT3,
+ TC_PT3A
+ },
+
+ /* umtsPdata */
+ {
+ /* rxBpi */
+ {
+ /*Band_Ind_0*/
+ {
+ RX_BAND_INDICATOR_0,
+ {
+ M_UMTS_PDATA_PR1(RX_BAND_INDICATOR_0),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_0),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_0), /* PR2b */
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_0),
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_0) /* PR3a */
+ }
+ #if IS_3G_RXD_FE_CONTROL_SUPPORT
+ ,{
+ M_UMTS_PDATA2_PR1(RX_BAND_INDICATOR_0),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_0),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_0), /* PR2b */
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_0),
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_0) /* PR3a */
+ }
+ #endif
+ },
+ /*Band_Ind_1*/
+ {
+ RX_BAND_INDICATOR_1,
+ {
+ M_UMTS_PDATA_PR1(RX_BAND_INDICATOR_1),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_1),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_1), /* PR2b */
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_1),
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_1) /* PR3a */
+ }
+ #if IS_3G_RXD_FE_CONTROL_SUPPORT
+ ,{
+ M_UMTS_PDATA2_PR1(RX_BAND_INDICATOR_1),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_1),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_1), /* PR2b */
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_1),
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_1) /* PR3a */
+ }
+ #endif
+ },
+ /*Band_Ind_2*/
+ {
+ RX_BAND_INDICATOR_2,
+ {
+ M_UMTS_PDATA_PR1(RX_BAND_INDICATOR_2),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_2),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_2), /* PR2b */
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_2),
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_2) /* PR3a */
+ }
+ #if IS_3G_RXD_FE_CONTROL_SUPPORT
+ ,{
+ M_UMTS_PDATA2_PR1(RX_BAND_INDICATOR_2),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_2),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_2), /* PR2b */
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_2),
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_2) /* PR3a */
+ }
+ #endif
+ },
+ /*Band_Ind_3*/
+ {
+ RX_BAND_INDICATOR_3,
+ {
+ M_UMTS_PDATA_PR1(RX_BAND_INDICATOR_3),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_3),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_3), /* PR2b */
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_3),
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_3) /* PR3a */
+ }
+ #if IS_3G_RXD_FE_CONTROL_SUPPORT
+ ,{
+ M_UMTS_PDATA2_PR1(RX_BAND_INDICATOR_3),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_3),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_3), /* PR2b */
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_3),
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_3) /* PR3a */
+ }
+ #endif
+ },
+ /*Band_Ind_4*/
+ {
+ RX_BAND_INDICATOR_4,
+ {
+ M_UMTS_PDATA_PR1(RX_BAND_INDICATOR_4),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_4),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_4), /* PR2b */
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_4),
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_4) /* PR3a */
+ }
+ #if IS_3G_RXD_FE_CONTROL_SUPPORT
+ ,{
+ M_UMTS_PDATA2_PR1(RX_BAND_INDICATOR_4),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_4),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_4), /* PR2b */
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_4),
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_4) /* PR3a */
+ }
+ #endif
+ },
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ /*Band_Ind_5*/
+ {
+ RX_BAND_INDICATOR_5,
+ {
+ M_UMTS_PDATA_PR1(RX_BAND_INDICATOR_5),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_5),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_5), /* PR2b */
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_5),
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_5) /* PR3a */
+ }
+ #if IS_3G_RXD_FE_CONTROL_SUPPORT
+ ,{
+ M_UMTS_PDATA2_PR1(RX_BAND_INDICATOR_5),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_5),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_5), /* PR2b */
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_5),
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_5) /* PR3a */
+ }
+ #endif
+ },
+ /*Band_Ind_6*/
+ {
+ RX_BAND_INDICATOR_6,
+ {
+ M_UMTS_PDATA_PR1(RX_BAND_INDICATOR_6),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_6),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_6), /* PR2b */
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_6),
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_6) /* PR3a */
+ }
+ #if IS_3G_RXD_FE_CONTROL_SUPPORT
+ ,{
+ M_UMTS_PDATA2_PR1(RX_BAND_INDICATOR_6),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_6),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_6), /* PR2b */
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_6),
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_6) /* PR3a */
+ }
+ #endif
+ },
+ /*Band_Ind_7*/
+ {
+ RX_BAND_INDICATOR_7,
+ {
+ M_UMTS_PDATA_PR1(RX_BAND_INDICATOR_7),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_7),
+ M_UMTS_PDATA_PR2(RX_BAND_INDICATOR_7), /* PR2b */
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_7),
+ M_UMTS_PDATA_PR3(RX_BAND_INDICATOR_7) /* PR3a */
+ }
+ #if IS_3G_RXD_FE_CONTROL_SUPPORT
+ ,{
+ M_UMTS_PDATA2_PR1(RX_BAND_INDICATOR_7),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_7),
+ M_UMTS_PDATA2_PR2(RX_BAND_INDICATOR_7), /* PR2b */
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_7),
+ M_UMTS_PDATA2_PR3(RX_BAND_INDICATOR_7) /* PR3a */
+ }
+ #endif
+ },
+#endif // IS_3G_SUPPORT_8_BANDINDICATOR
+ /* CA usage */
+ {0}
+ }, //RxBpi structure
+
+ /* txBpi */
+ {
+ /*Band_Ind_0*/
+ {
+ RX_BAND_INDICATOR_0,
+ {
+ M_UMTS_PDATA_PT1(RX_BAND_INDICATOR_0),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_0),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_0), /* PT2b */
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_0),
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_0) /* PT3a */
+ }
+ },
+ /*Band_Ind_1*/
+ {
+ RX_BAND_INDICATOR_1,
+ {
+ M_UMTS_PDATA_PT1(RX_BAND_INDICATOR_1),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_1),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_1), /* PT2b */
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_1),
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_1) /* PT3a */
+ }
+ },
+ /*Band_Ind_2*/
+ {
+ RX_BAND_INDICATOR_2,
+ {
+ M_UMTS_PDATA_PT1(RX_BAND_INDICATOR_2),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_2),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_2), /* PT2b */
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_2),
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_2) /* PT3a */
+ }
+ },
+ /*Band_Ind_3*/
+ {
+ RX_BAND_INDICATOR_3,
+ {
+ M_UMTS_PDATA_PT1(RX_BAND_INDICATOR_3),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_3),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_3), /* PT2b */
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_3),
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_3) /* PT3a */
+ }
+ },
+ /*Band_Ind_4*/
+ {
+ RX_BAND_INDICATOR_4,
+ {
+ M_UMTS_PDATA_PT1(RX_BAND_INDICATOR_4),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_4),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_4), /* PT2b */
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_4),
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_4) /* PT3a */
+ }
+ },
+ #if IS_3G_SUPPORT_8_BANDINDICATOR
+ /*Band_Ind_5*/
+ {
+ RX_BAND_INDICATOR_5,
+ {
+ M_UMTS_PDATA_PT1(RX_BAND_INDICATOR_5),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_5),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_5), /* PT2b */
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_5),
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_5) /* PT3a */
+ }
+ },
+ /*Band_Ind_6*/
+ {
+ RX_BAND_INDICATOR_6,
+ {
+ M_UMTS_PDATA_PT1(RX_BAND_INDICATOR_6),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_6),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_6), /* PT2b */
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_6),
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_6) /* PT3a */
+ }
+ },
+ /*Band_Ind_7*/
+ {
+ RX_BAND_INDICATOR_7,
+ {
+ M_UMTS_PDATA_PT1(RX_BAND_INDICATOR_7),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_7),
+ M_UMTS_PDATA_PT2(RX_BAND_INDICATOR_7), /* PT2b */
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_7),
+ M_UMTS_PDATA_PT3(RX_BAND_INDICATOR_7) /* PT3a */
+ }
+ },
+#endif // IS_3G_SUPPORT_8_BANDINDICATOR
+ /* CA usage */
+ {0}
+ } //TxBpi structure
+ },
+
+ /* umtsBandIndicator */
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ {
+ {
+ RX_BAND_INDICATOR_0,
+ RX_BAND_INDICATOR_1,
+ RX_BAND_INDICATOR_2,
+ RX_BAND_INDICATOR_3,
+ RX_BAND_INDICATOR_4,
+ RX_BAND_INDICATOR_5,
+ RX_BAND_INDICATOR_6,
+ RX_BAND_INDICATOR_7,
+ }
+ },
+#else
+ {
+ RX_BAND_INDICATOR_0,
+ RX_BAND_INDICATOR_1,
+ RX_BAND_INDICATOR_2,
+ RX_BAND_INDICATOR_3,
+ RX_BAND_INDICATOR_4,
+ },
+#endif // IS_3G_SUPPORT_8_BANDINDICATOR
+
+ /* sUl1dRfRxLnaPortSel */
+ {
+ {
+ /* Band_ind_0 */
+ {
+ RX_BAND_INDICATOR_0,
+ {M_UMTS_RX_IO(RX_BAND_INDICATOR_0), M_UMTS_RXD_IO(RX_BAND_INDICATOR_0)}
+ },
+ /* Band_ind_1 */
+ {
+ RX_BAND_INDICATOR_1,
+ {M_UMTS_RX_IO(RX_BAND_INDICATOR_1), M_UMTS_RXD_IO(RX_BAND_INDICATOR_1)}
+ },
+ /* Band_ind_2 */
+ {
+ RX_BAND_INDICATOR_2,
+ {M_UMTS_RX_IO(RX_BAND_INDICATOR_2), M_UMTS_RXD_IO(RX_BAND_INDICATOR_2)}
+ },
+ /* Band_ind_3 */
+ {
+ RX_BAND_INDICATOR_3,
+ {M_UMTS_RX_IO(RX_BAND_INDICATOR_3), M_UMTS_RXD_IO(RX_BAND_INDICATOR_3)}
+ },
+ /* Band_ind_4 */
+ {
+ RX_BAND_INDICATOR_4,
+ {M_UMTS_RX_IO(RX_BAND_INDICATOR_4), M_UMTS_RXD_IO(RX_BAND_INDICATOR_4)}
+ },
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ {
+ RX_BAND_INDICATOR_5,
+ {M_UMTS_RX_IO(RX_BAND_INDICATOR_5), M_UMTS_RXD_IO(RX_BAND_INDICATOR_5)}
+ },
+ {
+ RX_BAND_INDICATOR_6,
+ {M_UMTS_RX_IO(RX_BAND_INDICATOR_6), M_UMTS_RXD_IO(RX_BAND_INDICATOR_6)}
+ },
+ {
+ RX_BAND_INDICATOR_7,
+ {M_UMTS_RX_IO(RX_BAND_INDICATOR_7), M_UMTS_RXD_IO(RX_BAND_INDICATOR_7)}
+ },
+#endif
+ /* CA usage */
+ {0}
+ }
+ },
+
+ /* umtsTxPathSel */
+ {
+ {
+ /* Band_ind_0 */
+ {
+ RX_BAND_INDICATOR_0,
+ {M_UMTS_TX_IO(RX_BAND_INDICATOR_0),M_UMTS_TX_DET_IO(RX_BAND_INDICATOR_0)}
+ },
+ /* Band_ind_1 */
+ {
+ RX_BAND_INDICATOR_1,
+ {M_UMTS_TX_IO(RX_BAND_INDICATOR_1),M_UMTS_TX_DET_IO(RX_BAND_INDICATOR_1)}
+ },
+ /* Band_ind_2 */
+ {
+ RX_BAND_INDICATOR_2,
+ {M_UMTS_TX_IO(RX_BAND_INDICATOR_2),M_UMTS_TX_DET_IO(RX_BAND_INDICATOR_2)}
+ },
+ /* Band_ind_3 */
+ {
+ RX_BAND_INDICATOR_3,
+ {M_UMTS_TX_IO(RX_BAND_INDICATOR_3),M_UMTS_TX_DET_IO(RX_BAND_INDICATOR_3)}
+ },
+ /* Band_ind_4 */
+ {
+ RX_BAND_INDICATOR_4,
+ {M_UMTS_TX_IO(RX_BAND_INDICATOR_4),M_UMTS_TX_DET_IO(RX_BAND_INDICATOR_4)}
+ },
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ {
+ RX_BAND_INDICATOR_5,
+ {M_UMTS_TX_IO(RX_BAND_INDICATOR_5),M_UMTS_TX_DET_IO(RX_BAND_INDICATOR_5)}
+ },
+ {
+ RX_BAND_INDICATOR_6,
+ {M_UMTS_TX_IO(RX_BAND_INDICATOR_6),M_UMTS_TX_DET_IO(RX_BAND_INDICATOR_6)}
+ },
+ {
+ RX_BAND_INDICATOR_7,
+ {M_UMTS_TX_IO(RX_BAND_INDICATOR_7),M_UMTS_TX_DET_IO(RX_BAND_INDICATOR_7)}
+ },
+#endif
+ /* CA usage */
+ {0}
+ }
+ },
+
+ /* xPMU_PA_CONTROL */
+ PMU_PASETTING,
+
+#if defined (__UL1_HS_PLUS_PLATFORM__)
+ /* umtsMprBackOff */
+ {
+ {
+ MPR_BACK_OFF_HSDPA_BAND1 , MPR_BACK_OFF_HSDPA_BAND2 , MPR_BACK_OFF_HSDPA_BAND3 , MPR_BACK_OFF_HSDPA_BAND4 , MPR_BACK_OFF_HSDPA_BAND5 ,
+ MPR_BACK_OFF_HSDPA_BAND6 , MPR_BACK_OFF_HSDPA_BAND7 , MPR_BACK_OFF_HSDPA_BAND8 , MPR_BACK_OFF_HSDPA_BAND9 , MPR_BACK_OFF_HSDPA_BAND10,
+ MPR_BACK_OFF_HSDPA_BAND11, MPR_BACK_OFF_HSDPA_BAND12, MPR_BACK_OFF_HSDPA_BAND13, MPR_BACK_OFF_HSDPA_BAND14, MPR_BACK_OFF_HSDPA_BAND15,
+ MPR_BACK_OFF_HSDPA_BAND16, MPR_BACK_OFF_HSDPA_BAND17, MPR_BACK_OFF_HSDPA_BAND18, MPR_BACK_OFF_HSDPA_BAND19, MPR_BACK_OFF_HSDPA_BAND19
+ },
+ {
+ MPR_BACK_OFF_HSUPA_BAND1 , MPR_BACK_OFF_HSUPA_BAND2 , MPR_BACK_OFF_HSUPA_BAND3 , MPR_BACK_OFF_HSUPA_BAND4 , MPR_BACK_OFF_HSUPA_BAND5 ,
+ MPR_BACK_OFF_HSUPA_BAND6 , MPR_BACK_OFF_HSUPA_BAND7 , MPR_BACK_OFF_HSUPA_BAND8 , MPR_BACK_OFF_HSUPA_BAND9 , MPR_BACK_OFF_HSUPA_BAND10,
+ MPR_BACK_OFF_HSUPA_BAND11, MPR_BACK_OFF_HSUPA_BAND12, MPR_BACK_OFF_HSUPA_BAND13, MPR_BACK_OFF_HSUPA_BAND14, MPR_BACK_OFF_HSUPA_BAND15,
+ MPR_BACK_OFF_HSUPA_BAND16, MPR_BACK_OFF_HSUPA_BAND17, MPR_BACK_OFF_HSUPA_BAND18, MPR_BACK_OFF_HSUPA_BAND19, MPR_BACK_OFF_HSUPA_BAND19
+ }
+ #if IS_3G_MPR_EXTEND_SUPPORT
+ ,{ /*MPR_Setting_SUB HSUPA_MprBackOff_SUB[20][5];*/
+ /*00*/{MPR_R6_B1_SUB_1 , MPR_R6_B1_SUB_2 , MPR_R6_B1_SUB_3 , MPR_R6_B1_SUB_4 , MPR_R6_B1_SUB_5 },
+ /*01*/{MPR_R6_B2_SUB_1 , MPR_R6_B2_SUB_2 , MPR_R6_B2_SUB_3 , MPR_R6_B2_SUB_4 , MPR_R6_B2_SUB_5 },
+ /*02*/{MPR_R6_B3_SUB_1 , MPR_R6_B3_SUB_2 , MPR_R6_B3_SUB_3 , MPR_R6_B3_SUB_4 , MPR_R6_B3_SUB_5 },
+ /*03*/{MPR_R6_B4_SUB_1 , MPR_R6_B4_SUB_2 , MPR_R6_B4_SUB_3 , MPR_R6_B4_SUB_4 , MPR_R6_B4_SUB_5 },
+ /*04*/{MPR_R6_B5_SUB_1 , MPR_R6_B5_SUB_2 , MPR_R6_B5_SUB_3 , MPR_R6_B5_SUB_4 , MPR_R6_B5_SUB_5 },
+ /*05*/{MPR_R6_B6_SUB_1 , MPR_R6_B6_SUB_2 , MPR_R6_B6_SUB_3 , MPR_R6_B6_SUB_4 , MPR_R6_B6_SUB_5 },
+ /*06*/{MPR_R6_B7_SUB_1 , MPR_R6_B7_SUB_2 , MPR_R6_B7_SUB_3 , MPR_R6_B7_SUB_4 , MPR_R6_B7_SUB_5 },
+ /*07*/{MPR_R6_B8_SUB_1 , MPR_R6_B8_SUB_2 , MPR_R6_B8_SUB_3 , MPR_R6_B8_SUB_4 , MPR_R6_B8_SUB_5 },
+ /*08*/{MPR_R6_B9_SUB_1 , MPR_R6_B9_SUB_2 , MPR_R6_B9_SUB_3 , MPR_R6_B9_SUB_4 , MPR_R6_B9_SUB_5 },
+ /*09*/{MPR_R6_B10_SUB_1 , MPR_R6_B10_SUB_2 , MPR_R6_B10_SUB_3 , MPR_R6_B10_SUB_4 , MPR_R6_B10_SUB_5},
+ /*10*/{MPR_R6_B11_SUB_1 , MPR_R6_B11_SUB_2 , MPR_R6_B11_SUB_3 , MPR_R6_B11_SUB_4 , MPR_R6_B11_SUB_5},
+ /*11*/{MPR_R6_B12_SUB_1 , MPR_R6_B12_SUB_2 , MPR_R6_B12_SUB_3 , MPR_R6_B12_SUB_4 , MPR_R6_B12_SUB_5},
+ /*12*/{MPR_R6_B13_SUB_1 , MPR_R6_B13_SUB_2 , MPR_R6_B13_SUB_3 , MPR_R6_B13_SUB_4 , MPR_R6_B13_SUB_5},
+ /*13*/{MPR_R6_B14_SUB_1 , MPR_R6_B14_SUB_2 , MPR_R6_B14_SUB_3 , MPR_R6_B14_SUB_4 , MPR_R6_B14_SUB_5},
+ /*14*/{MPR_R6_B15_SUB_1 , MPR_R6_B15_SUB_2 , MPR_R6_B15_SUB_3 , MPR_R6_B15_SUB_4 , MPR_R6_B15_SUB_5},
+ /*15*/{MPR_R6_B16_SUB_1 , MPR_R6_B16_SUB_2 , MPR_R6_B16_SUB_3 , MPR_R6_B16_SUB_4 , MPR_R6_B16_SUB_5},
+ /*16*/{MPR_R6_B17_SUB_1 , MPR_R6_B17_SUB_2 , MPR_R6_B17_SUB_3 , MPR_R6_B17_SUB_4 , MPR_R6_B17_SUB_5},
+ /*17*/{MPR_R6_B18_SUB_1 , MPR_R6_B18_SUB_2 , MPR_R6_B18_SUB_3 , MPR_R6_B18_SUB_4 , MPR_R6_B18_SUB_5},
+ /*18*/{MPR_R6_B19_SUB_1 , MPR_R6_B19_SUB_2 , MPR_R6_B19_SUB_3 , MPR_R6_B19_SUB_4 , MPR_R6_B19_SUB_5},
+ /*19*/{MPR_R6_B20_SUB_1 , MPR_R6_B20_SUB_2 , MPR_R6_B20_SUB_3 , MPR_R6_B20_SUB_4 , MPR_R6_B20_SUB_5}
+ },
+ R6_MPR_SUB_EN,/*R6_MPR_SUB_EN*/
+ #endif/*IS_3G_MPR_EXTEND_SUPPORT*/
+ },
+#endif
+
+ /* RxD support bit map*/
+ RX_DIVERSITY_ALWAYS_ON,
+
+ /* Tx PA dirft compensation bit map*/
+ PA_DIRFT_COMPENSATION,
+
+ /*At MT6589+MT6320PMIC, Vrf18_1(MD1) can use bulk/LDO mode, this is the switch*/
+ ULTRA_LOW_COST_EN,
+
+ /*At MT6589/MT6280+OrionRF, temperature measurement enable switch */
+ TEAMPERATURE_MEAS_EN,
+
+ /* Baseband Idle Mode RXD Feature enable Default ON */
+#if IS_3G_FORCE_IDLE_MODE_RXD_SUPPORT
+ KAL_TRUE,
+#else
+ KAL_FALSE,
+#endif
+
+ /* VPA Mode Setting */
+ VPA_FPWM_MODE,
+
+ /* PA Section */
+ PA_SECTION,
+
+#if IS_3G_MIPI_SUPPORT
+ {
+ IS_3G_MIPI_ENABLE,
+ MIPI_OFFSET
+ },
+#endif
+
+ /* umtsCaBandIndicator */
+ {
+ RX_CABAND_IND_00,
+ RX_CABAND_IND_01,
+ RX_CABAND_IND_02,
+ RX_CABAND_IND_03,
+ RX_CABAND_IND_04,
+ },
+
+ /* CA RF FE usage table */
+ //UMTS_FE_USAGE_T umtsCaFrontEndUsageLut[UMTS_RF_FRONT_END_NUM_MAX];
+ {
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}}
+ },
+
+#if IS_3G_FDD_RX_PATH_SELECTION_SUPPORT
+ {
+ KAL_FALSE,
+ ANT_RX_BOTH,
+ },
+#endif
+
+ BAND5_AND_BAND6_INDICATOR,
+
+#if IS_3G_B5_AND_B19_INDICATOR_SUPPORT
+ BAND5_AND_BAND19_INDICATOR,
+ DISABLE_B5_INDICATOR,
+#endif
+
+#if IS_3G_RX_POWER_OFFSET_SUPPORT
+ {
+ RPO_3G_ENABLE,
+ RPO_3G_META_ENABLE
+ },
+#endif
+ /* End Pattern */
+ 0xABCD1234
+};
+
+#else
+U_sUl1dRfCustomInputData UMTS_RF_CUSTOM_INPUT_DATA_PCORE =
+{
+ /* Start Pattern */
+ 0x1234ABCD,
+
+ /* Structure Version */
+ 1,
+
+ /* RF Type */
+ UMTS_RF_TYPE,
+
+ /* isDataUpdate */
+ 1,
+
+#if defined (__UL1_HS_PLUS_PLATFORM__)
+ /* proityOfNvramInCustomization */
+ RF_SETTING_BY_NVRAM,
+#endif
+
+ /* umtsRfPaControlTimingOffset */
+ {
+ MAX_OFFSET,
+ VM_OFFSET,
+ VBIAS_OFFSET,
+ DC2DC_OFFSET,
+ VGA_OFFSET
+ },
+
+ /* umtsBsiBpiTiming */
+ {
+ /* RX window end timing */
+ -TC_PR1,
+ -TC_PR2,
+ -TC_PR2B,
+
+ /* RX window end timing */
+ TC_PR3,
+ TC_PR3A,
+
+ /* TX window start timing */
+ -TC_PT1,
+ -TC_PT2,
+ -TC_PT2B,
+
+ /* TX window end timing */
+ TC_PT3,
+ TC_PT3A
+ },
+
+ /* umtsBandIndicator */
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ {
+ {
+ RX_BAND_INDICATOR_0,
+ RX_BAND_INDICATOR_1,
+ RX_BAND_INDICATOR_2,
+ RX_BAND_INDICATOR_3,
+ RX_BAND_INDICATOR_4,
+ RX_BAND_INDICATOR_5,
+ RX_BAND_INDICATOR_6,
+ RX_BAND_INDICATOR_7,
+ }
+ },
+#else
+ {
+ RX_BAND_INDICATOR_0,
+ RX_BAND_INDICATOR_1,
+ RX_BAND_INDICATOR_2,
+ RX_BAND_INDICATOR_3,
+ RX_BAND_INDICATOR_4,
+ },
+#endif // IS_3G_SUPPORT_8_BANDINDICATOR
+
+ /* sUl1dRfRxLnaPortSel */
+
+ /* umtsTxPathSel */
+
+
+ /* xPMU_PA_CONTROL */
+ PMU_PASETTING,
+
+#if defined (__UL1_HS_PLUS_PLATFORM__)
+ /* umtsMprBackOff */
+ {
+ {
+ MPR_BACK_OFF_HSDPA_BAND1 , MPR_BACK_OFF_HSDPA_BAND2 , MPR_BACK_OFF_HSDPA_BAND3 , MPR_BACK_OFF_HSDPA_BAND4 , MPR_BACK_OFF_HSDPA_BAND5 ,
+ MPR_BACK_OFF_HSDPA_BAND6 , MPR_BACK_OFF_HSDPA_BAND7 , MPR_BACK_OFF_HSDPA_BAND8 , MPR_BACK_OFF_HSDPA_BAND9 , MPR_BACK_OFF_HSDPA_BAND10,
+ MPR_BACK_OFF_HSDPA_BAND11, MPR_BACK_OFF_HSDPA_BAND12, MPR_BACK_OFF_HSDPA_BAND13, MPR_BACK_OFF_HSDPA_BAND14, MPR_BACK_OFF_HSDPA_BAND15,
+ MPR_BACK_OFF_HSDPA_BAND16, MPR_BACK_OFF_HSDPA_BAND17, MPR_BACK_OFF_HSDPA_BAND18, MPR_BACK_OFF_HSDPA_BAND19, MPR_BACK_OFF_HSDPA_BAND19
+ },
+ {
+ MPR_BACK_OFF_HSUPA_BAND1 , MPR_BACK_OFF_HSUPA_BAND2 , MPR_BACK_OFF_HSUPA_BAND3 , MPR_BACK_OFF_HSUPA_BAND4 , MPR_BACK_OFF_HSUPA_BAND5 ,
+ MPR_BACK_OFF_HSUPA_BAND6 , MPR_BACK_OFF_HSUPA_BAND7 , MPR_BACK_OFF_HSUPA_BAND8 , MPR_BACK_OFF_HSUPA_BAND9 , MPR_BACK_OFF_HSUPA_BAND10,
+ MPR_BACK_OFF_HSUPA_BAND11, MPR_BACK_OFF_HSUPA_BAND12, MPR_BACK_OFF_HSUPA_BAND13, MPR_BACK_OFF_HSUPA_BAND14, MPR_BACK_OFF_HSUPA_BAND15,
+ MPR_BACK_OFF_HSUPA_BAND16, MPR_BACK_OFF_HSUPA_BAND17, MPR_BACK_OFF_HSUPA_BAND18, MPR_BACK_OFF_HSUPA_BAND19, MPR_BACK_OFF_HSUPA_BAND19
+ }
+ #if IS_3G_MPR_EXTEND_SUPPORT
+ ,{ /*MPR_Setting_SUB HSUPA_MprBackOff_SUB[20][5];*/
+ /*00*/{MPR_R6_B1_SUB_1 , MPR_R6_B1_SUB_2 , MPR_R6_B1_SUB_3 , MPR_R6_B1_SUB_4 , MPR_R6_B1_SUB_5 },
+ /*01*/{MPR_R6_B2_SUB_1 , MPR_R6_B2_SUB_2 , MPR_R6_B2_SUB_3 , MPR_R6_B2_SUB_4 , MPR_R6_B2_SUB_5 },
+ /*02*/{MPR_R6_B3_SUB_1 , MPR_R6_B3_SUB_2 , MPR_R6_B3_SUB_3 , MPR_R6_B3_SUB_4 , MPR_R6_B3_SUB_5 },
+ /*03*/{MPR_R6_B4_SUB_1 , MPR_R6_B4_SUB_2 , MPR_R6_B4_SUB_3 , MPR_R6_B4_SUB_4 , MPR_R6_B4_SUB_5 },
+ /*04*/{MPR_R6_B5_SUB_1 , MPR_R6_B5_SUB_2 , MPR_R6_B5_SUB_3 , MPR_R6_B5_SUB_4 , MPR_R6_B5_SUB_5 },
+ /*05*/{MPR_R6_B6_SUB_1 , MPR_R6_B6_SUB_2 , MPR_R6_B6_SUB_3 , MPR_R6_B6_SUB_4 , MPR_R6_B6_SUB_5 },
+ /*06*/{MPR_R6_B7_SUB_1 , MPR_R6_B7_SUB_2 , MPR_R6_B7_SUB_3 , MPR_R6_B7_SUB_4 , MPR_R6_B7_SUB_5 },
+ /*07*/{MPR_R6_B8_SUB_1 , MPR_R6_B8_SUB_2 , MPR_R6_B8_SUB_3 , MPR_R6_B8_SUB_4 , MPR_R6_B8_SUB_5 },
+ /*08*/{MPR_R6_B9_SUB_1 , MPR_R6_B9_SUB_2 , MPR_R6_B9_SUB_3 , MPR_R6_B9_SUB_4 , MPR_R6_B9_SUB_5 },
+ /*09*/{MPR_R6_B10_SUB_1 , MPR_R6_B10_SUB_2 , MPR_R6_B10_SUB_3 , MPR_R6_B10_SUB_4 , MPR_R6_B10_SUB_5},
+ /*10*/{MPR_R6_B11_SUB_1 , MPR_R6_B11_SUB_2 , MPR_R6_B11_SUB_3 , MPR_R6_B11_SUB_4 , MPR_R6_B11_SUB_5},
+ /*11*/{MPR_R6_B12_SUB_1 , MPR_R6_B12_SUB_2 , MPR_R6_B12_SUB_3 , MPR_R6_B12_SUB_4 , MPR_R6_B12_SUB_5},
+ /*12*/{MPR_R6_B13_SUB_1 , MPR_R6_B13_SUB_2 , MPR_R6_B13_SUB_3 , MPR_R6_B13_SUB_4 , MPR_R6_B13_SUB_5},
+ /*13*/{MPR_R6_B14_SUB_1 , MPR_R6_B14_SUB_2 , MPR_R6_B14_SUB_3 , MPR_R6_B14_SUB_4 , MPR_R6_B14_SUB_5},
+ /*14*/{MPR_R6_B15_SUB_1 , MPR_R6_B15_SUB_2 , MPR_R6_B15_SUB_3 , MPR_R6_B15_SUB_4 , MPR_R6_B15_SUB_5},
+ /*15*/{MPR_R6_B16_SUB_1 , MPR_R6_B16_SUB_2 , MPR_R6_B16_SUB_3 , MPR_R6_B16_SUB_4 , MPR_R6_B16_SUB_5},
+ /*16*/{MPR_R6_B17_SUB_1 , MPR_R6_B17_SUB_2 , MPR_R6_B17_SUB_3 , MPR_R6_B17_SUB_4 , MPR_R6_B17_SUB_5},
+ /*17*/{MPR_R6_B18_SUB_1 , MPR_R6_B18_SUB_2 , MPR_R6_B18_SUB_3 , MPR_R6_B18_SUB_4 , MPR_R6_B18_SUB_5},
+ /*18*/{MPR_R6_B19_SUB_1 , MPR_R6_B19_SUB_2 , MPR_R6_B19_SUB_3 , MPR_R6_B19_SUB_4 , MPR_R6_B19_SUB_5},
+ /*19*/{MPR_R6_B20_SUB_1 , MPR_R6_B20_SUB_2 , MPR_R6_B20_SUB_3 , MPR_R6_B20_SUB_4 , MPR_R6_B20_SUB_5}
+ },
+ R6_MPR_SUB_EN,/*R6_MPR_SUB_EN*/
+ #endif/*IS_3G_MPR_EXTEND_SUPPORT*/
+ },
+#endif
+
+ /* RxD support bit map*/
+ RX_DIVERSITY_ALWAYS_ON,
+
+ /* Tx PA dirft compensation bit map*/
+ PA_DIRFT_COMPENSATION,
+
+ /*At MT6589+MT6320PMIC, Vrf18_1(MD1) can use bulk/LDO mode, this is the switch*/
+ ULTRA_LOW_COST_EN,
+
+ /*At MT6589/MT6280+OrionRF, temperature measurement enable switch */
+ TEAMPERATURE_MEAS_EN,
+
+ /* Baseband Idle Mode RXD Feature enable Default ON */
+#if IS_3G_FORCE_IDLE_MODE_RXD_SUPPORT
+ KAL_TRUE,
+#else
+ KAL_FALSE,
+#endif
+
+ /* VPA Mode Setting */
+ VPA_FPWM_MODE,
+
+ /* PA Section */
+ PA_SECTION,
+
+ /* umtsCaBandIndicator */
+ {
+ RX_CABAND_IND_00,
+ RX_CABAND_IND_01,
+ RX_CABAND_IND_02,
+ RX_CABAND_IND_03,
+ RX_CABAND_IND_04,
+ },
+
+ /* CA RF FE usage table */
+ //UMTS_FE_USAGE_T umtsCaFrontEndUsageLut[UMTS_RF_FRONT_END_NUM_MAX];
+
+#if IS_3G_FDD_RX_PATH_SELECTION_SUPPORT
+ {
+ KAL_FALSE,
+ ANT_RX_BOTH,
+ },
+#endif
+ BAND5_AND_BAND6_INDICATOR,
+
+#if IS_3G_B5_AND_B19_INDICATOR_SUPPORT
+ BAND5_AND_BAND19_INDICATOR,
+ DISABLE_B5_INDICATOR,
+#endif
+
+#if IS_3G_RX_POWER_OFFSET_SUPPORT
+ {
+ RPO_3G_ENABLE,
+ RPO_3G_META_ENABLE
+ },
+#endif
+ /* End Pattern */
+ 0xABCD1234
+};
+#endif
+
+#if __IS_UL1D_DPD_SUPPORT__
+U_sUl1dDpdCustomInputData UMTS_DPD_CUSTOM_INPUT_DATA_PCORE =
+{
+ /*U_Ul1D_PCFE_DPD_OTFC_NONCUSTOM_PARA_T*/
+ {
+ /*U_DPD_OTFC_NONCUSTOM_PARA_T*/
+ {
+ 0, /*en_dpd_am_track*/
+ 0, /*en_dpd_pm_track*/
+ 0, /*en_force_dpd_default_lut*/
+ 1, /*en_dpd_coarse_tde*/
+ 1, /*en_dpd_fine_tde*/
+ },
+ /*U_PCFE_NONCUSTOM_PARA_T*/
+ {
+ 0, /*op_mode_force_en*/
+ 0, /*op_mode_force_mode*/
+ },
+ },
+ {
+ /*U_UL1D_PCFE_DPD_OTFC_CUSTOM_PARA_T*/
+ //dpd_apt_temperature_th_by_rfic
+ {
+ { 0x41 , 0x41 }
+ },
+ /*U_PCFE_CUSTOM_PARA_T*/
+ //reserved0
+ {0},
+
+ /* PCFE power threshold form DPD mode to linear mode */
+ 0x0A00,
+ /* PCFE power threshold form linear mode to DPD mode */
+ 0x0B00,
+ }
+};
+
+DPD_ENABLE_E UMTS_DPD_ENABLE_PCORE = IS_WCDMA_DPD_ENABLE_SetDefault;
+
+#endif
+
+#if IS_3G_TAS_UL1_CUSTOM_SUPPORT
+#if !IS_3G_UTAS_SUPPORT
+UMTS_CUSTOM_TAS_FE_DATABASE_T UMTS_TAS_FE_DATABASE_SetDefault =
+{
+ {{{0}}}, {{{0}}}, {{{0}}}
+};
+#endif
+UMTS_CUSTOM_TAS_FEATURE_BY_RAT_T UMTS_TAS_FEATURE_BY_RAT_SetDefault =
+{
+#if !IS_3G_UTAS_SUPPORT
+ UMTS_TAS_VERSION(SetDefault),
+#endif
+ {
+ UMTS_TAS_FORCE_ENABLE(SetDefault),
+ UMTS_TAS_FORCE_INIT_SETTING(SetDefault)
+ },
+ UMTS_TAS_ICS_INIT_ANT_STATE(SetDefault),
+ UMTS_TAS_ENABLE_ON_REAL_SIM(SetDefault),
+ UMTS_TAS_ENABLE_ON_TEST_SIM(SetDefault),
+};
+#if IS_3G_TAS_TST_SUPPORT
+#if IS_3G_GEN97_TAS_SUPPORT
+UMTS_CUSTOM_TAS_TST_FE_ROUTE_DATABASE_T UMTS_TAS_TST_FE_ROUTE_DATABASE_PCORE =
+{
+ UMTS_TAS_TST_ENABLE_BY_RAT(SetDefault),
+ {
+ /*Index 1*/ UMTS_SB_TAS_TST_CONFIGURE( RX_BAND_INDICATOR_0_SetDefault , SetDefault ) ,
+ /*Index 2*/ UMTS_SB_TAS_TST_CONFIGURE( RX_BAND_INDICATOR_1_SetDefault , SetDefault ) ,
+ /*Index 3*/ UMTS_SB_TAS_TST_CONFIGURE( RX_BAND_INDICATOR_2_SetDefault , SetDefault ) ,
+ /*Index 4*/ UMTS_SB_TAS_TST_CONFIGURE( RX_BAND_INDICATOR_3_SetDefault , SetDefault ) ,
+ /*Index 5*/ UMTS_SB_TAS_TST_CONFIGURE( RX_BAND_INDICATOR_4_SetDefault , SetDefault ) ,
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ /*Index 3*/ UMTS_SB_TAS_TST_CONFIGURE( RX_BAND_INDICATOR_5_SetDefault , SetDefault ) ,
+ /*Index 4*/ UMTS_SB_TAS_TST_CONFIGURE( RX_BAND_INDICATOR_6_SetDefault , SetDefault ) ,
+ /*Index 5*/ UMTS_SB_TAS_TST_CONFIGURE( RX_BAND_INDICATOR_7_SetDefault , SetDefault ) ,
+#endif
+ }
+};
+#else
+UMTS_CUSTOM_TAS_TST_FE_ROUTE_DATABASE_T UMTS_TAS_TST_FE_ROUTE_DATABASE_PCORE =
+{
+ UMTS_TAS_TST_ENABLE_BY_RAT(SetDefault),
+ {
+ /*Index 1*/ UMTS_SB_TAS_TST_CONFIGURE( BAND_TAS_INDICATOR0_SetDefault , SetDefault ) ,
+ /*Index 2*/ UMTS_SB_TAS_TST_CONFIGURE( BAND_TAS_INDICATOR1_SetDefault , SetDefault ) ,
+ /*Index 3*/ UMTS_SB_TAS_TST_CONFIGURE( BAND_TAS_INDICATOR2_SetDefault , SetDefault ) ,
+ /*Index 4*/ UMTS_SB_TAS_TST_CONFIGURE( BAND_TAS_INDICATOR3_SetDefault , SetDefault ) ,
+ /*Index 5*/ UMTS_SB_TAS_TST_CONFIGURE( BAND_TAS_INDICATOR4_SetDefault , SetDefault ) ,
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ /*Index 3*/ UMTS_SB_TAS_TST_CONFIGURE( BAND_TAS_INDICATOR5_SetDefault , SetDefault ) ,
+ /*Index 4*/ UMTS_SB_TAS_TST_CONFIGURE( BAND_TAS_INDICATOR6_SetDefault , SetDefault ) ,
+ /*Index 5*/ UMTS_SB_TAS_TST_CONFIGURE( BAND_TAS_INDICATOR7_SetDefault , SetDefault ) ,
+#endif
+ }
+};
+#endif
+#endif
+#endif
+
+#if IS_3G_DAT_UL1_CUSTOM_SUPPORT
+#if !IS_3G_UDAT_SUPPORT
+UMTS_CUSTOM_DAT_FE_DATABASE_T UMTS_DAT_FE_DATABASE_SetDefault =
+{
+ {{{0}}}, {{{0}}}
+};
+#endif
+
+UMTS_CUSTOM_DAT_FEATURE_BY_RAT_T UMTS_DAT_FEATURE_BY_RAT_SetDefault =
+{
+ UMTS_DAT_FEATURE_ENABLE(SetDefault),
+ UMTS_DAT_SCENARIO_DEFAULT
+};
+#endif
+
+
+//Power on CAL
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBandNone_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(None);
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBand1_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(1);
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBand2_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(2);
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBand3_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(3);
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBand4_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(4);
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBand5_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(5);
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBand6_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(6);
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBand8_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(8);
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBand9_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(9);
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBand11_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(11);
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBand18_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(18);
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T UMTSBand19_PWRON_CAL_DATA = M_UL1D_DEFAULT_RFC_B(19);
+
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+#if IS_3G_REMOVE_MIPI
+UMTS_FE_USAGE_T UMTS_FE_USAGE_TBL[UMTS_RF_FRONT_END_NUM_MAX] =
+{
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}},
+ {{0,{0,0}},{{0,0},{0}},{{0,0},{0}},{{0,0},{0}}}
+};
+
+/* P-core Table ============================================================================= */
+UMTS_RX_PDATABASE_T UMTS_RX_PDATABASE[UMTS_FE_RXBASE_TBL_SIZE_MAX] =
+{
+ M_UMTS_RF_RX_PDATABASE(RX_BAND_INDICATOR_0),
+ M_UMTS_RF_RX_PDATABASE(RX_BAND_INDICATOR_1),
+ M_UMTS_RF_RX_PDATABASE(RX_BAND_INDICATOR_2),
+ M_UMTS_RF_RX_PDATABASE(RX_BAND_INDICATOR_3),
+ M_UMTS_RF_RX_PDATABASE(RX_BAND_INDICATOR_4),
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ M_UMTS_RF_RX_PDATABASE(RX_BAND_INDICATOR_5),
+ M_UMTS_RF_RX_PDATABASE(RX_BAND_INDICATOR_6),
+ M_UMTS_RF_RX_PDATABASE(RX_BAND_INDICATOR_7),
+#endif
+ M_UMTS_RF_RX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_RX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_RX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_RX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_RX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_RX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_RX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_RX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_RX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_RX_PDATABASE(UMTSBandNone),
+};
+
+UMTS_TX_PDATABASE_T UMTS_TX_PDATABASE[UMTS_FE_TXBASE_TBL_SIZE_MAX] =
+{
+ M_UMTS_RF_TX_PDATABASE(RX_BAND_INDICATOR_0),
+ M_UMTS_RF_TX_PDATABASE(RX_BAND_INDICATOR_1),
+ M_UMTS_RF_TX_PDATABASE(RX_BAND_INDICATOR_2),
+ M_UMTS_RF_TX_PDATABASE(RX_BAND_INDICATOR_3),
+ M_UMTS_RF_TX_PDATABASE(RX_BAND_INDICATOR_4),
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ M_UMTS_RF_TX_PDATABASE(RX_BAND_INDICATOR_5),
+ M_UMTS_RF_TX_PDATABASE(RX_BAND_INDICATOR_6),
+ M_UMTS_RF_TX_PDATABASE(RX_BAND_INDICATOR_7),
+#endif
+ M_UMTS_RF_TX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_TX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_TX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_TX_PDATABASE(UMTSBandNone),
+ M_UMTS_RF_TX_PDATABASE(UMTSBandNone),
+};
+
+UMTS_RXIOBASE_T UMTS_RF_RXIOBASE[UMTS_FE_RXBASE_TBL_SIZE_MAX] =
+{
+ M_UMTS_RF_RXIOBASE(RX_BAND_INDICATOR_0 ),
+ M_UMTS_RF_RXIOBASE(RX_BAND_INDICATOR_1 ),
+ M_UMTS_RF_RXIOBASE(RX_BAND_INDICATOR_2 ),
+ M_UMTS_RF_RXIOBASE(RX_BAND_INDICATOR_3 ),
+ M_UMTS_RF_RXIOBASE(RX_BAND_INDICATOR_4 ),
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ M_UMTS_RF_RXIOBASE(RX_BAND_INDICATOR_5),
+ M_UMTS_RF_RXIOBASE(RX_BAND_INDICATOR_6),
+ M_UMTS_RF_RXIOBASE(RX_BAND_INDICATOR_7),
+#endif
+ M_UMTS_RF_RXIOBASE(UMTSBandNone),
+ M_UMTS_RF_RXIOBASE(UMTSBandNone),
+ M_UMTS_RF_RXIOBASE(UMTSBandNone),
+ M_UMTS_RF_RXIOBASE(UMTSBandNone),
+ M_UMTS_RF_RXIOBASE(UMTSBandNone),
+ M_UMTS_RF_RXIOBASE(UMTSBandNone),
+ M_UMTS_RF_RXIOBASE(UMTSBandNone),
+ M_UMTS_RF_RXIOBASE(UMTSBandNone),
+ M_UMTS_RF_RXIOBASE(UMTSBandNone),
+ M_UMTS_RF_RXIOBASE(UMTSBandNone),
+};
+
+UMTS_TXIOBASE_T UMTS_RF_TXIOBASE[UMTS_FE_TXBASE_TBL_SIZE_MAX] =
+{
+ M_UMTS_RF_TXIOBASE(RX_BAND_INDICATOR_0 ),
+ M_UMTS_RF_TXIOBASE(RX_BAND_INDICATOR_1 ),
+ M_UMTS_RF_TXIOBASE(RX_BAND_INDICATOR_2 ),
+ M_UMTS_RF_TXIOBASE(RX_BAND_INDICATOR_3 ),
+ M_UMTS_RF_TXIOBASE(RX_BAND_INDICATOR_4 ),
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ M_UMTS_RF_TXIOBASE(RX_BAND_INDICATOR_5 ),
+ M_UMTS_RF_TXIOBASE(RX_BAND_INDICATOR_6 ),
+ M_UMTS_RF_TXIOBASE(RX_BAND_INDICATOR_7 ),
+#endif
+ M_UMTS_RF_TXIOBASE(UMTSBandNone ),
+ M_UMTS_RF_TXIOBASE(UMTSBandNone ),
+ M_UMTS_RF_TXIOBASE(UMTSBandNone ),
+ M_UMTS_RF_TXIOBASE(UMTSBandNone ),
+ M_UMTS_RF_TXIOBASE(UMTSBandNone ),
+};
+
+#else
+//Useless afte Gen97
+#endif
+
+const UMTS_RF_POWER_ON_CAL_DATA_PER_BAND_T* UMTS_PWRON_CAL_DATA_PTR[UL1D_RF_CUSTOM_BAND] =
+{
+ &UMTS_PWRON_CAL_DATA(UMTSBandNone) ,
+ &UMTS_PWRON_CAL_DATA(RX_BAND_INDICATOR_0) ,
+ &UMTS_PWRON_CAL_DATA(RX_BAND_INDICATOR_1) ,
+ &UMTS_PWRON_CAL_DATA(RX_BAND_INDICATOR_2) ,
+ &UMTS_PWRON_CAL_DATA(RX_BAND_INDICATOR_3) ,
+ &UMTS_PWRON_CAL_DATA(RX_BAND_INDICATOR_4) ,
+#if IS_3G_SUPPORT_8_BANDINDICATOR
+ &UMTS_PWRON_CAL_DATA(RX_BAND_INDICATOR_5) ,
+ &UMTS_PWRON_CAL_DATA(RX_BAND_INDICATOR_6) ,
+ &UMTS_PWRON_CAL_DATA(RX_BAND_INDICATOR_7) ,
+#endif
+};
+
+#if IS_3G_ELNA_IDX_SUPPORT
+UMTS_CUSTOM_ELNA_IDX_T UMTS_ELNA_IDX_LUT_PCORE =
+{
+ { /*RxElnaIdx[20]*/
+ UMTSBand1_RX_eLNA_IDX,
+ UMTSBand2_RX_eLNA_IDX,
+ UMTSBand3_RX_eLNA_IDX,
+ UMTSBand4_RX_eLNA_IDX,
+ UMTSBand5_RX_eLNA_IDX,
+ UMTSBand6_RX_eLNA_IDX,
+ UMTSBand7_RX_eLNA_IDX,
+ UMTSBand8_RX_eLNA_IDX,
+ UMTSBand9_RX_eLNA_IDX,
+ UMTSBand10_RX_eLNA_IDX,
+ UMTSBand11_RX_eLNA_IDX,
+ UMTSBand12_RX_eLNA_IDX,
+ UMTSBand13_RX_eLNA_IDX,
+ UMTSBand14_RX_eLNA_IDX,
+ UMTSBand15_RX_eLNA_IDX,
+ UMTSBand16_RX_eLNA_IDX,
+ UMTSBand17_RX_eLNA_IDX,
+ UMTSBand18_RX_eLNA_IDX,
+ UMTSBand19_RX_eLNA_IDX,
+ UMTSBand20_RX_eLNA_IDX
+ },
+ { /*RxdElnaIdx[20]*/
+ UMTSBand1_RXD_eLNA_IDX,
+ UMTSBand2_RXD_eLNA_IDX,
+ UMTSBand3_RXD_eLNA_IDX,
+ UMTSBand4_RXD_eLNA_IDX,
+ UMTSBand5_RXD_eLNA_IDX,
+ UMTSBand6_RXD_eLNA_IDX,
+ UMTSBand7_RXD_eLNA_IDX,
+ UMTSBand8_RXD_eLNA_IDX,
+ UMTSBand9_RXD_eLNA_IDX,
+ UMTSBand10_RXD_eLNA_IDX,
+ UMTSBand11_RXD_eLNA_IDX,
+ UMTSBand12_RXD_eLNA_IDX,
+ UMTSBand13_RXD_eLNA_IDX,
+ UMTSBand14_RXD_eLNA_IDX,
+ UMTSBand15_RXD_eLNA_IDX,
+ UMTSBand16_RXD_eLNA_IDX,
+ UMTSBand17_RXD_eLNA_IDX,
+ UMTSBand18_RXD_eLNA_IDX,
+ UMTSBand19_RXD_eLNA_IDX,
+ UMTSBand20_RXD_eLNA_IDX
+ }
+};
+#endif//IS_3G_ELNA_IDX_SUPPORT
+
+#if IS_3G_FDD_INDICATION_FOR_AP_CLOCK_HOPPING_SUPPORT
+UMTS_RF_INTERFERENCE_FREQUENCY_T UMTS_RF_INTERFERENCE_FREQUENCY_PCORE =
+{
+ {
+ {/*Table0*/
+ { /*groupA*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ },
+ { /*groupB*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ }
+ },
+ {/*Table1*/
+ { /*groupA*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ },
+ { /*groupB*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ }
+ },
+ {/*Table2*/
+ { /*groupA*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ },
+ { /*groupB*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ }
+ },
+ {/*Table3*/
+ { /*groupA*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ },
+ { /*groupB*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ }
+ },
+ {/*Table4*/
+ { /*groupA*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ },
+ { /*groupB*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ }
+ },
+ {/*Table5*/
+ { /*groupA*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ },
+ { /*groupB*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ }
+ },
+ {/*Table6*/
+ { /*groupA*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ },
+ { /*groupB*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ }
+ },
+ {/*Table7*/
+ { /*groupA*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ },
+ { /*groupB*/
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF},
+ {0xFFFF,0xFFFF}
+ }
+ }
+ }, UMTS_RF_INTERFERE_CHECK_CONFIGURE(SetDefault)
+};
+#endif
+
+
+#if UL1CUSTOM_DRDI_ENABLE
+ kal_bool isWcdmaDrdiEnable = KAL_TRUE;
+#else
+ kal_bool isWcdmaDrdiEnable = KAL_FALSE;
+#endif
diff --git a/mcu/interface/l1/ul1/internal/ehlhwsim_struct.h b/mcu/interface/l1/ul1/internal/ehlhwsim_struct.h
new file mode 100644
index 0000000..3779100
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ehlhwsim_struct.h
@@ -0,0 +1,104 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * uhlhwsim_struct.h
+ *
+ * Project:
+ * --------
+ * U4G adaptor
+ *
+ * Description:
+ * ------------
+ * File that contains UMTS high-level (VRf) data structure for HWSIM. This file
+ * is used by u4g_ehlhwsim.h.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+ * Included header files
+ *******************************************************************************/
+#ifndef _u4g_ehlHWSIM_STRUCT_H
+#define _u4g_ehlHWSIM_STRUCT_H
+
+#if defined(__UNITE_SPLIT_SYSTEM_TARGET_SIDE__) || defined(__UESIM_KS_FPGA_SIDE__)
+#include "common.h"
+#endif
+
+#include "kal_public_api.h"
+#include "evrf_hl_intf.h"
+
+
+typedef struct u4g_ehlhwsim_dl_data_tag
+{
+ Evrf_rxFilter_t rx_filter;
+} u4g_ehlhwsim_dl_data_t;
+
+
+
+typedef struct u4g_ehlhwsim_dl_resource_req_tag
+{
+ Evrf_rxFilter_t rx_filter;
+} u4g_ehlhwsim_dl_resource_req_t;
+
+typedef struct u4g_ehlhwsim_ul_data_req_struct_tag
+{
+ int dummy;
+} u4g_ehlhwsim_ul_data_req_struct_t;
+
+typedef struct u4g_ehlhwsim_ul_resource_req_tag
+{
+ Evrf_txFilter_t tx_filter;
+ Evrf_hl_txPayloadObject_t txPayLoadObject;
+#if defined(__UESIM_KS_FPGA_SIDE__)
+ UINT32 padding2;
+#endif
+} u4g_ehlhwsim_ul_resource_req_t;
+
+#endif /* _UHLHWSIM_STRUCT_H */
diff --git a/mcu/interface/l1/ul1/internal/hal_ul1_def_internal.h b/mcu/interface/l1/ul1/internal/hal_ul1_def_internal.h
new file mode 100644
index 0000000..6f9992b
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/hal_ul1_def_internal.h
@@ -0,0 +1,166 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * hal_ul1_def_internal.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * This file contains common typedef, definition prototypes exported by L1 for MMI/Middleware
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _HAL_UL1_DEF_H_internal
+#define _HAL_UL1_DEF_H_internal
+
+#if defined(MT6280_S00) //MT6280E1
+
+#define MTCMOS_HSPASYS_1_MODE 1 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_2_MODE 1
+#define MTCMOS_HSPASYS_3_MODE 1
+#define MTCMOS_HSPASYS_4_MODE 1
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_2_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 1
+
+#elif defined(MT6280_S01) //MT6280E2
+
+#define MTCMOS_HSPASYS_1_MODE 1 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_2_MODE 1
+#define MTCMOS_HSPASYS_3_MODE 0
+#define MTCMOS_HSPASYS_4_MODE 0
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_2_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 1
+
+#elif defined(MT6589_S00) //MT6589E1
+
+#define MTCMOS_HSPASYS_1_MODE 1 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_2_MODE 1
+#define MTCMOS_HSPASYS_3_MODE 0
+#define MTCMOS_HSPASYS_4_MODE 0
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 3
+#define MTCMOS_HSPASYS_2_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 3
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 2
+
+#elif defined(MT6572_S00) //MT6572E1
+
+#define MTCMOS_HSPASYS_1_MODE 0 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_3_MODE 0
+#define MTCMOS_HSPASYS_4_MODE 0
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 2
+
+#elif defined(MT6582_S00) //MT6582E1
+
+#define MTCMOS_HSPASYS_1_MODE 0 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_3_MODE 0
+#define MTCMOS_HSPASYS_4_MODE 0
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 2
+
+#elif defined(MT6290_S00) || defined(MT6290_S01) || defined(MT6595_S00) // MT6290E1 || MT6290E2 || MT6595_S00
+
+#define MTCMOS_HSPASYS_1_MODE 1 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_2_MODE 1
+#define MTCMOS_HSPASYS_3_MODE 0
+#define MTCMOS_HSPASYS_4_MODE 0
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_2_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 3
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 2
+
+#endif
+
+#endif
+
+
+
+
diff --git a/mcu/interface/l1/ul1/internal/nrhwsim_struct.h b/mcu/interface/l1/ul1/internal/nrhwsim_struct.h
new file mode 100644
index 0000000..936a38a
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/nrhwsim_struct.h
@@ -0,0 +1,54 @@
+/***************************************************************************
+ * Copyright (c) 2018 MediaTek Inc. All Rights Reserved.
+ * --------------------
+ * This software is protected by copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc.
+ ***************************************************************************
+ *
+ * $Id: $
+ * $Revision: $
+ * $DateTime: $
+ *
+ *************************************************************************
+ *
+ * File Description
+ * ----------------
+ *
+ *
+ ***************************************************************************/
+/*******************************************************************************
+ * Included header files
+ *******************************************************************************/
+#ifndef NR_HWSIM_STRUCT_H
+#define NR_HWSIM_STRUCT_H
+
+#include "kal_public_api.h"
+#include "nrvrf_intf.h"
+
+
+typedef struct NrHwsimDlData_tag
+{
+ Nrvrf_rxFilter_t rx_filter;
+} NrHwsimDlData_t;
+
+
+
+typedef struct NrHwsimDlResourceReq_tag
+{
+ Nrvrf_rxFilter_t rx_filter;
+} NrHwsimDlResourceReq_t;
+
+typedef struct NrHwsimUlDataReq_tag
+{
+ int dummy;
+} NrHwsimUlDataReq_t;
+
+typedef struct NrHwsimUlResourceReq_tag
+{
+ Nrvrf_txFilter_t tx_filter;
+ Nrvrf_txPayloadObject_t txPayLoadObject;
+} NrHwsimUlResourceReq_t;
+
+#endif /* NR_HWSIM_STRUCT_H */
diff --git a/mcu/interface/l1/ul1/internal/uhlhwsim_struct.h b/mcu/interface/l1/ul1/internal/uhlhwsim_struct.h
new file mode 100644
index 0000000..fb3f27d
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/uhlhwsim_struct.h
@@ -0,0 +1,570 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * uhlhwsim_struct.h
+ *
+ * Project:
+ * --------
+ * U4G adaptor
+ *
+ * Description:
+ * ------------
+ * File that contains UMTS high-level (VRf) data structure for HWSIM. This file
+ * is used by uhlhwsim.h.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+ * Included header files
+ *******************************************************************************/
+#ifndef _UHLHWSIM_STRUCT_H
+#define _UHLHWSIM_STRUCT_H
+
+#include "kal_public_api.h"
+
+/*****************************************************************************
+* Definitions
+*****************************************************************************/
+//#define TTS_OF_2MS TTS_OF_A_ECHIP*30720/500
+#define TTS_OF_2MS 307200/5
+#define TTS_OF_10MS 307200
+
+/* These are temporary defined as there exist no IRQ codes for C2K */
+#define IRQ_EVENT_TIMER_CODE OSC_ISR_SRC_CUSTOM7
+
+#define U3G_SLOT_MAX_WRAP_VALUE 16
+#define UHLHWSIM_MAX_PCCPCH_DATA_SIZE 39
+#define UHLHWSIM_MAX_FOUND_CELLS 8
+#define UHLHWSIM_MAX_UL_CELLS 2
+#define UHLHWSIM_MAX_TRCH 8
+#define UHLHWSIM_MAX_SCCPCH 5
+#define UHLHWSIM_MAX_DL_UARFCNS 4
+#ifdef __UE_SIMULATOR__
+#define UHLHWSIM_MAX_UL_DATA 829 /* Maximum UL transport block array size. Matches ul1_cnst.h in mcu/interface/ul1_interface */
+#else
+/* Used in UL1B unit test only.*/
+#define UHLHWSIM_MAX_UL_DATA (829/4)
+#endif
+#define UHLHWSIM_MAX_SFN 4096
+#define UHLHWSIM_MAX_SUB_FRAME 5
+#ifdef __UE_SIMULATOR__
+#define UHLHWSIM_MAX_HS_PDU_SIZE_IN_BITS (42192)
+#else
+/* Used in UL1B unit test only.*/
+#define UHLHWSIM_MAX_HS_PDU_SIZE_IN_BITS (42192/16)
+#endif
+#define UHLHWSIM_MAX_HS_PDU_SIZE_IN_BYTES (((UHLHWSIM_MAX_HS_PDU_SIZE_IN_BITS+32+31)/32)*4) /* 42192/8 = 5274 Bytes */
+#define UHLHWSIM_MAX_EDCH_TB_SIZE (23000/8) /* s according to HW spec max tb size is 22996 bits (Rel-8)*/
+#ifdef __UE_SIMULATOR__
+#define UHLHWSIM_MAX_DL_DATA_SIZE 1150
+#else
+/* Used in UL1B unit test only.*/
+/* MSCComposer crashed when uhlhwsim_dl_data_ind_struct size too big.*/
+#define UHLHWSIM_MAX_DL_DATA_SIZE 575/2
+#endif
+
+
+/*******************************************************************************
+ * Global Declarations
+ ******************************************************************************/
+typedef kal_uint16 uhlhwsim_dl_uarfcn_t;
+typedef kal_uint16 uhlhwsim_num_uarfcn_t;
+typedef kal_uint16 uhlhwsim_num_cell_obj_t;
+typedef kal_int32 uhlhwsim_dl_power_t;
+typedef kal_uint16 uhlhwsim_cell_psc_t;
+typedef kal_uint16 uhlhwsim_sfn_t;
+typedef kal_uint8 uhlhwsim_tb_data_t;
+typedef kal_uint8 uhlhwsim_sccpch_num_t;
+
+typedef kal_int32 uhlhwsim_ul_power_t;
+typedef kal_uint16 uhlhwsim_ul_uarfcn_t;
+typedef kal_uint16 uhlhwsim_ul_tfci_t;
+typedef kal_uint16 uhlhwsim_ul_trch_id_t;
+typedef kal_uint32 uhlhwsim_ul_tb_size_t;
+typedef kal_uint32 uhlhwsim_ul_tb_cnt;
+typedef kal_uint16 uhlhwsim_ul_code_type_t;
+typedef kal_uint16 uhlhwsim_ul_tti_t;
+typedef kal_uint16 uhlhwsim_ul_crc_size_t;
+typedef kal_uint16 uhlhwsim_no_frames_t;
+typedef kal_uint16 uhlhwsim_ul_num_trch_t;
+
+typedef kal_uint16 uhlhwsim_dl_tti_t;
+typedef kal_uint16 uhlhwsim_dl_trch_id_t;
+typedef kal_uint32 uhlhwsim_dl_tb_cnt_t;
+typedef kal_uint16 uhlhwsim_dl_tb_size_t;
+typedef kal_uint8 uhlhwsim_dl_tfci_t;
+typedef kal_uint8 uhlhwsim_no_of_trch_t;
+typedef kal_uint8 uhlhwsim_data_t;
+typedef kal_uint16 uhlhwsim_num_data_t;
+typedef kal_uint16 uhlhwsim_cfn_t;
+
+typedef kal_uint8 uhlhwsim_sub_frame_t;
+typedef kal_uint8 uhlhwsim_cqi_t;
+typedef kal_uint16 uhlhwsim_hrnti_t;
+typedef kal_uint32 uhlhwsim_ovsf_t;
+typedef kal_uint8 uhlhwsim_sf_t;
+
+typedef kal_uint8 uhlhwsim_tb_size_index_t; /**< Transport-block size information (6 bits) 25.212 sec 4.6 */
+typedef kal_uint8 uhlhwsim_special_inform_type_t; /**< Special Information type (6 bits) 25.212 sec 4.6A */
+typedef kal_uint8 uhlhwsim_special_inform_t; /**< Special Information (7 bits) 25.212 sec 4.6A */
+
+typedef kal_uint16 uhlhwsim_ul_etfci_t;
+typedef kal_uint8 uhlhwsim_ag_value_t;
+typedef kal_bool uhlhwsim_cqi_valid_t;
+typedef kal_uint8 uhlhwsim_prach_signature_t;
+typedef kal_uint8 uhlhwsim_prach_access_slot_t;
+
+typedef enum
+{
+ UHLHWSIM_NOT_PRESENT = 0,
+ UHLHWSIM_PRESENT = 1
+} uhlhwsim_present_t;
+
+typedef enum
+{
+ UHLHWSIM_FRAME_3G_10MS,
+ UHLHWSIM_FRAME_HSPA_2MS
+} uhlhwsim_frame_duration_t;
+
+typedef enum
+{
+ UHLHWSIM_DISABLED = 0,
+ UHLHWSIM_ENABLED = 1
+} uhlhwsim_trch_enabled_t;
+
+typedef enum
+{
+ UHLHWSIM_DL_CRC_OK = 0,
+ UHLHWSIM_DL_CRC_ERROR = 1
+} uhlhwsim_crc_statuc_t;
+
+
+typedef enum
+{
+ UHLHWSIM_HARQ_NACK = 0,
+ UHLHWSIM_HARQ_ACK = 1
+}uhlhwsim_ack_nack_info_t;
+
+typedef enum
+{
+ UHLHWSIM_HARQ_INVALID = 0,
+ UHLHWSIM_HARQ_VALID = 1
+}uhlhwsim_harq_valid_t;
+
+typedef enum
+{
+ UHLHWSIM_DL_OK_CRC_ERROR = 0,
+ UHLHWSIM_DL_OK_CRC_OK = 1
+} uhlhwsim_crc_ok_statuc_t;
+
+typedef enum
+{
+ UHLHWSIM_HSDPA_SSCH_TYPE1,
+ UHLHWSIM_HSDPA_SSCH_TYPE2,
+ UHLHWSIM_HSDPA_SSCH_TYPE3
+} uhlhwsim_hsdpa_scch_type_t;
+
+typedef enum
+{
+ UHLHWSIM_HSDPA_TYPE_ONE_QPSK,
+ UHLHWSIM_HSDPA_TYPE_ONE_16QAM,
+ UHLHWSIM_HSDPA_TYPE_ONE_64QAM
+} uhlhwsim_hsdpa_mod_schem_type_one_t;
+
+typedef enum
+{
+ UHLHWSIM_HSDPA_TYPE_TWO_QPSK,
+ UHLHWSIM_HSDPA_TYPE_TWO_OTHERWISE
+} uhlhwsim_hsdpa_mod_schem_type_two_t;
+
+
+typedef enum
+{
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_0,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_1,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_2,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_3,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_4,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_5,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_6,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_7,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_INVALID
+} uhlhwsim_hsdpa_harq_process_id_t;
+
+
+
+typedef enum
+{
+ UHLHWSIM_HSDPA__REDUNDAN_VER_0,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_1,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_2,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_3,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_4,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_5,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_6,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_7,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_INVALID
+}uhlhwsim_hsdpa_rv_t;
+
+typedef enum
+{
+ UHLHWSIM_HSDPA_NEW_DATA_TOGGLE_0,
+ UHLHWSIM_HSDPA_NEW_DATA_TOGGLE_1,
+ UHLHWSIM_HSDPA_NEW_DATA_INVALID
+}uhlhwsim_hsdpa_new_data_t;
+
+
+typedef enum {
+ UHLHWSIM_EDCH_INITIAL_TRANS,
+ UHLHWSIM_EDCH_FIRST_RETRANS,
+ UHLHWSIM_EDCH_SECOND_RETRANS,
+ UHLHWSIM_EDCH_SUBSEQUENT_RETRANS
+} uhlhwsim_edch_rsn_t;
+
+
+typedef enum
+{
+ UHLHWSIM_EDCH__NOT_HAPPY = 0, /**< NOT OK!!!! */
+ UHLHWSIM_EDCH__HAPPY = 1 /**< OK :-) */
+} uhlhwsim_edch_happy_bit_t;
+
+typedef enum
+{
+ UHLHWSIM__ALL_HARQ_PROCESSES = 0,
+ UHLHWSIM__PER_HARQ_PROCESS = 1
+} uhlhwsim_ag_scope_t;
+
+
+
+typedef enum
+{
+ UHLHWSIM_EHICH_HARQ_NACK_NON_SERVING = 0,
+ UHLHWSIM_EHICH_HARQ_ACK = 1,
+ UHLHWSIM_EHICH_HARQ_NACK_SERVING = 0xffffffff /* -1 to make ATEC decode */
+} uhlhwsim_harq_indcator_type_t;
+
+
+typedef struct uhlhwsim_sibTag_tag
+{
+ kal_uint32 seg_Rep;
+ kal_uint32 seg_Pos;
+} uhlhwsim_sibTag_t;
+
+typedef struct
+{
+ uhlhwsim_ovsf_t ccs; /**< Channelization-code-set information (7 bits) 25.212 sec 4.6 */
+ uhlhwsim_hsdpa_mod_schem_type_one_t modulation_scheme; /**< Modulation scheme information (1 bit) 25.212 sec 4.6 */
+ uhlhwsim_tb_size_index_t tb_size_index; /**< Transport-block size information (6 bits) 25.212 sec 4.6 */
+ uhlhwsim_hsdpa_harq_process_id_t harq_process_id; /**< Hybrid-ARQ process information (3 bits) 25.212 sec 4.6 */
+ uhlhwsim_hsdpa_rv_t redundancy_ver; /**< Redundancy and constellation version (3 bits) 25.212 sec 4.6 */
+ uhlhwsim_hsdpa_new_data_t new_data; /**< New Data indicator (1 bit) 25.212 sec 4.6 */
+} uhlhwsim_hsdpa_scch_data_type1_t;
+
+typedef struct
+{
+ uhlhwsim_ovsf_t ccs; /**< Channelization-code-set information (7 bits) 25.212 sec 4.6A */
+ uhlhwsim_hsdpa_mod_schem_type_two_t modulation_scheme; /**< Modulation scheme information (1 bit) 25.212 sec 4.6A */
+ uhlhwsim_special_inform_type_t special_info_type; /**< Special Information type (6 bits) 25.212 sec 4.6A */
+ uhlhwsim_special_inform_t special_info; /**< Special Information (7 bits) 25.212 sec 4.6A */
+} uhlhwsim_hsdpa_scch_data_type2_t;
+
+typedef union
+{
+ uhlhwsim_hsdpa_scch_data_type1_t data_type1;
+ uhlhwsim_hsdpa_scch_data_type2_t data_type2;
+} uhlhwsim_hsdpa_scch_data_t;
+
+
+typedef struct uhlhwsim_dl_resource_req_tag
+{
+ /*if num_dl_uarfcn is unknown and set to 0, no matching will be done at the NW and all available UARFCN will be returned */
+ uhlhwsim_num_uarfcn_t num_dl_uarfcn;
+ uhlhwsim_dl_uarfcn_t dl_uarfcn[UHLHWSIM_MAX_DL_UARFCNS];
+} uhlhwsim_dl_resource_req_t;
+
+
+typedef struct uhlhwsim_cell_info_tag
+{
+ uhlhwsim_dl_uarfcn_t dl_uarfcn;
+ uhlhwsim_cell_psc_t psc;
+ uhlhwsim_dl_power_t rssi;
+ uhlhwsim_dl_power_t rscp;
+ uhlhwsim_sfn_t sfn;
+
+
+ struct {
+ uhlhwsim_present_t status_pccpch_present;
+ uhlhwsim_sibTag_t sib_tag_info;
+ uhlhwsim_tb_data_t sib_data[UHLHWSIM_MAX_PCCPCH_DATA_SIZE];
+ } pccpchCnf;
+
+ uhlhwsim_sccpch_num_t no_sccpch;
+
+ struct
+ {
+ uhlhwsim_dl_tfci_t tfci;
+ uhlhwsim_sf_t sf;
+ uhlhwsim_ovsf_t ovsf;
+ uhlhwsim_no_of_trch_t no_of_trch;
+ struct
+ {
+ uhlhwsim_trch_enabled_t status_trch_enabled;
+ uhlhwsim_crc_statuc_t crc_status;
+ uhlhwsim_dl_tti_t tti;
+ uhlhwsim_dl_trch_id_t trch_id;
+ uhlhwsim_dl_tb_cnt_t tb_cnt;
+ uhlhwsim_dl_tb_size_t tb_size;
+ } trch[UHLHWSIM_MAX_TRCH];
+ uhlhwsim_num_data_t num_data;
+ uhlhwsim_data_t data[UHLHWSIM_MAX_DL_DATA_SIZE];
+ } sccpch[UHLHWSIM_MAX_SCCPCH];
+
+ struct
+ {
+ uhlhwsim_dl_tfci_t tfci;
+ uhlhwsim_cfn_t cfn;
+ uhlhwsim_no_of_trch_t no_of_trch;
+ struct
+ {
+ uhlhwsim_trch_enabled_t status_trch_enabled;
+ uhlhwsim_crc_statuc_t crc_status;
+ uhlhwsim_dl_tti_t tti;
+ uhlhwsim_dl_trch_id_t trch_id;
+ uhlhwsim_dl_tb_cnt_t tb_cnt;
+ uhlhwsim_dl_tb_size_t tb_size;
+ uhlhwsim_data_t tb_data[UHLHWSIM_MAX_DL_DATA_SIZE];
+ } trch[UHLHWSIM_MAX_TRCH];
+ } dpch;
+
+} uhlhwsim_cell_info_t;
+
+typedef struct uhlhwsim__rxCellObj_tag
+{
+ uhlhwsim_cell_info_t cell_info;
+} uhlhwsim_rx_cell_obj_t;
+
+typedef struct uhlhwsim_hspa_cell_info_tag
+{
+ uhlhwsim_dl_uarfcn_t dl_uarfcn;
+ uhlhwsim_cell_psc_t psc;
+ uhlhwsim_dl_power_t rssi;
+ uhlhwsim_dl_power_t rscp;
+ uhlhwsim_sfn_t sfn;
+
+ struct
+ {
+ uhlhwsim_present_t status_hsdsch_present;
+ uhlhwsim_sfn_t sfn; //Frame Number
+ uhlhwsim_sub_frame_t sub_frame; //Subframe Number
+
+ uhlhwsim_hrnti_t h_rnti;
+
+
+ uhlhwsim_ovsf_t ovsf;
+ uhlhwsim_hsdpa_scch_type_t hsscch_type; /**< Type of HS-SCCH */
+ uhlhwsim_hsdpa_scch_data_t hsscch_data; /**< Data carried on the HS-SCCH */
+
+ uhlhwsim_crc_ok_statuc_t crc_ok; // True=correct. False=wrong.
+ uhlhwsim_dl_tb_size_t tb_size;
+ uhlhwsim_data_t data[UHLHWSIM_MAX_HS_PDU_SIZE_IN_BYTES];
+ } hsdsch;
+
+ struct
+ {
+ uhlhwsim_present_t status_eagch_present;
+ uhlhwsim_sfn_t sfn; //Frame Number
+ uhlhwsim_sub_frame_t sub_frame; //Subframe Number
+ uhlhwsim_ag_value_t ag_value;
+ uhlhwsim_ag_scope_t ag_scope;
+ uhlhwsim_hsdpa_harq_process_id_t harq_process_id;
+ } eagch;
+
+ struct
+ {
+ uhlhwsim_present_t status_ehich_present;
+ uhlhwsim_harq_indcator_type_t harq_indcator;
+ uhlhwsim_hsdpa_harq_process_id_t harq_process_id;
+ } ehich;
+
+ struct
+ {
+ uhlhwsim_present_t status_fdpch_present;
+ } fdpch;
+
+
+} uhlhwsim_hspa_cell_info_t;
+
+typedef struct uhlhwsim__rxHspaCellObj_tag
+{
+ uhlhwsim_hspa_cell_info_t hspa_cell_info;
+} uhlhwsim_rx_hspa_cell_obj_t;
+
+
+
+typedef struct uhlhwsim_dl_data_tag
+{
+ uhlhwsim_num_cell_obj_t num_cell_obj;
+ uhlhwsim_rx_cell_obj_t cell_obj[UHLHWSIM_MAX_FOUND_CELLS];
+ uhlhwsim_rx_hspa_cell_obj_t hspa_cell_obj[UHLHWSIM_MAX_FOUND_CELLS];
+} uhlhwsim_dl_data_t;
+
+
+typedef struct _uhlhwsim_dl_data_ind_struct
+{
+ uhlhwsim_dl_data_t dl_data;
+} uhlhwsim_dl_data_ind_struct;
+
+
+typedef struct
+{
+ uhlhwsim_ul_uarfcn_t ul_arfcn;
+ uhlhwsim_ul_power_t ul_power;
+ uhlhwsim_cell_psc_t psc;
+ uhlhwsim_ul_tfci_t tfci;
+ uhlhwsim_sfn_t sfn;
+ //uhlhwsim_frame_duration_t frame_duration;
+ uhlhwsim_no_frames_t no_frames;
+ struct
+ {
+ uhlhwsim_ul_trch_id_t trch_id;
+ uhlhwsim_ul_tb_size_t tb_size;
+ uhlhwsim_ul_tb_cnt tb_cnt;
+ uhlhwsim_ul_code_type_t code_type;
+ uhlhwsim_ul_tti_t tti;
+ uhlhwsim_ul_crc_size_t crc_size;
+ uhlhwsim_tb_data_t tb_data[UHLHWSIM_MAX_UL_DATA];
+ } tbs;
+} uhlhwsim_prach_t;
+
+typedef struct
+{
+ uhlhwsim_ul_uarfcn_t ul_arfcn;
+ uhlhwsim_ul_power_t ul_power;
+ uhlhwsim_cell_psc_t psc;
+ uhlhwsim_ul_tfci_t tfci;
+ uhlhwsim_cfn_t cfn;
+ uhlhwsim_cfn_t sfn;
+ //uhlhwsim_frame_duration_t frame_duration;
+ uhlhwsim_ul_num_trch_t num_trch;
+ struct
+ {
+ uhlhwsim_ul_trch_id_t trch_id;
+ uhlhwsim_ul_tb_size_t tb_size;
+ uhlhwsim_ul_tb_cnt tb_cnt;
+ uhlhwsim_ul_tti_t tti;
+ uhlhwsim_tb_data_t tb_data[UHLHWSIM_MAX_UL_DATA];
+ } trch[UHLHWSIM_MAX_TRCH];
+} uhlhwsim_pdpch_t;
+
+typedef struct
+{
+ uhlhwsim_ul_uarfcn_t ul_arfcn;
+ uhlhwsim_cfn_t cfn;
+ uhlhwsim_sub_frame_t sub_frame;
+ uhlhwsim_cqi_valid_t cqi_valid;
+ uhlhwsim_cqi_t primary_cqi_value;
+ uhlhwsim_cqi_t secondary_cqi_value;
+ uhlhwsim_harq_valid_t primary_harq_info_valid;
+ uhlhwsim_ack_nack_info_t primary_harq_info_ind;
+ uhlhwsim_harq_valid_t secondary_harq_info_valid;
+ uhlhwsim_ack_nack_info_t secondary_harq_info_ind;
+}uhlhwsim_hs_dpcch_t;
+
+
+typedef struct
+{
+ uhlhwsim_ul_uarfcn_t prach_ul_arfcn;
+ uhlhwsim_prach_signature_t prach_signature;
+ uhlhwsim_prach_access_slot_t prach_access_slot;
+} uhlhwsim_prach_preamble_t;
+typedef struct
+{
+ uhlhwsim_ul_uarfcn_t ul_arfcn;
+ uhlhwsim_ul_power_t ul_power;
+ uhlhwsim_cfn_t cfn;
+ uhlhwsim_sub_frame_t sub_frame;
+
+ uhlhwsim_edch_happy_bit_t happy_bit;
+ uhlhwsim_edch_rsn_t rsn;
+ uhlhwsim_ul_tti_t tti;
+ uhlhwsim_ul_etfci_t e_tfci;
+ uhlhwsim_ul_tb_size_t tb_size;
+ uhlhwsim_tb_data_t tb_data[UHLHWSIM_MAX_EDCH_TB_SIZE];
+} uhlhwsim_edch_t;
+
+typedef struct
+{
+ uhlhwsim_present_t prach_present;
+ uhlhwsim_prach_t prach_data;
+ uhlhwsim_present_t pdpch_present;
+ uhlhwsim_pdpch_t pdpch_data;
+ uhlhwsim_present_t hs_dpcch_present;
+ uhlhwsim_hs_dpcch_t hs_dpcch_data;
+ uhlhwsim_present_t prach_preamble_present;
+ uhlhwsim_prach_preamble_t prach_preamble;
+
+ uhlhwsim_present_t edch_present;
+ uhlhwsim_edch_t edch_data;
+} uhlhwsim_tx_cell_obj_t;
+
+
+typedef struct uhlhwsim_ul_data_tag
+{
+ uhlhwsim_num_cell_obj_t num_cell_obj;
+ uhlhwsim_tx_cell_obj_t cell_obj[UHLHWSIM_MAX_UL_CELLS];
+} uhlhwsim_ul_data_t;
+
+
+typedef struct _uhlhwsim_ul_data_req_struct
+{
+ uhlhwsim_ul_data_t ul_data;
+} uhlhwsim_ul_data_req_struct;
+
+#endif /* _UHLHWSIM_STRUCT_H */
diff --git a/mcu/interface/l1/ul1/internal/ul1_cnst.h b/mcu/interface/l1/ul1/internal/ul1_cnst.h
new file mode 100644
index 0000000..1b4fab3
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ul1_cnst.h
@@ -0,0 +1,485 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_cnst.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * Layer 1 related constant and enum definitions for MediaTek WCDMA software
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _UL1_CNST_H
+#define _UL1_CNST_H
+
+#include "ul1_protected_cnst.h"
+
+#define UL1_SIM_IDX_INVALID ( 0xFF )
+
+/*-------- BCH related constant ----------------------*/
+#define FDD_MAX_SIB_PATTERN 31 /* The maximum number of BCH SIB blocks */
+#define FDD_MAX_SIB_SEG_COUNT 16 /* The maximum number of segments in 1 BCH SIB */
+
+/*-------- TrCH related constant (For UL/DL 384Kbps capability) ----------------------*/
+/* MAUI_02850564 : According to spec 25.306 and MTK implementation, FDD_MAX_DL_DATA should be 956 bytes :
+ FDD_MAX_DL_DATA = 6400 + 24*32 (CRC bits*MaxTBNum) + 7*32 (max bit offset for each TB)
+ + 7*32 (max byte alignment for each TB) + 4*8 (4 bytes report header) = 7648 bits = 956 bytes.
+ But we have seen an overspec case : PS TrCH 336*24 + SRB TrCH 148*1, thus define FDD_MAX_DL_DATA as 1150 bytes.
+ FDD_MAX_DL_DATA = [PS part] 336*24 + 24*24 + 7*24 + 7*24
+ [SRB part] + 148*1 + 24*1 + 7*1 + 7*1
+ + 4*8 (4 bytes report header) = 9194 bits = 1149.25 bytes. */
+#define FDD_MAX_DL_DATA 1150 /* Maximum DL transport block array size. */
+#define FDD_MAX_TRCH_NUM 8 /* Maximum Simultaneous TrCHs */
+#define FDD_MAX_DL_TB 32 /* Maximum simultaneous DL TBs */
+#define FDD_MAX_DL_TFC 128 /* Maximum number of TFCs per DL CCTrCH */
+#define FDD_MAX_DL_TRCH 32 /* Maximum number of DL TrCH */
+#define FDD_MAXTF 32 /* Maximum number of TF per UL or DL TrCH TFS */
+#define FDD_MAXFACHPCH 8 /* Maximum number of TrCHs per S-CCPCH CCTrCH */
+#define FDD_MAX_UL_TFC 64 /* Maximum number of TFCs per UL CCTrCH */
+#define FDD_MAX_UL_TB 16 /* Maximum simultaneous DUL TBs */
+#define FDD_MAX_UL_TFs 32 /* Maximum numbre of TFs per UL CCTrCH */
+#define FDD_MAX_UL_TRCH 32 /* Maximum number of UL TrCH */
+
+/*-------- PhyCh related constant (For UL/DL 384Kbps capability) ----------------------*/
+#define FDD_MAX_TGPS 6 /* Maximum number of TGPS sequences */
+#define FDD_MAX_PENDING_TGPS_NUM 5 /* Maximum number of pending confiuration for one TGPS */
+#define FDD_MAX_TGMP_NUM 5 /* Maximum number of TGMP */
+#define FDD_MAX_ASC 8 /* Maximum access service class number */
+#define FDD_MAX_DLDPCH 3 /* Maximum number of physical channel codes per DL DPCH CCTrCH */
+#define FDD_MAX_ULDPCH 6 /* Maximum number of physical channel codes per UL DPCH CCTrCH */
+#define FDD_MAX_RL 8 /* Maximum number of DPCH radio links in active set */
+
+#ifdef __UMTS_R10__
+
+#ifdef __MULTI_CARRIER_HSDPA__ /* __MULTI_CARRIER_HSDPA__ = 3 or 4 */
+#define FDD_MAX_ADDI_DC_HSDPA ( __MULTI_CARRIER_HSDPA__ - 2 ) /* [R10] The maximum additional dc-hsdpa frequency */
+#else /*__MULTI_CARRIER_HSDPA__*/
+#define FDD_MAX_ADDI_DC_HSDPA 1 /* default value is 1. */
+#endif /*__MULTI_CARRIER_HSDPA__*/
+
+#endif
+
+
+
+/*-------- Measurement related constant ----------------------*/
+#ifdef __GEMINI__
+#define FDD_MAX_FREQ_RANGE 15 /* Max size of frequency ranges for frequency scan.
+ Extend range number for Enhanced Freq Scan in Gemini2.0.*/
+#else
+#define FDD_MAX_FREQ_RANGE 8 /* Max size of frequency ranges for frequency scan. */
+#endif /*__GEMINI__*/
+
+#define FDD_MAX_FREQ_EXCLUDE 13 /*Max possible UARFCNs per PLMN*/
+#define FDD_MAX_FREQ_LIST 36 /* Max size of stored frequency list for frequency scan */
+#define FDD_MAX_PREFERRED_PSC 96 /* Max number of preferred cells on 1 frequency for frequency scan */
+#define FDD_MAX_NUM_MEAS_CELL 32 /* Max number of reported cells in the measurement cell indication primitive */
+#define FDD_MAX_NUM_MEASURED_CELL 96 /* Max number of monitored cells in the measurement cell request primitive */
+#define FDD_MAX_NUM_SFN_CELL 12 /* Max number of cells whose SFN will be read by L1 when nc_nbr_dch=0 */
+
+#ifdef __UMTS_R9_UL1__
+#define FDD_MAX_UMTS_FREQ 4 /* Maximum number of FDD frequency supported in a UMTS UE : 1st intra + 2nd intra + inter x 2 */
+#else
+#define FDD_MAX_UMTS_FREQ 3 /* Maximum number of FDD frequency supported in a UMTS UE */
+#endif /*__UMTS_R9_UL1__*/
+
+#define FDD_MAX_RSSI_SNIFFER_SCAN_LIST 12 /* Maximum number of RSSI SNIFFER UARFCN (Add by Janet) */
+
+/*-------- Magic value related constant ----------------------*/
+#define FDD_TM_VALID 307200 /* Default value representing Tm known. 38400*8 */
+#define FDD_TM_INVALID ( -1 ) /* Default value representing Tm unknown. */
+#define FDD_OFF_VALID 4096 /* Default valure representing OFF known. */
+#define FDD_OFF_INVALID ( -1 ) /* Default value representing OFF unknown. */
+#define FDD_RSSI_INVALID ( -32768 ) /* Default value representing RSSI unknown. */
+#define FDD_RSCP_INVALID ( -32768 ) /* Default value representing RSCP unknown. */
+#define FDD_ECN0_INVALID ( -32768 ) /* Default value representing EcNo unknown. */
+#define FDD_UARFCN_INVALID 65535 /* Invalid UARFCN for setting empty freq. entry in meas. config req. */
+
+
+
+
+/*-------- BMC (CTCH) related constant ----------------------*/
+#define FDD_BMC_MAX_BITMAP_SIZE 64 /* CTCH level 2 bitmap siz */
+
+/*-------- Activation time related constant ----------------------*/
+#define FDD_CFN_IMMEDIATE (kal_int16)(-1) /* Immediate CFN activation time. */
+#define FDD_SFN_IMMEDIATE (kal_int16)(-1) /* Immediate SFN activation time. */
+
+/*-------- [R5R6] HS-DSCH related ----------------------*/
+#ifdef __MULTI_CARRIER_HSDPA__
+#define FDD_MAX_SUPPORT_CELL __MULTI_CARRIER_HSDPA__ /* Possible __MULTI_CARRIER_HSDPA__ value is 3,4 or not defined. */
+#else
+#define FDD_MAX_SUPPORT_CELL 2 /* 1 */ /*Use 3 before __MULTI_CARRIER_HSDPA__ defined in project for easy development*/
+#endif
+
+#define FDD_MAX_HS_SCCH_NUM 4
+#define FDD_MAX_HS_PROCESS_NUM 8
+#define FDD_MAX_HS_PDU_NUM_IN_FRAME 5
+#ifdef __UMTS_R7__
+#define FDD_MAX_HS_PDU_SIZE_IN_BITS 42192
+#else
+#define FDD_MAX_HS_PDU_SIZE_IN_BITS 14411
+#endif
+#define FDD_MAX_HS_PDU_SIZE_IN_BYTES (((FDD_MAX_HS_PDU_SIZE_IN_BITS+32+31)/32)*4)
+#ifdef __UMTS_R8__
+
+#define FDD_HDA_BUFF_NUM_PRI 45 // 5*8(MAX flow B * HARQ process NUM) + 5 (less mode)
+#define FDD_HDA_BUFF_NUM_SEC 8 // HARQ process NUM
+
+#define FDD_MAX_HS_PDU_BUFF_NUM 160 // for DC hsdpa
+#define FDD_HDA_BUFF_NUM (FDD_HDA_BUFF_NUM_PRI + FDD_HDA_BUFF_NUM_SEC * (FDD_MAX_SUPPORT_CELL-1))
+#else
+#define FDD_MAX_HS_PDU_BUFF_NUM 40
+#endif
+#define FDD_MAX_HS_RB_NUM 3
+#define FDD_MAX_EDCH_RL 4
+#define FDD_MAX_REF_ETFCI_NUM 8
+#define FDD_MAX_ETFC_NUM 128
+#define FDD_MIN_NTX1_10MS 8 /* 25.212 s4.4.4 */
+#define FDD_MAX_NTX1_10MS (15 - FDD_MIN_NTX1_10MS + 1)
+
+#define FDD_HS_PDU_UL1_CC_DELAY_PREALLOCATION_NUM (FDD_MAX_SUPPORT_CELL*5)
+#define FDD_PHY_HSDSCH_MAC_EV_SETUP_BIT 0
+#define FDD_PHY_HSDSCH_MAC_EV_RELEASE_BIT 1
+#define FDD_PHY_HSDSCH_MAC_EV_MODIFY_BIT 2
+#define FDD_PHY_HSDSCH_MAC_EV_RESET_BIT 3
+#define FDD_PHY_HSDSCH_MAC_EV_SETUP (0x1 << FDD_PHY_HSDSCH_MAC_EV_SETUP_BIT) /* 0x01 */
+#define FDD_PHY_HSDSCH_MAC_EV_RELEASE (0x1 << FDD_PHY_HSDSCH_MAC_EV_RELEASE_BIT) /* 0x02 */
+#define FDD_PHY_HSDSCH_MAC_EV_MODIFY (0x1 << FDD_PHY_HSDSCH_MAC_EV_MODIFY_BIT) /* 0x04 */
+#define FDD_PHY_HSDSCH_MAC_EV_RESET (0x1 << FDD_PHY_HSDSCH_MAC_EV_RESET_BIT) /* 0x08 */
+
+/*-----------Add PLMN , RAC and LAC info to Container Req---------------------------*/
+#define NUM_PLMN_INFO 3
+#define NUM_MCC_MNC 3
+
+#endif
+
diff --git a/mcu/interface/l1/ul1/internal/ul1_def.h b/mcu/interface/l1/ul1/internal/ul1_def.h
new file mode 100644
index 0000000..f0a76b0
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ul1_def.h
@@ -0,0 +1,2795 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_def.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * This file contains common typedef, definition prototypes exported by L1
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _UL1_DEF_H
+#define _UL1_DEF_H
+
+/* auto add by kw_check begin */
+#include "ul1_cnst.h"
+#include "kal_general_types.h"
+/* auto add by kw_check end */
+
+#include "gmss_public.h"
+#include "ul1_protected_def.h"
+
+
+/* ---------------------- L+W Gemini ----------------------*/
+typedef enum _UL1_SIM_INDEX_E
+{
+ UL1_SIM_1 = 0,
+#ifdef __GEMINI_WCDMA__
+ UL1_SIM_2,
+#if (GEMINI_PLUS_WCDMA >= 3)
+ UL1_SIM_3,
+#if (GEMINI_PLUS_WCDMA >= 4)
+ UL1_SIM_4,
+#endif /* GEMINI_PLUS_WCDMA >= 4 */
+#endif /* GEMINI_PLUS_WCDMA >= 3 */
+#endif /* __GEMINI_WCDMA__ */
+ UL1_SIM_NUM
+} UL1_SIM_INDEX_E;
+
+#if (GEMINI_PLUS_WCDMA > 4)
+#error "The number of SIM can't be over than 4 pieces."
+#endif
+
+/*-------------------- ADT -----------------------*/
+typedef enum _FDD_ADT_Mode_E
+{
+ FDD_ADT_NONE = 0,
+ FDD_ADT_NORMAL,
+ FDD_ADT_TALKING
+} FDD_ADT_Mode_E;
+
+/*-------- TGPS related definition ----------------------*/
+typedef enum _FDD_tgps_act_E
+{
+ FDD_TGPS_ACTIVATE, /* Activate the TGPS */
+ FDD_TGPS_DEACTIVATE /* Deactivate the TGPS */
+} FDD_tgps_act_E;
+
+typedef enum _FDD_tg_mode_E
+{
+ FDD_TG_UL, /* UL only */
+ FDD_TG_DL, /* DL only */
+ FDD_TG_UL_DL /* Both UL and DL */
+} FDD_tg_mode_E;
+
+typedef enum _FDD_tgmp_E
+{
+ FDD_TG_FDD_MEASURE, /* Inter-frequency measurement */
+ FDD_TG_GSM_RSSI, /* GSM RSSI measurement */
+ FDD_TG_GSM_BSIC_INIT, /* GSM initial BSIC */
+ FDD_TG_GSM_BSIC_CNF, /* GSM BSIC confirm */
+ FDD_TG_EUTRA, /* E-UTRA */
+ FDD_TG_TGMP_UNDEFINED
+} FDD_tgmp_E;
+
+typedef enum _FDD_tg_method_E
+{
+ FDD_TG_PUNCT, /* Puncturing. only for DL */
+ FDD_TG_HLS, /* Higher layer scheduling */
+ FDD_TG_SF_2, /* SF/2 */
+ FDD_TG_NONE /* None */
+} FDD_tg_method_E;
+
+typedef struct _FDD_tgps_info_T
+{
+ kal_uint8 tgpsi; /* TGPSI. 1 ~ 6 */
+ kal_uint8 tgcfn; /* TGCFN. 0 ~ 255 */
+ FDD_tgps_act_E status; /* Action applied to TGPS */
+ kal_bool tgps_para_valid; /* indicate if following parameter should be modifed */
+ FDD_tgmp_E purpose; /* TGMP. TGPS purpose */
+ FDD_tg_mode_E mode; /* TG mode */
+ FDD_tg_method_E ul_method; /* UL TG method */
+ FDD_tg_method_E dl_method; /* DL TG method */
+ kal_uint8 rpp; /* RPP. 0 or 1 */
+ kal_uint8 itp; /* ITP. 0 or 1 */
+ kal_uint8 dl_frame_type; /* DL TG frame type. 0 : type A. 1 : type B */
+ kal_uint8 sir1; /* DeltaSIR1. 0 ~ 30. true value is sir1/10 */
+ kal_uint8 sir_after1; /* DeltaSIRafter1. 0 ! 10. true value is sir_after1/10 */
+ kal_uint8 sir2; /* DeltaSIR1. 0 ~ 30. true value is sir2/10 */
+ kal_uint8 sir_after2; /* DeltaSIRafter1. 0 ! 10. true value is sir_after2/10 */
+ kal_uint16 tgprc; /* TGPRC. 0 ~ 511. 0 for infinity*/
+ kal_uint8 tgsn; /* TGSN. 0 ~ 14 */
+ kal_uint8 tgl1; /* TGL1. 1 ~ 14 slts */
+ kal_uint8 tgl2; /* TGL2. 1 ~ 14 slts */
+ kal_uint16 tgd; /* TGD. 15 ~ 270. 270 means TGD is undefed (only 1 TG) */
+ kal_uint8 tgpl1; /* TGPL1. 1 ~ 144 */
+ kal_uint8 tgpl2; /* TGPL2. 1 ~ 144 */
+ kal_uint8 ident_abort; /* N_IDENTIFY_ABORT. 1 ~ 128 */
+ kal_uint8 reconf_abort; /* Treconfirm_abort. 1 ~ 20. true value is divided by 2 */
+ kal_bool freq_specific_compressed_mode; /* [R10] true: tgps is not applied on serving band. */
+} FDD_tgps_info_T;
+
+typedef enum _FDD_tgps_status_E
+{
+ FDD_TGPS_ACTIVE,
+ FDD_TGPS_DEACTIVE
+} FDD_tgps_status_E;
+
+typedef struct _FDD_tgps_status_T
+{
+ kal_uint8 tgpsi; /* TGPS index */
+ kal_uint8 tgcfn; /* TGCFN. 0 ~ 255 */
+ FDD_tgps_status_E status; /* Status to be applied to TGPS */
+ kal_bool freq_specific_compressed_mode; /* [R10] true: tgps is not applied on serving band. */
+} FDD_tgps_status_T;
+
+typedef struct _FDD_tgps_status_info_T
+{
+ kal_uint8 num_tgps; /* # of TGPS status pattern */
+ kal_int16 reconf_time; /* TGPS reconfiguration CFN. -1 ~ 255. -1 means immediate */
+ FDD_tgps_status_T tgps_status[FDD_MAX_TGPS]; /* TGPS status information */
+} FDD_tgps_status_info_T;
+
+
+typedef struct _FDD_tgps_config_T
+{
+ kal_uint8 tgpsi; /* tgpsi */
+ FDD_tgmp_E tgmp; /* purpose of this tgpsi */
+ FDD_tgps_status_E status; /*tgps status at the activation time*/
+} FDD_tgps_config_T;
+
+typedef struct _FDD_p_tgps_config_T
+{
+ kal_int16 sfn; /* reconfig time of this pending tgps configuration*/
+ kal_uint8 tgps_num; /* number of tgps in this pneding tgps */
+ FDD_tgps_config_T tgps[FDD_MAX_TGPS]; /* tgps config (tgpsi, tgmp, status) */
+} FDD_p_tgps_config_T;
+
+typedef struct _FDD_tgps_config_by_tgmp_T
+{
+ kal_uint8 tgpsi; /* tgpsi for the tgmp */
+ kal_uint8 p_tgps_config_num; /* pending tgps_config num of this tgpsi */
+ kal_bool c_tgps_config_valid; /* existence of current tgps_config of this tgpsi,
+ if false, c_tgps_config is meaningless */
+ FDD_tgps_config_T c_tgps_config; /* current tgps_config of this tgpsi */
+ FDD_tgps_config_T p_tgps_config[FDD_MAX_PENDING_TGPS_NUM]; /* pending tgps config of this tgpsi */
+} FDD_tgps_config_by_tgmp_T;
+
+typedef enum _FDD_tgps_time_relationship_E
+{
+ FDD_TGPS_BEFORE,
+ FDD_TGPS_EQUAL,
+ FDD_TGPS_AFTER
+} FDD_tgps_time_relationship_E;
+
+typedef enum _FDD_tgps_complete_status_E
+{
+ FDD_TGPS_COMPLETE_OR_INACTIVE,
+ FDD_TGPS_NOT_COMPLETE
+} FDD_tgps_complete_status_E;
+
+typedef struct _FDD_tgps_complete_status_by_tgmp_T
+{
+ kal_int16 sfn; /*activation time or TGPS reconfiguration SFN,
+ range: -1-4095, -1 means immediate(only used in current tgps config)*/
+
+ FDD_tgps_complete_status_E tgps_complete_status; /* tgps complete status for that tgpsi*/
+} FDD_tgps_complete_status_by_tgmp_T;
+
+typedef struct _FDD_tgps_status_by_tgmp_T
+{
+ kal_uint8 tgmp_num; /* num of valid tgmp in the structure */
+ FDD_tgmp_E tgmp[FDD_MAX_TGMP_NUM]; /* tgmp queried */
+ kal_bool status[FDD_MAX_TGMP_NUM]; /* TRUE: if there is current or pending active and incompleted tgps for that tgmp */
+} FDD_tgps_status_by_tgmp_T;
+
+
+/* U3G */
+typedef struct _FDD_tgps_info_share_memory_T
+{
+ kal_uint8 tgpsi; /* tgpsi */
+ FDD_tgmp_E tgmp; /* purpose of this tgpsi */
+ FDD_tgps_status_E status; /* tgps status at the activation time*/
+ FDD_tgps_complete_status_E complete_status;
+} FDD_tgps_info_share_memory_T;
+
+typedef struct _FDD_tgps_param_share_memory_T
+{
+ kal_int16 sfn; /* reconfig time of this pending tgps configuration*/
+ kal_uint8 tgps_info_num; /* number of tgps in this pneding tgps */
+ FDD_tgps_info_share_memory_T tgps_info[FDD_MAX_TGPS]; /* tgps config (tgpsi, tgmp, status) */
+} FDD_tgps_param_share_memory_T;
+
+typedef struct _FDD_tgps_status_share_memory_T
+{
+ kal_uint8 tgps_param_num;
+ FDD_tgps_param_share_memory_T tgps_param[FDD_MAX_TGPS];
+} FDD_tgps_status_share_memory_T;
+/* U3G */
+
+/*-------- PhyCH related definition ----------------------*/
+typedef struct _FDD_pich_drx_T
+{
+ kal_uint8 pch_drx; /* DRX cycle length coefficient. 3 ~ 9 */
+ kal_uint8 pi_num; /* # of PI per frame. 18, 36, 72, 144 */
+ kal_uint8 pi; /* Paging Indicator index. */
+ kal_uint16 sfn_po; /* SFN of the frame containing start of PICH for the first paging occasion. */
+} FDD_pich_drx_T;
+
+#ifdef __SMART_PAGING_3G_FDD__
+typedef struct _FDD_pich_smartpaging_T
+{
+ kal_bool support_repeat; /* If true: RRCE has detected that current NW can support smart paging (has repeated paging pattern) */
+ kal_uint16 sfn_po; /* DRX parameters for PICH.(when smartpging active) */
+} FDD_pich_smartpaging_T;
+#endif
+
+typedef enum _FDD_pich_reconfig_type_E
+{
+ FDD_PCH_MODIFY, /* traditionaly PCH modify */
+ FDD_PCH_SMARTPAGE, /* to inform UL1 enable/disable SmartPaging*/
+} FDD_pich_reconfig_type_E;
+
+typedef struct _FDD_pich_info_T
+{
+ kal_bool sttd; /* If STTD is used. */
+ kal_int8 cpich_tx_power; /* CPICH TX power. -10~50 dBm */
+ kal_int8 power_offset; /* PICH power offset to CPICH. -10 ~ 5 dB */
+ kal_uint8 ovsf; /* Channelization code. 0 ~ 255 */
+ FDD_pich_drx_T pich_drx; /* DRX parameters for PICH. */
+#ifdef __SMART_PAGING_3G_FDD__
+ FDD_pich_smartpaging_T smartpaging_info;
+#endif
+#ifdef __UMTS_R7__
+ FDD_pich_drx_T pich_drx_cycle2; /* DRX parameters 2 for PICH. */
+ kal_uint16 drx_cycle2_time; /* if it's not 0. UL1 shall use pich_drx_2 for PICH receptin, else shall directly use pich_drx for PICH reception. 0~5120 ms */
+#endif /* __UMTS_R7__ */
+} FDD_pich_info_T;
+
+typedef struct _FDD_ctch_drx_level1_T
+{
+ kal_uint8 m_tti;
+ kal_uint8 start_off; /* Offset of the start of first block set k. */
+ kal_uint16 repe_period; /* Block set repetition period. */
+ kal_uint16 bmc_sm_period; /*[R6] Period of BMC scheduling message (P)
+ [Value] 1, 8, 16, 32, 64, 128, 256
+ If this value is set to 1, UL1 will receive CTCH in all CTCH allocation.
+ For R5 and R99, or for R6 but this field is not configured by the network, this value should be set to 1 */
+} FDD_ctch_drx_level1_T;
+
+typedef struct _FDD_ctch_drx_level2_T
+{
+// kal_uint8 bs_mask[32];
+// kal_uint16 bs_mask_len; /* 1 ~ 256 */
+ kal_uint8 level2_bitmap[FDD_BMC_MAX_BITMAP_SIZE];
+ kal_uint16 lenOfBitmap;
+ kal_uint8 bitmapOffset;
+ kal_uint16 sfnOfLastScheduleMsg;
+ kal_bool flush_l2;
+} FDD_ctch_drx_level2_T;
+
+typedef union _FDD_ctch_drx_level
+{
+ FDD_ctch_drx_level1_T drx_level1; /* CTCH DRX Level 1 information. */
+ FDD_ctch_drx_level2_T drx_level2; /* CTCH DRX Level 2 information. */
+} FDD_ctch_drx_level;
+
+typedef struct _FDD_ctch_drx_T
+{
+ kal_bool level1_Ind; /* True: CTCH level 1 parameters is used. */
+ FDD_ctch_drx_level ctch_drx_level; /* CTCH DRX level parameters */
+} FDD_ctch_drx_T;
+
+typedef union _FDD_pich_ctch_info_T
+{
+ FDD_ctch_drx_T ctch_drx; /* CTCH DRX information */
+ FDD_pich_info_T pich_info; /* PICH information */
+} FDD_pich_ctch_info_T;
+
+typedef struct _FDD_sccpch_info_T
+{
+ kal_uint8 ssc; /* Secondary scrambling code. 0 ~ 15 */
+ /* This value will not be used, if SCCPCH is used to carrying PCH */
+ /* if the value is equal to 0, it means primary scrambling code is used */
+ kal_bool sttd; /* True if STTD is used */
+ kal_bool pilot_exit; /* If pilot symbol exists */
+ kal_bool tfci_exit; /* If TFCI is used. */
+ kal_bool fixed_pos_ind; /* If Fixed or flexible position is used. True means Fixed */
+ kal_uint16 timing_offset; /* Frame boundary to P-CCPCH. 0 ~ 38144 by step of 256. */
+ kal_uint16 sf; /* Spreading Factor. 4 ~ 256 */
+ kal_uint16 ovsf; /* Channelization code. 0 ~ sf-1 */
+} FDD_sccpch_info_T;
+
+typedef enum _FDD_access_status_E
+{
+ FDD_AI_ACK, /* Network ACK in AICH */
+ FDD_AI_NACK, /* Network NACK in AICH */
+ FDD_AI_NOACK, /* Network no response in AICH*/
+ FDD_AI_ABORT, /* Aborted by higher layer */
+ FDD_AI_PARAMERROR, /* Access request without preliminary Data request */
+ FDD_AI_NESTEDREQUEST /* Access request before previous one finished */
+} FDD_access_status_E;
+
+typedef struct _FDD_aich_info_T
+{
+ kal_int8 power_offset; /* Power offset to CPICH. -22 ~ 5 dB */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 255*/
+ kal_bool sttd; /* Indicate if STTD is used */
+ kal_uint8 tx_timing; /* AICH transmission timie. 0 or 1 */
+} FDD_aich_info_T;
+
+typedef struct _FDD_asc_T
+{
+ kal_uint8 avail_sig_start; /* Available signature start index */
+ kal_uint8 avail_sig_end; /* Available signature end index */
+ kal_uint8 assigned_subchannel; /* Assigned subchannel number */
+ /* Bit0 represent bit b0, only 4 rightmost bit is valid */
+} FDD_asc_T;
+
+typedef struct _FDD_prach_info_T
+{
+ kal_uint16 min_sf; /* Min allowed SF. 32,64,128,256 */
+ kal_uint8 punc_limit; /* Puncturing limit. 40 ~ 100 */
+ kal_uint8 asc_num; /* # of valid ASC information in asc[]. 1 ~ 8 */
+ kal_uint8 pream_psc; /* Preamble scrambling code. 0 ~ 15 */
+ kal_uint16 avail_signature; /* Available signature. Bit string (16) */
+ /* Bit0 represent signature 0 */
+ kal_uint16 avail_subchannel; /* Available subchannels. Bit string (12)*/
+ /* Bit0 represent sub-channel 0 */
+ FDD_asc_T asc[FDD_MAX_ASC]; /* ASC information */
+} FDD_prach_info_T;
+
+typedef struct _FDD_prach_power_T
+{
+ kal_int8 max_tx_power; /* Max allowed TX power. -50 ~ 33dBm */
+ kal_int8 umts_power_class; /* UE capability*/
+ kal_int8 init_power_offset; /* SUM of "P-CPICH TX power" and "constant value" */
+ /* L1 will use this offste - CPICH_RSCP - UL_INTERFERENCE */
+ kal_uint8 power_step; /* Preamble power ramping step. 1 ~ 8dB */
+ kal_uint8 retrans_max; /* Max preamble retrans. 1 ~ 64 */
+} FDD_prach_power_T;
+
+typedef struct _FDD_ul_pc_info_T
+{
+ kal_uint8 pc_pream; /* Power control Preamble. 0 ~ 7 frames */
+ kal_uint8 pc_algo; /* Power control algorithm. 1 or 2; inherited from primary for secondary ul freq */
+ kal_uint8 tpc_step; /* Power control step size. 1 or 2dB */
+ /* This is only valid for pc_algo = 1; inherited from primary for secondary ul freq */
+ kal_int16 dpcch_power_offset; /* DPCCH initial power offset. -164 ~ 6 dBm */
+} FDD_ul_pc_info_T;
+
+typedef enum _FDD_sc_type_E
+{
+ FDD_SC_SHORT, /* Short type scrambling code */
+ FDD_SC_LONG /* Long type scrambling code */
+} FDD_sc_type_E;
+
+typedef struct _FDD_ul_dpch_info_T
+{
+ FDD_ul_pc_info_T ul_pc; /* UL power control info */
+ FDD_sc_type_E sc_type; /* Type of scrambling code */
+ kal_uint32 sc_code; /* Scrambling code #. 0 ~ 16777215 */
+ kal_uint8 ul_dpch_num; /* # of UL DPDCH. 0 ~ FDD_MAX_ULDPCH; ignored by secondary ul freq */
+ kal_uint16 min_sf; /* Min SF. 4,8,16,32,64,128,256; ignored by secondary ul freq */
+ kal_bool tfci_exist; /* Indicate if TFCI exists; inherited from primary for secondary ul freq */
+ kal_uint8 fbi_num; /* # of FBI bits. 0, 1, 2; inherited from primary for secondary ul freq */
+ kal_uint8 punc_limit; /* Puncture limit. 40 ~ 100 in step 4; ignored by secondary ul freq */
+ /* The acture PM = punc_limit/100; ignored by secondary ul freq */
+#ifdef __UMTS_R7__
+ kal_uint8 tpc_bit_num; /* # of TPC bits. 2, 4; inherited from primary for secondary ul freq */
+#endif /* __UMTS_R7__ */
+} FDD_ul_dpch_info_T;
+
+/*-------- TFS related definition ----------------------*/
+typedef enum _FDD_cc_type_T
+{
+ FDD_CC_NONE,
+ FDD_CC_CONV12,
+ FDD_CC_CONV13,
+ FDD_CC_TURBO,
+ FDD_CC_TOTAL
+} FDD_cc_type_T;
+
+typedef struct _FDD_tfs_static_T
+{
+ kal_uint8 tti; /* TTI. # of frames, 1, 2, 4, 8 */
+ FDD_cc_type_T channel_coding; /* Coding type */
+ kal_uint8 rm_attr; /* RM attribute */
+ kal_uint8 crc_size; /* # of CRC bits. 0,8,12,16,24 */
+} FDD_tfs_static_T;
+
+typedef struct _FDD_tfs_dyn_T
+{
+ kal_uint8 tb_num; /* # of TB */
+ kal_uint16 tb_size; /* # of bibts in a TB */
+} FDD_tfs_dyn_T;
+
+typedef struct _FDD_tfs_T
+{
+ kal_uint8 tf_num; /* # of TF in this TFS */
+ FDD_tfs_dyn_T tfs_dynamic[FDD_MAXTF]; /* TFS dynamic part */
+ FDD_tfs_static_T tfs_static; /* TFS static part */
+} FDD_tfs_T;
+
+typedef enum _FDD_tx_diversity_E
+{
+ FDD_DL_TX_NONE = 0, /* No TX diversity */
+ FDD_DL_TX_STTD = 1, /* STTD */
+ FDD_DL_TX_CLM1 = 2, /* Closed loop mode 1 */
+ FDD_DL_TX_CLM2 = 3 /* Closed loop mode 2 */
+
+} FDD_tx_diversity_E;
+
+typedef enum _FDD_cws_len_E
+{
+ FDD_SSDT_LONG, /* Long code word */
+ FDD_SSDT_MEDIUM, /* Medium code word */
+ FDD_SSDT_SHORT, /* Short code word */
+ FDD_SSDT_OFF /* SSDT is off */
+
+} FDD_cws_len_E;
+
+typedef struct _FDD_ssdt_conf_T
+{
+ kal_uint8 s_field; /* # of s bits. 1 or 2 */
+ FDD_cws_len_E cws_len; /* Code word set length */
+} FDD_ssdt_conf_T;
+
+typedef enum _FDD_dpch_type_E
+{
+ FDD_DPCH_TYPE = 0,
+ FDD_FDPCH_TYPE = 1,
+ /* __UMTS_R7__ BEGIN */
+ FDD_NO_DPCH_TYPE
+ /* __UMTS_R7__ END */
+} FDD_dpch_type_E;
+
+typedef struct _FDD_dl_dpch_rla_T
+{
+ kal_uint8 dpc_mode; /* DL Power control mode. 0 or 1 or 2 */
+ kal_uint8 pilot_power_offset; /* Ppilot - Pdpdch. 0 ~ 24dB */ /*[R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint16 sf; /* SF. 4,8,16,32,64,128,256,512 */ /*[R6] For F-DPCH, UL1 doesn't care this value */
+ kal_bool fixed_pos; /* Fixed or flexible position. True = Fixed */ /*[R6] For F-DPCH, UL1 doesn't care this value */
+ kal_bool tfci_exist; /* Indicate if TFCI exist */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint8 pilot_num; /* # of pilot bits. 2,4,8,16 */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint8 tgps_num; /* # of TGPS in the list. 0 ~ 6 */
+ FDD_tgps_info_T tgps_info[FDD_MAX_TGPS]; /* TGPS list */
+ FDD_tx_diversity_E tx_diversity; /* TX diversity mode */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ FDD_ssdt_conf_T ssdt_conf; /* SSDT configuration */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_int32 doff; /* Default DPCH offset value. -1 ~ 306688 */
+ /* -1 is an invalid value */
+
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rl */
+ kal_uint8 tpc_target; /* [R6] F-DPCH only, range: 1~10, the actual TPC command error rate target is tpc_target/100 */
+} FDD_dl_dpch_rla_T;
+
+typedef struct _FDD_dldpch_code_T
+{
+ kal_uint8 ssc; /* Scrambling code # for this code channel */
+ /* 0 ~ 15. 0 for "the same scrambling code for the P-CPICH */
+ kal_uint16 sf; /* 4,8,16,32,64,128,256,512 */
+ kal_uint16 ovsf; /* OVSF code. 0 ~ SF-1 */
+ kal_bool sc_change; /* True : Changed scrambling code is used */
+} FDD_dldpch_code_T;
+
+typedef struct _FDD_dl_dpch_rl_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */
+ /* If the value of tm is not equal to -1, UL1 will use this value */
+ /* If the value of tm is equal to -1, UL1 will not use this value */
+ kal_int32 tm; /* Cell boundary to LST. -1 ~ 38400*8-1 */
+ kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell */
+ kal_bool pcpich_usage; /* Indicate if P-CPICH can be used for channel estimation */
+ /* KAL_TRUE means P-CPICH could be used */
+ kal_int8 scpich_ssc; /* Scrambling code of S-CPICH. */
+ /* -1 ~ 15. 0 means use primary scramblign code */
+ /* -1 means there is not S-CPICH */
+ kal_uint8 scpich_ovsf; /* OVSF code. 0 ~ 255 */
+ kal_bool tx_diversity_disable; /* Indicate if TX diversity is used */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ /* True means TX diversity is disabled. */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint8 closedlooptimingadj_mode; /* 0 : CLTD timing adjust mode 0 */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ /* 1 : CLTD timing adjust mode 1 */
+ kal_uint8 ssdt_id; /* 0 ~ 8. 1 for 'A'. 8 for not applicable*/
+ kal_uint8 tpc_index; /* TPC combination index. 0 ~ 5 */
+ kal_int8 tpc_power_offset; /* Power offset between TPC and DPDCH,-1 means INVALID, range 0~24 dB (actual 0:0.25:6) [R5 only] */
+ /* [R6] For F-DPCH, UL1 doesn't care this value */
+
+ /* [R6] F-DPCH: dl_dpch_num must be 1 and the index of the F-DPCH info must be 0 in dl_dpch_info list */
+ kal_uint8 dl_dpch_num; /* # of DPDCH on the RL */
+ FDD_dldpch_code_T dl_dpch_info[FDD_MAX_DLDPCH]; /* Information for each code channel */
+
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rla */
+ kal_uint8 fdpch_slot_format; /* [R7] F-DPCH only, range: 0~9. For R6 and previous version, this value should be 0 */
+ kal_bool fdpch_sttd_ind; /* [R6] F-DPCH only, TRUE when STTD is used. FALSE, otherwise */
+
+ kal_bool hsdsch_serving_rl_ind; /* [R5] The value "TRUE" indicates that this radio link is the serving HS-DSCH radio link. FALSE, otherwise */
+ kal_bool edch_serving_rl_ind; /* [R6] The value "TRUE" indicates that this radio link is the serving E-DCH radio link. FALSE, otherwise */
+ kal_bool sttd_valid; /* To judge if sttd value can be used by UL1 when doing SCS */
+} FDD_dl_dpch_rl_T;
+
+typedef struct _FDD_dl_establish_T
+{
+ kal_uint8 t312; /* T312 */
+ kal_uint16 n312; /* N312 */
+ kal_uint8 n313; /* N313 */
+ kal_uint8 t313; /* T313 */
+ kal_uint16 n315; /* N315 */
+} FDD_dl_establish_T;
+
+#ifdef __UMTS_R7__
+/* [R7] Determine whether UL1 need to store HS-SCCH order when release DCH channel */
+typedef enum _FDD_dpch_release_type_E
+{
+ FDD_DCH_RELEASE = 0, /* Don't need to store HS-SCCH order */
+ FDD_DCH_TRHHO_RELEASE, /* Need to store HS-SCCH order */
+ FDD_DCH_TRHHO_REVERT_RELEASE, /* Don't need to store HS-SCCH order */
+ FDD_DCH_TMHHO_RELEASE, /* Need to store HS-SCCH order */
+ FDD_DCH_TMHHO_REVERT_RELEASE, /* Don't need to store HS-SCCH order */
+ FDD_DCH_IRAT_RELEASE, /* Need to store HS-SCCH order */
+ FDD_DCH_ALL_RL_TIMING_MODIFY_RELEASE /* Need to store HS-SCCH order */
+} FDD_dpch_release_type_E;
+#endif /* __UMTS_R7__ */
+
+/*-------- TFCS related definition ----------------------*/
+typedef struct _FDD_sig_gain_T
+{
+ kal_uint8 beta_c; /* Bc. 0 ~ 15 */
+ kal_uint8 beta_d; /* Bd. 0 ~ 15 */
+ kal_int8 ref_tfc_id; /* Reference TFC ID. -1 ~ 3. */
+ /* 0 ~ 3 : This TFCI is a referenced id for other computed TFC. */
+ /* -1 : It is an invalid value. Means it will not be referenced by other TFC. */
+} FDD_sig_gain_T;
+
+typedef union _FDD_gain_factor
+{
+ kal_int8 computed_gain_id; /* For computed gain factor using reference TFC id. 0 ~ 3 */
+ FDD_sig_gain_T sig_gain; /* The signaled gain factor. */
+} FDD_gain_factor;
+
+typedef struct _FDD_ul_dpch_tfc_T
+{
+ kal_uint8 tfi_list[FDD_MAX_TRCH_NUM]; /* The list of TFI for this TFCI for UL DCH TrCH */
+ kal_bool sig_gain_ind; /* True: Gain factor is siganled. False: Gain factor is computed from reference TFCI */
+ FDD_gain_factor gain_factor; /* Gain factor */
+} FDD_ul_dpch_tfc_T, FDD_ul_tfc_T;
+//} FDD_ul_dpch_tfc_T;
+
+typedef struct _FDD_rach_tfc_T
+{
+ kal_uint8 tfi_list; /* The list of TFI for this TFCI. The number of TrCH for PRACH is 1. */
+ kal_bool sig_gain_ind; /* True: Gain factor is siganled. False: Gain factor is computed from reference TFCI */
+ kal_int8 msg_pwr_offset; /* Power offset between the last preamble and the control part of RACH */
+ FDD_gain_factor gain_factor; /* Gain factor */
+} FDD_ul_rach_tfc_T;
+
+typedef struct _FDD_dl_tfc_T
+{
+ kal_uint8 tfi_list[FDD_MAX_TRCH_NUM]; /* The list of TFI for this TFCI for DL TrCH */
+} FDD_dl_tfc_T;
+
+/*-------- TrCH related definition ----------------------*/
+
+#if 0 //Modify by Anthony Chin, for UL1D's convenience to maintain DB
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+typedef struct _FDD_trch_T
+{
+ kal_uint8 trch_id; /* TrCH ID 1 ~ 32 */
+ kal_uint8 bit_offset; /* Bit offset. 0 ~ 7 */
+ FDD_tfs_T tfs; /* TFS of this TrCH */
+ kal_int8 target_bler; /* Diving the value of this field to 10 get the real BLER. -63 ~ 0 */
+} FDD_trch_T,
+FDD_ul_rach_trch_T,
+FDD_ul_dch_trch_T,
+FDD_dl_fachpch_trch_T,
+FDD_dl_dch_trch_T;
+#endif
+
+/*-------- CCTrCH related definition ----------------------*/
+typedef enum _FDD_cctrch_type_E
+{
+ FDD_CCTRCH_UL_RACH, /* UL RACH CCTrCH */
+ FDD_CCTRCH_UL_DCH, /* UL DCH CCTrCH */
+ FDD_CCTRCH_DL_DCH, /* DL DCH CCTrCH */
+ FDD_CCTRCH_DL_PCH, /* DL PCH CCTrCH */
+ FDD_CCTRCH_DL_FACH, /* DL FACH CCTrCH */
+ FDD_CCTRCH_DL_BCH, /* DL BCH CCTrCH */
+ FDD_CCTRCH_DL_FDPCH, /* DL FDPCH, only for UL1 use */
+ /* __UMTS_R7__ BEGIN */
+ FDD_CCTRCH_DL_EPCH, /* DL EPCH CCTrCH */
+ /* __UMTS_R7__ END */
+ /* __UMTS_R8__ BEGIN */
+ FDD_CCTRCH_UL_EDCH /* UL EDCH CCTrCH */
+ /* __UMTS_R8__ END */
+} FDD_cctrch_type_E;
+
+typedef struct _FDD_FACH_PCH_Info_T
+{
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */
+ /* If the value of tm is not equal to -1, UL1 will use this value */
+ /* If the value of tm is equal to -1, UL1 will not use this value */
+ kal_int16 rscp; /* Serving cell RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
+ FDD_sccpch_info_T sccpch_info; /* Physical channel for PCH/FACH to be carried over */
+ kal_bool sccpch_optimization; /* True if FACH and PCH use the same S-CCPCH. valid only for configuring CTCH */
+ kal_uint16 tfc_num; /* # of TFC in TFCS */
+ FDD_dl_tfc_T tfcs[FDD_MAX_DL_TFC]; /* TFCS */
+ kal_uint8 active_dl_trch_list; /* Active TrCHs by bit string. MSB is the lowest numbered TrCH ID */
+ kal_uint8 trch_num; /* # of TrCHs carried on this CCTrCH */
+ FDD_dl_fachpch_trch_T trch_list[FDD_MAXFACHPCH]; /* List of TrCHs carried on this CCTrCH */
+ kal_bool pich_ctch_valid; /* True means "pich_ctch_info" is valid. */
+ FDD_pich_ctch_info_T pich_ctch_info; /* PICH or CTCH information */
+} FDD_FACH_PCH_Info_T;
+
+/*-------- BCH related definition ----------------------*/
+typedef struct _FDD_sib_info_T
+{
+ kal_uint8 seg_count; /* SEG_COUNT 1 ~ 16 */
+ kal_uint16 sib_rep; /* SIB_REP 2^2 ~ 2^12 */
+ kal_uint16 sib_pos; /* SIB_POS 0 ~ sib_rep-2 */
+ kal_uint8 sib_off[FDD_MAX_SIB_SEG_COUNT]; /* SIB_OFF 2 ~ 32 The # of elements of this field is equal to seg_count-1 */
+} FDD_sib_info_T;
+
+typedef enum _FDD_bch_priority_E
+{
+ FDD_BCH_PRIOHIGH, /* Priority High */
+ FDD_BCH_PRIOMEDIUM, /* Priority Medium */
+ FDD_BCH_PRIOLOW, /* Priority Low */
+ FDD_BCH_PRIORR, /* Priority for SIB round robin */
+} FDD_bch_priority_E;
+
+/*------- PHY_POST_TX_IND related ---------*/
+typedef struct _FDD_tPhyPostTxMemInfo
+{
+ kal_uint8 RbId;
+ kal_uint8 *pContainer;
+} FDD_tPhyPostTxMemInfo;
+
+typedef struct _FDD_tPhyPostTxElement
+{
+ kal_uint8 Num;
+ FDD_tPhyPostTxMemInfo TxMemInfo[FDD_MAX_UL_TB];
+#if defined(__GEMINI__) && defined(__UMTS_RAT__)
+ kal_bool is_tx_suspend; /* This flag is only used for ULDCH when Gemini2.0. For RACH, this flag is always false.
+ It indicates if there is SIM2 gap in the minTTI period of the released ul data, and UL1D will set this flag. */
+ kal_uint8 cfn; /* This value is only used for ULDCH when Gemini2.0.
+ It indicates the cfn value that UL1C gets the ul data from UMAC. */
+#endif
+} FDD_tPhyPostTxElement;
+
+typedef enum _FDD_tPhyPostTxType
+{
+ FDD_POST_TX_RACH,
+ FDD_POST_TX_DCH
+} FDD_tPhyPostTxType;
+
+/*-------- Data related definition ----------------------*/
+typedef struct _FDD_dlTrchData
+{
+ kal_bool valid_fpch; /* Raymond,20070327 Eric/Anthony add this, already notify UMAC */
+ kal_bool is_dual_TF; /* Andrew/Sean: For MAC to identify BTFD_DUAL_TF TrCh */
+ kal_int8 crc_status; /* Jay: For DUAL-TF TrCH power control*/
+ kal_uint8 trchId; /* TrCH ID */
+ kal_uint16 tb_size; /* TB size in bit. 0 ~ 4992 */
+ kal_uint16 num_tb; /* # of TB. 0 ~ 512 */
+ kal_uint16 addi_crc_size; /*Indicate additional crc size for MT6290E1 RXBRP DOB issue workaround*/
+ kal_bool is_hw_out_extra; /*L1 internal: Indicate whether HW output extra bytes for MT6290E1 RXBRP DOB issue workaround*/
+} FDD_dlTrchData;
+
+typedef struct _FDD_ulTrchData
+{
+ kal_uint8 trchId; /* TrCH ID */
+ kal_uint16 tb_size; /* TB size in bit. 0 ~ 4992 */
+ kal_uint16 num_tb; /* # of TB. 0 ~ 512 */
+} FDD_ulTrchData;
+
+/*-------- Measurement related definition ----------------------*/
+typedef struct _FDD_preferred_cell_list_T
+{
+ kal_uint8 uarfcn_index; /* Frequency index */
+ /* Freq. array is contained in Frequency scan message */
+ kal_uint16 psc; /* Primary Scrambling code */
+} FDD_preferred_cell_list_T;
+
+typedef enum _FDD_measured_type_E
+{
+ FDD_INTRA_FREQENCY_MEASURED,
+ FDD_INTER_FREQENCY_MEASURED,
+ FDD_FREQ_SCAN_DETECTED,
+ FDD_INTRA_SEC_FREQENCY_MEASURED /* [R9]Secondary intra-freq measurement */
+} FDD_measured_type_E;
+
+
+typedef enum _FDD_cell_type_E
+{
+ FDD_MONITORED,
+ FDD_DETECTED,
+ FDD_SPECIFIC_CELL_SEARCH,
+ FDD_MONITORED_CELL_FOUND,
+ FDD_DETECTED_CELL_FOUND
+} FDD_cell_type_E;
+
+typedef enum _FDD_meas_status_E
+{
+ FDD_MS_INCLUDED,
+ FDD_MS_NOTINCLUDED
+} FDD_meas_status_E;
+
+typedef enum _FDD_meas_tm_off_type_E
+{
+ FDD_TM_OFF_RST,
+ FDD_TM_OFF_DCH,
+ FDD_TM_OFF_COMMON,
+ FDD_TM_OFF_NA
+} FDD_meas_tm_off_type_E;
+
+typedef struct _FDD_measured_cell_T
+{
+ kal_bool sttd; /* Indicate if STTD is used */
+ kal_int16 ec_no; /* Ec/No. Range: -100~0 means (-25~0) dB in 0.25 dB step */
+ kal_int16 rscp; /* RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_uint16 freq; /* DL UARFCN */
+ FDD_meas_tm_off_type_E tm_off_type; /*Indicate which field is applicable in this report*/
+ kal_int16 sfn; /* SFN in BCH. -1 ~ 4095 : -1 means unknown SFN */
+ kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */
+ kal_int32 tm; /* Cell boundary. -1 ~ 38400*8-1 : -1 means unknown timing*/
+ kal_uint32 meas_sfn_diff; /* SFN_SFN difference in chips*/
+ FDD_meas_status_E meas_status; /* Indicate whether this cell is measured in this time */
+ FDD_cell_type_E cell_type; /* AS, MS or DS cell */
+ kal_bool update_timing; /* Indicates if it is recommended by UL1 for MEME to update cell timing based on FS result */
+} FDD_measured_cell_T;
+
+typedef enum _FDD_meas_type_E
+{
+ FDD_MT_INTRA_FREQ, /* Intra-frequency measurement */
+ FDD_MT_INTER_FREQ, /* Inter-frequency measurement */
+ FDD_MT_GSM_RAT /* GSM-RAT measurement */
+} FDD_meas_type_E;
+
+typedef enum _FDD_sfn_priority_E
+{
+ FDD_SFN_HIGH,
+ FDD_SFN_MEDIUM,
+ FDD_SFN_LOW,
+ FDD_SFN_OFF
+} FDD_sfn_priority_E;
+
+typedef struct _FDD_meas_spec_T
+{
+ kal_bool ds_meas_intra; /* Indicate if measure on intra-freq (and R9 secondary intra-freq) detected set*/
+ kal_bool ds_sfn_intra; /* Indicate if reading SFN of detected set */
+#ifdef __UMTS_R10__
+ kal_bool ds_meas_inter; /* Indicate if measure on inter-freq detected set*/
+#endif
+ kal_int8 nc_nbr_dch; /* # of best cells to read SFN in DCH. -1 ~ 32
+ -1 means L1 should not read SFN for any cell
+ 0 means L1 should read SFN for cells which have stronger CPICH measurement
+ Other values means L1 should read FN for nc_nbr_dch cells from active set, monitored set and detected set.
+ */
+ FDD_sfn_priority_E serving_prio; /* The priority of reading SFN of cells in active set.
+ Only used when L1 is in DCH state and nc_nbr_dch > 0 */
+ FDD_sfn_priority_E monitor_prio; /* The priority of reading SFN of cells in monitored set.
+ Only used when L1 is in DCH state and nc_nbr_dch > 0 */
+ FDD_sfn_priority_E detect_prio; /* The priority of reading SFN of cells in detected set.
+ Only used when L1 is in DCH state and nc_nbr_dch > 0 */
+ kal_uint8 nc_nbr_rach; /* # of best cells to read SFN in non-DCH state. 0 ~ 32 */
+} FDD_meas_spec_T;
+
+#ifdef __UMTS_R8__
+typedef enum _FDD_higher_prio_search_support_E /* [Rel8][Absolute Priority Search] absolute priority search type */
+{
+ FDD_REGULAR_MEAS_ONLY,
+ FDD_HIGHER_PRIORITY_ONLY,
+ FDD_HIGHER_PRIORITY_AND_REGULAR_MEAS
+} FDD_higher_prio_search_support_E;
+#endif
+
+typedef struct _FDD_cell_info_list_T
+{
+ kal_uint8 freq_index; /* UARFCN index */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_bool sttd; /* Indicate if STTD is used */
+ kal_bool read_sfn_ind; /* Indicate if read SFN */
+ kal_int16 ref_timing; /* Cell boundary. -1 ~ 38400-1 : -1 means unknown timing*/
+ kal_bool ref_timing_sib; /* Indicate if the reference timing comes from SIB or Meas. Control */
+ kal_int32 tm; /* Cell boundary. -1 ~ 38400*8-1 : -1 means unknown timing*/
+ kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */
+#ifdef __UMTS_R8__
+ FDD_higher_prio_search_support_E prio_search_control; /* [Rel8] Higher priority search control */
+#endif
+} FDD_cell_info_list_T;
+
+typedef enum _FDD_event_cond_E
+{
+ FDD_COND_ABOVE, /* Above threshold */
+ FDD_COND_ABOVE_EQUAL, /* Above or equal to threshold */
+ FDD_COND_BELOW, /* Below threshold */
+ FDD_COND_BELOW_EQUAL, /* Below or equal to threshold */
+ FDD_COND_EVENT_6C, /* [R6] Reporting event 6C: The UE Tx power reaches its minimum value */
+ FDD_COND_EVENT_6D /* [R6] Reporting event 6D: The UE Tx power reaches its maximum value */
+} FDD_event_cond_E;
+
+typedef struct _FDD_meas_event_T
+{
+ kal_uint8 event_id; /* Measurement event ID */
+ kal_uint8 measurement_id; /* Measurement ID */
+ kal_int16 threshold;
+ kal_uint16 delay; /* Time to Triggered. 0 ~ 500 frames */
+ FDD_event_cond_E condition; /* Event triggered condition */
+} FDD_meas_event_T;
+
+typedef struct _FDD_rl_meas_result_T
+{
+ kal_uint8 rl_status; /* RL status */
+ /* 0 : Not detected */
+ /* 1 : Detected not used */
+ /* 2 : Detected and demodulated */
+ kal_uint16 psc; /* Scrambling code of this RL */
+ kal_uint32 time_diff; /* RX-TX Timd diff. 0 ~ 38400*8-1 */
+} FDD_rl_meas_result_T;
+
+typedef enum _FDD_meas_act_E
+{
+ FDD_MEAS_UNCHANGE, /* Unchange a cell list */
+#ifndef __MTK_UL1_FDD__ /* 20080305: For Venus, still use old I/F */
+ FDD_MEAS_MODIFY, /* Modify an existed cell list */
+#endif
+ FDD_MEAS_DELETE, /* Delete an existed cell list */
+ FDD_MEAS_UPDATE /* Update the configuration of an existed cell list */
+} FDD_meas_act_E;
+
+typedef enum _FDD_triggering_cause_E
+{
+ FDD_REGULAR_REPORT,
+ FDD_ONE_SHOT_MEASUREMENT,
+ FDD_T_RESELECTION_EXPIRY
+} FDD_triggering_cause_E;
+
+typedef enum
+{
+ FDD_CPHY_MEAS_STOP_CAUSE_NONE, /* none: fill when none stop */
+ FDD_CPHY_MEAS_STOP_CAUSE_REGULAR, /* normal stop */
+ FDD_CPHY_MEAS_STOP_CAUSE_4G3IRHO /* stop triggered by 4G3 IRHO */
+} FDD_CPHY_MEASUREMENT_STOP_CAUSE_E;
+
+typedef struct _FDD_supplementary_meas_parameter_T
+{
+ kal_bool intra_meas_one_shot_ind; /* When intra-F cell list is updated,to notify if UL1 needs to do one-shot measurement on intra-F or not */
+ kal_bool inter_meas_one_shot_ind; /* When inter-F cell list is updated,to notify if UL1 needs to do one-shot measurement on inter-F or not */
+} FDD_supplementary_meas_parameter_T;
+
+typedef struct _FDD_supplementary_report_info_T
+{
+ FDD_triggering_cause_E triggering_cause; /* The triggering cause of this meas tick */
+ kal_bool evaluate_req; /* To notify if L3 need to trigger cell evaluattion */
+#ifdef __UMTS_R7__
+ kal_bool is_cycle2; /* Indicate whether the current DRX is cycle2 or not */
+#endif /* __UMTS_R7__ */
+} FDD_supplementary_report_info_T;
+
+/*-------- FACH MO related definition ----------------------*/
+typedef struct _FDD_fach_mo_info_T
+{
+ kal_uint8 n; /* # of frames in max TTI. 1,2,4,8 */
+ kal_uint8 k; /* MO cycle length coefficient. M_REP=2^k */
+ kal_bool inter_freq_ind; /* Indicate if inter-frequency meas in MO */
+ kal_bool inter_rat_ind; /* Indicate if inter-RAT meas in MO */
+ kal_bool inter_freq_cell_exist; /* Indicate if inter-freq cell in BA lsit is existed */
+ kal_bool inter_rat_cell_exist; /* Indicate if inter-rat cell in BA list is existed */
+ kal_uint16 start_off; /* C_RNTI % M_REP. 0 ~ 4095 */
+} FDD_fach_mo_info_T;
+
+/*-------- Operation-Mode related definition ----------------------*/
+typedef enum _FDD_mode_type_E
+{
+ FDD_OM_SINGLE, /* Single Mode */
+ FDD_OM_MULTI /* Dual Mode */
+} FDD_mode_type_E;
+
+typedef enum _FDD_rat_type_E
+{
+ FDD_UL1_RAT_UMTS_ACTIVE, /* UMTS_Active */
+ FDD_UL1_RAT_UMTS_INACTIVE /* UMTS_Inactive */
+} FDD_rat_type_E;
+
+typedef struct _FDD_duplex_mode_info_T
+{
+ umts_duplex_mode_type source_umts_duplex_mode;
+ umts_duplex_mode_type target_umts_duplex_mode;
+ lte_duplex_mode_type source_lte_duplex_mode;
+ lte_duplex_mode_type target_lte_duplex_mode;
+} FDD_duplex_mode_info_T;
+
+/*-------- Message(Primitive) related definition ----------------------*/
+typedef enum _FDD_dch_setup_msg_type_E
+{
+ FDD_DCH_SETUP, /* Used when DCH is established first time */
+ FDD_DCH_TRHHO, /* Used when timing reinitialized hard hand over */
+ FDD_DCH_TRHHO_REVERT, /* Used when timing reinitialized HHO revert */
+ FDD_DCH_TMHHO, /* Used when timing maintained hard hand over */
+ FDD_DCH_TMHHO_REVERT, /* Used when timing maintained HHO revert */
+ FDD_DCH_IRAT_REVERT, /* Used when Inter-RAT HHO revert */
+ FDD_DCH_ALL_RL_TIMING_MODIFY /* Used when all dpch rl timing offset is modified.*/
+} FDD_dch_setup_msg_type_E;
+
+
+typedef enum _FDD_dch_modify_msg_type_E
+{
+ FDD_DCH_RECONFIG, /* Used when DCH is reconfigured */
+ FDD_DCH_ASU, /* Used when active set update */
+ FDD_DCH_LOOP_MODE_2 /* Used when DCH loop back mode 2 */
+} FDD_dch_modify_msg_type_E;
+
+
+typedef enum _FDD_msg_container_error_E /* Error cause of message container, MA only*/
+{
+ FDD_NONE,
+ FDD_DCH_SETUP_FAIL
+} FDD_msg_container_error_E;
+
+typedef enum _FDD_TGPS_Action_E
+{
+ FDD_TGPS_ACT_START,
+ FDD_TGPS_ACT_STOP,
+ FDD_TGPS_ACT_SUSPEND,
+ FDD_TGPS_ACT_RESUME,
+ FDD_TGPS_ACT_CONTINUE,
+ FDD_TGPS_ACT_DELETE
+} FDD_TGPS_Action_E;
+
+typedef struct _FDD_TGPS_Action_T
+{
+ kal_uint8 tgpsi; /* TGPIS of the TGPS on which the action and apply flag should be applied */
+ kal_bool apply_current;
+ kal_bool apply_suspend;
+ FDD_TGPS_Action_E action;
+} FDD_TGPS_Action_T;
+
+typedef enum _FDD_meas_control_E
+{
+ FDD_MEAS_CTRL_INVALID, /* No meas. control action in current MSG_CONTAINER */
+ FDD_MEAS_CM_STOP, /* For inter-RAT HHO, stop CM measurement when receiving DCH release msg */
+ FDD_MAX_MEAS_CONTROL = FDD_MEAS_CM_STOP
+} FDD_meas_control_E;
+
+/*Add for improving full band FS efficiency -- by excluding some UARFCN or some frequency range*/
+typedef enum _FDD_full_band_option_E
+{
+ FDD_FULL_BAND_ONLY, /*Normal full band FS*/
+ FDD_FULL_BAND_AND_EXCLUDE /*Full band FS but the indicated frequency list/range will be excluded in the full band FS procedure*/
+} FDD_full_band_option_E;
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+typedef enum _FDD_uas_gemini_conflict_cause_enum
+{
+ FDD_URR_NO_CONFLICT,
+ FDD_URR_CONFLICT_WITH_GSM_BCCH,
+ FDD_URR_CONFLICT_WITH_GSM_NBCCH,
+ FDD_URR_CONFLICT_WITH_GSM_PCH,
+ FDD_URR_CONFLICT_WITH_GSM_OTHERS,
+ FDD_URR_CONFLICT_WITH_WCDMA_BCH_HIGH,
+ FDD_URR_CONFLICT_WITH_WCDMA_BCH_LOW,
+ FDD_URR_CONFLICT_WITH_WCDMA_PICH,
+ FDD_URR_CONFLICT_WITH_WCDMA_OTHERS,
+ FDD_URR_CONFLICT_WITH_LTE_BCCH,
+ FDD_URR_CONFLICT_WITH_LTE_NBCCH_HIGH,
+ FDD_URR_CONFLICT_WITH_LTE_NBCCH_MIDDLE,
+ FDD_URR_CONFLICT_WITH_LTE_NBCCH_LOW,
+ FDD_URR_CONFLICT_WITH_LTE_PCH,
+ FDD_URR_CONFLICT_WITH_LTE_OTHERS
+} FDD_uas_gemini_conflict_cause_enum;
+
+#ifdef __MODIFY_CTCH_RECEPTION_PRIO__
+typedef enum _FDD_rrce_gemini_priority_adjust_E
+{
+ FDD_GEMINI_PRIORITY_ADJUST_ALL_NORMAL, /* Currently only used in Gemini2.0, to raise all rx/tx/BCH channel priority for RRC connection establishment or DL sync procedure. */
+ FDD_GEMINI_PRIORITY_ADJUST_ALL_HIGH,
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH_NORMAL,
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH_IMPRV, /* Added as a part of CBS improvement, to raise one SIM CTCH priority over other SIM CTCH*/
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH_ETWS /* R8 ETWS feature, used for receiving ETWS CB. */
+} FDD_rrce_gemini_priority_adjust_E;
+#else
+typedef enum _FDD_rrce_gemini_priority_adjust_E
+{
+ FDD_GEMINI_PRIORITY_ADJUST_ALL, /* Currently only used in Gemini2.0, to raise all rx/tx/BCH channel priority for RRC connection establishment or DL sync procedure. */
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH /* R8 ETWS feature, used for receiving ETWS CB. */
+} FDD_rrce_gemini_priority_adjust_E;
+#endif
+
+#endif
+/*-------- [R5R6] HS-DSCH related ----------------------*/
+typedef enum _FDD_hs_cqi_k_E
+{
+ FDD_CQI_K_0,
+ FDD_CQI_K_2,
+ FDD_CQI_K_4,
+ FDD_CQI_K_8,
+ FDD_CQI_K_10,
+ FDD_CQI_K_20,
+ FDD_CQI_K_40,
+ FDD_CQI_K_80,
+ FDD_CQI_K_160,
+ /* __UMTS_R7__ BEGIN */
+ FDD_CQI_K_16,
+ FDD_CQI_K_32,
+ FDD_CQI_K_64
+ /* __UMTS_R7__ END */
+} FDD_hs_cqi_k_E;
+
+#ifdef __UMTS_R7__
+/* [R7] FDD_UE_OWN_CATEGORY or FDD_CATEGORY_12. According to 25.331 CR#4159, UE should use the number of soft channel bits
+ according to this category to decode HS-PDSCH TB. */
+typedef enum _FDD_hs_harq_ir_type_E
+{
+ FDD_UE_OWN_CATEGORY = 0,
+ FDD_CATEGORY_12
+} FDD_hs_harq_ir_type_E;
+
+typedef enum
+{
+ FDD_E_SCELL_PRI = 0,
+ FDD_E_SCELL_SEC,
+ FDD_E_SCELL_TOTAL, /* 0:primary, 1: secondary */
+ FDD_E_SCELL_BOTH = FDD_E_SCELL_TOTAL,
+} FDD_edch_scell_E;
+
+typedef struct _FDD_hs_tb_size_list_T
+{
+ kal_int8 tbs_index; /* [Range] 1~90, -1 if this is invalid */
+ kal_bool second_code_support; /* Indicates whether the second HS-PDSCH code is used for this TB size.
+ If TRUE, the HS-PDSCH second code index value is the value of IE 'HSPDSCH Code Index' incremented by 1. */
+} FDD_hs_tb_size_list_T;
+
+/* [R7] MAC entity types for handling HS-DSCH */
+typedef enum _FDD_hs_mac_entity_type_E
+{
+ FDD_HS_MAC_HS_ENTITY = 0,
+ FDD_HS_MAC_EHS_ENTITY,
+ FDD_HS_MAC_EHS_ENTITY_DC
+} FDD_hs_mac_entity_type_E;
+#endif /* __UMTS_R7__ */
+
+typedef struct _FDD_hs_scch_info_T
+{
+ kal_uint8 ssc; /* DL scrambling code to be applied for HS-DSCH and HS-SCCH */
+ kal_uint8 ovsf_code_num; /* Number of HS-SCCH to be received. Range:1~4 */
+ kal_uint8 ovsf[FDD_MAX_HS_SCCH_NUM]; /* OVSF code of HS-SCCH to be received */
+} FDD_hs_scch_info_T;
+
+typedef struct _FDD_hs_meas_fb_info_T
+{
+ kal_int8 meas_po; /* Measurement power offset. Range: -12~26 */
+ FDD_hs_cqi_k_E cqi_k; /* Measurement feedback cycle */
+ kal_uint8 cqi_repe_factor; /* CQI repetition factor. Range: 1~4 */
+ kal_uint8 delta_cqi; /* DeltaCQI. Range: 0~8 */
+} FDD_hs_meas_fb_info_T;
+
+typedef struct _FDD_hs_harq_info_T
+{
+ kal_uint8 process_num; /* Number of HARQ process. Range: 1~8 */
+ kal_bool explicit_partition; /* TRUE indicates explicit memory partition. FALSE indicates implicit memory partition */
+ kal_uint8 process_mem_size[FDD_MAX_HS_PROCESS_NUM]; /* index of HARQ memory size. range: 0~60, only valid when memory partition is explicit */
+#ifdef __UMTS_R7__
+ FDD_hs_harq_ir_type_E harq_ir_type; /* FDD_UE_OWN_CATEGORY or FDD_CATEGORY_12. According to 25.331 CR#4159, UE should use the number of soft channel bits
+ according to this category to decode HS-PDSCH TB. */
+ FDD_hs_mac_entity_type_E hs_mac_entity; /* enum for MAC-hs, MAC-ehs and MAC-ehs with DC */
+#endif /* __UMTS_R7__ */
+} FDD_hs_harq_info_T;
+
+typedef struct _FDD_hs_ulpc_info_T
+{
+ kal_uint8 delta_ack; /* delta_ack. range: 0~8 */
+ kal_uint8 delta_nack; /* delta_nack. range: 0~8 */
+ kal_uint8 acknack_repe_factor; /* ack_nack_repetition_factor. range: 1~4 */
+ kal_uint8 harq_preamble_mode; /* [R6] range: 0~1, 1: indicates the preamble and postable are used
+ for R5 and previous version, this value should be 0 */
+} FDD_hs_ulpc_info_T;
+
+typedef enum
+{
+ FDD_DSCH_NO_HRNTI_DETECTED = 0, /*HS-SCCH CRC check is failed*/
+ FDD_DSCH_D_HRNTI_DETECTED = 1, /*HS-PDSCH is indicated by HS-SCCH with dH-RNTI*/
+ FDD_DSCH_C_HRNTI_DETECTED = 2, /*HS-PDSCH is indicated by HS-SCCH with cH-RNTI*/
+ FDD_DSCH_B_HRNTI_DETECTED = 3, /*HS-PDSCH is indicated by HS-SCCH with bH-RNTI*/
+ FDD_DSCH_HRNTI_LESS = 4, /*HS-PDSCH is decoded blindly without HS-SCCH */
+ FDD_DSCH_NOT_RECEIVE = 5, /*This subframe is not received by HW */
+
+} FDD_hs_dsch_decode_hrnti_E;
+
+typedef struct _FDD_hsdsch_data_T
+{
+ kal_uint16 tb_size; /*[Range]: 137 ~ 27952 bits, MAC-hs PDU size */
+ kal_uint8 *p_data; /* The buffer contains MAC-hs data */
+ kal_uint8 *p_data_head; /* The address of the HDA buffer allocated by UMAC */
+ FDD_hs_dsch_decode_hrnti_E decode_hrnti; /*H-RNTI dectected info*/
+ kal_int8 pi_repeat_cycle; /* -1:invalid, -2:retransmission with CRC pass, 1~20:valid pi_repeat_cyle */
+
+ kal_uint8 decode_counter; /* For EM in UMAC */
+} FDD_hsdsch_data_T;
+
+#ifdef __UMTS_R7__
+typedef enum _FDD_mac_ehs_reset_cause_E
+{
+ FDD_Treset_Expired
+} FDD_mac_ehs_reset_cause_E;
+#endif /* __UMTS_R7__ */
+
+typedef enum _FDD_edch_tti_E
+{
+ FDD_EDCH_TTI_2 = 0,
+ FDD_EDCH_TTI_10 = 1,
+ FDD_EDCH_TTI_TOTAL
+} FDD_edch_tti_E;
+
+typedef enum _FDD_edch_sf_E
+{
+ FDD_EDCH_SF256 = 0,
+ FDD_EDCH_SF128 = 1,
+ FDD_EDCH_SF64 = 2,
+ FDD_EDCH_SF32 = 3,
+ FDD_EDCH_SF16 = 4,
+ FDD_EDCH_SF8 = 5,
+ FDD_EDCH_SF4 = 6,
+ FDD_EDCH_ONE_PHCH = 6,
+ FDD_EDCH_2SF4 = 7,
+ FDD_EDCH_SF2 = 7,
+ FDD_EDCH_2SF2 = 8,
+ FDD_EDCH_2SF2AND2SF4 = 9,
+ FDD_EDCH_2SF2AND2SF4_16QAM = 10,
+ FDD_EDCH_SF_CNT = 11,
+ FDD_EDCH_SF_NA = 12
+} FDD_edch_sf_E;
+
+typedef enum
+{
+ MPR_COMBO_BETA_D_ZERO_HS_ZERO = 0,
+ MPR_COMBO_BETA_D_NON_ZERO_HS_ZERO,
+ MPR_COMBO_BETA_D_ZERO_HS_NON_ZERO,
+ MPR_COMBO_BETA_D_NON_ZERO_HS_NON_ZERO,
+ MPR_COMBO_MAX
+} mpr_combo_E;
+
+typedef enum _FDD_edch_rv_config_E
+{
+ FDD_EDCH_RV0 = 0,
+ FDD_EDCH_RVTABLE = 1
+} FDD_edch_rv_config_E;
+
+typedef struct _FDD_eagch_info_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 255 */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell */
+ FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-AGCH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/
+} FDD_eagch_info_T;
+
+typedef struct _FDD_ehich_info_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 127 */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell (tauDPCH) */
+ FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-HICH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/
+ kal_uint8 signature_seq; /* E-HICH signature sequence 0~39*/
+ kal_uint8 tpc_index; /* TPC combination index. 0 ~ 5 */
+} FDD_ehich_info_T;
+
+typedef struct _FDD_ergch_info_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 127. Should be the same as E-HICH ovsf code */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell (tauDPCH) */
+ FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-RGCH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/
+ kal_uint8 signature_seq; /* E-RGCH signature sequence 0~39*/
+ kal_uint8 rg_comb_index; /* RG combination index. 0 ~ 5 */
+} FDD_ergch_info_T;
+
+typedef struct _FDD_ref_etfci_T
+{
+ kal_uint8 ref_etfci; /* Reference E-TFCI. 0~127 */
+ /* __UMTS_R7__ */
+ kal_uint8 ref_etfci_po; /* Reference E-TFCI PO. 0~31 */
+} FDD_ref_etfci_T;
+
+#ifdef __UMTS_R8__
+/* [R8] Minimum reduced E-DPDCH gain factor */
+typedef enum _FDD_beta_ed_reduced_min_E
+{
+ FDD_beta_ed_8_15 = 0, /* 8/15 */
+ FDD_beta_ed_11_15, /* 11/15 */
+ FDD_beta_ed_15_15, /* 15/15 */
+ FDD_beta_ed_21_15, /* 21/15 */
+ FDD_beta_ed_30_15, /* 30/15 */
+ FDD_beta_ed_42_15, /* 42/15 */
+ FDD_beta_ed_60_15, /* 60/15 */
+ FDD_beta_ed_84_15 /* 84/15 */
+} FDD_beta_ed_reduced_min_E;
+#endif /* __UMTS_R8__ */
+
+typedef struct _FDD_edpdch_info_T
+{
+ /* __UMTS_R7__ */
+ kal_uint8 etfci_table_index; /* E-TFCI table index. 0~1. If the UE is operating in 16QAM, the value is increased by 2. 0~3. */
+ kal_uint8 num_of_ref_etfci; /* number of reference etfci. range:1~8 */
+ FDD_ref_etfci_T ref_etfci[FDD_MAX_REF_ETFCI_NUM]; /* reference E-TFCIs */
+ FDD_edch_sf_E max_ch_code; /* Max. channelisation code */
+ kal_uint8 ul_dpch_num; /* # of UL DPCH, range:0~FDD_MAX_ULDPCH*/
+ kal_uint8 pl_non_max; /* PLnon-max*100/4, range:11~25 */
+#ifdef __UMTS_R8__
+ FDD_beta_ed_reduced_min_E beta_ed_reduced_min; /* Minimum reduced E-DPDCH gain factor */
+#endif /* __UMTS_R8__ */
+} FDD_edpdch_info_T;
+
+typedef struct _FDD_edpcch_info_T
+{
+ kal_uint8 edpcch_po; /* E-DPCCH/DPCCH power offset. 0~8 */
+#ifdef __UMTS_R7__
+ kal_uint8 etfci_boost; /* [Range] Integer(0..127)E-TFCI threshold beyond which boosting of EDPCCH is enabled */
+ kal_uint8 delta_t2tp; /* [Range] Integer (0..6)If E-TFCI-Boost is set to 127 this IE is not needed, otherwise it is mandatory. */
+ kal_bool edpdch_pwr_interpolation; /* True means EDPDCH power Interpolation formula is used, False means EDPDCH power
+ Extrapolation formula is used for the computation of the gain factor £]ed */
+#endif /* __UMTS_R7__ */
+} FDD_edpcch_info_T;
+
+typedef struct _FDD_edch_harq_info_T
+{
+ FDD_edch_rv_config_E edch_rv_config; /* RV config */
+} FDD_edch_harq_info_T;
+
+
+/**********************************************************************************************************************/
+/*********************************** UL1 Interface maintained by UL1D (Begin) *************************************/
+/**********************************************************************************************************************/
+/*UL1D*/typedef enum _FDD_hs_dsch_dc_data_source_E
+/*UL1D*/
+{
+ /*UL1D*/ FDD_PRIMARY_CELL = 0, /* data from primary cell, only hsdsch_data[] should be processed */
+ /*UL1D*/ FDD_SECONDARY_CELL = 1, /* data from secondary cell, only hsdsch_data2[] should be processed */
+ /*UL1D*/ FDD_DUAL_CELL = 2 /* data from dual cells, both hsdsch_data[] and hsdsch_data2[] should be processed*/
+ /*UL1D*/
+} FDD_hs_dsch_dc_data_source_E;
+/*UL1D*/
+/*UL1D*/typedef struct _FDD_uldch_data_req_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn;
+ /*UL1D*/ kal_uint8 ul_mac_event; /* bit 0: UL DCH setup, */
+ /*UL1D*/ /* bit 1: UL DCH release */
+ /*UL1D*/ /* bit 2: UL DCH modify */
+ /*UL1D*/ kal_uint8 dpdch_num;
+ /*UL1D*/ kal_bool restartSRB;
+ /*UL1D*/ kal_bool tx_enable;
+ /*UL1D*/ kal_bool tx_suspend;
+ /*UL1D*/ kal_uint8 tfc_status[FDD_MAX_UL_TFC];
+ /*UL1D*/
+} FDD_uldch_data_req_T;
+/*UL1D*/
+/*UL1D*/
+/*UL1D*/typedef struct _FDD_uldch_data_ind_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn;
+ /*UL1D*/ kal_uint8 num_trch;
+ /*UL1D*/ FDD_ulTrchData trchInfo[FDD_MAX_TRCH_NUM]; /* TrCH information including number of TB and TB size. Note that only 1 TRCH is included in RACH data. */
+ /*UL1D*/ kal_uint16 tfci;
+ /*UL1D*/ kal_uint16 num_data[FDD_MAX_TRCH_NUM]; /* num_data[FDD_MAX_TRCH_NUM]. It means the total TB size on 1 TRCH. Value: 0 ~ FDD_MAX_UL_TB. */
+ /*UL1D*/ kal_uint8 *data[FDD_MAX_TRCH_NUM];
+ /*UL1D*/#ifdef UNIT_TEST
+ /*UL1D*/ void *addr;
+ /*UL1D*/#endif /* UNIT_TEST */
+ /*UL1D*/
+} FDD_uldch_data_ind_T;
+/*UL1D*/
+/*UL1D*//* Input parameters of FDD_umac_e_dch_tick_1() */
+/*UL1D*/typedef struct _FDD_etfc_eval_info_req_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn;
+ /*UL1D*/ kal_uint8 subframe;
+ /*UL1D*/ kal_uint8 mac_event; /* bit0: setup; bit1: release; bit2: modify */
+ /*UL1D*/ FDD_edch_tti_E edch_tti;
+ /*UL1D*/ kal_bool is_tx_suspend[FDD_E_SCELL_TOTAL];
+ /*UL1D*/#if defined( __GEMINI__ ) && defined( __UMTS_RAT__ )
+ /*UL1D*/ kal_bool is_gemini_tx_suspend; /* tx suspended due to Gemini */
+ /*UL1D*/#endif
+ /*UL1D*/ kal_bool compressed_2ms; /* subframe overlaps TG (Refer this value only when 2ms TTI) */
+ /*UL1D*/ kal_uint8 num_of_non_dtx_slots_10ms; /* number of non-gap slots in the corresponding TTI (Refer this value only when 10ms TTI) */
+ /*UL1D*/ kal_uint8 e_agch_result[FDD_E_SCELL_TOTAL]; /* 0: Invalid 1:primary E-RNTI detected 2: secondary E-RNTI detected */
+ /*UL1D*/ kal_uint8 e_agch_data[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint8 e_hich_result_serving[FDD_E_SCELL_TOTAL]; /*0:DTX, 1:ACK, 2:invalid(shall ASSERT), 3:NACK */
+ /*UL1D*/ kal_uint8 e_hich_result_non_serving[FDD_E_SCELL_TOTAL]; /*0:DTX or NACK, 1:ACK, 2:invalid(shall ASSERT) , 3:invalid(shall ASSERT)*/
+ /*UL1D*/ kal_uint8 e_rgch_result_serving[FDD_E_SCELL_TOTAL]; /*0:HOLD or DTX, 1:UP, 2:invalid(shall ASSERT), 3:DOWN */
+ /*UL1D*/ kal_uint8 e_rgch_result_non_serving[FDD_E_SCELL_TOTAL]; /*0:HOLD or DTX, 1:invalid(shall ASSERT), 2:invalid(shall ASSERT), 3:DOWN */
+ /*UL1D*/
+ /*UL1D*/ kal_bool isTtiChangeSuspend;
+ /*UL1D*/ kal_bool isServingCellChange[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_bool isServingCellChNotPartOfPrevEdchRls[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint16 mac_harq_event; /* bit 0: TTI change */
+ /*UL1D*/ /* bit 1: E-TFCI table index change */
+ /*UL1D*/ /* bit 2: HARQ RV ReConfiguration */
+ /*UL1D*/ /* bit 3: PLnon-max change */
+ /*UL1D*/ /* bit 4: Secondary cell activated */
+ /*UL1D*/ /* bit 5: Secondary cell deactivated */
+ /*UL1D*/ kal_bool insufficient_preamble[FDD_E_SCELL_TOTAL]; // Cannot transmit E-DCH due to insufficient UL DPCCH preamble.
+ /*UL1D*/ kal_bool match_mac_dtx_cycle[FDD_E_SCELL_TOTAL]; // If the condition of last paragraph of 25.321 11.8.1.4 is fulfilled.
+ /*UL1D*/ kal_bool is_dtx_cycle_2[FDD_E_SCELL_TOTAL]; // The DTX feature is configured by higher layers, and there has not been any E-DCH transmission for the last "Inactivity Threshold for UE DTX cycle 2" E-DCH TTIs.
+ /*UL1D*/ kal_bool is_cedch; /*Notify UMAC if common EDCH or not*/
+ /*UL1D*/ kal_uint8 *sf_of_etfci;
+ /*UL1D*/ kal_bool restartSRB;
+ /*UL1D*/ kal_uint32 SlotTick_FRC; /* The absolute FRC (free-run counter) value of 1 slot ahead of Tx timing, the unit is micro-second (us) */
+ /*UL1D*/ /* Ex: FRC value of slot 8 will be provided if Tx on slot 9 */
+ /*UL1D*/
+ /*UL1D*/
+} FDD_etfc_eval_info_req_T ;
+/*UL1D*/
+/*UL1D*//* Output parameters of FDD_umac_e_dch_tick_1() */
+/*UL1D*/typedef struct _FDD_etfc_eval_info_ind_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/ kal_uint8 harq_id; /* 2ms TTI: 0..7, 10ms TTI: 0..3 */
+ /*UL1D*/ kal_bool tx_enable[FDD_E_SCELL_TOTAL]; /* true=on, false=off */
+ /*UL1D*/ kal_bool is_new_tx[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint8 delta_harq[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_bool collision_resolved;
+ /*UL1D*/ kal_bool is_tebs_larger_than_0;
+ /*UL1D*/ kal_uint8 serving_grant[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint8 non_scheduled_delta_harq;
+ /*UL1D*/ kal_uint16 non_scheduled_data_size;
+ /*UL1D*/
+} FDD_etfc_eval_info_ind_T;
+/*UL1D*/
+/*UL1D*//* Input parameters of FDD_umac_e_dch_tick_2() */
+/*UL1D*/typedef struct _FDD_edch_data_req_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/ FDD_edch_scell_E edch_cell;
+ /*UL1D*/ FDD_edch_tti_E edch_tti; /* E-DCH TTI 2ms or 10ms */
+ /*UL1D*/
+ /*UL1D*/ kal_bool compressed_2ms; /* If the corresponding subframe overlaps TG (Refer this value only when 2ms TTI) */
+ /*UL1D*/ kal_uint8 num_of_non_dtx_slots_10ms; /* number of non-gap slots in the corresponding TTI (Refer this value only when 10ms TTI) */
+ /*UL1D*/ kal_uint8 *supported_etfci_bitmap; /* 2 LSB bits of [0] = etfci 0, 2 MSB bits of [31] = etfci 127. */
+ /*UL1D*/ /* 11=support, 10=power not support, 01=data size not support, 00=not support */
+ /*UL1D*/ kal_uint16 uph_in_dB; /*UE transmission power headroom reported by UL1(unit: dB)*/
+ /*UL1D*/
+} FDD_edch_data_req_T ;
+/*UL1D*/
+/*UL1D*//* Output parameters of FDD_umac_e_dch_tick_2() */
+/*UL1D*/typedef struct _FDD_edch_data_ind_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/ kal_bool tx_enable; /* true=on, false=off */
+ /*UL1D*/ kal_uint8 harq_id; /* 2ms TTI: 0..7, 10ms TTI: 0..3 */
+ /*UL1D*/ kal_bool is_new_tx;
+ /*UL1D*/ kal_uint8 etfci; /* Range: 0..127 */
+ /*UL1D*/ kal_uint8 ntx1; /* 10 ms TTI: 8..15, 2ms TTI: don't care */
+ /*UL1D*/ kal_bool happy;
+ /*UL1D*/ kal_uint8 rsn; /* Range: 0..3 */
+ /*UL1D*/ kal_uint8 delta_harq; /* Range: 0..6 */
+ /*UL1D*/ kal_uint16 tb_size;
+ /*UL1D*/ kal_uint8 *data; /* The buffer contains MAC-es/e PDU data */
+ /*UL1D*/ /* Must be 4 bytes alignment */
+ /*UL1D*/ /* NULL if tx_enable == false */
+ /*UL1D*/ kal_uint8 tebs; /* SI of UMAC */
+ /*UL1D*/ kal_uint8 re_tx_num; /* re-transmission number */
+ /*UL1D*/ kal_uint32 ScheduledGrantPayloadBits; /* Configured SG bits; for RG judgement */
+ /*UL1D*/ kal_uint32 ScheduledGrantUsedBits; /* Used SG bits; for RG judgement */
+ /*UL1D*/ kal_bool scheduled; /* Whether this is scheduled E-DCH transmission or not. */
+ /*UL1D*/
+} FDD_edch_data_ind_T;
+/*UL1D*/
+/*UL1D*//* No output parameters of FDD_umac_e_dch_tick_3() */
+/*UL1D*/
+/*UL1D*//* Input parameters of FDD_umac_e_dch_tick_3() */
+/*UL1D*/typedef struct _FDD_umac_edch_data_req_tick_3_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/
+} FDD_umac_edch_data_req_tick_3_T;
+/*UL1D*/
+/*UL1D*//* Output parameters of FDD_umac_e_dch_tick_3() */
+/*UL1D*/typedef struct _FDD_umac_edch_data_ind_tick_3_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/
+} FDD_umac_edch_data_ind_tick_3_T;
+/*UL1D*/
+/*UL1D*/extern kal_bool FDD_UL1D_Check_ASU( kal_int32 added_cell_tm/* echips */, kal_uint16 added_cell_dpch_offset /* chips */ );
+/*UL1D*/extern kal_bool FDD_UL1D_RxDualCarrier_Check( kal_uint16 pri_uarfcn, kal_uint16 sec_uarfcn, kal_int16 *pri_sec_diff );
+/*UL1D*/extern kal_bool FDD_UL1D_RxMultiCarrier_Check( kal_uint16 *uarfcn_list, kal_uint8 num_uarfcn );
+/*UL1D*/extern kal_bool FDD_UL1D_TxMultiCarrier_Check( kal_uint16 *uarfcn_list, kal_uint8 num_uarfcn );
+/*UL1D*/kal_uint16/*100kHz*/ FDD_UL1D_RRC_UlUarfcnToFrequency( kal_uint16 uarfcn );
+/**********************************************************************************************************************/
+/*********************************** UL1 Interface maintained by UL1D (End) ***************************************/
+/**********************************************************************************************************************/
+/* Input parameters of FDD_umac_e_dch_tick_5() */
+typedef struct
+{
+ kal_bool match_mac_dtx_cycle;
+ kal_uint8 long_preamble_target_cfn; // 0..255.
+ kal_uint8 long_preamble_target_subframe; // 10ms=0, 2ms=0..4.
+ FDD_edch_scell_E edch_cell;
+} FDD_etfc_eval_lpr_info_req_T;
+
+#ifdef __UMTS_R7__
+/* [R7] Enumeration of rrc state. To distinguish the usage of HS-DSCH */
+typedef enum _FDD_rrc_state_E
+{
+ FDD_CELL_DCH,
+ FDD_URA_PCH,
+ FDD_CELL_PCH,
+ FDD_IDLE_FACH,
+ FDD_CELL_FACH
+} FDD_rrc_state_E;
+
+/* [R7] Enumeration of octet aligned table 9.2.3.2 is used, else bit aligned table 9.2.3.1 is used in [25.321]. */
+typedef enum _FDD_hs_tbsize_table_E
+{
+ FDD_BIT_ALIGNED = 0,
+ FDD_OCTET_ALIGNED
+} FDD_hs_tbsize_table_E;
+
+/* [R7] Enumeration of dtx_drx_status. */
+typedef enum _FDD_dtx_drx_status_E
+{
+ FDD_DTX_DRX_OFF = 0, /* Disable CPC operation */
+ FDD_DTX_DRX_NEW_TIMING, /* Use new CPC configuration */
+ FDD_DTX_DRX_ON_REVERT, /* Uses the old CPC configuration when HHO revert. Consider oly the HS-SCCH orders which were acknowledged prior to the activation timer of the received message. */
+ FDD_DTX_DRX_ON_HS_SERV_CELL_CHANGE, /* Uses the old CPC configuration when serving cell was changed. Consider the HS-SCCH order were never received. */
+ FDD_DTX_DRX_ALL_RL_TIMING_MODIFY, /* If the CPC choice timing is ¡§continue¡¨ when receiving ALL RL TIMING MODIFY, Uses the old CPC configuration. */
+ FDD_DTX_DRX_INVALID /* Invalid DTX_DRX status */
+} FDD_dtx_drx_status_E;
+
+/* [R7] Enumeration of enabling delay. Uint is radio frame. */
+typedef enum _FDD_enabling_delay_E
+{
+ FDD_ED_0 = 0,
+ FDD_ED_1,
+ FDD_ED_2,
+ FDD_ED_4,
+ FDD_ED_8,
+ FDD_ED_16,
+ FDD_ED_32,
+ FDD_ED_64,
+ FDD_ED_128
+} FDD_enabling_delay_E;
+
+/* [R7] Enumeration of ue_dtx_cycle2_inactivity_threshold. Uint is E-DCH TTIs. */
+typedef enum _FDD_ue_dtx_cycle2_inactivity_threshold_E
+{
+ FDD_dtx_cycle2_inaTrHd_1 = 0,
+ FDD_dtx_cycle2_inaTrHd_4,
+ FDD_dtx_cycle2_inaTrHd_8,
+ FDD_dtx_cycle2_inaTrHd_16,
+ FDD_dtx_cycle2_inaTrHd_32,
+ FDD_dtx_cycle2_inaTrHd_64,
+ FDD_dtx_cycle2_inaTrHd_128,
+ FDD_dtx_cycle2_inaTrHd_256
+} FDD_ue_dtx_cycle2_inactivity_threshold_E;
+
+/* [R7] Enumeration of ue_dtx_long_preamble_length. Uint is slot. */
+typedef enum _FDD_ue_dtx_long_preamble_length_E
+{
+ FDD_slot_2 = 0,
+ FDD_slot_4,
+ FDD_slot_15,
+ FDD_slot_invalid
+} FDD_ue_dtx_long_preamble_length_E, FDD_dtx_pream_len_E;
+
+/* [R7] Enumeration of cqi_dtx_timer period. Uint is subframe. */
+typedef enum _FDD_cqi_dtx_timer_E
+{
+ FDD_subframe_0 = 0,
+ FDD_subframe_1,
+ FDD_subframe_2,
+ FDD_subframe_4,
+ FDD_subframe_8,
+ FDD_subframe_16,
+ FDD_subframe_32,
+ FDD_subframe_64,
+ FDD_subframe_128,
+ FDD_subframe_256,
+ FDD_subframe_512,
+ FDD_subframe_infinity
+} FDD_cqi_dtx_timer_E;
+
+/* [R7] Enumeration of ue_dpcch_burst. Uint is subframe. */
+typedef enum _FDD_ue_dpcch_burst_E
+{
+ FDD_burst_1 = 0,
+ FDD_burst_2,
+ FDD_burst_5
+} FDD_ue_dpcch_burst_E;
+
+/* [R7] Enumeration of mac_inactivity_threshold. Uint is E-DCH TTI. */
+typedef enum _FDD_mac_inactivity_threshold_E
+{
+ FDD_mac_inaTrHd_1 = 0,
+ FDD_mac_inaTrHd_2,
+ FDD_mac_inaTrHd_4,
+ FDD_mac_inaTrHd_8,
+ FDD_mac_inaTrHd_16,
+ FDD_mac_inaTrHd_32,
+ FDD_mac_inaTrHd_64,
+ FDD_mac_inaTrHd_128,
+ FDD_mac_inaTrHd_256,
+ FDD_mac_inaTrHd_512,
+ FDD_mac_inaTrHd_infinity
+} FDD_mac_inactivity_threshold_E;
+
+/* [R7] Enumeration of ue_rx_cycle. Uint is subframe. */
+typedef enum _FDD_ue_drx_cycle_E
+{
+ FDD_drx_cycle_4 = 0,
+ FDD_drx_cycle_5,
+ FDD_drx_cycle_8,
+ FDD_drx_cycle_10,
+ FDD_drx_cycle_16,
+ FDD_drx_cycle_20
+} FDD_ue_drx_cycle_E;
+
+/* [R7] Enumeration of ue_drx_cycle_inactivity_threshold. Uint is subframe. */
+typedef enum _FDD_ue_drx_cycle_inactivity_threshold_E
+{
+ FDD_drx_cycle_inaTrHd_0 = 0,
+ FDD_drx_cycle_inaTrHd_1,
+ FDD_drx_cycle_inaTrHd_2,
+ FDD_drx_cycle_inaTrHd_4,
+ FDD_drx_cycle_inaTrHd_8,
+ FDD_drx_cycle_inaTrHd_16,
+ FDD_drx_cycle_inaTrHd_32,
+ FDD_drx_cycle_inaTrHd_64,
+ FDD_drx_cycle_inaTrHd_128,
+ FDD_drx_cycle_inaTrHd_256,
+ FDD_drx_cycle_inaTrHd_512
+} FDD_ue_drx_cycle_inactivity_threshold_E;
+
+/* [R7] Enumeration of ue_grantMonitoring_inactivity_threshold. Uint is subframe. */
+typedef enum _FDD_ue_grantMonitoring_inactivity_threshold_E
+{
+ FDD_graMon_inaTrhd_0 = 0,
+ FDD_graMon_inaTrhd_1,
+ FDD_graMon_inaTrhd_2,
+ FDD_graMon_inaTrhd_4,
+ FDD_graMon_inaTrhd_8,
+ FDD_graMon_inaTrhd_16,
+ FDD_graMon_inaTrhd_32,
+ FDD_graMon_inaTrhd_64,
+ FDD_graMon_inaTrhd_128,
+ FDD_graMon_inaTrhd_256
+} FDD_ue_grantMonitoring_inactivity_threshold_E;
+
+/* [R7] HS-SCCH less mode status in CELL_DCH state */
+typedef enum _FDD_hs_scch_less_status_E
+{
+ FDD_HS_SCCH_LESS_OFF = 0, /* disable HS-SCCH less operation and all HS-SCCH less parameters are invalid. */
+ FDD_HS_SCCH_LESS_ON, /* use new HS-SCCH less configuration and reset order. */
+ FDD_HS_SCCH_LESS_ON_REVERT, /* Uses the old HS-SCCH less configuration when HHO revert or 3G to 2G inter-RAT procedure revert. */
+ FDD_HS_SCCH_LESS_ALL_RL_TIMING_MODIFY, /* If the HS-SCCH less operation choice timing is "continue" when receiving ALL RL TIMING MODIFY,
+ * uses the old HS-SCCH less configuration without reset order. */
+ FDD_HS_SCCH_LESS_INVALID /* SLCE internal use, won't config this enum to UL1. */
+} FDD_hs_scch_less_status_E;
+#endif /* __UMTS_R7__ */
+
+#ifdef __UMTS_R8__
+/* [R8] Enumeration of enhanced CELL_FACH DRX status */
+typedef enum _FDD_hs_cell_fach_drx_status_E
+{
+ FDD_DRX_OFF = 0, /* No DRX in CELL_FACH state or ETWS reception is on-going */
+ FDD_DRX_ON_NORMAL, /* UL1 should start CELL_FACH DRX when the normal criterion is fulfilled */
+ FDD_DRX_ON_ETWS_END, /* SLCE should set this enum when the ETWS procedure ends */
+ FDD_DRX_INVALID /* SLCE internal use. Invalid for UL1. */
+} FDD_hs_cell_fach_drx_status_E;
+
+/* [R8] inactivity timer to start HS CELL_FACH DRX */
+typedef enum _FDD_hs_t321_E
+{
+ FDD_t321_100 = 0, /* 100ms */
+ FDD_t321_200 = 1, /* 200ms */
+ FDD_t321_400 = 2, /* 400ms */
+ FDD_t321_800 = 3 /* 800ms */
+} FDD_hs_t321_E;
+
+/* Length of inactivity timer T321/T328/T329 */
+typedef enum
+{
+ FDD_EFACH_DRX_1_LEVEL,
+ FDD_EFACH_DRX_2_LEVEL
+} FDD_hs_cell_fach_drx_level_E;
+
+/* Length of inactivity timer T321/T328/T329 */
+typedef enum
+{
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_INVALID,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_20MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_40MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_60MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_80MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_100MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_200MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_400MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_500MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_800MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_1000MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_2000MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_4000MS
+} FDD_hs_cell_fach_drx_status_timer_length_E;
+
+/* Length of EFACH DRX cycle */
+typedef enum
+{
+ FDD_EFACH_DRX_CYCLE_LEN_INVALID,
+ FDD_EFACH_DRX_CYCLE_LEN_2_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_4_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_8_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_16_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_32_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_64_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_128_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_256_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_512_FRAMES
+} FDD_hs_cell_fach_drx_cycle_E;
+
+/* Length of EFACH DRX burst */
+typedef enum
+{
+ FDD_EFACH_DRX_BURST_LEN_INVALID,
+ FDD_EFACH_DRX_BURST_LEN_1_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_2_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_4_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_8_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_16_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_2_SUBFRAMES,
+ FDD_EFACH_DRX_BURST_LEN_4_SUBFRAMES
+} FDD_hs_cell_fach_drx_rx_burst_E;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/* [R8] variable to control UL1 DC HS-DSCH receiving */
+typedef enum _FDD_dc_hsdpa_status_E
+{
+ FDD_DC_HSDPA_OFF = 0, /* Disable DC-HSDPA operation and all DC-HSDPA parameters are invalid. */
+ FDD_DC_HSDPA_ON, /* Use new DC-HSDPA configuration and reset order */
+ FDD_DC_HSDPA_ON_REVERT, /* Uses the old DC-HSDPA configuration when HHO revert or 3G to 2G inter-RAT procedure revert. */
+ FDD_DC_HSDPA_ALL_RL_TIMING_MODIFY, /* If the DC-HSDPA choice timing is "continue" when receiving ALL_RL_TIMING_MODIFY,
+ * uses the old DC-HSDPA configuration without reset order. */
+ FDD_DC_HSDPA_ON_WITHOUT_RESET_ORDER, /* Use new DC-HSDPA configuration and do not reset order */
+ FDD_DC_HSDPA_INVALID /* SLCE internal use, won't config this enum to UL1 */
+} FDD_dc_hsdpa_status_E;
+
+/* [R8] Specify that E-DCH transmission is in dedicated state or common state */
+typedef enum _FDD_edch_transmission_type_E
+{
+ FDD_EDCH_IN_DCH_STATE = 0, /* E-DCH allocated in dedicated state */
+ FDD_EDCH_IN_COMMON_STATE /* E-DCH allocated in common state */
+} FDD_edch_transmission_type_E;
+
+/* [R8] common E-DCH suspend cause. UL1 Internal use */
+typedef enum _FDD_cedch_suspend_cause_type_E
+{
+ FDD_CEDCH_NONE = 0, /* no common EDCH */
+ FDD_CEDCH_SUSPEND_RLF, /* common EDCH terminate due to RLF */
+ FDD_CEDCH_SUSPEND_SYNCAA_FAIL, /* common EDCH terminate due to Sync AA failure */
+ FDD_CEDCH_SUSPEND_PROCESS_TERMINATION, /* common EDCH terminate from UMAC */
+ FDD_CEDCH_SUSPEND_PREAMBLE, /* common EDCH terminate when AI result has not been received by UL1C */
+ FDD_CEDCH_SUSPEND_CHANNEL_RELEASE /* common EDCH terminate due to channel release */
+} FDD_cedch_suspend_cause_type_E;
+
+/* [R8] Transport channel type in random access procedure */
+typedef enum _FDD_cell_fach_ul_trch_type_E
+{
+ FDD_CELL_FACH_UL_TRCH_TYPE_RACH = 0, /* random access attemp for RACH transmission */
+ FDD_CELL_FACH_UL_TRCH_TYPE_EDCH /* random access attemp for E-DCH transmission */
+} FDD_cell_fach_ul_trch_type_E;
+#endif /* __UMTS_R8__ */
+
+
+#ifdef __UMTS_R7__
+typedef struct _FDD_hs_scch_less_info_T
+{
+ FDD_hs_scch_less_status_E hs_scch_less_status; /* HS-SCCH less mode control flag */
+ kal_uint8 hs_scch_less_hspdsch_code_index; /* [Range] Integer(1..15) Index of the first HS-PDSCH code */
+ FDD_hs_tb_size_list_T hs_scch_less_tb_size_list[FDD_MAX_SCCH_LESS_BLK_NUM]; /* 1..<maxHSSCCHLessTrBlk > maxHSSCCHLessTrBlk = 4 */
+} FDD_hs_scch_less_info_T;
+
+typedef struct _FDD_hs_fach_pch_rl_info_T
+{
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */
+ /* If the value of tm is not equal to -1, UL1 will use this value */
+ /* If the value of tm is equal to -1, UL1 will not use this value */
+ kal_int16 rscp; /* Serving cell RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
+} FDD_hs_fach_pch_rl_info_T;
+
+typedef struct _FDD_hs_dtx_drx_timing_info_T
+{
+ FDD_enabling_delay_E ED; /* Time threshold the UE waits until enabling a new timing pattern for DTX/ DRX operation. Uint is radio frame. */
+ kal_uint8 ue_dtx_drx_offset; /* [Range]: 0~159 Units of subframes. Offset of the DTX and DRX cycles at the given TTI. */
+} FDD_hs_dtx_drx_timing_info_T;
+
+typedef struct _FDD_hs_dtx_param_T
+{
+ kal_bool ue_dtx_on; /* DTX operation enable/ disable */
+ kal_bool tti_change; /* E-DCH TTI is change to 2ms->10ms or 10ms->2ms */
+ kal_uint8 ue_dtx_cycle1; /* DPCCH activity pattern.(1, 5, 10, 20 subframes for 10 ms TTI; 1, 4, 5, 8, 10, 16, 20 subframes for 2 ms TTI) */
+ kal_uint8 ue_dtx_cycle2; /* DPCCH activity pattern.(5, 10, 20, 40, 80, 160 subframes for 10 ms TTI;4, 5, 8, 10, 16, 20, 32, 40, 64, 80, 128, 160 subframes for 2 ms TTI) */
+ FDD_ue_dtx_cycle2_inactivity_threshold_E cycle2_inactivity_threshold; /* When to activate the UE DTX cycle 2 after the last uplink data transmission */
+ FDD_ue_dtx_long_preamble_length_E preamble_length; /* Uplink preamble length. Units of slots.Default value is 2 slots */
+ FDD_cqi_dtx_timer_E timer_length; /* Number of subframes after an HS-DSCH reception during which the CQI reports have higher priority than the DTX pattern and are transmitted according to the regular CQI pattern */
+ FDD_ue_dpcch_burst_E dpcch_burst1; /* Length of DPCCH transmission when UE DTX cycle 1 is active Units of sub-frames */
+ FDD_ue_dpcch_burst_E dpcch_burst2; /* Length of DPCCH transmission when UE DTX cycle 2 is active Units of sub-frames */
+
+ kal_uint8 mac_dtx_cycle; /* Pattern of time instances where the start of uplink E-DCH transmission after inactivity is allowed.(5, 10, 20 subframes for 10 ms TTI; 1, 4, 5, 8, 10, 16, 20 subframes for 2 ms TTI */
+ FDD_mac_inactivity_threshold_E mac_inactivity_threshold; /* E-DCH inactivity time after which the UE can start E-DCH transmission only at given time. */
+} FDD_hs_dtx_param_T;
+
+typedef struct _FDD_hs_drx_param_T
+{
+ kal_bool ue_drx_on; /* DRX operation enable/ disable */
+ FDD_ue_drx_cycle_E drx_cycle_length; /* HS-SCCH reception pattern, i.e. how often UE has to monitor HSSCCH. */
+ FDD_ue_drx_cycle_inactivity_threshold_E drx_cycle_inactivity_threshold; /* Number of subframes after downlink activity where UE has to continuously monitor HS-SCCH. Units of subframes */
+ FDD_ue_grantMonitoring_inactivity_threshold_E grantMonitoring_inactivity_threshold; /* Number of subframes after uplink activity when UE has to continue to monitor E-AGCH/E-RGCH. Units of E-DCH TTIs. */
+ kal_bool ue_drx_grantMonitoring; /* whether the UE is required to monitor E-AGCH/E-RGCH when they overlap with the start of an HS-SCCH reception as defined in the HS-SCCH reception pattern */
+} FDD_hs_drx_param_T;
+
+typedef struct _FDD_hs_dtx_drx_info_T
+{
+ FDD_dtx_drx_status_E status;
+ FDD_hs_dtx_drx_timing_info_T timing;
+ FDD_hs_dtx_param_T hs_dtx_param;
+ FDD_hs_drx_param_T hs_drx_param;
+} FDD_hs_dtx_drx_info_T;
+
+typedef struct _FDD_hs_cell_pch_state_info_T
+{
+#ifdef UL1_PHASE3_TEST
+ kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+ kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#else
+// kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+// kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#endif
+ FDD_pich_info_T pich_info;
+ kal_uint8 pcch_hspdsch_ovsf; /* [Range] Integer (0..15) HS-PDSCH channel associated with the PICH for HSSCCH less PAGING TYPE 1 message transmission. */
+ kal_uint8 num_of_pcch_trans; /* [Range] Integer (1..5) number of subframes used to transmit the PAGING TYPE 1. */
+ kal_int8 pcch_tb_size_index[2]; /* [Range] Integer (1..32). -1 if this is invalid. Index of value range 1 to 32 of the MAC-ehs transport block size as described in appendix A of 25.321. */
+ FDD_hs_fach_pch_rl_info_T fach_pch_rl_info;
+} FDD_hs_cell_pch_state_info_T;
+
+typedef struct _FDD_hs_cell_fach_state_info_T
+{
+#ifdef UL1_PHASE3_TEST
+ kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+ kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#else
+// kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+// kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#endif
+ FDD_hs_fach_pch_rl_info_T fach_pch_rl_info;
+} FDD_hs_cell_fach_state_info_T;
+
+typedef struct _FDD_hs_cell_dch_state_info_T
+{
+ kal_bool dl_64QAM_on; /* 64QAM enable/disable */
+ FDD_hs_tbsize_table_E hsdsch_tbsize_table; /* If this IE is present, octet aligned table [25.321] is used, else bit aligned table [25.321] is used.
+ In DCH state, this field is assigned by SLCE. Otherthan DCH state, UL1 should use octet-aligned table by itself.*/
+} FDD_hs_cell_dch_state_info_T;
+
+typedef union _FDD_hspdsch_state_info_T
+{
+ FDD_hs_cell_pch_state_info_T cell_pch; /* The parameters in CELL_PCH or URA state. */
+ FDD_hs_cell_fach_state_info_T cell_fach; /* The parameters in CELL_FACH or IDLE_FAC state. */
+ FDD_hs_cell_dch_state_info_T cell_dch; /* The parameters in CELL_DCH state. */
+} FDD_hspdsch_state_info_T;
+
+#ifdef __UMTS_R8__
+typedef struct _FDD_hs_cell_fach_drx_T
+{
+ kal_bool interrupt_by_hsdsch; /* TRUE : the DRX operation can be interrupted by HS-DSCH data. */
+ /* FALSE: the DRX operation cannot be interrupted by HS-DSCH data. */
+ FDD_hs_cell_fach_drx_status_E hs_cell_fach_drx_status; /* enhanced CELL_FACH DRX status */
+ FDD_hs_cell_fach_drx_level_E drx_level; /* 1-level DRX or 2-level DRX cycle is used */
+ /* When NW configures R8 DRX pattern, SLCE will configure 2nd-level DRX parameters only
+ and set 1st-level DRX parameters as invalid */
+ FDD_hs_cell_fach_drx_status_timer_length_E second_timer_length; /* Inactivity timer to start 1-level HS CELL_FACH DRX. Set from T321(SIB5) or T329 (SIB22) */
+ FDD_hs_cell_fach_drx_cycle_E second_drx_cycle_length; /* HS CELL_FACH DRX cycle length during the 2nd DRX operation */
+ FDD_hs_cell_fach_drx_rx_burst_E second_drx_burst_length; /* the period within the 2nd HS DRX cycle that the UE continuously receive */
+ FDD_hs_cell_fach_drx_status_timer_length_E first_timer_length; /* Inactivity timer to start 2-level HS CELL_FACH DRX. Set from T321(SIB5) or T328 (SIB22) */
+ FDD_hs_cell_fach_drx_cycle_E first_drx_cycle_length; /* HS CELL_FACH DRX cycle length during the 1st DRX operation */
+ FDD_hs_cell_fach_drx_rx_burst_E first_drx_burst_length; /* The period within the 1st HS DRX cycle that the UE continuously receive */
+} FDD_hs_cell_fach_drx_T;
+
+typedef struct _FDD_secondary_hspdsch_info_T
+{
+ kal_bool dl_64QAM_on; /* If 64QAM supported in secondary HS-DSCH */
+ kal_uint16 h_rnti; /* h_rnti to decode secondary HS-DSCH receiving */
+ FDD_hs_tbsize_table_E hsdsch_tbsize_table; /* If dl_64QAM_on = KAL_TRUE, hsdsch_tbsize_table should be FDD_OCTET_ALIGNED. */
+} FDD_secondary_hspdsch_info_T;
+
+#define FDD_DC_HSDPA_ALL_CONFIG_BIT 0x7F
+typedef struct _FDD_dc_hsdpa_info_T
+{
+ kal_uint8 modify_field; /* Bit 0: FDD_hs_scch_info_T
+ * Bit 1: FDD_secondary_hspdsch_info_T
+ * Bit 2: psc
+ * Bit 3: meas_po
+ * Bit 4: dl_freq
+ * Bit 5: sttd
+ * Bit 6: dpch_offset */
+ FDD_dc_hsdpa_status_E dc_hsdpa_status; /* variable to control UL1 DC HS-DSCH receiving */
+ FDD_hs_scch_info_T hs_scch_info; /* Secondary HS-SCCH info. */
+ FDD_secondary_hspdsch_info_T sec_h_info; /* Secondary HS-PDSCH info. */
+ kal_uint16 psc; /* Primary scrambling code used in secondary H cell*/
+ kal_int8 meas_po; /* Measurement power offset, step = half dB. Range = -12~26 (-6dB~13dB)*/
+ kal_uint16 dl_freq; /* DL UARFCN, 0~16383*/
+ kal_bool sttd; /* TRUE: STTD is used for P-CPICH of the secondary cell
+ * FALSE: STTD is not used for P-CPICH of the secondary cell.*/
+#ifdef __UMTS_R9__
+ kal_uint8 dpch_offset; /* [R9] f-dpch offset of 2nd freq when DC-HSUPA is configured,
+ otherwise invalid value 0xFFFF is configured. (0~38144 chips by step of 256 )
+ [R10] For additional dc-hsdpa (dc_hsdpa_info[1]/dc_hsdpa_info[2]), this is always invalid value 0xFFFF. */
+#endif /*__UMTS_R9__*/
+} FDD_dc_hsdpa_info_T;
+
+typedef struct _FDD_dl_pc_info_T /* DL power control information used for common E-DCH */
+{
+ kal_uint8 tpc_target; /* range: 1~10, the actual TPC command error rate target is tpc_target/100 */
+ kal_uint8 dpc_mode; /*DL Power control mode. 0 or 1 or 2. In current spec, SLCE will always fix this field by 0 for common E-DCH. */
+ kal_uint8 fdpch_slot_format; /* range: 0~9. In current spec, SLCE will always fix this field by 0 for common E-DCH. */
+} FDD_dl_pc_info_T;
+
+typedef struct _FDD_ul_dpch_code_info_T /* UL DPCH information used for common E-DCH transmission */
+{
+ FDD_sc_type_E sc_type; /* short type or long type scrambling code */
+ kal_uint32 sc_code; /* 0 ~ 16777215 */
+} FDD_ul_dpch_code_info_T;
+
+typedef struct _FDD_edch_resource_list_T
+{
+ kal_uint8 s_offset; /* symbol offset. range: 0~9 */
+ kal_uint8 fdpch_ovsf; /* 0 ~ 255 */
+ kal_uint8 ehirgch_ovsf; /* ovsf code for receiving E-HICH and E-RGCH in common E-DCH transmission */
+ kal_uint8 hich_signature_seq; /* E-HICH signature sequence in common E-DCH transmission [Range: 0~39] */
+ kal_uint8 rgch_signature_seq; /* E-RGCH signature sequence in common E-DCH transmission [Range: 0~39, 0xff means invalid. No need to decode E-RGCH] */
+ FDD_ul_dpch_code_info_T ul_dpch_code_info; /* UL DPCH information used for common E-DCH transmission */
+} FDD_edch_resource_list_T;
+
+typedef struct _FDD_common_edch_info_T
+{
+ kal_uint8 add_tran_back_off; /* 0 ~ 15, unit is TTI */
+ kal_uint8 edch_resource_num; /* 1~32 */
+ FDD_edch_resource_list_T edch_resource_list[32]; /* common RLs for E-DCH transmission */
+ FDD_ul_pc_info_T ul_pc; /* ul power control info. */
+} FDD_common_edch_info_T;
+
+typedef struct _FDD_edch_specific_info_T
+{
+ kal_bool e_ai_ind; /* TRUE: E-AI should be used. FALSE: E-AI should not be used. */
+ kal_int8 po_p_e; /* -5 ~ 10 dB, power offset between last TX preamble and initial DPCCH */
+} FDD_edch_specific_info_T;
+
+
+typedef struct
+{
+ kal_bool d_hrnti_valid;
+ kal_uint16 d_hrnti;/*dH-RNTI*/
+
+ kal_bool c_hrnti_valid;
+ kal_uint16 c_hrnti;/*cH-RNTI*/
+
+ kal_bool b_hrnti_valid;
+ kal_uint16 b_hrnti;/*cH-RNTI*/
+
+} FDD_hs_hrnti_info_T;
+
+
+#ifdef __UMTS_R9__
+
+typedef enum
+{
+ FDD_DC_HSUPA_OFF, /* disable DC-HSUPA operation and all DC-HSUPA parameters are invalid */
+ FDD_DC_HSUPA_ON, /* use new DC-HSUPA configuration and reset order.
+ The default status is deactivated until receiving HS-SCCH order to activate,
+ and don't need sync A procedure on 2nd freq. */
+ FDD_DC_HSUPA_ALL_RL_TIMING_MODIFY, /* If the DC-HSUPA choice timing is "continue" when receiving ALL_RL_TIMING_MODIFY,
+ SLCE uses the old DC-HSUPA configuration to UL1, and UL1 applies the configuration without reset order.
+ Do not apply sync A procedue no matter the DC-HSUPA status after E-DCH setup. */
+ FDD_DC_HSUPA_ON_WITHOUT_RESET_ORDER, /* Use new DC-HSUPA configuration and do not reset order.
+ Sync A will need if DC-HSUPA is activate after E-DCH setup, but not for E-DCH modify. */
+ FDD_DC_HSUPA_INVALID /* SLCE internal use, won't config this enum to UL1 */
+
+} FDD_dc_hsupa_status_E;
+
+typedef enum
+{
+ FDD_DC_HSUPA_MODIFY_NORMAL_CONFIG, /* Normal configuration */
+ FDD_DC_HSUPA_MODIFY_ASU, /* ASU configuration. */
+ FDD_DC_HSUPA_MODIFY_ALL_ACTIVE_SET, /* All active set cell change (RBR) */
+ FDD_DC_HSUPA_MODIFY_NUM
+} FDD_dc_hsupa_modify_type_E;
+
+
+typedef struct
+{
+ kal_bool pri_e_rnti_valid; /* Indicate if pri_e_rnti field is valid */
+ kal_uint16 pri_e_rnti; /* Primary E-RNTI assigned to UE */
+ kal_bool sec_e_rnti_valid; /* Indicate if sec_e_rnti field is valid */
+ kal_uint16 sec_e_rnti; /* Secondary E-RNTI assigned to UE */
+} FDD_sec_e_rnti_info_T;
+
+typedef struct
+{
+ kal_uint16 ul_freq; /* UL UARFCN */
+ kal_uint16 dl_freq; /* DL UARFCN */
+ FDD_sc_type_E sc_type; /* Type of scrambling code */
+ kal_uint32 sc_code; /* Scrambling code #. 0 ~ 16777215 */
+ FDD_beta_ed_reduced_min_E beta_ed_reduced_min; /* Minimum reduced E-DPDCH gain factor.
+ If not configured in RRC message, SLCE should set the default value "FDD_beta_ed_8_15". */
+ kal_uint8 dpcch_po_SecondaryULFrequency; /* power offset. Integer (0..7 by step of 1) */
+ kal_uint8 pc_pream; /* Power control Preamble. 0 ~ 7 frames */
+} FDD_sec_edch_info_common_T;
+
+#define FDD_DC_HSUPA_ALL_CONFIG_BIT 0x7F
+
+typedef struct
+{
+ /*** mandatory configuration ***/
+ FDD_dc_hsupa_status_E dc_hsupa_status; /* variable to control UL1 DC-HSUPA receiving */
+ FDD_dc_hsupa_modify_type_E modify_type; /* DC-HSUPA modify type */
+ kal_int16 edch_serv_rscp; /* RSCP of secondary edch serving cell. Range: -464 ~ -100 dBm.
+ SLCE always sets RSCP value from DB_cell without comparison.*/
+ /*** optional configuration ***/
+ kal_uint8 config_field; /* Indicates the configured field:
+ Bit 0: sec_e_rnti_info
+ Bit 1: sec_edch_info_common
+ Bit 2: dl_dpch_rl_delete/dl_dpch_rl_add
+ Bit 3: edch_serv_psc
+ Bit 4: eagch_info
+ Bit 5: ehich_info
+ Bit 6: ergch_info
+ All field must be configured when switching DC-HSUPA OFF to ON. */
+ /* Bit 0: sec_e_rnti_info */
+ FDD_sec_e_rnti_info_T sec_e_rnti_info; /* [TS25.331]10.3.6.116 Secondary serving E-DCH cell info */
+ /* Bit 1: sec_edch_info_common */
+ FDD_sec_edch_info_common_T sec_edch_info_common; /* [TS25.331]10.3.6.117 Secondary E-DCH info common */
+ /* Bit 2: dl_dpch_rl_delete/dl_dpch_rl_add */
+ kal_uint8 dl_dpch_rl_delete_num; /* Number of RL to be removed: 0~FDD_MAX_EDCH_RL */
+ kal_uint16 dl_dpch_rl_delete[FDD_MAX_EDCH_RL]; /* RL to be removed (PSC) */
+ kal_uint8 dl_dpch_rl_add_num; /* Number of DL DPCH RL to be added: 0~FDD_MAX_EDCH_RL */
+ FDD_dl_dpch_rl_T dl_dpch_rl_add[FDD_MAX_EDCH_RL]; /* DL DPCH info. for each RL.
+ If modify_type != ASU, dl_dpch_rl_add is the full set of DL DPCH RL info. */
+ /* Bit 3: edch_serv_psc */
+ kal_uint16 edch_serv_psc; /* serving E-DCH cell */
+ /* Bit 4: eagch_info */
+ FDD_eagch_info_T eagch_info; /* E-AGCH info */
+ /* Bit 5: ehich_info */
+ kal_uint8 ehich_info_num; /* Number of E-HICH info: 1~FDD_MAX_EDCH_RL */
+ FDD_ehich_info_T ehich_info[FDD_MAX_EDCH_RL]; /* E-HICH info */
+ /* Bit 6: ergch_info */
+ kal_uint8 ergch_info_num; /* Number of E-RGCH info: 0~FDD_MAX_EDCH_RL */
+ FDD_ergch_info_T ergch_info[FDD_MAX_EDCH_RL]; /* E-RGCH info */
+
+} FDD_dc_hsupa_info_T;
+
+#endif /* __UMTS_R9__ */
+#endif /* __UMTS_R8__ */
+#endif /* __UMTS_R7__ */
+
+#if defined (__L1_STANDALONE__ )
+/*HsDsch check Interface*/
+typedef struct
+{
+ kal_bool is_hsscch_result_valid ; // need each tti hsscch result
+ kal_bool is_valid_data ; // need each tti hspdsch result
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint8 s_drx;// need each subframe number
+ kal_bool is_scheduled;//need each tti scheduling information
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ kal_bool is_in_gap; // is current tti is gap
+ kal_bool is_postpone;// is postpone condition
+ kal_uint8 ndi;// is new data or retransmission (1: new data, 0: retransmssion)
+
+} FDD_IF_HSDSCH_PARAM_T;
+typedef struct
+{
+ kal_bool is_valid_data;// need each tti result
+ kal_uint8 ag_value;// need each tti result
+ kal_uint8 ag_scope;// need each tti result
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint8 s_drx;// need each subframe number
+ kal_bool is_tti_2ms;// need each tti result
+ kal_bool is_scheduled;//need each tti scheduling information
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ kal_bool is_in_gap;// is current tti is gap ,current test is without gap
+ FDD_edch_scell_E ecell_type;
+} FDD_IF_EAGCH_PARAM_T;
+typedef struct
+{
+ kal_uint8 e_rgch_result_serving; // need each tti result
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint8 s_drx;// need each subframe number
+ kal_bool is_tti_2ms;// need each tti result
+ kal_bool is_scheduled;// need each tti result
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ kal_bool is_in_gap;// is current tti is gap, current test is without gap
+ FDD_edch_scell_E ecell_type;
+} FDD_IF_ERGCH_PARAM_T;
+typedef struct
+{
+
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint16 scheduled_bimap;//need each slot result
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ FDD_edch_scell_E ecell_type;
+
+} FDD_IF_ULDPCCH_PARAM_T;
+#endif /*__L1_STANDALONE__*/
+
+typedef enum
+{
+ RAS_INVALID,
+ RAS_PATH_MAIN,
+ RAS_PATH_BOTH
+} RAS_PATH_T;
+
+typedef enum
+{
+ CS_PS_INVALID,
+ CS_ONLY,
+ CS_PS_BOTH,
+ PS_ONLY
+} FDD_IS_CS_PS;
+
+typedef struct
+{
+ kal_uint8 numElements;
+ kal_uint8 elements[NUM_MCC_MNC];
+} FDD_MCC_MNC_T;
+
+typedef struct
+{
+ FDD_MCC_MNC_T mcc;
+ FDD_MCC_MNC_T mnc;
+} FDD_PLMN_IDENTITY_T;
+
+typedef struct
+{
+ kal_uint8 cell_plmn_num;
+ FDD_PLMN_IDENTITY_T cell_plmn_info[NUM_PLMN_INFO];
+ kal_uint16 lac;
+ kal_uint16 rac;
+ kal_int16 cellidx;
+} FDD_PLMN_LAC_PARAM_T;
+typedef struct
+{
+ kal_uint8 radio_bearer_ID;
+ kal_uint32 rx_window_size;
+} FDD_RLC_WINDOW_SIZE_INFO_T;
+
+#endif
diff --git a/mcu/interface/l1/ul1/internal/ul1_protected_cnst.h b/mcu/interface/l1/ul1/internal/ul1_protected_cnst.h
new file mode 100644
index 0000000..f751c4f
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ul1_protected_cnst.h
@@ -0,0 +1,130 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_protected_cnst.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * Layer 1 related constant and enum definitions for MediaTek WCDMA software
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _UL1_PROTECTED_CNST_H
+#define _UL1_PROTECTED_CNST_H
+
+/*-------- BCH related constant ----------------------*/
+#define FDD_MIN_DECODE_FRAMES 2 /* SFN/SFN_MEAS mini decode frame */
+
+/*-------- TrCH related constant (For UL/DL 384Kbps capability) ----------------------*/
+#define FDD_MAX_DL_TFs 64 /* Maximum numbre of TFs per DL CCTrCH */
+#define FDD_MAX_UL_DATA 829 /* Maximum UL transport block array size. */
+
+/*-------- PhyCh related constant (For UL/DL 384Kbps capability) ----------------------*/
+#define FDD_MAX_RL_SYNC_STATUS 6 /* Maximum number of radio link sync status */
+
+#define FDD_MIN_FS_PRIORITY_LEVEL 2 /* Minimum number of FS priority level */
+
+
+#define FDD_MAX_PLMN_PER_LOCATION 15 /*Max possible PLMN IDs that can be detected in a given location*/
+#define FDD_MAX_PLMN_LIST_FILTER ( FDD_MAX_PLMN_PER_LOCATION * FDD_MAX_FREQ_EXCLUDE )
+#define FDD_MAX_MEAS_EVENT 8 /* Maximum number of measurement events */
+#define FDD_MAX_CPICH_MEAS_CELL 16 /* Maximum cell that can be reported in CPICH report */
+
+#ifdef __UMTS_R10_UL1__
+#define FDD_MAX_UMTS_ADJ_FREQ ( 1 + FDD_MAX_ADDI_DC_HSDPA ) /* Maximum number of ADJ frequency supported in a UMTS UE */
+#elif defined(__UMTS_R8__)
+#define FDD_MAX_UMTS_ADJ_FREQ 1 /* Maximum number of ADJ frequency supported in a UMTS UE */
+#else
+#define FDD_MAX_UMTS_ADJ_FREQ 0 /* Maximum number of ADJ frequency supported in a UMTS UE */
+#endif
+
+#define FDD_MAX_UMTS_INTRA_FREQ 1 /* Maximum number of intra frequency supported in a UMTS UE */
+#define FDD_MAX_UMTS_INTER_FREQ 2 /* Maximum number of inter frequency supported in a UMTS UE */
+
+#define FDD_REPORT_INFINITY 0xff /* Tx_power measurement report number infinity*/
+#define FDD_UMTS_FDD_MLL1_INFINITE_GAP ( -1 ) /* Infinite length of standby gap */
+
+/* For cell measurement clipping */
+#define FDD_RSCP_LOWER_BOUND ( -480 ) /* CSD limit= -508, but upper lauer request -480 */
+#define FDD_RSCP_UPPER_BOUND ( -20 )
+#define FDD_RSSI_LOWER_BOUND ( -480 )
+#define FDD_RSSI_UPPER_BOUND ( -20 )
+#define FDD_EcN0_LOWER_BOUND ( -100 )
+#define FDD_EcN0_UPPER_BOUND 0
+
+/* For EM reporting */
+#define FDD_EM_RSSI_ABNORMAL_LOWER_BOUND ( -468 ) // -117, mapping to RSSI_ABNORMAL_LOWER_BOUND defined in Wcore.h
+
+#define FDD_EM_REPORTING_RSSI_INVALID ( -255 )
+#define FDD_EM_REPORTING_RSCP_INVALID ( -255 )
+
+#define FDD_INVALID_INT8 (0x80) /* -128 */
+#define FDD_INVALID_UINT8 (0xFF)
+#define FDD_INVALID_INT16 (0x8000) /* -32768 */
+#define FDD_INVALID_UINT16 (0xFFFF)
+#define FDD_INVALID_INT32 (0x80000000) /* -2147483648 */
+#define FDD_INVALID_UINT32 (0xFFFFFFFF)
+
+#define UL1_EXTENDED_LCE_MODE0 (0)
+#define UL1_EXTENDED_LCE_MODE1 (1)
+#define UL1_EXTENDED_LCE_MODE2 (2)
+
+/*-------- Activation time related constant ----------------------*/
+#define FDD_INVALID_ACTT (kal_int16)0x7FFF /* Invalid activation time */
+
+/*-------- [R5R6] HS-DSCH related ----------------------*/
+#define FDD_MAX_SCCH_LESS_BLK_NUM 4
+#define FDD_MAX_DELTA_HARQ_NUM 7 /* 25.213 s4.2.1.3 tbl 1B.3 */
+#define FDD_MAX_SEC_FDPCH_RL 4
+#define FDD_HS_SECONDARY_CELL_NUM (FDD_MAX_SUPPORT_CELL-1)
+
+
+/*-------- TX Power Measurement related constant ----------------------*/
+#define FDD_MAX_TXP_REACHED 0x15555555 /* Criterion for max TX power reached: all slots in a frame reach max TX power. */
+#define FDD_MIN_TXP_REACHED 0x3FFFFFFF /* Criterion for min TX power reached: all slots in a frame reach min TX power. */
+#define FDD_MAX_MIN_TXP_SKIPPED 0x2AAAAAAA /* During CPC, if all slots are TX off or only DPCCH is transmitted. This frame is not counted for Max or Min Tx event criteria. */
+
+#endif
+
diff --git a/mcu/interface/l1/ul1/internal/ul1_protected_def.h b/mcu/interface/l1/ul1/internal/ul1_protected_def.h
new file mode 100644
index 0000000..89816a1
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ul1_protected_def.h
@@ -0,0 +1,68 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_protected_def.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * This file contains typedef, definition prototypes only used by L1
+ ****************************************************************************/
+
+#ifndef _UL1_PROTECTED_DEF_H
+#define _UL1_PROTECTED_DEF_H
+
+/* auto add by kw_check begin */
+#include "ul1_cnst.h"
+#include "kal_general_types.h"
+/* auto add by kw_check end */
+
+#include "gmss_public.h"
+
+#if defined(UL1_TX_PHASE3_TEST)
+#define UL1_TX_PHASE3_TEST_TK6291_ADD 1
+#define UL1_TX_PHASE3_TEST_TK6291_TODO 0
+#define UL1_TX_PHASE3_TEST_TK6291_REMOVE 0
+#endif
+
+
+#endif
diff --git a/mcu/interface/l1/ul1/internal/ul1_struct.h b/mcu/interface/l1/ul1/internal/ul1_struct.h
new file mode 100644
index 0000000..440893a
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ul1_struct.h
@@ -0,0 +1,3897 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_struct.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * Layer 1 and Protocol Stack message and callback function definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _UL1_STRUCT_H
+#define _UL1_STRUCT_H
+
+/* auto add by kw_check begin */
+#include "ul1_def.h"
+#include "kal_general_types.h"
+#include "ul1_cnst.h"
+/*#include "ul1tst_msg.h"*/
+#include "kal_public_defs.h" //MSBB change #include "stack_msgs.h"
+#include "kal_public_api.h" //MSBB change #include "app_ltlcom.h"
+/* auto add by kw_check end */
+#include "em_public_struct.h"
+
+#include "global_type.h" /* [UBin] For inclusion of erac_rat_enum */
+#include "mll1_umts_fdd.h" /* umts_fdd_dch_gap_struct */
+#if !defined(__XL1SIM__)
+#include "rsvak_public_enum.h" /* for freq_scan_type_enum */
+#endif
+
+#if defined(__ATERFTX_ERROR_HANDLE_ENHANCE__)
+#include "ps_public_enum.h" /*for error cause in AT+ERFTX EM changes*/
+#endif //__ATERFTX_ERROR_HANDLE_ENHANCE__
+
+/*****************************************************************************
+Request from 3G PS
+*****************************************************************************/
+typedef struct _fdd_cphy_bch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. should -1 (Immediate) */
+ kal_int16 rx_sfn; /* SFN for start BCH. -1 ~ 4095. -1 means immedaite */
+ kal_int32 tm; /* LST of the cell boundary. 0 ~ 38400*8-1 */
+ kal_int16 off; /* Frame # offset to LST. -1 ~ 4095. -1 means unknown */
+ kal_bool sfn_only; /* Only read SFN */
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_bool sttd; /* STTD setting */
+ kal_int8 sib7_index; /* Indicate which SIB Info in sib_list is SIB7 */
+ /* -1 means there is not SIB7 in the list */
+ kal_uint16 sib7_rep_cycle; /* 2 ~ 256. The meaning of sib7_rep_cycle becomes "SIB7 expiration timer / SIP_REP" */
+ /* The true value is 2^sib7_rep_cycle. */
+ kal_bool servingcell; /* MTK not used */
+ FDD_bch_priority_E bch_priority; /* Priority of this BCH */
+ kal_uint8 priority_level;
+ kal_uint8 sib_num; /* # of SIB to be read, 0 means all SIBs reception.*/
+ FDD_sib_info_T sib_list[FDD_MAX_SIB_PATTERN]; /* SIB information */
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ kal_uint16 priority_index; /*Priority_index for same priority channel in 3G Gemini project*/
+#endif
+
+ kal_bool is_auto_gap_support; /* this bch req is for rptCGI */
+
+} fdd_cphy_bch_setup_req_struct;
+
+typedef struct _fdd_cphy_bch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 4095. -1 means immediate */
+ kal_int16 rx_sfn; /* SFN for start BCH. -1 ~ 4095. -1 means immedaite */
+ kal_uint8 modify_flag; /* 0x01 : bch_priority is changed */
+ /* 0x02 : SIB information is changed */
+ /* 0x03 : Both bch_priority and SIB information are changed */
+ /*0x04: priority idx*/
+ kal_int8 sib7_index; /* Indicate which SIB Info in sib_list is SIB7 */
+ /* -1 means there is not SIB7 in the list */
+ kal_uint16 sib7_rep_cycle; /* 2 ~ 256. The meaning of sib7_rep_cycle becomes "SIB7 expiration timer / SIP_REP" */
+ /* The true value is 2^sib7_rep_cycle. */
+
+ FDD_bch_priority_E bch_priority; /* Priority of this BCH */
+ kal_uint8 priority_level;
+ kal_uint8 sib_num; /* # of SIB to be read */
+ FDD_sib_info_T sib_list[FDD_MAX_SIB_PATTERN]; /* SIB Information */
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ kal_uint16 priority_index; /*Priority_index for same priority channel in 3G Gemini project*/
+#endif
+
+} fdd_cphy_bch_modify_req_struct;
+
+typedef struct _fdd_cphy_bch_release_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_release_req_struct;
+
+typedef struct _fdd_cphy_pch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+ kal_bool is_CSFB; /* to specify this PCH setup is for CSFB redirection */
+ FDD_FACH_PCH_Info_T fach_pch_info; /* Channel information */
+} fdd_cphy_pch_setup_req_struct;
+
+typedef struct _fdd_cphy_pch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ FDD_pich_reconfig_type_E reconfig_type;
+ FDD_pich_drx_T pich_drx; /* Modified DRX information */
+#ifdef __SMART_PAGING_3G_FDD__
+ FDD_pich_smartpaging_T smartpaging_info;
+#endif
+#ifdef __UMTS_R7__
+ FDD_pich_drx_T pich_drx_cycle2; /* DRX parameters 2 for PICH. */
+ kal_uint16 drx_cycle2_time; /* if it's not 0. UL1 shall use pich_drx_2 for PICH receptin, else shall directly use pich_drx for PICH reception. 0~5120 ms */
+#endif /* __UMTS_R7__ */
+} fdd_cphy_pch_modify_req_struct;
+
+typedef struct _fdd_cphy_pch_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+} fdd_cphy_pch_release_req_struct;
+
+typedef struct _fdd_cphy_fach_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+ FDD_FACH_PCH_Info_T fach_pch_info; /* Channel information */
+} fdd_cphy_fach_setup_req_struct;
+
+typedef struct _fdd_cphy_fach_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ FDD_ctch_drx_T ctch_drx; /* Modified CTCH DRX information */
+} fdd_cphy_fach_modify_req_struct;
+
+typedef struct _fdd_cphy_fach_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+} fdd_cphy_fach_release_req_struct;
+
+typedef struct _fdd_cphy_rach_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ kal_uint16 ul_freq; /* UL UARFCN */
+ FDD_aich_info_T aich_info; /* AICH info and ASC setting for PRACH partition */
+ FDD_prach_info_T prach_info; /* PRACH information */
+ FDD_prach_power_T prach_power; /* PRACH power information */
+ kal_uint8 tfc_num; /* # of TFC. 1 ~ 32 (Only 1 TrCH for 1 PRACH) */
+ FDD_ul_rach_tfc_T tfcs[FDD_MAXTF]; /* TFCS (TFS) */
+ FDD_ul_rach_trch_T trch_list[1]; /* Only 1 TrCH */
+#ifdef __UMTS_R8__
+ FDD_cell_fach_ul_trch_type_E trch_type; /* the transport channel type of random access attemp */
+ FDD_edch_specific_info_T edch_specific_info; /* PRACH and AICH specific information used for common E-DCH transmission */
+#endif /* __UMTS_R8__ */
+} fdd_cphy_rach_setup_req_struct;
+
+typedef struct _fdd_cphy_rach_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+} fdd_cphy_rach_release_req_struct;
+
+typedef struct _fdd_cphy_dch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ FDD_dch_setup_msg_type_E setup_type; /* SETUP, TRHHO or TRHHO revert */
+ kal_int8 tm_rl_index; /* indicate the index of specific RL in array dl_dpch_rl[] which has the valid Tm value. */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+ kal_int16 rscp; /* Serving cell RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
+ kal_uint8 tid; /* Transaction id */
+
+ kal_uint8 dl_crc_ind; /* For those TrCHs whose CRC data should be sent to MAC,
+ their corresponding bit will be set to 1.
+ The MSB represents the lowest numbered TrCH ID.
+ */
+
+ kal_uint16 ul_freq; /* UL UARFCN */
+ kal_uint16 ul_tfc_num; /* # of TFC for UL DPCH */
+ FDD_ul_dpch_tfc_T ul_tfcs[FDD_MAX_UL_TFC]; /* UL TFCS */
+ kal_uint8 ul_trch_num; /* # of UL TrCH */
+ FDD_ul_dch_trch_T ul_trch_list[FDD_MAX_UL_TRCH]; /* UL DPCH TrCH Info */
+ FDD_ul_dpch_info_T ul_dpch_info;
+
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_uint16 dl_tfc_num; /* # of TFC for DL DPCH */
+ FDD_dl_tfc_T dl_tfcs[FDD_MAX_DL_TFC]; /* DL TFCS */
+ kal_uint8 dl_trch_num; /* # of DL TrCH */
+ FDD_dl_dch_trch_T dl_trch_list[FDD_MAX_DL_TRCH]; /* DL DPCH TrCH Info */
+ kal_int8 max_tx_power; /* Max allowed TX power. -50 ~ 33 dBm */
+ kal_int8 umts_power_class; /* UE capability*/
+
+ kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
+ FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
+
+ FDD_dl_dpch_rla_T dl_dpch_rla; /* DL Info & DL DPCH Info common for all RLs */
+ kal_uint8 rl_num; /* # of RL. 1 ~ 8 */
+ FDD_dl_dpch_rl_T dl_dpch_rl[FDD_MAX_RL]; /* DL Info & DL DPCH Info. for each RL */
+
+ FDD_dl_establish_T dl_sync_info; /* DL DPCH establishment criterion */
+
+ kal_bool non_sync_ind; /* [R6] FALSE: sync procedure shall be performed. TRUE: Sync procedure shall not be performed
+ for R5 and previous version, this value should be FALSE.
+ This field can be set to true only when setup_type is FDD_DCH_TMHHO */
+ kal_bool post_verification; /* [R6] TRUE: Post verification period shall be used . FALSE: Post verification period shall not be used.
+ for R5 and previous version, this value should be FALSE */
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rl */
+
+ kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event */
+#ifdef __UMTS_R8__
+ kal_bool edch_info_included; /* True means that IE "E-DCH info" is include in the reconfiguration message in the transition
+ * from FACH state to DCH state. UL1 uses this and following flags and other condition to determine
+ * if it is needed to perform Sync A procedure. Please see UL1 SAP in details. */
+ kal_bool fach_to_dch_cell_change; /* the PSC of RLs included in active set does not include the PSC of the current cell in CELL_FACH. */
+#endif /* __UMTS_R8__ */
+ FDD_IS_CS_PS is_cs_ps_call; /* for TAS feature. To check if DCH channel is for CS call */
+ kal_bool is_cs_call_only; /* for lo_rx. To check if DCH channel is only CS call */
+ kal_bool is_CSFB; /* to specify this DCH setup is for CSFB redirection */
+ kal_bool is_ecall_or_callback; /* To use eCall Information so that UL1 can disable features like LoRX, ARX */
+ kal_bool is_vc_resume; /* To decide DCH setup type after Virtual connected resume */
+} fdd_cphy_dch_setup_req_struct;
+
+typedef struct _fdd_cphy_dch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ FDD_dch_modify_msg_type_E modify_type; /* MODIFY, ASU, or Loop back mode 2 */
+
+ kal_uint8 tid; /* Transaction id */
+
+ kal_bool ul_mod_ind; /* Indicate whether UL modify indication should be sent to MAC */
+ kal_bool dl_mod_ind; /* Indicate whether DL modify indication should be sent to MAC */
+
+ kal_uint8 dl_crc_ind; /* For those TrCHs whose CRC data should be sent to MAC,
+ their corresponding bit will be set to 1.
+ The MSB represents the lowest numbered TrCH ID.
+ */
+
+ kal_uint16 modify_field; /* Bit field to represent for the parameters that should be modified
+ Bit 0 : DL TrCH parameter
+ Bit 1 : DL TFCS parameter
+ Bit 2 : UL TrCH parameter
+ Bit 3 : UL TFCS parameter
+ Bit 4 : DL common RL parameter
+ Bit 5 : DL each RL parameter
+ Bit 6 : UL RL parameter
+ Bit 7 : Physical parameters such as UL/DL freq and max TX power
+ Bit 8 : DL sync info which means timer and constant updating
+ */
+ /* Bit 3 */
+ kal_uint16 ul_tfc_num; /* # of TFC for UL DPCH */
+ FDD_ul_dpch_tfc_T ul_tfcs[FDD_MAX_UL_TFC]; /* UL TFCS */
+ /* Bit 2 */
+ kal_uint8 ul_trch_num; /* # of UL TrCH */
+ FDD_ul_dch_trch_T ul_trch_list[FDD_MAX_UL_TRCH]; /* UL DPCH TrCH Info */
+ /* Bit 1 */
+ kal_uint16 dl_tfc_num; /* # of TFC for DL DPCH */
+ FDD_dl_tfc_T dl_tfcs[FDD_MAX_DL_TFC]; /* DL TFCS */
+ /* Bit 0 */
+ kal_uint8 dl_trch_num; /* # of DL TrCH */
+ FDD_dl_dch_trch_T dl_trch_list[FDD_MAX_DL_TRCH]; /* DL DPCH TrCH Info */
+ /* Bit 4 */
+ FDD_dl_dpch_rla_T dl_dpch_rla; /* DL Info & DL DPCH Info common for all RLs */
+
+ kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
+ FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
+
+ /* Bit 6 */
+ FDD_ul_dpch_info_T ul_dpch_info;
+ /* Bit 7 */
+ /*remove these fields according to frequency info handler discussion*/
+// kal_uint16 ul_freq; /* UL UARFCN */
+// kal_uint16 dl_freq; /* DL UARFCN */
+ kal_int8 max_tx_power; /* Max allowed TX power. -50 ~ 33 dBm */
+ kal_int8 umts_power_class; /* UE capability*/
+ /* Bit 5 or ASU */ /* For Bit 5 modification, only rl_num_add and dl_dpch_rl_add are used */
+ kal_uint8 rl_num_delete; /* # of RL to be removed. 1 ~ 8*/
+ kal_uint16 dl_dpch_rl_delete[FDD_MAX_RL]; /* RL to be removed (PSC) */
+ kal_uint8 rl_num_add; /* # of RL to be added. 1 ~ 8 */
+ FDD_dl_dpch_rl_T dl_dpch_rl_add[FDD_MAX_RL]; /* DL Info & DL DPCH Info. for each RL */
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rl */
+
+ kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event */
+
+ /* Bit 8 for dl sync info updating */
+ FDD_dl_establish_T dl_sync_info; /* DL DPCH establishment criterion */
+ FDD_IS_CS_PS is_cs_ps_call; /* for TAS feature. To check if DCH channel is for CS call */
+ kal_bool is_cs_call_only; /* for lo_rx. To check if DCH channel is only CS call */
+ kal_bool is_ecall_or_callback; /* To use eCall Information so that UL1 can disable features like LoRX, ARX */
+} fdd_cphy_dch_modify_req_struct;
+
+typedef struct _fdd_cphy_dch_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+ kal_bool isStopLoopTestM2First; /* LCL needs to stop Loop Test explicitly before releasing DCH in abnormal case. */
+
+ kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
+ FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
+
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rl */
+
+ kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event */
+#ifdef __UMTS_R7__
+ FDD_dpch_release_type_E release_type; /* [R7] for whether UL1 need to record the HSS-SCCH oreder */
+#endif /* __UMTS_R7__ */
+
+} fdd_cphy_dch_release_req_struct;
+
+typedef struct _fdd_cphy_tgps_delete_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
+ FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
+
+} fdd_cphy_tgps_delete_req_struct;
+
+/* RRCE notifies UL1 if UL1 should resume sending cphy_tgps_overlap_ind*/
+typedef struct _fdd_cphy_tgps_overlap_resume_reporting_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tgpsi; /* TGPSI of TGPS beging removed. 1 ~ 6 */
+} fdd_cphy_tgps_overlap_resume_reporting_req_struct;
+
+
+typedef struct _fdd_cphy_frequency_scan_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 max_num_cell; /* maximum # of cells reported in 1 freq scan
+ If L1 found and report max_num_cell in 1 freq,
+ it should halt the freq scan
+ */
+ kal_int16 timeout; /* The max time spent to do cell search on 1 freq. (ms)
+ If L1 has spent so much time to do cell search on 1 freq,
+ it will send an ind to RRC and halt the freq scan procedure.
+ */
+
+ kal_uint8 num_freq_range; /* # of range list */
+ kal_uint16 uarfcn_begin[FDD_MAX_FREQ_RANGE]; /* Begin of DL uARFCN for range cell search */
+ kal_uint16 uarfcn_end[FDD_MAX_FREQ_RANGE]; /* End of DL uARFCN for range cell search */
+
+ kal_uint8 num_freq_list; /* # of freq for preferred freq list */
+ kal_uint16 uarfcn_list[FDD_MAX_FREQ_LIST]; /* List of UARFCN */
+
+ kal_uint8 num_psc; /* # of preferred cells */
+ FDD_preferred_cell_list_T preferred_cell_list[FDD_MAX_PREFERRED_PSC]; /* Preferred cell list */
+
+ kal_bool full_band_search; /* Perform full band scan; igonoring other parameters. */
+ kal_bool freq_correct; /* If 3G L1 need to do frequency correction */
+ kal_bool resume; /* TRUE: UL1 should resume previous freq scan, UL1 didn't care the other fields in this msg
+ FALSE: UL1 should start a new freq scan according to this msg */
+ /*Flag to indicate Quick Search Scan enabled or not*/
+ kal_bool quick_search;
+ /*Add for improving full band FS efficiency -- by excluding some UARFCN or some frequency range*/
+ FDD_full_band_option_E full_band_option; /*To indicate if "[filtered frequency list]/[frequency range]" shall be refered for full band search"*/
+ kal_uint8 working_UMTS_FDD_band[4]; /* Bitmask for frequency bands necessary to be scanned for this request */
+ kal_uint8 prefer_freq_list_cnt; /* # of preferred freq list */
+ kal_uint16 prefer_uarfcn_list[FDD_MAX_FREQ_LIST]; /* List of prefered freq */
+ kal_bool is_plmn_list; /* the prefered freq list is PLMN list or PLMN search */
+#ifdef __UMTS_R8__
+ kal_bool is_csg_search; /* [Rel8][CSG search]: to notify that current fs is for csg */
+#endif
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+#if !defined(__XL1SIM__)
+ freq_scan_type_enum freq_scan_type;
+#else
+ kal_uint16 priority_index;
+#endif
+
+ kal_uint8 priority_level; /* This field is only used for Gemini 2.0. to indicate the gap pattern used for this freq scan in Virtual mode.
+ The higher the priority, the smaller the priority level number. The highest priority is 2, which means this field can't be smaller than 2. */
+#endif /* __GEMINI__ && __UMTS_RAT__ */
+
+ kal_bool is_auto_gap_support; /* [MM] this freq scan req is for rptCGI */
+ kal_bool is_CSFB_search; /* [MM] to notify L1 the frequency scan is specified for CSFB */
+
+} fdd_cphy_frequency_scan_req_struct;
+
+typedef struct _fdd_cphy_frequency_scan_continue_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool continue_cell; /* True if MEME want L1 to do continue cell search on current frequency
+ instead of jumping to next specified frequency. */
+ kal_uint16 ecs_freq; /* exhaustive cell search frequency */
+ kal_bool apply_l1_filter;
+ kal_uint8 num_exclude_frequency_list;
+ kal_uint16 exclude_frequency_list[FDD_MAX_FREQ_EXCLUDE];
+} fdd_cphy_frequency_scan_continue_req_struct;
+
+typedef struct _fdd_cphy_frequency_scan_suspend_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool is_compensate_meas_cell_required; /* True if the suspend_req is triggered by RSVAU itself, UL1 may help to send a measurement_cell_ind */
+} fdd_cphy_frequency_scan_suspend_req_struct;
+
+/* This interface should not be used in MT6268 */
+typedef struct _fdd_cphy_frequency_scan_stop_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_stop_req_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_START_REQ (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_start_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 num_freq_list; /* # of freq for scan list of RSSI sniffer */
+ kal_uint16 uarfcn_list[FDD_MAX_RSSI_SNIFFER_SCAN_LIST]; /* List of UARFCN */
+
+} fdd_cphy_rssi_sniffer_start_req_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_STOP_REQ (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_stop_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rssi_sniffer_stop_req_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_PERIOD_CHANGE_REQ*/
+typedef struct _fdd_cphy_rssi_sniffer_period_change_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 periodicity_time; /*Range: [10,60], default: 30 // If the setting value is greater than the max value that xL1 can support, use the max supported value as setting*/
+
+} fdd_cphy_rssi_sniffer_period_change_req_struct;
+
+typedef struct _fdd_cphy_measurement_config_tgps_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 rx_cfn; /* message rx_cfn */
+ FDD_tgps_status_info_T tgps_status_info; /* Used to enable/disable particular TGPSs */
+
+ kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
+ FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
+} fdd_cphy_measurement_config_tgps_req_struct;
+
+typedef struct _fdd_cphy_measurement_config_fmo_req_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_fach_mo_info_T fach_mo_info; /* FACH MO param */
+} fdd_cphy_measurement_config_fmo_req_struct;
+
+typedef struct _fdd_cphy_auto_gap_on_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_auto_gap_on_req_struct;
+
+typedef struct _fdd_cphy_auto_gap_on_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_auto_gap_on_cnf_struct;
+
+typedef struct _fdd_cphy_auto_gap_off_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_auto_gap_off_req_struct;
+
+typedef struct _fdd_cphy_auto_gap_off_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_auto_gap_off_cnf_struct;
+
+typedef struct _fdd_cphy_measurement_config_cell_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; /* Transaction ID to sync between request and indication */
+ kal_bool stop_flag; /* TRUE : just stop meas. UL1 will NOT clear all cell info list and meas param */
+ FDD_CPHY_MEASUREMENT_STOP_CAUSE_E stop_cause; /* check this value only when stop_flag=TRUE */
+
+ kal_bool meas_spec_valid; /* Indicate if meas_spec is valid */
+ FDD_meas_spec_T meas_spec; /* meas spec for CPICH cell meas */
+
+ kal_bool cell_info_list_valid; /* Indicate if cell_info_list[], uarfcn[] and action[] are valid */
+ kal_uint16 uarfcn[FDD_MAX_UMTS_FREQ]; /* List of reference DL UARFCN */
+ kal_uint8 num_cell; /* # of cells in cell_info_list[] */
+ FDD_cell_info_list_T cell_info_list[FDD_MAX_NUM_MEASURED_CELL]; /* List of cells to be measured. */
+ FDD_meas_act_E action[FDD_MAX_UMTS_FREQ]; /* Action that should be applied to cell lsits.
+ FDD_MEAS_UPDATE : Add/Repleace cell list of a new specified freq (Both freq and cell list with tm/off are changed)
+ FDD_MEAS_MODIFY : (20080130: Removed)
+ FDD_MEAS_DELETE : Delete the cell list of a freq.
+ */
+
+ FDD_supplementary_meas_parameter_T supplementary_meas_parameter; /* These parameters are supplementary for UL1 measurement. These parameters may be set by CSCE or MEME */
+
+ kal_int8 idx_intra_freq; /* [Range]: 0 ~ 2. Indicate which frequency in the array uarfcn[FDD_MAX_UMTS_FREQ] is intra-frequency, -1 means invalid */
+
+ kal_bool intra_meas_period_valid; /* Only for MTK L1: configure Intra-freq. meas. period in DCH/FACH */
+ kal_uint8 intra_period_N; /* Num. of 40/50 ms */
+
+ kal_bool inter_meas_period_valid; /* Only for MTK L1: configure Inter-freq. meas. period in DCH/FACH */
+ kal_uint8 inter_period_N; /* Num. of GAPs or FMOs */
+
+ kal_bool meas_period_valid; /* Only for MA */
+ kal_uint16 period_unit; /* Only for MA */
+ kal_uint8 period_N; /* Only for MA */
+
+#ifdef __UMTS_R8__
+ kal_int16 T_higher_prio_search; /* [Rel8][Absolute Priority Search] -1: no need to watch priority_search_control in FDD_cell_info_list_T */
+ /* [Rel8][Absolute Priority Search] others: real value for the timer */
+
+ kal_bool detected_cell_info_list_valid; /* [Rel8][CSG search]: to judge if detected cell list is valid, the list is configured under IDLE state */
+ kal_uint8 num_detected_cell; /* [Rel8][CSG search]: number of detected cell, number <= 6 */
+ FDD_cell_info_list_T detected_cell_info_list[6]; /* [Rel8][CSG search]: information of the detected cell list */
+
+ kal_bool non_compressed_mode_inter_freq[FDD_MAX_UMTS_FREQ]; /* Indicates which inter-frequency in the array uarfcn[] should be measured without compressed mode */
+#endif /*__UMTS_R8__*/
+
+ kal_bool is_detected_cell_meas[FDD_MAX_UMTS_FREQ]; /* [MM] other-RATs can use this flag to trigger detected search */
+ kal_bool is_standby_meas_period_reset; /* [Rel8][MM] MEME notifies UL1 if short period meas cell list changes. */
+ /* If changes, measurement needs to be reconfigured (reset short period timer) */
+ kal_bool is_standby_prio_meas_period_reset; /* [Rel8][MM] MEME notifies UL1 if long period meas cell list changes. */
+ /* If changes, measurement needs to be reconfigured (reset long period timer) */
+
+ kal_bool prohibit_apply_n_layer; /* [Rel8][MM] Due to OOS, MEME notifies UL1 not to apply n_layer factor to accelerate meas frequency */
+
+ kal_int8 idx_first_meas_uarfcn_for_3g_standby; /* [Rel8][ABPCR] under standby mode, indicated uarfcn controlled by RR is first to be scheduling measured */
+#ifdef __UMTS_R9__
+ kal_int8 idx_sec_intra_freq; /* [R9]Indicates which frequency in the array uarfcn[] is secondary intra-freq. -1 measn invalid. [Range]0~3.*/
+#endif /*__UMTS_R9__*/
+} fdd_cphy_measurement_config_cell_req_struct;
+
+typedef struct _fdd_cphy_measurement_config_tx_power_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool periodic_ind; /* Indicate periodically or event triggered. TRUE means period */
+
+ kal_uint8 periodic_measurement_id;
+ kal_uint8 report_num; /* # of period report to be sent. 0 ~ 64 */
+ kal_uint16 period; /* Report period. 25 ~ 6400 frames */
+
+ kal_uint8 event_num; /* # of events in event[] */
+ FDD_meas_event_T event[FDD_MAX_MEAS_EVENT]; /* List of TX power meas event */
+
+ kal_uint8 filter; /* L3 filtering coefficient. 0 ~ 19 */
+
+} fdd_cphy_measurement_config_tx_power_req_struct;
+
+typedef struct _fdd_cphy_measurement_config_tx_power_stop_req_struct
+{
+ LOCAL_PARA_HDR
+
+} fdd_cphy_measurement_config_tx_power_stop_req_struct;
+
+
+
+typedef struct _fdd_cphy_treselection_start_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint32 treselection_value; /* One shot cell measurement will be triggered after T_reselection.
+ treselection_value can not be 0. uint = ms */
+ kal_uint8 freq_num; /* Indicate the number of freq that need to perform CM after T_reselection.
+ range: 1~FDD_MAX_UMTS_FREQ */
+ kal_uint16 freq[FDD_MAX_UMTS_FREQ]; /* Indicate the frequency that need to perfrom CM. */
+} fdd_cphy_treselection_start_req_struct;
+
+typedef struct _fdd_cphy_tx_power_result_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_tx_power_result_req_struct;
+
+typedef struct _fdd_cphy_specific_cell_search_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 freq; /* UARFCN of the specific cell */
+ kal_uint16 psc; /* Primary scrambling code of the specific cell */
+ kal_bool sttd; /* True if STTD is used in the designated cell. */
+ kal_bool sttd_valid; /* True if sttd is useful to UL1 */
+ kal_bool freq_correction; /* True if frequency correction is required */
+
+} fdd_cphy_specific_cell_search_req_struct;
+
+typedef struct _fdd_cphy_specific_cell_search_stop_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_specific_cell_search_stop_req_struct;
+
+typedef struct _fdd_cphy_reset_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_reset_req_struct;
+
+typedef struct _fdd_cphy_rf_on_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 working_UMTS_FDD_band[4];
+} fdd_cphy_rf_on_req_struct;
+
+typedef struct _fdd_cphy_rf_off_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rf_off_req_struct;
+
+typedef struct _fdd_cphy_set_active_rat_req_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_mode_type_E mode; /* Curernt mode setting (Single, Dual) */
+ FDD_rat_type_E rat; /* Current active RAT setting (Flight, UMTS, GSM) */
+ erac_rat_enum full_rat_info; /* Full RAT info */
+} fdd_cphy_set_active_rat_req_struct;
+
+/* 20080131: By MEME's request, define new I/F for event 6E. */
+typedef struct _fdd_cphy_measurement_config_rssi_event_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool enable; /* Indicate if we need to monitor the 6E RSSI event. TRUE means to be activated */
+ kal_uint16 delay; /* Time to Trigger. 0 ~ 500 frames */
+} fdd_cphy_measurement_config_rssi_event_req_struct;
+
+/*-------- Message(Primitive) related definition ----------------------*/
+
+typedef struct _FDD_msg_buf_T /* Buffer of message container */
+{
+ kal_uint8 channel_id; /* Channel ID */
+ msg_type msg_id; /* Message ID */
+ kal_uint16 buff_size; /* Buffer size */
+ local_para_struct *buffer; /* Channel configuration message buffer */
+} FDD_msg_buf_T;
+
+
+typedef struct _fdd_cphy_msg_container_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 at_ref; /* Reference channge of activation time.
+ 0 : Ref channel is the released channel.
+ There should be ch to be released
+ 1 : Ref channel is the setup channel.
+ There should be ch to be setup.
+ */
+ kal_int16 rx_cfn; /* Indicate peer message receive cfn. Ex: tti = 4, receive frame number : 0,1,2,3. rx_cfn = 3 (set by ul1)
+ [Range]: -1 ~ 255.
+ -1 : Means upper layer internal control
+ */
+#ifdef __UMTS_R6__
+ kal_bool delay_restriction; /* From R6 : TS25.331 8.6.3.1 */
+#endif
+ FDD_meas_control_E meas_control; /* Indicate whether UL1 need to not to resume meas. after apply corresponding buffer's config. */
+
+ kal_uint8 msg_num; /* # of included msg. 1 ~ 4 */
+ FDD_msg_buf_T msg_buffer[4]; /* List of msg buffer for included channel msg */
+
+ /* [R5R6] For HS-DSCH and E-DCH */
+ kal_uint8 h_msg_num; /* # of included H-msg. 0~2 */
+ FDD_msg_buf_T h_msg_buffer[2]; /* List of msg buffer for included channel msg */
+ kal_uint8 e_msg_num; /* # of included E-msg. 0~2 */
+ FDD_msg_buf_T e_msg_buffer[2]; /* List of msg buffer for included channel msg */
+#ifdef __UMTS_R7__
+ kal_uint8 cpc_msg_num; /* # of included CPC-msg. 0~1 */
+ FDD_msg_buf_T cpc_msg_buffer[1]; /* List of msg buffer for included CPC msg */
+#endif /* __UMTS_R7__ */
+// PLMN releated info
+ FDD_PLMN_LAC_PARAM_T plmn_info; /*PLMN, RAC and LAC info*/
+// RLC window size info
+ kal_uint8 rlc_info_msg_num; /* # of included rlc_info */
+ FDD_RLC_WINDOW_SIZE_INFO_T rlc_info_msg_buffer[4]; /* List of msg buffer for included rlc_info msg */
+} fdd_cphy_msg_container_req_struct;
+
+typedef struct _fdd_cphy_abort_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_abort_req_struct;
+
+typedef struct _fdd_cphy_TAS_notify_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_TAS_notify_ind_struct;
+/****************************************************************/
+/* __HSDPA_SUPPORT__ */
+typedef struct _fdd_cphy_hsdsch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+ FDD_dl_dpch_rla_T hsdsch_rla; /* Downlink information common for all RLs and downlink DPCH info. common for all RLs */
+ /* tgps_num in hsdsch_rla should be 0.*/
+ FDD_dl_dpch_rl_T hsdsch_rl; /* Downlink information for each RL (and downlink DPCH info. for each RL (for HS-DSCH serving cell*/
+ FDD_hs_scch_info_T hs_scch_info; /* HS-SCCH Info (25.331 10.3.6.36a) */
+ FDD_hs_meas_fb_info_T hs_meas_fb_info; /* Measurement Feedback Info (25.331 10.3.6.40a) */
+ FDD_hs_harq_info_T hs_harq_info; /* HARQ Info (25.331 10.3.5.7a) */
+ FDD_hs_ulpc_info_T hs_ulpc_info; /* Uplink power control info related to HSDPA */
+
+ kal_bool mac_hs_reset; /* TRUE indicates the MAC-hs entity needs to be reset */
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+ kal_uint16 h_rnti; /* H-RNTI assigned to UE */
+#ifdef __UMTS_R7__
+ FDD_rrc_state_E rrc_status; /* Indicate the RRC current status */
+ FDD_hspdsch_state_info_T hspdsch_state_info; /* HSPDSCH related parameter */
+ FDD_hs_scch_less_info_T hs_scch_less_info; /* HS-SCCH less Info (25.331 10.3.6.36ab) */
+ kal_bool h_rnti_valid; /* Indicate if h_rnti field is valid for UL1. H-RNTI shall be always valid for CELL_DCH, CELL_FACH, IDLE_FACH, and shall be always invalid for URA_PCH. */
+ kal_bool c_h_rnti_valid; /* [R7] Indicate if common H-RNTI is valid for UL1. This field shall be set to FALSE when rrc_status is equal to CELL_DCH. */
+ kal_uint16 c_h_rnti; /* [R7] Common H-RNTI assigned to UE. UL1 should not refer to this field if c_h_rnti_valid = KAL_FALSE. */
+ kal_bool b_h_rnti_valid; /* [R7] Indicate if bcch-specific H-RNTI is valid for UL1 */
+ kal_uint16 b_h_rnti; /* [R7] bcch-specific H-RNTI assigned to UE. UL1 should not refer to this field if b_h_rnti_valid = KAL_FALSE. */
+#ifdef __UMTS_R8__
+ kal_bool cqi_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
+ kal_bool ack_nack_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
+ FDD_hs_cell_fach_drx_T hs_cell_fach_drx; /* HS CELL_FACH DRX information. This field is only valid when rrc_status = CELL_FACH. */
+ FDD_dc_hsdpa_info_T dc_hsdpa_info; /* DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH. */
+ FDD_dl_pc_info_T dl_pc_common_edch; /* dl power control info. This field in only valid in EFACH state with common E-DCH transmission */
+#ifdef __UMTS_R10__
+ FDD_dc_hsdpa_info_T addi_dc_hsdpa_info[FDD_MAX_ADDI_DC_HSDPA]; /* Additional DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH.
+ FDD_MAX_ADDI_DC_HSDPA = 2. */
+#endif /* __UMTS_R10__ */
+#endif /* __UMTS_R8__ */
+#endif /* __UMTS_R7__ */
+} fdd_cphy_hsdsch_setup_req_struct;
+
+typedef struct _fdd_cphy_hsdsch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+#ifdef __UMTS_R7__
+ kal_uint16 modify_field; /* Bit field to represent for the parameters that should be modified
+ Bit 0 : dedicated H-RNTI or common H-RNTI
+ Bit 1 : hsdsch_rla
+ Bit 2 : hsdsch_rl
+ Bit 3 : HS-SCCH Info
+ Bit 4 : Measurement Feedback Info
+ Bit 5 : HARQ Info
+ Bit 6 : Uplink power control info related to HSDPA
+ Bit 7 : h_rnti_valid or hspdsch_state_info
+ Bit 8 : HS-SCCH less Info
+ Bit 9 : [R8] FDD_dc_hsdpa_info_T
+ Bit10 : [R8] FDD_hs_cell_fach_drx_T
+ Bit11 : [R10] addi_dc_hsdpa_info[0]
+ */
+#else /* __UMTS_R7__ */
+ kal_uint8 modify_field; /* Bit field to represent for the parameters that should be modified
+ Bit 0 : H-RNTI
+ Bit 1 : hsdsch_rla
+ Bit 2 : hsdsch_rl
+ Bit 3 : HS-SCCH Info
+ Bit 4 : Measurement Feedback Info
+ Bit 5 : HARQ Info
+ Bit 6 : Uplink power control info related to HSDPA
+ */
+#endif /* !__UMTS_R7__ */
+ FDD_dl_dpch_rla_T hsdsch_rla; /* Downlink information common for all RLs and downlink DPCH info. common for all RLs */
+ /* tgps_num in hsdsch_rla should be 0.*/
+ FDD_dl_dpch_rl_T hsdsch_rl; /* Downlink information for each RL (and downlink DPCH info. for each RL (for HS-DSCH serving cell*/
+ FDD_hs_scch_info_T hs_scch_info; /* HS-SCCH Info (25.331 10.3.6.36a) */
+ FDD_hs_meas_fb_info_T hs_meas_fb_info; /* Measurement Feedback Info (25.331 10.3.6.40a) */
+ FDD_hs_harq_info_T hs_harq_info; /* HARQ Info (25.331 10.3.5.7a) */
+ FDD_hs_ulpc_info_T hs_ulpc_info; /* Uplink power control info related to HSDPA */
+ kal_bool mac_hs_reset; /* TRUE indicates the MAC-hs entity needs to be reset */
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+ kal_uint16 h_rnti; /* H-RNTI assigned to UE */
+#ifdef __UMTS_R7__
+ FDD_rrc_state_E rrc_status; /* Indicate the RRC current status */
+ FDD_hspdsch_state_info_T hspdsch_state_info; /* HSPDSCH related parameter */
+ FDD_hs_scch_less_info_T hs_scch_less_info; /* HS-SCCH less Info (25.331 10.3.6.36ab) */
+ kal_bool h_rnti_valid; /* Indicate if h_rnti field is valid for UL1. H-RNTI shall be always valid for CELL_DCH, CELL_FACH, IDLE_FACH, and shall be always invalid for URA_PCH. */
+ kal_bool c_h_rnti_valid; /* [R7] Indicate if common H-RNTI is valid for UL1. This field shall be set to FALSE when rrc_status is equal to CELL_DCH. */
+ kal_uint16 c_h_rnti; /* [R7] Common H-RNTI assigned to UE. UL1 should not refer to this field if c_h_rnti_valid = KAL_FALSE. */
+ kal_bool b_h_rnti_valid; /* [R7] Indicate if bcch-specific H-RNTI is valid for UL1 */
+ kal_uint16 b_h_rnti; /* [R7] bcch-specific H-RNTI assigned to UE. UL1 should not refer to this field if b_h_rnti_valid = KAL_FALSE. */
+#ifdef __UMTS_R8__
+ kal_bool cqi_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
+ kal_bool ack_nack_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
+ FDD_hs_cell_fach_drx_T hs_cell_fach_drx; /* HS CELL_FACH DRX information. This field is only valid when rrc_status = CELL_FACH. */
+ FDD_dc_hsdpa_info_T dc_hsdpa_info; /* DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH. */
+#ifdef __UMTS_R10__
+ FDD_dc_hsdpa_info_T addi_dc_hsdpa_info[FDD_MAX_ADDI_DC_HSDPA]; /* Additional DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH.
+ FDD_MAX_ADDI_DC_HSDPA = 2. */
+#endif /* __UMTS_R10__ */
+#endif /* __UMTS_R8__ */
+#endif /* __UMTS_R7__ */
+} fdd_cphy_hsdsch_modify_req_struct;
+
+typedef struct _fdd_cphy_hsdsch_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+ kal_bool mac_hs_reset; /* TRUE indicates the MAC-hs entity needs to be reset */
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+} fdd_cphy_hsdsch_release_req_struct;
+
+#ifdef __UMTS_R7__
+typedef struct _FDD_phy_mac_ehs_reset_req_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_mac_ehs_reset_cause_E cause; /* Indicate the cause about the reason of UMAC reset */
+} fdd_phy_mac_ehs_reset_req_struct;
+#endif /* __UMTS_R7__ */
+
+#ifdef __UMTS_R7__
+typedef struct _fdd_cphy_cpc_config_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ FDD_hs_dtx_drx_info_T hs_dtx_drx_info; /* DTX/DRX information */
+} fdd_cphy_cpc_config_req_struct;
+
+typedef struct _fdd_cphy_d_hrnti_detected_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_d_hrnti_detected_ind_struct;
+
+#ifdef __UMTS_R8__
+typedef struct _fdd_cphy_start_monitor_order_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 h_rnti; /* h_rnti to decode target cell HS-SCCH */
+ kal_uint16 psc; /* psc to receive target cell HS-SCCH */
+ FDD_hs_scch_info_T hs_scch_info; /* ovsf_code_num field should always be 1 */
+ kal_int16 rpt_act_time; /* [Range]: (-1~255). (0-255) for CFN type, */
+} fdd_cphy_start_monitor_order_req_struct;
+
+typedef struct _fdd_cphy_start_monitor_order_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_start_monitor_order_cnf_struct;
+
+typedef struct _fdd_cphy_stop_monitor_order_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_stop_monitor_order_req_struct;
+
+typedef struct _fdd_cphy_stop_monitor_order_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_stop_monitor_order_cnf_struct;
+
+typedef struct _fdd_cphy_monitor_order_received_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 psc; /* Range: {0..511} */
+ kal_int16 act_time; /* Range {-1..255}: -1 is T324, 0..255 is AT */
+ kal_uint16 rx_cfn;
+} fdd_cphy_monitor_order_received_ind_struct;
+#endif /* __UMTS_R8__ */
+
+#endif /* __UMTS_R7__ */
+
+typedef struct _fdd_cphy_rlc_info_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 distance[FDD_MAX_HS_RB_NUM]; /* The distance between VR_H and VR_R (VR_H - VR_R) */
+ kal_uint32 rx_window_size[FDD_MAX_HS_RB_NUM];
+ kal_uint32 RTT[FDD_MAX_HS_RB_NUM]; /* Round trip time */
+} fdd_cphy_rlc_info_req_struct;
+
+/****************************************************************/
+
+/****************************************************************/
+/* __HSUPA_SUPPORT__ */
+typedef struct _fdd_cphy_edch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+ kal_bool pri_e_rnti_valid; /* Indicate if pri_e_rnti field is valid */
+ kal_uint16 pri_e_rnti; /* Primary E-RNTI assigned to UE */
+ kal_bool sec_e_rnti_valid; /* Indicate if sec_e_rnti field is valid */
+ kal_uint16 sec_e_rnti; /* Secondary E-RNTI assigned to UE */
+
+ FDD_edch_tti_E edch_tti; /* E-DCH TTI 2ms or 10ms */
+
+ kal_uint16 edch_serv_psc; /* serving E-DCH cell */
+
+ FDD_eagch_info_T eagch_info; /* E-AGCH info*/
+
+ kal_uint8 ehich_info_num; /* Number of E-HICH info: 1~FDD_MAX_EDCH_RL */
+ FDD_ehich_info_T ehich_info[FDD_MAX_EDCH_RL]; /* E-HICH info */
+ kal_uint8 ergch_info_num; /* Number of E-RGCH info: 0~FDD_MAX_EDCH_RL */
+ FDD_ergch_info_T ergch_info[FDD_MAX_EDCH_RL]; /* E-RGCH info */
+
+ FDD_edpdch_info_T edpdch_info; /* E-DPDCH info */
+ FDD_edpcch_info_T edpcch_info; /* E-DPCCH info */
+
+ FDD_edch_harq_info_T edch_harq_info; /* HARQ info for E-DCH */
+
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+#ifdef __UMTS_R7__
+ kal_bool ul_16QAM_on; /* Uplink 16QAM enable/disable */
+#endif /* __UMTS_R7__ */
+#ifdef __UMTS_R8__
+ FDD_edch_transmission_type_E transmission_type; /* Specify that E-DCH is allocated in dedicated state or common state */
+ FDD_common_edch_info_T common_edch_info; /* [R8] This field is only valid when transmission_type is equal to FDD_EDCH_IN_COMMON_STATE */
+#ifdef __UMTS_R9__
+ FDD_dc_hsupa_info_T dc_hsupa_info; /* [R9] DC-HSUPA information. This field is only valid when rrc_status = CELL_DCH. */
+#endif /* __UMTS_R9__ */
+#endif /* __UMTS_R8__ */
+} fdd_cphy_edch_setup_req_struct;
+
+typedef struct _fdd_cphy_edch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+ kal_uint16 modify_field; /* Bit field to represent for the parameters that should be modified
+ Bit 0 : E-RNTI
+ Bit 1 : E-DCH TTI
+ Bit 2 : E-AGCH info
+ Bit 3 : E-HICH info
+ Bit 4 : E-RGCH info
+ Bit 5 : E-DPDCH info
+ Bit 6 : E-DPCCH info
+ Bit 7 : E-DCH serving cell
+ Bit 8 : E-DCH harq info
+ Bit 9 : ul_16QAM_on
+ Bit 10: [R8] FDD_common_edch_info_T
+ Bit 11: [R9] FDD_dc_hsupa_info_T
+ */
+
+ kal_bool pri_e_rnti_valid; /* Indicate if pri_e_rnti field is valid */
+ kal_uint16 pri_e_rnti; /* Primary E-RNTI assigned to UE */
+ kal_bool sec_e_rnti_valid; /* Indicate if sec_e_rnti field is valid */
+ kal_uint16 sec_e_rnti; /* Secondary E-RNTI assigned to UE */
+ FDD_edch_tti_E edch_tti; /* E-DCH TTI 2ms or 10ms */
+
+ kal_uint16 edch_serv_psc; /* serving E-DCH cell */
+
+ FDD_eagch_info_T eagch_info; /* E-AGCH info*/
+
+ kal_uint8 ehich_info_num; /* Number of E-HICH info: 1~FDD_MAX_EDCH_RL */
+ FDD_ehich_info_T ehich_info[FDD_MAX_EDCH_RL]; /* E-HICH info */
+ kal_uint8 ergch_info_num; /* Number of E-RGCH info: 0~FDD_MAX_EDCH_RL */
+ FDD_ergch_info_T ergch_info[FDD_MAX_EDCH_RL]; /* E-RGCH info */
+
+ FDD_edpdch_info_T edpdch_info; /* E-DPDCH info */
+ FDD_edpcch_info_T edpcch_info; /* E-DPCCH info */
+
+ FDD_edch_harq_info_T edch_harq_info; /* HARQ info for E-DCH */
+
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+#ifdef __UMTS_R7__
+ kal_bool ul_16QAM_on; /* Uplink 16QAM enable/disable */
+#endif /* __UMTS_R7__ */
+#ifdef __UMTS_R8__
+ FDD_edch_transmission_type_E transmission_type; /* Specify that E-DCH is allocated in dedicated state or common state */
+ FDD_common_edch_info_T common_edch_info; /* [R8] This field is only valid when transmission_type is equal to FDD_EDCH_IN_COMMON_STATE */
+#ifdef __UMTS_R9__
+ FDD_dc_hsupa_info_T dc_hsupa_info; /* [R9] DC-HSUPA information. This field is only valid when rrc_status = CELL_DCH. */
+#endif /* __UMTS_R9__ */
+#endif /* __UMTS_R8__ */
+} fdd_cphy_edch_modify_req_struct;
+
+typedef struct _fdd_cphy_edch_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+} fdd_cphy_edch_release_req_struct;
+/****************************************************************/
+
+/****************************************************************/
+/* GEMINI 2.0 */
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+typedef struct _fdd_cphy_channel_priority_adjustment_req_struct
+{
+ LOCAL_PARA_HDR
+#ifdef __MODIFY_CTCH_RECEPTION_PRIO__
+ FDD_rrce_gemini_priority_adjust_E channel_priority;
+#else
+ kal_bool channel_priority_high; /* TRUE: UL1 channel priority is set to high. The priority of the timer related DCH/FACH will has the highest priority.
+ FALSE: UL1 channel priority is set to normal. The priority of the timer related DCH/FACH will has the lowest priority. */
+ FDD_rrce_gemini_priority_adjust_E adjust_channel;
+#endif
+} fdd_cphy_channel_priority_adjustment_req_struct;
+
+typedef struct _FDD_urr_ul1_switch_gemini_mode_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool is_virtual_mode; /* TRUE: UL1 will switch from Normal mode to Virtual mode.
+ FALSE: UL1 will switch from Virtual mode to Normal mode. */
+} fdd_urr_ul1_switch_gemini_mode_req_struct;
+
+
+typedef struct _fdd_cphy_peer_gemini_mode_notify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool is_peer_virtual_mode; /* TRUE: UL1 is informed that peer SIM enters virtual mode.
+ FALSE: UL1 is informed that peer SIM leaves virtual mode. */
+} fdd_cphy_peer_gemini_mode_notify_req_struct;
+
+
+
+typedef struct _FDD_rsvas_ul1_virtual_resume_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_rsvas_ul1_virtual_resume_req_struct;
+
+#endif /* __GEMINI__ && __UMTS_RAT__ */
+
+typedef struct _fdd_cphy_rb_lpbk_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rb_lpbk_req_struct;
+
+/****************************************************************/
+
+
+/*****************************************************************************
+ confirm & indication for cphy
+*****************************************************************************/
+typedef struct _fdd_cphy_rb_lpbk_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rb_lpbk_cnf_struct;
+
+typedef struct _fdd_cphy_bch_setup_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_setup_cnf_struct;
+
+typedef struct _fdd_cphy_bch_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate if BCH setup success.
+ For current L1, it always return true.
+ */
+} fdd_cphy_bch_setup_ind_struct;
+
+typedef struct _fdd_cphy_bch_modify_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_modify_cnf_struct;
+
+typedef struct _fdd_cphy_bch_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_modify_ind_struct;
+
+typedef struct _fdd_cphy_bch_release_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_release_cnf_struct;
+
+typedef struct _fdd_cphy_bch_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_release_ind_struct;
+
+typedef struct _fdd_cphy_sfn_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate if SFN ready success */
+ kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+
+ kal_uint16 dl_freq; /* UARFCN of the specific cell */
+ kal_uint16 psc; /* Primary scrambling code of the specific cell */
+
+ kal_bool dch_meas_valid; /* TRUE: DCH related parameters are valid */
+ kal_uint8 CFN; /* CFN of serving cell*/
+ kal_uint16 SFN; /* SFN of neighbor cell*/
+ kal_uint8 meas_off; /* SFN_CFN difference in frames*/
+ kal_uint16 meas_tm; /* SFN_CFN difference in chips*/
+
+ kal_bool common_meas_valid; /* TRUE: common channel related parameter is valid */
+ kal_uint32 meas_sfn_diff; /* SFN_SFN difference in chips*/
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ FDD_uas_gemini_conflict_cause_enum conflict_cause;
+ kal_uint16 peer_priority_index;
+#endif
+
+} fdd_cphy_sfn_ind_struct;
+
+
+/* MEME use this primitive as a trigger point to query UL1 tgps status */
+typedef struct _fdd_cphy_tgps_delete_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tgpsi_nbr; /* Number of TGPSI deleted */
+ kal_uint8 tgpsi[FDD_MAX_TGPS]; /* TGPSI deleted*/
+} fdd_cphy_tgps_delete_ind_struct;
+
+typedef struct _fdd_cphy_tgps_info_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ umts_fdd_dch_gap_struct dch_gap_pattern; /* The latest TGPS pattern indicator */
+} fdd_cphy_tgps_info_ind_struct;
+
+typedef struct _fdd_cphy_tgps_overlap_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tgpsi; /* TGPSI of TGPS beging removed. 1 ~ 6 */
+} fdd_cphy_tgps_overlap_ind_struct;
+
+typedef struct _fdd_cphy_gap_complete_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tgpsi; /* TGPSI of TGPS beging completed. 1 ~ 6 */
+} fdd_cphy_gap_complete_ind_struct;
+
+typedef struct _fdd_cphy_t312_expiry_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; /* Transaction id */
+
+} fdd_cphy_t312_expiry_ind_struct;
+
+typedef struct _fdd_cphy_dl_init_sync_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; /* Transaction id */
+ kal_int32 dpch_tm; /* For CFN-SFN TD */
+ kal_int16 dpch_off; /* For CFN-SFN TD */
+} fdd_cphy_dl_init_sync_ind_struct;
+
+typedef struct _phy_ul_not_activated_ind_struct
+{
+ LOCAL_PARA_HDR
+} phy_ul_not_activated_ind_struct;
+
+typedef struct _fdd_cphy_rl_failure_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rl_failure_ind_struct;
+
+/*Raymond 20070717 remove DELETE_TGPS CNF/IND interface*/
+typedef struct _fdd_cphy_frequency_scan_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_cnf_struct;
+
+typedef struct _fdd_cphy_frequency_scan_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_ind_struct;
+
+typedef struct _fdd_cphy_frequency_scan_continue_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_continue_cnf_struct;
+
+typedef struct _fdd_cphy_frequency_scan_suspend_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_suspend_cnf_struct;
+
+typedef struct _fdd_cphy_frequency_scan_suspend_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_suspend_ind_struct;
+
+/* This interface should not be used in MT6268 */
+typedef struct _fdd_cphy_frequency_scan_stop_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_stop_cnf_struct;
+
+/* This interface should not be used in MT6268 */
+typedef struct _fdd_cphy_frequency_scan_stop_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_stop_ind_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_START_CNF (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_start_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rssi_sniffer_start_cnf_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_STOP_CNF (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_stop_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+} fdd_cphy_rssi_sniffer_stop_cnf_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_STOP_IND (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_stop_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rssi_sniffer_stop_ind_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_SIGNAL_APPEAR_IND (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_signal_appear_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 num_freq_list; /* # of freq for scan list of RSSI sniffer */
+ kal_uint16 uarfcn_list[FDD_MAX_RSSI_SNIFFER_SCAN_LIST]; /* List of UARFCN */
+
+} fdd_cphy_rssi_sniffer_signal_appear_ind_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_EXECUTED_IND */
+typedef struct _fdd_cphy_rssi_sniffer_executed_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rssi_sniffer_executed_ind_struct;
+typedef struct _fdd_cphy_measurement_config_tgps_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_measurement_config_tgps_cnf_struct;
+
+typedef struct _fdd_cphy_measurement_config_tgps_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_measurement_config_tgps_ind_struct;
+
+typedef struct _fdd_cphy_measurement_config_fmo_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_measurement_config_fmo_cnf_struct;
+
+typedef struct _fdd_cphy_measurement_config_cell_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; /* Transaction ID to sync between req and ind */
+} fdd_cphy_measurement_config_cell_cnf_struct;
+
+typedef struct _fdd_cphy_measurement_cell_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; /* Transaction ID to sync between req and ind */
+ FDD_measured_type_E measured_type; /*IntraFrequency or InterFrequency*/
+ kal_uint16 uarfcn; /* DL UARFCN */
+ kal_int16 rssi; /* RSSI. Range: -400 ~ -100 means (-100 ~ -25)dBm 0.25 dB step */
+ kal_bool fs_halt; /* Indicate if freq scan halt. only for freq scan report */
+ kal_bool isSuspendByRSVAU; /* Indicate CSE the frequency is suspended. Only TRUE if UL1 receive suspend_req in FS_START and FS_CONTINUE. */
+ kal_uint8 num_cell; /* # of cell reported in this msg */
+ FDD_measured_cell_T measured_cell[FDD_MAX_NUM_MEAS_CELL]; /* list of measured cells */
+ kal_bool rl_status; /* Indicate tx available */
+#ifdef __UMTS_R8__
+ kal_bool isLongPeriodIn3GStandby; /* [Rel8][ABPCR] For RR, Indicate if it is prio search peiorid*/
+#endif
+ FDD_supplementary_report_info_T supplementary_report_info; /* to notify L3 further information */
+ kal_bool sttd_valid; /* Indicate sttd result is valid (reliable) or not */
+} fdd_cphy_measurement_cell_ind_struct;
+
+typedef struct _fdd_cphy_measurement_cell_sfn_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 dl_freq; /* UARFCN of the specific cell */
+ kal_uint16 psc; /* Primary scrambling code of the specific cell */
+ kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+ kal_uint16 SFN; /* SFN of neighbor cell*/
+ kal_bool sttd; /* STTD info of the specified cell */
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ FDD_uas_gemini_conflict_cause_enum conflict_cause;
+#endif
+} fdd_cphy_measurement_cell_sfn_ind_struct;
+
+typedef struct _fdd_cphy_measurement_rl_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rl_num; /* # of RL */
+ FDD_rl_meas_result_T rl_meas_result[FDD_MAX_RL]; /* RL measurement result for each RL */
+ kal_int16 tx_power; /* Averaged TX power meas result */
+} fdd_cphy_measurement_rl_ind_struct;
+
+typedef struct _fdd_cphy_measurement_config_tx_power_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_measurement_config_tx_power_cnf_struct;
+
+typedef struct _fdd_cphy_measurement_tx_power_periodic_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 periodic_measurement_id;
+ kal_int16 tx_power; /* Averaged TX power meas result */
+ kal_bool last_report; /* Indicate if this is the last report for period rpt */
+} fdd_cphy_measurement_tx_power_periodic_ind_struct;
+
+typedef struct _fdd_cphy_measurement_tx_power_event_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 tx_power; /* Averaged TX power meas result */
+ kal_uint8 event_id; /* Event ID being triggered */
+ kal_uint8 measurement_id; /* Measurement ID being triggered. */
+} fdd_cphy_measurement_tx_power_event_ind_struct;
+
+typedef struct _fdd_cphy_tx_power_result_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool valid; /* Indicate if below tx_power is vaide */
+ kal_int16 tx_power; /* Averaged TX power meas result */
+} fdd_cphy_tx_power_result_ind_struct;
+
+typedef struct _fdd_cphy_specific_cell_search_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate if search success */
+ FDD_measured_cell_T measured_cell; /* The found(1) cell */
+} fdd_cphy_specific_cell_search_ind_struct;
+
+typedef struct _fdd_cphy_specific_cell_search_stop_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_specific_cell_search_stop_ind_struct;
+
+typedef struct _fdd_cphy_reset_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate whether the L1 initialization sucess or fail */
+} fdd_cphy_reset_cnf_struct;
+
+
+typedef struct _fdd_cphy_rf_on_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rf_on_cnf_struct;
+
+typedef struct _fdd_cphy_rf_off_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rf_off_cnf_struct;
+
+typedef struct _fdd_cphy_set_active_rat_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_set_active_rat_cnf_struct;
+
+
+typedef struct _fdd_cphy_msg_container_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_msg_container_cnf_struct;
+
+typedef struct _fdd_cphy_msg_container_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success_flag; /* Indicate if configure success
+ For current L1, it always returns true.
+ */
+ kal_bool pending_tgps; /* Indicate if there is any pending TGPS.
+ Only sent when there is any channel to be released.
+ */
+ FDD_msg_container_error_E error_cause; /* Error cause of message container.
+ */
+} fdd_cphy_msg_container_ind_struct;
+
+typedef struct _fdd_cphy_abort_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate if abort request success
+ TRUE : L1 will back to the old channel configure.
+ FALSE : L1 will go forward to the new channel configure.
+ */
+} fdd_cphy_abort_cnf_struct;
+
+typedef struct _fdd_cphy_tx_status_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool is_tx_allow; /* the current TX status
+ TRUE : Currentlly, TX is available in UL1.
+ FALSE : Currentlly, TX is not available in UL1.
+ */
+} fdd_cphy_tx_status_ind_struct;
+
+/* 20080131: By MEME's request, define new I/F for event 6E. */
+typedef struct _fdd_cphy_rssi_exceed_range_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 tx_power; /* Averaged TX power meas result */
+} fdd_cphy_rssi_exceed_range_ind_struct;
+
+typedef struct _fdd_cphy_duplex_mode_change_req_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_duplex_mode_info_T duplex_mode_info;
+} fdd_cphy_duplex_mode_change_req_struct;
+
+typedef struct _fdd_cphy_duplex_mode_change_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool result;
+} fdd_cphy_duplex_mode_change_cnf_struct;
+
+/* Suspend and resume Smart Paging feature */
+
+typedef struct _fdd_cphy_smart_paging_reconfig_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool smartpaging_enabled;
+} fdd_cphy_smart_paging_reconfig_req_struct;
+
+/*****************************************************************************
+ request for phy
+*****************************************************************************/
+typedef struct _FDD_phy_rach_data_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 tfci; /* TFCI. 0 ~ 1023 */
+ FDD_ulTrchData TrchInfo; /* UL TrCH information */
+ kal_uint16 size_data; /* This parameter represents the number of bytes of the buffer. This number will be equal to the size of allocated buffer plus 4 bytes. */
+ kal_uint8 *data[FDD_MAX_UL_TB]; /* data for each TB. PS shoul allocate the buffer */
+} fdd_phy_rach_data_req_struct;
+
+typedef struct _FDD_phy_access_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool retry; /* Indicate if this is a retry request
+ TRUE : RACH TX failed in last acces procedure.
+ L1 will use the same RACH data an ASC in previous access procedure.
+ */
+ kal_uint8 asc; /* ASC. 0 ~ 7 */
+ kal_int16 ul_interference; /* UL interference in SIB7. -110 ~ 70dBm */
+#ifdef __UMTS_R8__
+ kal_bool is_CEDCH_CCCH; /* [R8] True: Common E-DCH transmission is for CCCH. FALSE for DTCH/DCCH */
+#endif /* __UMTS_R8__ */
+} fdd_phy_access_req_struct;
+
+
+/* confirm & indication for phy */
+typedef struct _FDD_phy_pch_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_pch_setup_ind_struct;
+
+typedef struct _FDD_phy_pch_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_pch_modify_ind_struct;
+
+typedef struct _FDD_phy_pch_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_pch_release_ind_struct;
+
+typedef struct _FDD_phy_fach_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_fach_setup_ind_struct;
+
+typedef struct _FDD_phy_fach_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_fach_modify_ind_struct;
+
+typedef struct _FDD_phy_fach_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_fach_release_ind_struct;
+
+typedef struct _FDD_phy_rach_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_rach_setup_ind_struct;
+
+typedef struct _FDD_phy_rach_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_rach_release_ind_struct;
+
+typedef struct _FDD_phy_dch_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 direction; /* Indicate UL or DL is being setup
+ 0 : DL DCH
+ 1 : UL DCH
+ 2 : FDPCH
+ */
+ kal_uint16 sfn; /* The LST value of the frame when DL DCH is setup.*/
+ kal_bool syncA_procedure_needed ; /* TRUE: Indicate syncA procedure is performed.*/
+} fdd_phy_dch_setup_ind_struct;
+
+typedef struct _FDD_phy_dch_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 direction; /* Indicate UL or DL is being setup
+ 0 : DL_DCH
+ 1 : UL_DCH
+ 2 : FDPCH
+ */
+} fdd_phy_dch_modify_ind_struct;
+
+typedef struct _FDD_phy_dch_release_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 direction; /* Indicate UL or DL is being setup
+ 0 : DL DCH
+ 1 : UL DCH
+ 2 : FDPCH
+ */
+ kal_uint16 sfn; /* The LST value of the frame when DL DCH is setup.*/
+} fdd_phy_dch_release_ind_struct;
+
+typedef struct _FDD_phy_config_abort_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate if abort request success
+ TRUE : L1 will back to old channel configure
+ FALSE : L1 will go forward to new channel configure
+ */
+} fdd_phy_config_abort_ind_struct;
+
+typedef struct _FDD_phy_dl_init_sync_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_dl_init_sync_ind_struct;
+
+typedef struct _FDD_phy_bch_data_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 *data; /* PS2 Excel request to add a "data" field in
+ fdd_phy_bch_data_ind_struct. This field is only for
+ protocol and not used by UL1 */
+ kal_bool no_path; /* True: L1 could not find the cell*/
+ kal_int32 tm; /* LST of the cell boundary. 0 ~ 38400*8-1 */
+ kal_int16 off; /* Frame # offset to LST. -1 ~ 4095. -1 means unknown */
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_uint8 crc_status; /* CRC result.
+ 0 : CRC error
+ 1 : CRC ok
+ 2 : no CRC */
+ kal_uint16 num_data; /* Length of the valid byte in data. 0 ~ FDD_MAX_DL_DATA */
+ /* Data is contained in peer buffer */
+ kal_bool measurement_valid;
+ kal_int16 rssi;
+ kal_int16 rscp;
+ kal_int16 ec_no;
+ kal_bool standby_no_gap; /* True: L1 has no enough gap time for SIB reception */
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ FDD_uas_gemini_conflict_cause_enum conflict_cause;
+ kal_uint16 peer_priority_index;
+#endif
+} fdd_phy_bch_data_ind_struct;
+
+typedef struct _FDD_phy_data_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_cctrch_type_E dl_cctrch; /* PCH, FACH or DCH CCTrCH */
+ kal_uint8 rx_fn; /* FN of the last frame in the TTI that was received */
+ kal_uint16 rx_sfn;
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_uint8 num_trch; /* # of trch */
+ FDD_dlTrchData TrchInfo[FDD_MAX_TRCH_NUM]; /* DL TrCH Info */
+ kal_uint32 crc; /* CRC result for each TB
+ 1 : CRC ok.
+ 0 : CRC error.
+ */
+ //kal_uint32 crc_bits[FDD_MAX_DL_TB]; /* CRC bits of each TB. (Used for Loop back mode) */
+ kal_uint16 num_data; /* Length of the valid byte in data. 0 ~ FDD_MAX_DL_DATA */
+ kal_uint8 *data; /* TB data pointer on share memory. This buffer is allocated by UL1, and freed by UMAC. */
+
+ kal_uint8 num_tb; /* num of TB. UMAC will put this value in the first byte of data allocated from ADM,
+ and the real data part starts at byte 4.*/
+
+ kal_uint32 raw_crc; /* Unmodified CRC for speech decoder */
+ kal_uint32 s_value[FDD_MAX_TRCH_NUM]; /* Viterbi decoder output S value for speech decoder */
+
+ /* UL1A provides debugging info. for VM in DCH dldata*/
+ kal_int16 tpc_SIR_lta; // For recording into speech VM
+ kal_int16 dpdch_SIR_lta; // For recording into speech VM
+ kal_int16 TFCI_max_corr; // For recording into speech VM
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ FDD_uas_gemini_conflict_cause_enum conflict_cause; /* This field is only used for Gemini. It indicates the channel conflict cause with peer channel.
+ It is only meaningful for PCH and CTCH. */
+ kal_uint8 rx_suspend; /* This field is only used for Gemini 2.0.It is a bitmap to indicate if some TrCH is conflicted with SIM2 gap.
+ The bit is set to ¡§1¡¨ only when the TrCH TTI ends in this frame and SIM2 gap exists in this TTI.
+ LSB bit is mapped to trchInfo[0]. */
+#endif /* __GEMINI__ && __UMTS_RAT__ */
+
+#ifdef __SMART_PAGING_3G_FDD__
+ kal_int8 pi_repeat_cycle;/* -1:invalid, -2:retransmission with CRC pass, 1~20:valid pi_repeat_cyle */
+#endif
+
+ kal_bool is_EBD_CRC_workaround; /*MT6290E1: indicate to MAC if additional CRC append in this data ind due to RXBRP workaround*/
+
+ /* serving cell information for speech debug. */
+ /* These values are valid only when DCH state and RL exists, otherwise, the value will be "0". */
+ kal_uint8 RSSI;
+ kal_uint8 RSCP;
+ kal_uint8 ECIO;
+ kal_uint8 HHO_SHO;
+
+} fdd_phy_data_ind_struct;
+
+typedef struct _fdd_phy_data_buffer_free_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 *data;
+} fdd_phy_data_buffer_free_ind_struct;
+
+typedef struct _FDD_phy_access_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_access_status_E access_status; /* The result of RACH access */
+} fdd_phy_access_ind_struct;
+
+
+/* __HSDPA_SUPPORT__ */
+typedef struct _FDD_phy_hsdsch_data_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 cfn; /* [Range]: 0-255 */
+ kal_uint8 subframe; /* indicate subf-number of this data_ind */
+ kal_uint8 mac_event; /* bit 0: MAC-hs setup, */
+ /* bit 1: MAC-hs release, */
+ /* bit 2: MAC-hs modify */
+ /* bit 3: MAC-(e)hs reset */
+ kal_uint8 cell_bitmap;
+ FDD_hsdsch_data_T hsdsch_data[FDD_MAX_SUPPORT_CELL];
+
+} fdd_phy_hsdsch_data_ind_struct;
+
+
+
+#ifdef __UMTS_R8__
+typedef struct _FDD_phy_cedch_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_cedch_setup_ind_struct;
+
+typedef struct _FDD_phy_cedch_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_cedch_modify_ind_struct;
+
+typedef struct _FDD_phy_cedch_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_cedch_release_ind_struct;
+
+typedef struct _FDD_phy_cedch_termination_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_cedch_termination_req_struct;
+
+typedef struct _FDD_phy_cedch_termination_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool stopped_by_ul1; /* CEDCH is terminated due to radio link failure */
+} fdd_phy_cedch_termination_ind_struct;
+#endif /* __UMTS_R8__ */
+
+/* U3G */
+typedef struct _FDD_ul1_l1sp_update_dch_info_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ /* SP3G_UpdateL1InFo */
+ /* called by L1A to update DCH on/off and TX in/off(DCH UL on/off) */
+ /* bitmap indicates DCH setup type, and value indicates the status */
+ /* bitmap = 0: DCH on/off (1: on, 0: off) */
+ /* bitmap = 1: DCH UL on/off (1: on, 0: off) */
+ /* bitmap = 2: indicate RLF status (1: indicate RLF, 0: reset RLF) */
+ kal_uint8 bitmap;
+ kal_uint8 value;
+} fdd_ul1_l1sp_update_dch_info_ind_struct;
+/* U3G */
+
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+
+typedef struct _FDD_rsvas_ul1_suspend_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_rsvas_ul1_suspend_req_struct;
+
+typedef struct _FDD_rsvas_ul1_suspend_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_rsvas_ul1_suspend_cnf_struct;
+
+typedef struct _FDD_rsvas_ul1_resume_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_rsvas_ul1_resume_req_struct;
+#endif
+
+#if defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__) || defined(__L1_GPS_REF_TIME_SUPPORT__)
+/* __GPS_FRAME_SYNC_SUPPORT__ */
+/* CSCE uses this primitive to inform UL1 that OOS occurs when AGPS feature turns on. */
+typedef struct _fdd_cphy_out_of_service_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_out_of_service_req_struct;
+#endif
+
+typedef struct _FDD_user_wakeup_3g_lock_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 user_sm_handle;
+} FDD_user_wakeup_3g_lock_struct;
+
+/* SEQUENCE OF MCC */
+typedef struct ul1_mcc
+{
+ kal_uint8 numElements;
+
+ kal_uint8 element[3];
+}
+ul1_mcc;
+
+/* SEQUENCE OF MNC */
+typedef struct ul1_mnc
+{
+ kal_uint8 numElements;
+
+ kal_uint8 element[3];
+}
+ul1_mnc;
+
+
+/* SEQUENCE PLMN-Identity */
+typedef struct ul1_plmn_identity
+{
+ ul1_mcc mcc; /* MANDATORY */
+ ul1_mnc mnc; /* MANDATORY */
+}
+ul1_plmn_identity;
+/*****************************************************************************
+* Functions exported to RRC
+*****************************************************************************/
+void UL1_Lcore_Compare_CFN_SFN( UL1_SIM_INDEX_E sim_idx, kal_int16 cfn, kal_int16 sfn, FDD_tgps_time_relationship_E *cfn_sfn_relation );
+void UL1D_PS_SessionStarted( kal_bool If_PS_SessionStarted );
+kal_bool UL1D_FDD_HSDPA_Phy_DualCarrier_Status( void *data );
+
+
+
+/*------------------- Function prototype -----------------------------*/
+/* L1 provides this function to other entities to get current CFN & SFN */
+/* CFN : -1 ~ 255. 0 ~ 255 if UE in DCH/FACH mode otherwise -1 */
+/* SFN : -1 ~ 4095. 0 ~ 4095 for the LST frame number. -1 for an invalid value. */
+void UL1_GetCurrentTime( UL1_SIM_INDEX_E sim_index, kal_int16 *cfn, kal_int16 *sfn );
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*****************************************************************************
+* Function: UL1_Compare_CFN_SFN
+*
+* Parameters: kal_int16 cfn ; cfn which RRCE wants to compare, range:0~255
+* kal_int16 sfn ; sfn which RRCE wants to compare, range:0~4095
+* FDD_tgps_time_relationship_E* cfn_sfn_relation ; FDD_TGPS_AFTER means that expanded CFN is after the specified sfn
+* ; FDD_TGPS_EQUAL means that expanded CFN is equal to the specified sfn
+* ; FDD_TGPS_BEFORE means that expanded CFN is equal to the specified sfn
+* Returns: void
+*
+* Description:
+* The function is to expand the specified CFN to the range 0~4095 and compare the expanded CFN to the specified SFN
+*****************************************************************************/
+void UL1_Compare_CFN_SFN( kal_int16 cfn, kal_int16 sfn, FDD_tgps_time_relationship_E *cfn_sfn_relation );
+
+
+/*****************************************************************************
+* Function: UL1_CEDCH_Check_Started
+*
+* Parameters: Non
+* Returns: If the return value is KAL_TRUE, UL1 has the common EDCH resource, otherwise it's KAL_FALSE.
+*
+* Description:
+* This is a callback function and provide to indicate the common edch status for upper layer.
+* The resolution is frame base because this function is provided by UL1C.
+*****************************************************************************/
+#ifdef __UMTS_R8__
+#define UL1_Lcore_CEDCH_Check_Started UL1_CEDCH_Check_Started
+kal_bool UL1_CEDCH_Check_Started( UL1_SIM_INDEX_E sim_index );
+#endif /* __UMTS_R8__ */
+
+/*****************************************************************************
+* Functions exported to MEME
+*****************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*****************************************************************************
+* Functions exported to UMAC
+*****************************************************************************/
+/*****************************************************************************
+* Function: UL1_FreePhyDataIndBuffer
+*
+* Parameters: kal_uint8* data : DL data buffer to be freed
+*
+* Returns: void
+*
+* Description:
+* The function is for UMAC to free the data buffer in PHY_DATA_IND
+*****************************************************************************/
+void UL1_FreePhyDataIndBuffer( kal_uint8 *data );
+
+
+/**********************************************************************************************************************/
+/*********************************** UL1 Interface maintained by UMAC (Begin) *************************************/
+/**********************************************************************************************************************/
+/*UMAC*/
+extern kal_bool FDD_ul_dpch_cctrch(
+ /*UMAC*/ kal_uint8 cfn,
+ /*UMAC*/ kal_bool availabe,
+ /*UMAC*/ kal_bool reconfig_status, /*For notifying DPCH modification*/
+ /*UMAC*/ kal_uint16 *tfci,
+ /*UMAC*/ kal_uint8 *num_trch,
+ /*UMAC*/ FDD_ulTrchData *TrchInfo,
+ /*UMAC*/ kal_uint16 *size_data,
+ /*UMAC*/ kal_uint8 **data );
+/*UMAC*/
+/*UMAC*/
+extern void FDD_ul_dpch_cctrch_task(
+ /*UMAC*/ kal_uint8 cfn,
+ /*UMAC*/ kal_bool availabe,
+ /*UMAC*/ kal_bool reconfig_status /*For notifying DPCH modification*/ );
+/*UMAC*/
+/*UMAC*/
+extern kal_bool FDD_ul_dpch_cctrch_HISR(
+ /*UMAC*/ kal_uint8 cfn,
+ /*UMAC*/ kal_bool availabe,
+ /*UMAC*/ kal_bool reconfig_status, /*For notifying DPCH modification*/
+ /*UMAC*/ kal_uint16 *tfci,
+ /*UMAC*/ kal_uint8 *num_trch,
+ /*UMAC*/ FDD_ulTrchData *TrchInfo,
+ /*UMAC*/ kal_uint16 *size_data,
+ /*UMAC*/ kal_uint8 **data );
+/*UMAC*/
+/*UMAC*/
+extern void FDD_ul_inform_MAC( kal_uint32 data );
+/*UMAC*/
+/*UMAC*/
+extern void FDD_ul_dpch_power( kal_uint8 cfn, kal_uint8 tfc_status[FDD_MAX_UL_TFC] );
+/*UMAC*/
+extern void FDD_mac_hs_get_variable_pdu_buffer( kal_uint8 **buffer_ptr, kal_uint32 num );
+#ifdef __HSDSCH_HARQ_OFF__
+/*UMAC*/extern void FDD_mac_hs_free_variable_pdu_buffer( kal_uint8 **buffer_ptr, kal_uint32 num ); // for HARQ off
+#endif
+/*UMAC*/extern void FDD_mac_hs_get_pdu_buffer( kal_uint8 **buffer_ptr );
+/*UMAC*/
+/*UMAC*/
+extern FDD_uldch_data_ind_T *FDD_UMAC_UL_DCH_Tick_LISR( UL1_SIM_INDEX_E sim_idx, FDD_uldch_data_req_T *uldch_data_req );
+/*UMAC*/
+extern FDD_etfc_eval_info_ind_T *FDD_umac_e_dch_evaluate_tx_process_LISR( UL1_SIM_INDEX_E sim_idx, FDD_etfc_eval_info_req_T *etfc_eval_input );
+/*UMAC*/
+extern kal_bool FDD_umac_e_dch_is_tx_permitted_LISR( UL1_SIM_INDEX_E sim_idx, kal_uint8 *supported_etfci_bitmap, FDD_edch_scell_E edch_cell, kal_bool *is_sched_data_included );
+/*UMAC*/
+extern FDD_edch_data_ind_T *FDD_umac_e_dch_prepare_data_LISR( UL1_SIM_INDEX_E sim_idx, FDD_edch_data_req_T *edch_data_input );
+/*UMAC*/
+extern kal_bool FDD_umac_e_dch_get_happy_bit_LISR( UL1_SIM_INDEX_E sim_idx, kal_bool happy[FDD_E_SCELL_TOTAL] );
+/*UMAC*/
+extern void FDD_umac_e_dch_post_tx_process_LISR( UL1_SIM_INDEX_E sim_idx );
+/*UMAC*/
+extern void FDD_umac_e_dch_update_ref_etpr_LISR( UL1_SIM_INDEX_E sim_idx, kal_bool tx_enable[FDD_E_SCELL_TOTAL], kal_uint32 ref_etpr_x225[FDD_E_SCELL_TOTAL] );
+/*UMAC*/
+extern void FDD_try_to_trigger_CSR_STATUS_IND_LISR( UL1_SIM_INDEX_E sim_idx, kal_uint8 cfn );
+/*UMAC*/
+extern kal_bool FDD_umac_e_dch_predict_tx_process_LISR( UL1_SIM_INDEX_E sim_idx, FDD_etfc_eval_lpr_info_req_T *info );
+/*UMAC*/
+extern void FDD_ul_inform_Edch_MAC( void *data );
+/*UMAC*/
+extern void FDD_send_CSR_STATUS_IND( kal_uint32 data );
+/*UMAC*/
+/*UMAC*/
+#define FDD_UMAC_UL_DCH_Tick(sim_idx,uldch_data_req) FDD_UMAC_UL_DCH_Tick_LISR(sim_idx,uldch_data_req)
+/*UMAC*/#define FDD_umac_e_dch_tick_1( sim_idx, etfc_eval_input ) FDD_umac_e_dch_evaluate_tx_process_LISR( sim_idx, etfc_eval_input )
+/*UMAC*/#define FDD_umac_e_dch_is_tx_permitted( sim_idx, supported_etfci_bitmap, edch_cell, is_sched_data_included ) FDD_umac_e_dch_is_tx_permitted_LISR( sim_idx, supported_etfci_bitmap, edch_cell, is_sched_data_included )
+/*UMAC*/#define FDD_umac_e_dch_tick_2( sim_idx, edch_data_input ) FDD_umac_e_dch_prepare_data_LISR( sim_idx, edch_data_input )
+/*UMAC*/#define FDD_umac_e_dch_get_happy_bit( sim_idx, happy ) FDD_umac_e_dch_get_happy_bit_LISR( sim_idx, happy )
+/*UMAC*/#define FDD_umac_e_dch_tick_3( sim_idx, tx_enable, ref_etpr_x225 ) FDD_umac_e_dch_post_tx_process_LISR( sim_idx )
+/*UMAC*/#define FDD_umac_e_dch_tick_4( sim_idx ) {} //FDD_umac_e_dch_tick_4_LISR(sim_idx)
+/*UMAC*/#define FDD_umac_e_dch_update_ref_etpr( sim_idx, tx_enable, ref_etpr_x225 ) FDD_umac_e_dch_update_ref_etpr_LISR( sim_idx, tx_enable, ref_etpr_x225 )
+/*UMAC*/#define FDD_umac_e_dch_tick_5( sim_idx, info ) FDD_umac_e_dch_predict_tx_process_LISR( sim_idx, info )
+/*UMAC*/
+/*UMAC*//*========== UMAC END TX STRUCT (BEGIN) ==========*/
+/*UMAC*/typedef struct _FDD_phy_end_dch_tx_ind_struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ /*UMAC*/
+} fdd_phy_end_dch_tx_ind_struct;
+/*UMAC*/
+/*UMAC*//* __HSUPA_SUPPORT__ */
+/*UMAC*/
+typedef struct _FDD_phy_end_edch_tx_ind_struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_uint8 subframe;
+ /*UMAC*/
+ kal_uint8 harq_id;
+ /*UMAC*/
+ kal_uint8 mode;
+ /*UMAC*/
+} fdd_phy_end_edch_tx_ind_struct;
+/*UMAC*//*========== UMAC END TX STRUCT (END) ==========*/
+/*UMAC*//*========== UMAC UT SIMULATE MESSAGE ==========*/
+/*UMAC*///#ifdef __MNT_UT_UMAC_ALONE_WITHOUT_L1__ /* UMAC UT */
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_bool availabe;
+ /*UMAC*/
+ kal_bool reconfig_status;
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_cctrch_task_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_uint8 ul_mac_event; /* bit 0: UL DCH setup, */
+ /*UMAC*/ /* bit 1: UL DCH release, */
+ /*UMAC*/ /* bit 2: UL DCH modify */
+ /*UMAC*/
+ kal_uint8 dpdch_num;
+ /*UMAC*/
+ kal_bool restartSRB; /* set true when PCP_Finish (not align max TTI) */
+ /*UMAC*/
+ kal_bool tx_enable; /* set true if TX data could be sent (min TTI) */
+ /*UMAC*/
+ kal_bool tx_suspend;
+ /*UMAC*/
+ kal_uint8 tfc_status[FDD_MAX_UL_TFC];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_cctrch_lisr_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_bool availabe;
+ /*UMAC*/
+ kal_bool reconfig_status;
+ /*UMAC*/ /* Use structure instead of pointer to simulate this */
+ /*UMAC*/
+ kal_uint16 tfci;
+ /*UMAC*/
+ kal_uint8 num_trch;
+ /*UMAC*/
+ FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint16 size_data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint8 *data[FDD_MAX_UL_TB];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_cctrch_hisr_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_uint8 num_trch;
+ /*UMAC*/
+ FDD_ulTrchData trchInfo[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint16 tfci;
+ /*UMAC*/
+ kal_uint16 num_data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint8 *data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ /*UMAC*/
+#ifdef UNIT_TEST
+ /*UMAC*/ void *addr;
+ /*UMAC*/
+#endif /* UNIT_TEST */
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_cctrch_lisr_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_bool availabe;
+ /*UMAC*/
+ kal_bool reconfig_status;
+ /*UMAC*/ /* Use structure instead of pointer to simulate this */
+ /*UMAC*/
+ kal_uint16 tfci;
+ /*UMAC*/
+ kal_uint8 num_trch;
+ /*UMAC*/
+ FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint16 size_data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint8 *data[FDD_MAX_UL_TB];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_cctrch_hisr_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_bool availabe;
+ /*UMAC*/
+ kal_bool reconfig_status;
+ /*UMAC*/ /* Use structure instead of pointer to simulate this */
+ /*UMAC*/
+ kal_uint16 tfci;
+ /*UMAC*/
+ kal_uint8 num_trch;
+ /*UMAC*/
+ FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint16 size_data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint8 *data[FDD_MAX_UL_TB];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_callback_cctrch_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_uint8 tfc_status[FDD_MAX_UL_TFC];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_callback_power_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct /* Old DCH Callback */
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_bool availabe;
+ /*UMAC*/
+ kal_bool reconfig_status; /*MA only, for notifying DPCH modification*/
+ /*UMAC*/ /* Use structure instead of pointer to simulate this */
+ /*UMAC*/
+ kal_uint16 tfci;
+ /*UMAC*/
+ kal_uint8 num_trch;
+ /*UMAC*/
+ FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint16 size_data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint8 *data[FDD_MAX_UL_TB];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_callback_cctrch_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ /*UMAC*/
+} fdd_phy_simulate_end_dch_tx_ind_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/ /* For MT6291 U3G */
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ FDD_etfc_eval_info_req_T etfc_eval_info_req;
+ /*UMAC*/
+ /*UMAC*/
+ kal_uint8 sf_of_etfci[8][128 / 2];
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_eval_tx_proc_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ FDD_etfc_eval_info_ind_T etfc_eval_info_ind;
+ /*UMAC*/
+ kal_uint8 active_process[FDD_E_SCELL_TOTAL]; /* easy to check the result after processing AG command */
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_eval_tx_proc_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ /* MAX_NUM_OF_ETFC = 128 */
+ /*UMAC*/ kal_uint8 supported_etfci_bitmap[128 / 4];
+ /*UMAC*/
+ /*UMAC*/ /* FDD_MAX_NTX1_10MS = (15-8+1), FDD_MAX_ETFC_NUM = 128 */
+ /*UMAC*/
+ FDD_edch_scell_E edch_cell;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_is_tx_permit_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_bool is_sched_data_included;
+ /*UMAC*/
+ kal_bool tx_enable;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_is_tx_permit_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ FDD_edch_data_req_T edch_data_req;
+ /*UMAC*/ /* FDD_MAX_ETFC_NUM = 128 */
+ /*UMAC*/
+ kal_uint8 supported_etfci_bitmap[128 / 4];
+ /*UMAC*/
+ kal_uint32 FRC_Curr_Time;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_prepare_data_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ FDD_edch_data_ind_T edch_data_ind;
+ /*UMAC*/
+ kal_uint8 SI_HLID; /* easy to check result of Highest Priority Logical Channel Identity */
+ /*UMAC*/
+ kal_uint32 SI_HLBS; /* easy to check result of Highest priority Logical channel Buffer Status (Bytes) */
+ /*UMAC*/
+ kal_uint8 NoOfCoproTBTriggered;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_prepare_data_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_get_happy_bit_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_bool happy[FDD_E_SCELL_TOTAL]; /* easy to check result of Highest priority Logical channel Buffer Status (Bytes) */
+ /*UMAC*/
+ kal_bool is_tebs_larger_than_0;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_get_happy_bit_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint32 FRC_Curr_Time;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_post_tx_proc_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 NoOfCoproTBTriggered;
+ /*UMAC*/
+ kal_uint8 NotifyRLCHarqBitmap[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_post_tx_proc_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+#ifdef __UMTS_R7__
+/*UMAC*/typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ FDD_etfc_eval_lpr_info_req_T etfc_eval_lpr_info_req;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_predict_tx_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_bool result;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_predict_tx_rsp_struct;
+#endif /* __UMTS_R7__*/
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_bool tx_enable[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+ kal_uint32 ReferenceEtpr[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_update_ref_etpr_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_update_ref_etpr_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ /* MAX_NUM_OF_ETFC = 128 */
+ /*UMAC*/ kal_uint8 supported_etfci_bitmap[128 / 4];
+ /*UMAC*/
+ /*UMAC*/ /* NUM_OF_NTX1_10MS = (15-8+1), MAX_NUM_OF_ETFC = 128 */
+ /*UMAC*/
+ kal_uint8 sf_of_etfci[8][128 / 2];
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_tx_param_setup_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+} fdd_phy_simulate_try_to_trigger_csr_status_ind_struct;
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ kal_uint8 ref_count;
+ /*UMAC*/
+ kal_uint16 msg_len;
+ /*UMAC*/
+ /*UMAC*/
+ kal_uint8 get_num;
+ /*UMAC*/
+} fdd_phy_simulate_umac_get_hs_buffer_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ kal_uint8 ref_count;
+ /*UMAC*/
+ kal_uint16 msg_len;
+ /*UMAC*/
+ /*UMAC*/
+ kal_uint8 free_num;
+ /*UMAC*/
+} fdd_phy_simulate_umac_free_hs_buffer_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint32 NoOfEdchCell;
+ /*UMAC*/
+} fdd_phy_simulate_umac_forced_to_send_edch_em_info_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+} fdd_phy_simulate_umac_forced_to_send_hsdsch_em_info_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_bool b_pch_Crc;
+ /*UMAC*/
+ kal_bool b_em_from_logger;
+ /*UMAC*/
+} fdd_phy_simulate_umac_setup_pch_em_info_struct;
+/*UMAC*///#endif /* __MNT_UT_UMAC_ALONE_WITHOUT_L1__ */
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint32 kpi;
+ /*UMAC*/
+} fdd_phy_simulate_umac_forced_to_send_mdmi_mac_em_info_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint32 kpi;
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/ kal_uint8 subframe;
+ /*UMAC*/ kal_uint8 harq_id;
+ /*UMAC*/ kal_uint8 dummy;
+ /*UMAC*/
+} fdd_phy_simulate_umac_forced_to_send_mdmi_upa_em_info_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+} fdd_phy_simulate_umac_forced_to_send_mdmi_mea_em_info_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*//*========== END UMAC UT SIMULATE MESSAGE ==========*/
+/*UMAC*/
+/*UMAC*//*========== UMAC DEBUG MESSAGE ==========*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+ /*UMAC*/ FDD_etfc_eval_info_req_T etfc_eval_info_req;
+ /*UMAC*/
+ FDD_etfc_eval_info_ind_T etfc_eval_info_ind;
+ /*UMAC*/
+ kal_uint8 ServingGrant;
+ /*UMAC*/
+ kal_bool old_isNewTransmission;
+ /*UMAC*/
+ kal_bool update_isNewTransmission;
+ /*UMAC*/
+ /*UMAC*/
+} FDD_umac_umac_edch_eval_tx_proc_ind_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+ /*UMAC*/ FDD_edch_data_ind_T edch_data_ind;
+ /*UMAC*/
+ kal_uint8 supported_etfci_bitmap[32];
+ /*UMAC*/
+} FDD_umac_umac_edch_prepare_data_ind_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+ /*UMAC*/ kal_bool tx_enable[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+ kal_uint8 old_ReferenceEtpr[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+ kal_uint8 update_ReferenceEtpr[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+ kal_uint32 ref_etpr_x225[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+ kal_uint32 update_ref_etpr_x225[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+} FDD_umac_umac_edch_post_tx_proc_ind_struct;
+/*UMAC*//*========== END UMAC DEBUG MESSAGE ==========*/
+/**********************************************************************************************************************/
+/*********************************** UL1 Interface maintained by UMAC (END) *************************************/
+/**********************************************************************************************************************/
+
+/*------------------- MSC Composer -----------------------------*/
+/* The following definition is used only for MSC composer. */
+typedef union _FDD_local_para_unpack_T
+{
+ fdd_cphy_pch_setup_req_struct cphy_pch_setup_req;
+ fdd_cphy_pch_modify_req_struct cphy_pch_modify_req;
+ fdd_cphy_pch_release_req_struct cphy_pch_release_req;
+ fdd_cphy_fach_setup_req_struct cphy_fach_setup_req;
+ fdd_cphy_fach_modify_req_struct cphy_fach_modify_req;
+ fdd_cphy_fach_release_req_struct cphy_fach_release_req;
+ fdd_cphy_dch_setup_req_struct cphy_dch_setup_req;
+ fdd_cphy_dch_modify_req_struct cphy_dch_modify_req;
+ fdd_cphy_dch_release_req_struct cphy_dch_release_req;
+ fdd_cphy_rach_setup_req_struct cphy_rach_setup_req;
+ fdd_cphy_rach_release_req_struct cphy_rach_release_req;
+ fdd_cphy_hsdsch_setup_req_struct cphy_hsdsch_setup_req;
+ fdd_cphy_hsdsch_modify_req_struct cphy_hsdsch_modify_req;
+ fdd_cphy_hsdsch_release_req_struct cphy_hsdsch_release_req;
+ fdd_cphy_edch_setup_req_struct cphy_edch_setup_req;
+ fdd_cphy_edch_modify_req_struct cphy_edch_modify_req;
+ fdd_cphy_edch_release_req_struct cphy_edch_release_req;
+#ifdef __UMTS_R7__
+ fdd_cphy_cpc_config_req_struct cphy_cpc_setup_req;
+#endif /* __UMTS_R7__ */
+} FDD_local_para_unpack_T;
+
+typedef struct _FDD_msg_buf_unpack_T /* Buffer of message container */
+{
+ kal_uint8 channel_id; /* Channel ID */
+ msg_type msg_id; /* Message ID */
+ kal_uint16 buff_size; /* Buffer size */
+ FDD_local_para_unpack_T buffer; /* Channel configuration message buffer */
+} FDD_msg_buf_unpack_T;
+
+typedef struct _fdd_cphy_msg_container_req_unpack_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 at_ref; /* Reference channge of activation time.
+ 0 : Ref channel is the released channel.
+ There should be ch to be released
+ 1 : Ref channel is the setup channel.
+ There should be ch to be setup.
+ */
+ kal_int16 rx_cfn; /* Indicate peer message receive cfn. Ex: tti = 4, receive frame number : 0,1,2,3. rx_cfn = 3 (set by ul1)
+ [Range]: -1 ~ 255.
+ -1 : Means upper layer internal control
+ */
+#ifdef __UMTS_R6__
+ kal_bool delay_restriction; /* From R6 : TS25.331 8.6.3.1 */
+#endif
+ FDD_meas_control_E meas_control; /* Indicate whether UL1 need to not to resume meas. after apply corresponding buffer's config. */
+
+ kal_uint8 msg_num; /* # of included msg. 1 ~ 4 */
+ FDD_msg_buf_unpack_T msg_buffer[4]; /* List of msg buffer for included channel msg */
+
+ /* [R5R6] For HS-DSCH and E-DCH */
+ kal_uint8 h_msg_num; /* # of included H-msg. 0~2 */
+ FDD_msg_buf_unpack_T h_msg_buffer[2]; /* List of msg buffer for included channel msg */
+ kal_uint8 e_msg_num; /* # of included E-msg. 0~2 */
+ FDD_msg_buf_unpack_T e_msg_buffer[2]; /* List of msg buffer for included channel msg */
+#ifdef __UMTS_R7__
+ kal_uint8 cpc_msg_num; /* # of included CPC-msg. 0~1 */
+ FDD_msg_buf_unpack_T cpc_msg_buffer[1]; /* List of msg buffer for included CPC msg */
+#endif /* __UMTS_R7__ */
+} fdd_cphy_msg_container_req_unpack_struct;
+
+typedef struct _ul1_umts_max_tx_pwr_red_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool valid;
+ //UMTS_CUSTOM_TAS_STATE_E tas_state; /*0: Main, 1: Div, 2: Main'*/
+ kal_uint8 umts_power_reduction_in_edb[20][2/*Service*/];
+
+ /* Add power reduction value for ANT1 (op=9/10).
+ * When user only specify one set of values by using op=1/3,
+ * L4C help copy parameters from umts_power_reduction_in_edb[] to umts_power_reduction_in_edb_tas[]*/
+ kal_uint8 umts_power_reduction_in_edb_tas[20][2/*Service*/];
+} ul1_umts_max_tx_pwr_red_req_struct;
+
+typedef enum
+{
+ FDD_UL1_EM_TST_CMD_TX_DPCH = 0,
+ FDD_UL1_EM_TST_CMD_RX_RSSI_MEASURE = 1,
+ FDD_UL1_EM_TST_CMD_GET_PD_MEASUREMENT = 2, // retrieved TX power
+ FDD_UL1_EM_TST_CMD_END
+} FDD_UL1_EM_TSTCmdType;
+
+typedef struct
+{
+ kal_int8 power;
+ kal_uint8 rf_band;
+ kal_uint16 ul_freq;
+} FDD_UL1_EM_TSTCmdTxDPCh_T;
+
+typedef struct
+{
+ kal_uint16 dl_freq;
+} FDD_UL1_EM_TSTCmdRxRSSI_T;
+
+typedef union
+{
+ FDD_UL1_EM_TSTCmdTxDPCh_T txdpch;
+ FDD_UL1_EM_TSTCmdRxRSSI_T rxrssi;
+} FDD_UL1_EM_TSTCmdParam;
+
+typedef struct _l4ul1_em_tst_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 src_id;
+ FDD_UL1_EM_TSTCmdType type;
+ FDD_UL1_EM_TSTCmdParam param;
+} l4ul1_em_tst_req_struct;
+
+
+typedef struct _l4ul1_em_tst_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 src_id;
+ kal_bool success;
+#if defined(__ATERFTX_ERROR_HANDLE_ENHANCE__)
+ ps_cause_enum err_cause;
+#endif //__ATERFTX_ERROR_HANDLE_ENHANCE__
+} l4ul1_em_tst_cnf_struct;
+
+typedef struct _l4ul1_em_tx_report_ind
+{
+ LOCAL_PARA_HDR
+
+ kal_int32 tx_power; // retrieved TX power
+} l4ul1_em_tx_report_ind_struct;
+
+typedef l4ul1_em_tst_req_struct l4cul1_em_tst_control_req_struct;
+typedef l4ul1_em_tst_cnf_struct l4cul1_em_tst_control_cnf_struct;
+typedef l4ul1_em_tx_report_ind_struct l4cul1_em_tx_report_ind_struct;
+
+typedef struct _l4cul1_get_rf_temperature_req_struct
+{
+ LOCAL_PARA_HDR
+
+} l4cul1_get_rf_temperature_req_struct;
+
+typedef struct _l4cul1_get_rf_temperature_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 modem_temperature;
+} l4cul1_get_rf_temperature_cnf_struct;
+
+typedef struct _l4cul1_rssi_measurement_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 rssi[2]; /* RSSI. Range: -400 ~ -100 means (-100 ~ -25)dBm 0.25 dB step */
+ kal_int32 rssi_edBm[2]; /* RSSI value in 1/8 dBm */
+ kal_uint16 uarfcn; /* UARFCN */
+
+} l4cul1_rssi_measurement_ind_struct;
+
+/* Inform SLT task that UL1 has finished task init */
+typedef struct _FDD_ul1_slt_task_init_ind_struct
+{
+ LOCAL_PARA_HDR
+
+} fdd_ul1_slt_task_init_ind_struct;
+
+#if defined (__MML1_ADT_ENABLE__)
+/*****************************************************************************
+ UL1 req for ADT Task
+*****************************************************************************/
+typedef struct _fdd_ul1_l1adt_enter_connected_req_struct
+{
+ LOCAL_PARA_HDR
+ FDD_ADT_Mode_E adt_mode;
+} fdd_ul1_l1adt_enter_connected_req_struct;
+
+typedef struct _fdd_ul1_l1adt_leave_connected_req_struct
+{
+ LOCAL_PARA_HDR
+ FDD_ADT_Mode_E adt_mode;
+} fdd_ul1_l1adt_leave_connected_req_struct;
+
+typedef struct _fdd_ul1_l1adt_enter_fdd_mode_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_ul1_l1adt_enter_fdd_mode_req_struct;
+
+typedef struct _fdd_ul1_l1adt_enter_fdd_mode_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_ul1_l1adt_enter_fdd_mode_ind_struct;
+
+/*****************************************************************************
+ confirm from ADT Task to UL1
+*****************************************************************************/
+typedef struct _fdd_ul1_l1adt_enter_connected_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_int32 adt_dl_result;
+ /*
+ {//PASS_DL_(UN)COMPLETE_xxx -> xxx means the current RAT mode
+ FAIL_OTHER_RAT_IS_CONN,
+ PASS_DL_COMPLETE_CONN,
+ PASS_DL_NOT_YET_FINISHED_CONN,
+ PASS_DL_COMPLETE_IDLE,
+ PASS_DL_NOT_YET_FINISHED_IDLE,
+ PASS_STOP_N_RESTART_DL_IDLE,
+ PASS_START_DL_IDLE
+ }
+ */
+} fdd_ul1_l1adt_enter_connected_cnf_struct;
+
+typedef struct _fdd_ul1_l1adt_leave_connected_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_int32 idle_result;
+ /*
+ {
+ NORMAL,
+ ABNORMAL_IDLE,
+ ABNORMAL_OTHER_CONN
+ }
+ */
+} fdd_ul1_l1adt_leave_connected_cnf_struct;
+
+typedef struct _fdd_ul1_l1adt_enter_fdd_mode_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_ul1_l1adt_enter_fdd_mode_cnf_struct;
+
+#endif
+
+/******************************************************************************
+ * MSG_ID_UL1D_LOOPBACK_REQ primptive
+ * FROM : TST
+ * TO : Dummy UPS
+ * DESCRIPTION :
+ *
+ ******************************************************************************/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 test_id;
+ kal_uint16 case_id;
+ kal_uint16 pattern_id;
+ void *pattern_address;
+ kal_uint32 pattern_size; // unit: byte
+ kal_uint32 pm[10];
+ kal_uint32 sz[30];
+ kal_uint32 ad[30];
+} ul1d_loopback_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 test_id;
+ kal_uint16 case_id;
+ kal_uint16 pattern_id;
+ void *pattern_address;
+ kal_uint32 pattern_size; // unit: byte
+ kal_uint32 pm[10];
+ kal_uint32 sz[30];
+ kal_uint32 ad[30];
+} modem_loopback_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 test_id;
+ kal_uint16 case_id;
+ kal_uint16 pattern_id;
+ kal_bool result; // true=pass, false=fail
+ char trace_msg[256]; // null-terminated string
+} modem_loopback_result_ind_struct;
+/* Yuda.lee added for Android M */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 srcid; /* srcid is set by REQUEST */
+ kal_uint32 lce_mode; /* STOP: 0, PUSH MODE: 1, PULL_MODE: 2 */
+ kal_uint32 lce_rpt_interval_ms; /* flexible time unit [ms] */
+} l4cul1_hspa_lce_report_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 srcid; /* srcid is set by REQUEST */
+} l4cul1_hspa_lce_report_pulldata_req_struct;
+
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 srcid; /* srcid is same as REQUEST */
+ kal_int8 lce_status; /* stopped:0, active: 1 */
+ kal_uint32 lce_act_interval_ms; /* actually reporting interval, unit [ms]*/
+} l4cul1_hspa_lce_report_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 srcid; /* PUSH MODE: 0xFF, otherwise srcid is same as REQUEST */
+ kal_uint8 conf_level; /* confidence level of capacity estimate (0~100)*/
+ kal_uint8 lce_suspend; /* 0: not suspended, 1: suspended, radio idle, handover, outage, and etc.*/
+ kal_uint32 last_hop_cap_kbps; /* capacity:kilobits/second, kbps*/
+} l4cul1_hspa_lce_report_ind_struct;
+
+#endif
+
diff --git a/mcu/interface/l1/ul1/internal/wlog3g.h b/mcu/interface/l1/ul1/internal/wlog3g.h
new file mode 100644
index 0000000..9521447
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/wlog3g.h
@@ -0,0 +1,33 @@
+void WriteHWRegister(kal_uint32 Address, kal_uint16 Value);
+void USB_LOGGING_3G_HISR(void);
+
+kal_uint16 USB_LOGGING_Get_3G_Status(kal_uint32 buf_index);
+void USB_LOGGING_3G_Reset(void);
+void USB_LOGGING_3G_Restart(void);
+void USB_LOGGING_3G_Init(kal_uint8* add1, kal_uint8* add2, kal_uint8* add3, kal_uint8* add4);
+void USB_LOGGING_3G_Start(void);
+void USB_LOGGING_3G_Stop(void);
+void USB_LOGGING_3G_LISR(void);
+void USB_LOGGING_3G_Drv_Create_ISR(void);
+void USB_LOGGING_3G_Clear_Buffer(kal_uint8 buf_idx, kal_uint8 idx);
+
+
+#define LOG3G_USB_L1D_FLLT_1 0x02
+#define LOG3G_USB_L1D_RDY_1 0x70
+#define LOG3G_USB_L1D_PID_1 0x3216
+#define LOG3G_USB_L1D_LEN_1 1024
+#define LOG3G_USB_L1D_ADDR_1 0x00
+
+/* LOG3G_USB_BUF_CTRL */
+#define LOG3G_USB_BUF_CTRL_CLR 0x00000000
+#define LOG3G_USB_BUF_CTRL_RDY 0x00000001
+#define LOG3G_USB_BUF_CTRL_RST 0x00000002
+#define LOG3G_LOG_ENABLE 0x80000000
+#define LOG3G_SCALER_DUMP_ENABLE 0x00000001
+
+#if IS_3G_CHIP_MT6276_AND_LATTER_VERSION
+#define LOG3G_ATB_BUFFER_NUM 0x0000000f
+#define LOG3G_ATB_BUFFER_SIZE 0x00007fff
+#define LOG3G_ATB_IF_ENABLE 0x40000000
+#endif
+
diff --git a/mcu/interface/l1/ul1/ul1_option.h b/mcu/interface/l1/ul1/ul1_option.h
new file mode 100644
index 0000000..a2ce987
--- /dev/null
+++ b/mcu/interface/l1/ul1/ul1_option.h
@@ -0,0 +1,361 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_option.h
+ *
+ * Project:
+ * --------
+ * MT6268 Project
+ *
+ * Description:
+ * ------------
+ * Define compile option for UL1A/UL1C.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef UL1_OPTION_H
+#define UL1_OPTION_H
+
+//#define __UL1C_R5R6_CODE__
+//#define __UL1_FAST_ABORT_SUPPORT__
+
+#if defined(__MTK_TARGET__)
+
+#if (defined __MD93__)
+#define __TASOLD_SUPPORT__
+#endif
+// one of the other will be enabled . both can not
+#if (defined __MD95__) || (defined __MD97__) || (defined __MD97P__)
+#define __UTAS_SUPPORT__
+#endif
+
+#if (defined __MD97__) || (defined __MD97P__)
+#define IS_UL1C_DYNAMIC_ANTENNA_TUNING_SUPPORT 1 /*Gen97 DAT is default enable*/
+#else
+#define IS_UL1C_DYNAMIC_ANTENNA_TUNING_SUPPORT defined(__DYNAMIC_ANTENNA_TUNING__)
+#endif
+
+#endif
+
+#if defined(__MTK_TARGET__)
+#if ( IS_3G_CHIP_MT6297 || IS_3G_CHIP_MT3967 || IS_3G_CHIP_MT6779)
+#define UL1_GNSS_MD_TIME_SYNC_SUPPORT 0
+#elif defined(__GNSS_MD_TIME_SYNC__)
+#define UL1_GNSS_MD_TIME_SYNC_SUPPORT 1
+#else
+#define UL1_GNSS_MD_TIME_SYNC_SUPPORT 0
+#endif
+#endif
+
+#if defined(L1_SIM)
+#define UL1_GNSS_MD_TIME_SYNC_SUPPORT 1
+#endif
+
+#if defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__) || defined(__L1_GPS_REF_TIME_SUPPORT__)
+#define __UL1_GPS_FRAME_SYNC_SUPPORT__
+#endif
+
+// For RAs change , this flag does not depend one amy other flag/HW
+//#ifndef __L1_STANDALONE__
+//#define __RAS_SUPPORT__
+//#endif
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+#define __UL1_GEMINI__
+/*As part of GEMINI Flag Cleanup __GEMINI_GSM__ and __GEMINI_MONITOR_PAGE_DURING_TRANSFER__ are replaced with __GEMINI__.
+__GEMINI_GSM__ can be replaced with __GEMINI__, but __GEMINI_MONITOR_PAGE_DURING_TRANSFER__ can be replaced with __GEMINI__ only provided that GEMINI V2 is always enabled and GEMINI 1 alone is not required.
+So with this change for UL1 __UL1_GEMINI__ is same as __UL1_GEMINI_2_0__*/
+//#ifdef __GEMINI_MONITOR_PAGE_DURING_TRANSFER__
+#define __UL1_GEMINI_2_0__
+//#endif /* __GEMINI_MONITOR_PAGE_DURING_TRANSFER__ */
+
+#endif /* __GEMINI__ && __UMTS_RAT__ */
+
+#ifdef __GEMINI_WCDMA__
+#define __UL1_GEMINI_WCDMA__
+#endif /* __GEMINI_WCDMA__ */
+
+#ifdef __UMTS_R8__
+/* new DL data buffer is only applied on 6280 and later projects.
+ If ul1d_p is built by other compile option, we should change the condition. */
+#define __UL1_NEW_DL_DATA_BUFFER__
+
+#ifdef __DYNAMIC_SWITCH_CACHEABILITY__
+#define __UL1_DL_DATA_DYNAMIC_CACHEABILITY__
+#endif /*__DYNAMIC_SWITCH_CACHEABILITY__*/
+
+#endif /*__UMTS_R8__*/
+
+
+#if defined( __UL1_GEMINI__ ) && defined( __UMTS_R8__ ) && defined( __MODIFY_CTCH_RECEPTION_PRIO__ )
+#define __CBS_IMPROVEMENT__
+#endif
+
+
+#if defined(__HSDPA_SUPPORT__) && defined(__UMTS_R8__)
+/* HSPASYS Control is only applied on 6280 or later projectes. */
+#define __UL1_HSPASYS_CONTROL__
+#endif /*__HSDPA_SUPPORT__ && __UMTS_R8__*/
+
+
+#ifdef __UMTS_R9__
+//Disable R9 compile option flag in UL1AC internally since there is no R9R10 support request, it can help reduce the EMI cost
+//#define __UMTS_R9_UL1__
+#endif /* __UMTS_R9__ */
+
+#ifdef __UMTS_R10__
+//Disable R10 compile option flag in UL1AC internally since there is no R9R10 support request, it can help reduce the EMI cost
+//#define __UMTS_R10_UL1__
+#endif /* __UMTS_R10__ */
+
+//Disable __L1_INTERNAL_TEST__ flag to reduce target code size. It can be enabled while carrying on Inject String Commands for internal testing only.
+//#define __L1_INTERNAL_TEST__
+
+#define __UL1_RF_TEMPERATURE_SUPPORT__
+
+#define __SMART_CS_3G_FDD__
+#define __SMART_CM_3G_FDD__
+//[ALPS04720723]: Disabling 5M filter
+//#define __5M_FILTER__
+//#define __SMART_CM_FORCE_SWITCH__
+#endif
+
diff --git a/mcu/interface/l1/ul1/ul1_public.h b/mcu/interface/l1/ul1/ul1_public.h
new file mode 100644
index 0000000..e2b331d
--- /dev/null
+++ b/mcu/interface/l1/ul1/ul1_public.h
@@ -0,0 +1,452 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_public.h
+ *
+ * Project:
+ * --------
+ * MT6276 Project
+ *
+ * Description:
+ * ------------
+ * UL1 exports functions which are used by other Layer 1 modules, such as L1, RTB, DM.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef UL1_PUBLIC_H
+#define UL1_PUBLIC_H
+
+#if 0
+#if defined(__UL1_GEMINI__) || defined ( __GEMINI__ )
+/* under construction !*/
+#endif
+#endif
+//#include "kal_general_types.h"
+#include "ul1_def.h"
+#if ( defined( __GEMINI__ ) && defined ( __UMTS_RAT__ ) ) && defined ( __MTK_TARGET__ )
+#include "l1_rtb.h"
+#endif
+
+#define MS_PER_FRAME 10
+#define CHIP_COUNT_PER_FRAME 38400
+#define CHIP_COUNT_PER_SLOT 2560
+#define CHIP_COUNT_PER_SYMBOL 256
+#define ECHIP_COUNT_PER_CHIP 8
+#define ECHIP_COUNT_PER_FRAME ( CHIP_COUNT_PER_FRAME*ECHIP_COUNT_PER_CHIP )
+#define ECHIP_COUNT_PER_SLOT ( CHIP_COUNT_PER_SLOT*ECHIP_COUNT_PER_CHIP )
+#define SLOTS_PER_FRAME 15
+#define SUBFRAMES_PER_FRAME 5
+#define SLOTS_PER_SUBFRAME 3
+#define ECHIP_2_SLOT( len ) ( (len) / ECHIP_COUNT_PER_SLOT )
+#define ECHIP_2_FRAME( len ) ( (len) / ECHIP_COUNT_PER_FRAME )
+#define MAX_SFN 4096
+#define MAX_CFN 256
+#define FIND_TIMER_ALL_SFN_RANGE (MAX_SFN - 1)
+#define FIND_TIMER_ALL_CFN_RANGE (MAX_CFN - 1)
+
+#define TIMER_PRIORITY_INTRABCH_LOW 0x00000001 /* SIB, SIB7, SFN, SFN meas. */
+#define TIMER_PRIORITY_INTRABCH_MED 0x00000002 /* SIB, SIB7, SFN, SFN meas. */
+#define TIMER_PRIORITY_INTRABCH_HIGH 0x00000004 /* SIB, SIB7, SFN, SFN meas. */
+#define TIMER_PRIORITY_INTERBCH_LOW 0x00000010 /* SIB, SIB7, SFN, SFN meas. */
+#define TIMER_PRIORITY_INTERBCH_MED 0x00000020 /* SIB, SIB7, SFN, SFN meas. */
+#define TIMER_PRIORITY_INTERBCH_HIGH 0x00000040 /* SIB, SIB7, SFN, SFN meas. */
+#define TIMER_PRIORITY_MAINCH 0x00000080 /* PICH(PCH), FACH, DLDCH, ULDCH. */
+#define TIMER_TRIORITY_PHASE2_PCH 0x00020000 /* Phase 2 PCH */
+#define TIMER_PRIORITY_SUBCH 0x00000100 /* CTCH, RACH. */
+#define TIMER_PRIORITY_TGPS 0x00000200
+#define TIMER_PRIORITY_CCM 0x00000400 /* Channel configuration start/stop. */
+#define TIMER_PRIORITY_BCHSTOP 0x00000800
+#define TIMER_PRIORITY_STOP_ALL 0x00002000 /* Stop all CH, CM, CS */
+#define TIMER_PRIORITY_CS_LOW 0x00001000 /* FS or CS, depending on L1 state. */
+#define TIMER_PRIORITY_CS_HIGH 0x00004000 /* SCS. */
+#define TIMER_PRIORITY_DCH_CONTROL 0x00008000
+#define TIMER_PRIORITY_HSDSCH_CONTROL 0x00000008 /* HSDSCH control */
+#define TIMER_PRIORITY_EDCH_CONTROL 0x00002000 /* EDCH control */
+#define TIMER_PRIORITY_EFACH_DRX_MEAS 0x10000000 /* Inter-F and inter-RAT CM for EFACH DRX */
+#define TIMER_PRIORITY_EM 0x00010000 /* EM usage*/
+
+#define UL1_FRAME ( 10000 )
+#define UL1_FRAME2RTB( x ) ( (x)*UL1_FRAME )
+#define UL1_ECHIP2RTB( x ) ( ((x)*25)/(2*384) )
+#define RTB2UL1_ECHIP( x ) ( ((x)*2*384)/25 )
+
+typedef kal_int16 ACT_TIME; /* -1 ~ 255 */
+typedef kal_int16 CFN; /* 0 ~ 255 */
+typedef kal_int16 SFN; /* 0 ~ 4095 */
+typedef kal_uint32 UTimeStamp;
+typedef kal_uint8 UTID;
+typedef kal_uint16 UARFCN;
+
+/* UTimer structures and API. */
+#define UL1_TIMER_TYPE(x) x
+typedef enum
+{
+#include "ul1_timertype.h"
+} UTimerType;
+#undef UL1_TIMER_TYPE
+
+typedef struct
+{
+ kal_int16 fn;
+ kal_int32 echips;
+} UTime;
+
+/* L1S use only!
+ * It is used for calculating DL TPC CER(Command Error Rate). */
+#ifdef __L1_STANDALONE__
+typedef struct
+{
+ LOCAL_PARA_HDR
+ FDD_edch_scell_E carrier;
+ kal_uint8 cfn;
+ kal_uint8 dl_tpc_result[15]; /* DL TPC result for each slot.
+ - dl_tpc_result[0]: slot 0, dl_tpc_result[1]: slot 1, dl_tpc_result[2]: slot 2,...
+ - dl_tpc_result[]: 1 -> UP; 3 -> DOWN; 0 -> HOLD */
+} ul1d_dl_tpc_result_ind_struct;
+#endif
+
+void UL1_SFNTimeAdd_Frames( UTime *time, kal_uint16 fn );
+void UL1_SFNTimeSub_Frames( UTime *time, kal_int16 fn );
+void UL1_SFNTimeAdd_EChips( UTime *time, kal_int32 tm );
+void UL1_SFNTimeSub_EChips( UTime *time, kal_int32 tm );
+void UL1_SFNTimeAdd( UTime *time, kal_int16 fn, kal_int32 tm );
+void UL1_SFNTimeSub( UTime *time, kal_int16 fn, kal_int32 tm );
+kal_int32 UL1_SFNTimeDiff( UTime timeA, UTime timeB );
+void UL1_CFNTimeAdd_EChips( UTime *time, kal_int32 tm );
+void UL1_CFNTimeSub_EChips( UTime *time, kal_int32 tm );
+void UL1_CFNTimeAdd( UTime *time, kal_int16 fn, kal_int32 tm );
+void UL1_CFNTimeSub( UTime *time, kal_int16 fn, kal_int32 tm );
+kal_int32 UL1_CFNTimeDiff( UTime timeA, UTime timeB );
+//Riley add
+void UL1_TimeAdd( UTime *time, kal_int32 fn, kal_int32 tm );
+void UL1_TimeSub( UTime *time, kal_int16 fn, kal_int32 tm, kal_int16 max_sfn_add );
+//Riley add end
+/* End of Time arithmetic. */
+void UL1_TimeAdd_EChips( UTime *time, kal_int32 tm, kal_int32 *max_sfn_add );
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+kal_int16 UL1I_GetTimeStamp_2G( kal_int32 *tsChips );
+#endif
+
+/* Frame numbers arithmetic. */
+SFN UL1_SFNAdd( SFN a, SFN b );
+SFN UL1_SFNAdd_For_Sib( SFN a, SFN b );
+SFN UL1_SFNSub( SFN a, SFN b );
+kal_int16 UL1_SFNDiff( SFN a, SFN b );
+CFN UL1_CFNAdd( CFN a, CFN b );
+CFN UL1_CFNSub( CFN a, CFN b );
+kal_int16 UL1_CFNDiff( CFN a, CFN b );
+CFN UL1_GetCFN( SFN sfn );
+/* End of Frame numbers arithmetic. */
+
+/* L1I queue function. */
+void UL1I_QueueFunction( void ( *code )( void ) );
+void UL1I_RemoveQueueFunction( void ( *code )( void ) );
+/* End of L1I queue function. */
+
+kal_int16 UL1I_Calc_Delay_To_Next_PICH( void );
+#if defined(__UL1_GEMINI__) || defined ( __GEMINI__ )
+void *UL1I_Get_PICHUTimerAddress( void );
+#endif
+
+kal_bool UL1C_Is3GDedicated( void );
+kal_bool UL1C_CheckSleep( kal_uint32 *sn );
+#ifdef MTK_SLEEP_ENABLE
+void UL1C_RecoverTime( kal_uint16 fn );
+#endif
+
+/*Speech-Modem Resycn API*/
+void UL1D_Speech_Resync_Reset_Time_Offset( void );
+kal_int16 UL1D_Speech_Resync_Get_Time_Offset( void );
+void UL1D_Speech_Resync_Update_Time_Offset( kal_bool direction );
+
+#if ( defined( __GEMINI__ ) && defined ( __UMTS_RAT__ ) ) && defined ( __MTK_TARGET__ )
+void UL1_AssertFunction( RTB_ASSERT_CAUSE cause, RTB_SIM_INDEX SIM_Index, kal_uint32 para1, kal_uint32 para2 );
+#endif /* __UL1_GEMINI__&&__MTK_TARGET__ */
+#endif
+
diff --git a/mcu/interface/l1/ul1/ul1_timertype.h b/mcu/interface/l1/ul1/ul1_timertype.h
new file mode 100644
index 0000000..7c619d5
--- /dev/null
+++ b/mcu/interface/l1/ul1/ul1_timertype.h
@@ -0,0 +1,518 @@
+/*******************************************************************************
+* Modification Notice:
+* --------------------------
+* This software is modified by MediaTek Inc. and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*******************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_timertype.h
+ *
+ * Project:
+ * --------
+ * MT6276 Project
+ *
+ * Description:
+ * ------------
+ * Define 3G utimertype
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+UL1_TIMER_TYPE( UTimerNone ),
+ UL1_TIMER_TYPE( UTimerTGPSTick ),
+ UL1_TIMER_TYPE( UTimerStartTGPS ),
+ UL1_TIMER_TYPE( UTimerTGPSControl ),
+ UL1_TIMER_TYPE( UTimerDeleteTGPS ), //Also add to trace.tmd
+ UL1_TIMER_TYPE( UTimerStopCC ),
+ UL1_TIMER_TYPE( UTimerCCTimingAlign ),
+ UL1_TIMER_TYPE( UTimerStartCC ),
+ UL1_TIMER_TYPE( UTimerFACH ),
+ UL1_TIMER_TYPE( UTimerSkipGAP ),
+ UL1_TIMER_TYPE( UTimerResumeGAP ),
+ UL1_TIMER_TYPE( UTimerUnlockFMO ),
+ UL1_TIMER_TYPE( UTimerRACH ),
+ UL1_TIMER_TYPE( UTimerRestartRACH ),
+ UL1_TIMER_TYPE( UTimerSFNMeas ),
+ UL1_TIMER_TYPE( UTimerRxSFNMeas ),
+ UL1_TIMER_TYPE( UTimerStopSFNMeas ),
+ UL1_TIMER_TYPE( UTimerSFNMeas_DDLAbort ),
+ UL1_TIMER_TYPE( UTimerCTCH ),
+ UL1_TIMER_TYPE( UTimerRxCTCH ),
+ UL1_TIMER_TYPE( UTimerCTCH_DDLAbort ),
+ UL1_TIMER_TYPE( UTimerSFN ),
+ UL1_TIMER_TYPE( UTimerRxSFN ),
+ UL1_TIMER_TYPE( UTimerStopSFN ),
+ UL1_TIMER_TYPE( UTimerSFN_DDLAbort ),
+ UL1_TIMER_TYPE( UTimerPCH ),
+ UL1_TIMER_TYPE( UTimerRxPCH ),
+ UL1_TIMER_TYPE( UTimerRestartPCH ),
+ UL1_TIMER_TYPE( UTimerSkipPCH ),
+ UL1_TIMER_TYPE( UTimerResumePCH ),
+ UL1_TIMER_TYPE( UTimerReconfigSmartPaging ),
+ UL1_TIMER_TYPE( UTimerPCHRxDSwitch ),
+ UL1_TIMER_TYPE( UTimerPCHWakeup ),
+ UL1_TIMER_TYPE( UTimerClearForceNormalPCH ),
+ UL1_TIMER_TYPE(UTimerFreqCorrection),
+ UL1_TIMER_TYPE(UTimerRxFreqCorrection),
+ /* __TAS_SUPPORT__ */
+ UL1_TIMER_TYPE( UTimerTASPCH ),
+ UL1_TIMER_TYPE( UTimerTASDedicated ),
+ UL1_TIMER_TYPE( UTimerTASGuardPeriod ),
+ UL1_TIMER_TYPE( UTimerTASSwitchBackPeriod ),
+ UL1_TIMER_TYPE( UTimerTASRelaxDB ),
+ UL1_TIMER_TYPE( UTimerRASDedicated ),
+ UL1_TIMER_TYPE( UTimerRASProtect ),
+ UL1_TIMER_TYPE( UTimerRASS2W ),
+ /* END of __TAS_SUPPORT__ */
+ UL1_TIMER_TYPE( UTimerUTASDedicated ),
+ UL1_TIMER_TYPE( UTimerUTASSwitchBackPeriod ),
+ UL1_TIMER_TYPE( UTimerUTASRelaxPwrDB ),
+ UL1_TIMER_TYPE( UTimerUTASRelaxHrDB ),
+ UL1_TIMER_TYPE( UTimerUTASRBSetup ),
+ UL1_TIMER_TYPE( UTimerConfigCTCH ),
+ UL1_TIMER_TYPE( UTimerCTCHL2SCHED ),
+ UL1_TIMER_TYPE( UTimerCTCHAdjustment ),
+ UL1_TIMER_TYPE( UTimerSIB ),
+ UL1_TIMER_TYPE( UTimerRxSIB ),
+ UL1_TIMER_TYPE( UTimerReconfigSIB ),
+ UL1_TIMER_TYPE( UTimerStopSIB ),
+ UL1_TIMER_TYPE( UTimerSIB_DDLAbort ),
+ UL1_TIMER_TYPE( UTimerSIB_RRPriority ),
+ UL1_TIMER_TYPE( UTimerDLDCH ),
+ UL1_TIMER_TYPE( UTimerCRC ),
+ UL1_TIMER_TYPE( UTimerASU ),
+ UL1_TIMER_TYPE( UTimerASUStop ),
+ UL1_TIMER_TYPE( UTimerDLDCHConfig ),
+ UL1_TIMER_TYPE( UTimerDLDCHQuality ),
+ UL1_TIMER_TYPE( UTimerULDCH ),
+ UL1_TIMER_TYPE( UTimerULDCHConfig ),
+ UL1_TIMER_TYPE( UTimerULDCHTFC ),
+ UL1_TIMER_TYPE( UTimerFreqScan ),
+ UL1_TIMER_TYPE( UTimerSCS ),
+ UL1_TIMER_TYPE( UTimerFAChRptPeriod ),
+ UL1_TIMER_TYPE( UTimerDChRptPeriod ),
+ UL1_TIMER_TYPE( UTimerNullRptPeriod ),
+ UL1_TIMER_TYPE( UTimerCMStop ),
+ UL1_TIMER_TYPE( UTimerGAP ),
+ UL1_TIMER_TYPE( UTimerGAPStop ),
+ UL1_TIMER_TYPE( UTimerGAPStopCnf ),
+ UL1_TIMER_TYPE( UTimerLeaveConfig ),
+ UL1_TIMER_TYPE( UTimerStandby ),
+ UL1_TIMER_TYPE( UTimerDM ),
+ UL1_TIMER_TYPE( UTimerTGPSReconfigCheck ),
+ UL1_TIMER_TYPE( UTimerTGPSReconstruct ),
+ UL1_TIMER_TYPE( UTimerDummyTGPSTick ),
+ UL1_TIMER_TYPE( UTimerRssiSnifferStart ),
+ UL1_TIMER_TYPE( UTimerRssiSnifferStop ),
+ UL1_TIMER_TYPE( UTimerRssiSnifferContinue ),
+ UL1_TIMER_TYPE( UTimerTxAccessRACH ),
+ UL1_TIMER_TYPE( UTimerHSDSCHStart ),
+ UL1_TIMER_TYPE( UTimerHSDSCHStop ),
+ UL1_TIMER_TYPE( UTimerHSDSCHModify ),
+ UL1_TIMER_TYPE( UTimerHSDSCHSuspend ),
+ UL1_TIMER_TYPE( UTimerHSDSCH_OCIC ),
+ UL1_TIMER_TYPE( UTimerEDCHStart ),
+ UL1_TIMER_TYPE( UTimerEDCHStop ),
+ UL1_TIMER_TYPE( UTimerEDCHRemove ),
+ UL1_TIMER_TYPE( UTimerEDCHConfig ),
+ UL1_TIMER_TYPE(UTimerBANDRpt),
+ /* __UL1_GEMINI__ */
+ UL1_TIMER_TYPE( UTimerLeaveSuspendConfig ),
+ UL1_TIMER_TYPE( UTimerSuspendConfig ),
+ /* __UL1_GEMINI_2_0__ */
+ UL1_TIMER_TYPE( UTimerRx ),
+ UL1_TIMER_TYPE( UTimerTx ),
+ UL1_TIMER_TYPE( UTimerFSGap ),
+ UL1_TIMER_TYPE( UTimerCMCSGap ),
+ UL1_TIMER_TYPE( UTimerRxTxDSPStop ),
+ /* __UL1_GEMINI_2_0__ */
+ /* End of __UL1_GEMINI__ */
+ UL1_TIMER_TYPE( UTimerTreselectionCM ),
+ UL1_TIMER_TYPE( UTimerCompensateCMCS ),
+ UL1_TIMER_TYPE( UTimerOneShotCMCS ),
+ UL1_TIMER_TYPE( UTimerAdditionalCS ),
+ UL1_TIMER_TYPE( UTimerGPSTimeSync ),
+ UL1_TIMER_TYPE( UTimerTimeSync ),
+ /* 20110110: inter-freq measurement alarm */
+ UL1_TIMER_TYPE( UTimerInterFreqAlarm ),
+ /* 20110110: End */
+ /* __UMTS_R7__ */
+ UL1_TIMER_TYPE( UTimerPCHCycle2 ),
+ UL1_TIMER_TYPE( UTimerEFACH ),
+ UL1_TIMER_TYPE( UTimerCPCEnable ),
+ UL1_TIMER_TYPE( UTimerCPCStop ),
+ UL1_TIMER_TYPE( UTimerCPCActivate ),
+ /* __UL1_GEMINI_2_0__ */
+ UL1_TIMER_TYPE( UTimerCPCTx ),
+ UL1_TIMER_TYPE( UTimerCPCTxRelease ),
+ /* __UL1_GEMINI_2_0__ END */
+ /* __UMTS_R7__ END */
+ /* __UMTS_R8__ */
+ UL1_TIMER_TYPE( UTimerSecHSDSCHSuspend ),
+ UL1_TIMER_TYPE( UTimerHSDSCH_MonitorOrderStart ),
+ UL1_TIMER_TYPE( UTimerHSDSCH_MonitorOrderStop ),
+ UL1_TIMER_TYPE( UTimerCEDCHSuspend ),
+ UL1_TIMER_TYPE( UTimerCEDCHReport ),
+ UL1_TIMER_TYPE( UTimerCEDCHRelease ),
+ /* __UL1_HSPASYS_CONTROL__ */
+ UL1_TIMER_TYPE( UTimerHSPASYSOn ),
+ UL1_TIMER_TYPE( UTimerHSPASYSOff ),
+ UL1_TIMER_TYPE( UTimerHSUPASYSOn ),
+ UL1_TIMER_TYPE( UTimerHSUPASYSOff ),
+ /*__UL1_HSPASYS_CONTROL__*/
+ UL1_TIMER_TYPE( UTimerDRXInterfCM ),
+ UL1_TIMER_TYPE( UTimerDRXInterratCM ),
+ /* __UMTS_R8__ END */
+ /* __UMTS_R9__ */
+ UL1_TIMER_TYPE( UTimerSecDLDCHQuality ),
+ UL1_TIMER_TYPE( UTimerSecASUStop ),
+ UL1_TIMER_TYPE( UTimerSecULDCH ),
+ UL1_TIMER_TYPE( UTimerSecEDCHStart ),
+ UL1_TIMER_TYPE( UTimerSecEDCHStop ),
+ UL1_TIMER_TYPE( UTimerSecEDCHRemove ),
+ UL1_TIMER_TYPE( UTimerSecEDCHConfig ),
+ /* __UMTS_R9__ END */
+ /* __MULTI_MODE_SUPPORT__ */
+ UL1_TIMER_TYPE( UTimerActiveAutoGap ),
+ UL1_TIMER_TYPE( UTimerStopActiveGap ),
+ UL1_TIMER_TYPE( UTimerStandbyAutoGap ),
+ UL1_TIMER_TYPE( UTimerStandbyAutoGapSuspendNormal ),
+ UL1_TIMER_TYPE( UTimerStandbyAutoGapStop ),
+ UL1_TIMER_TYPE( UTimerStandbyAutoGapEnd ),
+ UL1_TIMER_TYPE( UTimerFSAutoGap ),
+ UL1_TIMER_TYPE( UTimerFSAutoGapStop ),
+ /* __MULTI_MODE_SUPPORT__ END */
+ /* __IOT_ECS_SUPPORT__ */
+ UL1_TIMER_TYPE( UTimerECSStart ),
+ UL1_TIMER_TYPE( UTimerECSStop ),
+ /* __IOT_ECS_SUPPORT__ */
+ UL1_TIMER_TYPE( UTimerStandbyStopCMCS ),
+ /* Engineering Mode */
+ UL1_TIMER_TYPE( UTimerEM ),
+ /* Inject String related */
+ UL1_TIMER_TYPE( UTimerPseudoSuspend ),
+ UL1_TIMER_TYPE( UTimerPICHForceNormal ),
+ /* __LCE_SUPPORT__ */
+ UL1_TIMER_TYPE( UTimerLCE ),
+ UL1_TIMER_TYPE( UTimerLCEStop ),
+ UL1_TIMER_TYPE(UTimerExtendedLCE),
+ /* __UL1_GEMINI_WCDMA__ */
+ UL1_TIMER_TYPE( UTimerSlaveStopCC ),
+ UL1_TIMER_TYPE( UTimerSlaveStopStandbyGap ),
+ UL1_TIMER_TYPE( UTimerSlaveStartCC ),
+ UL1_TIMER_TYPE( UTimerMasterStopCC ),
+ UL1_TIMER_TYPE( UTimerMasterTimingAlign ),
+ UL1_TIMER_TYPE( UTimerMasterStartCC ),
+ UL1_TIMER_TYPE( UTimerPhase2PCH ),
+ UL1_TIMER_TYPE( UTimerPhase2RxPCH ),
+ UL1_TIMER_TYPE( UTimerInternalCMTickIDLE ),
+ UL1_TIMER_TYPE( UTimerTriggerDDL ),
+ /* __UL1_GEMINI_WCDMA__ */
+ /* RF tuning by AP events - DAT, SAR, ...... */
+ UL1_TIMER_TYPE( UTimerRFTuning ),
+ UL1_TIMER_TYPE( UTimerGNSSMDTimeSync ),
+ UL1_TIMER_TYPE(UTimerUARFCNRpt),
+ UL1_TIMER_TYPE( UTimerEnd ),
diff --git a/mcu/interface/l1/ul1/ul1c_struct.h b/mcu/interface/l1/ul1/ul1c_struct.h
new file mode 100644
index 0000000..57b67b8
--- /dev/null
+++ b/mcu/interface/l1/ul1/ul1c_struct.h
@@ -0,0 +1,122 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1c_struct.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * Layer 1 Cor and UL1A message definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _UL1C_STRUCT_H
+#define _UL1C_STRUCT_H
+
+#ifndef UL1_TYPES_H
+#error "ul1_types.h should be included before ul1c_struct.h"
+#endif
+
+
+typedef struct _ul1c_send_report_struct
+{
+ LOCAL_PARA_HDR
+
+ UReport report;
+
+} ul1c_send_report_struct;
+
+typedef struct _ul1c_wakeup_ul1task_struct
+{
+ LOCAL_PARA_HDR
+
+} ul1c_wakeup_ul1task_struct;
+
+
+typedef struct _ul1c_user_def_func_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 func_id;
+
+ /* Parameters */
+ kal_uint8 pu8[32];
+ kal_int8 p8[32];
+ kal_uint16 pu16[32];
+ kal_int16 p16[32];
+ kal_uint32 pu32[32];
+ kal_int32 p32[32];
+
+} ul1c_user_def_func_struct;
+
+#endif