[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/ul1/internal/ehlhwsim_struct.h b/mcu/interface/l1/ul1/internal/ehlhwsim_struct.h
new file mode 100644
index 0000000..3779100
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ehlhwsim_struct.h
@@ -0,0 +1,104 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * uhlhwsim_struct.h
+ *
+ * Project:
+ * --------
+ * U4G adaptor
+ *
+ * Description:
+ * ------------
+ * File that contains UMTS high-level (VRf) data structure for HWSIM. This file
+ * is used by u4g_ehlhwsim.h.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+ * Included header files
+ *******************************************************************************/
+#ifndef _u4g_ehlHWSIM_STRUCT_H
+#define _u4g_ehlHWSIM_STRUCT_H
+
+#if defined(__UNITE_SPLIT_SYSTEM_TARGET_SIDE__) || defined(__UESIM_KS_FPGA_SIDE__)
+#include "common.h"
+#endif
+
+#include "kal_public_api.h"
+#include "evrf_hl_intf.h"
+
+
+typedef struct u4g_ehlhwsim_dl_data_tag
+{
+ Evrf_rxFilter_t rx_filter;
+} u4g_ehlhwsim_dl_data_t;
+
+
+
+typedef struct u4g_ehlhwsim_dl_resource_req_tag
+{
+ Evrf_rxFilter_t rx_filter;
+} u4g_ehlhwsim_dl_resource_req_t;
+
+typedef struct u4g_ehlhwsim_ul_data_req_struct_tag
+{
+ int dummy;
+} u4g_ehlhwsim_ul_data_req_struct_t;
+
+typedef struct u4g_ehlhwsim_ul_resource_req_tag
+{
+ Evrf_txFilter_t tx_filter;
+ Evrf_hl_txPayloadObject_t txPayLoadObject;
+#if defined(__UESIM_KS_FPGA_SIDE__)
+ UINT32 padding2;
+#endif
+} u4g_ehlhwsim_ul_resource_req_t;
+
+#endif /* _UHLHWSIM_STRUCT_H */
diff --git a/mcu/interface/l1/ul1/internal/hal_ul1_def_internal.h b/mcu/interface/l1/ul1/internal/hal_ul1_def_internal.h
new file mode 100644
index 0000000..6f9992b
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/hal_ul1_def_internal.h
@@ -0,0 +1,166 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * hal_ul1_def_internal.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * This file contains common typedef, definition prototypes exported by L1 for MMI/Middleware
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _HAL_UL1_DEF_H_internal
+#define _HAL_UL1_DEF_H_internal
+
+#if defined(MT6280_S00) //MT6280E1
+
+#define MTCMOS_HSPASYS_1_MODE 1 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_2_MODE 1
+#define MTCMOS_HSPASYS_3_MODE 1
+#define MTCMOS_HSPASYS_4_MODE 1
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_2_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 1
+
+#elif defined(MT6280_S01) //MT6280E2
+
+#define MTCMOS_HSPASYS_1_MODE 1 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_2_MODE 1
+#define MTCMOS_HSPASYS_3_MODE 0
+#define MTCMOS_HSPASYS_4_MODE 0
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_2_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 1
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 1
+
+#elif defined(MT6589_S00) //MT6589E1
+
+#define MTCMOS_HSPASYS_1_MODE 1 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_2_MODE 1
+#define MTCMOS_HSPASYS_3_MODE 0
+#define MTCMOS_HSPASYS_4_MODE 0
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 3
+#define MTCMOS_HSPASYS_2_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 3
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 2
+
+#elif defined(MT6572_S00) //MT6572E1
+
+#define MTCMOS_HSPASYS_1_MODE 0 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_3_MODE 0
+#define MTCMOS_HSPASYS_4_MODE 0
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 2
+
+#elif defined(MT6582_S00) //MT6582E1
+
+#define MTCMOS_HSPASYS_1_MODE 0 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_3_MODE 0
+#define MTCMOS_HSPASYS_4_MODE 0
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 2
+
+#elif defined(MT6290_S00) || defined(MT6290_S01) || defined(MT6595_S00) // MT6290E1 || MT6290E2 || MT6595_S00
+
+#define MTCMOS_HSPASYS_1_MODE 1 //(0 means HW mode, 1 means SW mode)
+#define MTCMOS_HSPASYS_2_MODE 1
+#define MTCMOS_HSPASYS_3_MODE 0
+#define MTCMOS_HSPASYS_4_MODE 0
+#define MTCMOS_HSPASYS_1_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_2_PWRON_SETTLE 2
+#define MTCMOS_HSPASYS_3_PWRON_SETTLE 3
+#define MTCMOS_HSPASYS_4_PWRON_SETTLE 2
+
+#endif
+
+#endif
+
+
+
+
diff --git a/mcu/interface/l1/ul1/internal/nrhwsim_struct.h b/mcu/interface/l1/ul1/internal/nrhwsim_struct.h
new file mode 100644
index 0000000..936a38a
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/nrhwsim_struct.h
@@ -0,0 +1,54 @@
+/***************************************************************************
+ * Copyright (c) 2018 MediaTek Inc. All Rights Reserved.
+ * --------------------
+ * This software is protected by copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc.
+ ***************************************************************************
+ *
+ * $Id: $
+ * $Revision: $
+ * $DateTime: $
+ *
+ *************************************************************************
+ *
+ * File Description
+ * ----------------
+ *
+ *
+ ***************************************************************************/
+/*******************************************************************************
+ * Included header files
+ *******************************************************************************/
+#ifndef NR_HWSIM_STRUCT_H
+#define NR_HWSIM_STRUCT_H
+
+#include "kal_public_api.h"
+#include "nrvrf_intf.h"
+
+
+typedef struct NrHwsimDlData_tag
+{
+ Nrvrf_rxFilter_t rx_filter;
+} NrHwsimDlData_t;
+
+
+
+typedef struct NrHwsimDlResourceReq_tag
+{
+ Nrvrf_rxFilter_t rx_filter;
+} NrHwsimDlResourceReq_t;
+
+typedef struct NrHwsimUlDataReq_tag
+{
+ int dummy;
+} NrHwsimUlDataReq_t;
+
+typedef struct NrHwsimUlResourceReq_tag
+{
+ Nrvrf_txFilter_t tx_filter;
+ Nrvrf_txPayloadObject_t txPayLoadObject;
+} NrHwsimUlResourceReq_t;
+
+#endif /* NR_HWSIM_STRUCT_H */
diff --git a/mcu/interface/l1/ul1/internal/uhlhwsim_struct.h b/mcu/interface/l1/ul1/internal/uhlhwsim_struct.h
new file mode 100644
index 0000000..fb3f27d
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/uhlhwsim_struct.h
@@ -0,0 +1,570 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * uhlhwsim_struct.h
+ *
+ * Project:
+ * --------
+ * U4G adaptor
+ *
+ * Description:
+ * ------------
+ * File that contains UMTS high-level (VRf) data structure for HWSIM. This file
+ * is used by uhlhwsim.h.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+ * Included header files
+ *******************************************************************************/
+#ifndef _UHLHWSIM_STRUCT_H
+#define _UHLHWSIM_STRUCT_H
+
+#include "kal_public_api.h"
+
+/*****************************************************************************
+* Definitions
+*****************************************************************************/
+//#define TTS_OF_2MS TTS_OF_A_ECHIP*30720/500
+#define TTS_OF_2MS 307200/5
+#define TTS_OF_10MS 307200
+
+/* These are temporary defined as there exist no IRQ codes for C2K */
+#define IRQ_EVENT_TIMER_CODE OSC_ISR_SRC_CUSTOM7
+
+#define U3G_SLOT_MAX_WRAP_VALUE 16
+#define UHLHWSIM_MAX_PCCPCH_DATA_SIZE 39
+#define UHLHWSIM_MAX_FOUND_CELLS 8
+#define UHLHWSIM_MAX_UL_CELLS 2
+#define UHLHWSIM_MAX_TRCH 8
+#define UHLHWSIM_MAX_SCCPCH 5
+#define UHLHWSIM_MAX_DL_UARFCNS 4
+#ifdef __UE_SIMULATOR__
+#define UHLHWSIM_MAX_UL_DATA 829 /* Maximum UL transport block array size. Matches ul1_cnst.h in mcu/interface/ul1_interface */
+#else
+/* Used in UL1B unit test only.*/
+#define UHLHWSIM_MAX_UL_DATA (829/4)
+#endif
+#define UHLHWSIM_MAX_SFN 4096
+#define UHLHWSIM_MAX_SUB_FRAME 5
+#ifdef __UE_SIMULATOR__
+#define UHLHWSIM_MAX_HS_PDU_SIZE_IN_BITS (42192)
+#else
+/* Used in UL1B unit test only.*/
+#define UHLHWSIM_MAX_HS_PDU_SIZE_IN_BITS (42192/16)
+#endif
+#define UHLHWSIM_MAX_HS_PDU_SIZE_IN_BYTES (((UHLHWSIM_MAX_HS_PDU_SIZE_IN_BITS+32+31)/32)*4) /* 42192/8 = 5274 Bytes */
+#define UHLHWSIM_MAX_EDCH_TB_SIZE (23000/8) /* s according to HW spec max tb size is 22996 bits (Rel-8)*/
+#ifdef __UE_SIMULATOR__
+#define UHLHWSIM_MAX_DL_DATA_SIZE 1150
+#else
+/* Used in UL1B unit test only.*/
+/* MSCComposer crashed when uhlhwsim_dl_data_ind_struct size too big.*/
+#define UHLHWSIM_MAX_DL_DATA_SIZE 575/2
+#endif
+
+
+/*******************************************************************************
+ * Global Declarations
+ ******************************************************************************/
+typedef kal_uint16 uhlhwsim_dl_uarfcn_t;
+typedef kal_uint16 uhlhwsim_num_uarfcn_t;
+typedef kal_uint16 uhlhwsim_num_cell_obj_t;
+typedef kal_int32 uhlhwsim_dl_power_t;
+typedef kal_uint16 uhlhwsim_cell_psc_t;
+typedef kal_uint16 uhlhwsim_sfn_t;
+typedef kal_uint8 uhlhwsim_tb_data_t;
+typedef kal_uint8 uhlhwsim_sccpch_num_t;
+
+typedef kal_int32 uhlhwsim_ul_power_t;
+typedef kal_uint16 uhlhwsim_ul_uarfcn_t;
+typedef kal_uint16 uhlhwsim_ul_tfci_t;
+typedef kal_uint16 uhlhwsim_ul_trch_id_t;
+typedef kal_uint32 uhlhwsim_ul_tb_size_t;
+typedef kal_uint32 uhlhwsim_ul_tb_cnt;
+typedef kal_uint16 uhlhwsim_ul_code_type_t;
+typedef kal_uint16 uhlhwsim_ul_tti_t;
+typedef kal_uint16 uhlhwsim_ul_crc_size_t;
+typedef kal_uint16 uhlhwsim_no_frames_t;
+typedef kal_uint16 uhlhwsim_ul_num_trch_t;
+
+typedef kal_uint16 uhlhwsim_dl_tti_t;
+typedef kal_uint16 uhlhwsim_dl_trch_id_t;
+typedef kal_uint32 uhlhwsim_dl_tb_cnt_t;
+typedef kal_uint16 uhlhwsim_dl_tb_size_t;
+typedef kal_uint8 uhlhwsim_dl_tfci_t;
+typedef kal_uint8 uhlhwsim_no_of_trch_t;
+typedef kal_uint8 uhlhwsim_data_t;
+typedef kal_uint16 uhlhwsim_num_data_t;
+typedef kal_uint16 uhlhwsim_cfn_t;
+
+typedef kal_uint8 uhlhwsim_sub_frame_t;
+typedef kal_uint8 uhlhwsim_cqi_t;
+typedef kal_uint16 uhlhwsim_hrnti_t;
+typedef kal_uint32 uhlhwsim_ovsf_t;
+typedef kal_uint8 uhlhwsim_sf_t;
+
+typedef kal_uint8 uhlhwsim_tb_size_index_t; /**< Transport-block size information (6 bits) 25.212 sec 4.6 */
+typedef kal_uint8 uhlhwsim_special_inform_type_t; /**< Special Information type (6 bits) 25.212 sec 4.6A */
+typedef kal_uint8 uhlhwsim_special_inform_t; /**< Special Information (7 bits) 25.212 sec 4.6A */
+
+typedef kal_uint16 uhlhwsim_ul_etfci_t;
+typedef kal_uint8 uhlhwsim_ag_value_t;
+typedef kal_bool uhlhwsim_cqi_valid_t;
+typedef kal_uint8 uhlhwsim_prach_signature_t;
+typedef kal_uint8 uhlhwsim_prach_access_slot_t;
+
+typedef enum
+{
+ UHLHWSIM_NOT_PRESENT = 0,
+ UHLHWSIM_PRESENT = 1
+} uhlhwsim_present_t;
+
+typedef enum
+{
+ UHLHWSIM_FRAME_3G_10MS,
+ UHLHWSIM_FRAME_HSPA_2MS
+} uhlhwsim_frame_duration_t;
+
+typedef enum
+{
+ UHLHWSIM_DISABLED = 0,
+ UHLHWSIM_ENABLED = 1
+} uhlhwsim_trch_enabled_t;
+
+typedef enum
+{
+ UHLHWSIM_DL_CRC_OK = 0,
+ UHLHWSIM_DL_CRC_ERROR = 1
+} uhlhwsim_crc_statuc_t;
+
+
+typedef enum
+{
+ UHLHWSIM_HARQ_NACK = 0,
+ UHLHWSIM_HARQ_ACK = 1
+}uhlhwsim_ack_nack_info_t;
+
+typedef enum
+{
+ UHLHWSIM_HARQ_INVALID = 0,
+ UHLHWSIM_HARQ_VALID = 1
+}uhlhwsim_harq_valid_t;
+
+typedef enum
+{
+ UHLHWSIM_DL_OK_CRC_ERROR = 0,
+ UHLHWSIM_DL_OK_CRC_OK = 1
+} uhlhwsim_crc_ok_statuc_t;
+
+typedef enum
+{
+ UHLHWSIM_HSDPA_SSCH_TYPE1,
+ UHLHWSIM_HSDPA_SSCH_TYPE2,
+ UHLHWSIM_HSDPA_SSCH_TYPE3
+} uhlhwsim_hsdpa_scch_type_t;
+
+typedef enum
+{
+ UHLHWSIM_HSDPA_TYPE_ONE_QPSK,
+ UHLHWSIM_HSDPA_TYPE_ONE_16QAM,
+ UHLHWSIM_HSDPA_TYPE_ONE_64QAM
+} uhlhwsim_hsdpa_mod_schem_type_one_t;
+
+typedef enum
+{
+ UHLHWSIM_HSDPA_TYPE_TWO_QPSK,
+ UHLHWSIM_HSDPA_TYPE_TWO_OTHERWISE
+} uhlhwsim_hsdpa_mod_schem_type_two_t;
+
+
+typedef enum
+{
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_0,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_1,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_2,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_3,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_4,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_5,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_6,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_7,
+ UHLHWSIM_HSDPA_HARQ_PROCESS_ID_INVALID
+} uhlhwsim_hsdpa_harq_process_id_t;
+
+
+
+typedef enum
+{
+ UHLHWSIM_HSDPA__REDUNDAN_VER_0,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_1,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_2,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_3,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_4,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_5,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_6,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_7,
+ UHLHWSIM_HSDPA_REDUNDAN_VER_INVALID
+}uhlhwsim_hsdpa_rv_t;
+
+typedef enum
+{
+ UHLHWSIM_HSDPA_NEW_DATA_TOGGLE_0,
+ UHLHWSIM_HSDPA_NEW_DATA_TOGGLE_1,
+ UHLHWSIM_HSDPA_NEW_DATA_INVALID
+}uhlhwsim_hsdpa_new_data_t;
+
+
+typedef enum {
+ UHLHWSIM_EDCH_INITIAL_TRANS,
+ UHLHWSIM_EDCH_FIRST_RETRANS,
+ UHLHWSIM_EDCH_SECOND_RETRANS,
+ UHLHWSIM_EDCH_SUBSEQUENT_RETRANS
+} uhlhwsim_edch_rsn_t;
+
+
+typedef enum
+{
+ UHLHWSIM_EDCH__NOT_HAPPY = 0, /**< NOT OK!!!! */
+ UHLHWSIM_EDCH__HAPPY = 1 /**< OK :-) */
+} uhlhwsim_edch_happy_bit_t;
+
+typedef enum
+{
+ UHLHWSIM__ALL_HARQ_PROCESSES = 0,
+ UHLHWSIM__PER_HARQ_PROCESS = 1
+} uhlhwsim_ag_scope_t;
+
+
+
+typedef enum
+{
+ UHLHWSIM_EHICH_HARQ_NACK_NON_SERVING = 0,
+ UHLHWSIM_EHICH_HARQ_ACK = 1,
+ UHLHWSIM_EHICH_HARQ_NACK_SERVING = 0xffffffff /* -1 to make ATEC decode */
+} uhlhwsim_harq_indcator_type_t;
+
+
+typedef struct uhlhwsim_sibTag_tag
+{
+ kal_uint32 seg_Rep;
+ kal_uint32 seg_Pos;
+} uhlhwsim_sibTag_t;
+
+typedef struct
+{
+ uhlhwsim_ovsf_t ccs; /**< Channelization-code-set information (7 bits) 25.212 sec 4.6 */
+ uhlhwsim_hsdpa_mod_schem_type_one_t modulation_scheme; /**< Modulation scheme information (1 bit) 25.212 sec 4.6 */
+ uhlhwsim_tb_size_index_t tb_size_index; /**< Transport-block size information (6 bits) 25.212 sec 4.6 */
+ uhlhwsim_hsdpa_harq_process_id_t harq_process_id; /**< Hybrid-ARQ process information (3 bits) 25.212 sec 4.6 */
+ uhlhwsim_hsdpa_rv_t redundancy_ver; /**< Redundancy and constellation version (3 bits) 25.212 sec 4.6 */
+ uhlhwsim_hsdpa_new_data_t new_data; /**< New Data indicator (1 bit) 25.212 sec 4.6 */
+} uhlhwsim_hsdpa_scch_data_type1_t;
+
+typedef struct
+{
+ uhlhwsim_ovsf_t ccs; /**< Channelization-code-set information (7 bits) 25.212 sec 4.6A */
+ uhlhwsim_hsdpa_mod_schem_type_two_t modulation_scheme; /**< Modulation scheme information (1 bit) 25.212 sec 4.6A */
+ uhlhwsim_special_inform_type_t special_info_type; /**< Special Information type (6 bits) 25.212 sec 4.6A */
+ uhlhwsim_special_inform_t special_info; /**< Special Information (7 bits) 25.212 sec 4.6A */
+} uhlhwsim_hsdpa_scch_data_type2_t;
+
+typedef union
+{
+ uhlhwsim_hsdpa_scch_data_type1_t data_type1;
+ uhlhwsim_hsdpa_scch_data_type2_t data_type2;
+} uhlhwsim_hsdpa_scch_data_t;
+
+
+typedef struct uhlhwsim_dl_resource_req_tag
+{
+ /*if num_dl_uarfcn is unknown and set to 0, no matching will be done at the NW and all available UARFCN will be returned */
+ uhlhwsim_num_uarfcn_t num_dl_uarfcn;
+ uhlhwsim_dl_uarfcn_t dl_uarfcn[UHLHWSIM_MAX_DL_UARFCNS];
+} uhlhwsim_dl_resource_req_t;
+
+
+typedef struct uhlhwsim_cell_info_tag
+{
+ uhlhwsim_dl_uarfcn_t dl_uarfcn;
+ uhlhwsim_cell_psc_t psc;
+ uhlhwsim_dl_power_t rssi;
+ uhlhwsim_dl_power_t rscp;
+ uhlhwsim_sfn_t sfn;
+
+
+ struct {
+ uhlhwsim_present_t status_pccpch_present;
+ uhlhwsim_sibTag_t sib_tag_info;
+ uhlhwsim_tb_data_t sib_data[UHLHWSIM_MAX_PCCPCH_DATA_SIZE];
+ } pccpchCnf;
+
+ uhlhwsim_sccpch_num_t no_sccpch;
+
+ struct
+ {
+ uhlhwsim_dl_tfci_t tfci;
+ uhlhwsim_sf_t sf;
+ uhlhwsim_ovsf_t ovsf;
+ uhlhwsim_no_of_trch_t no_of_trch;
+ struct
+ {
+ uhlhwsim_trch_enabled_t status_trch_enabled;
+ uhlhwsim_crc_statuc_t crc_status;
+ uhlhwsim_dl_tti_t tti;
+ uhlhwsim_dl_trch_id_t trch_id;
+ uhlhwsim_dl_tb_cnt_t tb_cnt;
+ uhlhwsim_dl_tb_size_t tb_size;
+ } trch[UHLHWSIM_MAX_TRCH];
+ uhlhwsim_num_data_t num_data;
+ uhlhwsim_data_t data[UHLHWSIM_MAX_DL_DATA_SIZE];
+ } sccpch[UHLHWSIM_MAX_SCCPCH];
+
+ struct
+ {
+ uhlhwsim_dl_tfci_t tfci;
+ uhlhwsim_cfn_t cfn;
+ uhlhwsim_no_of_trch_t no_of_trch;
+ struct
+ {
+ uhlhwsim_trch_enabled_t status_trch_enabled;
+ uhlhwsim_crc_statuc_t crc_status;
+ uhlhwsim_dl_tti_t tti;
+ uhlhwsim_dl_trch_id_t trch_id;
+ uhlhwsim_dl_tb_cnt_t tb_cnt;
+ uhlhwsim_dl_tb_size_t tb_size;
+ uhlhwsim_data_t tb_data[UHLHWSIM_MAX_DL_DATA_SIZE];
+ } trch[UHLHWSIM_MAX_TRCH];
+ } dpch;
+
+} uhlhwsim_cell_info_t;
+
+typedef struct uhlhwsim__rxCellObj_tag
+{
+ uhlhwsim_cell_info_t cell_info;
+} uhlhwsim_rx_cell_obj_t;
+
+typedef struct uhlhwsim_hspa_cell_info_tag
+{
+ uhlhwsim_dl_uarfcn_t dl_uarfcn;
+ uhlhwsim_cell_psc_t psc;
+ uhlhwsim_dl_power_t rssi;
+ uhlhwsim_dl_power_t rscp;
+ uhlhwsim_sfn_t sfn;
+
+ struct
+ {
+ uhlhwsim_present_t status_hsdsch_present;
+ uhlhwsim_sfn_t sfn; //Frame Number
+ uhlhwsim_sub_frame_t sub_frame; //Subframe Number
+
+ uhlhwsim_hrnti_t h_rnti;
+
+
+ uhlhwsim_ovsf_t ovsf;
+ uhlhwsim_hsdpa_scch_type_t hsscch_type; /**< Type of HS-SCCH */
+ uhlhwsim_hsdpa_scch_data_t hsscch_data; /**< Data carried on the HS-SCCH */
+
+ uhlhwsim_crc_ok_statuc_t crc_ok; // True=correct. False=wrong.
+ uhlhwsim_dl_tb_size_t tb_size;
+ uhlhwsim_data_t data[UHLHWSIM_MAX_HS_PDU_SIZE_IN_BYTES];
+ } hsdsch;
+
+ struct
+ {
+ uhlhwsim_present_t status_eagch_present;
+ uhlhwsim_sfn_t sfn; //Frame Number
+ uhlhwsim_sub_frame_t sub_frame; //Subframe Number
+ uhlhwsim_ag_value_t ag_value;
+ uhlhwsim_ag_scope_t ag_scope;
+ uhlhwsim_hsdpa_harq_process_id_t harq_process_id;
+ } eagch;
+
+ struct
+ {
+ uhlhwsim_present_t status_ehich_present;
+ uhlhwsim_harq_indcator_type_t harq_indcator;
+ uhlhwsim_hsdpa_harq_process_id_t harq_process_id;
+ } ehich;
+
+ struct
+ {
+ uhlhwsim_present_t status_fdpch_present;
+ } fdpch;
+
+
+} uhlhwsim_hspa_cell_info_t;
+
+typedef struct uhlhwsim__rxHspaCellObj_tag
+{
+ uhlhwsim_hspa_cell_info_t hspa_cell_info;
+} uhlhwsim_rx_hspa_cell_obj_t;
+
+
+
+typedef struct uhlhwsim_dl_data_tag
+{
+ uhlhwsim_num_cell_obj_t num_cell_obj;
+ uhlhwsim_rx_cell_obj_t cell_obj[UHLHWSIM_MAX_FOUND_CELLS];
+ uhlhwsim_rx_hspa_cell_obj_t hspa_cell_obj[UHLHWSIM_MAX_FOUND_CELLS];
+} uhlhwsim_dl_data_t;
+
+
+typedef struct _uhlhwsim_dl_data_ind_struct
+{
+ uhlhwsim_dl_data_t dl_data;
+} uhlhwsim_dl_data_ind_struct;
+
+
+typedef struct
+{
+ uhlhwsim_ul_uarfcn_t ul_arfcn;
+ uhlhwsim_ul_power_t ul_power;
+ uhlhwsim_cell_psc_t psc;
+ uhlhwsim_ul_tfci_t tfci;
+ uhlhwsim_sfn_t sfn;
+ //uhlhwsim_frame_duration_t frame_duration;
+ uhlhwsim_no_frames_t no_frames;
+ struct
+ {
+ uhlhwsim_ul_trch_id_t trch_id;
+ uhlhwsim_ul_tb_size_t tb_size;
+ uhlhwsim_ul_tb_cnt tb_cnt;
+ uhlhwsim_ul_code_type_t code_type;
+ uhlhwsim_ul_tti_t tti;
+ uhlhwsim_ul_crc_size_t crc_size;
+ uhlhwsim_tb_data_t tb_data[UHLHWSIM_MAX_UL_DATA];
+ } tbs;
+} uhlhwsim_prach_t;
+
+typedef struct
+{
+ uhlhwsim_ul_uarfcn_t ul_arfcn;
+ uhlhwsim_ul_power_t ul_power;
+ uhlhwsim_cell_psc_t psc;
+ uhlhwsim_ul_tfci_t tfci;
+ uhlhwsim_cfn_t cfn;
+ uhlhwsim_cfn_t sfn;
+ //uhlhwsim_frame_duration_t frame_duration;
+ uhlhwsim_ul_num_trch_t num_trch;
+ struct
+ {
+ uhlhwsim_ul_trch_id_t trch_id;
+ uhlhwsim_ul_tb_size_t tb_size;
+ uhlhwsim_ul_tb_cnt tb_cnt;
+ uhlhwsim_ul_tti_t tti;
+ uhlhwsim_tb_data_t tb_data[UHLHWSIM_MAX_UL_DATA];
+ } trch[UHLHWSIM_MAX_TRCH];
+} uhlhwsim_pdpch_t;
+
+typedef struct
+{
+ uhlhwsim_ul_uarfcn_t ul_arfcn;
+ uhlhwsim_cfn_t cfn;
+ uhlhwsim_sub_frame_t sub_frame;
+ uhlhwsim_cqi_valid_t cqi_valid;
+ uhlhwsim_cqi_t primary_cqi_value;
+ uhlhwsim_cqi_t secondary_cqi_value;
+ uhlhwsim_harq_valid_t primary_harq_info_valid;
+ uhlhwsim_ack_nack_info_t primary_harq_info_ind;
+ uhlhwsim_harq_valid_t secondary_harq_info_valid;
+ uhlhwsim_ack_nack_info_t secondary_harq_info_ind;
+}uhlhwsim_hs_dpcch_t;
+
+
+typedef struct
+{
+ uhlhwsim_ul_uarfcn_t prach_ul_arfcn;
+ uhlhwsim_prach_signature_t prach_signature;
+ uhlhwsim_prach_access_slot_t prach_access_slot;
+} uhlhwsim_prach_preamble_t;
+typedef struct
+{
+ uhlhwsim_ul_uarfcn_t ul_arfcn;
+ uhlhwsim_ul_power_t ul_power;
+ uhlhwsim_cfn_t cfn;
+ uhlhwsim_sub_frame_t sub_frame;
+
+ uhlhwsim_edch_happy_bit_t happy_bit;
+ uhlhwsim_edch_rsn_t rsn;
+ uhlhwsim_ul_tti_t tti;
+ uhlhwsim_ul_etfci_t e_tfci;
+ uhlhwsim_ul_tb_size_t tb_size;
+ uhlhwsim_tb_data_t tb_data[UHLHWSIM_MAX_EDCH_TB_SIZE];
+} uhlhwsim_edch_t;
+
+typedef struct
+{
+ uhlhwsim_present_t prach_present;
+ uhlhwsim_prach_t prach_data;
+ uhlhwsim_present_t pdpch_present;
+ uhlhwsim_pdpch_t pdpch_data;
+ uhlhwsim_present_t hs_dpcch_present;
+ uhlhwsim_hs_dpcch_t hs_dpcch_data;
+ uhlhwsim_present_t prach_preamble_present;
+ uhlhwsim_prach_preamble_t prach_preamble;
+
+ uhlhwsim_present_t edch_present;
+ uhlhwsim_edch_t edch_data;
+} uhlhwsim_tx_cell_obj_t;
+
+
+typedef struct uhlhwsim_ul_data_tag
+{
+ uhlhwsim_num_cell_obj_t num_cell_obj;
+ uhlhwsim_tx_cell_obj_t cell_obj[UHLHWSIM_MAX_UL_CELLS];
+} uhlhwsim_ul_data_t;
+
+
+typedef struct _uhlhwsim_ul_data_req_struct
+{
+ uhlhwsim_ul_data_t ul_data;
+} uhlhwsim_ul_data_req_struct;
+
+#endif /* _UHLHWSIM_STRUCT_H */
diff --git a/mcu/interface/l1/ul1/internal/ul1_cnst.h b/mcu/interface/l1/ul1/internal/ul1_cnst.h
new file mode 100644
index 0000000..1b4fab3
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ul1_cnst.h
@@ -0,0 +1,485 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_cnst.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * Layer 1 related constant and enum definitions for MediaTek WCDMA software
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _UL1_CNST_H
+#define _UL1_CNST_H
+
+#include "ul1_protected_cnst.h"
+
+#define UL1_SIM_IDX_INVALID ( 0xFF )
+
+/*-------- BCH related constant ----------------------*/
+#define FDD_MAX_SIB_PATTERN 31 /* The maximum number of BCH SIB blocks */
+#define FDD_MAX_SIB_SEG_COUNT 16 /* The maximum number of segments in 1 BCH SIB */
+
+/*-------- TrCH related constant (For UL/DL 384Kbps capability) ----------------------*/
+/* MAUI_02850564 : According to spec 25.306 and MTK implementation, FDD_MAX_DL_DATA should be 956 bytes :
+ FDD_MAX_DL_DATA = 6400 + 24*32 (CRC bits*MaxTBNum) + 7*32 (max bit offset for each TB)
+ + 7*32 (max byte alignment for each TB) + 4*8 (4 bytes report header) = 7648 bits = 956 bytes.
+ But we have seen an overspec case : PS TrCH 336*24 + SRB TrCH 148*1, thus define FDD_MAX_DL_DATA as 1150 bytes.
+ FDD_MAX_DL_DATA = [PS part] 336*24 + 24*24 + 7*24 + 7*24
+ [SRB part] + 148*1 + 24*1 + 7*1 + 7*1
+ + 4*8 (4 bytes report header) = 9194 bits = 1149.25 bytes. */
+#define FDD_MAX_DL_DATA 1150 /* Maximum DL transport block array size. */
+#define FDD_MAX_TRCH_NUM 8 /* Maximum Simultaneous TrCHs */
+#define FDD_MAX_DL_TB 32 /* Maximum simultaneous DL TBs */
+#define FDD_MAX_DL_TFC 128 /* Maximum number of TFCs per DL CCTrCH */
+#define FDD_MAX_DL_TRCH 32 /* Maximum number of DL TrCH */
+#define FDD_MAXTF 32 /* Maximum number of TF per UL or DL TrCH TFS */
+#define FDD_MAXFACHPCH 8 /* Maximum number of TrCHs per S-CCPCH CCTrCH */
+#define FDD_MAX_UL_TFC 64 /* Maximum number of TFCs per UL CCTrCH */
+#define FDD_MAX_UL_TB 16 /* Maximum simultaneous DUL TBs */
+#define FDD_MAX_UL_TFs 32 /* Maximum numbre of TFs per UL CCTrCH */
+#define FDD_MAX_UL_TRCH 32 /* Maximum number of UL TrCH */
+
+/*-------- PhyCh related constant (For UL/DL 384Kbps capability) ----------------------*/
+#define FDD_MAX_TGPS 6 /* Maximum number of TGPS sequences */
+#define FDD_MAX_PENDING_TGPS_NUM 5 /* Maximum number of pending confiuration for one TGPS */
+#define FDD_MAX_TGMP_NUM 5 /* Maximum number of TGMP */
+#define FDD_MAX_ASC 8 /* Maximum access service class number */
+#define FDD_MAX_DLDPCH 3 /* Maximum number of physical channel codes per DL DPCH CCTrCH */
+#define FDD_MAX_ULDPCH 6 /* Maximum number of physical channel codes per UL DPCH CCTrCH */
+#define FDD_MAX_RL 8 /* Maximum number of DPCH radio links in active set */
+
+#ifdef __UMTS_R10__
+
+#ifdef __MULTI_CARRIER_HSDPA__ /* __MULTI_CARRIER_HSDPA__ = 3 or 4 */
+#define FDD_MAX_ADDI_DC_HSDPA ( __MULTI_CARRIER_HSDPA__ - 2 ) /* [R10] The maximum additional dc-hsdpa frequency */
+#else /*__MULTI_CARRIER_HSDPA__*/
+#define FDD_MAX_ADDI_DC_HSDPA 1 /* default value is 1. */
+#endif /*__MULTI_CARRIER_HSDPA__*/
+
+#endif
+
+
+
+/*-------- Measurement related constant ----------------------*/
+#ifdef __GEMINI__
+#define FDD_MAX_FREQ_RANGE 15 /* Max size of frequency ranges for frequency scan.
+ Extend range number for Enhanced Freq Scan in Gemini2.0.*/
+#else
+#define FDD_MAX_FREQ_RANGE 8 /* Max size of frequency ranges for frequency scan. */
+#endif /*__GEMINI__*/
+
+#define FDD_MAX_FREQ_EXCLUDE 13 /*Max possible UARFCNs per PLMN*/
+#define FDD_MAX_FREQ_LIST 36 /* Max size of stored frequency list for frequency scan */
+#define FDD_MAX_PREFERRED_PSC 96 /* Max number of preferred cells on 1 frequency for frequency scan */
+#define FDD_MAX_NUM_MEAS_CELL 32 /* Max number of reported cells in the measurement cell indication primitive */
+#define FDD_MAX_NUM_MEASURED_CELL 96 /* Max number of monitored cells in the measurement cell request primitive */
+#define FDD_MAX_NUM_SFN_CELL 12 /* Max number of cells whose SFN will be read by L1 when nc_nbr_dch=0 */
+
+#ifdef __UMTS_R9_UL1__
+#define FDD_MAX_UMTS_FREQ 4 /* Maximum number of FDD frequency supported in a UMTS UE : 1st intra + 2nd intra + inter x 2 */
+#else
+#define FDD_MAX_UMTS_FREQ 3 /* Maximum number of FDD frequency supported in a UMTS UE */
+#endif /*__UMTS_R9_UL1__*/
+
+#define FDD_MAX_RSSI_SNIFFER_SCAN_LIST 12 /* Maximum number of RSSI SNIFFER UARFCN (Add by Janet) */
+
+/*-------- Magic value related constant ----------------------*/
+#define FDD_TM_VALID 307200 /* Default value representing Tm known. 38400*8 */
+#define FDD_TM_INVALID ( -1 ) /* Default value representing Tm unknown. */
+#define FDD_OFF_VALID 4096 /* Default valure representing OFF known. */
+#define FDD_OFF_INVALID ( -1 ) /* Default value representing OFF unknown. */
+#define FDD_RSSI_INVALID ( -32768 ) /* Default value representing RSSI unknown. */
+#define FDD_RSCP_INVALID ( -32768 ) /* Default value representing RSCP unknown. */
+#define FDD_ECN0_INVALID ( -32768 ) /* Default value representing EcNo unknown. */
+#define FDD_UARFCN_INVALID 65535 /* Invalid UARFCN for setting empty freq. entry in meas. config req. */
+
+
+
+
+/*-------- BMC (CTCH) related constant ----------------------*/
+#define FDD_BMC_MAX_BITMAP_SIZE 64 /* CTCH level 2 bitmap siz */
+
+/*-------- Activation time related constant ----------------------*/
+#define FDD_CFN_IMMEDIATE (kal_int16)(-1) /* Immediate CFN activation time. */
+#define FDD_SFN_IMMEDIATE (kal_int16)(-1) /* Immediate SFN activation time. */
+
+/*-------- [R5R6] HS-DSCH related ----------------------*/
+#ifdef __MULTI_CARRIER_HSDPA__
+#define FDD_MAX_SUPPORT_CELL __MULTI_CARRIER_HSDPA__ /* Possible __MULTI_CARRIER_HSDPA__ value is 3,4 or not defined. */
+#else
+#define FDD_MAX_SUPPORT_CELL 2 /* 1 */ /*Use 3 before __MULTI_CARRIER_HSDPA__ defined in project for easy development*/
+#endif
+
+#define FDD_MAX_HS_SCCH_NUM 4
+#define FDD_MAX_HS_PROCESS_NUM 8
+#define FDD_MAX_HS_PDU_NUM_IN_FRAME 5
+#ifdef __UMTS_R7__
+#define FDD_MAX_HS_PDU_SIZE_IN_BITS 42192
+#else
+#define FDD_MAX_HS_PDU_SIZE_IN_BITS 14411
+#endif
+#define FDD_MAX_HS_PDU_SIZE_IN_BYTES (((FDD_MAX_HS_PDU_SIZE_IN_BITS+32+31)/32)*4)
+#ifdef __UMTS_R8__
+
+#define FDD_HDA_BUFF_NUM_PRI 45 // 5*8(MAX flow B * HARQ process NUM) + 5 (less mode)
+#define FDD_HDA_BUFF_NUM_SEC 8 // HARQ process NUM
+
+#define FDD_MAX_HS_PDU_BUFF_NUM 160 // for DC hsdpa
+#define FDD_HDA_BUFF_NUM (FDD_HDA_BUFF_NUM_PRI + FDD_HDA_BUFF_NUM_SEC * (FDD_MAX_SUPPORT_CELL-1))
+#else
+#define FDD_MAX_HS_PDU_BUFF_NUM 40
+#endif
+#define FDD_MAX_HS_RB_NUM 3
+#define FDD_MAX_EDCH_RL 4
+#define FDD_MAX_REF_ETFCI_NUM 8
+#define FDD_MAX_ETFC_NUM 128
+#define FDD_MIN_NTX1_10MS 8 /* 25.212 s4.4.4 */
+#define FDD_MAX_NTX1_10MS (15 - FDD_MIN_NTX1_10MS + 1)
+
+#define FDD_HS_PDU_UL1_CC_DELAY_PREALLOCATION_NUM (FDD_MAX_SUPPORT_CELL*5)
+#define FDD_PHY_HSDSCH_MAC_EV_SETUP_BIT 0
+#define FDD_PHY_HSDSCH_MAC_EV_RELEASE_BIT 1
+#define FDD_PHY_HSDSCH_MAC_EV_MODIFY_BIT 2
+#define FDD_PHY_HSDSCH_MAC_EV_RESET_BIT 3
+#define FDD_PHY_HSDSCH_MAC_EV_SETUP (0x1 << FDD_PHY_HSDSCH_MAC_EV_SETUP_BIT) /* 0x01 */
+#define FDD_PHY_HSDSCH_MAC_EV_RELEASE (0x1 << FDD_PHY_HSDSCH_MAC_EV_RELEASE_BIT) /* 0x02 */
+#define FDD_PHY_HSDSCH_MAC_EV_MODIFY (0x1 << FDD_PHY_HSDSCH_MAC_EV_MODIFY_BIT) /* 0x04 */
+#define FDD_PHY_HSDSCH_MAC_EV_RESET (0x1 << FDD_PHY_HSDSCH_MAC_EV_RESET_BIT) /* 0x08 */
+
+/*-----------Add PLMN , RAC and LAC info to Container Req---------------------------*/
+#define NUM_PLMN_INFO 3
+#define NUM_MCC_MNC 3
+
+#endif
+
diff --git a/mcu/interface/l1/ul1/internal/ul1_def.h b/mcu/interface/l1/ul1/internal/ul1_def.h
new file mode 100644
index 0000000..f0a76b0
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ul1_def.h
@@ -0,0 +1,2795 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_def.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * This file contains common typedef, definition prototypes exported by L1
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _UL1_DEF_H
+#define _UL1_DEF_H
+
+/* auto add by kw_check begin */
+#include "ul1_cnst.h"
+#include "kal_general_types.h"
+/* auto add by kw_check end */
+
+#include "gmss_public.h"
+#include "ul1_protected_def.h"
+
+
+/* ---------------------- L+W Gemini ----------------------*/
+typedef enum _UL1_SIM_INDEX_E
+{
+ UL1_SIM_1 = 0,
+#ifdef __GEMINI_WCDMA__
+ UL1_SIM_2,
+#if (GEMINI_PLUS_WCDMA >= 3)
+ UL1_SIM_3,
+#if (GEMINI_PLUS_WCDMA >= 4)
+ UL1_SIM_4,
+#endif /* GEMINI_PLUS_WCDMA >= 4 */
+#endif /* GEMINI_PLUS_WCDMA >= 3 */
+#endif /* __GEMINI_WCDMA__ */
+ UL1_SIM_NUM
+} UL1_SIM_INDEX_E;
+
+#if (GEMINI_PLUS_WCDMA > 4)
+#error "The number of SIM can't be over than 4 pieces."
+#endif
+
+/*-------------------- ADT -----------------------*/
+typedef enum _FDD_ADT_Mode_E
+{
+ FDD_ADT_NONE = 0,
+ FDD_ADT_NORMAL,
+ FDD_ADT_TALKING
+} FDD_ADT_Mode_E;
+
+/*-------- TGPS related definition ----------------------*/
+typedef enum _FDD_tgps_act_E
+{
+ FDD_TGPS_ACTIVATE, /* Activate the TGPS */
+ FDD_TGPS_DEACTIVATE /* Deactivate the TGPS */
+} FDD_tgps_act_E;
+
+typedef enum _FDD_tg_mode_E
+{
+ FDD_TG_UL, /* UL only */
+ FDD_TG_DL, /* DL only */
+ FDD_TG_UL_DL /* Both UL and DL */
+} FDD_tg_mode_E;
+
+typedef enum _FDD_tgmp_E
+{
+ FDD_TG_FDD_MEASURE, /* Inter-frequency measurement */
+ FDD_TG_GSM_RSSI, /* GSM RSSI measurement */
+ FDD_TG_GSM_BSIC_INIT, /* GSM initial BSIC */
+ FDD_TG_GSM_BSIC_CNF, /* GSM BSIC confirm */
+ FDD_TG_EUTRA, /* E-UTRA */
+ FDD_TG_TGMP_UNDEFINED
+} FDD_tgmp_E;
+
+typedef enum _FDD_tg_method_E
+{
+ FDD_TG_PUNCT, /* Puncturing. only for DL */
+ FDD_TG_HLS, /* Higher layer scheduling */
+ FDD_TG_SF_2, /* SF/2 */
+ FDD_TG_NONE /* None */
+} FDD_tg_method_E;
+
+typedef struct _FDD_tgps_info_T
+{
+ kal_uint8 tgpsi; /* TGPSI. 1 ~ 6 */
+ kal_uint8 tgcfn; /* TGCFN. 0 ~ 255 */
+ FDD_tgps_act_E status; /* Action applied to TGPS */
+ kal_bool tgps_para_valid; /* indicate if following parameter should be modifed */
+ FDD_tgmp_E purpose; /* TGMP. TGPS purpose */
+ FDD_tg_mode_E mode; /* TG mode */
+ FDD_tg_method_E ul_method; /* UL TG method */
+ FDD_tg_method_E dl_method; /* DL TG method */
+ kal_uint8 rpp; /* RPP. 0 or 1 */
+ kal_uint8 itp; /* ITP. 0 or 1 */
+ kal_uint8 dl_frame_type; /* DL TG frame type. 0 : type A. 1 : type B */
+ kal_uint8 sir1; /* DeltaSIR1. 0 ~ 30. true value is sir1/10 */
+ kal_uint8 sir_after1; /* DeltaSIRafter1. 0 ! 10. true value is sir_after1/10 */
+ kal_uint8 sir2; /* DeltaSIR1. 0 ~ 30. true value is sir2/10 */
+ kal_uint8 sir_after2; /* DeltaSIRafter1. 0 ! 10. true value is sir_after2/10 */
+ kal_uint16 tgprc; /* TGPRC. 0 ~ 511. 0 for infinity*/
+ kal_uint8 tgsn; /* TGSN. 0 ~ 14 */
+ kal_uint8 tgl1; /* TGL1. 1 ~ 14 slts */
+ kal_uint8 tgl2; /* TGL2. 1 ~ 14 slts */
+ kal_uint16 tgd; /* TGD. 15 ~ 270. 270 means TGD is undefed (only 1 TG) */
+ kal_uint8 tgpl1; /* TGPL1. 1 ~ 144 */
+ kal_uint8 tgpl2; /* TGPL2. 1 ~ 144 */
+ kal_uint8 ident_abort; /* N_IDENTIFY_ABORT. 1 ~ 128 */
+ kal_uint8 reconf_abort; /* Treconfirm_abort. 1 ~ 20. true value is divided by 2 */
+ kal_bool freq_specific_compressed_mode; /* [R10] true: tgps is not applied on serving band. */
+} FDD_tgps_info_T;
+
+typedef enum _FDD_tgps_status_E
+{
+ FDD_TGPS_ACTIVE,
+ FDD_TGPS_DEACTIVE
+} FDD_tgps_status_E;
+
+typedef struct _FDD_tgps_status_T
+{
+ kal_uint8 tgpsi; /* TGPS index */
+ kal_uint8 tgcfn; /* TGCFN. 0 ~ 255 */
+ FDD_tgps_status_E status; /* Status to be applied to TGPS */
+ kal_bool freq_specific_compressed_mode; /* [R10] true: tgps is not applied on serving band. */
+} FDD_tgps_status_T;
+
+typedef struct _FDD_tgps_status_info_T
+{
+ kal_uint8 num_tgps; /* # of TGPS status pattern */
+ kal_int16 reconf_time; /* TGPS reconfiguration CFN. -1 ~ 255. -1 means immediate */
+ FDD_tgps_status_T tgps_status[FDD_MAX_TGPS]; /* TGPS status information */
+} FDD_tgps_status_info_T;
+
+
+typedef struct _FDD_tgps_config_T
+{
+ kal_uint8 tgpsi; /* tgpsi */
+ FDD_tgmp_E tgmp; /* purpose of this tgpsi */
+ FDD_tgps_status_E status; /*tgps status at the activation time*/
+} FDD_tgps_config_T;
+
+typedef struct _FDD_p_tgps_config_T
+{
+ kal_int16 sfn; /* reconfig time of this pending tgps configuration*/
+ kal_uint8 tgps_num; /* number of tgps in this pneding tgps */
+ FDD_tgps_config_T tgps[FDD_MAX_TGPS]; /* tgps config (tgpsi, tgmp, status) */
+} FDD_p_tgps_config_T;
+
+typedef struct _FDD_tgps_config_by_tgmp_T
+{
+ kal_uint8 tgpsi; /* tgpsi for the tgmp */
+ kal_uint8 p_tgps_config_num; /* pending tgps_config num of this tgpsi */
+ kal_bool c_tgps_config_valid; /* existence of current tgps_config of this tgpsi,
+ if false, c_tgps_config is meaningless */
+ FDD_tgps_config_T c_tgps_config; /* current tgps_config of this tgpsi */
+ FDD_tgps_config_T p_tgps_config[FDD_MAX_PENDING_TGPS_NUM]; /* pending tgps config of this tgpsi */
+} FDD_tgps_config_by_tgmp_T;
+
+typedef enum _FDD_tgps_time_relationship_E
+{
+ FDD_TGPS_BEFORE,
+ FDD_TGPS_EQUAL,
+ FDD_TGPS_AFTER
+} FDD_tgps_time_relationship_E;
+
+typedef enum _FDD_tgps_complete_status_E
+{
+ FDD_TGPS_COMPLETE_OR_INACTIVE,
+ FDD_TGPS_NOT_COMPLETE
+} FDD_tgps_complete_status_E;
+
+typedef struct _FDD_tgps_complete_status_by_tgmp_T
+{
+ kal_int16 sfn; /*activation time or TGPS reconfiguration SFN,
+ range: -1-4095, -1 means immediate(only used in current tgps config)*/
+
+ FDD_tgps_complete_status_E tgps_complete_status; /* tgps complete status for that tgpsi*/
+} FDD_tgps_complete_status_by_tgmp_T;
+
+typedef struct _FDD_tgps_status_by_tgmp_T
+{
+ kal_uint8 tgmp_num; /* num of valid tgmp in the structure */
+ FDD_tgmp_E tgmp[FDD_MAX_TGMP_NUM]; /* tgmp queried */
+ kal_bool status[FDD_MAX_TGMP_NUM]; /* TRUE: if there is current or pending active and incompleted tgps for that tgmp */
+} FDD_tgps_status_by_tgmp_T;
+
+
+/* U3G */
+typedef struct _FDD_tgps_info_share_memory_T
+{
+ kal_uint8 tgpsi; /* tgpsi */
+ FDD_tgmp_E tgmp; /* purpose of this tgpsi */
+ FDD_tgps_status_E status; /* tgps status at the activation time*/
+ FDD_tgps_complete_status_E complete_status;
+} FDD_tgps_info_share_memory_T;
+
+typedef struct _FDD_tgps_param_share_memory_T
+{
+ kal_int16 sfn; /* reconfig time of this pending tgps configuration*/
+ kal_uint8 tgps_info_num; /* number of tgps in this pneding tgps */
+ FDD_tgps_info_share_memory_T tgps_info[FDD_MAX_TGPS]; /* tgps config (tgpsi, tgmp, status) */
+} FDD_tgps_param_share_memory_T;
+
+typedef struct _FDD_tgps_status_share_memory_T
+{
+ kal_uint8 tgps_param_num;
+ FDD_tgps_param_share_memory_T tgps_param[FDD_MAX_TGPS];
+} FDD_tgps_status_share_memory_T;
+/* U3G */
+
+/*-------- PhyCH related definition ----------------------*/
+typedef struct _FDD_pich_drx_T
+{
+ kal_uint8 pch_drx; /* DRX cycle length coefficient. 3 ~ 9 */
+ kal_uint8 pi_num; /* # of PI per frame. 18, 36, 72, 144 */
+ kal_uint8 pi; /* Paging Indicator index. */
+ kal_uint16 sfn_po; /* SFN of the frame containing start of PICH for the first paging occasion. */
+} FDD_pich_drx_T;
+
+#ifdef __SMART_PAGING_3G_FDD__
+typedef struct _FDD_pich_smartpaging_T
+{
+ kal_bool support_repeat; /* If true: RRCE has detected that current NW can support smart paging (has repeated paging pattern) */
+ kal_uint16 sfn_po; /* DRX parameters for PICH.(when smartpging active) */
+} FDD_pich_smartpaging_T;
+#endif
+
+typedef enum _FDD_pich_reconfig_type_E
+{
+ FDD_PCH_MODIFY, /* traditionaly PCH modify */
+ FDD_PCH_SMARTPAGE, /* to inform UL1 enable/disable SmartPaging*/
+} FDD_pich_reconfig_type_E;
+
+typedef struct _FDD_pich_info_T
+{
+ kal_bool sttd; /* If STTD is used. */
+ kal_int8 cpich_tx_power; /* CPICH TX power. -10~50 dBm */
+ kal_int8 power_offset; /* PICH power offset to CPICH. -10 ~ 5 dB */
+ kal_uint8 ovsf; /* Channelization code. 0 ~ 255 */
+ FDD_pich_drx_T pich_drx; /* DRX parameters for PICH. */
+#ifdef __SMART_PAGING_3G_FDD__
+ FDD_pich_smartpaging_T smartpaging_info;
+#endif
+#ifdef __UMTS_R7__
+ FDD_pich_drx_T pich_drx_cycle2; /* DRX parameters 2 for PICH. */
+ kal_uint16 drx_cycle2_time; /* if it's not 0. UL1 shall use pich_drx_2 for PICH receptin, else shall directly use pich_drx for PICH reception. 0~5120 ms */
+#endif /* __UMTS_R7__ */
+} FDD_pich_info_T;
+
+typedef struct _FDD_ctch_drx_level1_T
+{
+ kal_uint8 m_tti;
+ kal_uint8 start_off; /* Offset of the start of first block set k. */
+ kal_uint16 repe_period; /* Block set repetition period. */
+ kal_uint16 bmc_sm_period; /*[R6] Period of BMC scheduling message (P)
+ [Value] 1, 8, 16, 32, 64, 128, 256
+ If this value is set to 1, UL1 will receive CTCH in all CTCH allocation.
+ For R5 and R99, or for R6 but this field is not configured by the network, this value should be set to 1 */
+} FDD_ctch_drx_level1_T;
+
+typedef struct _FDD_ctch_drx_level2_T
+{
+// kal_uint8 bs_mask[32];
+// kal_uint16 bs_mask_len; /* 1 ~ 256 */
+ kal_uint8 level2_bitmap[FDD_BMC_MAX_BITMAP_SIZE];
+ kal_uint16 lenOfBitmap;
+ kal_uint8 bitmapOffset;
+ kal_uint16 sfnOfLastScheduleMsg;
+ kal_bool flush_l2;
+} FDD_ctch_drx_level2_T;
+
+typedef union _FDD_ctch_drx_level
+{
+ FDD_ctch_drx_level1_T drx_level1; /* CTCH DRX Level 1 information. */
+ FDD_ctch_drx_level2_T drx_level2; /* CTCH DRX Level 2 information. */
+} FDD_ctch_drx_level;
+
+typedef struct _FDD_ctch_drx_T
+{
+ kal_bool level1_Ind; /* True: CTCH level 1 parameters is used. */
+ FDD_ctch_drx_level ctch_drx_level; /* CTCH DRX level parameters */
+} FDD_ctch_drx_T;
+
+typedef union _FDD_pich_ctch_info_T
+{
+ FDD_ctch_drx_T ctch_drx; /* CTCH DRX information */
+ FDD_pich_info_T pich_info; /* PICH information */
+} FDD_pich_ctch_info_T;
+
+typedef struct _FDD_sccpch_info_T
+{
+ kal_uint8 ssc; /* Secondary scrambling code. 0 ~ 15 */
+ /* This value will not be used, if SCCPCH is used to carrying PCH */
+ /* if the value is equal to 0, it means primary scrambling code is used */
+ kal_bool sttd; /* True if STTD is used */
+ kal_bool pilot_exit; /* If pilot symbol exists */
+ kal_bool tfci_exit; /* If TFCI is used. */
+ kal_bool fixed_pos_ind; /* If Fixed or flexible position is used. True means Fixed */
+ kal_uint16 timing_offset; /* Frame boundary to P-CCPCH. 0 ~ 38144 by step of 256. */
+ kal_uint16 sf; /* Spreading Factor. 4 ~ 256 */
+ kal_uint16 ovsf; /* Channelization code. 0 ~ sf-1 */
+} FDD_sccpch_info_T;
+
+typedef enum _FDD_access_status_E
+{
+ FDD_AI_ACK, /* Network ACK in AICH */
+ FDD_AI_NACK, /* Network NACK in AICH */
+ FDD_AI_NOACK, /* Network no response in AICH*/
+ FDD_AI_ABORT, /* Aborted by higher layer */
+ FDD_AI_PARAMERROR, /* Access request without preliminary Data request */
+ FDD_AI_NESTEDREQUEST /* Access request before previous one finished */
+} FDD_access_status_E;
+
+typedef struct _FDD_aich_info_T
+{
+ kal_int8 power_offset; /* Power offset to CPICH. -22 ~ 5 dB */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 255*/
+ kal_bool sttd; /* Indicate if STTD is used */
+ kal_uint8 tx_timing; /* AICH transmission timie. 0 or 1 */
+} FDD_aich_info_T;
+
+typedef struct _FDD_asc_T
+{
+ kal_uint8 avail_sig_start; /* Available signature start index */
+ kal_uint8 avail_sig_end; /* Available signature end index */
+ kal_uint8 assigned_subchannel; /* Assigned subchannel number */
+ /* Bit0 represent bit b0, only 4 rightmost bit is valid */
+} FDD_asc_T;
+
+typedef struct _FDD_prach_info_T
+{
+ kal_uint16 min_sf; /* Min allowed SF. 32,64,128,256 */
+ kal_uint8 punc_limit; /* Puncturing limit. 40 ~ 100 */
+ kal_uint8 asc_num; /* # of valid ASC information in asc[]. 1 ~ 8 */
+ kal_uint8 pream_psc; /* Preamble scrambling code. 0 ~ 15 */
+ kal_uint16 avail_signature; /* Available signature. Bit string (16) */
+ /* Bit0 represent signature 0 */
+ kal_uint16 avail_subchannel; /* Available subchannels. Bit string (12)*/
+ /* Bit0 represent sub-channel 0 */
+ FDD_asc_T asc[FDD_MAX_ASC]; /* ASC information */
+} FDD_prach_info_T;
+
+typedef struct _FDD_prach_power_T
+{
+ kal_int8 max_tx_power; /* Max allowed TX power. -50 ~ 33dBm */
+ kal_int8 umts_power_class; /* UE capability*/
+ kal_int8 init_power_offset; /* SUM of "P-CPICH TX power" and "constant value" */
+ /* L1 will use this offste - CPICH_RSCP - UL_INTERFERENCE */
+ kal_uint8 power_step; /* Preamble power ramping step. 1 ~ 8dB */
+ kal_uint8 retrans_max; /* Max preamble retrans. 1 ~ 64 */
+} FDD_prach_power_T;
+
+typedef struct _FDD_ul_pc_info_T
+{
+ kal_uint8 pc_pream; /* Power control Preamble. 0 ~ 7 frames */
+ kal_uint8 pc_algo; /* Power control algorithm. 1 or 2; inherited from primary for secondary ul freq */
+ kal_uint8 tpc_step; /* Power control step size. 1 or 2dB */
+ /* This is only valid for pc_algo = 1; inherited from primary for secondary ul freq */
+ kal_int16 dpcch_power_offset; /* DPCCH initial power offset. -164 ~ 6 dBm */
+} FDD_ul_pc_info_T;
+
+typedef enum _FDD_sc_type_E
+{
+ FDD_SC_SHORT, /* Short type scrambling code */
+ FDD_SC_LONG /* Long type scrambling code */
+} FDD_sc_type_E;
+
+typedef struct _FDD_ul_dpch_info_T
+{
+ FDD_ul_pc_info_T ul_pc; /* UL power control info */
+ FDD_sc_type_E sc_type; /* Type of scrambling code */
+ kal_uint32 sc_code; /* Scrambling code #. 0 ~ 16777215 */
+ kal_uint8 ul_dpch_num; /* # of UL DPDCH. 0 ~ FDD_MAX_ULDPCH; ignored by secondary ul freq */
+ kal_uint16 min_sf; /* Min SF. 4,8,16,32,64,128,256; ignored by secondary ul freq */
+ kal_bool tfci_exist; /* Indicate if TFCI exists; inherited from primary for secondary ul freq */
+ kal_uint8 fbi_num; /* # of FBI bits. 0, 1, 2; inherited from primary for secondary ul freq */
+ kal_uint8 punc_limit; /* Puncture limit. 40 ~ 100 in step 4; ignored by secondary ul freq */
+ /* The acture PM = punc_limit/100; ignored by secondary ul freq */
+#ifdef __UMTS_R7__
+ kal_uint8 tpc_bit_num; /* # of TPC bits. 2, 4; inherited from primary for secondary ul freq */
+#endif /* __UMTS_R7__ */
+} FDD_ul_dpch_info_T;
+
+/*-------- TFS related definition ----------------------*/
+typedef enum _FDD_cc_type_T
+{
+ FDD_CC_NONE,
+ FDD_CC_CONV12,
+ FDD_CC_CONV13,
+ FDD_CC_TURBO,
+ FDD_CC_TOTAL
+} FDD_cc_type_T;
+
+typedef struct _FDD_tfs_static_T
+{
+ kal_uint8 tti; /* TTI. # of frames, 1, 2, 4, 8 */
+ FDD_cc_type_T channel_coding; /* Coding type */
+ kal_uint8 rm_attr; /* RM attribute */
+ kal_uint8 crc_size; /* # of CRC bits. 0,8,12,16,24 */
+} FDD_tfs_static_T;
+
+typedef struct _FDD_tfs_dyn_T
+{
+ kal_uint8 tb_num; /* # of TB */
+ kal_uint16 tb_size; /* # of bibts in a TB */
+} FDD_tfs_dyn_T;
+
+typedef struct _FDD_tfs_T
+{
+ kal_uint8 tf_num; /* # of TF in this TFS */
+ FDD_tfs_dyn_T tfs_dynamic[FDD_MAXTF]; /* TFS dynamic part */
+ FDD_tfs_static_T tfs_static; /* TFS static part */
+} FDD_tfs_T;
+
+typedef enum _FDD_tx_diversity_E
+{
+ FDD_DL_TX_NONE = 0, /* No TX diversity */
+ FDD_DL_TX_STTD = 1, /* STTD */
+ FDD_DL_TX_CLM1 = 2, /* Closed loop mode 1 */
+ FDD_DL_TX_CLM2 = 3 /* Closed loop mode 2 */
+
+} FDD_tx_diversity_E;
+
+typedef enum _FDD_cws_len_E
+{
+ FDD_SSDT_LONG, /* Long code word */
+ FDD_SSDT_MEDIUM, /* Medium code word */
+ FDD_SSDT_SHORT, /* Short code word */
+ FDD_SSDT_OFF /* SSDT is off */
+
+} FDD_cws_len_E;
+
+typedef struct _FDD_ssdt_conf_T
+{
+ kal_uint8 s_field; /* # of s bits. 1 or 2 */
+ FDD_cws_len_E cws_len; /* Code word set length */
+} FDD_ssdt_conf_T;
+
+typedef enum _FDD_dpch_type_E
+{
+ FDD_DPCH_TYPE = 0,
+ FDD_FDPCH_TYPE = 1,
+ /* __UMTS_R7__ BEGIN */
+ FDD_NO_DPCH_TYPE
+ /* __UMTS_R7__ END */
+} FDD_dpch_type_E;
+
+typedef struct _FDD_dl_dpch_rla_T
+{
+ kal_uint8 dpc_mode; /* DL Power control mode. 0 or 1 or 2 */
+ kal_uint8 pilot_power_offset; /* Ppilot - Pdpdch. 0 ~ 24dB */ /*[R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint16 sf; /* SF. 4,8,16,32,64,128,256,512 */ /*[R6] For F-DPCH, UL1 doesn't care this value */
+ kal_bool fixed_pos; /* Fixed or flexible position. True = Fixed */ /*[R6] For F-DPCH, UL1 doesn't care this value */
+ kal_bool tfci_exist; /* Indicate if TFCI exist */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint8 pilot_num; /* # of pilot bits. 2,4,8,16 */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint8 tgps_num; /* # of TGPS in the list. 0 ~ 6 */
+ FDD_tgps_info_T tgps_info[FDD_MAX_TGPS]; /* TGPS list */
+ FDD_tx_diversity_E tx_diversity; /* TX diversity mode */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ FDD_ssdt_conf_T ssdt_conf; /* SSDT configuration */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_int32 doff; /* Default DPCH offset value. -1 ~ 306688 */
+ /* -1 is an invalid value */
+
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rl */
+ kal_uint8 tpc_target; /* [R6] F-DPCH only, range: 1~10, the actual TPC command error rate target is tpc_target/100 */
+} FDD_dl_dpch_rla_T;
+
+typedef struct _FDD_dldpch_code_T
+{
+ kal_uint8 ssc; /* Scrambling code # for this code channel */
+ /* 0 ~ 15. 0 for "the same scrambling code for the P-CPICH */
+ kal_uint16 sf; /* 4,8,16,32,64,128,256,512 */
+ kal_uint16 ovsf; /* OVSF code. 0 ~ SF-1 */
+ kal_bool sc_change; /* True : Changed scrambling code is used */
+} FDD_dldpch_code_T;
+
+typedef struct _FDD_dl_dpch_rl_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */
+ /* If the value of tm is not equal to -1, UL1 will use this value */
+ /* If the value of tm is equal to -1, UL1 will not use this value */
+ kal_int32 tm; /* Cell boundary to LST. -1 ~ 38400*8-1 */
+ kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell */
+ kal_bool pcpich_usage; /* Indicate if P-CPICH can be used for channel estimation */
+ /* KAL_TRUE means P-CPICH could be used */
+ kal_int8 scpich_ssc; /* Scrambling code of S-CPICH. */
+ /* -1 ~ 15. 0 means use primary scramblign code */
+ /* -1 means there is not S-CPICH */
+ kal_uint8 scpich_ovsf; /* OVSF code. 0 ~ 255 */
+ kal_bool tx_diversity_disable; /* Indicate if TX diversity is used */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ /* True means TX diversity is disabled. */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint8 closedlooptimingadj_mode; /* 0 : CLTD timing adjust mode 0 */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ /* 1 : CLTD timing adjust mode 1 */
+ kal_uint8 ssdt_id; /* 0 ~ 8. 1 for 'A'. 8 for not applicable*/
+ kal_uint8 tpc_index; /* TPC combination index. 0 ~ 5 */
+ kal_int8 tpc_power_offset; /* Power offset between TPC and DPDCH,-1 means INVALID, range 0~24 dB (actual 0:0.25:6) [R5 only] */
+ /* [R6] For F-DPCH, UL1 doesn't care this value */
+
+ /* [R6] F-DPCH: dl_dpch_num must be 1 and the index of the F-DPCH info must be 0 in dl_dpch_info list */
+ kal_uint8 dl_dpch_num; /* # of DPDCH on the RL */
+ FDD_dldpch_code_T dl_dpch_info[FDD_MAX_DLDPCH]; /* Information for each code channel */
+
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rla */
+ kal_uint8 fdpch_slot_format; /* [R7] F-DPCH only, range: 0~9. For R6 and previous version, this value should be 0 */
+ kal_bool fdpch_sttd_ind; /* [R6] F-DPCH only, TRUE when STTD is used. FALSE, otherwise */
+
+ kal_bool hsdsch_serving_rl_ind; /* [R5] The value "TRUE" indicates that this radio link is the serving HS-DSCH radio link. FALSE, otherwise */
+ kal_bool edch_serving_rl_ind; /* [R6] The value "TRUE" indicates that this radio link is the serving E-DCH radio link. FALSE, otherwise */
+ kal_bool sttd_valid; /* To judge if sttd value can be used by UL1 when doing SCS */
+} FDD_dl_dpch_rl_T;
+
+typedef struct _FDD_dl_establish_T
+{
+ kal_uint8 t312; /* T312 */
+ kal_uint16 n312; /* N312 */
+ kal_uint8 n313; /* N313 */
+ kal_uint8 t313; /* T313 */
+ kal_uint16 n315; /* N315 */
+} FDD_dl_establish_T;
+
+#ifdef __UMTS_R7__
+/* [R7] Determine whether UL1 need to store HS-SCCH order when release DCH channel */
+typedef enum _FDD_dpch_release_type_E
+{
+ FDD_DCH_RELEASE = 0, /* Don't need to store HS-SCCH order */
+ FDD_DCH_TRHHO_RELEASE, /* Need to store HS-SCCH order */
+ FDD_DCH_TRHHO_REVERT_RELEASE, /* Don't need to store HS-SCCH order */
+ FDD_DCH_TMHHO_RELEASE, /* Need to store HS-SCCH order */
+ FDD_DCH_TMHHO_REVERT_RELEASE, /* Don't need to store HS-SCCH order */
+ FDD_DCH_IRAT_RELEASE, /* Need to store HS-SCCH order */
+ FDD_DCH_ALL_RL_TIMING_MODIFY_RELEASE /* Need to store HS-SCCH order */
+} FDD_dpch_release_type_E;
+#endif /* __UMTS_R7__ */
+
+/*-------- TFCS related definition ----------------------*/
+typedef struct _FDD_sig_gain_T
+{
+ kal_uint8 beta_c; /* Bc. 0 ~ 15 */
+ kal_uint8 beta_d; /* Bd. 0 ~ 15 */
+ kal_int8 ref_tfc_id; /* Reference TFC ID. -1 ~ 3. */
+ /* 0 ~ 3 : This TFCI is a referenced id for other computed TFC. */
+ /* -1 : It is an invalid value. Means it will not be referenced by other TFC. */
+} FDD_sig_gain_T;
+
+typedef union _FDD_gain_factor
+{
+ kal_int8 computed_gain_id; /* For computed gain factor using reference TFC id. 0 ~ 3 */
+ FDD_sig_gain_T sig_gain; /* The signaled gain factor. */
+} FDD_gain_factor;
+
+typedef struct _FDD_ul_dpch_tfc_T
+{
+ kal_uint8 tfi_list[FDD_MAX_TRCH_NUM]; /* The list of TFI for this TFCI for UL DCH TrCH */
+ kal_bool sig_gain_ind; /* True: Gain factor is siganled. False: Gain factor is computed from reference TFCI */
+ FDD_gain_factor gain_factor; /* Gain factor */
+} FDD_ul_dpch_tfc_T, FDD_ul_tfc_T;
+//} FDD_ul_dpch_tfc_T;
+
+typedef struct _FDD_rach_tfc_T
+{
+ kal_uint8 tfi_list; /* The list of TFI for this TFCI. The number of TrCH for PRACH is 1. */
+ kal_bool sig_gain_ind; /* True: Gain factor is siganled. False: Gain factor is computed from reference TFCI */
+ kal_int8 msg_pwr_offset; /* Power offset between the last preamble and the control part of RACH */
+ FDD_gain_factor gain_factor; /* Gain factor */
+} FDD_ul_rach_tfc_T;
+
+typedef struct _FDD_dl_tfc_T
+{
+ kal_uint8 tfi_list[FDD_MAX_TRCH_NUM]; /* The list of TFI for this TFCI for DL TrCH */
+} FDD_dl_tfc_T;
+
+/*-------- TrCH related definition ----------------------*/
+
+#if 0 //Modify by Anthony Chin, for UL1D's convenience to maintain DB
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+typedef struct _FDD_trch_T
+{
+ kal_uint8 trch_id; /* TrCH ID 1 ~ 32 */
+ kal_uint8 bit_offset; /* Bit offset. 0 ~ 7 */
+ FDD_tfs_T tfs; /* TFS of this TrCH */
+ kal_int8 target_bler; /* Diving the value of this field to 10 get the real BLER. -63 ~ 0 */
+} FDD_trch_T,
+FDD_ul_rach_trch_T,
+FDD_ul_dch_trch_T,
+FDD_dl_fachpch_trch_T,
+FDD_dl_dch_trch_T;
+#endif
+
+/*-------- CCTrCH related definition ----------------------*/
+typedef enum _FDD_cctrch_type_E
+{
+ FDD_CCTRCH_UL_RACH, /* UL RACH CCTrCH */
+ FDD_CCTRCH_UL_DCH, /* UL DCH CCTrCH */
+ FDD_CCTRCH_DL_DCH, /* DL DCH CCTrCH */
+ FDD_CCTRCH_DL_PCH, /* DL PCH CCTrCH */
+ FDD_CCTRCH_DL_FACH, /* DL FACH CCTrCH */
+ FDD_CCTRCH_DL_BCH, /* DL BCH CCTrCH */
+ FDD_CCTRCH_DL_FDPCH, /* DL FDPCH, only for UL1 use */
+ /* __UMTS_R7__ BEGIN */
+ FDD_CCTRCH_DL_EPCH, /* DL EPCH CCTrCH */
+ /* __UMTS_R7__ END */
+ /* __UMTS_R8__ BEGIN */
+ FDD_CCTRCH_UL_EDCH /* UL EDCH CCTrCH */
+ /* __UMTS_R8__ END */
+} FDD_cctrch_type_E;
+
+typedef struct _FDD_FACH_PCH_Info_T
+{
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */
+ /* If the value of tm is not equal to -1, UL1 will use this value */
+ /* If the value of tm is equal to -1, UL1 will not use this value */
+ kal_int16 rscp; /* Serving cell RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
+ FDD_sccpch_info_T sccpch_info; /* Physical channel for PCH/FACH to be carried over */
+ kal_bool sccpch_optimization; /* True if FACH and PCH use the same S-CCPCH. valid only for configuring CTCH */
+ kal_uint16 tfc_num; /* # of TFC in TFCS */
+ FDD_dl_tfc_T tfcs[FDD_MAX_DL_TFC]; /* TFCS */
+ kal_uint8 active_dl_trch_list; /* Active TrCHs by bit string. MSB is the lowest numbered TrCH ID */
+ kal_uint8 trch_num; /* # of TrCHs carried on this CCTrCH */
+ FDD_dl_fachpch_trch_T trch_list[FDD_MAXFACHPCH]; /* List of TrCHs carried on this CCTrCH */
+ kal_bool pich_ctch_valid; /* True means "pich_ctch_info" is valid. */
+ FDD_pich_ctch_info_T pich_ctch_info; /* PICH or CTCH information */
+} FDD_FACH_PCH_Info_T;
+
+/*-------- BCH related definition ----------------------*/
+typedef struct _FDD_sib_info_T
+{
+ kal_uint8 seg_count; /* SEG_COUNT 1 ~ 16 */
+ kal_uint16 sib_rep; /* SIB_REP 2^2 ~ 2^12 */
+ kal_uint16 sib_pos; /* SIB_POS 0 ~ sib_rep-2 */
+ kal_uint8 sib_off[FDD_MAX_SIB_SEG_COUNT]; /* SIB_OFF 2 ~ 32 The # of elements of this field is equal to seg_count-1 */
+} FDD_sib_info_T;
+
+typedef enum _FDD_bch_priority_E
+{
+ FDD_BCH_PRIOHIGH, /* Priority High */
+ FDD_BCH_PRIOMEDIUM, /* Priority Medium */
+ FDD_BCH_PRIOLOW, /* Priority Low */
+ FDD_BCH_PRIORR, /* Priority for SIB round robin */
+} FDD_bch_priority_E;
+
+/*------- PHY_POST_TX_IND related ---------*/
+typedef struct _FDD_tPhyPostTxMemInfo
+{
+ kal_uint8 RbId;
+ kal_uint8 *pContainer;
+} FDD_tPhyPostTxMemInfo;
+
+typedef struct _FDD_tPhyPostTxElement
+{
+ kal_uint8 Num;
+ FDD_tPhyPostTxMemInfo TxMemInfo[FDD_MAX_UL_TB];
+#if defined(__GEMINI__) && defined(__UMTS_RAT__)
+ kal_bool is_tx_suspend; /* This flag is only used for ULDCH when Gemini2.0. For RACH, this flag is always false.
+ It indicates if there is SIM2 gap in the minTTI period of the released ul data, and UL1D will set this flag. */
+ kal_uint8 cfn; /* This value is only used for ULDCH when Gemini2.0.
+ It indicates the cfn value that UL1C gets the ul data from UMAC. */
+#endif
+} FDD_tPhyPostTxElement;
+
+typedef enum _FDD_tPhyPostTxType
+{
+ FDD_POST_TX_RACH,
+ FDD_POST_TX_DCH
+} FDD_tPhyPostTxType;
+
+/*-------- Data related definition ----------------------*/
+typedef struct _FDD_dlTrchData
+{
+ kal_bool valid_fpch; /* Raymond,20070327 Eric/Anthony add this, already notify UMAC */
+ kal_bool is_dual_TF; /* Andrew/Sean: For MAC to identify BTFD_DUAL_TF TrCh */
+ kal_int8 crc_status; /* Jay: For DUAL-TF TrCH power control*/
+ kal_uint8 trchId; /* TrCH ID */
+ kal_uint16 tb_size; /* TB size in bit. 0 ~ 4992 */
+ kal_uint16 num_tb; /* # of TB. 0 ~ 512 */
+ kal_uint16 addi_crc_size; /*Indicate additional crc size for MT6290E1 RXBRP DOB issue workaround*/
+ kal_bool is_hw_out_extra; /*L1 internal: Indicate whether HW output extra bytes for MT6290E1 RXBRP DOB issue workaround*/
+} FDD_dlTrchData;
+
+typedef struct _FDD_ulTrchData
+{
+ kal_uint8 trchId; /* TrCH ID */
+ kal_uint16 tb_size; /* TB size in bit. 0 ~ 4992 */
+ kal_uint16 num_tb; /* # of TB. 0 ~ 512 */
+} FDD_ulTrchData;
+
+/*-------- Measurement related definition ----------------------*/
+typedef struct _FDD_preferred_cell_list_T
+{
+ kal_uint8 uarfcn_index; /* Frequency index */
+ /* Freq. array is contained in Frequency scan message */
+ kal_uint16 psc; /* Primary Scrambling code */
+} FDD_preferred_cell_list_T;
+
+typedef enum _FDD_measured_type_E
+{
+ FDD_INTRA_FREQENCY_MEASURED,
+ FDD_INTER_FREQENCY_MEASURED,
+ FDD_FREQ_SCAN_DETECTED,
+ FDD_INTRA_SEC_FREQENCY_MEASURED /* [R9]Secondary intra-freq measurement */
+} FDD_measured_type_E;
+
+
+typedef enum _FDD_cell_type_E
+{
+ FDD_MONITORED,
+ FDD_DETECTED,
+ FDD_SPECIFIC_CELL_SEARCH,
+ FDD_MONITORED_CELL_FOUND,
+ FDD_DETECTED_CELL_FOUND
+} FDD_cell_type_E;
+
+typedef enum _FDD_meas_status_E
+{
+ FDD_MS_INCLUDED,
+ FDD_MS_NOTINCLUDED
+} FDD_meas_status_E;
+
+typedef enum _FDD_meas_tm_off_type_E
+{
+ FDD_TM_OFF_RST,
+ FDD_TM_OFF_DCH,
+ FDD_TM_OFF_COMMON,
+ FDD_TM_OFF_NA
+} FDD_meas_tm_off_type_E;
+
+typedef struct _FDD_measured_cell_T
+{
+ kal_bool sttd; /* Indicate if STTD is used */
+ kal_int16 ec_no; /* Ec/No. Range: -100~0 means (-25~0) dB in 0.25 dB step */
+ kal_int16 rscp; /* RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_uint16 freq; /* DL UARFCN */
+ FDD_meas_tm_off_type_E tm_off_type; /*Indicate which field is applicable in this report*/
+ kal_int16 sfn; /* SFN in BCH. -1 ~ 4095 : -1 means unknown SFN */
+ kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */
+ kal_int32 tm; /* Cell boundary. -1 ~ 38400*8-1 : -1 means unknown timing*/
+ kal_uint32 meas_sfn_diff; /* SFN_SFN difference in chips*/
+ FDD_meas_status_E meas_status; /* Indicate whether this cell is measured in this time */
+ FDD_cell_type_E cell_type; /* AS, MS or DS cell */
+ kal_bool update_timing; /* Indicates if it is recommended by UL1 for MEME to update cell timing based on FS result */
+} FDD_measured_cell_T;
+
+typedef enum _FDD_meas_type_E
+{
+ FDD_MT_INTRA_FREQ, /* Intra-frequency measurement */
+ FDD_MT_INTER_FREQ, /* Inter-frequency measurement */
+ FDD_MT_GSM_RAT /* GSM-RAT measurement */
+} FDD_meas_type_E;
+
+typedef enum _FDD_sfn_priority_E
+{
+ FDD_SFN_HIGH,
+ FDD_SFN_MEDIUM,
+ FDD_SFN_LOW,
+ FDD_SFN_OFF
+} FDD_sfn_priority_E;
+
+typedef struct _FDD_meas_spec_T
+{
+ kal_bool ds_meas_intra; /* Indicate if measure on intra-freq (and R9 secondary intra-freq) detected set*/
+ kal_bool ds_sfn_intra; /* Indicate if reading SFN of detected set */
+#ifdef __UMTS_R10__
+ kal_bool ds_meas_inter; /* Indicate if measure on inter-freq detected set*/
+#endif
+ kal_int8 nc_nbr_dch; /* # of best cells to read SFN in DCH. -1 ~ 32
+ -1 means L1 should not read SFN for any cell
+ 0 means L1 should read SFN for cells which have stronger CPICH measurement
+ Other values means L1 should read FN for nc_nbr_dch cells from active set, monitored set and detected set.
+ */
+ FDD_sfn_priority_E serving_prio; /* The priority of reading SFN of cells in active set.
+ Only used when L1 is in DCH state and nc_nbr_dch > 0 */
+ FDD_sfn_priority_E monitor_prio; /* The priority of reading SFN of cells in monitored set.
+ Only used when L1 is in DCH state and nc_nbr_dch > 0 */
+ FDD_sfn_priority_E detect_prio; /* The priority of reading SFN of cells in detected set.
+ Only used when L1 is in DCH state and nc_nbr_dch > 0 */
+ kal_uint8 nc_nbr_rach; /* # of best cells to read SFN in non-DCH state. 0 ~ 32 */
+} FDD_meas_spec_T;
+
+#ifdef __UMTS_R8__
+typedef enum _FDD_higher_prio_search_support_E /* [Rel8][Absolute Priority Search] absolute priority search type */
+{
+ FDD_REGULAR_MEAS_ONLY,
+ FDD_HIGHER_PRIORITY_ONLY,
+ FDD_HIGHER_PRIORITY_AND_REGULAR_MEAS
+} FDD_higher_prio_search_support_E;
+#endif
+
+typedef struct _FDD_cell_info_list_T
+{
+ kal_uint8 freq_index; /* UARFCN index */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_bool sttd; /* Indicate if STTD is used */
+ kal_bool read_sfn_ind; /* Indicate if read SFN */
+ kal_int16 ref_timing; /* Cell boundary. -1 ~ 38400-1 : -1 means unknown timing*/
+ kal_bool ref_timing_sib; /* Indicate if the reference timing comes from SIB or Meas. Control */
+ kal_int32 tm; /* Cell boundary. -1 ~ 38400*8-1 : -1 means unknown timing*/
+ kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */
+#ifdef __UMTS_R8__
+ FDD_higher_prio_search_support_E prio_search_control; /* [Rel8] Higher priority search control */
+#endif
+} FDD_cell_info_list_T;
+
+typedef enum _FDD_event_cond_E
+{
+ FDD_COND_ABOVE, /* Above threshold */
+ FDD_COND_ABOVE_EQUAL, /* Above or equal to threshold */
+ FDD_COND_BELOW, /* Below threshold */
+ FDD_COND_BELOW_EQUAL, /* Below or equal to threshold */
+ FDD_COND_EVENT_6C, /* [R6] Reporting event 6C: The UE Tx power reaches its minimum value */
+ FDD_COND_EVENT_6D /* [R6] Reporting event 6D: The UE Tx power reaches its maximum value */
+} FDD_event_cond_E;
+
+typedef struct _FDD_meas_event_T
+{
+ kal_uint8 event_id; /* Measurement event ID */
+ kal_uint8 measurement_id; /* Measurement ID */
+ kal_int16 threshold;
+ kal_uint16 delay; /* Time to Triggered. 0 ~ 500 frames */
+ FDD_event_cond_E condition; /* Event triggered condition */
+} FDD_meas_event_T;
+
+typedef struct _FDD_rl_meas_result_T
+{
+ kal_uint8 rl_status; /* RL status */
+ /* 0 : Not detected */
+ /* 1 : Detected not used */
+ /* 2 : Detected and demodulated */
+ kal_uint16 psc; /* Scrambling code of this RL */
+ kal_uint32 time_diff; /* RX-TX Timd diff. 0 ~ 38400*8-1 */
+} FDD_rl_meas_result_T;
+
+typedef enum _FDD_meas_act_E
+{
+ FDD_MEAS_UNCHANGE, /* Unchange a cell list */
+#ifndef __MTK_UL1_FDD__ /* 20080305: For Venus, still use old I/F */
+ FDD_MEAS_MODIFY, /* Modify an existed cell list */
+#endif
+ FDD_MEAS_DELETE, /* Delete an existed cell list */
+ FDD_MEAS_UPDATE /* Update the configuration of an existed cell list */
+} FDD_meas_act_E;
+
+typedef enum _FDD_triggering_cause_E
+{
+ FDD_REGULAR_REPORT,
+ FDD_ONE_SHOT_MEASUREMENT,
+ FDD_T_RESELECTION_EXPIRY
+} FDD_triggering_cause_E;
+
+typedef enum
+{
+ FDD_CPHY_MEAS_STOP_CAUSE_NONE, /* none: fill when none stop */
+ FDD_CPHY_MEAS_STOP_CAUSE_REGULAR, /* normal stop */
+ FDD_CPHY_MEAS_STOP_CAUSE_4G3IRHO /* stop triggered by 4G3 IRHO */
+} FDD_CPHY_MEASUREMENT_STOP_CAUSE_E;
+
+typedef struct _FDD_supplementary_meas_parameter_T
+{
+ kal_bool intra_meas_one_shot_ind; /* When intra-F cell list is updated,to notify if UL1 needs to do one-shot measurement on intra-F or not */
+ kal_bool inter_meas_one_shot_ind; /* When inter-F cell list is updated,to notify if UL1 needs to do one-shot measurement on inter-F or not */
+} FDD_supplementary_meas_parameter_T;
+
+typedef struct _FDD_supplementary_report_info_T
+{
+ FDD_triggering_cause_E triggering_cause; /* The triggering cause of this meas tick */
+ kal_bool evaluate_req; /* To notify if L3 need to trigger cell evaluattion */
+#ifdef __UMTS_R7__
+ kal_bool is_cycle2; /* Indicate whether the current DRX is cycle2 or not */
+#endif /* __UMTS_R7__ */
+} FDD_supplementary_report_info_T;
+
+/*-------- FACH MO related definition ----------------------*/
+typedef struct _FDD_fach_mo_info_T
+{
+ kal_uint8 n; /* # of frames in max TTI. 1,2,4,8 */
+ kal_uint8 k; /* MO cycle length coefficient. M_REP=2^k */
+ kal_bool inter_freq_ind; /* Indicate if inter-frequency meas in MO */
+ kal_bool inter_rat_ind; /* Indicate if inter-RAT meas in MO */
+ kal_bool inter_freq_cell_exist; /* Indicate if inter-freq cell in BA lsit is existed */
+ kal_bool inter_rat_cell_exist; /* Indicate if inter-rat cell in BA list is existed */
+ kal_uint16 start_off; /* C_RNTI % M_REP. 0 ~ 4095 */
+} FDD_fach_mo_info_T;
+
+/*-------- Operation-Mode related definition ----------------------*/
+typedef enum _FDD_mode_type_E
+{
+ FDD_OM_SINGLE, /* Single Mode */
+ FDD_OM_MULTI /* Dual Mode */
+} FDD_mode_type_E;
+
+typedef enum _FDD_rat_type_E
+{
+ FDD_UL1_RAT_UMTS_ACTIVE, /* UMTS_Active */
+ FDD_UL1_RAT_UMTS_INACTIVE /* UMTS_Inactive */
+} FDD_rat_type_E;
+
+typedef struct _FDD_duplex_mode_info_T
+{
+ umts_duplex_mode_type source_umts_duplex_mode;
+ umts_duplex_mode_type target_umts_duplex_mode;
+ lte_duplex_mode_type source_lte_duplex_mode;
+ lte_duplex_mode_type target_lte_duplex_mode;
+} FDD_duplex_mode_info_T;
+
+/*-------- Message(Primitive) related definition ----------------------*/
+typedef enum _FDD_dch_setup_msg_type_E
+{
+ FDD_DCH_SETUP, /* Used when DCH is established first time */
+ FDD_DCH_TRHHO, /* Used when timing reinitialized hard hand over */
+ FDD_DCH_TRHHO_REVERT, /* Used when timing reinitialized HHO revert */
+ FDD_DCH_TMHHO, /* Used when timing maintained hard hand over */
+ FDD_DCH_TMHHO_REVERT, /* Used when timing maintained HHO revert */
+ FDD_DCH_IRAT_REVERT, /* Used when Inter-RAT HHO revert */
+ FDD_DCH_ALL_RL_TIMING_MODIFY /* Used when all dpch rl timing offset is modified.*/
+} FDD_dch_setup_msg_type_E;
+
+
+typedef enum _FDD_dch_modify_msg_type_E
+{
+ FDD_DCH_RECONFIG, /* Used when DCH is reconfigured */
+ FDD_DCH_ASU, /* Used when active set update */
+ FDD_DCH_LOOP_MODE_2 /* Used when DCH loop back mode 2 */
+} FDD_dch_modify_msg_type_E;
+
+
+typedef enum _FDD_msg_container_error_E /* Error cause of message container, MA only*/
+{
+ FDD_NONE,
+ FDD_DCH_SETUP_FAIL
+} FDD_msg_container_error_E;
+
+typedef enum _FDD_TGPS_Action_E
+{
+ FDD_TGPS_ACT_START,
+ FDD_TGPS_ACT_STOP,
+ FDD_TGPS_ACT_SUSPEND,
+ FDD_TGPS_ACT_RESUME,
+ FDD_TGPS_ACT_CONTINUE,
+ FDD_TGPS_ACT_DELETE
+} FDD_TGPS_Action_E;
+
+typedef struct _FDD_TGPS_Action_T
+{
+ kal_uint8 tgpsi; /* TGPIS of the TGPS on which the action and apply flag should be applied */
+ kal_bool apply_current;
+ kal_bool apply_suspend;
+ FDD_TGPS_Action_E action;
+} FDD_TGPS_Action_T;
+
+typedef enum _FDD_meas_control_E
+{
+ FDD_MEAS_CTRL_INVALID, /* No meas. control action in current MSG_CONTAINER */
+ FDD_MEAS_CM_STOP, /* For inter-RAT HHO, stop CM measurement when receiving DCH release msg */
+ FDD_MAX_MEAS_CONTROL = FDD_MEAS_CM_STOP
+} FDD_meas_control_E;
+
+/*Add for improving full band FS efficiency -- by excluding some UARFCN or some frequency range*/
+typedef enum _FDD_full_band_option_E
+{
+ FDD_FULL_BAND_ONLY, /*Normal full band FS*/
+ FDD_FULL_BAND_AND_EXCLUDE /*Full band FS but the indicated frequency list/range will be excluded in the full band FS procedure*/
+} FDD_full_band_option_E;
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+typedef enum _FDD_uas_gemini_conflict_cause_enum
+{
+ FDD_URR_NO_CONFLICT,
+ FDD_URR_CONFLICT_WITH_GSM_BCCH,
+ FDD_URR_CONFLICT_WITH_GSM_NBCCH,
+ FDD_URR_CONFLICT_WITH_GSM_PCH,
+ FDD_URR_CONFLICT_WITH_GSM_OTHERS,
+ FDD_URR_CONFLICT_WITH_WCDMA_BCH_HIGH,
+ FDD_URR_CONFLICT_WITH_WCDMA_BCH_LOW,
+ FDD_URR_CONFLICT_WITH_WCDMA_PICH,
+ FDD_URR_CONFLICT_WITH_WCDMA_OTHERS,
+ FDD_URR_CONFLICT_WITH_LTE_BCCH,
+ FDD_URR_CONFLICT_WITH_LTE_NBCCH_HIGH,
+ FDD_URR_CONFLICT_WITH_LTE_NBCCH_MIDDLE,
+ FDD_URR_CONFLICT_WITH_LTE_NBCCH_LOW,
+ FDD_URR_CONFLICT_WITH_LTE_PCH,
+ FDD_URR_CONFLICT_WITH_LTE_OTHERS
+} FDD_uas_gemini_conflict_cause_enum;
+
+#ifdef __MODIFY_CTCH_RECEPTION_PRIO__
+typedef enum _FDD_rrce_gemini_priority_adjust_E
+{
+ FDD_GEMINI_PRIORITY_ADJUST_ALL_NORMAL, /* Currently only used in Gemini2.0, to raise all rx/tx/BCH channel priority for RRC connection establishment or DL sync procedure. */
+ FDD_GEMINI_PRIORITY_ADJUST_ALL_HIGH,
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH_NORMAL,
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH_IMPRV, /* Added as a part of CBS improvement, to raise one SIM CTCH priority over other SIM CTCH*/
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH_ETWS /* R8 ETWS feature, used for receiving ETWS CB. */
+} FDD_rrce_gemini_priority_adjust_E;
+#else
+typedef enum _FDD_rrce_gemini_priority_adjust_E
+{
+ FDD_GEMINI_PRIORITY_ADJUST_ALL, /* Currently only used in Gemini2.0, to raise all rx/tx/BCH channel priority for RRC connection establishment or DL sync procedure. */
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH /* R8 ETWS feature, used for receiving ETWS CB. */
+} FDD_rrce_gemini_priority_adjust_E;
+#endif
+
+#endif
+/*-------- [R5R6] HS-DSCH related ----------------------*/
+typedef enum _FDD_hs_cqi_k_E
+{
+ FDD_CQI_K_0,
+ FDD_CQI_K_2,
+ FDD_CQI_K_4,
+ FDD_CQI_K_8,
+ FDD_CQI_K_10,
+ FDD_CQI_K_20,
+ FDD_CQI_K_40,
+ FDD_CQI_K_80,
+ FDD_CQI_K_160,
+ /* __UMTS_R7__ BEGIN */
+ FDD_CQI_K_16,
+ FDD_CQI_K_32,
+ FDD_CQI_K_64
+ /* __UMTS_R7__ END */
+} FDD_hs_cqi_k_E;
+
+#ifdef __UMTS_R7__
+/* [R7] FDD_UE_OWN_CATEGORY or FDD_CATEGORY_12. According to 25.331 CR#4159, UE should use the number of soft channel bits
+ according to this category to decode HS-PDSCH TB. */
+typedef enum _FDD_hs_harq_ir_type_E
+{
+ FDD_UE_OWN_CATEGORY = 0,
+ FDD_CATEGORY_12
+} FDD_hs_harq_ir_type_E;
+
+typedef enum
+{
+ FDD_E_SCELL_PRI = 0,
+ FDD_E_SCELL_SEC,
+ FDD_E_SCELL_TOTAL, /* 0:primary, 1: secondary */
+ FDD_E_SCELL_BOTH = FDD_E_SCELL_TOTAL,
+} FDD_edch_scell_E;
+
+typedef struct _FDD_hs_tb_size_list_T
+{
+ kal_int8 tbs_index; /* [Range] 1~90, -1 if this is invalid */
+ kal_bool second_code_support; /* Indicates whether the second HS-PDSCH code is used for this TB size.
+ If TRUE, the HS-PDSCH second code index value is the value of IE 'HSPDSCH Code Index' incremented by 1. */
+} FDD_hs_tb_size_list_T;
+
+/* [R7] MAC entity types for handling HS-DSCH */
+typedef enum _FDD_hs_mac_entity_type_E
+{
+ FDD_HS_MAC_HS_ENTITY = 0,
+ FDD_HS_MAC_EHS_ENTITY,
+ FDD_HS_MAC_EHS_ENTITY_DC
+} FDD_hs_mac_entity_type_E;
+#endif /* __UMTS_R7__ */
+
+typedef struct _FDD_hs_scch_info_T
+{
+ kal_uint8 ssc; /* DL scrambling code to be applied for HS-DSCH and HS-SCCH */
+ kal_uint8 ovsf_code_num; /* Number of HS-SCCH to be received. Range:1~4 */
+ kal_uint8 ovsf[FDD_MAX_HS_SCCH_NUM]; /* OVSF code of HS-SCCH to be received */
+} FDD_hs_scch_info_T;
+
+typedef struct _FDD_hs_meas_fb_info_T
+{
+ kal_int8 meas_po; /* Measurement power offset. Range: -12~26 */
+ FDD_hs_cqi_k_E cqi_k; /* Measurement feedback cycle */
+ kal_uint8 cqi_repe_factor; /* CQI repetition factor. Range: 1~4 */
+ kal_uint8 delta_cqi; /* DeltaCQI. Range: 0~8 */
+} FDD_hs_meas_fb_info_T;
+
+typedef struct _FDD_hs_harq_info_T
+{
+ kal_uint8 process_num; /* Number of HARQ process. Range: 1~8 */
+ kal_bool explicit_partition; /* TRUE indicates explicit memory partition. FALSE indicates implicit memory partition */
+ kal_uint8 process_mem_size[FDD_MAX_HS_PROCESS_NUM]; /* index of HARQ memory size. range: 0~60, only valid when memory partition is explicit */
+#ifdef __UMTS_R7__
+ FDD_hs_harq_ir_type_E harq_ir_type; /* FDD_UE_OWN_CATEGORY or FDD_CATEGORY_12. According to 25.331 CR#4159, UE should use the number of soft channel bits
+ according to this category to decode HS-PDSCH TB. */
+ FDD_hs_mac_entity_type_E hs_mac_entity; /* enum for MAC-hs, MAC-ehs and MAC-ehs with DC */
+#endif /* __UMTS_R7__ */
+} FDD_hs_harq_info_T;
+
+typedef struct _FDD_hs_ulpc_info_T
+{
+ kal_uint8 delta_ack; /* delta_ack. range: 0~8 */
+ kal_uint8 delta_nack; /* delta_nack. range: 0~8 */
+ kal_uint8 acknack_repe_factor; /* ack_nack_repetition_factor. range: 1~4 */
+ kal_uint8 harq_preamble_mode; /* [R6] range: 0~1, 1: indicates the preamble and postable are used
+ for R5 and previous version, this value should be 0 */
+} FDD_hs_ulpc_info_T;
+
+typedef enum
+{
+ FDD_DSCH_NO_HRNTI_DETECTED = 0, /*HS-SCCH CRC check is failed*/
+ FDD_DSCH_D_HRNTI_DETECTED = 1, /*HS-PDSCH is indicated by HS-SCCH with dH-RNTI*/
+ FDD_DSCH_C_HRNTI_DETECTED = 2, /*HS-PDSCH is indicated by HS-SCCH with cH-RNTI*/
+ FDD_DSCH_B_HRNTI_DETECTED = 3, /*HS-PDSCH is indicated by HS-SCCH with bH-RNTI*/
+ FDD_DSCH_HRNTI_LESS = 4, /*HS-PDSCH is decoded blindly without HS-SCCH */
+ FDD_DSCH_NOT_RECEIVE = 5, /*This subframe is not received by HW */
+
+} FDD_hs_dsch_decode_hrnti_E;
+
+typedef struct _FDD_hsdsch_data_T
+{
+ kal_uint16 tb_size; /*[Range]: 137 ~ 27952 bits, MAC-hs PDU size */
+ kal_uint8 *p_data; /* The buffer contains MAC-hs data */
+ kal_uint8 *p_data_head; /* The address of the HDA buffer allocated by UMAC */
+ FDD_hs_dsch_decode_hrnti_E decode_hrnti; /*H-RNTI dectected info*/
+ kal_int8 pi_repeat_cycle; /* -1:invalid, -2:retransmission with CRC pass, 1~20:valid pi_repeat_cyle */
+
+ kal_uint8 decode_counter; /* For EM in UMAC */
+} FDD_hsdsch_data_T;
+
+#ifdef __UMTS_R7__
+typedef enum _FDD_mac_ehs_reset_cause_E
+{
+ FDD_Treset_Expired
+} FDD_mac_ehs_reset_cause_E;
+#endif /* __UMTS_R7__ */
+
+typedef enum _FDD_edch_tti_E
+{
+ FDD_EDCH_TTI_2 = 0,
+ FDD_EDCH_TTI_10 = 1,
+ FDD_EDCH_TTI_TOTAL
+} FDD_edch_tti_E;
+
+typedef enum _FDD_edch_sf_E
+{
+ FDD_EDCH_SF256 = 0,
+ FDD_EDCH_SF128 = 1,
+ FDD_EDCH_SF64 = 2,
+ FDD_EDCH_SF32 = 3,
+ FDD_EDCH_SF16 = 4,
+ FDD_EDCH_SF8 = 5,
+ FDD_EDCH_SF4 = 6,
+ FDD_EDCH_ONE_PHCH = 6,
+ FDD_EDCH_2SF4 = 7,
+ FDD_EDCH_SF2 = 7,
+ FDD_EDCH_2SF2 = 8,
+ FDD_EDCH_2SF2AND2SF4 = 9,
+ FDD_EDCH_2SF2AND2SF4_16QAM = 10,
+ FDD_EDCH_SF_CNT = 11,
+ FDD_EDCH_SF_NA = 12
+} FDD_edch_sf_E;
+
+typedef enum
+{
+ MPR_COMBO_BETA_D_ZERO_HS_ZERO = 0,
+ MPR_COMBO_BETA_D_NON_ZERO_HS_ZERO,
+ MPR_COMBO_BETA_D_ZERO_HS_NON_ZERO,
+ MPR_COMBO_BETA_D_NON_ZERO_HS_NON_ZERO,
+ MPR_COMBO_MAX
+} mpr_combo_E;
+
+typedef enum _FDD_edch_rv_config_E
+{
+ FDD_EDCH_RV0 = 0,
+ FDD_EDCH_RVTABLE = 1
+} FDD_edch_rv_config_E;
+
+typedef struct _FDD_eagch_info_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 255 */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell */
+ FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-AGCH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/
+} FDD_eagch_info_T;
+
+typedef struct _FDD_ehich_info_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 127 */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell (tauDPCH) */
+ FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-HICH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/
+ kal_uint8 signature_seq; /* E-HICH signature sequence 0~39*/
+ kal_uint8 tpc_index; /* TPC combination index. 0 ~ 5 */
+} FDD_ehich_info_T;
+
+typedef struct _FDD_ergch_info_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 127. Should be the same as E-HICH ovsf code */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell (tauDPCH) */
+ FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-RGCH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/
+ kal_uint8 signature_seq; /* E-RGCH signature sequence 0~39*/
+ kal_uint8 rg_comb_index; /* RG combination index. 0 ~ 5 */
+} FDD_ergch_info_T;
+
+typedef struct _FDD_ref_etfci_T
+{
+ kal_uint8 ref_etfci; /* Reference E-TFCI. 0~127 */
+ /* __UMTS_R7__ */
+ kal_uint8 ref_etfci_po; /* Reference E-TFCI PO. 0~31 */
+} FDD_ref_etfci_T;
+
+#ifdef __UMTS_R8__
+/* [R8] Minimum reduced E-DPDCH gain factor */
+typedef enum _FDD_beta_ed_reduced_min_E
+{
+ FDD_beta_ed_8_15 = 0, /* 8/15 */
+ FDD_beta_ed_11_15, /* 11/15 */
+ FDD_beta_ed_15_15, /* 15/15 */
+ FDD_beta_ed_21_15, /* 21/15 */
+ FDD_beta_ed_30_15, /* 30/15 */
+ FDD_beta_ed_42_15, /* 42/15 */
+ FDD_beta_ed_60_15, /* 60/15 */
+ FDD_beta_ed_84_15 /* 84/15 */
+} FDD_beta_ed_reduced_min_E;
+#endif /* __UMTS_R8__ */
+
+typedef struct _FDD_edpdch_info_T
+{
+ /* __UMTS_R7__ */
+ kal_uint8 etfci_table_index; /* E-TFCI table index. 0~1. If the UE is operating in 16QAM, the value is increased by 2. 0~3. */
+ kal_uint8 num_of_ref_etfci; /* number of reference etfci. range:1~8 */
+ FDD_ref_etfci_T ref_etfci[FDD_MAX_REF_ETFCI_NUM]; /* reference E-TFCIs */
+ FDD_edch_sf_E max_ch_code; /* Max. channelisation code */
+ kal_uint8 ul_dpch_num; /* # of UL DPCH, range:0~FDD_MAX_ULDPCH*/
+ kal_uint8 pl_non_max; /* PLnon-max*100/4, range:11~25 */
+#ifdef __UMTS_R8__
+ FDD_beta_ed_reduced_min_E beta_ed_reduced_min; /* Minimum reduced E-DPDCH gain factor */
+#endif /* __UMTS_R8__ */
+} FDD_edpdch_info_T;
+
+typedef struct _FDD_edpcch_info_T
+{
+ kal_uint8 edpcch_po; /* E-DPCCH/DPCCH power offset. 0~8 */
+#ifdef __UMTS_R7__
+ kal_uint8 etfci_boost; /* [Range] Integer(0..127)E-TFCI threshold beyond which boosting of EDPCCH is enabled */
+ kal_uint8 delta_t2tp; /* [Range] Integer (0..6)If E-TFCI-Boost is set to 127 this IE is not needed, otherwise it is mandatory. */
+ kal_bool edpdch_pwr_interpolation; /* True means EDPDCH power Interpolation formula is used, False means EDPDCH power
+ Extrapolation formula is used for the computation of the gain factor £]ed */
+#endif /* __UMTS_R7__ */
+} FDD_edpcch_info_T;
+
+typedef struct _FDD_edch_harq_info_T
+{
+ FDD_edch_rv_config_E edch_rv_config; /* RV config */
+} FDD_edch_harq_info_T;
+
+
+/**********************************************************************************************************************/
+/*********************************** UL1 Interface maintained by UL1D (Begin) *************************************/
+/**********************************************************************************************************************/
+/*UL1D*/typedef enum _FDD_hs_dsch_dc_data_source_E
+/*UL1D*/
+{
+ /*UL1D*/ FDD_PRIMARY_CELL = 0, /* data from primary cell, only hsdsch_data[] should be processed */
+ /*UL1D*/ FDD_SECONDARY_CELL = 1, /* data from secondary cell, only hsdsch_data2[] should be processed */
+ /*UL1D*/ FDD_DUAL_CELL = 2 /* data from dual cells, both hsdsch_data[] and hsdsch_data2[] should be processed*/
+ /*UL1D*/
+} FDD_hs_dsch_dc_data_source_E;
+/*UL1D*/
+/*UL1D*/typedef struct _FDD_uldch_data_req_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn;
+ /*UL1D*/ kal_uint8 ul_mac_event; /* bit 0: UL DCH setup, */
+ /*UL1D*/ /* bit 1: UL DCH release */
+ /*UL1D*/ /* bit 2: UL DCH modify */
+ /*UL1D*/ kal_uint8 dpdch_num;
+ /*UL1D*/ kal_bool restartSRB;
+ /*UL1D*/ kal_bool tx_enable;
+ /*UL1D*/ kal_bool tx_suspend;
+ /*UL1D*/ kal_uint8 tfc_status[FDD_MAX_UL_TFC];
+ /*UL1D*/
+} FDD_uldch_data_req_T;
+/*UL1D*/
+/*UL1D*/
+/*UL1D*/typedef struct _FDD_uldch_data_ind_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn;
+ /*UL1D*/ kal_uint8 num_trch;
+ /*UL1D*/ FDD_ulTrchData trchInfo[FDD_MAX_TRCH_NUM]; /* TrCH information including number of TB and TB size. Note that only 1 TRCH is included in RACH data. */
+ /*UL1D*/ kal_uint16 tfci;
+ /*UL1D*/ kal_uint16 num_data[FDD_MAX_TRCH_NUM]; /* num_data[FDD_MAX_TRCH_NUM]. It means the total TB size on 1 TRCH. Value: 0 ~ FDD_MAX_UL_TB. */
+ /*UL1D*/ kal_uint8 *data[FDD_MAX_TRCH_NUM];
+ /*UL1D*/#ifdef UNIT_TEST
+ /*UL1D*/ void *addr;
+ /*UL1D*/#endif /* UNIT_TEST */
+ /*UL1D*/
+} FDD_uldch_data_ind_T;
+/*UL1D*/
+/*UL1D*//* Input parameters of FDD_umac_e_dch_tick_1() */
+/*UL1D*/typedef struct _FDD_etfc_eval_info_req_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn;
+ /*UL1D*/ kal_uint8 subframe;
+ /*UL1D*/ kal_uint8 mac_event; /* bit0: setup; bit1: release; bit2: modify */
+ /*UL1D*/ FDD_edch_tti_E edch_tti;
+ /*UL1D*/ kal_bool is_tx_suspend[FDD_E_SCELL_TOTAL];
+ /*UL1D*/#if defined( __GEMINI__ ) && defined( __UMTS_RAT__ )
+ /*UL1D*/ kal_bool is_gemini_tx_suspend; /* tx suspended due to Gemini */
+ /*UL1D*/#endif
+ /*UL1D*/ kal_bool compressed_2ms; /* subframe overlaps TG (Refer this value only when 2ms TTI) */
+ /*UL1D*/ kal_uint8 num_of_non_dtx_slots_10ms; /* number of non-gap slots in the corresponding TTI (Refer this value only when 10ms TTI) */
+ /*UL1D*/ kal_uint8 e_agch_result[FDD_E_SCELL_TOTAL]; /* 0: Invalid 1:primary E-RNTI detected 2: secondary E-RNTI detected */
+ /*UL1D*/ kal_uint8 e_agch_data[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint8 e_hich_result_serving[FDD_E_SCELL_TOTAL]; /*0:DTX, 1:ACK, 2:invalid(shall ASSERT), 3:NACK */
+ /*UL1D*/ kal_uint8 e_hich_result_non_serving[FDD_E_SCELL_TOTAL]; /*0:DTX or NACK, 1:ACK, 2:invalid(shall ASSERT) , 3:invalid(shall ASSERT)*/
+ /*UL1D*/ kal_uint8 e_rgch_result_serving[FDD_E_SCELL_TOTAL]; /*0:HOLD or DTX, 1:UP, 2:invalid(shall ASSERT), 3:DOWN */
+ /*UL1D*/ kal_uint8 e_rgch_result_non_serving[FDD_E_SCELL_TOTAL]; /*0:HOLD or DTX, 1:invalid(shall ASSERT), 2:invalid(shall ASSERT), 3:DOWN */
+ /*UL1D*/
+ /*UL1D*/ kal_bool isTtiChangeSuspend;
+ /*UL1D*/ kal_bool isServingCellChange[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_bool isServingCellChNotPartOfPrevEdchRls[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint16 mac_harq_event; /* bit 0: TTI change */
+ /*UL1D*/ /* bit 1: E-TFCI table index change */
+ /*UL1D*/ /* bit 2: HARQ RV ReConfiguration */
+ /*UL1D*/ /* bit 3: PLnon-max change */
+ /*UL1D*/ /* bit 4: Secondary cell activated */
+ /*UL1D*/ /* bit 5: Secondary cell deactivated */
+ /*UL1D*/ kal_bool insufficient_preamble[FDD_E_SCELL_TOTAL]; // Cannot transmit E-DCH due to insufficient UL DPCCH preamble.
+ /*UL1D*/ kal_bool match_mac_dtx_cycle[FDD_E_SCELL_TOTAL]; // If the condition of last paragraph of 25.321 11.8.1.4 is fulfilled.
+ /*UL1D*/ kal_bool is_dtx_cycle_2[FDD_E_SCELL_TOTAL]; // The DTX feature is configured by higher layers, and there has not been any E-DCH transmission for the last "Inactivity Threshold for UE DTX cycle 2" E-DCH TTIs.
+ /*UL1D*/ kal_bool is_cedch; /*Notify UMAC if common EDCH or not*/
+ /*UL1D*/ kal_uint8 *sf_of_etfci;
+ /*UL1D*/ kal_bool restartSRB;
+ /*UL1D*/ kal_uint32 SlotTick_FRC; /* The absolute FRC (free-run counter) value of 1 slot ahead of Tx timing, the unit is micro-second (us) */
+ /*UL1D*/ /* Ex: FRC value of slot 8 will be provided if Tx on slot 9 */
+ /*UL1D*/
+ /*UL1D*/
+} FDD_etfc_eval_info_req_T ;
+/*UL1D*/
+/*UL1D*//* Output parameters of FDD_umac_e_dch_tick_1() */
+/*UL1D*/typedef struct _FDD_etfc_eval_info_ind_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/ kal_uint8 harq_id; /* 2ms TTI: 0..7, 10ms TTI: 0..3 */
+ /*UL1D*/ kal_bool tx_enable[FDD_E_SCELL_TOTAL]; /* true=on, false=off */
+ /*UL1D*/ kal_bool is_new_tx[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint8 delta_harq[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_bool collision_resolved;
+ /*UL1D*/ kal_bool is_tebs_larger_than_0;
+ /*UL1D*/ kal_uint8 serving_grant[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint8 non_scheduled_delta_harq;
+ /*UL1D*/ kal_uint16 non_scheduled_data_size;
+ /*UL1D*/
+} FDD_etfc_eval_info_ind_T;
+/*UL1D*/
+/*UL1D*//* Input parameters of FDD_umac_e_dch_tick_2() */
+/*UL1D*/typedef struct _FDD_edch_data_req_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/ FDD_edch_scell_E edch_cell;
+ /*UL1D*/ FDD_edch_tti_E edch_tti; /* E-DCH TTI 2ms or 10ms */
+ /*UL1D*/
+ /*UL1D*/ kal_bool compressed_2ms; /* If the corresponding subframe overlaps TG (Refer this value only when 2ms TTI) */
+ /*UL1D*/ kal_uint8 num_of_non_dtx_slots_10ms; /* number of non-gap slots in the corresponding TTI (Refer this value only when 10ms TTI) */
+ /*UL1D*/ kal_uint8 *supported_etfci_bitmap; /* 2 LSB bits of [0] = etfci 0, 2 MSB bits of [31] = etfci 127. */
+ /*UL1D*/ /* 11=support, 10=power not support, 01=data size not support, 00=not support */
+ /*UL1D*/ kal_uint16 uph_in_dB; /*UE transmission power headroom reported by UL1(unit: dB)*/
+ /*UL1D*/
+} FDD_edch_data_req_T ;
+/*UL1D*/
+/*UL1D*//* Output parameters of FDD_umac_e_dch_tick_2() */
+/*UL1D*/typedef struct _FDD_edch_data_ind_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/ kal_bool tx_enable; /* true=on, false=off */
+ /*UL1D*/ kal_uint8 harq_id; /* 2ms TTI: 0..7, 10ms TTI: 0..3 */
+ /*UL1D*/ kal_bool is_new_tx;
+ /*UL1D*/ kal_uint8 etfci; /* Range: 0..127 */
+ /*UL1D*/ kal_uint8 ntx1; /* 10 ms TTI: 8..15, 2ms TTI: don't care */
+ /*UL1D*/ kal_bool happy;
+ /*UL1D*/ kal_uint8 rsn; /* Range: 0..3 */
+ /*UL1D*/ kal_uint8 delta_harq; /* Range: 0..6 */
+ /*UL1D*/ kal_uint16 tb_size;
+ /*UL1D*/ kal_uint8 *data; /* The buffer contains MAC-es/e PDU data */
+ /*UL1D*/ /* Must be 4 bytes alignment */
+ /*UL1D*/ /* NULL if tx_enable == false */
+ /*UL1D*/ kal_uint8 tebs; /* SI of UMAC */
+ /*UL1D*/ kal_uint8 re_tx_num; /* re-transmission number */
+ /*UL1D*/ kal_uint32 ScheduledGrantPayloadBits; /* Configured SG bits; for RG judgement */
+ /*UL1D*/ kal_uint32 ScheduledGrantUsedBits; /* Used SG bits; for RG judgement */
+ /*UL1D*/ kal_bool scheduled; /* Whether this is scheduled E-DCH transmission or not. */
+ /*UL1D*/
+} FDD_edch_data_ind_T;
+/*UL1D*/
+/*UL1D*//* No output parameters of FDD_umac_e_dch_tick_3() */
+/*UL1D*/
+/*UL1D*//* Input parameters of FDD_umac_e_dch_tick_3() */
+/*UL1D*/typedef struct _FDD_umac_edch_data_req_tick_3_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/
+} FDD_umac_edch_data_req_tick_3_T;
+/*UL1D*/
+/*UL1D*//* Output parameters of FDD_umac_e_dch_tick_3() */
+/*UL1D*/typedef struct _FDD_umac_edch_data_ind_tick_3_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/
+} FDD_umac_edch_data_ind_tick_3_T;
+/*UL1D*/
+/*UL1D*/extern kal_bool FDD_UL1D_Check_ASU( kal_int32 added_cell_tm/* echips */, kal_uint16 added_cell_dpch_offset /* chips */ );
+/*UL1D*/extern kal_bool FDD_UL1D_RxDualCarrier_Check( kal_uint16 pri_uarfcn, kal_uint16 sec_uarfcn, kal_int16 *pri_sec_diff );
+/*UL1D*/extern kal_bool FDD_UL1D_RxMultiCarrier_Check( kal_uint16 *uarfcn_list, kal_uint8 num_uarfcn );
+/*UL1D*/extern kal_bool FDD_UL1D_TxMultiCarrier_Check( kal_uint16 *uarfcn_list, kal_uint8 num_uarfcn );
+/*UL1D*/kal_uint16/*100kHz*/ FDD_UL1D_RRC_UlUarfcnToFrequency( kal_uint16 uarfcn );
+/**********************************************************************************************************************/
+/*********************************** UL1 Interface maintained by UL1D (End) ***************************************/
+/**********************************************************************************************************************/
+/* Input parameters of FDD_umac_e_dch_tick_5() */
+typedef struct
+{
+ kal_bool match_mac_dtx_cycle;
+ kal_uint8 long_preamble_target_cfn; // 0..255.
+ kal_uint8 long_preamble_target_subframe; // 10ms=0, 2ms=0..4.
+ FDD_edch_scell_E edch_cell;
+} FDD_etfc_eval_lpr_info_req_T;
+
+#ifdef __UMTS_R7__
+/* [R7] Enumeration of rrc state. To distinguish the usage of HS-DSCH */
+typedef enum _FDD_rrc_state_E
+{
+ FDD_CELL_DCH,
+ FDD_URA_PCH,
+ FDD_CELL_PCH,
+ FDD_IDLE_FACH,
+ FDD_CELL_FACH
+} FDD_rrc_state_E;
+
+/* [R7] Enumeration of octet aligned table 9.2.3.2 is used, else bit aligned table 9.2.3.1 is used in [25.321]. */
+typedef enum _FDD_hs_tbsize_table_E
+{
+ FDD_BIT_ALIGNED = 0,
+ FDD_OCTET_ALIGNED
+} FDD_hs_tbsize_table_E;
+
+/* [R7] Enumeration of dtx_drx_status. */
+typedef enum _FDD_dtx_drx_status_E
+{
+ FDD_DTX_DRX_OFF = 0, /* Disable CPC operation */
+ FDD_DTX_DRX_NEW_TIMING, /* Use new CPC configuration */
+ FDD_DTX_DRX_ON_REVERT, /* Uses the old CPC configuration when HHO revert. Consider oly the HS-SCCH orders which were acknowledged prior to the activation timer of the received message. */
+ FDD_DTX_DRX_ON_HS_SERV_CELL_CHANGE, /* Uses the old CPC configuration when serving cell was changed. Consider the HS-SCCH order were never received. */
+ FDD_DTX_DRX_ALL_RL_TIMING_MODIFY, /* If the CPC choice timing is ¡§continue¡¨ when receiving ALL RL TIMING MODIFY, Uses the old CPC configuration. */
+ FDD_DTX_DRX_INVALID /* Invalid DTX_DRX status */
+} FDD_dtx_drx_status_E;
+
+/* [R7] Enumeration of enabling delay. Uint is radio frame. */
+typedef enum _FDD_enabling_delay_E
+{
+ FDD_ED_0 = 0,
+ FDD_ED_1,
+ FDD_ED_2,
+ FDD_ED_4,
+ FDD_ED_8,
+ FDD_ED_16,
+ FDD_ED_32,
+ FDD_ED_64,
+ FDD_ED_128
+} FDD_enabling_delay_E;
+
+/* [R7] Enumeration of ue_dtx_cycle2_inactivity_threshold. Uint is E-DCH TTIs. */
+typedef enum _FDD_ue_dtx_cycle2_inactivity_threshold_E
+{
+ FDD_dtx_cycle2_inaTrHd_1 = 0,
+ FDD_dtx_cycle2_inaTrHd_4,
+ FDD_dtx_cycle2_inaTrHd_8,
+ FDD_dtx_cycle2_inaTrHd_16,
+ FDD_dtx_cycle2_inaTrHd_32,
+ FDD_dtx_cycle2_inaTrHd_64,
+ FDD_dtx_cycle2_inaTrHd_128,
+ FDD_dtx_cycle2_inaTrHd_256
+} FDD_ue_dtx_cycle2_inactivity_threshold_E;
+
+/* [R7] Enumeration of ue_dtx_long_preamble_length. Uint is slot. */
+typedef enum _FDD_ue_dtx_long_preamble_length_E
+{
+ FDD_slot_2 = 0,
+ FDD_slot_4,
+ FDD_slot_15,
+ FDD_slot_invalid
+} FDD_ue_dtx_long_preamble_length_E, FDD_dtx_pream_len_E;
+
+/* [R7] Enumeration of cqi_dtx_timer period. Uint is subframe. */
+typedef enum _FDD_cqi_dtx_timer_E
+{
+ FDD_subframe_0 = 0,
+ FDD_subframe_1,
+ FDD_subframe_2,
+ FDD_subframe_4,
+ FDD_subframe_8,
+ FDD_subframe_16,
+ FDD_subframe_32,
+ FDD_subframe_64,
+ FDD_subframe_128,
+ FDD_subframe_256,
+ FDD_subframe_512,
+ FDD_subframe_infinity
+} FDD_cqi_dtx_timer_E;
+
+/* [R7] Enumeration of ue_dpcch_burst. Uint is subframe. */
+typedef enum _FDD_ue_dpcch_burst_E
+{
+ FDD_burst_1 = 0,
+ FDD_burst_2,
+ FDD_burst_5
+} FDD_ue_dpcch_burst_E;
+
+/* [R7] Enumeration of mac_inactivity_threshold. Uint is E-DCH TTI. */
+typedef enum _FDD_mac_inactivity_threshold_E
+{
+ FDD_mac_inaTrHd_1 = 0,
+ FDD_mac_inaTrHd_2,
+ FDD_mac_inaTrHd_4,
+ FDD_mac_inaTrHd_8,
+ FDD_mac_inaTrHd_16,
+ FDD_mac_inaTrHd_32,
+ FDD_mac_inaTrHd_64,
+ FDD_mac_inaTrHd_128,
+ FDD_mac_inaTrHd_256,
+ FDD_mac_inaTrHd_512,
+ FDD_mac_inaTrHd_infinity
+} FDD_mac_inactivity_threshold_E;
+
+/* [R7] Enumeration of ue_rx_cycle. Uint is subframe. */
+typedef enum _FDD_ue_drx_cycle_E
+{
+ FDD_drx_cycle_4 = 0,
+ FDD_drx_cycle_5,
+ FDD_drx_cycle_8,
+ FDD_drx_cycle_10,
+ FDD_drx_cycle_16,
+ FDD_drx_cycle_20
+} FDD_ue_drx_cycle_E;
+
+/* [R7] Enumeration of ue_drx_cycle_inactivity_threshold. Uint is subframe. */
+typedef enum _FDD_ue_drx_cycle_inactivity_threshold_E
+{
+ FDD_drx_cycle_inaTrHd_0 = 0,
+ FDD_drx_cycle_inaTrHd_1,
+ FDD_drx_cycle_inaTrHd_2,
+ FDD_drx_cycle_inaTrHd_4,
+ FDD_drx_cycle_inaTrHd_8,
+ FDD_drx_cycle_inaTrHd_16,
+ FDD_drx_cycle_inaTrHd_32,
+ FDD_drx_cycle_inaTrHd_64,
+ FDD_drx_cycle_inaTrHd_128,
+ FDD_drx_cycle_inaTrHd_256,
+ FDD_drx_cycle_inaTrHd_512
+} FDD_ue_drx_cycle_inactivity_threshold_E;
+
+/* [R7] Enumeration of ue_grantMonitoring_inactivity_threshold. Uint is subframe. */
+typedef enum _FDD_ue_grantMonitoring_inactivity_threshold_E
+{
+ FDD_graMon_inaTrhd_0 = 0,
+ FDD_graMon_inaTrhd_1,
+ FDD_graMon_inaTrhd_2,
+ FDD_graMon_inaTrhd_4,
+ FDD_graMon_inaTrhd_8,
+ FDD_graMon_inaTrhd_16,
+ FDD_graMon_inaTrhd_32,
+ FDD_graMon_inaTrhd_64,
+ FDD_graMon_inaTrhd_128,
+ FDD_graMon_inaTrhd_256
+} FDD_ue_grantMonitoring_inactivity_threshold_E;
+
+/* [R7] HS-SCCH less mode status in CELL_DCH state */
+typedef enum _FDD_hs_scch_less_status_E
+{
+ FDD_HS_SCCH_LESS_OFF = 0, /* disable HS-SCCH less operation and all HS-SCCH less parameters are invalid. */
+ FDD_HS_SCCH_LESS_ON, /* use new HS-SCCH less configuration and reset order. */
+ FDD_HS_SCCH_LESS_ON_REVERT, /* Uses the old HS-SCCH less configuration when HHO revert or 3G to 2G inter-RAT procedure revert. */
+ FDD_HS_SCCH_LESS_ALL_RL_TIMING_MODIFY, /* If the HS-SCCH less operation choice timing is "continue" when receiving ALL RL TIMING MODIFY,
+ * uses the old HS-SCCH less configuration without reset order. */
+ FDD_HS_SCCH_LESS_INVALID /* SLCE internal use, won't config this enum to UL1. */
+} FDD_hs_scch_less_status_E;
+#endif /* __UMTS_R7__ */
+
+#ifdef __UMTS_R8__
+/* [R8] Enumeration of enhanced CELL_FACH DRX status */
+typedef enum _FDD_hs_cell_fach_drx_status_E
+{
+ FDD_DRX_OFF = 0, /* No DRX in CELL_FACH state or ETWS reception is on-going */
+ FDD_DRX_ON_NORMAL, /* UL1 should start CELL_FACH DRX when the normal criterion is fulfilled */
+ FDD_DRX_ON_ETWS_END, /* SLCE should set this enum when the ETWS procedure ends */
+ FDD_DRX_INVALID /* SLCE internal use. Invalid for UL1. */
+} FDD_hs_cell_fach_drx_status_E;
+
+/* [R8] inactivity timer to start HS CELL_FACH DRX */
+typedef enum _FDD_hs_t321_E
+{
+ FDD_t321_100 = 0, /* 100ms */
+ FDD_t321_200 = 1, /* 200ms */
+ FDD_t321_400 = 2, /* 400ms */
+ FDD_t321_800 = 3 /* 800ms */
+} FDD_hs_t321_E;
+
+/* Length of inactivity timer T321/T328/T329 */
+typedef enum
+{
+ FDD_EFACH_DRX_1_LEVEL,
+ FDD_EFACH_DRX_2_LEVEL
+} FDD_hs_cell_fach_drx_level_E;
+
+/* Length of inactivity timer T321/T328/T329 */
+typedef enum
+{
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_INVALID,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_20MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_40MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_60MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_80MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_100MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_200MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_400MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_500MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_800MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_1000MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_2000MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_4000MS
+} FDD_hs_cell_fach_drx_status_timer_length_E;
+
+/* Length of EFACH DRX cycle */
+typedef enum
+{
+ FDD_EFACH_DRX_CYCLE_LEN_INVALID,
+ FDD_EFACH_DRX_CYCLE_LEN_2_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_4_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_8_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_16_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_32_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_64_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_128_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_256_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_512_FRAMES
+} FDD_hs_cell_fach_drx_cycle_E;
+
+/* Length of EFACH DRX burst */
+typedef enum
+{
+ FDD_EFACH_DRX_BURST_LEN_INVALID,
+ FDD_EFACH_DRX_BURST_LEN_1_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_2_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_4_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_8_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_16_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_2_SUBFRAMES,
+ FDD_EFACH_DRX_BURST_LEN_4_SUBFRAMES
+} FDD_hs_cell_fach_drx_rx_burst_E;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/* [R8] variable to control UL1 DC HS-DSCH receiving */
+typedef enum _FDD_dc_hsdpa_status_E
+{
+ FDD_DC_HSDPA_OFF = 0, /* Disable DC-HSDPA operation and all DC-HSDPA parameters are invalid. */
+ FDD_DC_HSDPA_ON, /* Use new DC-HSDPA configuration and reset order */
+ FDD_DC_HSDPA_ON_REVERT, /* Uses the old DC-HSDPA configuration when HHO revert or 3G to 2G inter-RAT procedure revert. */
+ FDD_DC_HSDPA_ALL_RL_TIMING_MODIFY, /* If the DC-HSDPA choice timing is "continue" when receiving ALL_RL_TIMING_MODIFY,
+ * uses the old DC-HSDPA configuration without reset order. */
+ FDD_DC_HSDPA_ON_WITHOUT_RESET_ORDER, /* Use new DC-HSDPA configuration and do not reset order */
+ FDD_DC_HSDPA_INVALID /* SLCE internal use, won't config this enum to UL1 */
+} FDD_dc_hsdpa_status_E;
+
+/* [R8] Specify that E-DCH transmission is in dedicated state or common state */
+typedef enum _FDD_edch_transmission_type_E
+{
+ FDD_EDCH_IN_DCH_STATE = 0, /* E-DCH allocated in dedicated state */
+ FDD_EDCH_IN_COMMON_STATE /* E-DCH allocated in common state */
+} FDD_edch_transmission_type_E;
+
+/* [R8] common E-DCH suspend cause. UL1 Internal use */
+typedef enum _FDD_cedch_suspend_cause_type_E
+{
+ FDD_CEDCH_NONE = 0, /* no common EDCH */
+ FDD_CEDCH_SUSPEND_RLF, /* common EDCH terminate due to RLF */
+ FDD_CEDCH_SUSPEND_SYNCAA_FAIL, /* common EDCH terminate due to Sync AA failure */
+ FDD_CEDCH_SUSPEND_PROCESS_TERMINATION, /* common EDCH terminate from UMAC */
+ FDD_CEDCH_SUSPEND_PREAMBLE, /* common EDCH terminate when AI result has not been received by UL1C */
+ FDD_CEDCH_SUSPEND_CHANNEL_RELEASE /* common EDCH terminate due to channel release */
+} FDD_cedch_suspend_cause_type_E;
+
+/* [R8] Transport channel type in random access procedure */
+typedef enum _FDD_cell_fach_ul_trch_type_E
+{
+ FDD_CELL_FACH_UL_TRCH_TYPE_RACH = 0, /* random access attemp for RACH transmission */
+ FDD_CELL_FACH_UL_TRCH_TYPE_EDCH /* random access attemp for E-DCH transmission */
+} FDD_cell_fach_ul_trch_type_E;
+#endif /* __UMTS_R8__ */
+
+
+#ifdef __UMTS_R7__
+typedef struct _FDD_hs_scch_less_info_T
+{
+ FDD_hs_scch_less_status_E hs_scch_less_status; /* HS-SCCH less mode control flag */
+ kal_uint8 hs_scch_less_hspdsch_code_index; /* [Range] Integer(1..15) Index of the first HS-PDSCH code */
+ FDD_hs_tb_size_list_T hs_scch_less_tb_size_list[FDD_MAX_SCCH_LESS_BLK_NUM]; /* 1..<maxHSSCCHLessTrBlk > maxHSSCCHLessTrBlk = 4 */
+} FDD_hs_scch_less_info_T;
+
+typedef struct _FDD_hs_fach_pch_rl_info_T
+{
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */
+ /* If the value of tm is not equal to -1, UL1 will use this value */
+ /* If the value of tm is equal to -1, UL1 will not use this value */
+ kal_int16 rscp; /* Serving cell RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
+} FDD_hs_fach_pch_rl_info_T;
+
+typedef struct _FDD_hs_dtx_drx_timing_info_T
+{
+ FDD_enabling_delay_E ED; /* Time threshold the UE waits until enabling a new timing pattern for DTX/ DRX operation. Uint is radio frame. */
+ kal_uint8 ue_dtx_drx_offset; /* [Range]: 0~159 Units of subframes. Offset of the DTX and DRX cycles at the given TTI. */
+} FDD_hs_dtx_drx_timing_info_T;
+
+typedef struct _FDD_hs_dtx_param_T
+{
+ kal_bool ue_dtx_on; /* DTX operation enable/ disable */
+ kal_bool tti_change; /* E-DCH TTI is change to 2ms->10ms or 10ms->2ms */
+ kal_uint8 ue_dtx_cycle1; /* DPCCH activity pattern.(1, 5, 10, 20 subframes for 10 ms TTI; 1, 4, 5, 8, 10, 16, 20 subframes for 2 ms TTI) */
+ kal_uint8 ue_dtx_cycle2; /* DPCCH activity pattern.(5, 10, 20, 40, 80, 160 subframes for 10 ms TTI;4, 5, 8, 10, 16, 20, 32, 40, 64, 80, 128, 160 subframes for 2 ms TTI) */
+ FDD_ue_dtx_cycle2_inactivity_threshold_E cycle2_inactivity_threshold; /* When to activate the UE DTX cycle 2 after the last uplink data transmission */
+ FDD_ue_dtx_long_preamble_length_E preamble_length; /* Uplink preamble length. Units of slots.Default value is 2 slots */
+ FDD_cqi_dtx_timer_E timer_length; /* Number of subframes after an HS-DSCH reception during which the CQI reports have higher priority than the DTX pattern and are transmitted according to the regular CQI pattern */
+ FDD_ue_dpcch_burst_E dpcch_burst1; /* Length of DPCCH transmission when UE DTX cycle 1 is active Units of sub-frames */
+ FDD_ue_dpcch_burst_E dpcch_burst2; /* Length of DPCCH transmission when UE DTX cycle 2 is active Units of sub-frames */
+
+ kal_uint8 mac_dtx_cycle; /* Pattern of time instances where the start of uplink E-DCH transmission after inactivity is allowed.(5, 10, 20 subframes for 10 ms TTI; 1, 4, 5, 8, 10, 16, 20 subframes for 2 ms TTI */
+ FDD_mac_inactivity_threshold_E mac_inactivity_threshold; /* E-DCH inactivity time after which the UE can start E-DCH transmission only at given time. */
+} FDD_hs_dtx_param_T;
+
+typedef struct _FDD_hs_drx_param_T
+{
+ kal_bool ue_drx_on; /* DRX operation enable/ disable */
+ FDD_ue_drx_cycle_E drx_cycle_length; /* HS-SCCH reception pattern, i.e. how often UE has to monitor HSSCCH. */
+ FDD_ue_drx_cycle_inactivity_threshold_E drx_cycle_inactivity_threshold; /* Number of subframes after downlink activity where UE has to continuously monitor HS-SCCH. Units of subframes */
+ FDD_ue_grantMonitoring_inactivity_threshold_E grantMonitoring_inactivity_threshold; /* Number of subframes after uplink activity when UE has to continue to monitor E-AGCH/E-RGCH. Units of E-DCH TTIs. */
+ kal_bool ue_drx_grantMonitoring; /* whether the UE is required to monitor E-AGCH/E-RGCH when they overlap with the start of an HS-SCCH reception as defined in the HS-SCCH reception pattern */
+} FDD_hs_drx_param_T;
+
+typedef struct _FDD_hs_dtx_drx_info_T
+{
+ FDD_dtx_drx_status_E status;
+ FDD_hs_dtx_drx_timing_info_T timing;
+ FDD_hs_dtx_param_T hs_dtx_param;
+ FDD_hs_drx_param_T hs_drx_param;
+} FDD_hs_dtx_drx_info_T;
+
+typedef struct _FDD_hs_cell_pch_state_info_T
+{
+#ifdef UL1_PHASE3_TEST
+ kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+ kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#else
+// kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+// kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#endif
+ FDD_pich_info_T pich_info;
+ kal_uint8 pcch_hspdsch_ovsf; /* [Range] Integer (0..15) HS-PDSCH channel associated with the PICH for HSSCCH less PAGING TYPE 1 message transmission. */
+ kal_uint8 num_of_pcch_trans; /* [Range] Integer (1..5) number of subframes used to transmit the PAGING TYPE 1. */
+ kal_int8 pcch_tb_size_index[2]; /* [Range] Integer (1..32). -1 if this is invalid. Index of value range 1 to 32 of the MAC-ehs transport block size as described in appendix A of 25.321. */
+ FDD_hs_fach_pch_rl_info_T fach_pch_rl_info;
+} FDD_hs_cell_pch_state_info_T;
+
+typedef struct _FDD_hs_cell_fach_state_info_T
+{
+#ifdef UL1_PHASE3_TEST
+ kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+ kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#else
+// kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+// kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#endif
+ FDD_hs_fach_pch_rl_info_T fach_pch_rl_info;
+} FDD_hs_cell_fach_state_info_T;
+
+typedef struct _FDD_hs_cell_dch_state_info_T
+{
+ kal_bool dl_64QAM_on; /* 64QAM enable/disable */
+ FDD_hs_tbsize_table_E hsdsch_tbsize_table; /* If this IE is present, octet aligned table [25.321] is used, else bit aligned table [25.321] is used.
+ In DCH state, this field is assigned by SLCE. Otherthan DCH state, UL1 should use octet-aligned table by itself.*/
+} FDD_hs_cell_dch_state_info_T;
+
+typedef union _FDD_hspdsch_state_info_T
+{
+ FDD_hs_cell_pch_state_info_T cell_pch; /* The parameters in CELL_PCH or URA state. */
+ FDD_hs_cell_fach_state_info_T cell_fach; /* The parameters in CELL_FACH or IDLE_FAC state. */
+ FDD_hs_cell_dch_state_info_T cell_dch; /* The parameters in CELL_DCH state. */
+} FDD_hspdsch_state_info_T;
+
+#ifdef __UMTS_R8__
+typedef struct _FDD_hs_cell_fach_drx_T
+{
+ kal_bool interrupt_by_hsdsch; /* TRUE : the DRX operation can be interrupted by HS-DSCH data. */
+ /* FALSE: the DRX operation cannot be interrupted by HS-DSCH data. */
+ FDD_hs_cell_fach_drx_status_E hs_cell_fach_drx_status; /* enhanced CELL_FACH DRX status */
+ FDD_hs_cell_fach_drx_level_E drx_level; /* 1-level DRX or 2-level DRX cycle is used */
+ /* When NW configures R8 DRX pattern, SLCE will configure 2nd-level DRX parameters only
+ and set 1st-level DRX parameters as invalid */
+ FDD_hs_cell_fach_drx_status_timer_length_E second_timer_length; /* Inactivity timer to start 1-level HS CELL_FACH DRX. Set from T321(SIB5) or T329 (SIB22) */
+ FDD_hs_cell_fach_drx_cycle_E second_drx_cycle_length; /* HS CELL_FACH DRX cycle length during the 2nd DRX operation */
+ FDD_hs_cell_fach_drx_rx_burst_E second_drx_burst_length; /* the period within the 2nd HS DRX cycle that the UE continuously receive */
+ FDD_hs_cell_fach_drx_status_timer_length_E first_timer_length; /* Inactivity timer to start 2-level HS CELL_FACH DRX. Set from T321(SIB5) or T328 (SIB22) */
+ FDD_hs_cell_fach_drx_cycle_E first_drx_cycle_length; /* HS CELL_FACH DRX cycle length during the 1st DRX operation */
+ FDD_hs_cell_fach_drx_rx_burst_E first_drx_burst_length; /* The period within the 1st HS DRX cycle that the UE continuously receive */
+} FDD_hs_cell_fach_drx_T;
+
+typedef struct _FDD_secondary_hspdsch_info_T
+{
+ kal_bool dl_64QAM_on; /* If 64QAM supported in secondary HS-DSCH */
+ kal_uint16 h_rnti; /* h_rnti to decode secondary HS-DSCH receiving */
+ FDD_hs_tbsize_table_E hsdsch_tbsize_table; /* If dl_64QAM_on = KAL_TRUE, hsdsch_tbsize_table should be FDD_OCTET_ALIGNED. */
+} FDD_secondary_hspdsch_info_T;
+
+#define FDD_DC_HSDPA_ALL_CONFIG_BIT 0x7F
+typedef struct _FDD_dc_hsdpa_info_T
+{
+ kal_uint8 modify_field; /* Bit 0: FDD_hs_scch_info_T
+ * Bit 1: FDD_secondary_hspdsch_info_T
+ * Bit 2: psc
+ * Bit 3: meas_po
+ * Bit 4: dl_freq
+ * Bit 5: sttd
+ * Bit 6: dpch_offset */
+ FDD_dc_hsdpa_status_E dc_hsdpa_status; /* variable to control UL1 DC HS-DSCH receiving */
+ FDD_hs_scch_info_T hs_scch_info; /* Secondary HS-SCCH info. */
+ FDD_secondary_hspdsch_info_T sec_h_info; /* Secondary HS-PDSCH info. */
+ kal_uint16 psc; /* Primary scrambling code used in secondary H cell*/
+ kal_int8 meas_po; /* Measurement power offset, step = half dB. Range = -12~26 (-6dB~13dB)*/
+ kal_uint16 dl_freq; /* DL UARFCN, 0~16383*/
+ kal_bool sttd; /* TRUE: STTD is used for P-CPICH of the secondary cell
+ * FALSE: STTD is not used for P-CPICH of the secondary cell.*/
+#ifdef __UMTS_R9__
+ kal_uint8 dpch_offset; /* [R9] f-dpch offset of 2nd freq when DC-HSUPA is configured,
+ otherwise invalid value 0xFFFF is configured. (0~38144 chips by step of 256 )
+ [R10] For additional dc-hsdpa (dc_hsdpa_info[1]/dc_hsdpa_info[2]), this is always invalid value 0xFFFF. */
+#endif /*__UMTS_R9__*/
+} FDD_dc_hsdpa_info_T;
+
+typedef struct _FDD_dl_pc_info_T /* DL power control information used for common E-DCH */
+{
+ kal_uint8 tpc_target; /* range: 1~10, the actual TPC command error rate target is tpc_target/100 */
+ kal_uint8 dpc_mode; /*DL Power control mode. 0 or 1 or 2. In current spec, SLCE will always fix this field by 0 for common E-DCH. */
+ kal_uint8 fdpch_slot_format; /* range: 0~9. In current spec, SLCE will always fix this field by 0 for common E-DCH. */
+} FDD_dl_pc_info_T;
+
+typedef struct _FDD_ul_dpch_code_info_T /* UL DPCH information used for common E-DCH transmission */
+{
+ FDD_sc_type_E sc_type; /* short type or long type scrambling code */
+ kal_uint32 sc_code; /* 0 ~ 16777215 */
+} FDD_ul_dpch_code_info_T;
+
+typedef struct _FDD_edch_resource_list_T
+{
+ kal_uint8 s_offset; /* symbol offset. range: 0~9 */
+ kal_uint8 fdpch_ovsf; /* 0 ~ 255 */
+ kal_uint8 ehirgch_ovsf; /* ovsf code for receiving E-HICH and E-RGCH in common E-DCH transmission */
+ kal_uint8 hich_signature_seq; /* E-HICH signature sequence in common E-DCH transmission [Range: 0~39] */
+ kal_uint8 rgch_signature_seq; /* E-RGCH signature sequence in common E-DCH transmission [Range: 0~39, 0xff means invalid. No need to decode E-RGCH] */
+ FDD_ul_dpch_code_info_T ul_dpch_code_info; /* UL DPCH information used for common E-DCH transmission */
+} FDD_edch_resource_list_T;
+
+typedef struct _FDD_common_edch_info_T
+{
+ kal_uint8 add_tran_back_off; /* 0 ~ 15, unit is TTI */
+ kal_uint8 edch_resource_num; /* 1~32 */
+ FDD_edch_resource_list_T edch_resource_list[32]; /* common RLs for E-DCH transmission */
+ FDD_ul_pc_info_T ul_pc; /* ul power control info. */
+} FDD_common_edch_info_T;
+
+typedef struct _FDD_edch_specific_info_T
+{
+ kal_bool e_ai_ind; /* TRUE: E-AI should be used. FALSE: E-AI should not be used. */
+ kal_int8 po_p_e; /* -5 ~ 10 dB, power offset between last TX preamble and initial DPCCH */
+} FDD_edch_specific_info_T;
+
+
+typedef struct
+{
+ kal_bool d_hrnti_valid;
+ kal_uint16 d_hrnti;/*dH-RNTI*/
+
+ kal_bool c_hrnti_valid;
+ kal_uint16 c_hrnti;/*cH-RNTI*/
+
+ kal_bool b_hrnti_valid;
+ kal_uint16 b_hrnti;/*cH-RNTI*/
+
+} FDD_hs_hrnti_info_T;
+
+
+#ifdef __UMTS_R9__
+
+typedef enum
+{
+ FDD_DC_HSUPA_OFF, /* disable DC-HSUPA operation and all DC-HSUPA parameters are invalid */
+ FDD_DC_HSUPA_ON, /* use new DC-HSUPA configuration and reset order.
+ The default status is deactivated until receiving HS-SCCH order to activate,
+ and don't need sync A procedure on 2nd freq. */
+ FDD_DC_HSUPA_ALL_RL_TIMING_MODIFY, /* If the DC-HSUPA choice timing is "continue" when receiving ALL_RL_TIMING_MODIFY,
+ SLCE uses the old DC-HSUPA configuration to UL1, and UL1 applies the configuration without reset order.
+ Do not apply sync A procedue no matter the DC-HSUPA status after E-DCH setup. */
+ FDD_DC_HSUPA_ON_WITHOUT_RESET_ORDER, /* Use new DC-HSUPA configuration and do not reset order.
+ Sync A will need if DC-HSUPA is activate after E-DCH setup, but not for E-DCH modify. */
+ FDD_DC_HSUPA_INVALID /* SLCE internal use, won't config this enum to UL1 */
+
+} FDD_dc_hsupa_status_E;
+
+typedef enum
+{
+ FDD_DC_HSUPA_MODIFY_NORMAL_CONFIG, /* Normal configuration */
+ FDD_DC_HSUPA_MODIFY_ASU, /* ASU configuration. */
+ FDD_DC_HSUPA_MODIFY_ALL_ACTIVE_SET, /* All active set cell change (RBR) */
+ FDD_DC_HSUPA_MODIFY_NUM
+} FDD_dc_hsupa_modify_type_E;
+
+
+typedef struct
+{
+ kal_bool pri_e_rnti_valid; /* Indicate if pri_e_rnti field is valid */
+ kal_uint16 pri_e_rnti; /* Primary E-RNTI assigned to UE */
+ kal_bool sec_e_rnti_valid; /* Indicate if sec_e_rnti field is valid */
+ kal_uint16 sec_e_rnti; /* Secondary E-RNTI assigned to UE */
+} FDD_sec_e_rnti_info_T;
+
+typedef struct
+{
+ kal_uint16 ul_freq; /* UL UARFCN */
+ kal_uint16 dl_freq; /* DL UARFCN */
+ FDD_sc_type_E sc_type; /* Type of scrambling code */
+ kal_uint32 sc_code; /* Scrambling code #. 0 ~ 16777215 */
+ FDD_beta_ed_reduced_min_E beta_ed_reduced_min; /* Minimum reduced E-DPDCH gain factor.
+ If not configured in RRC message, SLCE should set the default value "FDD_beta_ed_8_15". */
+ kal_uint8 dpcch_po_SecondaryULFrequency; /* power offset. Integer (0..7 by step of 1) */
+ kal_uint8 pc_pream; /* Power control Preamble. 0 ~ 7 frames */
+} FDD_sec_edch_info_common_T;
+
+#define FDD_DC_HSUPA_ALL_CONFIG_BIT 0x7F
+
+typedef struct
+{
+ /*** mandatory configuration ***/
+ FDD_dc_hsupa_status_E dc_hsupa_status; /* variable to control UL1 DC-HSUPA receiving */
+ FDD_dc_hsupa_modify_type_E modify_type; /* DC-HSUPA modify type */
+ kal_int16 edch_serv_rscp; /* RSCP of secondary edch serving cell. Range: -464 ~ -100 dBm.
+ SLCE always sets RSCP value from DB_cell without comparison.*/
+ /*** optional configuration ***/
+ kal_uint8 config_field; /* Indicates the configured field:
+ Bit 0: sec_e_rnti_info
+ Bit 1: sec_edch_info_common
+ Bit 2: dl_dpch_rl_delete/dl_dpch_rl_add
+ Bit 3: edch_serv_psc
+ Bit 4: eagch_info
+ Bit 5: ehich_info
+ Bit 6: ergch_info
+ All field must be configured when switching DC-HSUPA OFF to ON. */
+ /* Bit 0: sec_e_rnti_info */
+ FDD_sec_e_rnti_info_T sec_e_rnti_info; /* [TS25.331]10.3.6.116 Secondary serving E-DCH cell info */
+ /* Bit 1: sec_edch_info_common */
+ FDD_sec_edch_info_common_T sec_edch_info_common; /* [TS25.331]10.3.6.117 Secondary E-DCH info common */
+ /* Bit 2: dl_dpch_rl_delete/dl_dpch_rl_add */
+ kal_uint8 dl_dpch_rl_delete_num; /* Number of RL to be removed: 0~FDD_MAX_EDCH_RL */
+ kal_uint16 dl_dpch_rl_delete[FDD_MAX_EDCH_RL]; /* RL to be removed (PSC) */
+ kal_uint8 dl_dpch_rl_add_num; /* Number of DL DPCH RL to be added: 0~FDD_MAX_EDCH_RL */
+ FDD_dl_dpch_rl_T dl_dpch_rl_add[FDD_MAX_EDCH_RL]; /* DL DPCH info. for each RL.
+ If modify_type != ASU, dl_dpch_rl_add is the full set of DL DPCH RL info. */
+ /* Bit 3: edch_serv_psc */
+ kal_uint16 edch_serv_psc; /* serving E-DCH cell */
+ /* Bit 4: eagch_info */
+ FDD_eagch_info_T eagch_info; /* E-AGCH info */
+ /* Bit 5: ehich_info */
+ kal_uint8 ehich_info_num; /* Number of E-HICH info: 1~FDD_MAX_EDCH_RL */
+ FDD_ehich_info_T ehich_info[FDD_MAX_EDCH_RL]; /* E-HICH info */
+ /* Bit 6: ergch_info */
+ kal_uint8 ergch_info_num; /* Number of E-RGCH info: 0~FDD_MAX_EDCH_RL */
+ FDD_ergch_info_T ergch_info[FDD_MAX_EDCH_RL]; /* E-RGCH info */
+
+} FDD_dc_hsupa_info_T;
+
+#endif /* __UMTS_R9__ */
+#endif /* __UMTS_R8__ */
+#endif /* __UMTS_R7__ */
+
+#if defined (__L1_STANDALONE__ )
+/*HsDsch check Interface*/
+typedef struct
+{
+ kal_bool is_hsscch_result_valid ; // need each tti hsscch result
+ kal_bool is_valid_data ; // need each tti hspdsch result
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint8 s_drx;// need each subframe number
+ kal_bool is_scheduled;//need each tti scheduling information
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ kal_bool is_in_gap; // is current tti is gap
+ kal_bool is_postpone;// is postpone condition
+ kal_uint8 ndi;// is new data or retransmission (1: new data, 0: retransmssion)
+
+} FDD_IF_HSDSCH_PARAM_T;
+typedef struct
+{
+ kal_bool is_valid_data;// need each tti result
+ kal_uint8 ag_value;// need each tti result
+ kal_uint8 ag_scope;// need each tti result
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint8 s_drx;// need each subframe number
+ kal_bool is_tti_2ms;// need each tti result
+ kal_bool is_scheduled;//need each tti scheduling information
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ kal_bool is_in_gap;// is current tti is gap ,current test is without gap
+ FDD_edch_scell_E ecell_type;
+} FDD_IF_EAGCH_PARAM_T;
+typedef struct
+{
+ kal_uint8 e_rgch_result_serving; // need each tti result
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint8 s_drx;// need each subframe number
+ kal_bool is_tti_2ms;// need each tti result
+ kal_bool is_scheduled;// need each tti result
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ kal_bool is_in_gap;// is current tti is gap, current test is without gap
+ FDD_edch_scell_E ecell_type;
+} FDD_IF_ERGCH_PARAM_T;
+typedef struct
+{
+
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint16 scheduled_bimap;//need each slot result
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ FDD_edch_scell_E ecell_type;
+
+} FDD_IF_ULDPCCH_PARAM_T;
+#endif /*__L1_STANDALONE__*/
+
+typedef enum
+{
+ RAS_INVALID,
+ RAS_PATH_MAIN,
+ RAS_PATH_BOTH
+} RAS_PATH_T;
+
+typedef enum
+{
+ CS_PS_INVALID,
+ CS_ONLY,
+ CS_PS_BOTH,
+ PS_ONLY
+} FDD_IS_CS_PS;
+
+typedef struct
+{
+ kal_uint8 numElements;
+ kal_uint8 elements[NUM_MCC_MNC];
+} FDD_MCC_MNC_T;
+
+typedef struct
+{
+ FDD_MCC_MNC_T mcc;
+ FDD_MCC_MNC_T mnc;
+} FDD_PLMN_IDENTITY_T;
+
+typedef struct
+{
+ kal_uint8 cell_plmn_num;
+ FDD_PLMN_IDENTITY_T cell_plmn_info[NUM_PLMN_INFO];
+ kal_uint16 lac;
+ kal_uint16 rac;
+ kal_int16 cellidx;
+} FDD_PLMN_LAC_PARAM_T;
+typedef struct
+{
+ kal_uint8 radio_bearer_ID;
+ kal_uint32 rx_window_size;
+} FDD_RLC_WINDOW_SIZE_INFO_T;
+
+#endif
diff --git a/mcu/interface/l1/ul1/internal/ul1_protected_cnst.h b/mcu/interface/l1/ul1/internal/ul1_protected_cnst.h
new file mode 100644
index 0000000..f751c4f
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ul1_protected_cnst.h
@@ -0,0 +1,130 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_protected_cnst.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * Layer 1 related constant and enum definitions for MediaTek WCDMA software
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _UL1_PROTECTED_CNST_H
+#define _UL1_PROTECTED_CNST_H
+
+/*-------- BCH related constant ----------------------*/
+#define FDD_MIN_DECODE_FRAMES 2 /* SFN/SFN_MEAS mini decode frame */
+
+/*-------- TrCH related constant (For UL/DL 384Kbps capability) ----------------------*/
+#define FDD_MAX_DL_TFs 64 /* Maximum numbre of TFs per DL CCTrCH */
+#define FDD_MAX_UL_DATA 829 /* Maximum UL transport block array size. */
+
+/*-------- PhyCh related constant (For UL/DL 384Kbps capability) ----------------------*/
+#define FDD_MAX_RL_SYNC_STATUS 6 /* Maximum number of radio link sync status */
+
+#define FDD_MIN_FS_PRIORITY_LEVEL 2 /* Minimum number of FS priority level */
+
+
+#define FDD_MAX_PLMN_PER_LOCATION 15 /*Max possible PLMN IDs that can be detected in a given location*/
+#define FDD_MAX_PLMN_LIST_FILTER ( FDD_MAX_PLMN_PER_LOCATION * FDD_MAX_FREQ_EXCLUDE )
+#define FDD_MAX_MEAS_EVENT 8 /* Maximum number of measurement events */
+#define FDD_MAX_CPICH_MEAS_CELL 16 /* Maximum cell that can be reported in CPICH report */
+
+#ifdef __UMTS_R10_UL1__
+#define FDD_MAX_UMTS_ADJ_FREQ ( 1 + FDD_MAX_ADDI_DC_HSDPA ) /* Maximum number of ADJ frequency supported in a UMTS UE */
+#elif defined(__UMTS_R8__)
+#define FDD_MAX_UMTS_ADJ_FREQ 1 /* Maximum number of ADJ frequency supported in a UMTS UE */
+#else
+#define FDD_MAX_UMTS_ADJ_FREQ 0 /* Maximum number of ADJ frequency supported in a UMTS UE */
+#endif
+
+#define FDD_MAX_UMTS_INTRA_FREQ 1 /* Maximum number of intra frequency supported in a UMTS UE */
+#define FDD_MAX_UMTS_INTER_FREQ 2 /* Maximum number of inter frequency supported in a UMTS UE */
+
+#define FDD_REPORT_INFINITY 0xff /* Tx_power measurement report number infinity*/
+#define FDD_UMTS_FDD_MLL1_INFINITE_GAP ( -1 ) /* Infinite length of standby gap */
+
+/* For cell measurement clipping */
+#define FDD_RSCP_LOWER_BOUND ( -480 ) /* CSD limit= -508, but upper lauer request -480 */
+#define FDD_RSCP_UPPER_BOUND ( -20 )
+#define FDD_RSSI_LOWER_BOUND ( -480 )
+#define FDD_RSSI_UPPER_BOUND ( -20 )
+#define FDD_EcN0_LOWER_BOUND ( -100 )
+#define FDD_EcN0_UPPER_BOUND 0
+
+/* For EM reporting */
+#define FDD_EM_RSSI_ABNORMAL_LOWER_BOUND ( -468 ) // -117, mapping to RSSI_ABNORMAL_LOWER_BOUND defined in Wcore.h
+
+#define FDD_EM_REPORTING_RSSI_INVALID ( -255 )
+#define FDD_EM_REPORTING_RSCP_INVALID ( -255 )
+
+#define FDD_INVALID_INT8 (0x80) /* -128 */
+#define FDD_INVALID_UINT8 (0xFF)
+#define FDD_INVALID_INT16 (0x8000) /* -32768 */
+#define FDD_INVALID_UINT16 (0xFFFF)
+#define FDD_INVALID_INT32 (0x80000000) /* -2147483648 */
+#define FDD_INVALID_UINT32 (0xFFFFFFFF)
+
+#define UL1_EXTENDED_LCE_MODE0 (0)
+#define UL1_EXTENDED_LCE_MODE1 (1)
+#define UL1_EXTENDED_LCE_MODE2 (2)
+
+/*-------- Activation time related constant ----------------------*/
+#define FDD_INVALID_ACTT (kal_int16)0x7FFF /* Invalid activation time */
+
+/*-------- [R5R6] HS-DSCH related ----------------------*/
+#define FDD_MAX_SCCH_LESS_BLK_NUM 4
+#define FDD_MAX_DELTA_HARQ_NUM 7 /* 25.213 s4.2.1.3 tbl 1B.3 */
+#define FDD_MAX_SEC_FDPCH_RL 4
+#define FDD_HS_SECONDARY_CELL_NUM (FDD_MAX_SUPPORT_CELL-1)
+
+
+/*-------- TX Power Measurement related constant ----------------------*/
+#define FDD_MAX_TXP_REACHED 0x15555555 /* Criterion for max TX power reached: all slots in a frame reach max TX power. */
+#define FDD_MIN_TXP_REACHED 0x3FFFFFFF /* Criterion for min TX power reached: all slots in a frame reach min TX power. */
+#define FDD_MAX_MIN_TXP_SKIPPED 0x2AAAAAAA /* During CPC, if all slots are TX off or only DPCCH is transmitted. This frame is not counted for Max or Min Tx event criteria. */
+
+#endif
+
diff --git a/mcu/interface/l1/ul1/internal/ul1_protected_def.h b/mcu/interface/l1/ul1/internal/ul1_protected_def.h
new file mode 100644
index 0000000..89816a1
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ul1_protected_def.h
@@ -0,0 +1,68 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_protected_def.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * This file contains typedef, definition prototypes only used by L1
+ ****************************************************************************/
+
+#ifndef _UL1_PROTECTED_DEF_H
+#define _UL1_PROTECTED_DEF_H
+
+/* auto add by kw_check begin */
+#include "ul1_cnst.h"
+#include "kal_general_types.h"
+/* auto add by kw_check end */
+
+#include "gmss_public.h"
+
+#if defined(UL1_TX_PHASE3_TEST)
+#define UL1_TX_PHASE3_TEST_TK6291_ADD 1
+#define UL1_TX_PHASE3_TEST_TK6291_TODO 0
+#define UL1_TX_PHASE3_TEST_TK6291_REMOVE 0
+#endif
+
+
+#endif
diff --git a/mcu/interface/l1/ul1/internal/ul1_struct.h b/mcu/interface/l1/ul1/internal/ul1_struct.h
new file mode 100644
index 0000000..440893a
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/ul1_struct.h
@@ -0,0 +1,3897 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_struct.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * Layer 1 and Protocol Stack message and callback function definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _UL1_STRUCT_H
+#define _UL1_STRUCT_H
+
+/* auto add by kw_check begin */
+#include "ul1_def.h"
+#include "kal_general_types.h"
+#include "ul1_cnst.h"
+/*#include "ul1tst_msg.h"*/
+#include "kal_public_defs.h" //MSBB change #include "stack_msgs.h"
+#include "kal_public_api.h" //MSBB change #include "app_ltlcom.h"
+/* auto add by kw_check end */
+#include "em_public_struct.h"
+
+#include "global_type.h" /* [UBin] For inclusion of erac_rat_enum */
+#include "mll1_umts_fdd.h" /* umts_fdd_dch_gap_struct */
+#if !defined(__XL1SIM__)
+#include "rsvak_public_enum.h" /* for freq_scan_type_enum */
+#endif
+
+#if defined(__ATERFTX_ERROR_HANDLE_ENHANCE__)
+#include "ps_public_enum.h" /*for error cause in AT+ERFTX EM changes*/
+#endif //__ATERFTX_ERROR_HANDLE_ENHANCE__
+
+/*****************************************************************************
+Request from 3G PS
+*****************************************************************************/
+typedef struct _fdd_cphy_bch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. should -1 (Immediate) */
+ kal_int16 rx_sfn; /* SFN for start BCH. -1 ~ 4095. -1 means immedaite */
+ kal_int32 tm; /* LST of the cell boundary. 0 ~ 38400*8-1 */
+ kal_int16 off; /* Frame # offset to LST. -1 ~ 4095. -1 means unknown */
+ kal_bool sfn_only; /* Only read SFN */
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_bool sttd; /* STTD setting */
+ kal_int8 sib7_index; /* Indicate which SIB Info in sib_list is SIB7 */
+ /* -1 means there is not SIB7 in the list */
+ kal_uint16 sib7_rep_cycle; /* 2 ~ 256. The meaning of sib7_rep_cycle becomes "SIB7 expiration timer / SIP_REP" */
+ /* The true value is 2^sib7_rep_cycle. */
+ kal_bool servingcell; /* MTK not used */
+ FDD_bch_priority_E bch_priority; /* Priority of this BCH */
+ kal_uint8 priority_level;
+ kal_uint8 sib_num; /* # of SIB to be read, 0 means all SIBs reception.*/
+ FDD_sib_info_T sib_list[FDD_MAX_SIB_PATTERN]; /* SIB information */
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ kal_uint16 priority_index; /*Priority_index for same priority channel in 3G Gemini project*/
+#endif
+
+ kal_bool is_auto_gap_support; /* this bch req is for rptCGI */
+
+} fdd_cphy_bch_setup_req_struct;
+
+typedef struct _fdd_cphy_bch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 4095. -1 means immediate */
+ kal_int16 rx_sfn; /* SFN for start BCH. -1 ~ 4095. -1 means immedaite */
+ kal_uint8 modify_flag; /* 0x01 : bch_priority is changed */
+ /* 0x02 : SIB information is changed */
+ /* 0x03 : Both bch_priority and SIB information are changed */
+ /*0x04: priority idx*/
+ kal_int8 sib7_index; /* Indicate which SIB Info in sib_list is SIB7 */
+ /* -1 means there is not SIB7 in the list */
+ kal_uint16 sib7_rep_cycle; /* 2 ~ 256. The meaning of sib7_rep_cycle becomes "SIB7 expiration timer / SIP_REP" */
+ /* The true value is 2^sib7_rep_cycle. */
+
+ FDD_bch_priority_E bch_priority; /* Priority of this BCH */
+ kal_uint8 priority_level;
+ kal_uint8 sib_num; /* # of SIB to be read */
+ FDD_sib_info_T sib_list[FDD_MAX_SIB_PATTERN]; /* SIB Information */
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ kal_uint16 priority_index; /*Priority_index for same priority channel in 3G Gemini project*/
+#endif
+
+} fdd_cphy_bch_modify_req_struct;
+
+typedef struct _fdd_cphy_bch_release_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_release_req_struct;
+
+typedef struct _fdd_cphy_pch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+ kal_bool is_CSFB; /* to specify this PCH setup is for CSFB redirection */
+ FDD_FACH_PCH_Info_T fach_pch_info; /* Channel information */
+} fdd_cphy_pch_setup_req_struct;
+
+typedef struct _fdd_cphy_pch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ FDD_pich_reconfig_type_E reconfig_type;
+ FDD_pich_drx_T pich_drx; /* Modified DRX information */
+#ifdef __SMART_PAGING_3G_FDD__
+ FDD_pich_smartpaging_T smartpaging_info;
+#endif
+#ifdef __UMTS_R7__
+ FDD_pich_drx_T pich_drx_cycle2; /* DRX parameters 2 for PICH. */
+ kal_uint16 drx_cycle2_time; /* if it's not 0. UL1 shall use pich_drx_2 for PICH receptin, else shall directly use pich_drx for PICH reception. 0~5120 ms */
+#endif /* __UMTS_R7__ */
+} fdd_cphy_pch_modify_req_struct;
+
+typedef struct _fdd_cphy_pch_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+} fdd_cphy_pch_release_req_struct;
+
+typedef struct _fdd_cphy_fach_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+ FDD_FACH_PCH_Info_T fach_pch_info; /* Channel information */
+} fdd_cphy_fach_setup_req_struct;
+
+typedef struct _fdd_cphy_fach_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ FDD_ctch_drx_T ctch_drx; /* Modified CTCH DRX information */
+} fdd_cphy_fach_modify_req_struct;
+
+typedef struct _fdd_cphy_fach_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+} fdd_cphy_fach_release_req_struct;
+
+typedef struct _fdd_cphy_rach_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ kal_uint16 ul_freq; /* UL UARFCN */
+ FDD_aich_info_T aich_info; /* AICH info and ASC setting for PRACH partition */
+ FDD_prach_info_T prach_info; /* PRACH information */
+ FDD_prach_power_T prach_power; /* PRACH power information */
+ kal_uint8 tfc_num; /* # of TFC. 1 ~ 32 (Only 1 TrCH for 1 PRACH) */
+ FDD_ul_rach_tfc_T tfcs[FDD_MAXTF]; /* TFCS (TFS) */
+ FDD_ul_rach_trch_T trch_list[1]; /* Only 1 TrCH */
+#ifdef __UMTS_R8__
+ FDD_cell_fach_ul_trch_type_E trch_type; /* the transport channel type of random access attemp */
+ FDD_edch_specific_info_T edch_specific_info; /* PRACH and AICH specific information used for common E-DCH transmission */
+#endif /* __UMTS_R8__ */
+} fdd_cphy_rach_setup_req_struct;
+
+typedef struct _fdd_cphy_rach_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+} fdd_cphy_rach_release_req_struct;
+
+typedef struct _fdd_cphy_dch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ FDD_dch_setup_msg_type_E setup_type; /* SETUP, TRHHO or TRHHO revert */
+ kal_int8 tm_rl_index; /* indicate the index of specific RL in array dl_dpch_rl[] which has the valid Tm value. */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+ kal_int16 rscp; /* Serving cell RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
+ kal_uint8 tid; /* Transaction id */
+
+ kal_uint8 dl_crc_ind; /* For those TrCHs whose CRC data should be sent to MAC,
+ their corresponding bit will be set to 1.
+ The MSB represents the lowest numbered TrCH ID.
+ */
+
+ kal_uint16 ul_freq; /* UL UARFCN */
+ kal_uint16 ul_tfc_num; /* # of TFC for UL DPCH */
+ FDD_ul_dpch_tfc_T ul_tfcs[FDD_MAX_UL_TFC]; /* UL TFCS */
+ kal_uint8 ul_trch_num; /* # of UL TrCH */
+ FDD_ul_dch_trch_T ul_trch_list[FDD_MAX_UL_TRCH]; /* UL DPCH TrCH Info */
+ FDD_ul_dpch_info_T ul_dpch_info;
+
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_uint16 dl_tfc_num; /* # of TFC for DL DPCH */
+ FDD_dl_tfc_T dl_tfcs[FDD_MAX_DL_TFC]; /* DL TFCS */
+ kal_uint8 dl_trch_num; /* # of DL TrCH */
+ FDD_dl_dch_trch_T dl_trch_list[FDD_MAX_DL_TRCH]; /* DL DPCH TrCH Info */
+ kal_int8 max_tx_power; /* Max allowed TX power. -50 ~ 33 dBm */
+ kal_int8 umts_power_class; /* UE capability*/
+
+ kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
+ FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
+
+ FDD_dl_dpch_rla_T dl_dpch_rla; /* DL Info & DL DPCH Info common for all RLs */
+ kal_uint8 rl_num; /* # of RL. 1 ~ 8 */
+ FDD_dl_dpch_rl_T dl_dpch_rl[FDD_MAX_RL]; /* DL Info & DL DPCH Info. for each RL */
+
+ FDD_dl_establish_T dl_sync_info; /* DL DPCH establishment criterion */
+
+ kal_bool non_sync_ind; /* [R6] FALSE: sync procedure shall be performed. TRUE: Sync procedure shall not be performed
+ for R5 and previous version, this value should be FALSE.
+ This field can be set to true only when setup_type is FDD_DCH_TMHHO */
+ kal_bool post_verification; /* [R6] TRUE: Post verification period shall be used . FALSE: Post verification period shall not be used.
+ for R5 and previous version, this value should be FALSE */
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rl */
+
+ kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event */
+#ifdef __UMTS_R8__
+ kal_bool edch_info_included; /* True means that IE "E-DCH info" is include in the reconfiguration message in the transition
+ * from FACH state to DCH state. UL1 uses this and following flags and other condition to determine
+ * if it is needed to perform Sync A procedure. Please see UL1 SAP in details. */
+ kal_bool fach_to_dch_cell_change; /* the PSC of RLs included in active set does not include the PSC of the current cell in CELL_FACH. */
+#endif /* __UMTS_R8__ */
+ FDD_IS_CS_PS is_cs_ps_call; /* for TAS feature. To check if DCH channel is for CS call */
+ kal_bool is_cs_call_only; /* for lo_rx. To check if DCH channel is only CS call */
+ kal_bool is_CSFB; /* to specify this DCH setup is for CSFB redirection */
+ kal_bool is_ecall_or_callback; /* To use eCall Information so that UL1 can disable features like LoRX, ARX */
+ kal_bool is_vc_resume; /* To decide DCH setup type after Virtual connected resume */
+} fdd_cphy_dch_setup_req_struct;
+
+typedef struct _fdd_cphy_dch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ FDD_dch_modify_msg_type_E modify_type; /* MODIFY, ASU, or Loop back mode 2 */
+
+ kal_uint8 tid; /* Transaction id */
+
+ kal_bool ul_mod_ind; /* Indicate whether UL modify indication should be sent to MAC */
+ kal_bool dl_mod_ind; /* Indicate whether DL modify indication should be sent to MAC */
+
+ kal_uint8 dl_crc_ind; /* For those TrCHs whose CRC data should be sent to MAC,
+ their corresponding bit will be set to 1.
+ The MSB represents the lowest numbered TrCH ID.
+ */
+
+ kal_uint16 modify_field; /* Bit field to represent for the parameters that should be modified
+ Bit 0 : DL TrCH parameter
+ Bit 1 : DL TFCS parameter
+ Bit 2 : UL TrCH parameter
+ Bit 3 : UL TFCS parameter
+ Bit 4 : DL common RL parameter
+ Bit 5 : DL each RL parameter
+ Bit 6 : UL RL parameter
+ Bit 7 : Physical parameters such as UL/DL freq and max TX power
+ Bit 8 : DL sync info which means timer and constant updating
+ */
+ /* Bit 3 */
+ kal_uint16 ul_tfc_num; /* # of TFC for UL DPCH */
+ FDD_ul_dpch_tfc_T ul_tfcs[FDD_MAX_UL_TFC]; /* UL TFCS */
+ /* Bit 2 */
+ kal_uint8 ul_trch_num; /* # of UL TrCH */
+ FDD_ul_dch_trch_T ul_trch_list[FDD_MAX_UL_TRCH]; /* UL DPCH TrCH Info */
+ /* Bit 1 */
+ kal_uint16 dl_tfc_num; /* # of TFC for DL DPCH */
+ FDD_dl_tfc_T dl_tfcs[FDD_MAX_DL_TFC]; /* DL TFCS */
+ /* Bit 0 */
+ kal_uint8 dl_trch_num; /* # of DL TrCH */
+ FDD_dl_dch_trch_T dl_trch_list[FDD_MAX_DL_TRCH]; /* DL DPCH TrCH Info */
+ /* Bit 4 */
+ FDD_dl_dpch_rla_T dl_dpch_rla; /* DL Info & DL DPCH Info common for all RLs */
+
+ kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
+ FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
+
+ /* Bit 6 */
+ FDD_ul_dpch_info_T ul_dpch_info;
+ /* Bit 7 */
+ /*remove these fields according to frequency info handler discussion*/
+// kal_uint16 ul_freq; /* UL UARFCN */
+// kal_uint16 dl_freq; /* DL UARFCN */
+ kal_int8 max_tx_power; /* Max allowed TX power. -50 ~ 33 dBm */
+ kal_int8 umts_power_class; /* UE capability*/
+ /* Bit 5 or ASU */ /* For Bit 5 modification, only rl_num_add and dl_dpch_rl_add are used */
+ kal_uint8 rl_num_delete; /* # of RL to be removed. 1 ~ 8*/
+ kal_uint16 dl_dpch_rl_delete[FDD_MAX_RL]; /* RL to be removed (PSC) */
+ kal_uint8 rl_num_add; /* # of RL to be added. 1 ~ 8 */
+ FDD_dl_dpch_rl_T dl_dpch_rl_add[FDD_MAX_RL]; /* DL Info & DL DPCH Info. for each RL */
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rl */
+
+ kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event */
+
+ /* Bit 8 for dl sync info updating */
+ FDD_dl_establish_T dl_sync_info; /* DL DPCH establishment criterion */
+ FDD_IS_CS_PS is_cs_ps_call; /* for TAS feature. To check if DCH channel is for CS call */
+ kal_bool is_cs_call_only; /* for lo_rx. To check if DCH channel is only CS call */
+ kal_bool is_ecall_or_callback; /* To use eCall Information so that UL1 can disable features like LoRX, ARX */
+} fdd_cphy_dch_modify_req_struct;
+
+typedef struct _fdd_cphy_dch_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+ kal_bool isStopLoopTestM2First; /* LCL needs to stop Loop Test explicitly before releasing DCH in abnormal case. */
+
+ kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
+ FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
+
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rl */
+
+ kal_uint8 ul_mac_event; /* Indicate if UMAC need setup/modify/release event */
+#ifdef __UMTS_R7__
+ FDD_dpch_release_type_E release_type; /* [R7] for whether UL1 need to record the HSS-SCCH oreder */
+#endif /* __UMTS_R7__ */
+
+} fdd_cphy_dch_release_req_struct;
+
+typedef struct _fdd_cphy_tgps_delete_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
+ FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
+
+} fdd_cphy_tgps_delete_req_struct;
+
+/* RRCE notifies UL1 if UL1 should resume sending cphy_tgps_overlap_ind*/
+typedef struct _fdd_cphy_tgps_overlap_resume_reporting_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tgpsi; /* TGPSI of TGPS beging removed. 1 ~ 6 */
+} fdd_cphy_tgps_overlap_resume_reporting_req_struct;
+
+
+typedef struct _fdd_cphy_frequency_scan_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 max_num_cell; /* maximum # of cells reported in 1 freq scan
+ If L1 found and report max_num_cell in 1 freq,
+ it should halt the freq scan
+ */
+ kal_int16 timeout; /* The max time spent to do cell search on 1 freq. (ms)
+ If L1 has spent so much time to do cell search on 1 freq,
+ it will send an ind to RRC and halt the freq scan procedure.
+ */
+
+ kal_uint8 num_freq_range; /* # of range list */
+ kal_uint16 uarfcn_begin[FDD_MAX_FREQ_RANGE]; /* Begin of DL uARFCN for range cell search */
+ kal_uint16 uarfcn_end[FDD_MAX_FREQ_RANGE]; /* End of DL uARFCN for range cell search */
+
+ kal_uint8 num_freq_list; /* # of freq for preferred freq list */
+ kal_uint16 uarfcn_list[FDD_MAX_FREQ_LIST]; /* List of UARFCN */
+
+ kal_uint8 num_psc; /* # of preferred cells */
+ FDD_preferred_cell_list_T preferred_cell_list[FDD_MAX_PREFERRED_PSC]; /* Preferred cell list */
+
+ kal_bool full_band_search; /* Perform full band scan; igonoring other parameters. */
+ kal_bool freq_correct; /* If 3G L1 need to do frequency correction */
+ kal_bool resume; /* TRUE: UL1 should resume previous freq scan, UL1 didn't care the other fields in this msg
+ FALSE: UL1 should start a new freq scan according to this msg */
+ /*Flag to indicate Quick Search Scan enabled or not*/
+ kal_bool quick_search;
+ /*Add for improving full band FS efficiency -- by excluding some UARFCN or some frequency range*/
+ FDD_full_band_option_E full_band_option; /*To indicate if "[filtered frequency list]/[frequency range]" shall be refered for full band search"*/
+ kal_uint8 working_UMTS_FDD_band[4]; /* Bitmask for frequency bands necessary to be scanned for this request */
+ kal_uint8 prefer_freq_list_cnt; /* # of preferred freq list */
+ kal_uint16 prefer_uarfcn_list[FDD_MAX_FREQ_LIST]; /* List of prefered freq */
+ kal_bool is_plmn_list; /* the prefered freq list is PLMN list or PLMN search */
+#ifdef __UMTS_R8__
+ kal_bool is_csg_search; /* [Rel8][CSG search]: to notify that current fs is for csg */
+#endif
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+#if !defined(__XL1SIM__)
+ freq_scan_type_enum freq_scan_type;
+#else
+ kal_uint16 priority_index;
+#endif
+
+ kal_uint8 priority_level; /* This field is only used for Gemini 2.0. to indicate the gap pattern used for this freq scan in Virtual mode.
+ The higher the priority, the smaller the priority level number. The highest priority is 2, which means this field can't be smaller than 2. */
+#endif /* __GEMINI__ && __UMTS_RAT__ */
+
+ kal_bool is_auto_gap_support; /* [MM] this freq scan req is for rptCGI */
+ kal_bool is_CSFB_search; /* [MM] to notify L1 the frequency scan is specified for CSFB */
+
+} fdd_cphy_frequency_scan_req_struct;
+
+typedef struct _fdd_cphy_frequency_scan_continue_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool continue_cell; /* True if MEME want L1 to do continue cell search on current frequency
+ instead of jumping to next specified frequency. */
+ kal_uint16 ecs_freq; /* exhaustive cell search frequency */
+ kal_bool apply_l1_filter;
+ kal_uint8 num_exclude_frequency_list;
+ kal_uint16 exclude_frequency_list[FDD_MAX_FREQ_EXCLUDE];
+} fdd_cphy_frequency_scan_continue_req_struct;
+
+typedef struct _fdd_cphy_frequency_scan_suspend_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool is_compensate_meas_cell_required; /* True if the suspend_req is triggered by RSVAU itself, UL1 may help to send a measurement_cell_ind */
+} fdd_cphy_frequency_scan_suspend_req_struct;
+
+/* This interface should not be used in MT6268 */
+typedef struct _fdd_cphy_frequency_scan_stop_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_stop_req_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_START_REQ (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_start_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 num_freq_list; /* # of freq for scan list of RSSI sniffer */
+ kal_uint16 uarfcn_list[FDD_MAX_RSSI_SNIFFER_SCAN_LIST]; /* List of UARFCN */
+
+} fdd_cphy_rssi_sniffer_start_req_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_STOP_REQ (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_stop_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rssi_sniffer_stop_req_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_PERIOD_CHANGE_REQ*/
+typedef struct _fdd_cphy_rssi_sniffer_period_change_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 periodicity_time; /*Range: [10,60], default: 30 // If the setting value is greater than the max value that xL1 can support, use the max supported value as setting*/
+
+} fdd_cphy_rssi_sniffer_period_change_req_struct;
+
+typedef struct _fdd_cphy_measurement_config_tgps_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 rx_cfn; /* message rx_cfn */
+ FDD_tgps_status_info_T tgps_status_info; /* Used to enable/disable particular TGPSs */
+
+ kal_uint8 tgps_action_nbr; /* Number of TGPs actiosn */
+ FDD_TGPS_Action_T tgps_action[12]; /* TGPS actions */
+} fdd_cphy_measurement_config_tgps_req_struct;
+
+typedef struct _fdd_cphy_measurement_config_fmo_req_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_fach_mo_info_T fach_mo_info; /* FACH MO param */
+} fdd_cphy_measurement_config_fmo_req_struct;
+
+typedef struct _fdd_cphy_auto_gap_on_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_auto_gap_on_req_struct;
+
+typedef struct _fdd_cphy_auto_gap_on_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_auto_gap_on_cnf_struct;
+
+typedef struct _fdd_cphy_auto_gap_off_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_auto_gap_off_req_struct;
+
+typedef struct _fdd_cphy_auto_gap_off_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_auto_gap_off_cnf_struct;
+
+typedef struct _fdd_cphy_measurement_config_cell_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; /* Transaction ID to sync between request and indication */
+ kal_bool stop_flag; /* TRUE : just stop meas. UL1 will NOT clear all cell info list and meas param */
+ FDD_CPHY_MEASUREMENT_STOP_CAUSE_E stop_cause; /* check this value only when stop_flag=TRUE */
+
+ kal_bool meas_spec_valid; /* Indicate if meas_spec is valid */
+ FDD_meas_spec_T meas_spec; /* meas spec for CPICH cell meas */
+
+ kal_bool cell_info_list_valid; /* Indicate if cell_info_list[], uarfcn[] and action[] are valid */
+ kal_uint16 uarfcn[FDD_MAX_UMTS_FREQ]; /* List of reference DL UARFCN */
+ kal_uint8 num_cell; /* # of cells in cell_info_list[] */
+ FDD_cell_info_list_T cell_info_list[FDD_MAX_NUM_MEASURED_CELL]; /* List of cells to be measured. */
+ FDD_meas_act_E action[FDD_MAX_UMTS_FREQ]; /* Action that should be applied to cell lsits.
+ FDD_MEAS_UPDATE : Add/Repleace cell list of a new specified freq (Both freq and cell list with tm/off are changed)
+ FDD_MEAS_MODIFY : (20080130: Removed)
+ FDD_MEAS_DELETE : Delete the cell list of a freq.
+ */
+
+ FDD_supplementary_meas_parameter_T supplementary_meas_parameter; /* These parameters are supplementary for UL1 measurement. These parameters may be set by CSCE or MEME */
+
+ kal_int8 idx_intra_freq; /* [Range]: 0 ~ 2. Indicate which frequency in the array uarfcn[FDD_MAX_UMTS_FREQ] is intra-frequency, -1 means invalid */
+
+ kal_bool intra_meas_period_valid; /* Only for MTK L1: configure Intra-freq. meas. period in DCH/FACH */
+ kal_uint8 intra_period_N; /* Num. of 40/50 ms */
+
+ kal_bool inter_meas_period_valid; /* Only for MTK L1: configure Inter-freq. meas. period in DCH/FACH */
+ kal_uint8 inter_period_N; /* Num. of GAPs or FMOs */
+
+ kal_bool meas_period_valid; /* Only for MA */
+ kal_uint16 period_unit; /* Only for MA */
+ kal_uint8 period_N; /* Only for MA */
+
+#ifdef __UMTS_R8__
+ kal_int16 T_higher_prio_search; /* [Rel8][Absolute Priority Search] -1: no need to watch priority_search_control in FDD_cell_info_list_T */
+ /* [Rel8][Absolute Priority Search] others: real value for the timer */
+
+ kal_bool detected_cell_info_list_valid; /* [Rel8][CSG search]: to judge if detected cell list is valid, the list is configured under IDLE state */
+ kal_uint8 num_detected_cell; /* [Rel8][CSG search]: number of detected cell, number <= 6 */
+ FDD_cell_info_list_T detected_cell_info_list[6]; /* [Rel8][CSG search]: information of the detected cell list */
+
+ kal_bool non_compressed_mode_inter_freq[FDD_MAX_UMTS_FREQ]; /* Indicates which inter-frequency in the array uarfcn[] should be measured without compressed mode */
+#endif /*__UMTS_R8__*/
+
+ kal_bool is_detected_cell_meas[FDD_MAX_UMTS_FREQ]; /* [MM] other-RATs can use this flag to trigger detected search */
+ kal_bool is_standby_meas_period_reset; /* [Rel8][MM] MEME notifies UL1 if short period meas cell list changes. */
+ /* If changes, measurement needs to be reconfigured (reset short period timer) */
+ kal_bool is_standby_prio_meas_period_reset; /* [Rel8][MM] MEME notifies UL1 if long period meas cell list changes. */
+ /* If changes, measurement needs to be reconfigured (reset long period timer) */
+
+ kal_bool prohibit_apply_n_layer; /* [Rel8][MM] Due to OOS, MEME notifies UL1 not to apply n_layer factor to accelerate meas frequency */
+
+ kal_int8 idx_first_meas_uarfcn_for_3g_standby; /* [Rel8][ABPCR] under standby mode, indicated uarfcn controlled by RR is first to be scheduling measured */
+#ifdef __UMTS_R9__
+ kal_int8 idx_sec_intra_freq; /* [R9]Indicates which frequency in the array uarfcn[] is secondary intra-freq. -1 measn invalid. [Range]0~3.*/
+#endif /*__UMTS_R9__*/
+} fdd_cphy_measurement_config_cell_req_struct;
+
+typedef struct _fdd_cphy_measurement_config_tx_power_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool periodic_ind; /* Indicate periodically or event triggered. TRUE means period */
+
+ kal_uint8 periodic_measurement_id;
+ kal_uint8 report_num; /* # of period report to be sent. 0 ~ 64 */
+ kal_uint16 period; /* Report period. 25 ~ 6400 frames */
+
+ kal_uint8 event_num; /* # of events in event[] */
+ FDD_meas_event_T event[FDD_MAX_MEAS_EVENT]; /* List of TX power meas event */
+
+ kal_uint8 filter; /* L3 filtering coefficient. 0 ~ 19 */
+
+} fdd_cphy_measurement_config_tx_power_req_struct;
+
+typedef struct _fdd_cphy_measurement_config_tx_power_stop_req_struct
+{
+ LOCAL_PARA_HDR
+
+} fdd_cphy_measurement_config_tx_power_stop_req_struct;
+
+
+
+typedef struct _fdd_cphy_treselection_start_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint32 treselection_value; /* One shot cell measurement will be triggered after T_reselection.
+ treselection_value can not be 0. uint = ms */
+ kal_uint8 freq_num; /* Indicate the number of freq that need to perform CM after T_reselection.
+ range: 1~FDD_MAX_UMTS_FREQ */
+ kal_uint16 freq[FDD_MAX_UMTS_FREQ]; /* Indicate the frequency that need to perfrom CM. */
+} fdd_cphy_treselection_start_req_struct;
+
+typedef struct _fdd_cphy_tx_power_result_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_tx_power_result_req_struct;
+
+typedef struct _fdd_cphy_specific_cell_search_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 freq; /* UARFCN of the specific cell */
+ kal_uint16 psc; /* Primary scrambling code of the specific cell */
+ kal_bool sttd; /* True if STTD is used in the designated cell. */
+ kal_bool sttd_valid; /* True if sttd is useful to UL1 */
+ kal_bool freq_correction; /* True if frequency correction is required */
+
+} fdd_cphy_specific_cell_search_req_struct;
+
+typedef struct _fdd_cphy_specific_cell_search_stop_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_specific_cell_search_stop_req_struct;
+
+typedef struct _fdd_cphy_reset_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_reset_req_struct;
+
+typedef struct _fdd_cphy_rf_on_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 working_UMTS_FDD_band[4];
+} fdd_cphy_rf_on_req_struct;
+
+typedef struct _fdd_cphy_rf_off_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rf_off_req_struct;
+
+typedef struct _fdd_cphy_set_active_rat_req_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_mode_type_E mode; /* Curernt mode setting (Single, Dual) */
+ FDD_rat_type_E rat; /* Current active RAT setting (Flight, UMTS, GSM) */
+ erac_rat_enum full_rat_info; /* Full RAT info */
+} fdd_cphy_set_active_rat_req_struct;
+
+/* 20080131: By MEME's request, define new I/F for event 6E. */
+typedef struct _fdd_cphy_measurement_config_rssi_event_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool enable; /* Indicate if we need to monitor the 6E RSSI event. TRUE means to be activated */
+ kal_uint16 delay; /* Time to Trigger. 0 ~ 500 frames */
+} fdd_cphy_measurement_config_rssi_event_req_struct;
+
+/*-------- Message(Primitive) related definition ----------------------*/
+
+typedef struct _FDD_msg_buf_T /* Buffer of message container */
+{
+ kal_uint8 channel_id; /* Channel ID */
+ msg_type msg_id; /* Message ID */
+ kal_uint16 buff_size; /* Buffer size */
+ local_para_struct *buffer; /* Channel configuration message buffer */
+} FDD_msg_buf_T;
+
+
+typedef struct _fdd_cphy_msg_container_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 at_ref; /* Reference channge of activation time.
+ 0 : Ref channel is the released channel.
+ There should be ch to be released
+ 1 : Ref channel is the setup channel.
+ There should be ch to be setup.
+ */
+ kal_int16 rx_cfn; /* Indicate peer message receive cfn. Ex: tti = 4, receive frame number : 0,1,2,3. rx_cfn = 3 (set by ul1)
+ [Range]: -1 ~ 255.
+ -1 : Means upper layer internal control
+ */
+#ifdef __UMTS_R6__
+ kal_bool delay_restriction; /* From R6 : TS25.331 8.6.3.1 */
+#endif
+ FDD_meas_control_E meas_control; /* Indicate whether UL1 need to not to resume meas. after apply corresponding buffer's config. */
+
+ kal_uint8 msg_num; /* # of included msg. 1 ~ 4 */
+ FDD_msg_buf_T msg_buffer[4]; /* List of msg buffer for included channel msg */
+
+ /* [R5R6] For HS-DSCH and E-DCH */
+ kal_uint8 h_msg_num; /* # of included H-msg. 0~2 */
+ FDD_msg_buf_T h_msg_buffer[2]; /* List of msg buffer for included channel msg */
+ kal_uint8 e_msg_num; /* # of included E-msg. 0~2 */
+ FDD_msg_buf_T e_msg_buffer[2]; /* List of msg buffer for included channel msg */
+#ifdef __UMTS_R7__
+ kal_uint8 cpc_msg_num; /* # of included CPC-msg. 0~1 */
+ FDD_msg_buf_T cpc_msg_buffer[1]; /* List of msg buffer for included CPC msg */
+#endif /* __UMTS_R7__ */
+// PLMN releated info
+ FDD_PLMN_LAC_PARAM_T plmn_info; /*PLMN, RAC and LAC info*/
+// RLC window size info
+ kal_uint8 rlc_info_msg_num; /* # of included rlc_info */
+ FDD_RLC_WINDOW_SIZE_INFO_T rlc_info_msg_buffer[4]; /* List of msg buffer for included rlc_info msg */
+} fdd_cphy_msg_container_req_struct;
+
+typedef struct _fdd_cphy_abort_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_abort_req_struct;
+
+typedef struct _fdd_cphy_TAS_notify_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_TAS_notify_ind_struct;
+/****************************************************************/
+/* __HSDPA_SUPPORT__ */
+typedef struct _fdd_cphy_hsdsch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+ FDD_dl_dpch_rla_T hsdsch_rla; /* Downlink information common for all RLs and downlink DPCH info. common for all RLs */
+ /* tgps_num in hsdsch_rla should be 0.*/
+ FDD_dl_dpch_rl_T hsdsch_rl; /* Downlink information for each RL (and downlink DPCH info. for each RL (for HS-DSCH serving cell*/
+ FDD_hs_scch_info_T hs_scch_info; /* HS-SCCH Info (25.331 10.3.6.36a) */
+ FDD_hs_meas_fb_info_T hs_meas_fb_info; /* Measurement Feedback Info (25.331 10.3.6.40a) */
+ FDD_hs_harq_info_T hs_harq_info; /* HARQ Info (25.331 10.3.5.7a) */
+ FDD_hs_ulpc_info_T hs_ulpc_info; /* Uplink power control info related to HSDPA */
+
+ kal_bool mac_hs_reset; /* TRUE indicates the MAC-hs entity needs to be reset */
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+ kal_uint16 h_rnti; /* H-RNTI assigned to UE */
+#ifdef __UMTS_R7__
+ FDD_rrc_state_E rrc_status; /* Indicate the RRC current status */
+ FDD_hspdsch_state_info_T hspdsch_state_info; /* HSPDSCH related parameter */
+ FDD_hs_scch_less_info_T hs_scch_less_info; /* HS-SCCH less Info (25.331 10.3.6.36ab) */
+ kal_bool h_rnti_valid; /* Indicate if h_rnti field is valid for UL1. H-RNTI shall be always valid for CELL_DCH, CELL_FACH, IDLE_FACH, and shall be always invalid for URA_PCH. */
+ kal_bool c_h_rnti_valid; /* [R7] Indicate if common H-RNTI is valid for UL1. This field shall be set to FALSE when rrc_status is equal to CELL_DCH. */
+ kal_uint16 c_h_rnti; /* [R7] Common H-RNTI assigned to UE. UL1 should not refer to this field if c_h_rnti_valid = KAL_FALSE. */
+ kal_bool b_h_rnti_valid; /* [R7] Indicate if bcch-specific H-RNTI is valid for UL1 */
+ kal_uint16 b_h_rnti; /* [R7] bcch-specific H-RNTI assigned to UE. UL1 should not refer to this field if b_h_rnti_valid = KAL_FALSE. */
+#ifdef __UMTS_R8__
+ kal_bool cqi_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
+ kal_bool ack_nack_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
+ FDD_hs_cell_fach_drx_T hs_cell_fach_drx; /* HS CELL_FACH DRX information. This field is only valid when rrc_status = CELL_FACH. */
+ FDD_dc_hsdpa_info_T dc_hsdpa_info; /* DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH. */
+ FDD_dl_pc_info_T dl_pc_common_edch; /* dl power control info. This field in only valid in EFACH state with common E-DCH transmission */
+#ifdef __UMTS_R10__
+ FDD_dc_hsdpa_info_T addi_dc_hsdpa_info[FDD_MAX_ADDI_DC_HSDPA]; /* Additional DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH.
+ FDD_MAX_ADDI_DC_HSDPA = 2. */
+#endif /* __UMTS_R10__ */
+#endif /* __UMTS_R8__ */
+#endif /* __UMTS_R7__ */
+} fdd_cphy_hsdsch_setup_req_struct;
+
+typedef struct _fdd_cphy_hsdsch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+#ifdef __UMTS_R7__
+ kal_uint16 modify_field; /* Bit field to represent for the parameters that should be modified
+ Bit 0 : dedicated H-RNTI or common H-RNTI
+ Bit 1 : hsdsch_rla
+ Bit 2 : hsdsch_rl
+ Bit 3 : HS-SCCH Info
+ Bit 4 : Measurement Feedback Info
+ Bit 5 : HARQ Info
+ Bit 6 : Uplink power control info related to HSDPA
+ Bit 7 : h_rnti_valid or hspdsch_state_info
+ Bit 8 : HS-SCCH less Info
+ Bit 9 : [R8] FDD_dc_hsdpa_info_T
+ Bit10 : [R8] FDD_hs_cell_fach_drx_T
+ Bit11 : [R10] addi_dc_hsdpa_info[0]
+ */
+#else /* __UMTS_R7__ */
+ kal_uint8 modify_field; /* Bit field to represent for the parameters that should be modified
+ Bit 0 : H-RNTI
+ Bit 1 : hsdsch_rla
+ Bit 2 : hsdsch_rl
+ Bit 3 : HS-SCCH Info
+ Bit 4 : Measurement Feedback Info
+ Bit 5 : HARQ Info
+ Bit 6 : Uplink power control info related to HSDPA
+ */
+#endif /* !__UMTS_R7__ */
+ FDD_dl_dpch_rla_T hsdsch_rla; /* Downlink information common for all RLs and downlink DPCH info. common for all RLs */
+ /* tgps_num in hsdsch_rla should be 0.*/
+ FDD_dl_dpch_rl_T hsdsch_rl; /* Downlink information for each RL (and downlink DPCH info. for each RL (for HS-DSCH serving cell*/
+ FDD_hs_scch_info_T hs_scch_info; /* HS-SCCH Info (25.331 10.3.6.36a) */
+ FDD_hs_meas_fb_info_T hs_meas_fb_info; /* Measurement Feedback Info (25.331 10.3.6.40a) */
+ FDD_hs_harq_info_T hs_harq_info; /* HARQ Info (25.331 10.3.5.7a) */
+ FDD_hs_ulpc_info_T hs_ulpc_info; /* Uplink power control info related to HSDPA */
+ kal_bool mac_hs_reset; /* TRUE indicates the MAC-hs entity needs to be reset */
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+ kal_uint16 h_rnti; /* H-RNTI assigned to UE */
+#ifdef __UMTS_R7__
+ FDD_rrc_state_E rrc_status; /* Indicate the RRC current status */
+ FDD_hspdsch_state_info_T hspdsch_state_info; /* HSPDSCH related parameter */
+ FDD_hs_scch_less_info_T hs_scch_less_info; /* HS-SCCH less Info (25.331 10.3.6.36ab) */
+ kal_bool h_rnti_valid; /* Indicate if h_rnti field is valid for UL1. H-RNTI shall be always valid for CELL_DCH, CELL_FACH, IDLE_FACH, and shall be always invalid for URA_PCH. */
+ kal_bool c_h_rnti_valid; /* [R7] Indicate if common H-RNTI is valid for UL1. This field shall be set to FALSE when rrc_status is equal to CELL_DCH. */
+ kal_uint16 c_h_rnti; /* [R7] Common H-RNTI assigned to UE. UL1 should not refer to this field if c_h_rnti_valid = KAL_FALSE. */
+ kal_bool b_h_rnti_valid; /* [R7] Indicate if bcch-specific H-RNTI is valid for UL1 */
+ kal_uint16 b_h_rnti; /* [R7] bcch-specific H-RNTI assigned to UE. UL1 should not refer to this field if b_h_rnti_valid = KAL_FALSE. */
+#ifdef __UMTS_R8__
+ kal_bool cqi_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
+ kal_bool ack_nack_report_on; /* This field should always be TRUE when rrc_status = CELL_DCH, and should always be FALSE when rrc_status = CELL_PCH and URA_PCH. */
+ FDD_hs_cell_fach_drx_T hs_cell_fach_drx; /* HS CELL_FACH DRX information. This field is only valid when rrc_status = CELL_FACH. */
+ FDD_dc_hsdpa_info_T dc_hsdpa_info; /* DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH. */
+#ifdef __UMTS_R10__
+ FDD_dc_hsdpa_info_T addi_dc_hsdpa_info[FDD_MAX_ADDI_DC_HSDPA]; /* Additional DC-HSDPA information. This field is only valid when rrc_status = CELL_DCH.
+ FDD_MAX_ADDI_DC_HSDPA = 2. */
+#endif /* __UMTS_R10__ */
+#endif /* __UMTS_R8__ */
+#endif /* __UMTS_R7__ */
+} fdd_cphy_hsdsch_modify_req_struct;
+
+typedef struct _fdd_cphy_hsdsch_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+ kal_bool mac_hs_reset; /* TRUE indicates the MAC-hs entity needs to be reset */
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+} fdd_cphy_hsdsch_release_req_struct;
+
+#ifdef __UMTS_R7__
+typedef struct _FDD_phy_mac_ehs_reset_req_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_mac_ehs_reset_cause_E cause; /* Indicate the cause about the reason of UMAC reset */
+} fdd_phy_mac_ehs_reset_req_struct;
+#endif /* __UMTS_R7__ */
+
+#ifdef __UMTS_R7__
+typedef struct _fdd_cphy_cpc_config_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ FDD_hs_dtx_drx_info_T hs_dtx_drx_info; /* DTX/DRX information */
+} fdd_cphy_cpc_config_req_struct;
+
+typedef struct _fdd_cphy_d_hrnti_detected_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_d_hrnti_detected_ind_struct;
+
+#ifdef __UMTS_R8__
+typedef struct _fdd_cphy_start_monitor_order_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 h_rnti; /* h_rnti to decode target cell HS-SCCH */
+ kal_uint16 psc; /* psc to receive target cell HS-SCCH */
+ FDD_hs_scch_info_T hs_scch_info; /* ovsf_code_num field should always be 1 */
+ kal_int16 rpt_act_time; /* [Range]: (-1~255). (0-255) for CFN type, */
+} fdd_cphy_start_monitor_order_req_struct;
+
+typedef struct _fdd_cphy_start_monitor_order_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_start_monitor_order_cnf_struct;
+
+typedef struct _fdd_cphy_stop_monitor_order_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_stop_monitor_order_req_struct;
+
+typedef struct _fdd_cphy_stop_monitor_order_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_stop_monitor_order_cnf_struct;
+
+typedef struct _fdd_cphy_monitor_order_received_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 psc; /* Range: {0..511} */
+ kal_int16 act_time; /* Range {-1..255}: -1 is T324, 0..255 is AT */
+ kal_uint16 rx_cfn;
+} fdd_cphy_monitor_order_received_ind_struct;
+#endif /* __UMTS_R8__ */
+
+#endif /* __UMTS_R7__ */
+
+typedef struct _fdd_cphy_rlc_info_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 distance[FDD_MAX_HS_RB_NUM]; /* The distance between VR_H and VR_R (VR_H - VR_R) */
+ kal_uint32 rx_window_size[FDD_MAX_HS_RB_NUM];
+ kal_uint32 RTT[FDD_MAX_HS_RB_NUM]; /* Round trip time */
+} fdd_cphy_rlc_info_req_struct;
+
+/****************************************************************/
+
+/****************************************************************/
+/* __HSUPA_SUPPORT__ */
+typedef struct _fdd_cphy_edch_setup_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+ kal_bool pri_e_rnti_valid; /* Indicate if pri_e_rnti field is valid */
+ kal_uint16 pri_e_rnti; /* Primary E-RNTI assigned to UE */
+ kal_bool sec_e_rnti_valid; /* Indicate if sec_e_rnti field is valid */
+ kal_uint16 sec_e_rnti; /* Secondary E-RNTI assigned to UE */
+
+ FDD_edch_tti_E edch_tti; /* E-DCH TTI 2ms or 10ms */
+
+ kal_uint16 edch_serv_psc; /* serving E-DCH cell */
+
+ FDD_eagch_info_T eagch_info; /* E-AGCH info*/
+
+ kal_uint8 ehich_info_num; /* Number of E-HICH info: 1~FDD_MAX_EDCH_RL */
+ FDD_ehich_info_T ehich_info[FDD_MAX_EDCH_RL]; /* E-HICH info */
+ kal_uint8 ergch_info_num; /* Number of E-RGCH info: 0~FDD_MAX_EDCH_RL */
+ FDD_ergch_info_T ergch_info[FDD_MAX_EDCH_RL]; /* E-RGCH info */
+
+ FDD_edpdch_info_T edpdch_info; /* E-DPDCH info */
+ FDD_edpcch_info_T edpcch_info; /* E-DPCCH info */
+
+ FDD_edch_harq_info_T edch_harq_info; /* HARQ info for E-DCH */
+
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+#ifdef __UMTS_R7__
+ kal_bool ul_16QAM_on; /* Uplink 16QAM enable/disable */
+#endif /* __UMTS_R7__ */
+#ifdef __UMTS_R8__
+ FDD_edch_transmission_type_E transmission_type; /* Specify that E-DCH is allocated in dedicated state or common state */
+ FDD_common_edch_info_T common_edch_info; /* [R8] This field is only valid when transmission_type is equal to FDD_EDCH_IN_COMMON_STATE */
+#ifdef __UMTS_R9__
+ FDD_dc_hsupa_info_T dc_hsupa_info; /* [R9] DC-HSUPA information. This field is only valid when rrc_status = CELL_DCH. */
+#endif /* __UMTS_R9__ */
+#endif /* __UMTS_R8__ */
+} fdd_cphy_edch_setup_req_struct;
+
+typedef struct _fdd_cphy_edch_modify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+
+ kal_uint16 modify_field; /* Bit field to represent for the parameters that should be modified
+ Bit 0 : E-RNTI
+ Bit 1 : E-DCH TTI
+ Bit 2 : E-AGCH info
+ Bit 3 : E-HICH info
+ Bit 4 : E-RGCH info
+ Bit 5 : E-DPDCH info
+ Bit 6 : E-DPCCH info
+ Bit 7 : E-DCH serving cell
+ Bit 8 : E-DCH harq info
+ Bit 9 : ul_16QAM_on
+ Bit 10: [R8] FDD_common_edch_info_T
+ Bit 11: [R9] FDD_dc_hsupa_info_T
+ */
+
+ kal_bool pri_e_rnti_valid; /* Indicate if pri_e_rnti field is valid */
+ kal_uint16 pri_e_rnti; /* Primary E-RNTI assigned to UE */
+ kal_bool sec_e_rnti_valid; /* Indicate if sec_e_rnti field is valid */
+ kal_uint16 sec_e_rnti; /* Secondary E-RNTI assigned to UE */
+ FDD_edch_tti_E edch_tti; /* E-DCH TTI 2ms or 10ms */
+
+ kal_uint16 edch_serv_psc; /* serving E-DCH cell */
+
+ FDD_eagch_info_T eagch_info; /* E-AGCH info*/
+
+ kal_uint8 ehich_info_num; /* Number of E-HICH info: 1~FDD_MAX_EDCH_RL */
+ FDD_ehich_info_T ehich_info[FDD_MAX_EDCH_RL]; /* E-HICH info */
+ kal_uint8 ergch_info_num; /* Number of E-RGCH info: 0~FDD_MAX_EDCH_RL */
+ FDD_ergch_info_T ergch_info[FDD_MAX_EDCH_RL]; /* E-RGCH info */
+
+ FDD_edpdch_info_T edpdch_info; /* E-DPDCH info */
+ FDD_edpcch_info_T edpcch_info; /* E-DPCCH info */
+
+ FDD_edch_harq_info_T edch_harq_info; /* HARQ info for E-DCH */
+
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+#ifdef __UMTS_R7__
+ kal_bool ul_16QAM_on; /* Uplink 16QAM enable/disable */
+#endif /* __UMTS_R7__ */
+#ifdef __UMTS_R8__
+ FDD_edch_transmission_type_E transmission_type; /* Specify that E-DCH is allocated in dedicated state or common state */
+ FDD_common_edch_info_T common_edch_info; /* [R8] This field is only valid when transmission_type is equal to FDD_EDCH_IN_COMMON_STATE */
+#ifdef __UMTS_R9__
+ FDD_dc_hsupa_info_T dc_hsupa_info; /* [R9] DC-HSUPA information. This field is only valid when rrc_status = CELL_DCH. */
+#endif /* __UMTS_R9__ */
+#endif /* __UMTS_R8__ */
+} fdd_cphy_edch_modify_req_struct;
+
+typedef struct _fdd_cphy_edch_release_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 act_time; /* activation time. -1 ~ 255. -1 means immediate */
+ kal_uint8 mac_event; /* Indicate if UMAC need setup/modify/release event */
+} fdd_cphy_edch_release_req_struct;
+/****************************************************************/
+
+/****************************************************************/
+/* GEMINI 2.0 */
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+typedef struct _fdd_cphy_channel_priority_adjustment_req_struct
+{
+ LOCAL_PARA_HDR
+#ifdef __MODIFY_CTCH_RECEPTION_PRIO__
+ FDD_rrce_gemini_priority_adjust_E channel_priority;
+#else
+ kal_bool channel_priority_high; /* TRUE: UL1 channel priority is set to high. The priority of the timer related DCH/FACH will has the highest priority.
+ FALSE: UL1 channel priority is set to normal. The priority of the timer related DCH/FACH will has the lowest priority. */
+ FDD_rrce_gemini_priority_adjust_E adjust_channel;
+#endif
+} fdd_cphy_channel_priority_adjustment_req_struct;
+
+typedef struct _FDD_urr_ul1_switch_gemini_mode_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool is_virtual_mode; /* TRUE: UL1 will switch from Normal mode to Virtual mode.
+ FALSE: UL1 will switch from Virtual mode to Normal mode. */
+} fdd_urr_ul1_switch_gemini_mode_req_struct;
+
+
+typedef struct _fdd_cphy_peer_gemini_mode_notify_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool is_peer_virtual_mode; /* TRUE: UL1 is informed that peer SIM enters virtual mode.
+ FALSE: UL1 is informed that peer SIM leaves virtual mode. */
+} fdd_cphy_peer_gemini_mode_notify_req_struct;
+
+
+
+typedef struct _FDD_rsvas_ul1_virtual_resume_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_rsvas_ul1_virtual_resume_req_struct;
+
+#endif /* __GEMINI__ && __UMTS_RAT__ */
+
+typedef struct _fdd_cphy_rb_lpbk_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rb_lpbk_req_struct;
+
+/****************************************************************/
+
+
+/*****************************************************************************
+ confirm & indication for cphy
+*****************************************************************************/
+typedef struct _fdd_cphy_rb_lpbk_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rb_lpbk_cnf_struct;
+
+typedef struct _fdd_cphy_bch_setup_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_setup_cnf_struct;
+
+typedef struct _fdd_cphy_bch_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate if BCH setup success.
+ For current L1, it always return true.
+ */
+} fdd_cphy_bch_setup_ind_struct;
+
+typedef struct _fdd_cphy_bch_modify_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_modify_cnf_struct;
+
+typedef struct _fdd_cphy_bch_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_modify_ind_struct;
+
+typedef struct _fdd_cphy_bch_release_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_release_cnf_struct;
+
+typedef struct _fdd_cphy_bch_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_bch_release_ind_struct;
+
+typedef struct _fdd_cphy_sfn_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate if SFN ready success */
+ kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+
+ kal_uint16 dl_freq; /* UARFCN of the specific cell */
+ kal_uint16 psc; /* Primary scrambling code of the specific cell */
+
+ kal_bool dch_meas_valid; /* TRUE: DCH related parameters are valid */
+ kal_uint8 CFN; /* CFN of serving cell*/
+ kal_uint16 SFN; /* SFN of neighbor cell*/
+ kal_uint8 meas_off; /* SFN_CFN difference in frames*/
+ kal_uint16 meas_tm; /* SFN_CFN difference in chips*/
+
+ kal_bool common_meas_valid; /* TRUE: common channel related parameter is valid */
+ kal_uint32 meas_sfn_diff; /* SFN_SFN difference in chips*/
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ FDD_uas_gemini_conflict_cause_enum conflict_cause;
+ kal_uint16 peer_priority_index;
+#endif
+
+} fdd_cphy_sfn_ind_struct;
+
+
+/* MEME use this primitive as a trigger point to query UL1 tgps status */
+typedef struct _fdd_cphy_tgps_delete_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tgpsi_nbr; /* Number of TGPSI deleted */
+ kal_uint8 tgpsi[FDD_MAX_TGPS]; /* TGPSI deleted*/
+} fdd_cphy_tgps_delete_ind_struct;
+
+typedef struct _fdd_cphy_tgps_info_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ umts_fdd_dch_gap_struct dch_gap_pattern; /* The latest TGPS pattern indicator */
+} fdd_cphy_tgps_info_ind_struct;
+
+typedef struct _fdd_cphy_tgps_overlap_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tgpsi; /* TGPSI of TGPS beging removed. 1 ~ 6 */
+} fdd_cphy_tgps_overlap_ind_struct;
+
+typedef struct _fdd_cphy_gap_complete_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tgpsi; /* TGPSI of TGPS beging completed. 1 ~ 6 */
+} fdd_cphy_gap_complete_ind_struct;
+
+typedef struct _fdd_cphy_t312_expiry_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; /* Transaction id */
+
+} fdd_cphy_t312_expiry_ind_struct;
+
+typedef struct _fdd_cphy_dl_init_sync_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; /* Transaction id */
+ kal_int32 dpch_tm; /* For CFN-SFN TD */
+ kal_int16 dpch_off; /* For CFN-SFN TD */
+} fdd_cphy_dl_init_sync_ind_struct;
+
+typedef struct _phy_ul_not_activated_ind_struct
+{
+ LOCAL_PARA_HDR
+} phy_ul_not_activated_ind_struct;
+
+typedef struct _fdd_cphy_rl_failure_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rl_failure_ind_struct;
+
+/*Raymond 20070717 remove DELETE_TGPS CNF/IND interface*/
+typedef struct _fdd_cphy_frequency_scan_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_cnf_struct;
+
+typedef struct _fdd_cphy_frequency_scan_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_ind_struct;
+
+typedef struct _fdd_cphy_frequency_scan_continue_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_continue_cnf_struct;
+
+typedef struct _fdd_cphy_frequency_scan_suspend_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_suspend_cnf_struct;
+
+typedef struct _fdd_cphy_frequency_scan_suspend_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_suspend_ind_struct;
+
+/* This interface should not be used in MT6268 */
+typedef struct _fdd_cphy_frequency_scan_stop_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_stop_cnf_struct;
+
+/* This interface should not be used in MT6268 */
+typedef struct _fdd_cphy_frequency_scan_stop_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_frequency_scan_stop_ind_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_START_CNF (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_start_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rssi_sniffer_start_cnf_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_STOP_CNF (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_stop_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+} fdd_cphy_rssi_sniffer_stop_cnf_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_STOP_IND (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_stop_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rssi_sniffer_stop_ind_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_SIGNAL_APPEAR_IND (Add by Janet) */
+typedef struct _fdd_cphy_rssi_sniffer_signal_appear_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 num_freq_list; /* # of freq for scan list of RSSI sniffer */
+ kal_uint16 uarfcn_list[FDD_MAX_RSSI_SNIFFER_SCAN_LIST]; /* List of UARFCN */
+
+} fdd_cphy_rssi_sniffer_signal_appear_ind_struct;
+
+/* MSG_ID_FDD_CPHY_RSSI_SNIFFER_EXECUTED_IND */
+typedef struct _fdd_cphy_rssi_sniffer_executed_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rssi_sniffer_executed_ind_struct;
+typedef struct _fdd_cphy_measurement_config_tgps_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_measurement_config_tgps_cnf_struct;
+
+typedef struct _fdd_cphy_measurement_config_tgps_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_measurement_config_tgps_ind_struct;
+
+typedef struct _fdd_cphy_measurement_config_fmo_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_measurement_config_fmo_cnf_struct;
+
+typedef struct _fdd_cphy_measurement_config_cell_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; /* Transaction ID to sync between req and ind */
+} fdd_cphy_measurement_config_cell_cnf_struct;
+
+typedef struct _fdd_cphy_measurement_cell_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 tid; /* Transaction ID to sync between req and ind */
+ FDD_measured_type_E measured_type; /*IntraFrequency or InterFrequency*/
+ kal_uint16 uarfcn; /* DL UARFCN */
+ kal_int16 rssi; /* RSSI. Range: -400 ~ -100 means (-100 ~ -25)dBm 0.25 dB step */
+ kal_bool fs_halt; /* Indicate if freq scan halt. only for freq scan report */
+ kal_bool isSuspendByRSVAU; /* Indicate CSE the frequency is suspended. Only TRUE if UL1 receive suspend_req in FS_START and FS_CONTINUE. */
+ kal_uint8 num_cell; /* # of cell reported in this msg */
+ FDD_measured_cell_T measured_cell[FDD_MAX_NUM_MEAS_CELL]; /* list of measured cells */
+ kal_bool rl_status; /* Indicate tx available */
+#ifdef __UMTS_R8__
+ kal_bool isLongPeriodIn3GStandby; /* [Rel8][ABPCR] For RR, Indicate if it is prio search peiorid*/
+#endif
+ FDD_supplementary_report_info_T supplementary_report_info; /* to notify L3 further information */
+ kal_bool sttd_valid; /* Indicate sttd result is valid (reliable) or not */
+} fdd_cphy_measurement_cell_ind_struct;
+
+typedef struct _fdd_cphy_measurement_cell_sfn_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 dl_freq; /* UARFCN of the specific cell */
+ kal_uint16 psc; /* Primary scrambling code of the specific cell */
+ kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+ kal_uint16 SFN; /* SFN of neighbor cell*/
+ kal_bool sttd; /* STTD info of the specified cell */
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ FDD_uas_gemini_conflict_cause_enum conflict_cause;
+#endif
+} fdd_cphy_measurement_cell_sfn_ind_struct;
+
+typedef struct _fdd_cphy_measurement_rl_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 rl_num; /* # of RL */
+ FDD_rl_meas_result_T rl_meas_result[FDD_MAX_RL]; /* RL measurement result for each RL */
+ kal_int16 tx_power; /* Averaged TX power meas result */
+} fdd_cphy_measurement_rl_ind_struct;
+
+typedef struct _fdd_cphy_measurement_config_tx_power_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_measurement_config_tx_power_cnf_struct;
+
+typedef struct _fdd_cphy_measurement_tx_power_periodic_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 periodic_measurement_id;
+ kal_int16 tx_power; /* Averaged TX power meas result */
+ kal_bool last_report; /* Indicate if this is the last report for period rpt */
+} fdd_cphy_measurement_tx_power_periodic_ind_struct;
+
+typedef struct _fdd_cphy_measurement_tx_power_event_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 tx_power; /* Averaged TX power meas result */
+ kal_uint8 event_id; /* Event ID being triggered */
+ kal_uint8 measurement_id; /* Measurement ID being triggered. */
+} fdd_cphy_measurement_tx_power_event_ind_struct;
+
+typedef struct _fdd_cphy_tx_power_result_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool valid; /* Indicate if below tx_power is vaide */
+ kal_int16 tx_power; /* Averaged TX power meas result */
+} fdd_cphy_tx_power_result_ind_struct;
+
+typedef struct _fdd_cphy_specific_cell_search_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate if search success */
+ FDD_measured_cell_T measured_cell; /* The found(1) cell */
+} fdd_cphy_specific_cell_search_ind_struct;
+
+typedef struct _fdd_cphy_specific_cell_search_stop_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_specific_cell_search_stop_ind_struct;
+
+typedef struct _fdd_cphy_reset_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate whether the L1 initialization sucess or fail */
+} fdd_cphy_reset_cnf_struct;
+
+
+typedef struct _fdd_cphy_rf_on_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rf_on_cnf_struct;
+
+typedef struct _fdd_cphy_rf_off_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_rf_off_cnf_struct;
+
+typedef struct _fdd_cphy_set_active_rat_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_set_active_rat_cnf_struct;
+
+
+typedef struct _fdd_cphy_msg_container_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_msg_container_cnf_struct;
+
+typedef struct _fdd_cphy_msg_container_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success_flag; /* Indicate if configure success
+ For current L1, it always returns true.
+ */
+ kal_bool pending_tgps; /* Indicate if there is any pending TGPS.
+ Only sent when there is any channel to be released.
+ */
+ FDD_msg_container_error_E error_cause; /* Error cause of message container.
+ */
+} fdd_cphy_msg_container_ind_struct;
+
+typedef struct _fdd_cphy_abort_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate if abort request success
+ TRUE : L1 will back to the old channel configure.
+ FALSE : L1 will go forward to the new channel configure.
+ */
+} fdd_cphy_abort_cnf_struct;
+
+typedef struct _fdd_cphy_tx_status_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool is_tx_allow; /* the current TX status
+ TRUE : Currentlly, TX is available in UL1.
+ FALSE : Currentlly, TX is not available in UL1.
+ */
+} fdd_cphy_tx_status_ind_struct;
+
+/* 20080131: By MEME's request, define new I/F for event 6E. */
+typedef struct _fdd_cphy_rssi_exceed_range_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 tx_power; /* Averaged TX power meas result */
+} fdd_cphy_rssi_exceed_range_ind_struct;
+
+typedef struct _fdd_cphy_duplex_mode_change_req_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_duplex_mode_info_T duplex_mode_info;
+} fdd_cphy_duplex_mode_change_req_struct;
+
+typedef struct _fdd_cphy_duplex_mode_change_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool result;
+} fdd_cphy_duplex_mode_change_cnf_struct;
+
+/* Suspend and resume Smart Paging feature */
+
+typedef struct _fdd_cphy_smart_paging_reconfig_req_struct
+{
+ LOCAL_PARA_HDR
+ kal_bool smartpaging_enabled;
+} fdd_cphy_smart_paging_reconfig_req_struct;
+
+/*****************************************************************************
+ request for phy
+*****************************************************************************/
+typedef struct _FDD_phy_rach_data_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint16 tfci; /* TFCI. 0 ~ 1023 */
+ FDD_ulTrchData TrchInfo; /* UL TrCH information */
+ kal_uint16 size_data; /* This parameter represents the number of bytes of the buffer. This number will be equal to the size of allocated buffer plus 4 bytes. */
+ kal_uint8 *data[FDD_MAX_UL_TB]; /* data for each TB. PS shoul allocate the buffer */
+} fdd_phy_rach_data_req_struct;
+
+typedef struct _FDD_phy_access_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool retry; /* Indicate if this is a retry request
+ TRUE : RACH TX failed in last acces procedure.
+ L1 will use the same RACH data an ASC in previous access procedure.
+ */
+ kal_uint8 asc; /* ASC. 0 ~ 7 */
+ kal_int16 ul_interference; /* UL interference in SIB7. -110 ~ 70dBm */
+#ifdef __UMTS_R8__
+ kal_bool is_CEDCH_CCCH; /* [R8] True: Common E-DCH transmission is for CCCH. FALSE for DTCH/DCCH */
+#endif /* __UMTS_R8__ */
+} fdd_phy_access_req_struct;
+
+
+/* confirm & indication for phy */
+typedef struct _FDD_phy_pch_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_pch_setup_ind_struct;
+
+typedef struct _FDD_phy_pch_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_pch_modify_ind_struct;
+
+typedef struct _FDD_phy_pch_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_pch_release_ind_struct;
+
+typedef struct _FDD_phy_fach_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_fach_setup_ind_struct;
+
+typedef struct _FDD_phy_fach_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_fach_modify_ind_struct;
+
+typedef struct _FDD_phy_fach_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_fach_release_ind_struct;
+
+typedef struct _FDD_phy_rach_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_rach_setup_ind_struct;
+
+typedef struct _FDD_phy_rach_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_rach_release_ind_struct;
+
+typedef struct _FDD_phy_dch_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 direction; /* Indicate UL or DL is being setup
+ 0 : DL DCH
+ 1 : UL DCH
+ 2 : FDPCH
+ */
+ kal_uint16 sfn; /* The LST value of the frame when DL DCH is setup.*/
+ kal_bool syncA_procedure_needed ; /* TRUE: Indicate syncA procedure is performed.*/
+} fdd_phy_dch_setup_ind_struct;
+
+typedef struct _FDD_phy_dch_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 direction; /* Indicate UL or DL is being setup
+ 0 : DL_DCH
+ 1 : UL_DCH
+ 2 : FDPCH
+ */
+} fdd_phy_dch_modify_ind_struct;
+
+typedef struct _FDD_phy_dch_release_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 direction; /* Indicate UL or DL is being setup
+ 0 : DL DCH
+ 1 : UL DCH
+ 2 : FDPCH
+ */
+ kal_uint16 sfn; /* The LST value of the frame when DL DCH is setup.*/
+} fdd_phy_dch_release_ind_struct;
+
+typedef struct _FDD_phy_config_abort_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool success; /* Indicate if abort request success
+ TRUE : L1 will back to old channel configure
+ FALSE : L1 will go forward to new channel configure
+ */
+} fdd_phy_config_abort_ind_struct;
+
+typedef struct _FDD_phy_dl_init_sync_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_dl_init_sync_ind_struct;
+
+typedef struct _FDD_phy_bch_data_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 *data; /* PS2 Excel request to add a "data" field in
+ fdd_phy_bch_data_ind_struct. This field is only for
+ protocol and not used by UL1 */
+ kal_bool no_path; /* True: L1 could not find the cell*/
+ kal_int32 tm; /* LST of the cell boundary. 0 ~ 38400*8-1 */
+ kal_int16 off; /* Frame # offset to LST. -1 ~ 4095. -1 means unknown */
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_uint8 crc_status; /* CRC result.
+ 0 : CRC error
+ 1 : CRC ok
+ 2 : no CRC */
+ kal_uint16 num_data; /* Length of the valid byte in data. 0 ~ FDD_MAX_DL_DATA */
+ /* Data is contained in peer buffer */
+ kal_bool measurement_valid;
+ kal_int16 rssi;
+ kal_int16 rscp;
+ kal_int16 ec_no;
+ kal_bool standby_no_gap; /* True: L1 has no enough gap time for SIB reception */
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ FDD_uas_gemini_conflict_cause_enum conflict_cause;
+ kal_uint16 peer_priority_index;
+#endif
+} fdd_phy_bch_data_ind_struct;
+
+typedef struct _FDD_phy_data_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_cctrch_type_E dl_cctrch; /* PCH, FACH or DCH CCTrCH */
+ kal_uint8 rx_fn; /* FN of the last frame in the TTI that was received */
+ kal_uint16 rx_sfn;
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_uint8 num_trch; /* # of trch */
+ FDD_dlTrchData TrchInfo[FDD_MAX_TRCH_NUM]; /* DL TrCH Info */
+ kal_uint32 crc; /* CRC result for each TB
+ 1 : CRC ok.
+ 0 : CRC error.
+ */
+ //kal_uint32 crc_bits[FDD_MAX_DL_TB]; /* CRC bits of each TB. (Used for Loop back mode) */
+ kal_uint16 num_data; /* Length of the valid byte in data. 0 ~ FDD_MAX_DL_DATA */
+ kal_uint8 *data; /* TB data pointer on share memory. This buffer is allocated by UL1, and freed by UMAC. */
+
+ kal_uint8 num_tb; /* num of TB. UMAC will put this value in the first byte of data allocated from ADM,
+ and the real data part starts at byte 4.*/
+
+ kal_uint32 raw_crc; /* Unmodified CRC for speech decoder */
+ kal_uint32 s_value[FDD_MAX_TRCH_NUM]; /* Viterbi decoder output S value for speech decoder */
+
+ /* UL1A provides debugging info. for VM in DCH dldata*/
+ kal_int16 tpc_SIR_lta; // For recording into speech VM
+ kal_int16 dpdch_SIR_lta; // For recording into speech VM
+ kal_int16 TFCI_max_corr; // For recording into speech VM
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+ FDD_uas_gemini_conflict_cause_enum conflict_cause; /* This field is only used for Gemini. It indicates the channel conflict cause with peer channel.
+ It is only meaningful for PCH and CTCH. */
+ kal_uint8 rx_suspend; /* This field is only used for Gemini 2.0.It is a bitmap to indicate if some TrCH is conflicted with SIM2 gap.
+ The bit is set to ¡§1¡¨ only when the TrCH TTI ends in this frame and SIM2 gap exists in this TTI.
+ LSB bit is mapped to trchInfo[0]. */
+#endif /* __GEMINI__ && __UMTS_RAT__ */
+
+#ifdef __SMART_PAGING_3G_FDD__
+ kal_int8 pi_repeat_cycle;/* -1:invalid, -2:retransmission with CRC pass, 1~20:valid pi_repeat_cyle */
+#endif
+
+ kal_bool is_EBD_CRC_workaround; /*MT6290E1: indicate to MAC if additional CRC append in this data ind due to RXBRP workaround*/
+
+ /* serving cell information for speech debug. */
+ /* These values are valid only when DCH state and RL exists, otherwise, the value will be "0". */
+ kal_uint8 RSSI;
+ kal_uint8 RSCP;
+ kal_uint8 ECIO;
+ kal_uint8 HHO_SHO;
+
+} fdd_phy_data_ind_struct;
+
+typedef struct _fdd_phy_data_buffer_free_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 *data;
+} fdd_phy_data_buffer_free_ind_struct;
+
+typedef struct _FDD_phy_access_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ FDD_access_status_E access_status; /* The result of RACH access */
+} fdd_phy_access_ind_struct;
+
+
+/* __HSDPA_SUPPORT__ */
+typedef struct _FDD_phy_hsdsch_data_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 cfn; /* [Range]: 0-255 */
+ kal_uint8 subframe; /* indicate subf-number of this data_ind */
+ kal_uint8 mac_event; /* bit 0: MAC-hs setup, */
+ /* bit 1: MAC-hs release, */
+ /* bit 2: MAC-hs modify */
+ /* bit 3: MAC-(e)hs reset */
+ kal_uint8 cell_bitmap;
+ FDD_hsdsch_data_T hsdsch_data[FDD_MAX_SUPPORT_CELL];
+
+} fdd_phy_hsdsch_data_ind_struct;
+
+
+
+#ifdef __UMTS_R8__
+typedef struct _FDD_phy_cedch_setup_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_cedch_setup_ind_struct;
+
+typedef struct _FDD_phy_cedch_modify_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_cedch_modify_ind_struct;
+
+typedef struct _FDD_phy_cedch_release_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_cedch_release_ind_struct;
+
+typedef struct _FDD_phy_cedch_termination_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_phy_cedch_termination_req_struct;
+
+typedef struct _FDD_phy_cedch_termination_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool stopped_by_ul1; /* CEDCH is terminated due to radio link failure */
+} fdd_phy_cedch_termination_ind_struct;
+#endif /* __UMTS_R8__ */
+
+/* U3G */
+typedef struct _FDD_ul1_l1sp_update_dch_info_ind_struct
+{
+ LOCAL_PARA_HDR
+
+ /* SP3G_UpdateL1InFo */
+ /* called by L1A to update DCH on/off and TX in/off(DCH UL on/off) */
+ /* bitmap indicates DCH setup type, and value indicates the status */
+ /* bitmap = 0: DCH on/off (1: on, 0: off) */
+ /* bitmap = 1: DCH UL on/off (1: on, 0: off) */
+ /* bitmap = 2: indicate RLF status (1: indicate RLF, 0: reset RLF) */
+ kal_uint8 bitmap;
+ kal_uint8 value;
+} fdd_ul1_l1sp_update_dch_info_ind_struct;
+/* U3G */
+
+
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+
+typedef struct _FDD_rsvas_ul1_suspend_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_rsvas_ul1_suspend_req_struct;
+
+typedef struct _FDD_rsvas_ul1_suspend_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_rsvas_ul1_suspend_cnf_struct;
+
+typedef struct _FDD_rsvas_ul1_resume_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_rsvas_ul1_resume_req_struct;
+#endif
+
+#if defined(__L1_GPS_AUTO_TIMING_SYNC_SUPPORT__) || defined(__L1_GPS_REF_TIME_SUPPORT__)
+/* __GPS_FRAME_SYNC_SUPPORT__ */
+/* CSCE uses this primitive to inform UL1 that OOS occurs when AGPS feature turns on. */
+typedef struct _fdd_cphy_out_of_service_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_cphy_out_of_service_req_struct;
+#endif
+
+typedef struct _FDD_user_wakeup_3g_lock_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 user_sm_handle;
+} FDD_user_wakeup_3g_lock_struct;
+
+/* SEQUENCE OF MCC */
+typedef struct ul1_mcc
+{
+ kal_uint8 numElements;
+
+ kal_uint8 element[3];
+}
+ul1_mcc;
+
+/* SEQUENCE OF MNC */
+typedef struct ul1_mnc
+{
+ kal_uint8 numElements;
+
+ kal_uint8 element[3];
+}
+ul1_mnc;
+
+
+/* SEQUENCE PLMN-Identity */
+typedef struct ul1_plmn_identity
+{
+ ul1_mcc mcc; /* MANDATORY */
+ ul1_mnc mnc; /* MANDATORY */
+}
+ul1_plmn_identity;
+/*****************************************************************************
+* Functions exported to RRC
+*****************************************************************************/
+void UL1_Lcore_Compare_CFN_SFN( UL1_SIM_INDEX_E sim_idx, kal_int16 cfn, kal_int16 sfn, FDD_tgps_time_relationship_E *cfn_sfn_relation );
+void UL1D_PS_SessionStarted( kal_bool If_PS_SessionStarted );
+kal_bool UL1D_FDD_HSDPA_Phy_DualCarrier_Status( void *data );
+
+
+
+/*------------------- Function prototype -----------------------------*/
+/* L1 provides this function to other entities to get current CFN & SFN */
+/* CFN : -1 ~ 255. 0 ~ 255 if UE in DCH/FACH mode otherwise -1 */
+/* SFN : -1 ~ 4095. 0 ~ 4095 for the LST frame number. -1 for an invalid value. */
+void UL1_GetCurrentTime( UL1_SIM_INDEX_E sim_index, kal_int16 *cfn, kal_int16 *sfn );
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*****************************************************************************
+* Function: UL1_Compare_CFN_SFN
+*
+* Parameters: kal_int16 cfn ; cfn which RRCE wants to compare, range:0~255
+* kal_int16 sfn ; sfn which RRCE wants to compare, range:0~4095
+* FDD_tgps_time_relationship_E* cfn_sfn_relation ; FDD_TGPS_AFTER means that expanded CFN is after the specified sfn
+* ; FDD_TGPS_EQUAL means that expanded CFN is equal to the specified sfn
+* ; FDD_TGPS_BEFORE means that expanded CFN is equal to the specified sfn
+* Returns: void
+*
+* Description:
+* The function is to expand the specified CFN to the range 0~4095 and compare the expanded CFN to the specified SFN
+*****************************************************************************/
+void UL1_Compare_CFN_SFN( kal_int16 cfn, kal_int16 sfn, FDD_tgps_time_relationship_E *cfn_sfn_relation );
+
+
+/*****************************************************************************
+* Function: UL1_CEDCH_Check_Started
+*
+* Parameters: Non
+* Returns: If the return value is KAL_TRUE, UL1 has the common EDCH resource, otherwise it's KAL_FALSE.
+*
+* Description:
+* This is a callback function and provide to indicate the common edch status for upper layer.
+* The resolution is frame base because this function is provided by UL1C.
+*****************************************************************************/
+#ifdef __UMTS_R8__
+#define UL1_Lcore_CEDCH_Check_Started UL1_CEDCH_Check_Started
+kal_bool UL1_CEDCH_Check_Started( UL1_SIM_INDEX_E sim_index );
+#endif /* __UMTS_R8__ */
+
+/*****************************************************************************
+* Functions exported to MEME
+*****************************************************************************/
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/*****************************************************************************
+* Functions exported to UMAC
+*****************************************************************************/
+/*****************************************************************************
+* Function: UL1_FreePhyDataIndBuffer
+*
+* Parameters: kal_uint8* data : DL data buffer to be freed
+*
+* Returns: void
+*
+* Description:
+* The function is for UMAC to free the data buffer in PHY_DATA_IND
+*****************************************************************************/
+void UL1_FreePhyDataIndBuffer( kal_uint8 *data );
+
+
+/**********************************************************************************************************************/
+/*********************************** UL1 Interface maintained by UMAC (Begin) *************************************/
+/**********************************************************************************************************************/
+/*UMAC*/
+extern kal_bool FDD_ul_dpch_cctrch(
+ /*UMAC*/ kal_uint8 cfn,
+ /*UMAC*/ kal_bool availabe,
+ /*UMAC*/ kal_bool reconfig_status, /*For notifying DPCH modification*/
+ /*UMAC*/ kal_uint16 *tfci,
+ /*UMAC*/ kal_uint8 *num_trch,
+ /*UMAC*/ FDD_ulTrchData *TrchInfo,
+ /*UMAC*/ kal_uint16 *size_data,
+ /*UMAC*/ kal_uint8 **data );
+/*UMAC*/
+/*UMAC*/
+extern void FDD_ul_dpch_cctrch_task(
+ /*UMAC*/ kal_uint8 cfn,
+ /*UMAC*/ kal_bool availabe,
+ /*UMAC*/ kal_bool reconfig_status /*For notifying DPCH modification*/ );
+/*UMAC*/
+/*UMAC*/
+extern kal_bool FDD_ul_dpch_cctrch_HISR(
+ /*UMAC*/ kal_uint8 cfn,
+ /*UMAC*/ kal_bool availabe,
+ /*UMAC*/ kal_bool reconfig_status, /*For notifying DPCH modification*/
+ /*UMAC*/ kal_uint16 *tfci,
+ /*UMAC*/ kal_uint8 *num_trch,
+ /*UMAC*/ FDD_ulTrchData *TrchInfo,
+ /*UMAC*/ kal_uint16 *size_data,
+ /*UMAC*/ kal_uint8 **data );
+/*UMAC*/
+/*UMAC*/
+extern void FDD_ul_inform_MAC( kal_uint32 data );
+/*UMAC*/
+/*UMAC*/
+extern void FDD_ul_dpch_power( kal_uint8 cfn, kal_uint8 tfc_status[FDD_MAX_UL_TFC] );
+/*UMAC*/
+extern void FDD_mac_hs_get_variable_pdu_buffer( kal_uint8 **buffer_ptr, kal_uint32 num );
+#ifdef __HSDSCH_HARQ_OFF__
+/*UMAC*/extern void FDD_mac_hs_free_variable_pdu_buffer( kal_uint8 **buffer_ptr, kal_uint32 num ); // for HARQ off
+#endif
+/*UMAC*/extern void FDD_mac_hs_get_pdu_buffer( kal_uint8 **buffer_ptr );
+/*UMAC*/
+/*UMAC*/
+extern FDD_uldch_data_ind_T *FDD_UMAC_UL_DCH_Tick_LISR( UL1_SIM_INDEX_E sim_idx, FDD_uldch_data_req_T *uldch_data_req );
+/*UMAC*/
+extern FDD_etfc_eval_info_ind_T *FDD_umac_e_dch_evaluate_tx_process_LISR( UL1_SIM_INDEX_E sim_idx, FDD_etfc_eval_info_req_T *etfc_eval_input );
+/*UMAC*/
+extern kal_bool FDD_umac_e_dch_is_tx_permitted_LISR( UL1_SIM_INDEX_E sim_idx, kal_uint8 *supported_etfci_bitmap, FDD_edch_scell_E edch_cell, kal_bool *is_sched_data_included );
+/*UMAC*/
+extern FDD_edch_data_ind_T *FDD_umac_e_dch_prepare_data_LISR( UL1_SIM_INDEX_E sim_idx, FDD_edch_data_req_T *edch_data_input );
+/*UMAC*/
+extern kal_bool FDD_umac_e_dch_get_happy_bit_LISR( UL1_SIM_INDEX_E sim_idx, kal_bool happy[FDD_E_SCELL_TOTAL] );
+/*UMAC*/
+extern void FDD_umac_e_dch_post_tx_process_LISR( UL1_SIM_INDEX_E sim_idx );
+/*UMAC*/
+extern void FDD_umac_e_dch_update_ref_etpr_LISR( UL1_SIM_INDEX_E sim_idx, kal_bool tx_enable[FDD_E_SCELL_TOTAL], kal_uint32 ref_etpr_x225[FDD_E_SCELL_TOTAL] );
+/*UMAC*/
+extern void FDD_try_to_trigger_CSR_STATUS_IND_LISR( UL1_SIM_INDEX_E sim_idx, kal_uint8 cfn );
+/*UMAC*/
+extern kal_bool FDD_umac_e_dch_predict_tx_process_LISR( UL1_SIM_INDEX_E sim_idx, FDD_etfc_eval_lpr_info_req_T *info );
+/*UMAC*/
+extern void FDD_ul_inform_Edch_MAC( void *data );
+/*UMAC*/
+extern void FDD_send_CSR_STATUS_IND( kal_uint32 data );
+/*UMAC*/
+/*UMAC*/
+#define FDD_UMAC_UL_DCH_Tick(sim_idx,uldch_data_req) FDD_UMAC_UL_DCH_Tick_LISR(sim_idx,uldch_data_req)
+/*UMAC*/#define FDD_umac_e_dch_tick_1( sim_idx, etfc_eval_input ) FDD_umac_e_dch_evaluate_tx_process_LISR( sim_idx, etfc_eval_input )
+/*UMAC*/#define FDD_umac_e_dch_is_tx_permitted( sim_idx, supported_etfci_bitmap, edch_cell, is_sched_data_included ) FDD_umac_e_dch_is_tx_permitted_LISR( sim_idx, supported_etfci_bitmap, edch_cell, is_sched_data_included )
+/*UMAC*/#define FDD_umac_e_dch_tick_2( sim_idx, edch_data_input ) FDD_umac_e_dch_prepare_data_LISR( sim_idx, edch_data_input )
+/*UMAC*/#define FDD_umac_e_dch_get_happy_bit( sim_idx, happy ) FDD_umac_e_dch_get_happy_bit_LISR( sim_idx, happy )
+/*UMAC*/#define FDD_umac_e_dch_tick_3( sim_idx, tx_enable, ref_etpr_x225 ) FDD_umac_e_dch_post_tx_process_LISR( sim_idx )
+/*UMAC*/#define FDD_umac_e_dch_tick_4( sim_idx ) {} //FDD_umac_e_dch_tick_4_LISR(sim_idx)
+/*UMAC*/#define FDD_umac_e_dch_update_ref_etpr( sim_idx, tx_enable, ref_etpr_x225 ) FDD_umac_e_dch_update_ref_etpr_LISR( sim_idx, tx_enable, ref_etpr_x225 )
+/*UMAC*/#define FDD_umac_e_dch_tick_5( sim_idx, info ) FDD_umac_e_dch_predict_tx_process_LISR( sim_idx, info )
+/*UMAC*/
+/*UMAC*//*========== UMAC END TX STRUCT (BEGIN) ==========*/
+/*UMAC*/typedef struct _FDD_phy_end_dch_tx_ind_struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ /*UMAC*/
+} fdd_phy_end_dch_tx_ind_struct;
+/*UMAC*/
+/*UMAC*//* __HSUPA_SUPPORT__ */
+/*UMAC*/
+typedef struct _FDD_phy_end_edch_tx_ind_struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_uint8 subframe;
+ /*UMAC*/
+ kal_uint8 harq_id;
+ /*UMAC*/
+ kal_uint8 mode;
+ /*UMAC*/
+} fdd_phy_end_edch_tx_ind_struct;
+/*UMAC*//*========== UMAC END TX STRUCT (END) ==========*/
+/*UMAC*//*========== UMAC UT SIMULATE MESSAGE ==========*/
+/*UMAC*///#ifdef __MNT_UT_UMAC_ALONE_WITHOUT_L1__ /* UMAC UT */
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_bool availabe;
+ /*UMAC*/
+ kal_bool reconfig_status;
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_cctrch_task_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_uint8 ul_mac_event; /* bit 0: UL DCH setup, */
+ /*UMAC*/ /* bit 1: UL DCH release, */
+ /*UMAC*/ /* bit 2: UL DCH modify */
+ /*UMAC*/
+ kal_uint8 dpdch_num;
+ /*UMAC*/
+ kal_bool restartSRB; /* set true when PCP_Finish (not align max TTI) */
+ /*UMAC*/
+ kal_bool tx_enable; /* set true if TX data could be sent (min TTI) */
+ /*UMAC*/
+ kal_bool tx_suspend;
+ /*UMAC*/
+ kal_uint8 tfc_status[FDD_MAX_UL_TFC];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_cctrch_lisr_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_bool availabe;
+ /*UMAC*/
+ kal_bool reconfig_status;
+ /*UMAC*/ /* Use structure instead of pointer to simulate this */
+ /*UMAC*/
+ kal_uint16 tfci;
+ /*UMAC*/
+ kal_uint8 num_trch;
+ /*UMAC*/
+ FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint16 size_data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint8 *data[FDD_MAX_UL_TB];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_cctrch_hisr_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_uint8 num_trch;
+ /*UMAC*/
+ FDD_ulTrchData trchInfo[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint16 tfci;
+ /*UMAC*/
+ kal_uint16 num_data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint8 *data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ /*UMAC*/
+#ifdef UNIT_TEST
+ /*UMAC*/ void *addr;
+ /*UMAC*/
+#endif /* UNIT_TEST */
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_cctrch_lisr_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_bool availabe;
+ /*UMAC*/
+ kal_bool reconfig_status;
+ /*UMAC*/ /* Use structure instead of pointer to simulate this */
+ /*UMAC*/
+ kal_uint16 tfci;
+ /*UMAC*/
+ kal_uint8 num_trch;
+ /*UMAC*/
+ FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint16 size_data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint8 *data[FDD_MAX_UL_TB];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_cctrch_hisr_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_bool availabe;
+ /*UMAC*/
+ kal_bool reconfig_status;
+ /*UMAC*/ /* Use structure instead of pointer to simulate this */
+ /*UMAC*/
+ kal_uint16 tfci;
+ /*UMAC*/
+ kal_uint8 num_trch;
+ /*UMAC*/
+ FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint16 size_data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint8 *data[FDD_MAX_UL_TB];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_callback_cctrch_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_uint8 tfc_status[FDD_MAX_UL_TFC];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_callback_power_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct /* Old DCH Callback */
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ kal_bool availabe;
+ /*UMAC*/
+ kal_bool reconfig_status; /*MA only, for notifying DPCH modification*/
+ /*UMAC*/ /* Use structure instead of pointer to simulate this */
+ /*UMAC*/
+ kal_uint16 tfci;
+ /*UMAC*/
+ kal_uint8 num_trch;
+ /*UMAC*/
+ FDD_ulTrchData TrchInfo[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint16 size_data[FDD_MAX_TRCH_NUM];
+ /*UMAC*/
+ kal_uint8 *data[FDD_MAX_UL_TB];
+ /*UMAC*/
+} fdd_phy_simulate_dch_ul_callback_cctrch_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+ /*UMAC*/
+} fdd_phy_simulate_end_dch_tx_ind_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/ /* For MT6291 U3G */
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ FDD_etfc_eval_info_req_T etfc_eval_info_req;
+ /*UMAC*/
+ /*UMAC*/
+ kal_uint8 sf_of_etfci[8][128 / 2];
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_eval_tx_proc_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ FDD_etfc_eval_info_ind_T etfc_eval_info_ind;
+ /*UMAC*/
+ kal_uint8 active_process[FDD_E_SCELL_TOTAL]; /* easy to check the result after processing AG command */
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_eval_tx_proc_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ /* MAX_NUM_OF_ETFC = 128 */
+ /*UMAC*/ kal_uint8 supported_etfci_bitmap[128 / 4];
+ /*UMAC*/
+ /*UMAC*/ /* FDD_MAX_NTX1_10MS = (15-8+1), FDD_MAX_ETFC_NUM = 128 */
+ /*UMAC*/
+ FDD_edch_scell_E edch_cell;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_is_tx_permit_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_bool is_sched_data_included;
+ /*UMAC*/
+ kal_bool tx_enable;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_is_tx_permit_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ FDD_edch_data_req_T edch_data_req;
+ /*UMAC*/ /* FDD_MAX_ETFC_NUM = 128 */
+ /*UMAC*/
+ kal_uint8 supported_etfci_bitmap[128 / 4];
+ /*UMAC*/
+ kal_uint32 FRC_Curr_Time;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_prepare_data_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ FDD_edch_data_ind_T edch_data_ind;
+ /*UMAC*/
+ kal_uint8 SI_HLID; /* easy to check result of Highest Priority Logical Channel Identity */
+ /*UMAC*/
+ kal_uint32 SI_HLBS; /* easy to check result of Highest priority Logical channel Buffer Status (Bytes) */
+ /*UMAC*/
+ kal_uint8 NoOfCoproTBTriggered;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_prepare_data_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_get_happy_bit_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_bool happy[FDD_E_SCELL_TOTAL]; /* easy to check result of Highest priority Logical channel Buffer Status (Bytes) */
+ /*UMAC*/
+ kal_bool is_tebs_larger_than_0;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_get_happy_bit_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint32 FRC_Curr_Time;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_post_tx_proc_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 NoOfCoproTBTriggered;
+ /*UMAC*/
+ kal_uint8 NotifyRLCHarqBitmap[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_post_tx_proc_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+#ifdef __UMTS_R7__
+/*UMAC*/typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ FDD_etfc_eval_lpr_info_req_T etfc_eval_lpr_info_req;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_predict_tx_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_bool result;
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_predict_tx_rsp_struct;
+#endif /* __UMTS_R7__*/
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_bool tx_enable[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+ kal_uint32 ReferenceEtpr[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_update_ref_etpr_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_update_ref_etpr_rsp_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ /* MAX_NUM_OF_ETFC = 128 */
+ /*UMAC*/ kal_uint8 supported_etfci_bitmap[128 / 4];
+ /*UMAC*/
+ /*UMAC*/ /* NUM_OF_NTX1_10MS = (15-8+1), MAX_NUM_OF_ETFC = 128 */
+ /*UMAC*/
+ kal_uint8 sf_of_etfci[8][128 / 2];
+ /*UMAC*/
+} fdd_phy_simulate_umac_e_dch_tx_param_setup_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/
+} fdd_phy_simulate_try_to_trigger_csr_status_ind_struct;
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ kal_uint8 ref_count;
+ /*UMAC*/
+ kal_uint16 msg_len;
+ /*UMAC*/
+ /*UMAC*/
+ kal_uint8 get_num;
+ /*UMAC*/
+} fdd_phy_simulate_umac_get_hs_buffer_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ kal_uint8 ref_count;
+ /*UMAC*/
+ kal_uint16 msg_len;
+ /*UMAC*/
+ /*UMAC*/
+ kal_uint8 free_num;
+ /*UMAC*/
+} fdd_phy_simulate_umac_free_hs_buffer_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint32 NoOfEdchCell;
+ /*UMAC*/
+} fdd_phy_simulate_umac_forced_to_send_edch_em_info_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+} fdd_phy_simulate_umac_forced_to_send_hsdsch_em_info_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_bool b_pch_Crc;
+ /*UMAC*/
+ kal_bool b_em_from_logger;
+ /*UMAC*/
+} fdd_phy_simulate_umac_setup_pch_em_info_struct;
+/*UMAC*///#endif /* __MNT_UT_UMAC_ALONE_WITHOUT_L1__ */
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint32 kpi;
+ /*UMAC*/
+} fdd_phy_simulate_umac_forced_to_send_mdmi_mac_em_info_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/ kal_uint32 kpi;
+ /*UMAC*/ kal_uint8 cfn;
+ /*UMAC*/ kal_uint8 subframe;
+ /*UMAC*/ kal_uint8 harq_id;
+ /*UMAC*/ kal_uint8 dummy;
+ /*UMAC*/
+} fdd_phy_simulate_umac_forced_to_send_mdmi_upa_em_info_struct;
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+} fdd_phy_simulate_umac_forced_to_send_mdmi_mea_em_info_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*//*========== END UMAC UT SIMULATE MESSAGE ==========*/
+/*UMAC*/
+/*UMAC*//*========== UMAC DEBUG MESSAGE ==========*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+ /*UMAC*/ FDD_etfc_eval_info_req_T etfc_eval_info_req;
+ /*UMAC*/
+ FDD_etfc_eval_info_ind_T etfc_eval_info_ind;
+ /*UMAC*/
+ kal_uint8 ServingGrant;
+ /*UMAC*/
+ kal_bool old_isNewTransmission;
+ /*UMAC*/
+ kal_bool update_isNewTransmission;
+ /*UMAC*/
+ /*UMAC*/
+} FDD_umac_umac_edch_eval_tx_proc_ind_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+ /*UMAC*/ FDD_edch_data_ind_T edch_data_ind;
+ /*UMAC*/
+ kal_uint8 supported_etfci_bitmap[32];
+ /*UMAC*/
+} FDD_umac_umac_edch_prepare_data_ind_struct;
+/*UMAC*/
+/*UMAC*/
+/*UMAC*/
+typedef struct
+/*UMAC*/
+{
+ /*UMAC*/ LOCAL_PARA_HDR
+ /*UMAC*/
+ /*UMAC*/ kal_bool tx_enable[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+ kal_uint8 old_ReferenceEtpr[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+ kal_uint8 update_ReferenceEtpr[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+ kal_uint32 ref_etpr_x225[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+ kal_uint32 update_ref_etpr_x225[FDD_E_SCELL_TOTAL];
+ /*UMAC*/
+} FDD_umac_umac_edch_post_tx_proc_ind_struct;
+/*UMAC*//*========== END UMAC DEBUG MESSAGE ==========*/
+/**********************************************************************************************************************/
+/*********************************** UL1 Interface maintained by UMAC (END) *************************************/
+/**********************************************************************************************************************/
+
+/*------------------- MSC Composer -----------------------------*/
+/* The following definition is used only for MSC composer. */
+typedef union _FDD_local_para_unpack_T
+{
+ fdd_cphy_pch_setup_req_struct cphy_pch_setup_req;
+ fdd_cphy_pch_modify_req_struct cphy_pch_modify_req;
+ fdd_cphy_pch_release_req_struct cphy_pch_release_req;
+ fdd_cphy_fach_setup_req_struct cphy_fach_setup_req;
+ fdd_cphy_fach_modify_req_struct cphy_fach_modify_req;
+ fdd_cphy_fach_release_req_struct cphy_fach_release_req;
+ fdd_cphy_dch_setup_req_struct cphy_dch_setup_req;
+ fdd_cphy_dch_modify_req_struct cphy_dch_modify_req;
+ fdd_cphy_dch_release_req_struct cphy_dch_release_req;
+ fdd_cphy_rach_setup_req_struct cphy_rach_setup_req;
+ fdd_cphy_rach_release_req_struct cphy_rach_release_req;
+ fdd_cphy_hsdsch_setup_req_struct cphy_hsdsch_setup_req;
+ fdd_cphy_hsdsch_modify_req_struct cphy_hsdsch_modify_req;
+ fdd_cphy_hsdsch_release_req_struct cphy_hsdsch_release_req;
+ fdd_cphy_edch_setup_req_struct cphy_edch_setup_req;
+ fdd_cphy_edch_modify_req_struct cphy_edch_modify_req;
+ fdd_cphy_edch_release_req_struct cphy_edch_release_req;
+#ifdef __UMTS_R7__
+ fdd_cphy_cpc_config_req_struct cphy_cpc_setup_req;
+#endif /* __UMTS_R7__ */
+} FDD_local_para_unpack_T;
+
+typedef struct _FDD_msg_buf_unpack_T /* Buffer of message container */
+{
+ kal_uint8 channel_id; /* Channel ID */
+ msg_type msg_id; /* Message ID */
+ kal_uint16 buff_size; /* Buffer size */
+ FDD_local_para_unpack_T buffer; /* Channel configuration message buffer */
+} FDD_msg_buf_unpack_T;
+
+typedef struct _fdd_cphy_msg_container_req_unpack_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 at_ref; /* Reference channge of activation time.
+ 0 : Ref channel is the released channel.
+ There should be ch to be released
+ 1 : Ref channel is the setup channel.
+ There should be ch to be setup.
+ */
+ kal_int16 rx_cfn; /* Indicate peer message receive cfn. Ex: tti = 4, receive frame number : 0,1,2,3. rx_cfn = 3 (set by ul1)
+ [Range]: -1 ~ 255.
+ -1 : Means upper layer internal control
+ */
+#ifdef __UMTS_R6__
+ kal_bool delay_restriction; /* From R6 : TS25.331 8.6.3.1 */
+#endif
+ FDD_meas_control_E meas_control; /* Indicate whether UL1 need to not to resume meas. after apply corresponding buffer's config. */
+
+ kal_uint8 msg_num; /* # of included msg. 1 ~ 4 */
+ FDD_msg_buf_unpack_T msg_buffer[4]; /* List of msg buffer for included channel msg */
+
+ /* [R5R6] For HS-DSCH and E-DCH */
+ kal_uint8 h_msg_num; /* # of included H-msg. 0~2 */
+ FDD_msg_buf_unpack_T h_msg_buffer[2]; /* List of msg buffer for included channel msg */
+ kal_uint8 e_msg_num; /* # of included E-msg. 0~2 */
+ FDD_msg_buf_unpack_T e_msg_buffer[2]; /* List of msg buffer for included channel msg */
+#ifdef __UMTS_R7__
+ kal_uint8 cpc_msg_num; /* # of included CPC-msg. 0~1 */
+ FDD_msg_buf_unpack_T cpc_msg_buffer[1]; /* List of msg buffer for included CPC msg */
+#endif /* __UMTS_R7__ */
+} fdd_cphy_msg_container_req_unpack_struct;
+
+typedef struct _ul1_umts_max_tx_pwr_red_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_bool valid;
+ //UMTS_CUSTOM_TAS_STATE_E tas_state; /*0: Main, 1: Div, 2: Main'*/
+ kal_uint8 umts_power_reduction_in_edb[20][2/*Service*/];
+
+ /* Add power reduction value for ANT1 (op=9/10).
+ * When user only specify one set of values by using op=1/3,
+ * L4C help copy parameters from umts_power_reduction_in_edb[] to umts_power_reduction_in_edb_tas[]*/
+ kal_uint8 umts_power_reduction_in_edb_tas[20][2/*Service*/];
+} ul1_umts_max_tx_pwr_red_req_struct;
+
+typedef enum
+{
+ FDD_UL1_EM_TST_CMD_TX_DPCH = 0,
+ FDD_UL1_EM_TST_CMD_RX_RSSI_MEASURE = 1,
+ FDD_UL1_EM_TST_CMD_GET_PD_MEASUREMENT = 2, // retrieved TX power
+ FDD_UL1_EM_TST_CMD_END
+} FDD_UL1_EM_TSTCmdType;
+
+typedef struct
+{
+ kal_int8 power;
+ kal_uint8 rf_band;
+ kal_uint16 ul_freq;
+} FDD_UL1_EM_TSTCmdTxDPCh_T;
+
+typedef struct
+{
+ kal_uint16 dl_freq;
+} FDD_UL1_EM_TSTCmdRxRSSI_T;
+
+typedef union
+{
+ FDD_UL1_EM_TSTCmdTxDPCh_T txdpch;
+ FDD_UL1_EM_TSTCmdRxRSSI_T rxrssi;
+} FDD_UL1_EM_TSTCmdParam;
+
+typedef struct _l4ul1_em_tst_req_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 src_id;
+ FDD_UL1_EM_TSTCmdType type;
+ FDD_UL1_EM_TSTCmdParam param;
+} l4ul1_em_tst_req_struct;
+
+
+typedef struct _l4ul1_em_tst_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 src_id;
+ kal_bool success;
+#if defined(__ATERFTX_ERROR_HANDLE_ENHANCE__)
+ ps_cause_enum err_cause;
+#endif //__ATERFTX_ERROR_HANDLE_ENHANCE__
+} l4ul1_em_tst_cnf_struct;
+
+typedef struct _l4ul1_em_tx_report_ind
+{
+ LOCAL_PARA_HDR
+
+ kal_int32 tx_power; // retrieved TX power
+} l4ul1_em_tx_report_ind_struct;
+
+typedef l4ul1_em_tst_req_struct l4cul1_em_tst_control_req_struct;
+typedef l4ul1_em_tst_cnf_struct l4cul1_em_tst_control_cnf_struct;
+typedef l4ul1_em_tx_report_ind_struct l4cul1_em_tx_report_ind_struct;
+
+typedef struct _l4cul1_get_rf_temperature_req_struct
+{
+ LOCAL_PARA_HDR
+
+} l4cul1_get_rf_temperature_req_struct;
+
+typedef struct _l4cul1_get_rf_temperature_cnf_struct
+{
+ LOCAL_PARA_HDR
+
+ kal_int16 modem_temperature;
+} l4cul1_get_rf_temperature_cnf_struct;
+
+typedef struct _l4cul1_rssi_measurement_ind_struct
+{
+ LOCAL_PARA_HDR
+ kal_int16 rssi[2]; /* RSSI. Range: -400 ~ -100 means (-100 ~ -25)dBm 0.25 dB step */
+ kal_int32 rssi_edBm[2]; /* RSSI value in 1/8 dBm */
+ kal_uint16 uarfcn; /* UARFCN */
+
+} l4cul1_rssi_measurement_ind_struct;
+
+/* Inform SLT task that UL1 has finished task init */
+typedef struct _FDD_ul1_slt_task_init_ind_struct
+{
+ LOCAL_PARA_HDR
+
+} fdd_ul1_slt_task_init_ind_struct;
+
+#if defined (__MML1_ADT_ENABLE__)
+/*****************************************************************************
+ UL1 req for ADT Task
+*****************************************************************************/
+typedef struct _fdd_ul1_l1adt_enter_connected_req_struct
+{
+ LOCAL_PARA_HDR
+ FDD_ADT_Mode_E adt_mode;
+} fdd_ul1_l1adt_enter_connected_req_struct;
+
+typedef struct _fdd_ul1_l1adt_leave_connected_req_struct
+{
+ LOCAL_PARA_HDR
+ FDD_ADT_Mode_E adt_mode;
+} fdd_ul1_l1adt_leave_connected_req_struct;
+
+typedef struct _fdd_ul1_l1adt_enter_fdd_mode_req_struct
+{
+ LOCAL_PARA_HDR
+} fdd_ul1_l1adt_enter_fdd_mode_req_struct;
+
+typedef struct _fdd_ul1_l1adt_enter_fdd_mode_ind_struct
+{
+ LOCAL_PARA_HDR
+} fdd_ul1_l1adt_enter_fdd_mode_ind_struct;
+
+/*****************************************************************************
+ confirm from ADT Task to UL1
+*****************************************************************************/
+typedef struct _fdd_ul1_l1adt_enter_connected_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_int32 adt_dl_result;
+ /*
+ {//PASS_DL_(UN)COMPLETE_xxx -> xxx means the current RAT mode
+ FAIL_OTHER_RAT_IS_CONN,
+ PASS_DL_COMPLETE_CONN,
+ PASS_DL_NOT_YET_FINISHED_CONN,
+ PASS_DL_COMPLETE_IDLE,
+ PASS_DL_NOT_YET_FINISHED_IDLE,
+ PASS_STOP_N_RESTART_DL_IDLE,
+ PASS_START_DL_IDLE
+ }
+ */
+} fdd_ul1_l1adt_enter_connected_cnf_struct;
+
+typedef struct _fdd_ul1_l1adt_leave_connected_cnf_struct
+{
+ LOCAL_PARA_HDR
+ kal_int32 idle_result;
+ /*
+ {
+ NORMAL,
+ ABNORMAL_IDLE,
+ ABNORMAL_OTHER_CONN
+ }
+ */
+} fdd_ul1_l1adt_leave_connected_cnf_struct;
+
+typedef struct _fdd_ul1_l1adt_enter_fdd_mode_cnf_struct
+{
+ LOCAL_PARA_HDR
+} fdd_ul1_l1adt_enter_fdd_mode_cnf_struct;
+
+#endif
+
+/******************************************************************************
+ * MSG_ID_UL1D_LOOPBACK_REQ primptive
+ * FROM : TST
+ * TO : Dummy UPS
+ * DESCRIPTION :
+ *
+ ******************************************************************************/
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 test_id;
+ kal_uint16 case_id;
+ kal_uint16 pattern_id;
+ void *pattern_address;
+ kal_uint32 pattern_size; // unit: byte
+ kal_uint32 pm[10];
+ kal_uint32 sz[30];
+ kal_uint32 ad[30];
+} ul1d_loopback_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 test_id;
+ kal_uint16 case_id;
+ kal_uint16 pattern_id;
+ void *pattern_address;
+ kal_uint32 pattern_size; // unit: byte
+ kal_uint32 pm[10];
+ kal_uint32 sz[30];
+ kal_uint32 ad[30];
+} modem_loopback_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 test_id;
+ kal_uint16 case_id;
+ kal_uint16 pattern_id;
+ kal_bool result; // true=pass, false=fail
+ char trace_msg[256]; // null-terminated string
+} modem_loopback_result_ind_struct;
+/* Yuda.lee added for Android M */
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 srcid; /* srcid is set by REQUEST */
+ kal_uint32 lce_mode; /* STOP: 0, PUSH MODE: 1, PULL_MODE: 2 */
+ kal_uint32 lce_rpt_interval_ms; /* flexible time unit [ms] */
+} l4cul1_hspa_lce_report_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 srcid; /* srcid is set by REQUEST */
+} l4cul1_hspa_lce_report_pulldata_req_struct;
+
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 srcid; /* srcid is same as REQUEST */
+ kal_int8 lce_status; /* stopped:0, active: 1 */
+ kal_uint32 lce_act_interval_ms; /* actually reporting interval, unit [ms]*/
+} l4cul1_hspa_lce_report_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ kal_uint8 srcid; /* PUSH MODE: 0xFF, otherwise srcid is same as REQUEST */
+ kal_uint8 conf_level; /* confidence level of capacity estimate (0~100)*/
+ kal_uint8 lce_suspend; /* 0: not suspended, 1: suspended, radio idle, handover, outage, and etc.*/
+ kal_uint32 last_hop_cap_kbps; /* capacity:kilobits/second, kbps*/
+} l4cul1_hspa_lce_report_ind_struct;
+
+#endif
+
diff --git a/mcu/interface/l1/ul1/internal/wlog3g.h b/mcu/interface/l1/ul1/internal/wlog3g.h
new file mode 100644
index 0000000..9521447
--- /dev/null
+++ b/mcu/interface/l1/ul1/internal/wlog3g.h
@@ -0,0 +1,33 @@
+void WriteHWRegister(kal_uint32 Address, kal_uint16 Value);
+void USB_LOGGING_3G_HISR(void);
+
+kal_uint16 USB_LOGGING_Get_3G_Status(kal_uint32 buf_index);
+void USB_LOGGING_3G_Reset(void);
+void USB_LOGGING_3G_Restart(void);
+void USB_LOGGING_3G_Init(kal_uint8* add1, kal_uint8* add2, kal_uint8* add3, kal_uint8* add4);
+void USB_LOGGING_3G_Start(void);
+void USB_LOGGING_3G_Stop(void);
+void USB_LOGGING_3G_LISR(void);
+void USB_LOGGING_3G_Drv_Create_ISR(void);
+void USB_LOGGING_3G_Clear_Buffer(kal_uint8 buf_idx, kal_uint8 idx);
+
+
+#define LOG3G_USB_L1D_FLLT_1 0x02
+#define LOG3G_USB_L1D_RDY_1 0x70
+#define LOG3G_USB_L1D_PID_1 0x3216
+#define LOG3G_USB_L1D_LEN_1 1024
+#define LOG3G_USB_L1D_ADDR_1 0x00
+
+/* LOG3G_USB_BUF_CTRL */
+#define LOG3G_USB_BUF_CTRL_CLR 0x00000000
+#define LOG3G_USB_BUF_CTRL_RDY 0x00000001
+#define LOG3G_USB_BUF_CTRL_RST 0x00000002
+#define LOG3G_LOG_ENABLE 0x80000000
+#define LOG3G_SCALER_DUMP_ENABLE 0x00000001
+
+#if IS_3G_CHIP_MT6276_AND_LATTER_VERSION
+#define LOG3G_ATB_BUFFER_NUM 0x0000000f
+#define LOG3G_ATB_BUFFER_SIZE 0x00007fff
+#define LOG3G_ATB_IF_ENABLE 0x40000000
+#endif
+