[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/l1/ul1/internal/ul1_def.h b/mcu/interface/l1/ul1/internal/ul1_def.h
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+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * ul1_def.h
+ *
+ * Project:
+ * --------
+ * WCDMA_Software
+ *
+ * Description:
+ * ------------
+ * This file contains common typedef, definition prototypes exported by L1
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _UL1_DEF_H
+#define _UL1_DEF_H
+
+/* auto add by kw_check begin */
+#include "ul1_cnst.h"
+#include "kal_general_types.h"
+/* auto add by kw_check end */
+
+#include "gmss_public.h"
+#include "ul1_protected_def.h"
+
+
+/* ---------------------- L+W Gemini ----------------------*/
+typedef enum _UL1_SIM_INDEX_E
+{
+ UL1_SIM_1 = 0,
+#ifdef __GEMINI_WCDMA__
+ UL1_SIM_2,
+#if (GEMINI_PLUS_WCDMA >= 3)
+ UL1_SIM_3,
+#if (GEMINI_PLUS_WCDMA >= 4)
+ UL1_SIM_4,
+#endif /* GEMINI_PLUS_WCDMA >= 4 */
+#endif /* GEMINI_PLUS_WCDMA >= 3 */
+#endif /* __GEMINI_WCDMA__ */
+ UL1_SIM_NUM
+} UL1_SIM_INDEX_E;
+
+#if (GEMINI_PLUS_WCDMA > 4)
+#error "The number of SIM can't be over than 4 pieces."
+#endif
+
+/*-------------------- ADT -----------------------*/
+typedef enum _FDD_ADT_Mode_E
+{
+ FDD_ADT_NONE = 0,
+ FDD_ADT_NORMAL,
+ FDD_ADT_TALKING
+} FDD_ADT_Mode_E;
+
+/*-------- TGPS related definition ----------------------*/
+typedef enum _FDD_tgps_act_E
+{
+ FDD_TGPS_ACTIVATE, /* Activate the TGPS */
+ FDD_TGPS_DEACTIVATE /* Deactivate the TGPS */
+} FDD_tgps_act_E;
+
+typedef enum _FDD_tg_mode_E
+{
+ FDD_TG_UL, /* UL only */
+ FDD_TG_DL, /* DL only */
+ FDD_TG_UL_DL /* Both UL and DL */
+} FDD_tg_mode_E;
+
+typedef enum _FDD_tgmp_E
+{
+ FDD_TG_FDD_MEASURE, /* Inter-frequency measurement */
+ FDD_TG_GSM_RSSI, /* GSM RSSI measurement */
+ FDD_TG_GSM_BSIC_INIT, /* GSM initial BSIC */
+ FDD_TG_GSM_BSIC_CNF, /* GSM BSIC confirm */
+ FDD_TG_EUTRA, /* E-UTRA */
+ FDD_TG_TGMP_UNDEFINED
+} FDD_tgmp_E;
+
+typedef enum _FDD_tg_method_E
+{
+ FDD_TG_PUNCT, /* Puncturing. only for DL */
+ FDD_TG_HLS, /* Higher layer scheduling */
+ FDD_TG_SF_2, /* SF/2 */
+ FDD_TG_NONE /* None */
+} FDD_tg_method_E;
+
+typedef struct _FDD_tgps_info_T
+{
+ kal_uint8 tgpsi; /* TGPSI. 1 ~ 6 */
+ kal_uint8 tgcfn; /* TGCFN. 0 ~ 255 */
+ FDD_tgps_act_E status; /* Action applied to TGPS */
+ kal_bool tgps_para_valid; /* indicate if following parameter should be modifed */
+ FDD_tgmp_E purpose; /* TGMP. TGPS purpose */
+ FDD_tg_mode_E mode; /* TG mode */
+ FDD_tg_method_E ul_method; /* UL TG method */
+ FDD_tg_method_E dl_method; /* DL TG method */
+ kal_uint8 rpp; /* RPP. 0 or 1 */
+ kal_uint8 itp; /* ITP. 0 or 1 */
+ kal_uint8 dl_frame_type; /* DL TG frame type. 0 : type A. 1 : type B */
+ kal_uint8 sir1; /* DeltaSIR1. 0 ~ 30. true value is sir1/10 */
+ kal_uint8 sir_after1; /* DeltaSIRafter1. 0 ! 10. true value is sir_after1/10 */
+ kal_uint8 sir2; /* DeltaSIR1. 0 ~ 30. true value is sir2/10 */
+ kal_uint8 sir_after2; /* DeltaSIRafter1. 0 ! 10. true value is sir_after2/10 */
+ kal_uint16 tgprc; /* TGPRC. 0 ~ 511. 0 for infinity*/
+ kal_uint8 tgsn; /* TGSN. 0 ~ 14 */
+ kal_uint8 tgl1; /* TGL1. 1 ~ 14 slts */
+ kal_uint8 tgl2; /* TGL2. 1 ~ 14 slts */
+ kal_uint16 tgd; /* TGD. 15 ~ 270. 270 means TGD is undefed (only 1 TG) */
+ kal_uint8 tgpl1; /* TGPL1. 1 ~ 144 */
+ kal_uint8 tgpl2; /* TGPL2. 1 ~ 144 */
+ kal_uint8 ident_abort; /* N_IDENTIFY_ABORT. 1 ~ 128 */
+ kal_uint8 reconf_abort; /* Treconfirm_abort. 1 ~ 20. true value is divided by 2 */
+ kal_bool freq_specific_compressed_mode; /* [R10] true: tgps is not applied on serving band. */
+} FDD_tgps_info_T;
+
+typedef enum _FDD_tgps_status_E
+{
+ FDD_TGPS_ACTIVE,
+ FDD_TGPS_DEACTIVE
+} FDD_tgps_status_E;
+
+typedef struct _FDD_tgps_status_T
+{
+ kal_uint8 tgpsi; /* TGPS index */
+ kal_uint8 tgcfn; /* TGCFN. 0 ~ 255 */
+ FDD_tgps_status_E status; /* Status to be applied to TGPS */
+ kal_bool freq_specific_compressed_mode; /* [R10] true: tgps is not applied on serving band. */
+} FDD_tgps_status_T;
+
+typedef struct _FDD_tgps_status_info_T
+{
+ kal_uint8 num_tgps; /* # of TGPS status pattern */
+ kal_int16 reconf_time; /* TGPS reconfiguration CFN. -1 ~ 255. -1 means immediate */
+ FDD_tgps_status_T tgps_status[FDD_MAX_TGPS]; /* TGPS status information */
+} FDD_tgps_status_info_T;
+
+
+typedef struct _FDD_tgps_config_T
+{
+ kal_uint8 tgpsi; /* tgpsi */
+ FDD_tgmp_E tgmp; /* purpose of this tgpsi */
+ FDD_tgps_status_E status; /*tgps status at the activation time*/
+} FDD_tgps_config_T;
+
+typedef struct _FDD_p_tgps_config_T
+{
+ kal_int16 sfn; /* reconfig time of this pending tgps configuration*/
+ kal_uint8 tgps_num; /* number of tgps in this pneding tgps */
+ FDD_tgps_config_T tgps[FDD_MAX_TGPS]; /* tgps config (tgpsi, tgmp, status) */
+} FDD_p_tgps_config_T;
+
+typedef struct _FDD_tgps_config_by_tgmp_T
+{
+ kal_uint8 tgpsi; /* tgpsi for the tgmp */
+ kal_uint8 p_tgps_config_num; /* pending tgps_config num of this tgpsi */
+ kal_bool c_tgps_config_valid; /* existence of current tgps_config of this tgpsi,
+ if false, c_tgps_config is meaningless */
+ FDD_tgps_config_T c_tgps_config; /* current tgps_config of this tgpsi */
+ FDD_tgps_config_T p_tgps_config[FDD_MAX_PENDING_TGPS_NUM]; /* pending tgps config of this tgpsi */
+} FDD_tgps_config_by_tgmp_T;
+
+typedef enum _FDD_tgps_time_relationship_E
+{
+ FDD_TGPS_BEFORE,
+ FDD_TGPS_EQUAL,
+ FDD_TGPS_AFTER
+} FDD_tgps_time_relationship_E;
+
+typedef enum _FDD_tgps_complete_status_E
+{
+ FDD_TGPS_COMPLETE_OR_INACTIVE,
+ FDD_TGPS_NOT_COMPLETE
+} FDD_tgps_complete_status_E;
+
+typedef struct _FDD_tgps_complete_status_by_tgmp_T
+{
+ kal_int16 sfn; /*activation time or TGPS reconfiguration SFN,
+ range: -1-4095, -1 means immediate(only used in current tgps config)*/
+
+ FDD_tgps_complete_status_E tgps_complete_status; /* tgps complete status for that tgpsi*/
+} FDD_tgps_complete_status_by_tgmp_T;
+
+typedef struct _FDD_tgps_status_by_tgmp_T
+{
+ kal_uint8 tgmp_num; /* num of valid tgmp in the structure */
+ FDD_tgmp_E tgmp[FDD_MAX_TGMP_NUM]; /* tgmp queried */
+ kal_bool status[FDD_MAX_TGMP_NUM]; /* TRUE: if there is current or pending active and incompleted tgps for that tgmp */
+} FDD_tgps_status_by_tgmp_T;
+
+
+/* U3G */
+typedef struct _FDD_tgps_info_share_memory_T
+{
+ kal_uint8 tgpsi; /* tgpsi */
+ FDD_tgmp_E tgmp; /* purpose of this tgpsi */
+ FDD_tgps_status_E status; /* tgps status at the activation time*/
+ FDD_tgps_complete_status_E complete_status;
+} FDD_tgps_info_share_memory_T;
+
+typedef struct _FDD_tgps_param_share_memory_T
+{
+ kal_int16 sfn; /* reconfig time of this pending tgps configuration*/
+ kal_uint8 tgps_info_num; /* number of tgps in this pneding tgps */
+ FDD_tgps_info_share_memory_T tgps_info[FDD_MAX_TGPS]; /* tgps config (tgpsi, tgmp, status) */
+} FDD_tgps_param_share_memory_T;
+
+typedef struct _FDD_tgps_status_share_memory_T
+{
+ kal_uint8 tgps_param_num;
+ FDD_tgps_param_share_memory_T tgps_param[FDD_MAX_TGPS];
+} FDD_tgps_status_share_memory_T;
+/* U3G */
+
+/*-------- PhyCH related definition ----------------------*/
+typedef struct _FDD_pich_drx_T
+{
+ kal_uint8 pch_drx; /* DRX cycle length coefficient. 3 ~ 9 */
+ kal_uint8 pi_num; /* # of PI per frame. 18, 36, 72, 144 */
+ kal_uint8 pi; /* Paging Indicator index. */
+ kal_uint16 sfn_po; /* SFN of the frame containing start of PICH for the first paging occasion. */
+} FDD_pich_drx_T;
+
+#ifdef __SMART_PAGING_3G_FDD__
+typedef struct _FDD_pich_smartpaging_T
+{
+ kal_bool support_repeat; /* If true: RRCE has detected that current NW can support smart paging (has repeated paging pattern) */
+ kal_uint16 sfn_po; /* DRX parameters for PICH.(when smartpging active) */
+} FDD_pich_smartpaging_T;
+#endif
+
+typedef enum _FDD_pich_reconfig_type_E
+{
+ FDD_PCH_MODIFY, /* traditionaly PCH modify */
+ FDD_PCH_SMARTPAGE, /* to inform UL1 enable/disable SmartPaging*/
+} FDD_pich_reconfig_type_E;
+
+typedef struct _FDD_pich_info_T
+{
+ kal_bool sttd; /* If STTD is used. */
+ kal_int8 cpich_tx_power; /* CPICH TX power. -10~50 dBm */
+ kal_int8 power_offset; /* PICH power offset to CPICH. -10 ~ 5 dB */
+ kal_uint8 ovsf; /* Channelization code. 0 ~ 255 */
+ FDD_pich_drx_T pich_drx; /* DRX parameters for PICH. */
+#ifdef __SMART_PAGING_3G_FDD__
+ FDD_pich_smartpaging_T smartpaging_info;
+#endif
+#ifdef __UMTS_R7__
+ FDD_pich_drx_T pich_drx_cycle2; /* DRX parameters 2 for PICH. */
+ kal_uint16 drx_cycle2_time; /* if it's not 0. UL1 shall use pich_drx_2 for PICH receptin, else shall directly use pich_drx for PICH reception. 0~5120 ms */
+#endif /* __UMTS_R7__ */
+} FDD_pich_info_T;
+
+typedef struct _FDD_ctch_drx_level1_T
+{
+ kal_uint8 m_tti;
+ kal_uint8 start_off; /* Offset of the start of first block set k. */
+ kal_uint16 repe_period; /* Block set repetition period. */
+ kal_uint16 bmc_sm_period; /*[R6] Period of BMC scheduling message (P)
+ [Value] 1, 8, 16, 32, 64, 128, 256
+ If this value is set to 1, UL1 will receive CTCH in all CTCH allocation.
+ For R5 and R99, or for R6 but this field is not configured by the network, this value should be set to 1 */
+} FDD_ctch_drx_level1_T;
+
+typedef struct _FDD_ctch_drx_level2_T
+{
+// kal_uint8 bs_mask[32];
+// kal_uint16 bs_mask_len; /* 1 ~ 256 */
+ kal_uint8 level2_bitmap[FDD_BMC_MAX_BITMAP_SIZE];
+ kal_uint16 lenOfBitmap;
+ kal_uint8 bitmapOffset;
+ kal_uint16 sfnOfLastScheduleMsg;
+ kal_bool flush_l2;
+} FDD_ctch_drx_level2_T;
+
+typedef union _FDD_ctch_drx_level
+{
+ FDD_ctch_drx_level1_T drx_level1; /* CTCH DRX Level 1 information. */
+ FDD_ctch_drx_level2_T drx_level2; /* CTCH DRX Level 2 information. */
+} FDD_ctch_drx_level;
+
+typedef struct _FDD_ctch_drx_T
+{
+ kal_bool level1_Ind; /* True: CTCH level 1 parameters is used. */
+ FDD_ctch_drx_level ctch_drx_level; /* CTCH DRX level parameters */
+} FDD_ctch_drx_T;
+
+typedef union _FDD_pich_ctch_info_T
+{
+ FDD_ctch_drx_T ctch_drx; /* CTCH DRX information */
+ FDD_pich_info_T pich_info; /* PICH information */
+} FDD_pich_ctch_info_T;
+
+typedef struct _FDD_sccpch_info_T
+{
+ kal_uint8 ssc; /* Secondary scrambling code. 0 ~ 15 */
+ /* This value will not be used, if SCCPCH is used to carrying PCH */
+ /* if the value is equal to 0, it means primary scrambling code is used */
+ kal_bool sttd; /* True if STTD is used */
+ kal_bool pilot_exit; /* If pilot symbol exists */
+ kal_bool tfci_exit; /* If TFCI is used. */
+ kal_bool fixed_pos_ind; /* If Fixed or flexible position is used. True means Fixed */
+ kal_uint16 timing_offset; /* Frame boundary to P-CCPCH. 0 ~ 38144 by step of 256. */
+ kal_uint16 sf; /* Spreading Factor. 4 ~ 256 */
+ kal_uint16 ovsf; /* Channelization code. 0 ~ sf-1 */
+} FDD_sccpch_info_T;
+
+typedef enum _FDD_access_status_E
+{
+ FDD_AI_ACK, /* Network ACK in AICH */
+ FDD_AI_NACK, /* Network NACK in AICH */
+ FDD_AI_NOACK, /* Network no response in AICH*/
+ FDD_AI_ABORT, /* Aborted by higher layer */
+ FDD_AI_PARAMERROR, /* Access request without preliminary Data request */
+ FDD_AI_NESTEDREQUEST /* Access request before previous one finished */
+} FDD_access_status_E;
+
+typedef struct _FDD_aich_info_T
+{
+ kal_int8 power_offset; /* Power offset to CPICH. -22 ~ 5 dB */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 255*/
+ kal_bool sttd; /* Indicate if STTD is used */
+ kal_uint8 tx_timing; /* AICH transmission timie. 0 or 1 */
+} FDD_aich_info_T;
+
+typedef struct _FDD_asc_T
+{
+ kal_uint8 avail_sig_start; /* Available signature start index */
+ kal_uint8 avail_sig_end; /* Available signature end index */
+ kal_uint8 assigned_subchannel; /* Assigned subchannel number */
+ /* Bit0 represent bit b0, only 4 rightmost bit is valid */
+} FDD_asc_T;
+
+typedef struct _FDD_prach_info_T
+{
+ kal_uint16 min_sf; /* Min allowed SF. 32,64,128,256 */
+ kal_uint8 punc_limit; /* Puncturing limit. 40 ~ 100 */
+ kal_uint8 asc_num; /* # of valid ASC information in asc[]. 1 ~ 8 */
+ kal_uint8 pream_psc; /* Preamble scrambling code. 0 ~ 15 */
+ kal_uint16 avail_signature; /* Available signature. Bit string (16) */
+ /* Bit0 represent signature 0 */
+ kal_uint16 avail_subchannel; /* Available subchannels. Bit string (12)*/
+ /* Bit0 represent sub-channel 0 */
+ FDD_asc_T asc[FDD_MAX_ASC]; /* ASC information */
+} FDD_prach_info_T;
+
+typedef struct _FDD_prach_power_T
+{
+ kal_int8 max_tx_power; /* Max allowed TX power. -50 ~ 33dBm */
+ kal_int8 umts_power_class; /* UE capability*/
+ kal_int8 init_power_offset; /* SUM of "P-CPICH TX power" and "constant value" */
+ /* L1 will use this offste - CPICH_RSCP - UL_INTERFERENCE */
+ kal_uint8 power_step; /* Preamble power ramping step. 1 ~ 8dB */
+ kal_uint8 retrans_max; /* Max preamble retrans. 1 ~ 64 */
+} FDD_prach_power_T;
+
+typedef struct _FDD_ul_pc_info_T
+{
+ kal_uint8 pc_pream; /* Power control Preamble. 0 ~ 7 frames */
+ kal_uint8 pc_algo; /* Power control algorithm. 1 or 2; inherited from primary for secondary ul freq */
+ kal_uint8 tpc_step; /* Power control step size. 1 or 2dB */
+ /* This is only valid for pc_algo = 1; inherited from primary for secondary ul freq */
+ kal_int16 dpcch_power_offset; /* DPCCH initial power offset. -164 ~ 6 dBm */
+} FDD_ul_pc_info_T;
+
+typedef enum _FDD_sc_type_E
+{
+ FDD_SC_SHORT, /* Short type scrambling code */
+ FDD_SC_LONG /* Long type scrambling code */
+} FDD_sc_type_E;
+
+typedef struct _FDD_ul_dpch_info_T
+{
+ FDD_ul_pc_info_T ul_pc; /* UL power control info */
+ FDD_sc_type_E sc_type; /* Type of scrambling code */
+ kal_uint32 sc_code; /* Scrambling code #. 0 ~ 16777215 */
+ kal_uint8 ul_dpch_num; /* # of UL DPDCH. 0 ~ FDD_MAX_ULDPCH; ignored by secondary ul freq */
+ kal_uint16 min_sf; /* Min SF. 4,8,16,32,64,128,256; ignored by secondary ul freq */
+ kal_bool tfci_exist; /* Indicate if TFCI exists; inherited from primary for secondary ul freq */
+ kal_uint8 fbi_num; /* # of FBI bits. 0, 1, 2; inherited from primary for secondary ul freq */
+ kal_uint8 punc_limit; /* Puncture limit. 40 ~ 100 in step 4; ignored by secondary ul freq */
+ /* The acture PM = punc_limit/100; ignored by secondary ul freq */
+#ifdef __UMTS_R7__
+ kal_uint8 tpc_bit_num; /* # of TPC bits. 2, 4; inherited from primary for secondary ul freq */
+#endif /* __UMTS_R7__ */
+} FDD_ul_dpch_info_T;
+
+/*-------- TFS related definition ----------------------*/
+typedef enum _FDD_cc_type_T
+{
+ FDD_CC_NONE,
+ FDD_CC_CONV12,
+ FDD_CC_CONV13,
+ FDD_CC_TURBO,
+ FDD_CC_TOTAL
+} FDD_cc_type_T;
+
+typedef struct _FDD_tfs_static_T
+{
+ kal_uint8 tti; /* TTI. # of frames, 1, 2, 4, 8 */
+ FDD_cc_type_T channel_coding; /* Coding type */
+ kal_uint8 rm_attr; /* RM attribute */
+ kal_uint8 crc_size; /* # of CRC bits. 0,8,12,16,24 */
+} FDD_tfs_static_T;
+
+typedef struct _FDD_tfs_dyn_T
+{
+ kal_uint8 tb_num; /* # of TB */
+ kal_uint16 tb_size; /* # of bibts in a TB */
+} FDD_tfs_dyn_T;
+
+typedef struct _FDD_tfs_T
+{
+ kal_uint8 tf_num; /* # of TF in this TFS */
+ FDD_tfs_dyn_T tfs_dynamic[FDD_MAXTF]; /* TFS dynamic part */
+ FDD_tfs_static_T tfs_static; /* TFS static part */
+} FDD_tfs_T;
+
+typedef enum _FDD_tx_diversity_E
+{
+ FDD_DL_TX_NONE = 0, /* No TX diversity */
+ FDD_DL_TX_STTD = 1, /* STTD */
+ FDD_DL_TX_CLM1 = 2, /* Closed loop mode 1 */
+ FDD_DL_TX_CLM2 = 3 /* Closed loop mode 2 */
+
+} FDD_tx_diversity_E;
+
+typedef enum _FDD_cws_len_E
+{
+ FDD_SSDT_LONG, /* Long code word */
+ FDD_SSDT_MEDIUM, /* Medium code word */
+ FDD_SSDT_SHORT, /* Short code word */
+ FDD_SSDT_OFF /* SSDT is off */
+
+} FDD_cws_len_E;
+
+typedef struct _FDD_ssdt_conf_T
+{
+ kal_uint8 s_field; /* # of s bits. 1 or 2 */
+ FDD_cws_len_E cws_len; /* Code word set length */
+} FDD_ssdt_conf_T;
+
+typedef enum _FDD_dpch_type_E
+{
+ FDD_DPCH_TYPE = 0,
+ FDD_FDPCH_TYPE = 1,
+ /* __UMTS_R7__ BEGIN */
+ FDD_NO_DPCH_TYPE
+ /* __UMTS_R7__ END */
+} FDD_dpch_type_E;
+
+typedef struct _FDD_dl_dpch_rla_T
+{
+ kal_uint8 dpc_mode; /* DL Power control mode. 0 or 1 or 2 */
+ kal_uint8 pilot_power_offset; /* Ppilot - Pdpdch. 0 ~ 24dB */ /*[R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint16 sf; /* SF. 4,8,16,32,64,128,256,512 */ /*[R6] For F-DPCH, UL1 doesn't care this value */
+ kal_bool fixed_pos; /* Fixed or flexible position. True = Fixed */ /*[R6] For F-DPCH, UL1 doesn't care this value */
+ kal_bool tfci_exist; /* Indicate if TFCI exist */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint8 pilot_num; /* # of pilot bits. 2,4,8,16 */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint8 tgps_num; /* # of TGPS in the list. 0 ~ 6 */
+ FDD_tgps_info_T tgps_info[FDD_MAX_TGPS]; /* TGPS list */
+ FDD_tx_diversity_E tx_diversity; /* TX diversity mode */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ FDD_ssdt_conf_T ssdt_conf; /* SSDT configuration */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_int32 doff; /* Default DPCH offset value. -1 ~ 306688 */
+ /* -1 is an invalid value */
+
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rl */
+ kal_uint8 tpc_target; /* [R6] F-DPCH only, range: 1~10, the actual TPC command error rate target is tpc_target/100 */
+} FDD_dl_dpch_rla_T;
+
+typedef struct _FDD_dldpch_code_T
+{
+ kal_uint8 ssc; /* Scrambling code # for this code channel */
+ /* 0 ~ 15. 0 for "the same scrambling code for the P-CPICH */
+ kal_uint16 sf; /* 4,8,16,32,64,128,256,512 */
+ kal_uint16 ovsf; /* OVSF code. 0 ~ SF-1 */
+ kal_bool sc_change; /* True : Changed scrambling code is used */
+} FDD_dldpch_code_T;
+
+typedef struct _FDD_dl_dpch_rl_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */
+ /* If the value of tm is not equal to -1, UL1 will use this value */
+ /* If the value of tm is equal to -1, UL1 will not use this value */
+ kal_int32 tm; /* Cell boundary to LST. -1 ~ 38400*8-1 */
+ kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell */
+ kal_bool pcpich_usage; /* Indicate if P-CPICH can be used for channel estimation */
+ /* KAL_TRUE means P-CPICH could be used */
+ kal_int8 scpich_ssc; /* Scrambling code of S-CPICH. */
+ /* -1 ~ 15. 0 means use primary scramblign code */
+ /* -1 means there is not S-CPICH */
+ kal_uint8 scpich_ovsf; /* OVSF code. 0 ~ 255 */
+ kal_bool tx_diversity_disable; /* Indicate if TX diversity is used */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ /* True means TX diversity is disabled. */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ kal_uint8 closedlooptimingadj_mode; /* 0 : CLTD timing adjust mode 0 */ /* [R6] For F-DPCH, UL1 doesn't care this value */
+ /* 1 : CLTD timing adjust mode 1 */
+ kal_uint8 ssdt_id; /* 0 ~ 8. 1 for 'A'. 8 for not applicable*/
+ kal_uint8 tpc_index; /* TPC combination index. 0 ~ 5 */
+ kal_int8 tpc_power_offset; /* Power offset between TPC and DPDCH,-1 means INVALID, range 0~24 dB (actual 0:0.25:6) [R5 only] */
+ /* [R6] For F-DPCH, UL1 doesn't care this value */
+
+ /* [R6] F-DPCH: dl_dpch_num must be 1 and the index of the F-DPCH info must be 0 in dl_dpch_info list */
+ kal_uint8 dl_dpch_num; /* # of DPDCH on the RL */
+ FDD_dldpch_code_T dl_dpch_info[FDD_MAX_DLDPCH]; /* Information for each code channel */
+
+ FDD_dpch_type_E dpch_type; /* [R6] DPCH or F-DPCH, for R5 and previous version, this value should be FDD_DPCH_TYPE */
+ /* This value should be consistent with the dpch_type field in dl_dpch_rla */
+ kal_uint8 fdpch_slot_format; /* [R7] F-DPCH only, range: 0~9. For R6 and previous version, this value should be 0 */
+ kal_bool fdpch_sttd_ind; /* [R6] F-DPCH only, TRUE when STTD is used. FALSE, otherwise */
+
+ kal_bool hsdsch_serving_rl_ind; /* [R5] The value "TRUE" indicates that this radio link is the serving HS-DSCH radio link. FALSE, otherwise */
+ kal_bool edch_serving_rl_ind; /* [R6] The value "TRUE" indicates that this radio link is the serving E-DCH radio link. FALSE, otherwise */
+ kal_bool sttd_valid; /* To judge if sttd value can be used by UL1 when doing SCS */
+} FDD_dl_dpch_rl_T;
+
+typedef struct _FDD_dl_establish_T
+{
+ kal_uint8 t312; /* T312 */
+ kal_uint16 n312; /* N312 */
+ kal_uint8 n313; /* N313 */
+ kal_uint8 t313; /* T313 */
+ kal_uint16 n315; /* N315 */
+} FDD_dl_establish_T;
+
+#ifdef __UMTS_R7__
+/* [R7] Determine whether UL1 need to store HS-SCCH order when release DCH channel */
+typedef enum _FDD_dpch_release_type_E
+{
+ FDD_DCH_RELEASE = 0, /* Don't need to store HS-SCCH order */
+ FDD_DCH_TRHHO_RELEASE, /* Need to store HS-SCCH order */
+ FDD_DCH_TRHHO_REVERT_RELEASE, /* Don't need to store HS-SCCH order */
+ FDD_DCH_TMHHO_RELEASE, /* Need to store HS-SCCH order */
+ FDD_DCH_TMHHO_REVERT_RELEASE, /* Don't need to store HS-SCCH order */
+ FDD_DCH_IRAT_RELEASE, /* Need to store HS-SCCH order */
+ FDD_DCH_ALL_RL_TIMING_MODIFY_RELEASE /* Need to store HS-SCCH order */
+} FDD_dpch_release_type_E;
+#endif /* __UMTS_R7__ */
+
+/*-------- TFCS related definition ----------------------*/
+typedef struct _FDD_sig_gain_T
+{
+ kal_uint8 beta_c; /* Bc. 0 ~ 15 */
+ kal_uint8 beta_d; /* Bd. 0 ~ 15 */
+ kal_int8 ref_tfc_id; /* Reference TFC ID. -1 ~ 3. */
+ /* 0 ~ 3 : This TFCI is a referenced id for other computed TFC. */
+ /* -1 : It is an invalid value. Means it will not be referenced by other TFC. */
+} FDD_sig_gain_T;
+
+typedef union _FDD_gain_factor
+{
+ kal_int8 computed_gain_id; /* For computed gain factor using reference TFC id. 0 ~ 3 */
+ FDD_sig_gain_T sig_gain; /* The signaled gain factor. */
+} FDD_gain_factor;
+
+typedef struct _FDD_ul_dpch_tfc_T
+{
+ kal_uint8 tfi_list[FDD_MAX_TRCH_NUM]; /* The list of TFI for this TFCI for UL DCH TrCH */
+ kal_bool sig_gain_ind; /* True: Gain factor is siganled. False: Gain factor is computed from reference TFCI */
+ FDD_gain_factor gain_factor; /* Gain factor */
+} FDD_ul_dpch_tfc_T, FDD_ul_tfc_T;
+//} FDD_ul_dpch_tfc_T;
+
+typedef struct _FDD_rach_tfc_T
+{
+ kal_uint8 tfi_list; /* The list of TFI for this TFCI. The number of TrCH for PRACH is 1. */
+ kal_bool sig_gain_ind; /* True: Gain factor is siganled. False: Gain factor is computed from reference TFCI */
+ kal_int8 msg_pwr_offset; /* Power offset between the last preamble and the control part of RACH */
+ FDD_gain_factor gain_factor; /* Gain factor */
+} FDD_ul_rach_tfc_T;
+
+typedef struct _FDD_dl_tfc_T
+{
+ kal_uint8 tfi_list[FDD_MAX_TRCH_NUM]; /* The list of TFI for this TFCI for DL TrCH */
+} FDD_dl_tfc_T;
+
+/*-------- TrCH related definition ----------------------*/
+
+#if 0 //Modify by Anthony Chin, for UL1D's convenience to maintain DB
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+typedef struct _FDD_trch_T
+{
+ kal_uint8 trch_id; /* TrCH ID 1 ~ 32 */
+ kal_uint8 bit_offset; /* Bit offset. 0 ~ 7 */
+ FDD_tfs_T tfs; /* TFS of this TrCH */
+ kal_int8 target_bler; /* Diving the value of this field to 10 get the real BLER. -63 ~ 0 */
+} FDD_trch_T,
+FDD_ul_rach_trch_T,
+FDD_ul_dch_trch_T,
+FDD_dl_fachpch_trch_T,
+FDD_dl_dch_trch_T;
+#endif
+
+/*-------- CCTrCH related definition ----------------------*/
+typedef enum _FDD_cctrch_type_E
+{
+ FDD_CCTRCH_UL_RACH, /* UL RACH CCTrCH */
+ FDD_CCTRCH_UL_DCH, /* UL DCH CCTrCH */
+ FDD_CCTRCH_DL_DCH, /* DL DCH CCTrCH */
+ FDD_CCTRCH_DL_PCH, /* DL PCH CCTrCH */
+ FDD_CCTRCH_DL_FACH, /* DL FACH CCTrCH */
+ FDD_CCTRCH_DL_BCH, /* DL BCH CCTrCH */
+ FDD_CCTRCH_DL_FDPCH, /* DL FDPCH, only for UL1 use */
+ /* __UMTS_R7__ BEGIN */
+ FDD_CCTRCH_DL_EPCH, /* DL EPCH CCTrCH */
+ /* __UMTS_R7__ END */
+ /* __UMTS_R8__ BEGIN */
+ FDD_CCTRCH_UL_EDCH /* UL EDCH CCTrCH */
+ /* __UMTS_R8__ END */
+} FDD_cctrch_type_E;
+
+typedef struct _FDD_FACH_PCH_Info_T
+{
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */
+ /* If the value of tm is not equal to -1, UL1 will use this value */
+ /* If the value of tm is equal to -1, UL1 will not use this value */
+ kal_int16 rscp; /* Serving cell RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
+ FDD_sccpch_info_T sccpch_info; /* Physical channel for PCH/FACH to be carried over */
+ kal_bool sccpch_optimization; /* True if FACH and PCH use the same S-CCPCH. valid only for configuring CTCH */
+ kal_uint16 tfc_num; /* # of TFC in TFCS */
+ FDD_dl_tfc_T tfcs[FDD_MAX_DL_TFC]; /* TFCS */
+ kal_uint8 active_dl_trch_list; /* Active TrCHs by bit string. MSB is the lowest numbered TrCH ID */
+ kal_uint8 trch_num; /* # of TrCHs carried on this CCTrCH */
+ FDD_dl_fachpch_trch_T trch_list[FDD_MAXFACHPCH]; /* List of TrCHs carried on this CCTrCH */
+ kal_bool pich_ctch_valid; /* True means "pich_ctch_info" is valid. */
+ FDD_pich_ctch_info_T pich_ctch_info; /* PICH or CTCH information */
+} FDD_FACH_PCH_Info_T;
+
+/*-------- BCH related definition ----------------------*/
+typedef struct _FDD_sib_info_T
+{
+ kal_uint8 seg_count; /* SEG_COUNT 1 ~ 16 */
+ kal_uint16 sib_rep; /* SIB_REP 2^2 ~ 2^12 */
+ kal_uint16 sib_pos; /* SIB_POS 0 ~ sib_rep-2 */
+ kal_uint8 sib_off[FDD_MAX_SIB_SEG_COUNT]; /* SIB_OFF 2 ~ 32 The # of elements of this field is equal to seg_count-1 */
+} FDD_sib_info_T;
+
+typedef enum _FDD_bch_priority_E
+{
+ FDD_BCH_PRIOHIGH, /* Priority High */
+ FDD_BCH_PRIOMEDIUM, /* Priority Medium */
+ FDD_BCH_PRIOLOW, /* Priority Low */
+ FDD_BCH_PRIORR, /* Priority for SIB round robin */
+} FDD_bch_priority_E;
+
+/*------- PHY_POST_TX_IND related ---------*/
+typedef struct _FDD_tPhyPostTxMemInfo
+{
+ kal_uint8 RbId;
+ kal_uint8 *pContainer;
+} FDD_tPhyPostTxMemInfo;
+
+typedef struct _FDD_tPhyPostTxElement
+{
+ kal_uint8 Num;
+ FDD_tPhyPostTxMemInfo TxMemInfo[FDD_MAX_UL_TB];
+#if defined(__GEMINI__) && defined(__UMTS_RAT__)
+ kal_bool is_tx_suspend; /* This flag is only used for ULDCH when Gemini2.0. For RACH, this flag is always false.
+ It indicates if there is SIM2 gap in the minTTI period of the released ul data, and UL1D will set this flag. */
+ kal_uint8 cfn; /* This value is only used for ULDCH when Gemini2.0.
+ It indicates the cfn value that UL1C gets the ul data from UMAC. */
+#endif
+} FDD_tPhyPostTxElement;
+
+typedef enum _FDD_tPhyPostTxType
+{
+ FDD_POST_TX_RACH,
+ FDD_POST_TX_DCH
+} FDD_tPhyPostTxType;
+
+/*-------- Data related definition ----------------------*/
+typedef struct _FDD_dlTrchData
+{
+ kal_bool valid_fpch; /* Raymond,20070327 Eric/Anthony add this, already notify UMAC */
+ kal_bool is_dual_TF; /* Andrew/Sean: For MAC to identify BTFD_DUAL_TF TrCh */
+ kal_int8 crc_status; /* Jay: For DUAL-TF TrCH power control*/
+ kal_uint8 trchId; /* TrCH ID */
+ kal_uint16 tb_size; /* TB size in bit. 0 ~ 4992 */
+ kal_uint16 num_tb; /* # of TB. 0 ~ 512 */
+ kal_uint16 addi_crc_size; /*Indicate additional crc size for MT6290E1 RXBRP DOB issue workaround*/
+ kal_bool is_hw_out_extra; /*L1 internal: Indicate whether HW output extra bytes for MT6290E1 RXBRP DOB issue workaround*/
+} FDD_dlTrchData;
+
+typedef struct _FDD_ulTrchData
+{
+ kal_uint8 trchId; /* TrCH ID */
+ kal_uint16 tb_size; /* TB size in bit. 0 ~ 4992 */
+ kal_uint16 num_tb; /* # of TB. 0 ~ 512 */
+} FDD_ulTrchData;
+
+/*-------- Measurement related definition ----------------------*/
+typedef struct _FDD_preferred_cell_list_T
+{
+ kal_uint8 uarfcn_index; /* Frequency index */
+ /* Freq. array is contained in Frequency scan message */
+ kal_uint16 psc; /* Primary Scrambling code */
+} FDD_preferred_cell_list_T;
+
+typedef enum _FDD_measured_type_E
+{
+ FDD_INTRA_FREQENCY_MEASURED,
+ FDD_INTER_FREQENCY_MEASURED,
+ FDD_FREQ_SCAN_DETECTED,
+ FDD_INTRA_SEC_FREQENCY_MEASURED /* [R9]Secondary intra-freq measurement */
+} FDD_measured_type_E;
+
+
+typedef enum _FDD_cell_type_E
+{
+ FDD_MONITORED,
+ FDD_DETECTED,
+ FDD_SPECIFIC_CELL_SEARCH,
+ FDD_MONITORED_CELL_FOUND,
+ FDD_DETECTED_CELL_FOUND
+} FDD_cell_type_E;
+
+typedef enum _FDD_meas_status_E
+{
+ FDD_MS_INCLUDED,
+ FDD_MS_NOTINCLUDED
+} FDD_meas_status_E;
+
+typedef enum _FDD_meas_tm_off_type_E
+{
+ FDD_TM_OFF_RST,
+ FDD_TM_OFF_DCH,
+ FDD_TM_OFF_COMMON,
+ FDD_TM_OFF_NA
+} FDD_meas_tm_off_type_E;
+
+typedef struct _FDD_measured_cell_T
+{
+ kal_bool sttd; /* Indicate if STTD is used */
+ kal_int16 ec_no; /* Ec/No. Range: -100~0 means (-25~0) dB in 0.25 dB step */
+ kal_int16 rscp; /* RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_uint16 freq; /* DL UARFCN */
+ FDD_meas_tm_off_type_E tm_off_type; /*Indicate which field is applicable in this report*/
+ kal_int16 sfn; /* SFN in BCH. -1 ~ 4095 : -1 means unknown SFN */
+ kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */
+ kal_int32 tm; /* Cell boundary. -1 ~ 38400*8-1 : -1 means unknown timing*/
+ kal_uint32 meas_sfn_diff; /* SFN_SFN difference in chips*/
+ FDD_meas_status_E meas_status; /* Indicate whether this cell is measured in this time */
+ FDD_cell_type_E cell_type; /* AS, MS or DS cell */
+ kal_bool update_timing; /* Indicates if it is recommended by UL1 for MEME to update cell timing based on FS result */
+} FDD_measured_cell_T;
+
+typedef enum _FDD_meas_type_E
+{
+ FDD_MT_INTRA_FREQ, /* Intra-frequency measurement */
+ FDD_MT_INTER_FREQ, /* Inter-frequency measurement */
+ FDD_MT_GSM_RAT /* GSM-RAT measurement */
+} FDD_meas_type_E;
+
+typedef enum _FDD_sfn_priority_E
+{
+ FDD_SFN_HIGH,
+ FDD_SFN_MEDIUM,
+ FDD_SFN_LOW,
+ FDD_SFN_OFF
+} FDD_sfn_priority_E;
+
+typedef struct _FDD_meas_spec_T
+{
+ kal_bool ds_meas_intra; /* Indicate if measure on intra-freq (and R9 secondary intra-freq) detected set*/
+ kal_bool ds_sfn_intra; /* Indicate if reading SFN of detected set */
+#ifdef __UMTS_R10__
+ kal_bool ds_meas_inter; /* Indicate if measure on inter-freq detected set*/
+#endif
+ kal_int8 nc_nbr_dch; /* # of best cells to read SFN in DCH. -1 ~ 32
+ -1 means L1 should not read SFN for any cell
+ 0 means L1 should read SFN for cells which have stronger CPICH measurement
+ Other values means L1 should read FN for nc_nbr_dch cells from active set, monitored set and detected set.
+ */
+ FDD_sfn_priority_E serving_prio; /* The priority of reading SFN of cells in active set.
+ Only used when L1 is in DCH state and nc_nbr_dch > 0 */
+ FDD_sfn_priority_E monitor_prio; /* The priority of reading SFN of cells in monitored set.
+ Only used when L1 is in DCH state and nc_nbr_dch > 0 */
+ FDD_sfn_priority_E detect_prio; /* The priority of reading SFN of cells in detected set.
+ Only used when L1 is in DCH state and nc_nbr_dch > 0 */
+ kal_uint8 nc_nbr_rach; /* # of best cells to read SFN in non-DCH state. 0 ~ 32 */
+} FDD_meas_spec_T;
+
+#ifdef __UMTS_R8__
+typedef enum _FDD_higher_prio_search_support_E /* [Rel8][Absolute Priority Search] absolute priority search type */
+{
+ FDD_REGULAR_MEAS_ONLY,
+ FDD_HIGHER_PRIORITY_ONLY,
+ FDD_HIGHER_PRIORITY_AND_REGULAR_MEAS
+} FDD_higher_prio_search_support_E;
+#endif
+
+typedef struct _FDD_cell_info_list_T
+{
+ kal_uint8 freq_index; /* UARFCN index */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_bool sttd; /* Indicate if STTD is used */
+ kal_bool read_sfn_ind; /* Indicate if read SFN */
+ kal_int16 ref_timing; /* Cell boundary. -1 ~ 38400-1 : -1 means unknown timing*/
+ kal_bool ref_timing_sib; /* Indicate if the reference timing comes from SIB or Meas. Control */
+ kal_int32 tm; /* Cell boundary. -1 ~ 38400*8-1 : -1 means unknown timing*/
+ kal_int16 off; /* FN offset. -1 ~ 4095 : -1 means unknown timing */
+#ifdef __UMTS_R8__
+ FDD_higher_prio_search_support_E prio_search_control; /* [Rel8] Higher priority search control */
+#endif
+} FDD_cell_info_list_T;
+
+typedef enum _FDD_event_cond_E
+{
+ FDD_COND_ABOVE, /* Above threshold */
+ FDD_COND_ABOVE_EQUAL, /* Above or equal to threshold */
+ FDD_COND_BELOW, /* Below threshold */
+ FDD_COND_BELOW_EQUAL, /* Below or equal to threshold */
+ FDD_COND_EVENT_6C, /* [R6] Reporting event 6C: The UE Tx power reaches its minimum value */
+ FDD_COND_EVENT_6D /* [R6] Reporting event 6D: The UE Tx power reaches its maximum value */
+} FDD_event_cond_E;
+
+typedef struct _FDD_meas_event_T
+{
+ kal_uint8 event_id; /* Measurement event ID */
+ kal_uint8 measurement_id; /* Measurement ID */
+ kal_int16 threshold;
+ kal_uint16 delay; /* Time to Triggered. 0 ~ 500 frames */
+ FDD_event_cond_E condition; /* Event triggered condition */
+} FDD_meas_event_T;
+
+typedef struct _FDD_rl_meas_result_T
+{
+ kal_uint8 rl_status; /* RL status */
+ /* 0 : Not detected */
+ /* 1 : Detected not used */
+ /* 2 : Detected and demodulated */
+ kal_uint16 psc; /* Scrambling code of this RL */
+ kal_uint32 time_diff; /* RX-TX Timd diff. 0 ~ 38400*8-1 */
+} FDD_rl_meas_result_T;
+
+typedef enum _FDD_meas_act_E
+{
+ FDD_MEAS_UNCHANGE, /* Unchange a cell list */
+#ifndef __MTK_UL1_FDD__ /* 20080305: For Venus, still use old I/F */
+ FDD_MEAS_MODIFY, /* Modify an existed cell list */
+#endif
+ FDD_MEAS_DELETE, /* Delete an existed cell list */
+ FDD_MEAS_UPDATE /* Update the configuration of an existed cell list */
+} FDD_meas_act_E;
+
+typedef enum _FDD_triggering_cause_E
+{
+ FDD_REGULAR_REPORT,
+ FDD_ONE_SHOT_MEASUREMENT,
+ FDD_T_RESELECTION_EXPIRY
+} FDD_triggering_cause_E;
+
+typedef enum
+{
+ FDD_CPHY_MEAS_STOP_CAUSE_NONE, /* none: fill when none stop */
+ FDD_CPHY_MEAS_STOP_CAUSE_REGULAR, /* normal stop */
+ FDD_CPHY_MEAS_STOP_CAUSE_4G3IRHO /* stop triggered by 4G3 IRHO */
+} FDD_CPHY_MEASUREMENT_STOP_CAUSE_E;
+
+typedef struct _FDD_supplementary_meas_parameter_T
+{
+ kal_bool intra_meas_one_shot_ind; /* When intra-F cell list is updated,to notify if UL1 needs to do one-shot measurement on intra-F or not */
+ kal_bool inter_meas_one_shot_ind; /* When inter-F cell list is updated,to notify if UL1 needs to do one-shot measurement on inter-F or not */
+} FDD_supplementary_meas_parameter_T;
+
+typedef struct _FDD_supplementary_report_info_T
+{
+ FDD_triggering_cause_E triggering_cause; /* The triggering cause of this meas tick */
+ kal_bool evaluate_req; /* To notify if L3 need to trigger cell evaluattion */
+#ifdef __UMTS_R7__
+ kal_bool is_cycle2; /* Indicate whether the current DRX is cycle2 or not */
+#endif /* __UMTS_R7__ */
+} FDD_supplementary_report_info_T;
+
+/*-------- FACH MO related definition ----------------------*/
+typedef struct _FDD_fach_mo_info_T
+{
+ kal_uint8 n; /* # of frames in max TTI. 1,2,4,8 */
+ kal_uint8 k; /* MO cycle length coefficient. M_REP=2^k */
+ kal_bool inter_freq_ind; /* Indicate if inter-frequency meas in MO */
+ kal_bool inter_rat_ind; /* Indicate if inter-RAT meas in MO */
+ kal_bool inter_freq_cell_exist; /* Indicate if inter-freq cell in BA lsit is existed */
+ kal_bool inter_rat_cell_exist; /* Indicate if inter-rat cell in BA list is existed */
+ kal_uint16 start_off; /* C_RNTI % M_REP. 0 ~ 4095 */
+} FDD_fach_mo_info_T;
+
+/*-------- Operation-Mode related definition ----------------------*/
+typedef enum _FDD_mode_type_E
+{
+ FDD_OM_SINGLE, /* Single Mode */
+ FDD_OM_MULTI /* Dual Mode */
+} FDD_mode_type_E;
+
+typedef enum _FDD_rat_type_E
+{
+ FDD_UL1_RAT_UMTS_ACTIVE, /* UMTS_Active */
+ FDD_UL1_RAT_UMTS_INACTIVE /* UMTS_Inactive */
+} FDD_rat_type_E;
+
+typedef struct _FDD_duplex_mode_info_T
+{
+ umts_duplex_mode_type source_umts_duplex_mode;
+ umts_duplex_mode_type target_umts_duplex_mode;
+ lte_duplex_mode_type source_lte_duplex_mode;
+ lte_duplex_mode_type target_lte_duplex_mode;
+} FDD_duplex_mode_info_T;
+
+/*-------- Message(Primitive) related definition ----------------------*/
+typedef enum _FDD_dch_setup_msg_type_E
+{
+ FDD_DCH_SETUP, /* Used when DCH is established first time */
+ FDD_DCH_TRHHO, /* Used when timing reinitialized hard hand over */
+ FDD_DCH_TRHHO_REVERT, /* Used when timing reinitialized HHO revert */
+ FDD_DCH_TMHHO, /* Used when timing maintained hard hand over */
+ FDD_DCH_TMHHO_REVERT, /* Used when timing maintained HHO revert */
+ FDD_DCH_IRAT_REVERT, /* Used when Inter-RAT HHO revert */
+ FDD_DCH_ALL_RL_TIMING_MODIFY /* Used when all dpch rl timing offset is modified.*/
+} FDD_dch_setup_msg_type_E;
+
+
+typedef enum _FDD_dch_modify_msg_type_E
+{
+ FDD_DCH_RECONFIG, /* Used when DCH is reconfigured */
+ FDD_DCH_ASU, /* Used when active set update */
+ FDD_DCH_LOOP_MODE_2 /* Used when DCH loop back mode 2 */
+} FDD_dch_modify_msg_type_E;
+
+
+typedef enum _FDD_msg_container_error_E /* Error cause of message container, MA only*/
+{
+ FDD_NONE,
+ FDD_DCH_SETUP_FAIL
+} FDD_msg_container_error_E;
+
+typedef enum _FDD_TGPS_Action_E
+{
+ FDD_TGPS_ACT_START,
+ FDD_TGPS_ACT_STOP,
+ FDD_TGPS_ACT_SUSPEND,
+ FDD_TGPS_ACT_RESUME,
+ FDD_TGPS_ACT_CONTINUE,
+ FDD_TGPS_ACT_DELETE
+} FDD_TGPS_Action_E;
+
+typedef struct _FDD_TGPS_Action_T
+{
+ kal_uint8 tgpsi; /* TGPIS of the TGPS on which the action and apply flag should be applied */
+ kal_bool apply_current;
+ kal_bool apply_suspend;
+ FDD_TGPS_Action_E action;
+} FDD_TGPS_Action_T;
+
+typedef enum _FDD_meas_control_E
+{
+ FDD_MEAS_CTRL_INVALID, /* No meas. control action in current MSG_CONTAINER */
+ FDD_MEAS_CM_STOP, /* For inter-RAT HHO, stop CM measurement when receiving DCH release msg */
+ FDD_MAX_MEAS_CONTROL = FDD_MEAS_CM_STOP
+} FDD_meas_control_E;
+
+/*Add for improving full band FS efficiency -- by excluding some UARFCN or some frequency range*/
+typedef enum _FDD_full_band_option_E
+{
+ FDD_FULL_BAND_ONLY, /*Normal full band FS*/
+ FDD_FULL_BAND_AND_EXCLUDE /*Full band FS but the indicated frequency list/range will be excluded in the full band FS procedure*/
+} FDD_full_band_option_E;
+#if defined( __GEMINI__ ) && defined ( __UMTS_RAT__ )
+typedef enum _FDD_uas_gemini_conflict_cause_enum
+{
+ FDD_URR_NO_CONFLICT,
+ FDD_URR_CONFLICT_WITH_GSM_BCCH,
+ FDD_URR_CONFLICT_WITH_GSM_NBCCH,
+ FDD_URR_CONFLICT_WITH_GSM_PCH,
+ FDD_URR_CONFLICT_WITH_GSM_OTHERS,
+ FDD_URR_CONFLICT_WITH_WCDMA_BCH_HIGH,
+ FDD_URR_CONFLICT_WITH_WCDMA_BCH_LOW,
+ FDD_URR_CONFLICT_WITH_WCDMA_PICH,
+ FDD_URR_CONFLICT_WITH_WCDMA_OTHERS,
+ FDD_URR_CONFLICT_WITH_LTE_BCCH,
+ FDD_URR_CONFLICT_WITH_LTE_NBCCH_HIGH,
+ FDD_URR_CONFLICT_WITH_LTE_NBCCH_MIDDLE,
+ FDD_URR_CONFLICT_WITH_LTE_NBCCH_LOW,
+ FDD_URR_CONFLICT_WITH_LTE_PCH,
+ FDD_URR_CONFLICT_WITH_LTE_OTHERS
+} FDD_uas_gemini_conflict_cause_enum;
+
+#ifdef __MODIFY_CTCH_RECEPTION_PRIO__
+typedef enum _FDD_rrce_gemini_priority_adjust_E
+{
+ FDD_GEMINI_PRIORITY_ADJUST_ALL_NORMAL, /* Currently only used in Gemini2.0, to raise all rx/tx/BCH channel priority for RRC connection establishment or DL sync procedure. */
+ FDD_GEMINI_PRIORITY_ADJUST_ALL_HIGH,
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH_NORMAL,
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH_IMPRV, /* Added as a part of CBS improvement, to raise one SIM CTCH priority over other SIM CTCH*/
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH_ETWS /* R8 ETWS feature, used for receiving ETWS CB. */
+} FDD_rrce_gemini_priority_adjust_E;
+#else
+typedef enum _FDD_rrce_gemini_priority_adjust_E
+{
+ FDD_GEMINI_PRIORITY_ADJUST_ALL, /* Currently only used in Gemini2.0, to raise all rx/tx/BCH channel priority for RRC connection establishment or DL sync procedure. */
+ FDD_GEMINI_PRIORITY_ADJUST_CTCH /* R8 ETWS feature, used for receiving ETWS CB. */
+} FDD_rrce_gemini_priority_adjust_E;
+#endif
+
+#endif
+/*-------- [R5R6] HS-DSCH related ----------------------*/
+typedef enum _FDD_hs_cqi_k_E
+{
+ FDD_CQI_K_0,
+ FDD_CQI_K_2,
+ FDD_CQI_K_4,
+ FDD_CQI_K_8,
+ FDD_CQI_K_10,
+ FDD_CQI_K_20,
+ FDD_CQI_K_40,
+ FDD_CQI_K_80,
+ FDD_CQI_K_160,
+ /* __UMTS_R7__ BEGIN */
+ FDD_CQI_K_16,
+ FDD_CQI_K_32,
+ FDD_CQI_K_64
+ /* __UMTS_R7__ END */
+} FDD_hs_cqi_k_E;
+
+#ifdef __UMTS_R7__
+/* [R7] FDD_UE_OWN_CATEGORY or FDD_CATEGORY_12. According to 25.331 CR#4159, UE should use the number of soft channel bits
+ according to this category to decode HS-PDSCH TB. */
+typedef enum _FDD_hs_harq_ir_type_E
+{
+ FDD_UE_OWN_CATEGORY = 0,
+ FDD_CATEGORY_12
+} FDD_hs_harq_ir_type_E;
+
+typedef enum
+{
+ FDD_E_SCELL_PRI = 0,
+ FDD_E_SCELL_SEC,
+ FDD_E_SCELL_TOTAL, /* 0:primary, 1: secondary */
+ FDD_E_SCELL_BOTH = FDD_E_SCELL_TOTAL,
+} FDD_edch_scell_E;
+
+typedef struct _FDD_hs_tb_size_list_T
+{
+ kal_int8 tbs_index; /* [Range] 1~90, -1 if this is invalid */
+ kal_bool second_code_support; /* Indicates whether the second HS-PDSCH code is used for this TB size.
+ If TRUE, the HS-PDSCH second code index value is the value of IE 'HSPDSCH Code Index' incremented by 1. */
+} FDD_hs_tb_size_list_T;
+
+/* [R7] MAC entity types for handling HS-DSCH */
+typedef enum _FDD_hs_mac_entity_type_E
+{
+ FDD_HS_MAC_HS_ENTITY = 0,
+ FDD_HS_MAC_EHS_ENTITY,
+ FDD_HS_MAC_EHS_ENTITY_DC
+} FDD_hs_mac_entity_type_E;
+#endif /* __UMTS_R7__ */
+
+typedef struct _FDD_hs_scch_info_T
+{
+ kal_uint8 ssc; /* DL scrambling code to be applied for HS-DSCH and HS-SCCH */
+ kal_uint8 ovsf_code_num; /* Number of HS-SCCH to be received. Range:1~4 */
+ kal_uint8 ovsf[FDD_MAX_HS_SCCH_NUM]; /* OVSF code of HS-SCCH to be received */
+} FDD_hs_scch_info_T;
+
+typedef struct _FDD_hs_meas_fb_info_T
+{
+ kal_int8 meas_po; /* Measurement power offset. Range: -12~26 */
+ FDD_hs_cqi_k_E cqi_k; /* Measurement feedback cycle */
+ kal_uint8 cqi_repe_factor; /* CQI repetition factor. Range: 1~4 */
+ kal_uint8 delta_cqi; /* DeltaCQI. Range: 0~8 */
+} FDD_hs_meas_fb_info_T;
+
+typedef struct _FDD_hs_harq_info_T
+{
+ kal_uint8 process_num; /* Number of HARQ process. Range: 1~8 */
+ kal_bool explicit_partition; /* TRUE indicates explicit memory partition. FALSE indicates implicit memory partition */
+ kal_uint8 process_mem_size[FDD_MAX_HS_PROCESS_NUM]; /* index of HARQ memory size. range: 0~60, only valid when memory partition is explicit */
+#ifdef __UMTS_R7__
+ FDD_hs_harq_ir_type_E harq_ir_type; /* FDD_UE_OWN_CATEGORY or FDD_CATEGORY_12. According to 25.331 CR#4159, UE should use the number of soft channel bits
+ according to this category to decode HS-PDSCH TB. */
+ FDD_hs_mac_entity_type_E hs_mac_entity; /* enum for MAC-hs, MAC-ehs and MAC-ehs with DC */
+#endif /* __UMTS_R7__ */
+} FDD_hs_harq_info_T;
+
+typedef struct _FDD_hs_ulpc_info_T
+{
+ kal_uint8 delta_ack; /* delta_ack. range: 0~8 */
+ kal_uint8 delta_nack; /* delta_nack. range: 0~8 */
+ kal_uint8 acknack_repe_factor; /* ack_nack_repetition_factor. range: 1~4 */
+ kal_uint8 harq_preamble_mode; /* [R6] range: 0~1, 1: indicates the preamble and postable are used
+ for R5 and previous version, this value should be 0 */
+} FDD_hs_ulpc_info_T;
+
+typedef enum
+{
+ FDD_DSCH_NO_HRNTI_DETECTED = 0, /*HS-SCCH CRC check is failed*/
+ FDD_DSCH_D_HRNTI_DETECTED = 1, /*HS-PDSCH is indicated by HS-SCCH with dH-RNTI*/
+ FDD_DSCH_C_HRNTI_DETECTED = 2, /*HS-PDSCH is indicated by HS-SCCH with cH-RNTI*/
+ FDD_DSCH_B_HRNTI_DETECTED = 3, /*HS-PDSCH is indicated by HS-SCCH with bH-RNTI*/
+ FDD_DSCH_HRNTI_LESS = 4, /*HS-PDSCH is decoded blindly without HS-SCCH */
+ FDD_DSCH_NOT_RECEIVE = 5, /*This subframe is not received by HW */
+
+} FDD_hs_dsch_decode_hrnti_E;
+
+typedef struct _FDD_hsdsch_data_T
+{
+ kal_uint16 tb_size; /*[Range]: 137 ~ 27952 bits, MAC-hs PDU size */
+ kal_uint8 *p_data; /* The buffer contains MAC-hs data */
+ kal_uint8 *p_data_head; /* The address of the HDA buffer allocated by UMAC */
+ FDD_hs_dsch_decode_hrnti_E decode_hrnti; /*H-RNTI dectected info*/
+ kal_int8 pi_repeat_cycle; /* -1:invalid, -2:retransmission with CRC pass, 1~20:valid pi_repeat_cyle */
+
+ kal_uint8 decode_counter; /* For EM in UMAC */
+} FDD_hsdsch_data_T;
+
+#ifdef __UMTS_R7__
+typedef enum _FDD_mac_ehs_reset_cause_E
+{
+ FDD_Treset_Expired
+} FDD_mac_ehs_reset_cause_E;
+#endif /* __UMTS_R7__ */
+
+typedef enum _FDD_edch_tti_E
+{
+ FDD_EDCH_TTI_2 = 0,
+ FDD_EDCH_TTI_10 = 1,
+ FDD_EDCH_TTI_TOTAL
+} FDD_edch_tti_E;
+
+typedef enum _FDD_edch_sf_E
+{
+ FDD_EDCH_SF256 = 0,
+ FDD_EDCH_SF128 = 1,
+ FDD_EDCH_SF64 = 2,
+ FDD_EDCH_SF32 = 3,
+ FDD_EDCH_SF16 = 4,
+ FDD_EDCH_SF8 = 5,
+ FDD_EDCH_SF4 = 6,
+ FDD_EDCH_ONE_PHCH = 6,
+ FDD_EDCH_2SF4 = 7,
+ FDD_EDCH_SF2 = 7,
+ FDD_EDCH_2SF2 = 8,
+ FDD_EDCH_2SF2AND2SF4 = 9,
+ FDD_EDCH_2SF2AND2SF4_16QAM = 10,
+ FDD_EDCH_SF_CNT = 11,
+ FDD_EDCH_SF_NA = 12
+} FDD_edch_sf_E;
+
+typedef enum
+{
+ MPR_COMBO_BETA_D_ZERO_HS_ZERO = 0,
+ MPR_COMBO_BETA_D_NON_ZERO_HS_ZERO,
+ MPR_COMBO_BETA_D_ZERO_HS_NON_ZERO,
+ MPR_COMBO_BETA_D_NON_ZERO_HS_NON_ZERO,
+ MPR_COMBO_MAX
+} mpr_combo_E;
+
+typedef enum _FDD_edch_rv_config_E
+{
+ FDD_EDCH_RV0 = 0,
+ FDD_EDCH_RVTABLE = 1
+} FDD_edch_rv_config_E;
+
+typedef struct _FDD_eagch_info_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 255 */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell */
+ FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-AGCH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/
+} FDD_eagch_info_T;
+
+typedef struct _FDD_ehich_info_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 127 */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell (tauDPCH) */
+ FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-HICH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/
+ kal_uint8 signature_seq; /* E-HICH signature sequence 0~39*/
+ kal_uint8 tpc_index; /* TPC combination index. 0 ~ 5 */
+} FDD_ehich_info_T;
+
+typedef struct _FDD_ergch_info_T
+{
+ kal_uint16 psc; /* Primary scrambling code. 1 ~ 511 */
+ kal_uint8 ovsf; /* OVSF code. 0 ~ 127. Should be the same as E-HICH ovsf code */
+ kal_uint16 dpch_offset; /* DPCH frame offset to P-CPICH of this cell (tauDPCH) */
+ FDD_tx_diversity_E tx_diversity_mode; /* TX diversity mode of E-RGCH, and the value only can be FDD_DL_TX_NONE or FDD_DL_TX_STTD.*/
+ kal_uint8 signature_seq; /* E-RGCH signature sequence 0~39*/
+ kal_uint8 rg_comb_index; /* RG combination index. 0 ~ 5 */
+} FDD_ergch_info_T;
+
+typedef struct _FDD_ref_etfci_T
+{
+ kal_uint8 ref_etfci; /* Reference E-TFCI. 0~127 */
+ /* __UMTS_R7__ */
+ kal_uint8 ref_etfci_po; /* Reference E-TFCI PO. 0~31 */
+} FDD_ref_etfci_T;
+
+#ifdef __UMTS_R8__
+/* [R8] Minimum reduced E-DPDCH gain factor */
+typedef enum _FDD_beta_ed_reduced_min_E
+{
+ FDD_beta_ed_8_15 = 0, /* 8/15 */
+ FDD_beta_ed_11_15, /* 11/15 */
+ FDD_beta_ed_15_15, /* 15/15 */
+ FDD_beta_ed_21_15, /* 21/15 */
+ FDD_beta_ed_30_15, /* 30/15 */
+ FDD_beta_ed_42_15, /* 42/15 */
+ FDD_beta_ed_60_15, /* 60/15 */
+ FDD_beta_ed_84_15 /* 84/15 */
+} FDD_beta_ed_reduced_min_E;
+#endif /* __UMTS_R8__ */
+
+typedef struct _FDD_edpdch_info_T
+{
+ /* __UMTS_R7__ */
+ kal_uint8 etfci_table_index; /* E-TFCI table index. 0~1. If the UE is operating in 16QAM, the value is increased by 2. 0~3. */
+ kal_uint8 num_of_ref_etfci; /* number of reference etfci. range:1~8 */
+ FDD_ref_etfci_T ref_etfci[FDD_MAX_REF_ETFCI_NUM]; /* reference E-TFCIs */
+ FDD_edch_sf_E max_ch_code; /* Max. channelisation code */
+ kal_uint8 ul_dpch_num; /* # of UL DPCH, range:0~FDD_MAX_ULDPCH*/
+ kal_uint8 pl_non_max; /* PLnon-max*100/4, range:11~25 */
+#ifdef __UMTS_R8__
+ FDD_beta_ed_reduced_min_E beta_ed_reduced_min; /* Minimum reduced E-DPDCH gain factor */
+#endif /* __UMTS_R8__ */
+} FDD_edpdch_info_T;
+
+typedef struct _FDD_edpcch_info_T
+{
+ kal_uint8 edpcch_po; /* E-DPCCH/DPCCH power offset. 0~8 */
+#ifdef __UMTS_R7__
+ kal_uint8 etfci_boost; /* [Range] Integer(0..127)E-TFCI threshold beyond which boosting of EDPCCH is enabled */
+ kal_uint8 delta_t2tp; /* [Range] Integer (0..6)If E-TFCI-Boost is set to 127 this IE is not needed, otherwise it is mandatory. */
+ kal_bool edpdch_pwr_interpolation; /* True means EDPDCH power Interpolation formula is used, False means EDPDCH power
+ Extrapolation formula is used for the computation of the gain factor £]ed */
+#endif /* __UMTS_R7__ */
+} FDD_edpcch_info_T;
+
+typedef struct _FDD_edch_harq_info_T
+{
+ FDD_edch_rv_config_E edch_rv_config; /* RV config */
+} FDD_edch_harq_info_T;
+
+
+/**********************************************************************************************************************/
+/*********************************** UL1 Interface maintained by UL1D (Begin) *************************************/
+/**********************************************************************************************************************/
+/*UL1D*/typedef enum _FDD_hs_dsch_dc_data_source_E
+/*UL1D*/
+{
+ /*UL1D*/ FDD_PRIMARY_CELL = 0, /* data from primary cell, only hsdsch_data[] should be processed */
+ /*UL1D*/ FDD_SECONDARY_CELL = 1, /* data from secondary cell, only hsdsch_data2[] should be processed */
+ /*UL1D*/ FDD_DUAL_CELL = 2 /* data from dual cells, both hsdsch_data[] and hsdsch_data2[] should be processed*/
+ /*UL1D*/
+} FDD_hs_dsch_dc_data_source_E;
+/*UL1D*/
+/*UL1D*/typedef struct _FDD_uldch_data_req_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn;
+ /*UL1D*/ kal_uint8 ul_mac_event; /* bit 0: UL DCH setup, */
+ /*UL1D*/ /* bit 1: UL DCH release */
+ /*UL1D*/ /* bit 2: UL DCH modify */
+ /*UL1D*/ kal_uint8 dpdch_num;
+ /*UL1D*/ kal_bool restartSRB;
+ /*UL1D*/ kal_bool tx_enable;
+ /*UL1D*/ kal_bool tx_suspend;
+ /*UL1D*/ kal_uint8 tfc_status[FDD_MAX_UL_TFC];
+ /*UL1D*/
+} FDD_uldch_data_req_T;
+/*UL1D*/
+/*UL1D*/
+/*UL1D*/typedef struct _FDD_uldch_data_ind_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn;
+ /*UL1D*/ kal_uint8 num_trch;
+ /*UL1D*/ FDD_ulTrchData trchInfo[FDD_MAX_TRCH_NUM]; /* TrCH information including number of TB and TB size. Note that only 1 TRCH is included in RACH data. */
+ /*UL1D*/ kal_uint16 tfci;
+ /*UL1D*/ kal_uint16 num_data[FDD_MAX_TRCH_NUM]; /* num_data[FDD_MAX_TRCH_NUM]. It means the total TB size on 1 TRCH. Value: 0 ~ FDD_MAX_UL_TB. */
+ /*UL1D*/ kal_uint8 *data[FDD_MAX_TRCH_NUM];
+ /*UL1D*/#ifdef UNIT_TEST
+ /*UL1D*/ void *addr;
+ /*UL1D*/#endif /* UNIT_TEST */
+ /*UL1D*/
+} FDD_uldch_data_ind_T;
+/*UL1D*/
+/*UL1D*//* Input parameters of FDD_umac_e_dch_tick_1() */
+/*UL1D*/typedef struct _FDD_etfc_eval_info_req_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn;
+ /*UL1D*/ kal_uint8 subframe;
+ /*UL1D*/ kal_uint8 mac_event; /* bit0: setup; bit1: release; bit2: modify */
+ /*UL1D*/ FDD_edch_tti_E edch_tti;
+ /*UL1D*/ kal_bool is_tx_suspend[FDD_E_SCELL_TOTAL];
+ /*UL1D*/#if defined( __GEMINI__ ) && defined( __UMTS_RAT__ )
+ /*UL1D*/ kal_bool is_gemini_tx_suspend; /* tx suspended due to Gemini */
+ /*UL1D*/#endif
+ /*UL1D*/ kal_bool compressed_2ms; /* subframe overlaps TG (Refer this value only when 2ms TTI) */
+ /*UL1D*/ kal_uint8 num_of_non_dtx_slots_10ms; /* number of non-gap slots in the corresponding TTI (Refer this value only when 10ms TTI) */
+ /*UL1D*/ kal_uint8 e_agch_result[FDD_E_SCELL_TOTAL]; /* 0: Invalid 1:primary E-RNTI detected 2: secondary E-RNTI detected */
+ /*UL1D*/ kal_uint8 e_agch_data[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint8 e_hich_result_serving[FDD_E_SCELL_TOTAL]; /*0:DTX, 1:ACK, 2:invalid(shall ASSERT), 3:NACK */
+ /*UL1D*/ kal_uint8 e_hich_result_non_serving[FDD_E_SCELL_TOTAL]; /*0:DTX or NACK, 1:ACK, 2:invalid(shall ASSERT) , 3:invalid(shall ASSERT)*/
+ /*UL1D*/ kal_uint8 e_rgch_result_serving[FDD_E_SCELL_TOTAL]; /*0:HOLD or DTX, 1:UP, 2:invalid(shall ASSERT), 3:DOWN */
+ /*UL1D*/ kal_uint8 e_rgch_result_non_serving[FDD_E_SCELL_TOTAL]; /*0:HOLD or DTX, 1:invalid(shall ASSERT), 2:invalid(shall ASSERT), 3:DOWN */
+ /*UL1D*/
+ /*UL1D*/ kal_bool isTtiChangeSuspend;
+ /*UL1D*/ kal_bool isServingCellChange[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_bool isServingCellChNotPartOfPrevEdchRls[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint16 mac_harq_event; /* bit 0: TTI change */
+ /*UL1D*/ /* bit 1: E-TFCI table index change */
+ /*UL1D*/ /* bit 2: HARQ RV ReConfiguration */
+ /*UL1D*/ /* bit 3: PLnon-max change */
+ /*UL1D*/ /* bit 4: Secondary cell activated */
+ /*UL1D*/ /* bit 5: Secondary cell deactivated */
+ /*UL1D*/ kal_bool insufficient_preamble[FDD_E_SCELL_TOTAL]; // Cannot transmit E-DCH due to insufficient UL DPCCH preamble.
+ /*UL1D*/ kal_bool match_mac_dtx_cycle[FDD_E_SCELL_TOTAL]; // If the condition of last paragraph of 25.321 11.8.1.4 is fulfilled.
+ /*UL1D*/ kal_bool is_dtx_cycle_2[FDD_E_SCELL_TOTAL]; // The DTX feature is configured by higher layers, and there has not been any E-DCH transmission for the last "Inactivity Threshold for UE DTX cycle 2" E-DCH TTIs.
+ /*UL1D*/ kal_bool is_cedch; /*Notify UMAC if common EDCH or not*/
+ /*UL1D*/ kal_uint8 *sf_of_etfci;
+ /*UL1D*/ kal_bool restartSRB;
+ /*UL1D*/ kal_uint32 SlotTick_FRC; /* The absolute FRC (free-run counter) value of 1 slot ahead of Tx timing, the unit is micro-second (us) */
+ /*UL1D*/ /* Ex: FRC value of slot 8 will be provided if Tx on slot 9 */
+ /*UL1D*/
+ /*UL1D*/
+} FDD_etfc_eval_info_req_T ;
+/*UL1D*/
+/*UL1D*//* Output parameters of FDD_umac_e_dch_tick_1() */
+/*UL1D*/typedef struct _FDD_etfc_eval_info_ind_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/ kal_uint8 harq_id; /* 2ms TTI: 0..7, 10ms TTI: 0..3 */
+ /*UL1D*/ kal_bool tx_enable[FDD_E_SCELL_TOTAL]; /* true=on, false=off */
+ /*UL1D*/ kal_bool is_new_tx[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint8 delta_harq[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_bool collision_resolved;
+ /*UL1D*/ kal_bool is_tebs_larger_than_0;
+ /*UL1D*/ kal_uint8 serving_grant[FDD_E_SCELL_TOTAL];
+ /*UL1D*/ kal_uint8 non_scheduled_delta_harq;
+ /*UL1D*/ kal_uint16 non_scheduled_data_size;
+ /*UL1D*/
+} FDD_etfc_eval_info_ind_T;
+/*UL1D*/
+/*UL1D*//* Input parameters of FDD_umac_e_dch_tick_2() */
+/*UL1D*/typedef struct _FDD_edch_data_req_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/ FDD_edch_scell_E edch_cell;
+ /*UL1D*/ FDD_edch_tti_E edch_tti; /* E-DCH TTI 2ms or 10ms */
+ /*UL1D*/
+ /*UL1D*/ kal_bool compressed_2ms; /* If the corresponding subframe overlaps TG (Refer this value only when 2ms TTI) */
+ /*UL1D*/ kal_uint8 num_of_non_dtx_slots_10ms; /* number of non-gap slots in the corresponding TTI (Refer this value only when 10ms TTI) */
+ /*UL1D*/ kal_uint8 *supported_etfci_bitmap; /* 2 LSB bits of [0] = etfci 0, 2 MSB bits of [31] = etfci 127. */
+ /*UL1D*/ /* 11=support, 10=power not support, 01=data size not support, 00=not support */
+ /*UL1D*/ kal_uint16 uph_in_dB; /*UE transmission power headroom reported by UL1(unit: dB)*/
+ /*UL1D*/
+} FDD_edch_data_req_T ;
+/*UL1D*/
+/*UL1D*//* Output parameters of FDD_umac_e_dch_tick_2() */
+/*UL1D*/typedef struct _FDD_edch_data_ind_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/ kal_bool tx_enable; /* true=on, false=off */
+ /*UL1D*/ kal_uint8 harq_id; /* 2ms TTI: 0..7, 10ms TTI: 0..3 */
+ /*UL1D*/ kal_bool is_new_tx;
+ /*UL1D*/ kal_uint8 etfci; /* Range: 0..127 */
+ /*UL1D*/ kal_uint8 ntx1; /* 10 ms TTI: 8..15, 2ms TTI: don't care */
+ /*UL1D*/ kal_bool happy;
+ /*UL1D*/ kal_uint8 rsn; /* Range: 0..3 */
+ /*UL1D*/ kal_uint8 delta_harq; /* Range: 0..6 */
+ /*UL1D*/ kal_uint16 tb_size;
+ /*UL1D*/ kal_uint8 *data; /* The buffer contains MAC-es/e PDU data */
+ /*UL1D*/ /* Must be 4 bytes alignment */
+ /*UL1D*/ /* NULL if tx_enable == false */
+ /*UL1D*/ kal_uint8 tebs; /* SI of UMAC */
+ /*UL1D*/ kal_uint8 re_tx_num; /* re-transmission number */
+ /*UL1D*/ kal_uint32 ScheduledGrantPayloadBits; /* Configured SG bits; for RG judgement */
+ /*UL1D*/ kal_uint32 ScheduledGrantUsedBits; /* Used SG bits; for RG judgement */
+ /*UL1D*/ kal_bool scheduled; /* Whether this is scheduled E-DCH transmission or not. */
+ /*UL1D*/
+} FDD_edch_data_ind_T;
+/*UL1D*/
+/*UL1D*//* No output parameters of FDD_umac_e_dch_tick_3() */
+/*UL1D*/
+/*UL1D*//* Input parameters of FDD_umac_e_dch_tick_3() */
+/*UL1D*/typedef struct _FDD_umac_edch_data_req_tick_3_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/
+} FDD_umac_edch_data_req_tick_3_T;
+/*UL1D*/
+/*UL1D*//* Output parameters of FDD_umac_e_dch_tick_3() */
+/*UL1D*/typedef struct _FDD_umac_edch_data_ind_tick_3_T
+/*UL1D*/
+{
+ /*UL1D*/ kal_uint8 cfn; /* Range: 0..255 */
+ /*UL1D*/ kal_uint8 subframe; /* 10ms=0, 2ms=0..4. */
+ /*UL1D*/
+} FDD_umac_edch_data_ind_tick_3_T;
+/*UL1D*/
+/*UL1D*/extern kal_bool FDD_UL1D_Check_ASU( kal_int32 added_cell_tm/* echips */, kal_uint16 added_cell_dpch_offset /* chips */ );
+/*UL1D*/extern kal_bool FDD_UL1D_RxDualCarrier_Check( kal_uint16 pri_uarfcn, kal_uint16 sec_uarfcn, kal_int16 *pri_sec_diff );
+/*UL1D*/extern kal_bool FDD_UL1D_RxMultiCarrier_Check( kal_uint16 *uarfcn_list, kal_uint8 num_uarfcn );
+/*UL1D*/extern kal_bool FDD_UL1D_TxMultiCarrier_Check( kal_uint16 *uarfcn_list, kal_uint8 num_uarfcn );
+/*UL1D*/kal_uint16/*100kHz*/ FDD_UL1D_RRC_UlUarfcnToFrequency( kal_uint16 uarfcn );
+/**********************************************************************************************************************/
+/*********************************** UL1 Interface maintained by UL1D (End) ***************************************/
+/**********************************************************************************************************************/
+/* Input parameters of FDD_umac_e_dch_tick_5() */
+typedef struct
+{
+ kal_bool match_mac_dtx_cycle;
+ kal_uint8 long_preamble_target_cfn; // 0..255.
+ kal_uint8 long_preamble_target_subframe; // 10ms=0, 2ms=0..4.
+ FDD_edch_scell_E edch_cell;
+} FDD_etfc_eval_lpr_info_req_T;
+
+#ifdef __UMTS_R7__
+/* [R7] Enumeration of rrc state. To distinguish the usage of HS-DSCH */
+typedef enum _FDD_rrc_state_E
+{
+ FDD_CELL_DCH,
+ FDD_URA_PCH,
+ FDD_CELL_PCH,
+ FDD_IDLE_FACH,
+ FDD_CELL_FACH
+} FDD_rrc_state_E;
+
+/* [R7] Enumeration of octet aligned table 9.2.3.2 is used, else bit aligned table 9.2.3.1 is used in [25.321]. */
+typedef enum _FDD_hs_tbsize_table_E
+{
+ FDD_BIT_ALIGNED = 0,
+ FDD_OCTET_ALIGNED
+} FDD_hs_tbsize_table_E;
+
+/* [R7] Enumeration of dtx_drx_status. */
+typedef enum _FDD_dtx_drx_status_E
+{
+ FDD_DTX_DRX_OFF = 0, /* Disable CPC operation */
+ FDD_DTX_DRX_NEW_TIMING, /* Use new CPC configuration */
+ FDD_DTX_DRX_ON_REVERT, /* Uses the old CPC configuration when HHO revert. Consider oly the HS-SCCH orders which were acknowledged prior to the activation timer of the received message. */
+ FDD_DTX_DRX_ON_HS_SERV_CELL_CHANGE, /* Uses the old CPC configuration when serving cell was changed. Consider the HS-SCCH order were never received. */
+ FDD_DTX_DRX_ALL_RL_TIMING_MODIFY, /* If the CPC choice timing is ¡§continue¡¨ when receiving ALL RL TIMING MODIFY, Uses the old CPC configuration. */
+ FDD_DTX_DRX_INVALID /* Invalid DTX_DRX status */
+} FDD_dtx_drx_status_E;
+
+/* [R7] Enumeration of enabling delay. Uint is radio frame. */
+typedef enum _FDD_enabling_delay_E
+{
+ FDD_ED_0 = 0,
+ FDD_ED_1,
+ FDD_ED_2,
+ FDD_ED_4,
+ FDD_ED_8,
+ FDD_ED_16,
+ FDD_ED_32,
+ FDD_ED_64,
+ FDD_ED_128
+} FDD_enabling_delay_E;
+
+/* [R7] Enumeration of ue_dtx_cycle2_inactivity_threshold. Uint is E-DCH TTIs. */
+typedef enum _FDD_ue_dtx_cycle2_inactivity_threshold_E
+{
+ FDD_dtx_cycle2_inaTrHd_1 = 0,
+ FDD_dtx_cycle2_inaTrHd_4,
+ FDD_dtx_cycle2_inaTrHd_8,
+ FDD_dtx_cycle2_inaTrHd_16,
+ FDD_dtx_cycle2_inaTrHd_32,
+ FDD_dtx_cycle2_inaTrHd_64,
+ FDD_dtx_cycle2_inaTrHd_128,
+ FDD_dtx_cycle2_inaTrHd_256
+} FDD_ue_dtx_cycle2_inactivity_threshold_E;
+
+/* [R7] Enumeration of ue_dtx_long_preamble_length. Uint is slot. */
+typedef enum _FDD_ue_dtx_long_preamble_length_E
+{
+ FDD_slot_2 = 0,
+ FDD_slot_4,
+ FDD_slot_15,
+ FDD_slot_invalid
+} FDD_ue_dtx_long_preamble_length_E, FDD_dtx_pream_len_E;
+
+/* [R7] Enumeration of cqi_dtx_timer period. Uint is subframe. */
+typedef enum _FDD_cqi_dtx_timer_E
+{
+ FDD_subframe_0 = 0,
+ FDD_subframe_1,
+ FDD_subframe_2,
+ FDD_subframe_4,
+ FDD_subframe_8,
+ FDD_subframe_16,
+ FDD_subframe_32,
+ FDD_subframe_64,
+ FDD_subframe_128,
+ FDD_subframe_256,
+ FDD_subframe_512,
+ FDD_subframe_infinity
+} FDD_cqi_dtx_timer_E;
+
+/* [R7] Enumeration of ue_dpcch_burst. Uint is subframe. */
+typedef enum _FDD_ue_dpcch_burst_E
+{
+ FDD_burst_1 = 0,
+ FDD_burst_2,
+ FDD_burst_5
+} FDD_ue_dpcch_burst_E;
+
+/* [R7] Enumeration of mac_inactivity_threshold. Uint is E-DCH TTI. */
+typedef enum _FDD_mac_inactivity_threshold_E
+{
+ FDD_mac_inaTrHd_1 = 0,
+ FDD_mac_inaTrHd_2,
+ FDD_mac_inaTrHd_4,
+ FDD_mac_inaTrHd_8,
+ FDD_mac_inaTrHd_16,
+ FDD_mac_inaTrHd_32,
+ FDD_mac_inaTrHd_64,
+ FDD_mac_inaTrHd_128,
+ FDD_mac_inaTrHd_256,
+ FDD_mac_inaTrHd_512,
+ FDD_mac_inaTrHd_infinity
+} FDD_mac_inactivity_threshold_E;
+
+/* [R7] Enumeration of ue_rx_cycle. Uint is subframe. */
+typedef enum _FDD_ue_drx_cycle_E
+{
+ FDD_drx_cycle_4 = 0,
+ FDD_drx_cycle_5,
+ FDD_drx_cycle_8,
+ FDD_drx_cycle_10,
+ FDD_drx_cycle_16,
+ FDD_drx_cycle_20
+} FDD_ue_drx_cycle_E;
+
+/* [R7] Enumeration of ue_drx_cycle_inactivity_threshold. Uint is subframe. */
+typedef enum _FDD_ue_drx_cycle_inactivity_threshold_E
+{
+ FDD_drx_cycle_inaTrHd_0 = 0,
+ FDD_drx_cycle_inaTrHd_1,
+ FDD_drx_cycle_inaTrHd_2,
+ FDD_drx_cycle_inaTrHd_4,
+ FDD_drx_cycle_inaTrHd_8,
+ FDD_drx_cycle_inaTrHd_16,
+ FDD_drx_cycle_inaTrHd_32,
+ FDD_drx_cycle_inaTrHd_64,
+ FDD_drx_cycle_inaTrHd_128,
+ FDD_drx_cycle_inaTrHd_256,
+ FDD_drx_cycle_inaTrHd_512
+} FDD_ue_drx_cycle_inactivity_threshold_E;
+
+/* [R7] Enumeration of ue_grantMonitoring_inactivity_threshold. Uint is subframe. */
+typedef enum _FDD_ue_grantMonitoring_inactivity_threshold_E
+{
+ FDD_graMon_inaTrhd_0 = 0,
+ FDD_graMon_inaTrhd_1,
+ FDD_graMon_inaTrhd_2,
+ FDD_graMon_inaTrhd_4,
+ FDD_graMon_inaTrhd_8,
+ FDD_graMon_inaTrhd_16,
+ FDD_graMon_inaTrhd_32,
+ FDD_graMon_inaTrhd_64,
+ FDD_graMon_inaTrhd_128,
+ FDD_graMon_inaTrhd_256
+} FDD_ue_grantMonitoring_inactivity_threshold_E;
+
+/* [R7] HS-SCCH less mode status in CELL_DCH state */
+typedef enum _FDD_hs_scch_less_status_E
+{
+ FDD_HS_SCCH_LESS_OFF = 0, /* disable HS-SCCH less operation and all HS-SCCH less parameters are invalid. */
+ FDD_HS_SCCH_LESS_ON, /* use new HS-SCCH less configuration and reset order. */
+ FDD_HS_SCCH_LESS_ON_REVERT, /* Uses the old HS-SCCH less configuration when HHO revert or 3G to 2G inter-RAT procedure revert. */
+ FDD_HS_SCCH_LESS_ALL_RL_TIMING_MODIFY, /* If the HS-SCCH less operation choice timing is "continue" when receiving ALL RL TIMING MODIFY,
+ * uses the old HS-SCCH less configuration without reset order. */
+ FDD_HS_SCCH_LESS_INVALID /* SLCE internal use, won't config this enum to UL1. */
+} FDD_hs_scch_less_status_E;
+#endif /* __UMTS_R7__ */
+
+#ifdef __UMTS_R8__
+/* [R8] Enumeration of enhanced CELL_FACH DRX status */
+typedef enum _FDD_hs_cell_fach_drx_status_E
+{
+ FDD_DRX_OFF = 0, /* No DRX in CELL_FACH state or ETWS reception is on-going */
+ FDD_DRX_ON_NORMAL, /* UL1 should start CELL_FACH DRX when the normal criterion is fulfilled */
+ FDD_DRX_ON_ETWS_END, /* SLCE should set this enum when the ETWS procedure ends */
+ FDD_DRX_INVALID /* SLCE internal use. Invalid for UL1. */
+} FDD_hs_cell_fach_drx_status_E;
+
+/* [R8] inactivity timer to start HS CELL_FACH DRX */
+typedef enum _FDD_hs_t321_E
+{
+ FDD_t321_100 = 0, /* 100ms */
+ FDD_t321_200 = 1, /* 200ms */
+ FDD_t321_400 = 2, /* 400ms */
+ FDD_t321_800 = 3 /* 800ms */
+} FDD_hs_t321_E;
+
+/* Length of inactivity timer T321/T328/T329 */
+typedef enum
+{
+ FDD_EFACH_DRX_1_LEVEL,
+ FDD_EFACH_DRX_2_LEVEL
+} FDD_hs_cell_fach_drx_level_E;
+
+/* Length of inactivity timer T321/T328/T329 */
+typedef enum
+{
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_INVALID,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_20MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_40MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_60MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_80MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_100MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_200MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_400MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_500MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_800MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_1000MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_2000MS,
+ FDD_EFACH_DRX_INACTIVITY_TIMER_LEN_4000MS
+} FDD_hs_cell_fach_drx_status_timer_length_E;
+
+/* Length of EFACH DRX cycle */
+typedef enum
+{
+ FDD_EFACH_DRX_CYCLE_LEN_INVALID,
+ FDD_EFACH_DRX_CYCLE_LEN_2_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_4_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_8_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_16_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_32_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_64_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_128_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_256_FRAMES,
+ FDD_EFACH_DRX_CYCLE_LEN_512_FRAMES
+} FDD_hs_cell_fach_drx_cycle_E;
+
+/* Length of EFACH DRX burst */
+typedef enum
+{
+ FDD_EFACH_DRX_BURST_LEN_INVALID,
+ FDD_EFACH_DRX_BURST_LEN_1_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_2_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_4_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_8_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_16_FRAMES,
+ FDD_EFACH_DRX_BURST_LEN_2_SUBFRAMES,
+ FDD_EFACH_DRX_BURST_LEN_4_SUBFRAMES
+} FDD_hs_cell_fach_drx_rx_burst_E;
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+/* [R8] variable to control UL1 DC HS-DSCH receiving */
+typedef enum _FDD_dc_hsdpa_status_E
+{
+ FDD_DC_HSDPA_OFF = 0, /* Disable DC-HSDPA operation and all DC-HSDPA parameters are invalid. */
+ FDD_DC_HSDPA_ON, /* Use new DC-HSDPA configuration and reset order */
+ FDD_DC_HSDPA_ON_REVERT, /* Uses the old DC-HSDPA configuration when HHO revert or 3G to 2G inter-RAT procedure revert. */
+ FDD_DC_HSDPA_ALL_RL_TIMING_MODIFY, /* If the DC-HSDPA choice timing is "continue" when receiving ALL_RL_TIMING_MODIFY,
+ * uses the old DC-HSDPA configuration without reset order. */
+ FDD_DC_HSDPA_ON_WITHOUT_RESET_ORDER, /* Use new DC-HSDPA configuration and do not reset order */
+ FDD_DC_HSDPA_INVALID /* SLCE internal use, won't config this enum to UL1 */
+} FDD_dc_hsdpa_status_E;
+
+/* [R8] Specify that E-DCH transmission is in dedicated state or common state */
+typedef enum _FDD_edch_transmission_type_E
+{
+ FDD_EDCH_IN_DCH_STATE = 0, /* E-DCH allocated in dedicated state */
+ FDD_EDCH_IN_COMMON_STATE /* E-DCH allocated in common state */
+} FDD_edch_transmission_type_E;
+
+/* [R8] common E-DCH suspend cause. UL1 Internal use */
+typedef enum _FDD_cedch_suspend_cause_type_E
+{
+ FDD_CEDCH_NONE = 0, /* no common EDCH */
+ FDD_CEDCH_SUSPEND_RLF, /* common EDCH terminate due to RLF */
+ FDD_CEDCH_SUSPEND_SYNCAA_FAIL, /* common EDCH terminate due to Sync AA failure */
+ FDD_CEDCH_SUSPEND_PROCESS_TERMINATION, /* common EDCH terminate from UMAC */
+ FDD_CEDCH_SUSPEND_PREAMBLE, /* common EDCH terminate when AI result has not been received by UL1C */
+ FDD_CEDCH_SUSPEND_CHANNEL_RELEASE /* common EDCH terminate due to channel release */
+} FDD_cedch_suspend_cause_type_E;
+
+/* [R8] Transport channel type in random access procedure */
+typedef enum _FDD_cell_fach_ul_trch_type_E
+{
+ FDD_CELL_FACH_UL_TRCH_TYPE_RACH = 0, /* random access attemp for RACH transmission */
+ FDD_CELL_FACH_UL_TRCH_TYPE_EDCH /* random access attemp for E-DCH transmission */
+} FDD_cell_fach_ul_trch_type_E;
+#endif /* __UMTS_R8__ */
+
+
+#ifdef __UMTS_R7__
+typedef struct _FDD_hs_scch_less_info_T
+{
+ FDD_hs_scch_less_status_E hs_scch_less_status; /* HS-SCCH less mode control flag */
+ kal_uint8 hs_scch_less_hspdsch_code_index; /* [Range] Integer(1..15) Index of the first HS-PDSCH code */
+ FDD_hs_tb_size_list_T hs_scch_less_tb_size_list[FDD_MAX_SCCH_LESS_BLK_NUM]; /* 1..<maxHSSCCHLessTrBlk > maxHSSCCHLessTrBlk = 4 */
+} FDD_hs_scch_less_info_T;
+
+typedef struct _FDD_hs_fach_pch_rl_info_T
+{
+ kal_uint16 dl_freq; /* DL UARFCN */
+ kal_int32 tm; /* LST to Cell boundary. 0 ~ 38044*8-1 */
+ kal_int16 off; /* Frame # offset to LST. 0 ~ 4095 */
+ kal_uint16 psc; /* Primary scrambling code */
+ kal_bool sttd; /* Indicate if STTD is used for P-CPICH for this RL */
+ /* If the value of tm is not equal to -1, UL1 will use this value */
+ /* If the value of tm is equal to -1, UL1 will not use this value */
+ kal_int16 rscp; /* Serving cell RSCP. Range: -464 ~ -100 means (-116 ~ -25 )dBm in 0.25 dB step*/
+} FDD_hs_fach_pch_rl_info_T;
+
+typedef struct _FDD_hs_dtx_drx_timing_info_T
+{
+ FDD_enabling_delay_E ED; /* Time threshold the UE waits until enabling a new timing pattern for DTX/ DRX operation. Uint is radio frame. */
+ kal_uint8 ue_dtx_drx_offset; /* [Range]: 0~159 Units of subframes. Offset of the DTX and DRX cycles at the given TTI. */
+} FDD_hs_dtx_drx_timing_info_T;
+
+typedef struct _FDD_hs_dtx_param_T
+{
+ kal_bool ue_dtx_on; /* DTX operation enable/ disable */
+ kal_bool tti_change; /* E-DCH TTI is change to 2ms->10ms or 10ms->2ms */
+ kal_uint8 ue_dtx_cycle1; /* DPCCH activity pattern.(1, 5, 10, 20 subframes for 10 ms TTI; 1, 4, 5, 8, 10, 16, 20 subframes for 2 ms TTI) */
+ kal_uint8 ue_dtx_cycle2; /* DPCCH activity pattern.(5, 10, 20, 40, 80, 160 subframes for 10 ms TTI;4, 5, 8, 10, 16, 20, 32, 40, 64, 80, 128, 160 subframes for 2 ms TTI) */
+ FDD_ue_dtx_cycle2_inactivity_threshold_E cycle2_inactivity_threshold; /* When to activate the UE DTX cycle 2 after the last uplink data transmission */
+ FDD_ue_dtx_long_preamble_length_E preamble_length; /* Uplink preamble length. Units of slots.Default value is 2 slots */
+ FDD_cqi_dtx_timer_E timer_length; /* Number of subframes after an HS-DSCH reception during which the CQI reports have higher priority than the DTX pattern and are transmitted according to the regular CQI pattern */
+ FDD_ue_dpcch_burst_E dpcch_burst1; /* Length of DPCCH transmission when UE DTX cycle 1 is active Units of sub-frames */
+ FDD_ue_dpcch_burst_E dpcch_burst2; /* Length of DPCCH transmission when UE DTX cycle 2 is active Units of sub-frames */
+
+ kal_uint8 mac_dtx_cycle; /* Pattern of time instances where the start of uplink E-DCH transmission after inactivity is allowed.(5, 10, 20 subframes for 10 ms TTI; 1, 4, 5, 8, 10, 16, 20 subframes for 2 ms TTI */
+ FDD_mac_inactivity_threshold_E mac_inactivity_threshold; /* E-DCH inactivity time after which the UE can start E-DCH transmission only at given time. */
+} FDD_hs_dtx_param_T;
+
+typedef struct _FDD_hs_drx_param_T
+{
+ kal_bool ue_drx_on; /* DRX operation enable/ disable */
+ FDD_ue_drx_cycle_E drx_cycle_length; /* HS-SCCH reception pattern, i.e. how often UE has to monitor HSSCCH. */
+ FDD_ue_drx_cycle_inactivity_threshold_E drx_cycle_inactivity_threshold; /* Number of subframes after downlink activity where UE has to continuously monitor HS-SCCH. Units of subframes */
+ FDD_ue_grantMonitoring_inactivity_threshold_E grantMonitoring_inactivity_threshold; /* Number of subframes after uplink activity when UE has to continue to monitor E-AGCH/E-RGCH. Units of E-DCH TTIs. */
+ kal_bool ue_drx_grantMonitoring; /* whether the UE is required to monitor E-AGCH/E-RGCH when they overlap with the start of an HS-SCCH reception as defined in the HS-SCCH reception pattern */
+} FDD_hs_drx_param_T;
+
+typedef struct _FDD_hs_dtx_drx_info_T
+{
+ FDD_dtx_drx_status_E status;
+ FDD_hs_dtx_drx_timing_info_T timing;
+ FDD_hs_dtx_param_T hs_dtx_param;
+ FDD_hs_drx_param_T hs_drx_param;
+} FDD_hs_dtx_drx_info_T;
+
+typedef struct _FDD_hs_cell_pch_state_info_T
+{
+#ifdef UL1_PHASE3_TEST
+ kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+ kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#else
+// kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+// kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#endif
+ FDD_pich_info_T pich_info;
+ kal_uint8 pcch_hspdsch_ovsf; /* [Range] Integer (0..15) HS-PDSCH channel associated with the PICH for HSSCCH less PAGING TYPE 1 message transmission. */
+ kal_uint8 num_of_pcch_trans; /* [Range] Integer (1..5) number of subframes used to transmit the PAGING TYPE 1. */
+ kal_int8 pcch_tb_size_index[2]; /* [Range] Integer (1..32). -1 if this is invalid. Index of value range 1 to 32 of the MAC-ehs transport block size as described in appendix A of 25.321. */
+ FDD_hs_fach_pch_rl_info_T fach_pch_rl_info;
+} FDD_hs_cell_pch_state_info_T;
+
+typedef struct _FDD_hs_cell_fach_state_info_T
+{
+#ifdef UL1_PHASE3_TEST
+ kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+ kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#else
+// kal_bool bcch_h_rnti_valid; /* If bcch_h_rnti_valid = TRUE, UL1 need to receive BCCH over HS-DSCH. Otherwise, UL1 does not need to receive BCCH over HS-DSCH. */
+// kal_uint16 bcch_h_rnti; /* BCCH specific H-RNTI */
+#endif
+ FDD_hs_fach_pch_rl_info_T fach_pch_rl_info;
+} FDD_hs_cell_fach_state_info_T;
+
+typedef struct _FDD_hs_cell_dch_state_info_T
+{
+ kal_bool dl_64QAM_on; /* 64QAM enable/disable */
+ FDD_hs_tbsize_table_E hsdsch_tbsize_table; /* If this IE is present, octet aligned table [25.321] is used, else bit aligned table [25.321] is used.
+ In DCH state, this field is assigned by SLCE. Otherthan DCH state, UL1 should use octet-aligned table by itself.*/
+} FDD_hs_cell_dch_state_info_T;
+
+typedef union _FDD_hspdsch_state_info_T
+{
+ FDD_hs_cell_pch_state_info_T cell_pch; /* The parameters in CELL_PCH or URA state. */
+ FDD_hs_cell_fach_state_info_T cell_fach; /* The parameters in CELL_FACH or IDLE_FAC state. */
+ FDD_hs_cell_dch_state_info_T cell_dch; /* The parameters in CELL_DCH state. */
+} FDD_hspdsch_state_info_T;
+
+#ifdef __UMTS_R8__
+typedef struct _FDD_hs_cell_fach_drx_T
+{
+ kal_bool interrupt_by_hsdsch; /* TRUE : the DRX operation can be interrupted by HS-DSCH data. */
+ /* FALSE: the DRX operation cannot be interrupted by HS-DSCH data. */
+ FDD_hs_cell_fach_drx_status_E hs_cell_fach_drx_status; /* enhanced CELL_FACH DRX status */
+ FDD_hs_cell_fach_drx_level_E drx_level; /* 1-level DRX or 2-level DRX cycle is used */
+ /* When NW configures R8 DRX pattern, SLCE will configure 2nd-level DRX parameters only
+ and set 1st-level DRX parameters as invalid */
+ FDD_hs_cell_fach_drx_status_timer_length_E second_timer_length; /* Inactivity timer to start 1-level HS CELL_FACH DRX. Set from T321(SIB5) or T329 (SIB22) */
+ FDD_hs_cell_fach_drx_cycle_E second_drx_cycle_length; /* HS CELL_FACH DRX cycle length during the 2nd DRX operation */
+ FDD_hs_cell_fach_drx_rx_burst_E second_drx_burst_length; /* the period within the 2nd HS DRX cycle that the UE continuously receive */
+ FDD_hs_cell_fach_drx_status_timer_length_E first_timer_length; /* Inactivity timer to start 2-level HS CELL_FACH DRX. Set from T321(SIB5) or T328 (SIB22) */
+ FDD_hs_cell_fach_drx_cycle_E first_drx_cycle_length; /* HS CELL_FACH DRX cycle length during the 1st DRX operation */
+ FDD_hs_cell_fach_drx_rx_burst_E first_drx_burst_length; /* The period within the 1st HS DRX cycle that the UE continuously receive */
+} FDD_hs_cell_fach_drx_T;
+
+typedef struct _FDD_secondary_hspdsch_info_T
+{
+ kal_bool dl_64QAM_on; /* If 64QAM supported in secondary HS-DSCH */
+ kal_uint16 h_rnti; /* h_rnti to decode secondary HS-DSCH receiving */
+ FDD_hs_tbsize_table_E hsdsch_tbsize_table; /* If dl_64QAM_on = KAL_TRUE, hsdsch_tbsize_table should be FDD_OCTET_ALIGNED. */
+} FDD_secondary_hspdsch_info_T;
+
+#define FDD_DC_HSDPA_ALL_CONFIG_BIT 0x7F
+typedef struct _FDD_dc_hsdpa_info_T
+{
+ kal_uint8 modify_field; /* Bit 0: FDD_hs_scch_info_T
+ * Bit 1: FDD_secondary_hspdsch_info_T
+ * Bit 2: psc
+ * Bit 3: meas_po
+ * Bit 4: dl_freq
+ * Bit 5: sttd
+ * Bit 6: dpch_offset */
+ FDD_dc_hsdpa_status_E dc_hsdpa_status; /* variable to control UL1 DC HS-DSCH receiving */
+ FDD_hs_scch_info_T hs_scch_info; /* Secondary HS-SCCH info. */
+ FDD_secondary_hspdsch_info_T sec_h_info; /* Secondary HS-PDSCH info. */
+ kal_uint16 psc; /* Primary scrambling code used in secondary H cell*/
+ kal_int8 meas_po; /* Measurement power offset, step = half dB. Range = -12~26 (-6dB~13dB)*/
+ kal_uint16 dl_freq; /* DL UARFCN, 0~16383*/
+ kal_bool sttd; /* TRUE: STTD is used for P-CPICH of the secondary cell
+ * FALSE: STTD is not used for P-CPICH of the secondary cell.*/
+#ifdef __UMTS_R9__
+ kal_uint8 dpch_offset; /* [R9] f-dpch offset of 2nd freq when DC-HSUPA is configured,
+ otherwise invalid value 0xFFFF is configured. (0~38144 chips by step of 256 )
+ [R10] For additional dc-hsdpa (dc_hsdpa_info[1]/dc_hsdpa_info[2]), this is always invalid value 0xFFFF. */
+#endif /*__UMTS_R9__*/
+} FDD_dc_hsdpa_info_T;
+
+typedef struct _FDD_dl_pc_info_T /* DL power control information used for common E-DCH */
+{
+ kal_uint8 tpc_target; /* range: 1~10, the actual TPC command error rate target is tpc_target/100 */
+ kal_uint8 dpc_mode; /*DL Power control mode. 0 or 1 or 2. In current spec, SLCE will always fix this field by 0 for common E-DCH. */
+ kal_uint8 fdpch_slot_format; /* range: 0~9. In current spec, SLCE will always fix this field by 0 for common E-DCH. */
+} FDD_dl_pc_info_T;
+
+typedef struct _FDD_ul_dpch_code_info_T /* UL DPCH information used for common E-DCH transmission */
+{
+ FDD_sc_type_E sc_type; /* short type or long type scrambling code */
+ kal_uint32 sc_code; /* 0 ~ 16777215 */
+} FDD_ul_dpch_code_info_T;
+
+typedef struct _FDD_edch_resource_list_T
+{
+ kal_uint8 s_offset; /* symbol offset. range: 0~9 */
+ kal_uint8 fdpch_ovsf; /* 0 ~ 255 */
+ kal_uint8 ehirgch_ovsf; /* ovsf code for receiving E-HICH and E-RGCH in common E-DCH transmission */
+ kal_uint8 hich_signature_seq; /* E-HICH signature sequence in common E-DCH transmission [Range: 0~39] */
+ kal_uint8 rgch_signature_seq; /* E-RGCH signature sequence in common E-DCH transmission [Range: 0~39, 0xff means invalid. No need to decode E-RGCH] */
+ FDD_ul_dpch_code_info_T ul_dpch_code_info; /* UL DPCH information used for common E-DCH transmission */
+} FDD_edch_resource_list_T;
+
+typedef struct _FDD_common_edch_info_T
+{
+ kal_uint8 add_tran_back_off; /* 0 ~ 15, unit is TTI */
+ kal_uint8 edch_resource_num; /* 1~32 */
+ FDD_edch_resource_list_T edch_resource_list[32]; /* common RLs for E-DCH transmission */
+ FDD_ul_pc_info_T ul_pc; /* ul power control info. */
+} FDD_common_edch_info_T;
+
+typedef struct _FDD_edch_specific_info_T
+{
+ kal_bool e_ai_ind; /* TRUE: E-AI should be used. FALSE: E-AI should not be used. */
+ kal_int8 po_p_e; /* -5 ~ 10 dB, power offset between last TX preamble and initial DPCCH */
+} FDD_edch_specific_info_T;
+
+
+typedef struct
+{
+ kal_bool d_hrnti_valid;
+ kal_uint16 d_hrnti;/*dH-RNTI*/
+
+ kal_bool c_hrnti_valid;
+ kal_uint16 c_hrnti;/*cH-RNTI*/
+
+ kal_bool b_hrnti_valid;
+ kal_uint16 b_hrnti;/*cH-RNTI*/
+
+} FDD_hs_hrnti_info_T;
+
+
+#ifdef __UMTS_R9__
+
+typedef enum
+{
+ FDD_DC_HSUPA_OFF, /* disable DC-HSUPA operation and all DC-HSUPA parameters are invalid */
+ FDD_DC_HSUPA_ON, /* use new DC-HSUPA configuration and reset order.
+ The default status is deactivated until receiving HS-SCCH order to activate,
+ and don't need sync A procedure on 2nd freq. */
+ FDD_DC_HSUPA_ALL_RL_TIMING_MODIFY, /* If the DC-HSUPA choice timing is "continue" when receiving ALL_RL_TIMING_MODIFY,
+ SLCE uses the old DC-HSUPA configuration to UL1, and UL1 applies the configuration without reset order.
+ Do not apply sync A procedue no matter the DC-HSUPA status after E-DCH setup. */
+ FDD_DC_HSUPA_ON_WITHOUT_RESET_ORDER, /* Use new DC-HSUPA configuration and do not reset order.
+ Sync A will need if DC-HSUPA is activate after E-DCH setup, but not for E-DCH modify. */
+ FDD_DC_HSUPA_INVALID /* SLCE internal use, won't config this enum to UL1 */
+
+} FDD_dc_hsupa_status_E;
+
+typedef enum
+{
+ FDD_DC_HSUPA_MODIFY_NORMAL_CONFIG, /* Normal configuration */
+ FDD_DC_HSUPA_MODIFY_ASU, /* ASU configuration. */
+ FDD_DC_HSUPA_MODIFY_ALL_ACTIVE_SET, /* All active set cell change (RBR) */
+ FDD_DC_HSUPA_MODIFY_NUM
+} FDD_dc_hsupa_modify_type_E;
+
+
+typedef struct
+{
+ kal_bool pri_e_rnti_valid; /* Indicate if pri_e_rnti field is valid */
+ kal_uint16 pri_e_rnti; /* Primary E-RNTI assigned to UE */
+ kal_bool sec_e_rnti_valid; /* Indicate if sec_e_rnti field is valid */
+ kal_uint16 sec_e_rnti; /* Secondary E-RNTI assigned to UE */
+} FDD_sec_e_rnti_info_T;
+
+typedef struct
+{
+ kal_uint16 ul_freq; /* UL UARFCN */
+ kal_uint16 dl_freq; /* DL UARFCN */
+ FDD_sc_type_E sc_type; /* Type of scrambling code */
+ kal_uint32 sc_code; /* Scrambling code #. 0 ~ 16777215 */
+ FDD_beta_ed_reduced_min_E beta_ed_reduced_min; /* Minimum reduced E-DPDCH gain factor.
+ If not configured in RRC message, SLCE should set the default value "FDD_beta_ed_8_15". */
+ kal_uint8 dpcch_po_SecondaryULFrequency; /* power offset. Integer (0..7 by step of 1) */
+ kal_uint8 pc_pream; /* Power control Preamble. 0 ~ 7 frames */
+} FDD_sec_edch_info_common_T;
+
+#define FDD_DC_HSUPA_ALL_CONFIG_BIT 0x7F
+
+typedef struct
+{
+ /*** mandatory configuration ***/
+ FDD_dc_hsupa_status_E dc_hsupa_status; /* variable to control UL1 DC-HSUPA receiving */
+ FDD_dc_hsupa_modify_type_E modify_type; /* DC-HSUPA modify type */
+ kal_int16 edch_serv_rscp; /* RSCP of secondary edch serving cell. Range: -464 ~ -100 dBm.
+ SLCE always sets RSCP value from DB_cell without comparison.*/
+ /*** optional configuration ***/
+ kal_uint8 config_field; /* Indicates the configured field:
+ Bit 0: sec_e_rnti_info
+ Bit 1: sec_edch_info_common
+ Bit 2: dl_dpch_rl_delete/dl_dpch_rl_add
+ Bit 3: edch_serv_psc
+ Bit 4: eagch_info
+ Bit 5: ehich_info
+ Bit 6: ergch_info
+ All field must be configured when switching DC-HSUPA OFF to ON. */
+ /* Bit 0: sec_e_rnti_info */
+ FDD_sec_e_rnti_info_T sec_e_rnti_info; /* [TS25.331]10.3.6.116 Secondary serving E-DCH cell info */
+ /* Bit 1: sec_edch_info_common */
+ FDD_sec_edch_info_common_T sec_edch_info_common; /* [TS25.331]10.3.6.117 Secondary E-DCH info common */
+ /* Bit 2: dl_dpch_rl_delete/dl_dpch_rl_add */
+ kal_uint8 dl_dpch_rl_delete_num; /* Number of RL to be removed: 0~FDD_MAX_EDCH_RL */
+ kal_uint16 dl_dpch_rl_delete[FDD_MAX_EDCH_RL]; /* RL to be removed (PSC) */
+ kal_uint8 dl_dpch_rl_add_num; /* Number of DL DPCH RL to be added: 0~FDD_MAX_EDCH_RL */
+ FDD_dl_dpch_rl_T dl_dpch_rl_add[FDD_MAX_EDCH_RL]; /* DL DPCH info. for each RL.
+ If modify_type != ASU, dl_dpch_rl_add is the full set of DL DPCH RL info. */
+ /* Bit 3: edch_serv_psc */
+ kal_uint16 edch_serv_psc; /* serving E-DCH cell */
+ /* Bit 4: eagch_info */
+ FDD_eagch_info_T eagch_info; /* E-AGCH info */
+ /* Bit 5: ehich_info */
+ kal_uint8 ehich_info_num; /* Number of E-HICH info: 1~FDD_MAX_EDCH_RL */
+ FDD_ehich_info_T ehich_info[FDD_MAX_EDCH_RL]; /* E-HICH info */
+ /* Bit 6: ergch_info */
+ kal_uint8 ergch_info_num; /* Number of E-RGCH info: 0~FDD_MAX_EDCH_RL */
+ FDD_ergch_info_T ergch_info[FDD_MAX_EDCH_RL]; /* E-RGCH info */
+
+} FDD_dc_hsupa_info_T;
+
+#endif /* __UMTS_R9__ */
+#endif /* __UMTS_R8__ */
+#endif /* __UMTS_R7__ */
+
+#if defined (__L1_STANDALONE__ )
+/*HsDsch check Interface*/
+typedef struct
+{
+ kal_bool is_hsscch_result_valid ; // need each tti hsscch result
+ kal_bool is_valid_data ; // need each tti hspdsch result
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint8 s_drx;// need each subframe number
+ kal_bool is_scheduled;//need each tti scheduling information
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ kal_bool is_in_gap; // is current tti is gap
+ kal_bool is_postpone;// is postpone condition
+ kal_uint8 ndi;// is new data or retransmission (1: new data, 0: retransmssion)
+
+} FDD_IF_HSDSCH_PARAM_T;
+typedef struct
+{
+ kal_bool is_valid_data;// need each tti result
+ kal_uint8 ag_value;// need each tti result
+ kal_uint8 ag_scope;// need each tti result
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint8 s_drx;// need each subframe number
+ kal_bool is_tti_2ms;// need each tti result
+ kal_bool is_scheduled;//need each tti scheduling information
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ kal_bool is_in_gap;// is current tti is gap ,current test is without gap
+ FDD_edch_scell_E ecell_type;
+} FDD_IF_EAGCH_PARAM_T;
+typedef struct
+{
+ kal_uint8 e_rgch_result_serving; // need each tti result
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint8 s_drx;// need each subframe number
+ kal_bool is_tti_2ms;// need each tti result
+ kal_bool is_scheduled;// need each tti result
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ kal_bool is_in_gap;// is current tti is gap, current test is without gap
+ FDD_edch_scell_E ecell_type;
+} FDD_IF_ERGCH_PARAM_T;
+typedef struct
+{
+
+ kal_uint8 cfn_drx;//need each cfn number
+ kal_uint16 scheduled_bimap;//need each slot result
+ kal_bool is_ul1d_start_check;//if UL1D apply DRX, the flag shall be enabled, otherwise disabled.
+ FDD_edch_scell_E ecell_type;
+
+} FDD_IF_ULDPCCH_PARAM_T;
+#endif /*__L1_STANDALONE__*/
+
+typedef enum
+{
+ RAS_INVALID,
+ RAS_PATH_MAIN,
+ RAS_PATH_BOTH
+} RAS_PATH_T;
+
+typedef enum
+{
+ CS_PS_INVALID,
+ CS_ONLY,
+ CS_PS_BOTH,
+ PS_ONLY
+} FDD_IS_CS_PS;
+
+typedef struct
+{
+ kal_uint8 numElements;
+ kal_uint8 elements[NUM_MCC_MNC];
+} FDD_MCC_MNC_T;
+
+typedef struct
+{
+ FDD_MCC_MNC_T mcc;
+ FDD_MCC_MNC_T mnc;
+} FDD_PLMN_IDENTITY_T;
+
+typedef struct
+{
+ kal_uint8 cell_plmn_num;
+ FDD_PLMN_IDENTITY_T cell_plmn_info[NUM_PLMN_INFO];
+ kal_uint16 lac;
+ kal_uint16 rac;
+ kal_int16 cellidx;
+} FDD_PLMN_LAC_PARAM_T;
+typedef struct
+{
+ kal_uint8 radio_bearer_ID;
+ kal_uint32 rx_window_size;
+} FDD_RLC_WINDOW_SIZE_INFO_T;
+
+#endif