[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/interface/service/prbm/dpcopro_custom.h b/mcu/interface/service/prbm/dpcopro_custom.h
new file mode 100644
index 0000000..6b1d3d7
--- /dev/null
+++ b/mcu/interface/service/prbm/dpcopro_custom.h
@@ -0,0 +1,318 @@
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * dpcopro_custom.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * Copro & VRB related API released for Customer
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 09 23 2019 yi-chih.tsai
+ * [MOLY00442844] [Gen97] Add new key_idx for NR CM+IM security configuration
+ * .1. add key for no cipher 2. add log for control packet
+ *
+ * 12 10 2018 yi-chih.tsai
+ * [MOLY00366485] [MT6297][KS IODT EVB] 4G cipher of DRB problem
+ * .modify for EN-DC
+ *
+ * 11 14 2018 yi-chih.tsai
+ * [MOLY00364111] [MT6297][Apollo][Sanity Fail][20181112][NR RRC Reconfiguration] Assert fail: dpcopro_hisr.c 713 - (LISR)mml2_excep_lisr
+ * .sync cipher driver
+ *
+ * 03 30 2018 chia-chi.hsiao
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * .fix chip gen compile flag
+ *
+ * 02 13 2018 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * Enhance DMA trigger flow for reduce mask interrupt duration
+ *
+ * 01 25 2018 chi-yen.yu
+ * [MOLY00299272] [MT6763][Bianco][O1][MP2][TMO][MTBF][PHONE][HQ][Lab][Ericsson][Fatal error(task)] err_code10x00000B34 err_code20x90284CA1 err_code30xCCCCCCCC CaDeFa Supported
+ * For IPCore customer release
+ *
+ * 11 13 2017 chao-hung.hsu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * . 95 DEV code merge
+ *
+ * 11 13 2017 chao-hung.hsu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * . dpcopro 95 DEV code sync back to R3/TRUNK
+ *
+ * 09 01 2017 yi-chih.tsai
+ * [MOLY00274580] [MT6293][SMO- source code release] remove unnecessary include header file
+ * .copy ctrl pkt and key API to customer header
+ *
+ * 08 09 2017 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * Add API declare for cursomer release
+ *
+ * 04 13 2017 chi-yen.yu
+ * [MOLY00240758] [Bianco][N1][Blocking]Externel (EE),0,0,99,/data/core/,1,modem,
+ * For customer release
+****************************************************************************/
+#ifndef __DPCOPRO_CUSTOM_H__
+#define __DPCOPRO_CUSTOM_H__
+
+enum{
+VRB_USER_TX_LISR, // EMAC Module
+VRB_USER_ERT_TASK, // EMAC Module
+VRB_USER_EMACDL_TASK, // EMAC/ERLCUL Module
+VRB_USER_UL2_TASK, // 3G L2 module, high priority
+VRB_RTBL_NUM,
+VRB_USER_USBCORE_TASK=VRB_RTBL_NUM, // USB Core
+VRB_USER_IPCORE_TASK, // IPCore Module
+VRB_USER_LHIF_TASK, // LHIF Core
+VRB_USER_EL2H_TASK, // EL2H Module
+VRB_USER_EL2_TASK, // EL2 Module
+VRB_USER_ERRC_TASK, // ERRC Module (for SRB)
+VRB_USER_IMC_TASK, // LTE CSR Module
+VRB_USER_UL2D_TASK, // 3G L2 module, lower priority than UL2 Task
+//VRB_USER_L1_LISR, // 3G UL module, not used by 3G user
+VRB_USER_NUM
+};
+
+void copro_vrb_release(void* addr, kal_uint16 len, kal_uint8 task_id);
+void dpcopro_phy_to_vrb_mem_cpy(kal_uint8 *des_vrb_addr, kal_uint8 *src_addr, kal_uint32 len);
+typedef struct{
+ kal_uint32 v_addr;
+ kal_uint32 p_addr[5];
+ kal_uint16 v_len;
+ kal_uint16 p_len[5];// use 3 phy len for structure align
+}v2p_addr_t;
+kal_uint16 copro_vrb_to_phy_addr(v2p_addr_t *v2p);
+void dpcopro_vrb_copy(kal_uint8 *des, kal_uint8 *src, kal_uint32 len);
+
+//---------- L2 Key setting API ------------
+//!@brief cipher and integrity algorithm list
+typedef enum{
+ L2_ALGO_NULL = 0,
+ L2_ALGO_KASUMI,
+ L2_ALGO_SNOW3G,
+ L2_ALGO_AES,
+ L2_ALGO_ZUC
+}l2_key_algo;
+
+//!@brief key type list
+typedef enum{
+ //3G, 4G key
+ L2_KEY_NULL = 0,
+ L2_KEY_NRRC_ENC_MIRROR,
+ L2_KEY_NRRC_INT_MIRROR,
+ L2_KEY_NUP_ENC_MIRROR,
+ L2_KEY_NUP_INT_MIRROR,
+ L2_KEY_ERRC_ENC,
+ L2_KEY_ERRC_INT,
+ L2_KEY_EUP_ENC,
+ L2_KEY_EUP_S_ENC,
+ L2_KEY_ENAS_ENC,
+ L2_KEY_ENAS_INT,
+ L2_KEY_UUP_ENC1,
+ L2_KEY_UUP_ENC2,
+ L2_KEY_UUP_ENC3,
+ L2_KEY_UUP_ENC4,
+ L2_KEY_UUP_ENC5,
+ //5G key type
+ L2_KEY_NR_NULL,
+ L2_KEY_NRRC_ENC,
+ L2_KEY_NRRC_INT,
+ L2_KEY_NUP_ENC,
+ L2_KEY_NUP_INT,
+ L2_KEY_ERRC_ENC_MIRROR,
+ L2_KEY_ERRC_INT_MIRROR,
+ L2_KEY_EUP_ENC_MIRROR,
+ L2_KEY_NUP_NULL_FOR_CIPHER_DISABLED,
+ L2_KEY_NUP_INT_MIRROR_FOR_CIPHER_DISABLED
+}l2_key_type;
+
+//!@brief the key configuration struct
+typedef struct l2_key_cfg_t{
+ kal_uint32 algo;
+ kal_uint8 key[16];
+} l2_key_cfg;
+
+/*!
+ * @brief get key index by key type
+ * @param type: key type
+ * @return key index
+ */
+kal_uint32 l2_key_get_index(kal_uint32 type);
+
+/*!
+ * @brief get key configuration by key index
+ * @param key_idx: the key index, which get from "l2_key_get_index" or "l2_key_set_config"
+ * @param cfg: the key configuration info
+ * @return 0: failure, 1: success
+ */
+kal_uint32 l2_key_get_config(kal_uint32 key_idx, l2_key_cfg* cfg);
+
+/*!
+ * @brief set key and algorithm by key type
+ * single key: sw need to make sure hw don't use it
+ * dual key : driver will set another key index
+ * @param type: key type
+ * @param cfg: the key configuration info
+ * @return key index for key select
+ */
+kal_uint32 l2_key_set_config(kal_uint32 type, l2_key_cfg* cfg);
+
+//------- the control packet queue API -------
+//!@brief the arguments for integrity function
+typedef struct l2_cp_eia_info_t{
+ kal_uint8 dir;
+ kal_uint8 bearer;
+ kal_uint16 length;
+ kal_uint32 count;
+ kal_uint8* src_addr;
+ kal_uint8* dst_addr;
+}l2_cp_eia_info;
+
+//!@brief the arguments for cipher function
+typedef l2_cp_eia_info l2_cp_eea_info;
+
+/*!
+ * @brief Do integrity for ENAS. (task only!!!)
+ * This function will block task until HW done.
+ * @param nas: integrity parameters info
+ */
+void l2_cp_int_enas(l2_cp_eia_info *nas);
+
+/*!
+ * @brief Do cipher for ENAS. (task only!!!)
+ * This function will block task until HW done.
+ * @param nas: cipher parameters info
+ */
+void l2_cp_cip_enas(l2_cp_eea_info *nas);
+
+/*!
+ * @brief Do integrity for ERRC.(task only!!!)
+ * This function will block task until HW done
+ * @param rrc: integrity parameters info
+ * @param gen_hdr: if gen_hdr = 1, driver will generate pdcp header by count
+ */
+void l2_cp_int_errc(l2_cp_eia_info *rrc, kal_uint32 gen_hdr);
+
+/*!
+ * @brief Generate PDCP header and do integrity for EPDCP.(task only!!!)
+ * This function DON'T block task, SW need to poll "handle id" by itself
+ * @param pdcp: integrity parameters info
+ * @return handle id
+ */
+kal_uint32 l2_cp_int_epdcp(l2_cp_eia_info *pdcp, kal_uint32 key_index);
+
+/*!
+ * @brief Check that HW is done or not
+ * @param handle: handle id which is got from "l2_cp_int_epdcp"
+ * @return 0: undone, 1: done
+ */
+kal_uint32 l2_cp_is_hid_done(kal_uint32 handle);
+
+/*!
+ * @brief Check that HW is done and get mac_i
+ * @param handle: handle id which is got from "l2_cp_int_epdcp"
+ * @return 0: undone, 1: done
+ */
+kal_uint32 l2_cp_int_pdcp_get_maci(kal_uint32 handle, kal_uint32 *p_maci);
+
+//!@brief the arguments for cipher function
+typedef struct l2_cp_uea_info_t{
+ kal_uint8 dir:1;
+ kal_uint8 key_type:7;
+ kal_uint8 bearer;
+ kal_uint16 length;
+ kal_uint32 count;
+ kal_uint8* src_addr;
+ kal_uint8* dst_addr;
+}l2_cp_uea_info;
+
+/*!
+ * @brief Do cipher for 3G Lisr.
+ * This function will block Lisr until HW done.
+ * @param uea: cipher parameters info
+ */
+void l2_cp_cip_3g_lisr(l2_cp_uea_info *uea);
+
+void dpcopro_rbuf_release(void *addr,kal_uint16 len);
+
+typedef enum{
+ UL_IPF_META_MR_HPC_MATCH=0,
+ UL_IPF_META_MR_HPC_NEW,
+ UL_IPF_META_MR_NAT_MATCH,
+ UL_IPF_META_MR_NAT_MATCH_NO_TRAN,
+ UL_IPF_META_MR_NAT_DEL_MATCH,
+ UL_IPF_META_MR_NAT_DEL_NO_MATCH,
+ UL_IPF_META_MR_NAT_ADD,
+ UL_IPF_META_MR_UNKNOWN,
+ UL_IPF_META_MR_NUM
+}UL_IPF_META_MR;
+
+typedef enum{
+ DL_IPF_META_MR_AP=0,
+ DL_IPF_META_MR_FILTER_MATCH,
+ DL_IPF_META_MR_UNKNOWN,
+ DL_IPF_META_MR_NET_INVALID,
+ DL_IPF_META_MR_PN_NO_MATCH,
+ DL_IPF_META_MR_NAT_MATCH,
+ DL_IPF_META_MR_NAT_NO_MATCH,
+ DL_IPF_META_MR_NAT_MATCH_NO_TRAN,
+ DL_IPF_META_MR_NUM
+}DL_IPF_META_MR;
+
+typedef struct ipv4_filter_rule_t{
+ kal_uint8 pdn_sim_id;
+ kal_uint8 protocol;
+ kal_uint8 valid;
+ kal_uint8 resv0:4;
+ kal_uint8 ip:4;
+ kal_uint32 f_pro_word;
+ kal_uint32 remote_addr0;
+ kal_uint32 resv1;
+}ipv4_filter_rule;
+
+typedef struct ipv6_filter_rule_t{
+ kal_uint8 pdn_sim_id;
+ kal_uint8 protocol;
+ kal_uint8 valid;
+ kal_uint8 resv0:4;
+ kal_uint8 ip:4;
+ kal_uint32 f_pro_word;
+ kal_uint32 remote_addr0;
+ kal_uint32 resv1;
+ kal_uint32 resv2:28;
+ kal_uint32 ip1:4;
+ kal_uint32 remote_addr1;
+ kal_uint32 remote_addr2;
+ kal_uint32 remote_addr3;
+}ipv6_filter_rule;
+
+typedef struct ipf_dl_meta_t{
+ kal_uint16 count;
+ kal_uint8 channel_id;
+ kal_uint8 net_type:3;
+ kal_uint8 resv:5;
+ kal_uint16 len;
+ kal_uint8 rbid;
+ kal_uint8 pdn_sim_id;
+ kal_uint32 addr;
+ kal_uint8 match_idx;
+ kal_uint8 mr:3;
+ kal_uint8 rsv0:1;
+ kal_uint8 ip:1;
+ kal_uint8 fil_tog:2;
+ kal_uint8 rsv1:1;
+ kal_uint8 tcp_flag;
+ kal_uint8 filter_idx;
+}ipf_dl_meta;
+
+#endif
diff --git a/mcu/interface/service/prbm/prbm.h b/mcu/interface/service/prbm/prbm.h
new file mode 100644
index 0000000..4f2f512
--- /dev/null
+++ b/mcu/interface/service/prbm/prbm.h
@@ -0,0 +1,379 @@
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * prbm_conf.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * PRBM configuration header file
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 10 2020 wen-zhi.huang
+ * [MOLY00591398] [MT6833][Palmer][Q0][MP7][SQC][Log profiling] SA DL 2CC profiling
+ * [SA DL 2CC profiling] Copro log reduction
+ *
+ * 06 29 2020 wen-zhi.huang
+ * [MOLY00536882] [MDFPM] Dynamic switch check in
+ * log reduction for MDDP-WH
+ *
+ * 03 25 2020 chi-yen.yu
+ * [MOLY00507144] [MT6875][Margaux][Q0][MP3][SQC][China][Kunming][5GMM][NSA][Internal][FT][CT][IS:CT][Static][NSA_Self-Cer_FT_01_026][ASSERT]file:dsp3/coresonic/msonic/modem/brp/nr/nr_brp/src/nr_brp_top_irq.c line:925
+ * For log reduction
+ *
+ * 09 18 2019 chi-yen.yu
+ * [MOLY00437845] [Gen97][SMO][UTF2.5] Please move out trace from dpcopro_internal.h
+ * Increase UL USB PRB size
+ * .
+ *
+ * 07 30 2019 wen-zhi.huang
+ * [MOLY00423298] [MDDP][GEN97] patch back MDDP-WH
+ * .merge MDDPWH code to VMOLY TRUNK
+ *
+ * 07 04 2019 chi-yen.yu
+ * [MOLY00396869] [MODIS HW Copro] Work on making Modis to run with ESL HW models and Uplane with ESL
+ * Fix build error
+ *
+ * 07 04 2019 chi-yen.yu
+ * [MOLY00396869] [MODIS HW Copro] Work on making Modis to run with ESL HW models and Uplane with ESL
+ * Add compile flag for DPMAIF PRB
+ *
+ * 06 26 2019 chi-yen.yu
+ * [MOLY00396869] [MODIS HW Copro] Work on making Modis to run with ESL HW models and Uplane with ESL
+ * Add IMS PRB type
+ *
+ * 05 09 2019 hsin-hao.huang
+ * [MOLY00401354] [MT6297][Phone Call][NSA FullStack][Huawei][Shanghai][5G][VMOLY]Assert fail: el2_sec_utility.c 327 - IPCORE
+ * .LHIF/DPMAIF reorder ehance interface
+ *
+ * 10 08 2018 chi-yen.yu
+ * [MOLY00344818] NRL2 merge back to VMOLY
+ * Add PRBM type for 97 DPMAIF USB
+ *
+ * 10 04 2018 chi-yen.yu
+ * [MOLY00328022] GEN97 NRL2 driver build error
+ * Refine inline usage
+ *
+ * 09 27 2018 chi-yen.yu
+ * [MOLY00344818] NRL2 merge back to VMOLY
+ * Merge back from UMOLYE truck
+ *
+ * 09 18 2018 chi-yen.yu
+ * [MOLY00344818] NRL2 merge back to VMOLY
+ * Fix code gen error
+ *
+ * 08 20 2018 wen-zhi.huang
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * [VMOLY] merge driver code back with UMOLYE.TRUNK & 97.DEV
+ *
+ * 08 15 2018 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * .
+ *
+ * 08 08 2018 chi-yen.yu
+ * [MOLY00328022] GEN97 NRL2 driver build error
+ * Patch for NRL2 DVT
+ *
+ * 08 07 2018 chi-yen.yu
+ * [MOLY00328022] GEN97 NRL2 driver build error
+ * Patch cache operation API for VRB
+ *
+ * 07 24 2018 chi-yen.yu
+ * [MOLY00328022] GEN97 NRL2 driver build error
+ * Add PRB DL DPMAIF
+ *
+ * 05 24 2018 chi-yen.yu
+ * [MOLY00328022] GEN97 NRL2 driver build error
+ * Fix build error
+ *
+ * 04 11 2018 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * Extend VRB release to support 32bit length
+ *
+ * 03 20 2018 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * Patch for 95 MML2 router DVT test
+ *
+ * 03 09 2018 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * Integrate 95 MML2 router DVT related test
+ *
+ * 02 13 2018 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * Enhance DMA trigger flow for reduce mask interrupt duration
+ *
+ * 11 13 2017 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * Merge from 95 DEV branch
+ *
+ * 11 13 2017 chao-hung.hsu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * . dpcopro 95 DEV code sync back to R3/TRUNK
+ *
+ * 11 10 2017 wei-hao.kuo
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * Enable PRB_TYPE_DL_USB for _HIF_USB_SUPPORT_ load
+ *
+ * 08 21 2017 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * Reduce PRBM size for MT6739
+ *
+ * 08 16 2017 chi-yen.yu
+ * [MOLY00179693] [Bianco_SMT][Bianco Bring-up]MT6293 Copro driver integration
+ * PRBM full recover
+ *
+ * 07 20 2017 chi-yen.yu
+ * [MOLY00179693] [Bianco_SMT][Bianco Bring-up]MT6293 Copro driver integration
+ * Merge UMOLYA TRUCK code to R2
+ *
+ * 07 17 2017 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * Merege 95 MML2 driver to truck
+ *
+ * 07 13 2017 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * .
+ *
+ * 06 29 2017 chi-yen.yu
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * Port for 95 FPGA
+ *
+ * 03 06 2017 chi-yen.yu
+ * [MOLY00226321] [6293]DCM & Sleep Flow Integration and Verification
+ * .
+ *
+ * 03 06 2017 chi-yen.yu
+ * [MOLY00232231] [MT6763_234G_Sanity]93 DPCOPRO driver integration
+ * .
+ *
+ * 03 02 2017 chi-yen.yu
+ * [MOLY00232231] [MT6763_234G_Sanity]93 DPCOPRO driver integration
+ * .
+ *
+ * 01 20 2017 chao-hung.hsu
+ * [MOLY00226032] [Bianco Bring-up][DPCopro]
+ * . driver porting
+ *
+ * 01 10 2017 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 10 31 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 10 06 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 09 13 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 09 07 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 08 24 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 08 09 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 08 05 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 07 19 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 07 12 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 07 11 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 06 30 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 06 07 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+ * 05 25 2016 chi-yen.yu
+ * [MOLY00179693] MT6293 Copro driver integration
+ * .
+ *
+****************************************************************************/
+#ifndef __PRBM_H__
+#define __PRBM_H__
+
+#ifndef __MTK_TARGET__
+#define inline
+#endif
+
+typedef struct{
+ kal_uint32 prb_base;
+ kal_uint32 prb_size;
+ kal_uint16 prb_page_num;
+ kal_uint8 prb_id;
+ kal_uint8 prb_wrap_buf_unit;// unit:128 bytes
+ kal_uint32 prb_alloc_align:4;//0: no-align, 1: 2 byte align, 2: 4 byte align, 3: 8 align,...,5: 32 byte align,6: 64 byte align
+ //prb_psize_cfg:0 => page size= 16 byte
+ //prb_psize_cfg:1 => page size= 32 byte
+ //prb_psize_cfg:2 => page size= 64 byte
+ //prb_psize_cfg:3 => page size= 128 byte
+ //...
+ //prb_page_size:N => page size= 2^(4+prb_psize_cfg) byte
+ kal_uint32 prb_psize_cfg:4;
+ //when no_seq_rel=0, PRB is sequence release,
+ //When no_seq_rel=1, PRB is no-sequence release,
+ kal_uint32 rel_type:4;
+ kal_uint32 wrap_full_cover:1;
+ kal_uint32 multi_task_aloc:1;
+ kal_uint32 resv:18;
+}prbm_config_t;
+
+typedef enum
+{
+ PRB_TYPE_UL_ROHC=0,
+ PRB_TYPE_DL_ROHC,
+ PRB_TYPE_DL_IPHC,
+ PRB_TYPE_DL_CIPHER_META,
+ PRB_TYPE_DL_IP_FRAG, // 4
+ //=====start of HW PRB
+ PRB_TYPE_AP_UL_Q1,
+ PRB_TYPE_SHARE,
+#ifndef __MD93__
+ PRB_TYPE_DL_IPF,
+#endif
+#if !defined(__MD93__) && !defined(__TEMP_MDDP_WH_SUPPORT__)
+ PRB_TYPE_DL_NAT_SHRAM,
+#endif
+#ifdef ATEST_DPCOPRO_EN
+ PRB_TYPE_DPC_UT_CFG,
+#endif
+ //Due to only MODEM only load has MODEM USB function
+ //only enable DL USB buffer in MODEM only load
+//#ifdef __MODEM_ONLY__
+//L1S_L1DISABLE also has MODEM USB function. PRB_TYPE_DL_USB is needed as long as __HIF_USB_SUPPORT__ is defined.
+ PRB_TYPE_IMS,
+#ifdef __HIF_USB_SUPPORT__
+ PRB_TYPE_DL_USB,
+#endif
+#ifdef __MD97__
+ PRB_TYPE_DL_LHIF,
+ PRB_TYPE_DL_DPMAIF,
+#endif
+ PRB_TYPE_AP_UL_ACK,
+#ifdef __HIF_DPMAIF_DP_SUPPORT__
+ PRB_TYPE_DL_DPMAIF_BAT,
+ PRB_TYPE_DL_DPMAIF_FRAGBAT,
+#endif
+#ifdef __TEMP_MDDP_WH_SUPPORT__
+#if defined(__MDDP_USB_SUPPORT__) || defined(__MDDP_WH_SUPPORT__)
+ PRB_TYPE_DL_NAT_SHRAM,
+#endif
+#endif
+ PRB_TYPE_NUM
+}prbm_type;
+
+// PRB_TYPE_UL_IPHC, // not used in 2/3G
+// PRB_TYPE_DL_FLC, // not used in 2/3G
+
+enum{
+PRB_PSIZE_CFG_16=0,
+PRB_PSIZE_CFG_32,
+PRB_PSIZE_CFG_64,
+PRB_PSIZE_CFG_128,
+PRB_PSIZE_CFG_256,
+PRB_PSIZE_CFG_512,
+PRB_PSIZE_CFG_1024,
+PRB_PSIZE_CFG_2048,
+PRB_PSIZE_CFG_4096,
+PRB_PSIZE_CFG_NUM,
+};
+
+enum{
+PRB_ALLOC_ALIGN_1=0,
+PRB_ALLOC_ALIGN_2,
+PRB_ALLOC_ALIGN_4,
+PRB_ALLOC_ALIGN_8,
+PRB_ALLOC_ALIGN_16,
+PRB_ALLOC_ALIGN_32,
+PRB_ALLOC_ALIGN_64,
+PRB_ALLOC_ALIGN_NUM,
+};
+
+enum{
+PRB_REL_TYPE_SEQ=0,
+PRB_REL_TYPE_NOSEQ,
+PRB_REL_TYPE_HW_ALOC,
+PRB_REL_TYPE_NUM,
+};
+#define PRB_FULL_RESERVE_SIZE 4
+#define PRBM_INIT_REM_SIZE(_prb_size) ((_prb_size)-PRB_FULL_RESERVE_SIZE)
+#define PRBM_WRAP_BUF_UNIT (128)
+#define PSZIE_CFG_BIT_NUM(psize_cfg) ((kal_uint32)(psize_cfg)+4)
+#define PSIZE_CFG_SIZE(psize_cfg) (1<<PSZIE_CFG_BIT_NUM(psize_cfg))
+//#define PRB_GET_MEM_SIZE(P_SIZE,P_NUM, REL_TYPE) (PSIZE_CFG_SIZE(P_SIZE)*P_NUM)+(REL_TYPE*(sizeof(kal_uint16)*P_NUM))
+#define PRBM_PT_SIZE(P_NUM) (sizeof(kal_uint16)*(P_NUM))
+#define PRB_GET_MEM_SIZE(PAGE_SIZE_CFG,WRAP_SIZE_CFG,PAGE_NUM, REL_TYPE) ((PSIZE_CFG_SIZE(PAGE_SIZE_CFG)*(PAGE_NUM))+(WRAP_SIZE_CFG*PRBM_WRAP_BUF_UNIT)+((REL_TYPE>0)*PRBM_PT_SIZE(PAGE_NUM)))
+
+typedef kal_uint32(*HW_ALOC_OFS_CB)(void);//CB function to get write offset for HW ALLOC type
+typedef kal_uint32(*HW_ADD_REM_SIZE_CB)(kal_uint32);//CB function to add remain buffer size to HW & return current remain buffer size
+
+void _do_prbm_output_rel_merge_log(void);
+kal_bool prbm_get_def_cfg(prbm_config_t *cfg,kal_uint8 prbm_id);
+kal_bool prbm_set_def_cfg(prbm_config_t *cfg,kal_uint8 prbm_id);
+kal_uint32 prbm_get_def_mem_size(kal_uint8 prbm_id);
+void prbm_get_cfg(prbm_config_t *cfg,kal_uint8 prb_id);
+void prbm_get_cfg_for_hw_aloc_type(prbm_config_t *cfg,HW_ALOC_OFS_CB aloc_cb,HW_ADD_REM_SIZE_CB add_rem_size_cb,kal_uint8 prb_id);
+void prbm_init_cfg(prbm_config_t *prbm_cfg,HW_ALOC_OFS_CB wofs_cb,HW_ADD_REM_SIZE_CB add_rem_size_cb,kal_uint8 prbid);
+
+void prbm_reconfig(kal_uint32 base_addr,kal_uint32 size,kal_uint8 page_size_cfg,kal_uint32 page_num_unit,kal_uint32 max_pkt_size,kal_uint8 rel_type,kal_uint8 prbm_id);
+
+void prbm_init(void);
+kal_uint8* prbm_get_base(kal_uint8 prb_id);
+kal_uint8* prbm_allocate(kal_uint32 aloc_size, kal_uint8 prb_id);
+kal_uint32 prbm_release(void* addr, kal_uint32 rel_size, kal_uint8 prb_id);
+kal_uint32 prbm_get_remain_size(kal_uint8 prb_id);
+kal_uint32 prbm_get_alloc_size(kal_uint8 prb_id);
+kal_bool prbm_check_region(kal_uint32 addr, kal_uint32 len,kal_uint8 prb_id);
+#ifdef __TEMP_MDDP_WH_SUPPORT__
+kal_uint32 prbm_get_rel_ofs(kal_uint8 prb_id);
+#endif
+
+//in order to make packet in end of buffer in PRBM to be continuously
+//copy data from base of PRBM to wrap buffer region
+kal_bool prbm_wrap_buf_handle(kal_uint8 *pkt_addr, kal_uint16 pkt_len,kal_uint8 prb_id,kal_uint8 hw_write);
+
+typedef struct{
+ kal_uint32 buf_add_size:24;
+ kal_uint32 prbm_id:7;
+ kal_uint32 do_rel:1;
+}PRBM_TRY_REL_T;
+PRBM_TRY_REL_T _prbm_try_release(kal_uint32 addr, kal_uint32 rel_size);
+
+
+typedef kal_bool (*prb_rel_cb_t)(void*, kal_uint32);
+kal_uint8* prbm_usb_init(prb_rel_cb_t rel_cb);
+void prbm_wifi_init(prb_rel_cb_t rel_cb);
+
+#define PRB_SIZE_UL_USB (1*1024*1024)
+#endif