[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/protocol/interface/el2/errc_emac_msg.h b/mcu/protocol/interface/el2/errc_emac_msg.h
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+++ b/mcu/protocol/interface/el2/errc_emac_msg.h
@@ -0,0 +1,922 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * errc_emac_msg.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * Define ERRC EMAC interface enums, structures and constants
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 01 2018 sc.tung
+ * [MOLY00361478] [Gen97] Gemini Compile Option Clean Up
+ *
+ * [el2][emac] Gemini compiler option clean up.
+ *
+ * 07 31 2018 guang-yu.zheng
+ * [MOLY00342112] [MT6295] ERRC-EMAC interface extend for RA/TA configuration (UL2CC->3CC)
+ * Add back legacy interface for xl1sim flow
+ *
+ * 07 27 2018 guang-yu.zheng
+ * [MOLY00342112] [MT6295] ERRC-EMAC interface extend for RA/TA configuration (UL2CC->3CC)
+ * RA/TA interface extenstion for 3CC
+ *
+ * 06 14 2018 tina-yt.wang
+ * [MOLY00333176] [ICD] stage1+stage2 ICD UMOLYE CBr patch back to LR13.R0
+ * [EL2ICD] EMAC ERT related part
+ *
+ * 06 11 2018 jia-shi.lin
+ * [MOLY00319373] [MT6295] recommended bit rate feature
+ * recommended bit rate feature: txlisr and emac design
+ *
+ * 06 05 2018 guang-yu.zheng
+ * [MOLY00331352] [MT6295] EL2 MML2 DVFS control development
+ * Add CAT16 support for MML2 DVFS Control
+ *
+ * 04 11 2018 jia-shi.lin
+ * [MOLY00319373] [MT6295] recommended bit rate feature
+ * recommended bit rate feature: errc-emac interface
+ *
+ * 04 10 2018 nicole.hsu
+ * [MOLY00314955] [Gen 95][ERRC][RCM] MP1 capability config
+ * [UMOLYE TRUNK] add RBR_enable to ERRC-EMAC interface
+ *
+ * 03 19 2018 guang-yu.zheng
+ * [MOLY00313850] [MT6295] MML2 DVFS control feature development
+ * MML2 DVFS control and MCU DVFS re-org
+ *
+ * 02 26 2018 wen-jiunn.liu
+ * [MOLY00279230] [93/95 re-arch] Gen95 Development
+ * [EMAC][ERRC] Interface for PUSCH Enhancement Mode
+ *
+ * 01 11 2018 jia-shi.lin
+ * [MOLY00301451] [SMO release][93/95]EL1 relative interface
+ * emac/el1 interface re-arch
+ *
+ * 09 20 2017 nicole.hsu
+ * [MOLY00279184] [PCT][Anritsu][CAG50C][E40][7.1.1.2] fail
+ * [TRUNK] LCID vs. support release handling
+ *
+ * 08 16 2017 guang-yu.zheng
+ * [MOLY00271123] [MT6293][EMAC] SRLTE-enhance feature code sync
+ * Add EMAC interface for SRLTE enhancement handling
+ *
+ * 01 25 2017 eddie.wang
+ * [MOLY00210650] [MT6293][UMOLYA TRUNK] EMAC maintenance
+ * [MSIM][RSIM] Add emac config req cause for remote sim scenario
+ *
+ * 12 26 2016 mf.jhang
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * update errc_emac_ca_activate_ind_struct
+ *
+ * 11 08 2016 mf.jhang
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * Update errc_emac_ca_activate_ind_struct
+ *
+ * 10 06 2016 eddie.wang
+ * [MOLY00206522] [MT6293][NWSIM][Regression][TC_7_1_4_18] Test failed
+ * TRUNK:Remove redundant config like extendedBSR and MBMS in emac_config_req
+ *
+ * 09 13 2016 nicole.hsu
+ * [MOLY00194987] [MT6293][UMOLYA/PS DEV] EMAC maintenance
+ * [xL1Sim] remove errc_emac_config old field - tti_bundling_flag
+ *
+ * 03 16 2016 yk.liu
+ * [MOLY00165181] Syn EMAC from LR11 TO UMOLY for CL1990358
+ * .
+ *
+ * 03 15 2016 ryan.ou
+ * [MOLY00162291] [MT6292] EMAC code sync from LR11 to UMOLY
+ * CL1867764, [MOLY00151000] [MT6755] SRVCC Enhancement.
+ *
+ * 01 11 2016 ville.pukari
+ * [MOLY00156411] [MT6292] Logical Channel SR prohibit timer: New feature
+ *
+ * 10 16 2015 panu.peisa
+ * [MOLY00145084] DE6 code merge from UMOLY_92dev CBr to UMOLY trunk
+ * Integrated LTE_SEC changes from UMOLY_92dev ( errc part ).
+ *
+ * 10 06 2015 esko.oikarinen
+ * ERRC changes for multiple TA
+ *
+ * 09 10 2015 chun-fan.tsai
+ * [MOLY00098400] [6291] eRRC CONN EM
+ * Add CCCH Data Req cause for EMAC EM
+ *
+ * 03 18 2015 chen-wei.wang
+ * [MOLY00099525] [TK6291] EMAC MDT feature check-in
+ * interface file check-in
+ *
+ * 12 03 2014 sh.yang
+ * [MOLY00084081] [UMOLY] Trunk merge back
+ * .Add carrier index in si_ind_struct
+ *
+ * 11 11 2014 yiting.cheng
+ * [MOLY00084042] [UMOLY] merge UMOLY_DEV to UMOLY trunk
+ * .
+ *
+ * 10 08 2014 henry.lai
+ * [MOLY00079071] [MT6291][U4G] Low Power Modification for CEL Paging
+ * .
+ *
+ * 09 19 2014 chi-chung.lin
+ * [MOLY00073836] [MT6291][ERRC][CHM] LTE-A CHM development code check-in
+ * [CHM] MBMS interface check in
+ *
+ * 07 28 2014 yiting.cheng
+ * [MOLY00073830] [MT6291_DEV] check-in MT6291 modification
+ * Check-in EMAC-ERRC interface
+ *
+ * 08 06 2013 stanleyhy.chen
+ * [MOLY00032633] 4G Nbr Cell Info
+ * 4G Nbr Cell Info in LTE Domain
+ *
+ * 07 22 2013 stanleyhy.chen
+ * [MOLY00029602] [New Feature] NBR_CELL_INFO and TA_INFO related interfaces
+ * Add ERRC_EMAC_TA_INFO_INVALID_IND
+ *
+ * 07 12 2013 stanleyhy.chen
+ * [MOLY00029602] [New Feature] NBR_CELL_INFO and TA_INFO related interfaces
+ * TA_INFO and NBR_CELL_INFO interfaces for LPP feature
+ ****************************************************************************/
+
+#ifndef ERRC_EMAC_MSG_H
+#define ERRC_EMAC_MSG_H
+
+
+#include "kal_public_api.h"
+#include "el2_sap_common.h"
+#include "qmu_bm.h"
+#include "lte_time_common.h"
+#include "common_def.h"
+
+#if !defined(__XL1SIM_EL1__) && defined(__LTE_L1SIM__)
+#define __XL1SIM_EL1__
+#endif
+////////////////////////////////////////////////////////////////
+// MAC configuration request
+////////////////////////////////////////////////////////////////
+
+//mac config request info bitmap
+#define EMAC_CONFIG_INFO_RA_MASK 0x01
+#define EMAC_CONFIG_INFO_SCHED_MASK 0x02
+#define EMAC_CONFIG_INFO_DRX_MASK 0x04
+#define EMAC_CONFIG_INFO_PHR_MASK 0x08
+#define EMAC_CONFIG_INFO_CRNTI_MASK 0x10
+
+#define ERRC_EMAC_CCCH_SZ (6)
+
+//max number of RB
+#define ERRC_EMAC_MAX_RB_NB (10)
+
+//max number of STAG/SCell
+#if(CUR_GEN >= MD_GEN95)
+#define ERRC_EMAC_MAX_STAG_NB (1)
+#define ERRC_EMAC_MAX_SCELL_NB (3)
+#else
+#define ERRC_EMAC_MAX_STAG_NB (1)
+#define ERRC_EMAC_MAX_SCELL_NB (1)
+#endif
+
+
+
+typedef enum
+{
+ ERRC_EMAC_CONFIG_CAUSE_NON_HO = 0,
+ ERRC_EMAC_CONFIG_CAUSE_HO = 1,
+ ERRC_EMAC_CONFIG_CAUSE_RESET = 2,
+//#if defined(__REMOTE_SIM__)
+#if defined(__GEMINI__)
+ ERRC_EMAC_CONFIG_CAUSE_RESET_VIRTUAL_CONNECTED_ENTER = 3,
+ ERRC_EMAC_CONFIG_CAUSE_VIRTUAL_CONNECTED_LEAVE_PREPARE = 4,
+ ERRC_EMAC_CONFIG_CAUSE_VIRTUAL_CONNECTED_LEAVE = 5,
+ ERRC_EMAC_CONFIG_CAUSE_RESET_VIRTUAL_CONNECTED_LEAVE_FAIL = 6,
+//#if defined(__SRLTE_ENHANCE__)
+#if defined(__GEMINI__)
+ //The design for SRLTE enhancement will be the same as RSIM, but we still seperate the cause
+ ERRC_EMAC_CONFIG_CAUSE_RESET_VIRTUAL_CONNECTED_ENTER_FOR_SRLTE = 7,
+ ERRC_EMAC_CONFIG_CAUSE_VIRTUAL_CONNECTED_LEAVE_PREPARE_FOR_SRLTE = 8,
+ ERRC_EMAC_CONFIG_CAUSE_VIRTUAL_CONNECTED_LEAVE_FOR_SRLTE = 9,
+ ERRC_EMAC_CONFIG_CAUSE_RESET_VIRTUAL_CONNECTED_LEAVE_FAIL_FOR_SRLTE = 10,
+#endif
+#endif
+} errc_emac_config_cause_enum;
+
+//For ICD MAC_RESET_EVENT and MAC_CONFIGURATION_EVENT
+typedef enum
+{
+ ERRC_EMAC_ICD_RESET_CAUSE_OTHERS = 0,
+ ERRC_EMAC_ICD_RESET_CAUSE_RELEASE = 1,
+ ERRC_EMAC_ICD_RESET_CAUSE_HO = 2,
+ ERRC_EMAC_ICD_RESET_CAUSE_RLF = 3,
+ ERRC_EMAC_ICD_CONFIG_CAUSE_NORMAL = 4,
+ ERRC_EMAC_ICD_CONFIG_CAUSE_HO = 5,
+} errc_emac_icd_event_cause_enum;
+
+typedef enum
+{
+ ERRC_EMAC_TA_TIMER_500, ERRC_EMAC_TA_TIMER_750, ERRC_EMAC_TA_TIMER_1280, ERRC_EMAC_TA_TIMER_1920,
+ ERRC_EMAC_TA_TIMER_2560, ERRC_EMAC_TA_TIMER_5120, ERRC_EMAC_TA_TIMER_10240, ERRC_EMAC_TA_TIMER_INF
+} errc_emac_ta_timer_enum;
+
+typedef enum
+{
+ RA_PREAMBLE_NB_4, RA_PREAMBLE_NB_8, RA_PREAMBLE_NB_12, RA_PREAMBLE_NB_16,
+ RA_PREAMBLE_NB_20, RA_PREAMBLE_NB_24, RA_PREAMBLE_NB_28, RA_PREAMBLE_NB_32,
+ RA_PREAMBLE_NB_36, RA_PREAMBLE_NB_40, RA_PREAMBLE_NB_44, RA_PREAMBLE_NB_48,
+ RA_PREAMBLE_NB_52, RA_PREAMBLE_NB_56, RA_PREAMBLE_NB_60,RA_PREAMBLE_NB_64
+} errc_emac_ra_preamble_nb_enum;
+
+typedef enum
+{
+ RA_GROUP_A_SZ_4, RA_GROUP_A_SZ_8, RA_GROUP_A_SZ_12, RA_GROUP_A_SZ_16,
+ RA_GROUP_A_SZ_20, RA_GROUP_A_SZ_24, RA_GROUP_A_SZ_28, RA_GROUP_A_SZ_32,
+ RA_GROUP_A_SZ_36, RA_GROUP_A_SZ_40, RA_GROUP_A_SZ_44, RA_GROUP_A_SZ_48,
+ RA_GROUP_A_SZ_52, RA_GROUP_A_SZ_56, RA_GROUP_A_SZ_60
+} errc_emac_ra_group_a_sz_enum;
+
+typedef enum
+{
+ RA_GROUP_A_MSG_SZ_56, RA_GROUP_A_MSG_SZ_144, RA_GROUP_A_MSG_SZ_208, RA_GROUP_A_MSG_SZ_256
+} errc_emac_ra_msg_sz_group_a_enum;
+
+typedef enum
+{
+ MSG_POW_OFFSET_GROUP_B_MINUS_INF, MSG_POW_OFFSET_GROUP_B_0, MSG_POW_OFFSET_GROUP_B_5,
+ MSG_POW_OFFSET_GROUP_B_8, MSG_POW_OFFSET_GROUP_B_10, MSG_POW_OFFSET_GROUP_B_12,
+ MSG_POW_OFFSET_GROUP_B_15, MSG_POW_OFFSET_GROUP_B_18
+} errc_emac_msg_pow_offset_group_b_enum;
+
+typedef enum
+{
+ RA_POW_RAMPING_0, RA_POW_RAMPING_2, RA_POW_RAMPING_4, RA_POW_RAMPING_6
+} errc_emac_ra_pow_ramping_enum;
+
+typedef enum
+{
+ PREAMBLE_INIT_POW_MINUS120, PREAMBLE_INIT_POW_MINUS118, PREAMBLE_INIT_POW_MINUS116,
+ PREAMBLE_INIT_POW_MINUS114, PREAMBLE_INIT_POW_MINUS112, PREAMBLE_INIT_POW_MINUS110,
+ PREAMBLE_INIT_POW_MINUS108, PREAMBLE_INIT_POW_MINUS106, PREAMBLE_INIT_POW_MINUS104,
+ PREAMBLE_INIT_POW_MINUS102, PREAMBLE_INIT_POW_MINUS100,
+ PREAMBLE_INIT_POW_MINUS98, PREAMBLE_INIT_POW_MINUS96, PREAMBLE_INIT_POW_MINUS94,
+ PREAMBLE_INIT_POW_MINUS92, PREAMBLE_INIT_POW_MINUS90
+} errc_emac_preamble_init_pow_enum;
+
+typedef enum
+{
+ PREAMBLE_TX_MAX_3, PREAMBLE_TX_MAX_4, PREAMBLE_TX_MAX_5, PREAMBLE_TX_MAX_6,
+ PREAMBLE_TX_MAX_7, PREAMBLE_TX_MAX_8, PREAMBLE_TX_MAX_10, PREAMBLE_TX_MAX_20,
+ PREAMBLE_TX_MAX_50, PREAMBLE_TX_MAX_100, PREAMBLE_TX_MAX_200
+} errc_emac_preamble_tx_max_enum;
+
+typedef enum
+{
+ RAR_WND_SZ_2, RAR_WND_SZ_3, RAR_WND_SZ_4, RAR_WND_SZ_5, RAR_WND_SZ_6, RAR_WND_SZ_7,
+ RAR_WND_SZ_8, RAR_WND_SZ_10
+} errc_emac_rar_wnd_sz_enum;
+
+typedef enum
+{
+ CR_TIMER_8, CR_TIMER_16, CR_TIMER_24, CR_TIMER_32, CR_TIMER_40, CR_TIMER_48, CR_TIMER_56, CR_TIMER_64
+} errc_emac_cr_timer_enum;
+
+
+typedef enum
+{
+ MAX_HARQ_TX_1, MAX_HARQ_TX_2, MAX_HARQ_TX_3, MAX_HARQ_TX_4, MAX_HARQ_TX_5, MAX_HARQ_TX_6,
+ MAX_HARQ_TX_7, MAX_HARQ_TX_8, MAX_HARQ_TX_10, MAX_HARQ_TX_12, MAX_HARQ_TX_16, MAX_HARQ_TX_20,
+ MAX_HARQ_TX_24, MAX_HARQ_TX_28
+} errc_emac_max_harq_tx_enum;
+
+typedef enum
+{
+ PERIODIC_BSR_5, PERIODIC_BSR_10, PERIODIC_BSR_16, PERIODIC_BSR_20, PERIODIC_BSR_32,
+ PERIODIC_BSR_40, PERIODIC_BSR_64, PERIODIC_BSR_80, PERIODIC_BSR_128, PERIODIC_BSR_160,
+ PERIODIC_BSR_320, PERIODIC_BSR_640, PERIODIC_BSR_1280, PERIODIC_BSR_2560, PERIODIC_BSR_INF
+} errc_emac_periodic_bsr_timer_enum;
+
+typedef enum
+{
+ RETX_BSR_320, RETX_BSR_640, RETX_BSR_1280, RETX_BSR_2560, RETX_BSR_5120, RETX_BSR_10240
+} errc_emac_retx_bsr_timer_enum;
+
+typedef enum
+{
+ ON_DURATION_PS1, ON_DURATION_PS2, ON_DURATION_PS3, ON_DURATION_PS4, ON_DURATION_PS5, ON_DURATION_PS6,
+ ON_DURATION_PS8, ON_DURATION_PS10, ON_DURATION_PS20, ON_DURATION_PS30, ON_DURATION_PS40,
+ ON_DURATION_PS50, ON_DURATION_PS60, ON_DURATION_PS80, ON_DURATION_PS100, ON_DURATION_PS200,
+ ON_DURATION_PS300, ON_DURATION_PS400, ON_DURATION_PS500, ON_DURATION_PS600,
+ ON_DURATION_PS800, ON_DURATION_PS1000, ON_DURATION_PS1200, ON_DURATION_PS1600
+} errc_emac_on_duration_timer_enum;
+
+typedef enum
+{
+ DRX_INACTIVITY_PS1, DRX_INACTIVITY_PS2, DRX_INACTIVITY_PS3, DRX_INACTIVITY_PS4, DRX_INACTIVITY_PS5,
+ DRX_INACTIVITY_PS6, DRX_INACTIVITY_PS8, DRX_INACTIVITY_PS10, DRX_INACTIVITY_PS20, DRX_INACTIVITY_PS30,
+ DRX_INACTIVITY_PS40, DRX_INACTIVITY_PS50, DRX_INACTIVITY_PS60, DRX_INACTIVITY_PS80, DRX_INACTIVITY_PS100,
+ DRX_INACTIVITY_PS200, DRX_INACTIVITY_PS300, DRX_INACTIVITY_PS500, DRX_INACTIVITY_PS750, DRX_INACTIVITY_PS1280,
+ DRX_INACTIVITY_PS1920, DRX_INACTIVITY_PS2560, DRX_INACTIVITY_PS0
+} errc_emac_drx_inactivity_timer_enum;
+
+typedef enum
+{
+ DRX_RETX_TIMER_PS1, DRX_RETX_TIMER_PS2, DRX_RETX_TIMER_PS4, DRX_RETX_TIMER_PS6, DRX_RETX_TIMER_PS8,
+ DRX_RETX_TIMER_PS16, DRX_RETX_TIMER_PS24, DRX_RETX_TIMER_PS33, DRX_RETX_TIMER_PS0,
+ DRX_RETX_TIMER_PS40, DRX_RETX_TIMER_PS64, DRX_RETX_TIMER_PS80, DRX_RETX_TIMER_PS96,
+ DRX_RETX_TIMER_PS112, DRX_RETX_TIMER_PS128, DRX_RETX_TIMER_PS160, DRX_RETX_TIMER_PS320
+} errc_emac_drx_retx_timer_enum;
+
+typedef enum
+{
+ DRX_UL_RETX_TIMER_PS0, DRX_UL_RETX_TIMER_PS1, DRX_UL_RETX_TIMER_PS2, DRX_UL_RETX_TIMER_PS4, DRX_UL_RETX_TIMER_PS6, DRX_UL_RETX_TIMER_PS8,
+ DRX_UL_RETX_TIMER_PS16, DRX_UL_RETX_TIMER_PS24, DRX_UL_RETX_TIMER_PS33, DRX_UL_RETX_TIMER_PS40, DRX_UL_RETX_TIMER_PS64,
+ DRX_UL_RETX_TIMER_PS80, DRX_UL_RETX_TIMER_PS96, DRX_UL_RETX_TIMER_PS112, DRX_UL_RETX_TIMER_PS128, DRX_UL_RETX_TIMER_PS160, DRX_UL_RETX_TIMER_PS320
+} errc_emac_drx_ul_retx_timer_enum;
+
+typedef enum
+{
+ LONG_DRX_CYCLE_10, LONG_DRX_CYCLE_20, LONG_DRX_CYCLE_32, LONG_DRX_CYCLE_40, LONG_DRX_CYCLE_64,
+ LONG_DRX_CYCLE_80, LONG_DRX_CYCLE_128, LONG_DRX_CYCLE_160, LONG_DRX_CYCLE_256, LONG_DRX_CYCLE_320,
+ LONG_DRX_CYCLE_512, LONG_DRX_CYCLE_640, LONG_DRX_CYCLE_1024, LONG_DRX_CYCLE_1280, LONG_DRX_CYCLE_2048,
+ LONG_DRX_CYCLE_2560, LONG_DRX_CYCLE_60, LONG_DRX_CYCLE_70
+} errc_emac_long_drx_cycle_enum;
+
+typedef enum
+{
+ SHORT_DRX_CYCLE_2, SHORT_DRX_CYCLE_5, SHORT_DRX_CYCLE_8, SHORT_DRX_CYCLE_10, SHORT_DRX_CYCLE_16,
+ SHORT_DRX_CYCLE_20, SHORT_DRX_CYCLE_32, SHORT_DRX_CYCLE_40, SHORT_DRX_CYCLE_64, SHORT_DRX_CYCLE_80,
+ SHORT_DRX_CYCLE_128, SHORT_DRX_CYCLE_160, SHORT_DRX_CYCLE_256, SHORT_DRX_CYCLE_320, SHORT_DRX_CYCLE_512,
+ SHORT_DRX_CYCLE_640, SHORT_DRX_CYCLE_4
+} errc_emac_short_drx_cycle_enum;
+
+
+
+typedef enum
+{
+ PERIODIC_PHR_10, PERIODIC_PHR_20, PERIODIC_PHR_50, PERIODIC_PHR_100,
+ PERIODIC_PHR_200, PERIODIC_PHR_500, PERIODIC_PHR_1000, PERIODIC_PHR_INF
+} errc_emac_periodic_phr_timer_enum;
+
+typedef enum
+{
+ PROHIBIT_PHR_0, PROHIBIT_PHR_10, PROHIBIT_PHR_20, PROHIBIT_PHR_50,
+ PROHIBIT_PHR_100, PROHIBIT_PHR_200, PROHIBIT_PHR_500, PROHIBIT_PHR_1000
+} errc_emac_prohibit_phr_timer_enum;
+
+typedef enum
+{
+ DL_PATHLOSS_CHANGE_1, DL_PATHLOSS_CHANGE_3, DL_PATHLOSS_CHANGE_6, DL_PATHLOSS_CHANGE_INF
+} errc_emac_phr_dl_pathloss_change_enum;
+
+typedef enum
+{
+ BRQ_PROHIBIT_S0, BRQ_PROHIBIT_S0DOT4, BRQ_PROHIBIT_S0DOT8, BRQ_PROHIBIT_S1DOT6,
+ BRQ_PROHIBIT_S3, BRQ_PROHIBIT_S6, BRQ_PROHIBIT_S12, BRQ_PROHIBIT_S30
+} errc_emac_brq_prohibit_timer_enum;
+
+typedef enum
+{
+ ERRC_EMAC_TA_INFO_REQ_TYPE_STOP,
+ ERRC_EMAC_TA_INFO_REQ_TYPE_START
+} errc_emac_ta_info_req_type_enum;
+
+typedef enum
+{
+ EMAC_ERRC_RA_ERROR_ERRC_TRIGGER = 0,
+ EMAC_ERRC_RA_ERROR_NON_ERRC_TRIGGER = 0x01
+} emac_errc_ra_error_cause_enum;
+
+typedef enum
+{
+ EMAC_ERRC_L1_REL_CAUSE_TA = 0,
+ EMAC_ERRC_L1_REL_CAUSE_SR = 0x01,
+} emac_errc_ul_rel_cause_enum;
+
+typedef enum
+{
+ EMAC_ERRC_DRX_INC_GAP_REQ_TYPE_STOP,
+ EMAC_ERRC_DRX_INC_GAP_REQ_TYPE_START
+} errc_emac_drx_inc_gap_req_type_enum;
+
+typedef enum
+{
+ ERRC_EMAC_CCCH_CAUSE_CONN_REQ = 0,
+ ERRC_EMAC_CCCH_CAUSE_REEST_REQ = 0x01
+} errc_emac_ccch_cause_enum;
+
+typedef enum
+{
+ EMAC_SCELL_DEACTIVATION_TIMER_INFINITY, // defalut value
+ EMAC_SCELL_DEACTIVATION_TIMER_RF2,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF4,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF8,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF16,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF32,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF64,
+ EMAC_SCELL_DEACTIVATION_TIMER_RF128
+}emac_scell_deactivation_timer_enum;
+
+typedef enum
+{
+ ERRC_EMAC_TTI_BUNDLING_DISABLED,
+ ERRC_EMAC_TTI_BUNDLING_NORMAL,
+ ERRC_EMAC_TTI_BUNDLING_ENHANCED_FDD
+} errc_emac_tti_bundling_mode_enum;
+
+#if defined(__XL1SIM_EL1__)
+// old struct for XL1Sim test case use
+typedef struct
+{
+ errc_emac_ra_pow_ramping_enum power_ramping_step;
+ errc_emac_preamble_init_pow_enum preamble_init_rec_target_power;
+ errc_emac_preamble_tx_max_enum preamble_trans_max;
+} errc_emac_ul_scell_params_struct;
+#endif
+
+typedef struct
+{
+ kal_uint8 scell_index;
+ errc_emac_ra_pow_ramping_enum power_ramping_step;
+ errc_emac_preamble_init_pow_enum preamble_init_rec_target_power;
+ errc_emac_preamble_tx_max_enum preamble_trans_max;
+} errc_emac_scell_ul_params_struct;
+
+typedef enum
+{
+ ERRC_EMAC_SCELL_NOT_CONFIGURED = 0,
+ ERRC_EMAC_SCELL_ALL_DEACTIVATED = 1,
+ ERRC_EMAC_1_SCELL_ACTIVATED = 2
+}errc_emac_ca_activate_state_enum;
+
+typedef struct
+{
+ errc_emac_ra_preamble_nb_enum ra_preamble_nb_index;
+ errc_emac_ra_pow_ramping_enum ra_pow_ramping_index;
+ errc_emac_preamble_init_pow_enum ra_preamble_init_pow_index;
+ errc_emac_preamble_tx_max_enum ra_preamble_tx_max_index;
+ errc_emac_rar_wnd_sz_enum ra_rar_wnd_sz_index;
+ errc_emac_cr_timer_enum ra_cr_timer_index;
+
+ kal_uint8 ra_msg3_tx_max;
+
+ kal_bool group_a_valid;
+ errc_emac_ra_group_a_sz_enum ra_group_a_sz_index;
+ errc_emac_ra_msg_sz_group_a_enum ra_msg_sz_group_a_index;
+ errc_emac_msg_pow_offset_group_b_enum ra_msg_pow_offset_group_b_index;
+ kal_bool ra_dedicated_valid;
+ kal_uint8 rapid;
+ kal_uint8 prach_mask;
+
+#if defined(__XL1SIM_EL1__)
+ // old struct for XL1Sim test case use
+ errc_emac_ul_scell_params_struct ul_scell_params;
+ kal_bool ul_scell_params_are_valid;
+#else
+ errc_emac_scell_ul_params_struct scell_params[ERRC_EMAC_MAX_SCELL_NB];
+ kal_uint8 valid_scell_param_num;
+#endif
+} emac_ra_config_info_struct;
+
+
+typedef struct
+{
+ errc_emac_max_harq_tx_enum max_harq_tx_index;
+ errc_emac_periodic_bsr_timer_enum periodic_bsr_timer_index;
+ errc_emac_retx_bsr_timer_enum retx_bsr_timer_index;
+ errc_emac_tti_bundling_mode_enum tti_bundling;
+
+ kal_bool extended_bsr_sizes;
+} emac_sched_config_info_struct;
+
+
+
+typedef struct
+{
+ errc_emac_on_duration_timer_enum on_duration_timer_index;
+ errc_emac_drx_inactivity_timer_enum drx_inactivity_timer_index;
+ errc_emac_drx_retx_timer_enum drx_retx_timer_index;
+ errc_emac_long_drx_cycle_enum long_drx_cycle_index;
+
+ kal_bool drx_ul_retx_timer_valid;
+ errc_emac_drx_ul_retx_timer_enum drx_ul_retx_timer_index;
+
+ kal_bool short_cycle_valid;
+ errc_emac_short_drx_cycle_enum short_drx_cycle_index;
+ kal_uint8 drx_short_cycle_timer;
+
+ kal_uint16 drx_start_offset;
+} emac_drx_config_info_struct;
+
+
+typedef struct
+{
+ errc_emac_periodic_phr_timer_enum periodic_phr_timer_index;
+ errc_emac_prohibit_phr_timer_enum prohibit_phr_timer_index;
+ errc_emac_phr_dl_pathloss_change_enum phr_dl_pathloss_change_index;
+
+ kal_bool extended_phr;
+} emac_phr_config_info_struct;
+
+
+typedef struct
+{
+ kal_bool sr_mask; //r9 sr mask
+ kal_uint8 lcid;
+ kal_uint8 rb_idx;
+ errc_el2_rbid_enum rb_id;
+
+ ///RB direction
+ ///UL: 0x01 DL: 0x02 Bi-direction 0x03
+ ///EMAC_RB_UL_MASK 0x01
+ ///EMAC_RB_DL_MASK 0x02
+ kal_uint8 direction;
+ kal_uint8 lcg;
+ kal_uint8 ul_priority;
+ kal_bool logical_channel_sr_prohibit_timer_is_used;
+ kal_bool logical_channel_brq_prohibit_timer_index_is_valid;
+ errc_emac_brq_prohibit_timer_enum logical_channel_brq_prohibit_timer_index;
+} errc_emac_open_rb_struct;
+
+typedef struct
+{
+ kal_uint8 rb_idx;
+ errc_el2_rbid_enum rb_id;
+ kal_uint8 direction;
+} errc_emac_close_rb_struct;
+
+// MSG_ID_ERRC_EMAC_MEAS_GAP_IND
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 gap_pattern; //0: gap=40, 1: gap=80
+ kal_uint8 offset; //0xFF: no gap
+} errc_emac_meas_gap_ind_struct;
+
+/* CHM MBMS support start */
+typedef enum
+{
+ ERRC_EMAC_CONFIG_TYPE_ALL = 0, // configure SCH only, or configure both SCH+MCH
+ ERRC_EMAC_CONFIG_TYPE_MCH_ONLY = 1 // configure MCH only
+} errc_emac_config_type_enum;
+
+typedef struct
+{
+ kal_uint8 mbsfn_area_id; // 0~255
+
+ // numbered by eRRC and not from NW,
+ // If one carrier is supported, range 0~7
+ // If two carriers are supported, range 0~15
+ kal_uint8 mcch_idx;
+} errc_emac_open_mcch_struct;
+
+typedef struct
+{
+ kal_uint8 mbsfn_area_id; // 0~255, currently for debug purpose only
+ kal_uint8 mcch_idx;
+} errc_emac_close_mcch_struct;
+
+typedef struct
+{
+ kal_uint8 mbsfn_area_id; // 0~255
+ kal_uint8 pmch_id; // 0~15, numbered by eRRC and not from NW (directly use the index in asn)
+ kal_uint8 lcid; // 0~28
+ kal_uint8 mrb_idx; // numbered by eRRC, The range of mrb_idx depends on L2 HW capability
+} errc_emac_open_mrb_struct;
+
+typedef struct
+{
+ kal_uint8 mbsfn_area_id; // 0~255, currently for debug purpose only
+ kal_uint8 pmch_id; // 0~15, currently for debug purpose only
+ kal_uint8 lcid; // 0~28, currently for debug purpose only
+ kal_uint8 mrb_idx; // numbered by eRRC, The range of mrb_idx depends on L2 HW capability
+} errc_emac_close_mrb_struct;
+
+/* CHM MBMS support end */
+
+typedef struct
+{
+ kal_uint8 stag_id;
+ errc_emac_ta_timer_enum s_tag_ta_timer;
+} errc_emac_stag_timer_info_struct;
+
+// MSG_ID_ERRC_EMAC_CONFIG_REQ
+typedef struct
+{
+ LOCAL_PARA_HDR
+ errc_emac_config_type_enum config_type; //configure either MCH only or all
+ errc_emac_config_cause_enum cause; //HO or RESET or not
+ errc_emac_ta_timer_enum ta_timer_index; //TA timer index
+ kal_uint8 sr_prohibit_timer; //SR prohibit timer index
+ kal_uint8 open_rb_nb; //number of open RB
+ kal_uint8 close_rb_nb; //number of close RB
+ errc_emac_open_rb_struct open_rb[ERRC_EMAC_MAX_RB_NB];
+ errc_emac_close_rb_struct close_rb[ERRC_EMAC_MAX_RB_NB];
+
+ errc_emac_icd_event_cause_enum icd_event_cause; //ICD MAC_RESET_EVENT and MAC_CONFIGURATION_EVENT
+
+ //EMAC_CONFIG_INFO_RA_MASK
+ //EMAC_CONFIG_INFO_SCHED_MASK
+ //EMAC_CONFIG_INFO_DRX_MASK
+ //EMAC_CONFIG_INFO_PHR_MASK
+ //EMAC_CONFIG_INFP_CRNTI_MASK
+ kal_uint8 info_bitmap;
+ emac_ra_config_info_struct ra_config_info;
+ emac_sched_config_info_struct schd_config_info;
+ emac_drx_config_info_struct drx_config_info;
+ emac_phr_config_info_struct phr_config_info;
+ kal_uint16 c_rnti; //new C-RNTI value
+ kal_bool dl_data_sus_flg;
+
+ emac_scell_deactivation_timer_enum scell_deactivation_timer;
+ kal_uint8 configured_scell_bitmap;
+ kal_bool simultaneous_pucch_pusch;
+ kal_bool pusch_enhancement_mode;
+
+/* CHM MBMS support start */
+ //kal_uint8 open_mcch_nb[MAX_EMBMS_FREQ_SUPPORT]; // for 2 freq
+ //kal_uint8 close_mcch_nb[MAX_EMBMS_FREQ_SUPPORT]; // for 2 freq
+ //errc_emac_open_mcch_struct open_mcch[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MCCH_SUPPORT];
+ //errc_emac_close_mcch_struct close_mcch[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MCCH_SUPPORT];
+
+ //kal_uint8 open_mrb_nb[MAX_EMBMS_FREQ_SUPPORT]; // for 2 freq
+ //kal_uint8 close_mrb_nb[MAX_EMBMS_FREQ_SUPPORT]; // for 2 freq
+ //errc_emac_open_mrb_struct open_mrb[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MRB_SUPPORT];
+ //errc_emac_close_mrb_struct close_mrb[MAX_EMBMS_FREQ_SUPPORT][MAX_EMBMS_MRB_SUPPORT];
+/* CHM MBMS support end */
+
+ #if defined(__XL1SIM_EL1__)
+ // old struct for XL1Sim test case use
+ errc_emac_ta_timer_enum s_tag_ta_timer;
+ kal_bool s_tag_ta_timer_is_valid;
+ #else
+ kal_uint8 s_tag_ta_timer_valid_nb; //number of valid stag timer info nb
+ errc_emac_stag_timer_info_struct s_stag_ta_timer_info[ERRC_EMAC_MAX_STAG_NB];
+ #endif
+
+ kal_bool logical_channel_sr_prohibit_timer_is_valid;
+ kal_uint16 logical_channel_sr_prohibit_timer; /* Value in subframes */
+
+} errc_emac_config_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ errc_el2_cfg_result_enum result;
+} errc_emac_config_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ emac_errc_ra_error_cause_enum cause;
+} errc_emac_ra_error_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint16 crnti;
+ kal_uint8 preamble_tx_nb;
+ kal_bool contention_ind;
+} errc_emac_contention_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 preamble_tx_nb;
+ kal_bool contention_ind;
+} errc_emac_ra_info_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 preamble_tx_nb;
+ kal_bool contention_ind;
+ kal_bool max_txpower_reached;
+} errc_emac_estfail_report_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ emac_errc_ul_rel_cause_enum cause;
+ kal_bool s_tag_is_valid;
+ kal_uint8 s_tag;
+} errc_emac_l1_ul_rel_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 ccch_size;
+ kal_uint8 ccch[6];
+ errc_emac_ccch_cause_enum cause;
+} errc_emac_ccch_data_req_struct;
+
+/* Need to remove for TK6291 U4G */
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 paging_ctrl_info;
+ qbm_gpd* p_rgpd;
+ ABS_TICK_TIME proc_abs_time;
+ lte_cell_time proc_lte_time;
+} errc_emac_paging_ind_struct;
+
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 si_ctrl_info;
+ qbm_gpd* p_rgpd;
+ ABS_TICK_TIME proc_abs_time;
+ lte_cell_time proc_lte_time;
+
+ kal_uint8 carrier_info; //Carrier Index, only valid for 0 and 1
+} errc_emac_si_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ void* p_data; //93, start address of SRB data in VRB
+ kal_uint32 data_len; //93, length of SRB data in VRB
+
+} errc_emac_ccch_data_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ errc_emac_ta_info_req_type_enum req_type;
+} errc_emac_ta_info_req_struct;
+
+typedef struct
+{
+ kal_uint32 ta;
+ kal_uint8 s_tag_id;
+} errc_emac_s_tag_ta_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_bool is_valid;
+ kal_uint32 ta;
+ kal_bool s_tag_ta_is_valid;
+ errc_emac_s_tag_ta_struct s_tag_ta;
+} errc_emac_ta_info_cnf_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint32 ta;
+ kal_uint8 tag_id;
+} errc_emac_ta_info_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 tag_id;
+} errc_emac_ta_info_invalid_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ errc_emac_drx_inc_gap_req_type_enum req_type;
+ kal_uint32 max_interval;
+} errc_emac_drx_inc_gap_req_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+ kal_uint8 scell_activate_bmp_dl;
+ kal_uint8 scell_activate_bmp_ul;
+} errc_emac_ca_activate_ind_struct;
+
+
+typedef enum
+{
+ ERRC_EMAC_SUPPORT_REL_R9,
+ ERRC_EMAC_SUPPORT_REL_R10,
+ ERRC_EMAC_SUPPORT_REL_R11,
+ ERRC_EMAC_SUPPORT_REL_R12,
+ ERRC_EMAC_SUPPORT_REL_R13,
+ ERRC_EMAC_SUPPORT_REL_INVALID
+} errc_emac_support_release_enum;
+
+
+typedef enum
+{
+ ERRC_EMAC_DL_QAM_64 = 0,
+ ERRC_EMAC_DL_QAM_256 = 1,
+ ERRC_EMAC_DL_QAM_NUM = 2,
+ ERRC_EMAC_DL_QAM_INVALID
+} errc_emac_dl_modulation_enum;
+
+
+typedef enum
+{
+ ERRC_EMAC_UL_QAM_16 = 0,
+ ERRC_EMAC_UL_QAM_64 = 1,
+ ERRC_EMAC_UL_QAM_256 = 2,
+ ERRC_EMAC_UL_QAM_NUM = 3,
+ ERRC_EMAC_UL_QAM_INVALID
+} errc_emac_ul_modulation_enum;
+
+typedef enum
+{
+ ERRC_EMAC_DL_CAT_1 = 0,
+ ERRC_EMAC_DL_CAT_2 = 1,
+ ERRC_EMAC_DL_CAT_3 = 2,
+ ERRC_EMAC_DL_CAT_4 = 3,
+ ERRC_EMAC_DL_CAT_6 = 4,
+ ERRC_EMAC_DL_CAT_7 = 5,
+ ERRC_EMAC_DL_CAT_9 = 6,
+ ERRC_EMAC_DL_CAT_10 = 7,
+ ERRC_EMAC_DL_CAT_11 = 8,
+ ERRC_EMAC_DL_CAT_12 = 9,
+ ERRC_EMAC_DL_CAT_13 = 10,
+ ERRC_EMAC_DL_CAT_16 = 11,
+ ERRC_EMAC_DL_CAT_NUM = 12,
+ ERRC_EMAC_DL_CAT_INVALID
+} errc_emac_dl_category_enum;
+
+typedef enum
+{
+ ERRC_EMAC_UL_CAT_1 = 0,
+ ERRC_EMAC_UL_CAT_2 = 1,
+ ERRC_EMAC_UL_CAT_3 = 2,
+ ERRC_EMAC_UL_CAT_4 = 3,
+ ERRC_EMAC_UL_CAT_5 = 4,
+ ERRC_EMAC_UL_CAT_6 = 5,
+ ERRC_EMAC_UL_CAT_7 = 6,
+ ERRC_EMAC_UL_CAT_9 = 7,
+ ERRC_EMAC_UL_CAT_10 = 8,
+ ERRC_EMAC_UL_CAT_11 = 9,
+ ERRC_EMAC_UL_CAT_12 = 10,
+ ERRC_EMAC_UL_CAT_13 = 11,
+ ERRC_EMAC_UL_CAT_15 = 12,
+ ERRC_EMAC_UL_CAT_NUM = 13,
+ ERRC_EMAC_UL_CAT_INVALID
+} errc_emac_ul_category_enum;
+
+typedef struct
+{
+ LOCAL_PARA_HDR
+
+ // Support Release
+ errc_emac_support_release_enum support_release;
+
+ // Capability
+ errc_emac_dl_category_enum dl_category;
+ errc_emac_ul_category_enum ul_category;
+ errc_emac_dl_modulation_enum highest_dl_modulation;
+ errc_emac_ul_modulation_enum highest_ul_modulation;
+
+ // Features
+ kal_bool recommendBitRate_enable;
+
+} errc_emac_support_capability_ind_struct;
+
+#endif /*ERRC_EMAC_INTERFACE_H*/