[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/protocol/interface/enl2/el2/epdcp_enum.h b/mcu/protocol/interface/enl2/el2/epdcp_enum.h
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+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * epdcp_enum.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 25 2019 jia-shi.lin
+ * [MOLY00460829] [MT6885][Petrus][MP1][SQC][CT][NSIOT][HQ][KS][N78][SA][CTC_DP_6.2.3][TC-MF_NR_DT-02003]SA UL256QAM Tput not as expected
+ * 1. new sit_update msg from nl1
+ * 2. sit update profile
+ *
+ * 10 14 2019 yiting.cheng
+ * [MOLY00442846] [Gen97] Modem´¼¯à«ÝÉófeature - NSA part (implementation)
+ * .
+ *
+ * 04 25 2019 ken.li
+ * [MOLY00383711] [MT6297][Apollo][PreSQC][MP0.5][NVIOT][Nokia][Oulu][4G]: Assert Fail: dpcopro_hisr.c 713 - (LISR)mml2_excep_lisr
+ *
+ * EPDCP DL OOB and HFN desync handling
+ *
+ * 04 22 2019 ken.li
+ * [MOLY00383711] [MT6297][Apollo][PreSQC][MP0.5][NVIOT][Nokia][Oulu][4G]: Assert Fail: dpcopro_hisr.c 713 - (LISR)mml2_excep_lisr
+ *
+ * EPDCP DL OOB and HFN desync handling
+ *
+ * 08 17 2018 yk.liu
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * merge EMOLY CLs to VMOLY
+ *
+ * 07 05 2018 head.hsu
+ * [MOLY00327926] [GEN97][ENPDCP] base development check-in
+ * restructure:
+ * 1.fix some warning
+ * 2.remove legacy file
+ * 3.remove some phase-out context
+ * 4.rename internal term from epdcp to enpdcp
+ * 5.add trace
+ *
+ * [Protocol build tag]
+ * [Is CL self testable: YES]
+ * [Group CL list: NO]
+ *
+ * 05 18 2018 head.hsu
+ * [MOLY00326691] [MT6297] GEN97.DEV ENL2 Patch back
+ * port latest interface and code on Gen97.DEV (PDCP UL dummy)
+ *
+ * 07 13 2017 steve.kao
+ * [MOLY00264004] [6293] EPDCP R-SIM code changes and UT with bugfixes
+ *
+ * [UMOLYA][TRUNK] EPDCP changes for L+L, R-SIM, UT, and bugfixes.
+ *
+ * 05 04 2017 steve.kao
+ * [MOLY00246810] [BIANCO][MT6763][RDIT][FT][CMCC][BJ][TDL Case][1.3.1][ASSERT] file:mcu/pcore/modem/el2/el2/epdcp/src/epdcp_dl.c line:4692
+ * [UMOLYA][TRUNK][EPDCP] Handling flag V in LHIF mode handlers, and modify logs.
+ *
+ * 04 07 2017 steve.kao
+ * [MOLY00230062] [UMOLYA] M-PS related interface changes for UPCM, RATDM, and EPDCP
+ *
+ * [UMOLYA][TRUNK]
+ *
+ * [UPCM][M-PS] Code changes
+ * 1. Duplicating UPCM contexts,
+ * 2. Use protocol_idx in UL/DL callback/ILM interfaces,
+ * 3. Check protocol_idx in LHIF PIT entries,
+ * 4. Fix test mode UL data processing flow,
+ * 5. Allowing test mode on protocol 2/3/4,
+ * 6. Wrap interfaces with RATDM with __MULTIPLE_PS__,
+ *
+ * [EPDCP][L+L] Code changes
+ *
+ * [RATDM][L+L] Code changes
+ *
+ * 02 21 2017 steve.kao
+ * [MOLY00230998] [6293][EL2][EPDCP] Simplified DL mode switching.
+ * [UMOLYA][TRUNK][EPDCP] Simplified DL mode switch for NETIF binding.
+ *
+ * 11 01 2016 steve.kao
+ * [MOLY00195563] [6293][EL2][UPCM][RATDM][EPDCP] Initial feature integrations
+ * [UMOLYA_TRUNK][EPDCP] Add DL traces & fix c-model bugs.
+ *
+ * 01 21 2016 mingtsung.sun
+ * [MOLY00160421] [MT6292] ePDCP CE RAM Optimization
+ * [EPDCP] CE RAM OPT.
+ *
+ * 06 15 2015 mingtsung.sun
+ * [MOLY00121332] [TK6291] 4G EAS low power check in
+ * eL2 low power and ePDCP code sync: mcu\common\modem\lte_sec\...
+ *
+ * 07 04 2013 timothy.yao
+ * [MOLY00028092] [MT6290E1][EL2 IT] fix the log statement
+ * 1. fix variable order in log statement.
+ * 2. apply heximal & enum usage.
+ ****************************************************************************/
+#ifndef ENPDCP_ENUM_INC
+#define ENPDCP_ENUM_INC
+
+#include "enl2_def.h"
+
+/**
+* @brief RB state (SRB/DRB)
+*/
+typedef enum
+{
+ /* for RB entity/record common use */
+ RB_ST_NONE = 0,
+ RB_ST_ACTIVE,
+ RB_ST_SUSPENDED,
+ RB_ST_HANDOVER,
+
+ /* for RB record specific use */
+ RB_ST_HO_N_SUSP,
+ RB_ST_HO_N_ACTV,
+
+#if ENPDCP_REMOTE_SIM
+ /* for virtual connectivity */
+ RB_ST_VIRT_CONN_N_SUSP,
+ RB_ST_VIRT_CONN_N_ACTV,
+#endif
+
+} enpdcp_rb_st_e;
+
+typedef enum
+{
+ DETN_TMR3_MONTR_LV_OFF = 0,
+ DETN_TMR3_MONTR_LV_DRB,
+ DETN_TMR3_MONTR_LV_ALL_RB,
+} detnTmr3_montr_lv_e;
+
+typedef enum
+{
+ DETN_TMR3_PHASE_RRC = 0,
+ DETN_TMR3_PHASE_NAS,
+} detnTmr3_phase_e;
+
+typedef enum
+{
+ TMR_ST_STOPPED = 0,
+ TMR_ST_RUNNING,
+ TMR_ST_TIMEOUT
+} tmr_st_e;
+
+typedef enum
+{
+ ENPDCP_EC_OK = 0,
+
+ /* common */
+ ENPDCP_EC_INV_RB_NUM,
+ ENPDCP_EC_INV_RB_ID,
+ ENPDCP_EC_INV_RB_IDX,
+ ENPDCP_EC_UNEXP_RB_STATE,
+
+ /* Loopback TEST-REQ */
+ ENPDCP_EC_DRB_LB_ENABLED,
+
+ /* CONFIG-REQ */
+ ENPDCP_EC_SEC_CFG_WO_SRB1,
+ ENPDCP_EC_ADD_SRB2_DRB_WO_FULL_SEC,
+ ENPDCP_EC_INV_ADD_RB_ID,
+ ENPDCP_EC_INV_ADD_RB_IDX,
+ ENPDCP_EC_INV_ADD_RB_CMD,
+ ENPDCP_EC_INV_ADD_UM_DIR,
+ ENPDCP_EC_INV_MOD_RB_ID,
+ ENPDCP_EC_INV_MOD_RB_IDX,
+ ENPDCP_EC_INV_MOD_RB_CMD,
+ ENPDCP_EC_INV_MOD_UM_DIR,
+ ENPDCP_EC_INV_DEL_RB_ID,
+ ENPDCP_EC_INV_DEL_RB_IDX,
+ ENPDCP_EC_INV_DEL_RB_CMD,
+
+ /* DCCH_DATA_REQ */
+ ENPDCP_EC_INV_TGPD,
+ ENPDCP_EC_INV_PEER_BUF_PTR,
+
+ /* LTM_DATA_REQ */
+ ENPDCP_EC_INV_PRI_DATA_LIST,
+ ENPDCP_EC_INV_NML_DATA_LIST,
+ ENPDCP_EC_RB_UL_DIR_DISABLED,
+ ENPDCP_EC_RB_UL_FLOW_CTRL,
+
+ ENPDCP_EC_MAX
+} enpdcp_errcode_e;
+
+/////// ENPDCP DL related ///////
+/**
+ * @brief RB DL config stages (DRB)
+ */
+typedef enum
+{
+ DRB_DL_CFG_STG_NORMAL = 0,
+
+ // When the DL CFG STG is not NORMAL, then the DL mode of the DRB might be
+ // in the midst of being changed from VRB-mode to LHIF-mode .
+
+ /* REEST: AM DRB should be with VRB-RO */
+ DRB_DL_CFG_STG_REEST_FLUSHING,
+ DRB_DL_CFG_STG_REEST_REORDERING,
+ DRB_DL_CFG_STG_REEST_WAIT_FOR_HFN_SYNC,
+ DRB_DL_CFG_STG_REEST_DCIP_SUSPENDING,
+ DRB_DL_CFG_STG_REEST_WAIT_FOR_DELIVERY,
+ /* REEST: AM DRB should be with VRB-RO */
+
+ /* HFN Resync when not in reest stage: AM DRB should be with VRB-RO */
+ DRB_DL_CFG_STG_HFN_RESYNC_WAIT_FOR_HFN_SYNC,
+ DRB_DL_CFG_STG_HFN_RESYNC_DCIP_SUSPENDING,
+ DRB_DL_CFG_STG_HFN_RESYNC_WAIT_FOR_DELIVERY,
+ /* HFN Resync when not in reest stage: AM DRB should be with VRB-RO */
+
+ /* LWA */
+ DRB_DL_CFG_STG_EN_LWA_DCIP_SUSPENDING, // suspend DCIP for APRO enabling // TODO: REMOVE
+ DRB_DL_CFG_STG_EN_LWA_WAIT_APRO_CNF// TODO: REMOVE
+ /* LWA */
+} enpdcp_drb_dl_cfg_stg_e;
+
+typedef enum
+{
+ RB_DL_MODE_BIT_RO_ON = 0x1, // o.w. RO_OFF
+ RB_DL_MODE_BIT_DEST_VRB = 0x2, // o.w. DEST_LHIF
+} enpdcp_rb_dl_mode_bit_e;
+
+typedef enum
+{
+ RB_DL_MODE_LHIF_NRO = 0,
+ RB_DL_MODE_LHIF_RO = RB_DL_MODE_BIT_RO_ON,
+ RB_DL_MODE_VRB_NRO = RB_DL_MODE_BIT_DEST_VRB,
+ RB_DL_MODE_VRB_RO = RB_DL_MODE_BIT_DEST_VRB | RB_DL_MODE_BIT_RO_ON
+} enpdcp_rb_dl_mode_e;
+
+typedef enum{
+ ENPDCP_ILM_INVALID,
+ ENPDCP_ILM_ACCEPT,
+ ENPDCP_ILM_IGNORE
+} enpdcp_ilm_check_enum;
+
+typedef enum
+{
+ DL_MODE_SWITCH_CAUSE_BECOME_LHIF_MODE_CAPABLE = 0,
+ DL_MODE_SWITCH_CAUSE_DIS_TESTMODE,
+ DL_MODE_SWITCH_CAUSE_WAIT_FOR_DELIVERY_DONE,
+ DL_MODE_SWITCH_CAUSE_DIS_FORCED_INDIRECT_PATH,
+} dl_mode_switch_cause_e;
+
+typedef enum
+{
+ EPDCP_DL_LOG_LEVEL_RAW = 0,
+ EPDCP_DL_LOG_LEVEL_REFINED,
+} epdcp_dl_log_level_e;
+
+typedef enum
+{
+ EPDCP_UL_LOG_LEVEL_RAW = 0,
+ EPDCP_UL_LOG_LEVEL_REFINED,
+} epdcp_ul_log_level_e;
+
+typedef enum
+{
+ DRB_DL_HFN_SYNC = 0,
+ DRB_DL_HFN_RESYNC_DONE,
+ DRB_DL_HFN_DESYNC_TRY_CUR_HFN,
+ DRB_DL_HFN_DESYNC_DCIP_RESUME_TRYING,
+ DRB_DL_HFN_DESYNC_DCIP_SUSPEND,
+ DRB_DL_HFN_DESYNC_DCIP_SUSPEND_RESET_HFN,
+} epdcp_drb_dl_hfn_sync_stg_e;
+
+typedef enum
+{
+ ENPDCP_FUNC_SIT_UPDATE,
+ ENPDCP_FUNC_NRLC_PREGEN
+} enpdcp_func_profile_e;
+
+
+#endif // ~ #ifndef ENPDCP_ENUM_INC