[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/service/mdmp/mdmp_profile.c b/mcu/service/mdmp/mdmp_profile.c
new file mode 100644
index 0000000..2c38a88
--- /dev/null
+++ b/mcu/service/mdmp/mdmp_profile.c
@@ -0,0 +1,131 @@
+#include "mdmp_profile.h"
+
+unsigned int _mdmp_num_region_option = MAX_REGION_OPTION_NUM;
+unsigned int _mdmp_num_mem_type = MEM_TYPE_MAX;
+
+/////////////////////////////////////////
+// do not modify code above this line
+/////////////////////////////////////////
+
+mdmp_region_cfg_tbl region_tbl_full_dump =
+{
+ {MEM_SYS, {MEM_SYS_REGION_ALL} },
+ {MEM_SYS_SHM, {MEM_SYS_SHM_REGION_ALL} },
+ {MEM_DSP, {MEM_DSP_REGION_ALL} },
+ {MEM_SLA_CORE0, {MEM_SLA_CORE0_REGION_ALL} },
+ {MEM_SLA_CORE1, {MEM_SLA_CORE1_REGION_ALL} },
+ {MEM_SLA_CORE2, {MEM_SLA_CORE2_REGION_ALL} },
+ {MEM_SLA_CORE3, {MEM_SLA_CORE3_REGION_ALL} },
+ {MEM_SLA_BRP, {MEM_SLA_BRP_REGION_ALL} },
+ {MEM_SLA_INNER, {MEM_SLA_INNER_REGION_ALL} },
+ {MEM_SLA_FEC, {MEM_SLA_FEC_REGION_ALL} },
+ {MEM_SLA_SPEECH, {MEM_SLA_SPEECH_REGION_ALL} },
+ {MEM_SLA_MSONIC0, {MEM_SLA_MSONIC0_REGION_ALL} },
+ {MEM_SLA_MSONIC1, {MEM_SLA_MSONIC1_REGION_ALL} },
+ {MEM_SLA_VSONIC0, {MEM_SLA_VSONIC0_REGION_ALL} },
+ {MEM_USIP0, {MEM_USIP0_REGION_ALL} },
+ {MEM_USIP1, {MEM_USIP1_REGION_ALL} },
+ {MEM_SCQ16_0, {MEM_SCQ16_0_REGION_ALL} },
+ {MEM_SCQ16_1, {MEM_SCQ16_1_REGION_ALL} },
+ {MEM_SCQ16_2, {MEM_SCQ16_2_REGION_ALL} },
+ {MEM_SCQ16_3, {MEM_SCQ16_3_REGION_ALL} },
+ {MEM_MSONIC0, {MEM_MSONIC0_REGION_ALL, MEM_MSONIC0_REGION_MINI_NO_RO} },
+ {MEM_VSONIC0, {MEM_VSONIC0_REGION_ALL, MEM_VSONIC0_REGION_MINI_NO_RO} },
+ {MEM_MSONIC0_PHASE2, {MEM_MSONIC0_REGION_ALL, MEM_MSONIC0_REGION_MINI_NO_RO} },
+ {MEM_RAKE, {MEM_RAKE_REGION_ALL} },
+ {MEM_VRF, {MEM_VRF_REGION_ALL} },
+ {MEM_BB, {MEM_BB_REGION_ALL} },
+ {MEM_AST, {MEM_AST_REGION_ALL} }
+};
+
+mdmp_region_cfg_tbl region_tbl_mini_dump =
+{
+ {MEM_SYS, {MEM_SYS_REGION_WITHOUT_UC_ROM} },
+ {MEM_SYS_SHM, {MEM_SYS_SHM_REGION_APMD_CCCI_64K, MEM_SYS_SHM_REGION_APMD_CCCI_SCP, MEM_SYS_SHM_REGION_APMD_CCCI_CCB_CTRL,
+ MEM_SYS_SHM_REGION_APMD_CCCI_MDT_NETD, MEM_SYS_SHM_REGION_APMD_CCCI_MDT_USB, MEM_SYS_SHM_REGION_APMD_CCCI_AUDIO,
+ MEM_SYS_SHM_REGION_APMD_CCCI_MCU, MEM_SYS_SHM_REGION_APMD_CCCI_MCU_EXP} },
+ {MEM_DSP, {MEM_DSP_REGION_MINI} },
+ {MEM_SLA_CORE0, {MEM_SLA_CORE0_REGION_ALL} },
+ {MEM_SLA_CORE1, {MEM_SLA_CORE1_REGION_ALL} },
+ {MEM_SLA_CORE2, {MEM_SLA_CORE2_REGION_ALL} },
+ {MEM_SLA_CORE3, {MEM_SLA_CORE3_REGION_ALL} },
+ {MEM_SLA_BRP, {MEM_SLA_BRP_REGION_ALL} },
+ {MEM_SLA_INNER, {MEM_SLA_INNER_REGION_ALL} },
+ {MEM_SLA_FEC, {MEM_SLA_FEC_REGION_ALL} },
+ {MEM_SLA_SPEECH, {MEM_SLA_SPEECH_REGION_ALL} },
+ {MEM_SLA_MSONIC0, {MEM_SLA_MSONIC0_REGION_ALL} },
+ {MEM_SLA_MSONIC1, {MEM_SLA_MSONIC1_REGION_ALL} },
+ {MEM_SLA_VSONIC0, {MEM_SLA_VSONIC0_REGION_ALL} },
+ {MEM_USIP0, {MEM_USIP0_REGION_MINI} },
+ {MEM_USIP1, {MEM_USIP1_REGION_MINI} },
+ {MEM_SCQ16_0, {MEM_SCQ16_0_REGION_MINI} },
+ {MEM_SCQ16_1, {MEM_SCQ16_1_REGION_MINI} },
+ {MEM_SCQ16_2, {MEM_SCQ16_2_REGION_MINI} },
+ {MEM_SCQ16_3, {MEM_SCQ16_3_REGION_MINI} },
+ {MEM_MSONIC0, {MEM_MSONIC0_REGION_MINI_NO_RO} },
+ {MEM_VSONIC0, {MEM_VSONIC0_REGION_MINI_NO_RO} },
+ {MEM_MSONIC0_PHASE2, {MEM_MSONIC0_REGION_MINI_NO_RO} },
+ {MEM_RAKE, {MEM_RAKE_REGION_MINI} },
+ {MEM_VRF, {MEM_VRF_REGION_MINI} },
+ {MEM_BB, {NULL} },
+ {MEM_AST, {NULL} }
+};
+
+mdmp_region_cfg_tbl region_tbl_MIDR_dump =
+{
+ {MEM_SYS, {MEM_SYS_REGION_ALL} },
+ {MEM_SYS_SHM, {MEM_SYS_SHM_REGION_ALL} },
+ {MEM_DSP, {MEM_DSP_REGION_ALL} },
+ {MEM_SLA_CORE0, {MEM_SLA_CORE0_REGION_ALL} },
+ {MEM_SLA_CORE1, {MEM_SLA_CORE1_REGION_ALL} },
+ {MEM_SLA_CORE2, {MEM_SLA_CORE2_REGION_ALL} },
+ {MEM_SLA_CORE3, {MEM_SLA_CORE3_REGION_ALL} },
+ {MEM_SLA_BRP, {MEM_SLA_BRP_REGION_ALL} },
+ {MEM_SLA_INNER, {MEM_SLA_INNER_REGION_ALL} },
+ {MEM_SLA_FEC, {MEM_SLA_FEC_REGION_ALL} },
+ {MEM_SLA_SPEECH, {MEM_SLA_SPEECH_REGION_ALL} },
+ {MEM_SLA_MSONIC0, {MEM_SLA_MSONIC0_REGION_ALL} },
+ {MEM_SLA_MSONIC1, {MEM_SLA_MSONIC1_REGION_ALL} },
+ {MEM_SLA_VSONIC0, {MEM_SLA_VSONIC0_REGION_ALL} },
+ {MEM_USIP0, {MEM_USIP0_REGION_ALL} },
+ {MEM_USIP1, {MEM_USIP1_REGION_ALL} },
+ {MEM_SCQ16_0, {MEM_SCQ16_0_REGION_ALL} },
+ {MEM_SCQ16_1, {MEM_SCQ16_1_REGION_ALL} },
+ {MEM_SCQ16_2, {MEM_SCQ16_2_REGION_ALL} },
+ {MEM_SCQ16_3, {MEM_SCQ16_3_REGION_ALL} },
+ {MEM_MSONIC0, {MEM_MSONIC0_REGION_ALL, MEM_MSONIC0_REGION_MINI_NO_RO} },
+ {MEM_VSONIC0, {MEM_VSONIC0_REGION_ALL, MEM_VSONIC0_REGION_MINI_NO_RO} },
+ {MEM_MSONIC0_PHASE2, {MEM_MSONIC0_REGION_ALL, MEM_MSONIC0_REGION_MINI_NO_RO} },
+ {MEM_RAKE, {MEM_RAKE_REGION_ALL} },
+ {MEM_VRF, {MEM_VRF_REGION_ALL} },
+ {MEM_BB, {MEM_BB_REGION_ALL} },
+ {MEM_AST, {MEM_AST_REGION_ALL} }
+};
+
+extern MemDumpSymbol dhl;
+extern MemDumpSymbol g_dhl_ccb_buf_init_stage;
+
+// Example selective variable table
+mdmp_var_tbl selective_variables_oppo =
+// Format
+// Pointer to the symbol or address Size Type Access Mode
+{
+#ifdef __DHL_V2_ENABLE__
+ {&dhl, 128, MEM_SYS, ACCESS_MODE_NOT_SPECIFIED},
+#else
+#ifdef __DHL_CCB_LOGGING_SUPPORT__
+ {&g_dhl_ccb_buf_init_stage, 4, MEM_SYS, ACCESS_MODE_NOT_SPECIFIED},
+#endif
+#endif
+};
+
+
+// Configurate each memory dump profile here. The fist profile will be used as system default.
+mdmp_profile_table mdmp_profile_list =
+{
+// Format:
+// Region configuration table Selective variable table Flag
+ { ®ion_tbl_full_dump, NULL, 0 }, // Profile 0: full dump
+ { ®ion_tbl_mini_dump, NULL, 0 }, // Profile 1: mini dump
+ { ®ion_tbl_MIDR_dump, NULL, 0 }, // Profile 2: MIDR dump
+};