[Feature]Upload Modem source code
Change-Id: Id4294f30faced84d3e6fd6d5e61e1111bf287a37
diff --git a/mcu/tools/ldsGenLib.pl b/mcu/tools/ldsGenLib.pl
new file mode 100644
index 0000000..03efb6b
--- /dev/null
+++ b/mcu/tools/ldsGenLib.pl
@@ -0,0 +1,861 @@
+#!/usr/bin/perl
+#
+# Copyright Statement:
+# --------------------
+# This software is protected by Copyright and the information contained
+# herein is confidential. The software may not be copied and the information
+# contained herein may not be used or disclosed except with the written
+# permission of MediaTek Inc. (C) 2006
+#
+# BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+# THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+# RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+# AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+# NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+# SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+# SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+# THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+# NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+# SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+#
+# BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+# LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+# AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+# OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+# MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+#
+# THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+# WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+# LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+# RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+# THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+#
+#*****************************************************************************
+#*
+#* Filename:
+#* ---------
+#* ldsGenLib.pl
+#*
+#* Project:
+#* --------
+#*
+#*
+#* Description:
+#* ------------
+#* This script is to generate memory layout
+#*
+#* Author:
+#* -------
+#* Carl Kao (mtk08237)
+#*
+#****************************************************************************/
+#****************************************************************************
+# Included Modules
+#****************************************************************************
+use strict;
+BEGIN { push @INC, "pcore/" , './pcore/tools/' } # add additional library path
+use sysGenUtility;
+use ldsFrame;
+use FileInfoParser;
+use config_MemSegment;
+use tools::pack_dep_gen;
+use POSIX qw(floor ceil);
+PrintDependModule();
+
+#****************************************************************************
+# 0 >>> exit;
+#****************************************************************************
+return 1;
+#****************************************************************************
+# Constant
+#****************************************************************************
+
+
+#****************************************************************************
+# ldsGen Version
+#****************************************************************************
+sub ldsGen_verno
+{
+ return " v0.03_VMOLY + ldsFrame.pm ".&ldsFrame::ldsFrame_verno;
+ # v0.03_VMOLY, 2018/11/29, Tero, MT6297 FPGA builds uses 512MB memory map
+ # v0.02_VMOLY, 2018/11/19, Tero, MT6297 Ramdisk size increased to 32MB
+ # v0.01_VMOLY, 2018/10/17, Tero, MT6297 512MB memory config added
+ # a0.23_UMOLY, 2018/01/15, Tero, MT6295M/MT3967 increased L2C area size
+ # a0.22_UMOLY, 2018/01/17, Tero, MT6295M/MT3967 memory map updated
+ # a0.21_UMOLY, 2017/11/22, Tero, MT6739 memory map updated
+ # a0.20_UMOLY, 2017/02/11, Tero, MT6295M DSP size increased to 32M
+ # a0.19_UMOLY, 2017/09/27, Tero, MT6771 memory map updated
+ # a0.18_UMOLY, 2017/09/06, Tero, Adjusted MT6295M modem memoryy layout to 160MB
+ # a0.17_UMOLY, 2017/06/28, Carl, Reduced MT6763 modem size to 126MB
+ # a0.16_UMOLY, 2017/06/09, Tero, Reduced modem size to 248MB
+ # a0.15_UMOLY, 2017/04/21, Tero, Added support for MT6739
+ # a0.14_UMOLY, 2017/04/20, Tero, MT6295M support added
+ # a0.13_UMOLY, 2017/01/18, Tero, IOCU3 section added
+ # a0.12_UMOLY, 2017/01/04, Tero, UROM Size increased
+ # a0.11_UMOLY, 2016/12/12, Tero, UROM Size increased
+ # a0.10_UMOLY, 2016/11/21, Tero, GENTX/RX_SIZE uses custom_flavor as mode parameter
+ # a0.09_UMOLY, 2016/10/27, Tero, Autogen generated LDS support for MT6763
+ # a0.08_UMOLY, 2016/10/27, Tero, Remove unsued sections
+ # a0.08_UMOLY, 2016/08/01, Tero, l1core support removed
+ # a0.07_UMOLY, 2016/06/07, Carl, add GetRamdiskSize() for configruating ramdisk size
+ # a0.06_UMOLY, 2016/06/07, Carl, Change MD total size for 16MB ramdisk
+ # a0.05_UMOLY, 2016/04/15, Carl, Reduce UROM size, UROM and ROM share total 32 MB now
+ # a0.03_UMOLY, 2016/04/15, Carl, Do not use ISPRAM2, DSPRAM2 and L2SRAM in 93
+ # a0.03_UMOLY, 2016/04/01, JI, Support M17 new chip
+ # a0.02_UMOLY, 2016/03/31, JI, Support M17 new chip
+ # a0.01_UMOLY, 2016/03/21, BM, Branch from UMOLY trunk
+ #
+ # u0.38_UMOLY, 2016/03/03, Tero, Added GenEXTSRAM_END function
+ # u0.37_UMOLY, 2016/02/17, Tero, Default memory configuration for ELBRUS
+ # u0.36_UMOLY, 2016/01/31, Tero, GENTX/RX_SIZE uses original_flavor as mode parameter
+ # u0.35_UMOLY, 2016/01/26, Carl, Avoid dump sections with name "PHYSICAL_BOUNDARY" (for SPRAM physical name)
+ # u0.34_UMOLY, 2016/01/18, Tero, Elbrus total memory size get support added
+ # u0.23_UMOLY, 2015/07/20, Carl, Support ldsGen for MT6797
+ # u0.32_UMOLY, 2015/07/03, Carl, Change MT6755 MD only load size
+ # u0.31_UMOLY, 2015/06/23, Carl, Refine the way to use GetSharedMemorySize. It includes dsp tx/rx section now
+ # u0.30_UMOLY, 2015/06/05, Carl, Add MD size setting with ramdisk
+ # u0.29_UMOLY, 2015/06/04, Carl, Support ldsGen for MT6755
+ # u0.28_UMOLY, 2015/05/11, Carl, Support Ramdisk for TK6291
+ # u0.27_UMOLY, 2015/04/09, Carl, Align the shared DNC base to 64KB for input section MCU-RO, HW-RW (EMI RMPU)
+ # u0.26_UMOLY, 2015/01/26, Carl, Refine GetMPUAligned for adding debug log
+ # u0.25_UMOLY, 2015/01/06, Carl, lds refinement: 1) auto adjust shared region size, 2) reserve pcore, l1core SWLA space
+ # u0.24_UMOLY, 2014/12/22, Carl, Support L2SRAM section (in L1CORE)
+ # u0.23_UMOLY, 2014/11/25, Carl, Merge ATCM and BTCM as a single TCM
+ # u0.22_UMOLY, 2014/10/05, Carl, Align start address of shared memory section to 1MB
+ # u0.21_UMOLY, 2014/09/26, Carl, support GFH + SIG, move sig size to sysGenUtility.pm
+ # u0.21_UMOLY, 2014/09/26, Carl, support GFH + SIG
+ # u0.20_UMOLY, 2014/09/22, Carl, rename MT6291 to TK6291
+ # u0.19_UMOLY, 2014/09/11, mei, support l1core memory dump
+ # u0.18_UMOLY, 2014/09/05, Carl, reduce default shared memory size for PCORE ONLY project
+ # u0.17_UMOLY, 2014/08/20, Carl, refine l1core dump region
+ # u0.16_UMOLY, 2014/08/19, Carl, update L1core reset vector load view
+ # u0.15_UMOLY, 2014/07/31, Carl, dump l1core region
+ # u0.14_UMOLY, 2014/06/27, Carl, provide linker symbol rather than hardcode
+ # ...
+ # u0.01_UMOLY, 2014/02/20, BM, porting to MT6291_DEV
+
+}
+
+#****************************************************************************
+# Constants
+#****************************************************************************
+
+
+#****************************************************************************
+# Global Variables
+#****************************************************************************
+my $g_bb = undef;
+my $g_nRamSize = undef;
+my $g_bNeedBL = undef;
+my $g_BBFolder = undef;
+my $g_MakeFilePath = undef;
+my $g_MakeFile_ref = undef;
+my $g_nRAM_BASE = 0;
+
+my $g_l1core_offset = 0;
+#****************************************************************************
+# Input Parameters
+#****************************************************************************
+
+#****************************************************************************
+# subroutines
+#****************************************************************************
+
+#****************************************************************************
+# Unsupport: $flash_href, $flash_blk_href
+# $nor_device, $fota_cfg,
+# $mem_dev_h_cfg
+# $IsFlashtoolLayoutInput, $use_dummy_scatter, $feature_config, $nFactoryBinSize
+#****************************************************************************
+sub ldsGen_main
+{
+ ($g_bb, $g_nRamSize, $g_bNeedBL, $g_BBFolder, $g_MakeFilePath) = @_;
+ $g_MakeFile_ref = &FileInfo::GetMakeFileRef($g_MakeFilePath);
+ if ((FileInfo::is("BOARD_VER", "MT6297_FPGA") or FileInfo::is("BOARD_VER", "MT6885_FPGA")) and (FileInfo::get("CUSTOM_FLAVOR") =~/_SAP/)) {
+ $g_bb = &sysUtil::SwitchToClonedChip("MT6297_FPGA");
+ } else {
+ $g_bb = &sysUtil::SwitchToClonedChip($g_bb);
+ }
+ my $strLayout = &GenLDSProcess();
+ return $strLayout;
+}
+sub GenLDSProcess
+{
+ &ldsFrame::CleanCallBackFunc();
+ &ldsFrame::SetCallBackFunc("GetChip", \&GetChip);
+ &ldsFrame::SetCallBackFunc("CollectMemorySetting", \&CollectMemorySetting);
+ &ldsFrame::SetCallBackFunc("SetMemorySegment", \&SetMemorySegment) if(&FileInfo::is_NOR());
+ &ldsFrame::SetCallBackFunc("SetRegionList", \&SetRegionList);
+ &ldsFrame::SetCallBackFunc("GetCustomFolder", \&GetCustomFolder);
+
+ return &ldsFrame::GenLDS(ldsFrame::MAIN);
+}
+sub GetChip #CallBack func
+{
+ return $g_bb;
+}
+sub GetCustomFolder #CallBack func
+{
+ return $g_BBFolder;
+}
+
+sub CollectMemorySetting #CallBack func
+{
+ my ($MEMORYPath, $RegionList_ref, $Index_ref) = @_;
+ my $func = "$g_bb\_MemorySetting";
+ #&sysUtil::sysgen_die("Unsupported Memory Setting on $g_bb! $func must exist.", __FILE__, __LINE__) if not defined &{$func};
+ no strict 'refs';
+ my %Setting;
+ RefineMEMORYWithInput($MEMORYPath, \%Setting);
+ if (defined &{$func}) {
+ &{$func}(\%Setting);
+ }else {
+ Default_MemorySetting(\%Setting);
+ }
+# my $nReservedSize = &GetReservedSize_FromBottomToTop_OnRAM(undef, $RegionList_ref, $Index_ref, "DSP_RX", "DUMMY_END");
+# $Setting{"RESERVED_FOR_DUMMY_END"} = &CommonUtil::Dec2Hex($nReservedSize);
+ $Setting{"CACHEABLE_PREFIX"} = &CommonUtil::Dec2Hex(sysUtil::GetCacheablePrefix($g_bb));
+ $Setting{"NONCACHEABLE_PREFIX"} = &CommonUtil::Dec2Hex(sysUtil::GetNonCacheablePrefix($g_bb));
+
+ return \%Setting;
+}
+
+sub SetMemorySegment #CallBack func
+{
+ my ($MEMORY_SEGMENT_aref) = @_;
+ #nor
+}
+
+sub RefineMEMORYWithInput
+{
+ my ($MEMORYPath, $Setting_href) = @_;
+ my $Memory_aref = &ldsInfo::ParseMEMORY(&CommonUtil::GetFileContent($MEMORYPath));
+ foreach my $info (@$Memory_aref)
+ {
+ if($info->[0] eq "ROM")
+ {
+ my $strBase = GetUsefulInfo($info->[1]);
+ my $strLen = GetUsefulInfo($info->[2]);
+ $Setting_href->{ROM_BASE} = $strBase if(defined $strBase);
+ $Setting_href->{ROM_LEN} = $strLen if(defined $strLen);
+ }
+ elsif($info->[0] eq "RAM")
+ {
+ my $strBase = GetUsefulInfo($info->[1]);
+ my $strLen = GetUsefulInfo($info->[2]);
+# $Setting_href->{RAM_BASE} = $strBase if(defined $strBase);
+# $Setting_href->{RAM_LEN} = $strLen if(defined $strLen);
+ }
+ elsif($info->[0] eq "VRAM")
+ {
+ my $strBase = GetUsefulInfo($info->[1]);
+ my $strLen = GetUsefulInfo($info->[2]);
+# $Setting_href->{VRAM_BASE} = $strBase if(defined $strBase);
+# $Setting_href->{VRAM_LEN} = $strLen if(defined $strLen);
+ }
+ }
+}
+sub GetUsefulInfo
+{
+ my ($strInput) = @_;
+ $strInput =~ s/\[(.+)\]|\s//g;
+ $strInput = undef if($strInput !~ /^0x(\w+)$|(\w+)$/);
+ return $strInput;
+}
+
+sub SetRegionList #CallBack func
+{
+ my ($BasicRegionList_ref, $Index_ref, $MEMORYSetting_href) = @_;
+ my @RegionList;
+ foreach my $item (@$BasicRegionList_ref)
+ {
+ my $strCondition = $item->[$Index_ref->{Condition}];
+ next if($strCondition ne "" and 0 == &FileInfo::EvaluateFeatureOptionCondition($strCondition, $g_MakeFile_ref));
+ my $strCompileOption = $item->[$Index_ref->{CompileOption}];
+ next if($strCompileOption ne "" and (0 == BuildInfo::EvaluateCompileOption($strCompileOption)));
+ push @RegionList, $item;
+ }
+ for(my $i=0; $i<= $#RegionList; $i++)
+ {
+ my $nColumnCount = scalar(@{$RegionList[$i]});
+ for(my $j=0; $j <= $nColumnCount; $j++)
+ {
+ if($RegionList[$i]->[$j] =~/\[(\w+)\]/)
+ {
+ my $strToReplace = $1;
+ no strict 'refs';
+ if ($strToReplace =~ /[ID]SPRAM\d+_(BASE|SIZE)/)
+ {
+ my $template = &GetSPRAM_Info($MEMORYSetting_href, \@RegionList, $Index_ref, $strToReplace);
+ $RegionList[$i]->[$j] =~ s/\[$strToReplace\]/$template/g;
+ }
+ else
+ {
+ my $func = "Gen".$strToReplace;
+ my $template = &{$func}($MEMORYSetting_href, \@RegionList, $Index_ref) if (exists &{$func})
+ or &sysUtil::sysgen_die("$func() doesn't exists!", __FILE__, __LINE__);
+ $RegionList[$i]->[$j] =~ s/\[$strToReplace\]/$template/g;
+ }
+ }
+ }
+ }
+ return \@RegionList;
+}
+
+
+sub GetSPRAM_Info # Fill in RegionList.csv, design for get physical address of SPRAM
+{
+ my ($MEMORYSetting_href, $RegionList_aref, $Index_ref, $strSPRAMName) = @_;
+ my ($strkeyword, $strBaseOrSize);
+
+ if ($strSPRAMName =~ /(\w+)_(BASE|SIZE)/)
+ {
+ ($strkeyword, $strBaseOrSize) = ($1,$2);
+ }
+ else
+ {
+ sysUtil::sysgen_die("unexcept SPRAM name: $strSPRAMName!", __FILE__, __LINE__)
+ }
+
+ if ($strBaseOrSize eq "BASE")
+ {
+ return $MEMORYSetting_href->{$strkeyword}->[0];
+ }
+ else
+ {
+ return &CommonUtil::Dec2Hex( hex($MEMORYSetting_href->{$strkeyword}->[1]) );
+ }
+}
+
+sub GenTX_BASE # Fill in RegionList.csv
+{
+ my ($MEMORYSetting_href, $RegionList_aref, $Index_ref) = @_;
+
+ return &CommonUtil::Dec2Hex(hex(GenRX_BASE($MEMORYSetting_href, $RegionList_aref, $Index_ref)) -
+ hex(GenTX_SIZE($MEMORYSetting_href, $RegionList_aref, $Index_ref)));
+}
+
+##################################
+# RX is base line for above/below output sections
+##################################
+sub GenRX_BASE # Fill in RegionList.csv
+{
+ my ($MEMORYSetting_href, $RegionList_aref, $Index_ref) = @_;
+ return &CommonUtil::Dec2Hex( hex(&GenEXTSRAM_FS_ZI_BASE($g_bb)) - hex(GenRX_SIZE($MEMORYSetting_href, $RegionList_aref, $Index_ref)) );
+}
+sub GenTX_SIZE # Fill in RegionList.csv
+{
+ my ($MEMORYSetting_href, $RegionList_aref, $Index_ref) = @_;
+ my ($nTXLength,$nRXLength) = &sysUtil::DSPTXRX_query_length($g_bb, $g_MakeFile_ref->{custom_flavor});
+ return &CommonUtil::Dec2Hex($nTXLength);
+}
+sub GenRX_SIZE # Fill in RegionList.csv
+{
+ my ($MEMORYSetting_href, $RegionList_aref, $Index_ref) = @_;
+ my ($nTXLength,$nRXLength) = &sysUtil::DSPTXRX_query_length($g_bb, $g_MakeFile_ref->{custom_flavor});
+ return &CommonUtil::Dec2Hex($nRXLength);
+}
+
+sub GenEXTSRAM_END # Fill in RegionList.csv
+{
+ my ($MEMORYSetting_href, $RegionList_aref, $Index_ref) = @_;
+ return &CommonUtil::Dec2Hex( &GetMDTotalSize($g_bb));
+}
+
+sub GenCACHED_EXTSRAM_BASE # Fill in RegionList.csv
+{
+ my ($MEMORYSetting_href, $RegionList_aref, $Index_ref) = @_;
+ return &CommonUtil::Dec2Hex(sysUtil::GetCacheablePrefix($g_bb) |
+ ( hex(GenRX_BASE($MEMORYSetting_href, $RegionList_aref, $Index_ref)) +
+ hex(GenRX_SIZE($MEMORYSetting_href, $RegionList_aref, $Index_ref))));
+}
+
+sub GenEXTSRAM_FS_ZI_BASE # Fill in RegionList.csv
+{
+ my ($MEMORYSetting_href, $RegionList_aref, $Index_ref) = @_;
+ if ($g_bb =~/MT6297$/ && FileInfo::is("PLATFORM", "MT6297")) {
+ return &CommonUtil::Dec2Hex( &GetMDTotalSize($g_bb) - &GenEXTSRAM_FS_ZI_SIZE());
+ } elsif (FileInfo::is("PLATFORM", "MT6880") or FileInfo::is("PLATFORM", "MT6890") or FileInfo::is("PLATFORM", "MT2735")) {
+ return &CommonUtil::Dec2Hex( (0x12F80000 - &GenEXTSRAM_FS_ZI_SIZE()) & 0xFFF00000); #0x12F80000 is the base address of DSP section on EMI view.
+ } else {
+ return &CommonUtil::Dec2Hex( (hex(&GenL1DSP_ZI_BASE()) - &GenEXTSRAM_FS_ZI_SIZE()) & ~0xFFFFF);
+ }
+}
+
+sub GenEXTSRAM_FS_ZI_SIZE
+{
+ my $hexRamdiskSize = 0x1000000;
+ if ( FileInfo::is("FS_RAMDISK", "TRUE"))
+ {
+ if ($g_bb =~ /MT6297$/) {
+ $hexRamdiskSize = 0x2000000; #32MB
+ } else {
+ $hexRamdiskSize = 0x1000000; #16MB
+ }
+ }
+ return $hexRamdiskSize;
+}
+
+sub GenL1DSP_ZI_BASE
+{
+ if ($g_bb =~ /MT6297$/ && FileInfo::is("PLATFORM", "MT6297")) {
+ return &CommonUtil::Dec2Hex( 0x10000000 - hex(&GenL1DSP_ZI_SIZE()));
+ } elsif (FileInfo::is("PLATFORM", "MT6880") or FileInfo::is("PLATFORM", "MT6890") or FileInfo::is("PLATFORM", "MT2735")) {
+ return &CommonUtil::Dec2Hex( 0x1E000000 - hex(&GenL1DSP_ZI_SIZE())); #Move the base of DSP back by 13M
+ } else {
+ return &CommonUtil::Dec2Hex( &GetMDTotalSize($g_bb) - hex(&GenL1DSP_ZI_SIZE()));
+ }
+}
+
+sub GenL1DSP_ZI_SIZE
+{
+ my %BBtbl_DSP_ZI_size;
+ if ($g_bb =~ /MT6297$/ && FileInfo::is("PLATFORM", "MT6297")){
+ %BBtbl_DSP_ZI_size =
+ (
+ 'MT6297' => 0x03D80000, # 61.5 MB
+ 'MT6297_FPGA' => 0x03500000, # 53 MB
+ );
+ } elsif ($g_bb =~ /MT6297$/ && FileInfo::is("PLATFORM", "MT6885")) {
+ %BBtbl_DSP_ZI_size =
+ (
+ 'MT6297' => 0x03E24000, # 62.14MB
+ );
+ } elsif ($g_bb =~ /MT6297$/ && FileInfo::is("PLATFORM", "MT6873")) {
+ %BBtbl_DSP_ZI_size =
+ (
+ 'MT6297' => 0x03BC0000, # 59.75MB
+ );
+ } elsif (FileInfo::is("PLATFORM", "MT6893")) {
+ %BBtbl_DSP_ZI_size =
+ (
+ 'MT6297' => 0x037A4000, # 55.64MB
+ );
+ } elsif (FileInfo::is("PLATFORM", "MT6853") || FileInfo::is("PLATFORM", "MT6833")) {
+ %BBtbl_DSP_ZI_size =
+ (
+ 'MT6297' => 0x02840000, # 40.25MB
+ );
+ } elsif (FileInfo::is("PLATFORM", "MT6880") or FileInfo::is("PLATFORM", "MT6890") or FileInfo::is("PLATFORM", "MT2735")) {
+ %BBtbl_DSP_ZI_size =
+ (
+ 'MT6297' => 0x02AA4000, # 42.6 MB
+ );
+ } else {
+ %BBtbl_DSP_ZI_size =
+ (
+ 'MT6763' => 0x01000000, # 16 MB
+ 'MT6771' => 0x01000000, # 16 MB
+ 'MT6739' => 0x00E00000, # 14 MB
+ 'MT6295M' => 0x02000000, # 32 MB
+ 'MT6297' => 0x02840000, # 40.25MB
+ 'MT6297_FPGA' => 0x03500000, # 53 MB
+ );
+ }
+
+ &sysUtil::sysgen_die("No default DSP ZI total size for this chip $g_bb !", __FILE__, __LINE__)
+ if (!exists $BBtbl_DSP_ZI_size{$g_bb});
+ return &CommonUtil::Dec2Hex($BBtbl_DSP_ZI_size{$g_bb});
+}
+
+sub GenL2SRAM_SIZE
+{
+ my $L2SRAM_Size;
+ if (FileInfo::is("BOARD_VER", "MERCURY_FPGA") or FileInfo::is("BOARD_VER", "MT6885_FPGA")){
+ $L2SRAM_Size = 0x200000; # 2MB
+ } elsif (FileInfo::is("BOARD_VER", "MT6885_EVB")){
+ $L2SRAM_Size = 0x70000; # 448KB
+ } elsif (FileInfo::is("PLATFORM", "MT6833") or FileInfo::is("PLATFORM", "MT6877")){
+ $L2SRAM_Size = 0x8000; # 32KB
+ } else {
+ $L2SRAM_Size = 0x30000; # 192KB
+ }
+ return &CommonUtil::Dec2Hex($L2SRAM_Size);
+}
+
+# what is this for?
+sub GenUSIP_BASE # Fill in RegionList.csv
+{
+ my ($MEMORYSetting_href, $RegionList_aref, $Index_ref) = @_;
+ return &CommonUtil::Dec2Hex( &GetMDTotalSize($g_bb) - &sysUtil::VoLTE_core_query_length($g_bb));
+}
+
+sub GenUSIP_SIZE # Fill in RegionList.csv
+{
+
+ return 0x01000000; #16M, please sync this value with EXTSRAM_FS_ZI in RegionList.cvs
+}
+
+sub GenUROM_SIZE
+{
+ my ($bb) = @_;
+
+ my %UROM_Size;
+ if (FileInfo::is("PLATFORM", "MT6880") or FileInfo::is("PLATFORM", "MT6890") or FileInfo::is("PLATFORM", "MT2735") or FileInfo::is("PLATFORM", "MT2735")){
+ if (FileInfo::isnot("C2K_MODE_SUPPORT", "NONE")){
+ %UROM_Size =
+ (
+ 'MT6297' => 0x02800000, # 40 MB
+ );
+ } else{
+ %UROM_Size =
+ (
+ 'MT6297' => 0x02300000, # 35 MB
+ );
+ }
+ } elsif (FileInfo::is("MTK_MODEM_ARCH", "MT6297")){
+ %UROM_Size =
+ (
+ 'MT6297' => 0x03000000, # 48 MB
+ );
+ } else{
+ &sysUtil::sysgen_die("Current project cannot call GenUROM_SIZE function!", __FILE__, __LINE__);
+ }
+ &sysUtil::sysgen_die("No default UROM size for this chip $bb !", __FILE__, __LINE__) if (!exists $UROM_Size{$bb});
+
+ return $UROM_Size{$bb};
+}
+
+###################################################################################################
+#
+# MemorySetting By chip
+#
+###################################################################################################
+sub GetMDTotalSize
+{ #remember to check shared memory size in GetDefaultSharedMemorySize ( sysGenUtility.pm)
+
+ my ($bb) = @_;
+
+ my %BBtbl_MD_size;
+ if (FileInfo::is("PLATFORM", "MT6880") or FileInfo::is("PLATFORM", "MT6890") or FileInfo::is("PLATFORM", "MT2735")){
+ if (FileInfo::isnot("C2K_MODE_SUPPORT", "NONE")){
+ %BBtbl_MD_size =
+ (
+ 'MT6297' => 0x14000000, # 320 MB
+ );
+ } else {
+ %BBtbl_MD_size =
+ (
+ 'MT6297' => 0x10000000, # 256 MB
+ );
+ }
+ } elsif (FileInfo::isnot("PLATFORM", "MT6297") and FileInfo::isnot("PLATFORM", "MT6885") and FileInfo::isnot("PLATFORM", "MT6893")
+ and FileInfo::isnot("PLATFORM", "MT6873") and FileInfo::is("MTK_MODEM_ARCH", "MT6297")) {
+ %BBtbl_MD_size =
+ (
+ 'MT6297_FPGA' => 0x10000000, # 256 MB
+ 'MT6297' => 0x1D300000, # 467 MB
+ );
+ } else {
+ %BBtbl_MD_size =
+ (
+ 'MT6763' => 0x0F800000, # 248 MB
+ 'MT6739' => 0x07E00000, # 126 MB
+ 'MT6771' => 0x08000000, # 128 MB
+ 'MT6295M' => 0x0F800000, # 248 MB
+ 'MT6297_FPGA' => 0x10000000, # 256 MB
+ 'MT6297' => 0x1E000000, # 480 MB
+ );
+ }
+
+ my $MD_with_ramdisk_default_size = 0x0F800000; # 248 MB
+ my %BBtbl_MD_with_ramdisk_size;
+ if (FileInfo::is("PLATFORM", "MT6880") or FileInfo::is("PLATFORM", "MT6890") or FileInfo::is("PLATFORM", "MT2735")) {
+ %BBtbl_MD_with_ramdisk_size =
+ ( # format: '"chip"' -> 'size'
+ 'MT6297' => 0x16000000, # 352 MB
+ );
+ } elsif (FileInfo::isnot("PLATFORM", "MT6297") and FileInfo::isnot("PLATFORM", "MT6885") and FileInfo::isnot("PLATFORM", "MT6893")
+ and FileInfo::isnot("PLATFORM", "MT6873") and FileInfo::is("MTK_MODEM_ARCH", "MT6297")) {
+ %BBtbl_MD_with_ramdisk_size =
+ ( # format: '"chip"' -> 'size'
+ 'MT6297_FPGA' => 0x10000000, # 256 MB
+ 'MT6297' => 0x1D300000, # 467 MB
+ );
+ } else {
+ %BBtbl_MD_with_ramdisk_size =
+ ( # format: '"chip"' -> 'size'
+ 'MT6763' => 0x0F800000, # 248 MB
+ 'MT6739' => 0x07E00000, # 126 MB
+ 'MT6771' => 0x08000000, # 128 MB
+ 'MT6295M' => 0x0F800000, # 248 MB
+ 'MT6297_FPGA' => 0x10000000, # 256 MB
+ 'MT6297' => 0x1E000000, # 480 MB
+ );
+ }
+
+ &sysUtil::sysgen_die("No default MD total size for this chip $bb !", __FILE__, __LINE__)
+ if (!exists $BBtbl_MD_size{$bb});
+
+ # for ramdisk, MD only load
+ if ( FileInfo::is("FS_RAMDISK", "TRUE")
+ or FileInfo::is("SMART_PHONE_CORE", "MODEM_ONLY"))
+ {
+ return $BBtbl_MD_with_ramdisk_size{$bb} if (exists $BBtbl_MD_with_ramdisk_size{$bb});
+ return $MD_with_ramdisk_default_size;
+ }
+
+ # return default size
+ return $BBtbl_MD_size{$bb};
+}
+
+sub Default_MemorySetting # Called by CollectMemorySetting($Setting_href), fill in MEMORY
+{
+ my ($Setting_href) = @_;
+ my $nTotalSize = GetMDTotalSize($g_bb);
+
+ # ROM, the values could be got by 2-phase linking
+ my $nROMSize = 0x03000000; # 48MB
+ my $nROMBase = 0x90000000;
+ my $nUROMBase = 0x00000000;
+ my $nRAM_BASE = 0x00000000;
+ my $nRAM_SIZE = 0x05400000;
+
+
+ SetExistentValueByDefault($Setting_href, "ROM_BASE", $nROMBase);
+ SetExistentValueByDefault($Setting_href, "ROM_LEN", $nROMSize);
+ SetExistentValueByDefault($Setting_href, "UROM_BASE", $nUROMBase);
+ SetExistentValueByDefault($Setting_href, "UROM_LEN", $nROMSize);
+
+ #MCURO_HWRW
+ SetExistentValueByDefault($Setting_href, "MCURO_HWRW_BASE",$nUROMBase +$nROMSize);
+ SetExistentValueByDefault($Setting_href, "MCURO_HWRW_LEN",0x01c00000);
+
+ # RAM, the values could be got by 2-phase linking
+ SetExistentValueByDefault($Setting_href, "RAM_BASE", hex($Setting_href->{MCURO_HWRW_BASE}) + hex($Setting_href->{MCURO_HWRW_LEN}));
+ SetExistentValueByDefault($Setting_href, "RAM_LEN", $nRAM_SIZE);
+ SetExistentValueByDefault($Setting_href, "VRAM_BASE", $nRAM_BASE| sysUtil::GetCacheablePrefix($g_bb));
+ SetExistentValueByDefault($Setting_href, "VRAM_LEN", &GetMDTotalSize($g_bb));
+ #MCURW_HWRW
+ SetExistentValueByDefault($Setting_href, "MCURW_HWRW_BASE",hex($Setting_href->{RAM_BASE})+hex($Setting_href->{RAM_LEN}));
+ SetExistentValueByDefault($Setting_href, "MCURW_HWRW_LEN",0x02b00000);
+ SetExistentValueByDefault($Setting_href, "DSP_TXRX_BASE",hex($Setting_href->{MCURW_HWRW_BASE})+hex($Setting_href->{MCURW_HWRW_LEN}));
+ SetExistentValueByDefault($Setting_href, "DSP_TXRX_LEN",0x40000);
+ SetExistentValueByDefault($Setting_href, "IOCU2_BASE",0x6CC00000);
+ SetExistentValueByDefault($Setting_href, "IOCU2_LEN",0x00200000);
+ SetExistentValueByDefault($Setting_href, "IOCU3_BASE",0x3CE00000);
+ SetExistentValueByDefault($Setting_href, "IOCU3_LEN",0x00100000);
+ SetExistentValueByDefault($Setting_href, "L2C_LOCK_BASE",0x0cf00000|0x90000000);
+ SetExistentValueByDefault($Setting_href, "L2C_LOCK_LEN",0x00100000);
+
+ $g_nRAM_BASE = $nRAM_BASE ;
+ #Core spesific regions
+ SetExistentValueByDefault($Setting_href, "CORE0_BASE",0x0d000000);
+ SetExistentValueByDefault($Setting_href, "CORE0_LEN", 0x00200000);
+ SetExistentValueByDefault($Setting_href, "CORE1_BASE",0x0d200000);
+ SetExistentValueByDefault($Setting_href, "CORE1_LEN", 0x00200000);
+ SetExistentValueByDefault($Setting_href, "EXTSRAM_FS_BASE",hex(&GenEXTSRAM_FS_ZI_BASE()));
+ SetExistentValueByDefault($Setting_href, "EXTSRAM_FS_LEN", &GenEXTSRAM_FS_ZI_SIZE());
+ SetExistentValueByDefault($Setting_href, "L1DSP_BASE",hex(&GenL1DSP_ZI_BASE()));
+ SetExistentValueByDefault($Setting_href, "L1DSP_LEN",hex(&GenL1DSP_ZI_SIZE()));
+}
+
+sub MT6297_MemorySetting # Called by CollectMemorySetting($Setting_href), fill in MEMORY
+{
+ my ($Setting_href) = @_;
+ my $nTotalSize = GetMDTotalSize($g_bb);
+
+ # ROM, the values could be got by 2-phase linking
+ my $nUROMSize = GenUROM_SIZE($g_bb);
+ my $nUROMBase = 0x00000000;
+
+ my $nROMBase = 0x90000000;
+
+ my $nRAM_BASE = $nUROMBase + $nUROMSize;
+
+ SetExistentValueByDefault($Setting_href, "ROM_BASE", $nROMBase);
+ SetExistentValueByDefault($Setting_href, "ROM_LEN", 0x10000000);
+ SetExistentValueByDefault($Setting_href, "UROM_BASE", $nUROMBase);
+ SetExistentValueByDefault($Setting_href, "UROM_LEN", $nUROMSize);
+
+ # RAM, the values could be got by 2-phase linking
+ SetExistentValueByDefault($Setting_href, "RAM_BASE", hex($Setting_href->{UROM_BASE}) + hex($Setting_href->{UROM_LEN}));
+ SetExistentValueByDefault($Setting_href, "RAM_LEN", &GetMDTotalSize($g_bb));
+ SetExistentValueByDefault($Setting_href, "VRAM_BASE", sysUtil::GetCacheablePrefix($g_bb));
+ SetExistentValueByDefault($Setting_href, "VRAM_LEN", &GetMDTotalSize($g_bb));
+
+ SetExistentValueByDefault($Setting_href, "IOCU2_BASE",0x20000000);
+ SetExistentValueByDefault($Setting_href, "IOCU2_LEN",0x10000000);
+ SetExistentValueByDefault($Setting_href, "IOCU3_BASE",0x30000000);
+ SetExistentValueByDefault($Setting_href, "IOCU3_LEN",0x10000000);
+
+ $g_nRAM_BASE = $nRAM_BASE ;
+ SetExistentValueByDefault($Setting_href, "EXTSRAM_FS_BASE",hex(&GenEXTSRAM_FS_ZI_BASE()));
+ SetExistentValueByDefault($Setting_href, "EXTSRAM_FS_LEN", &GenEXTSRAM_FS_ZI_SIZE());
+ SetExistentValueByDefault($Setting_href, "L1DSP_BASE",hex(&GenL1DSP_ZI_BASE()));
+ SetExistentValueByDefault($Setting_href, "L1DSP_LEN",hex(&GenL1DSP_ZI_SIZE()));
+ SetExistentValueByDefault($Setting_href, "L2SRAM_LEN",hex(&GenL2SRAM_SIZE()));
+}
+
+sub MT6297_FPGA_MemorySetting # Called by CollectMemorySetting($Setting_href), fill in MEMORY
+{
+ my ($Setting_href) = @_;
+ my $nTotalSize = GetMDTotalSize($g_bb);
+
+ # ROM, the values could be got by 2-phase linking
+ my $nUROMSize;
+ if(FileInfo::is("CUSTOM_FLAVOR", "NLWCTG_MODEM") and FileInfo::is("BOARD_VER", "MT6297_FPGA")) {
+ $nUROMSize = 0x01800000; # 24MB
+ }
+ else {
+ $nUROMSize = 0x01B00000; # 27MB
+ }
+ my $nUROMBase = 0x00000000;
+
+ my $nROMBase = 0x90000000;
+ my $nRAM_BASE = 0x00000000;
+
+ SetExistentValueByDefault($Setting_href, "ROM_BASE", $nROMBase);
+ SetExistentValueByDefault($Setting_href, "ROM_LEN", &GetMDTotalSize($g_bb));
+ SetExistentValueByDefault($Setting_href, "UROM_BASE", $nUROMBase);
+ SetExistentValueByDefault($Setting_href, "UROM_LEN", $nUROMSize);
+
+ # RAM, the values could be got by 2-phase linking
+ SetExistentValueByDefault($Setting_href, "RAM_BASE", hex($Setting_href->{UROM_BASE}) + hex($Setting_href->{UROM_LEN}));
+ SetExistentValueByDefault($Setting_href, "RAM_LEN", &GetMDTotalSize($g_bb));
+ SetExistentValueByDefault($Setting_href, "VRAM_BASE", sysUtil::GetCacheablePrefix($g_bb));
+ SetExistentValueByDefault($Setting_href, "VRAM_LEN", &GetMDTotalSize($g_bb));
+
+ SetExistentValueByDefault($Setting_href, "IOCU2_BASE",0x20000000);
+ SetExistentValueByDefault($Setting_href, "IOCU2_LEN",&GetMDTotalSize($g_bb));
+ SetExistentValueByDefault($Setting_href, "IOCU3_BASE",0x30000000);
+ SetExistentValueByDefault($Setting_href, "IOCU3_LEN",&GetMDTotalSize($g_bb));
+
+ $g_nRAM_BASE = $nRAM_BASE ;
+ SetExistentValueByDefault($Setting_href, "EXTSRAM_FS_BASE",hex(&GenEXTSRAM_FS_ZI_BASE()));
+ SetExistentValueByDefault($Setting_href, "EXTSRAM_FS_LEN", &GenEXTSRAM_FS_ZI_SIZE());
+ SetExistentValueByDefault($Setting_href, "L1DSP_BASE",hex(&GenL1DSP_ZI_BASE()));
+ SetExistentValueByDefault($Setting_href, "L1DSP_LEN",hex(&GenL1DSP_ZI_SIZE()));
+}
+
+sub MT6295M_MemorySetting # Called by CollectMemorySetting($Setting_href), fill in MEMORY
+{
+ my ($Setting_href) = @_;
+ my $nTotalSize = GetMDTotalSize($g_bb);
+
+ # ROM, the values could be got by 2-phase linking
+ my $nUROMSize = 0x03000000; # 48MB
+ my $nUROMBase = 0x00000000;
+
+ my $nROMBase = 0x90000000;
+
+ my $nRAM_BASE = $nUROMBase + $nUROMSize;
+
+ SetExistentValueByDefault($Setting_href, "UROM_BASE", $nUROMBase);
+ SetExistentValueByDefault($Setting_href, "UROM_LEN", $nUROMSize);
+ SetExistentValueByDefault($Setting_href, "ROM_BASE", $nROMBase);
+ SetExistentValueByDefault($Setting_href, "ROM_LEN", &GetMDTotalSize($g_bb));
+
+ # RAM, the values could be got by 2-phase linking
+ SetExistentValueByDefault($Setting_href, "RAM_BASE", $nUROMBase + $nUROMSize);
+ SetExistentValueByDefault($Setting_href, "RAM_LEN", &GetMDTotalSize($g_bb));
+ SetExistentValueByDefault($Setting_href, "VRAM_BASE", sysUtil::GetCacheablePrefix($g_bb));
+ SetExistentValueByDefault($Setting_href, "VRAM_LEN", &GetMDTotalSize($g_bb));
+
+ SetExistentValueByDefault($Setting_href, "IOCU2_BASE", 0x20000000);
+ SetExistentValueByDefault($Setting_href, "IOCU2_LEN",&GetMDTotalSize($g_bb));
+ SetExistentValueByDefault($Setting_href, "IOCU3_BASE",0x00000000);
+ SetExistentValueByDefault($Setting_href, "IOCU3_LEN",&GetMDTotalSize($g_bb));
+
+ $g_nRAM_BASE = $nRAM_BASE ;
+
+ SetExistentValueByDefault($Setting_href, "EXTSRAM_FS_BASE",hex(&GenEXTSRAM_FS_ZI_BASE()));
+ SetExistentValueByDefault($Setting_href, "EXTSRAM_FS_LEN", &GenEXTSRAM_FS_ZI_SIZE());
+ SetExistentValueByDefault($Setting_href, "L1DSP_BASE",hex(&GenL1DSP_ZI_BASE()));
+ SetExistentValueByDefault($Setting_href, "L1DSP_LEN",hex(&GenL1DSP_ZI_SIZE()));
+}
+
+sub MT6739_MemorySetting # Called by CollectMemorySetting($Setting_href), fill in MEMORY
+{
+ my ($Setting_href) = @_;
+ my $nTotalSize = GetMDTotalSize($g_bb);
+
+ # ROM, the values could be got by 2-phase linking
+ my $nROMSize = 0x01C00000; # 48MB
+ my $nROMBase = 0x90000000;
+ my $nUROMBase = 0x00000000;
+ my $nRAM_BASE = 0x00000000;
+ my $nRAM_SIZE = 0x02000000;
+
+
+ SetExistentValueByDefault($Setting_href, "ROM_BASE", $nROMBase);
+ SetExistentValueByDefault($Setting_href, "ROM_LEN", $nROMSize);
+ SetExistentValueByDefault($Setting_href, "UROM_BASE", $nUROMBase);
+ SetExistentValueByDefault($Setting_href, "UROM_LEN", $nROMSize);
+
+
+ #MCURO_HWRW
+ SetExistentValueByDefault($Setting_href, "MCURO_HWRW_BASE",$nUROMBase +$nROMSize);
+ SetExistentValueByDefault($Setting_href, "MCURO_HWRW_LEN",0x00E00000);
+
+ # RAM, the values could be got by 2-phase linking
+ SetExistentValueByDefault($Setting_href, "RAM_BASE", hex($Setting_href->{MCURO_HWRW_BASE}) + hex($Setting_href->{MCURO_HWRW_LEN}));
+ SetExistentValueByDefault($Setting_href, "RAM_LEN", $nRAM_SIZE);
+ SetExistentValueByDefault($Setting_href, "VRAM_BASE", $nRAM_BASE| sysUtil::GetCacheablePrefix($g_bb));
+ SetExistentValueByDefault($Setting_href, "VRAM_LEN", &GetMDTotalSize($g_bb));
+ #MCURW_HWRW
+ SetExistentValueByDefault($Setting_href, "MCURW_HWRW_BASE",hex($Setting_href->{RAM_BASE})+hex($Setting_href->{RAM_LEN}));
+ SetExistentValueByDefault($Setting_href, "MCURW_HWRW_LEN",0x00E00000);
+ SetExistentValueByDefault($Setting_href, "DSP_TXRX_BASE",hex($Setting_href->{MCURW_HWRW_BASE})+hex($Setting_href->{MCURW_HWRW_LEN}));
+ SetExistentValueByDefault($Setting_href, "DSP_TXRX_LEN",0x40000);
+ SetExistentValueByDefault($Setting_href, "IOCU2_BASE", $nRAM_BASE|0x60000000);
+ SetExistentValueByDefault($Setting_href, "IOCU2_LEN",&GetMDTotalSize($g_bb));
+# SetExistentValueByDefault($Setting_href, "IOCU2_BASE",((hex($Setting_href->{DSP_TXRX_BASE})+hex($Setting_href->{DSP_TXRX_LEN})+0xfffff)&0x0ff00000)|0x60000000);
+# SetExistentValueByDefault($Setting_href, "IOCU2_LEN",0x00100000);
+ SetExistentValueByDefault($Setting_href, "IOCU3_BASE",(hex($Setting_href->{IOCU2_BASE})+hex($Setting_href->{IOCU2_LEN}))&0x0fffffff|0x30000000);
+ SetExistentValueByDefault($Setting_href, "IOCU3_LEN",0x00100000);
+ SetExistentValueByDefault($Setting_href, "L2C_LOCK_BASE",(hex($Setting_href->{IOCU3_BASE})+hex($Setting_href->{IOCU3_LEN}))&0x0fffffff|0x90000000);
+ SetExistentValueByDefault($Setting_href, "L2C_LOCK_LEN",0x00100000);
+
+ $g_nRAM_BASE = $nRAM_BASE ;
+ #Core spesific regions
+ SetExistentValueByDefault($Setting_href, "CORE0_BASE",(hex($Setting_href->{L2C_LOCK_BASE})+hex($Setting_href->{L2C_LOCK_LEN}))&0x0fffffff);
+ SetExistentValueByDefault($Setting_href, "CORE0_LEN", 0x00100000);
+ SetExistentValueByDefault($Setting_href, "CORE1_BASE",hex($Setting_href->{CORE0_BASE})+hex($Setting_href->{CORE0_LEN}));
+ SetExistentValueByDefault($Setting_href, "CORE1_LEN", 0x00100000);
+ SetExistentValueByDefault($Setting_href, "DRDI_BASE",(hex($Setting_href->{CORE1_BASE})+hex($Setting_href->{CORE1_LEN}))| sysUtil::GetCacheablePrefix($g_bb));
+ SetExistentValueByDefault($Setting_href, "DRDI_LEN", 0x00200000);
+ SetExistentValueByDefault($Setting_href, "EXTSRAM_FS_BASE",hex(&GenEXTSRAM_FS_ZI_BASE()));
+ SetExistentValueByDefault($Setting_href, "EXTSRAM_FS_LEN", &GenEXTSRAM_FS_ZI_SIZE());
+ SetExistentValueByDefault($Setting_href, "L1DSP_BASE",hex(&GenL1DSP_ZI_BASE()));
+ SetExistentValueByDefault($Setting_href, "L1DSP_LEN",hex(&GenL1DSP_ZI_SIZE()));
+}
+
+sub SetExistentValueByDefault
+{
+ my ($Setting_href, $strKey, $nValue) = @_;
+ $Setting_href->{$strKey} = (defined $Setting_href->{$strKey}) ?
+ $Setting_href->{$strKey} : CommonUtil::Dec2Hex($nValue);
+}
+sub GetPredefinedValue
+{ # to collocate with AAPMC
+ my ($Setting_href, $strFirst, $strSecond, $nDefaultValue) = @_;
+ my $nValue = $nDefaultValue;
+ if(defined $Setting_href->{$strFirst}) #1st Priority
+ {
+ $nValue = hex($Setting_href->{$strFirst});
+ }
+ elsif(defined $Setting_href->{$strSecond}) #2nd Priority
+ {
+ $nValue = hex($Setting_href->{$strSecond});
+ }
+ return $nValue;
+
+}
+
+
+
+
+##############################################
+# work around for 90 build pass
+##############################################
+
+sub GenDUMMY_END # Fill in RegionList.csv
+{
+ return 0;
+}
+
+
+