| #ifndef __BTDMA_PRIVATE_H__ |
| #define __BTDMA_PRIVATE_H__ |
| #include "reg_base.h" |
| |
| #if defined(__MD97P__) |
| #define BTDMA_BASE_ADDR BASE_ADDR_MCORE_MML1_DSPBTDMA |
| #else |
| #define BTDMA_BASE_ADDR BASE_MADDR_MCOREPERI_INFRA_BTDMA |
| #endif |
| /*************************************************** |
| * |
| * |
| * MPU |
| * |
| * |
| ***************************************************/ |
| #if !defined(MT6297)//defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) |
| |
| #define BTDMA_MPU_ENABLE_OFFSET 0x0 |
| #define BTDMA_MPU_TYPE_OFFSET 0x4 |
| #define BTDMA_MPU_REGION_AXI_START_OFFSET 0x8 |
| #define BTDMA_MPU_REGION_AXI_END_OFFSET 0x48 |
| #define BTDMA_MPU_REGION_DBUS_START_OFFSET 0x20 |
| #define BTDMA_MPU_REGION_DBUS_END_OFFSET 0x60 |
| |
| #define BTDMA_MPU_ENABLE_ADDR (BTDMA_BASE_ADDR + BTDMA_MPU_ENABLE_OFFSET) |
| #define BTDMA_MPU_TYPE_ADDR (BTDMA_BASE_ADDR + BTDMA_MPU_TYPE_OFFSET) |
| #define BTDMA_MPU_REGION_AXI_START_ADDR (BTDMA_BASE_ADDR + BTDMA_MPU_REGION_AXI_START_OFFSET) |
| #define BTDMA_MPU_REGION_AXI_END_ADDR (BTDMA_BASE_ADDR + BTDMA_MPU_REGION_AXI_END_OFFSET) |
| #define BTDMA_MPU_REGION_DBUS_START_ADDR (BTDMA_BASE_ADDR + BTDMA_MPU_REGION_DBUS_START_OFFSET) |
| #define BTDMA_MPU_REGION_DBUS_END_ADDR (BTDMA_BASE_ADDR + BTDMA_MPU_REGION_DBUS_END_OFFSET) |
| #define BTDMA_MPU_AXI_CHANNEL_NUM 6 |
| #define BTDMA_MPU_DBUS_CHANNEL_NUM 6 |
| |
| |
| |
| #else |
| #define BTDMA_MPU_ENABLE_OFFSET 0x0 |
| #define BTDMA_MPU_REGION_AXI_START_OFFSET 0x4 |
| #define BTDMA_MPU_REGION_AXI_END_OFFSET 0x14 |
| #define BTDMA_MPU_REGION_DBUS_START_OFFSET 0x44 |
| #define BTDMA_MPU_REGION_DBUS_END_OFFSET 0x54 |
| |
| |
| |
| #define BTDMA_MPU_ENABLE_ADDR (BTDMA_BASE_ADDR + BTDMA_MPU_ENABLE_OFFSET) |
| #define BTDMA_MPU_REGION_AXI_START_ADDR (BTDMA_BASE_ADDR + BTDMA_MPU_REGION_AXI_START_OFFSET) |
| #define BTDMA_MPU_REGION_AXI_END_ADDR (BTDMA_BASE_ADDR + BTDMA_MPU_REGION_AXI_END_OFFSET) |
| #define BTDMA_MPU_REGION_DBUS_START_ADDR (BTDMA_BASE_ADDR + BTDMA_MPU_REGION_DBUS_START_OFFSET) |
| #define BTDMA_MPU_REGION_DBUS_END_ADDR (BTDMA_BASE_ADDR + BTDMA_MPU_REGION_DBUS_END_OFFSET) |
| #define BTDMA_MPU_AXI_CHANNEL_NUM 4 |
| #define BTDMA_MPU_DBUS_CHANNEL_NUM 4 |
| #endif |
| /*************************************************** |
| * |
| * |
| * Exception |
| * |
| * |
| ***************************************************/ |
| |
| #if !defined(MT6297)// defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) |
| |
| |
| |
| #define BTDMA_ERR_STS_ALL_OFFSET 0x19c |
| #define BTDMA_TRIGGER_EXCEPTION_STS_OFFSET 0x1a0 |
| #define BTDMA_DESC_EXCEPTION_STS_OFFSET 0x1a4 |
| #define BTDMA_JOB_EXCEPTION_STS_OFFSET 0x1a8 |
| #define BTDMA_CRC_EXCEPTION_STS_OFFSET 0x1ac |
| #define BTDMA_AXI_EXCEPTION_STS_OFFSET 0x1b0 |
| #define BTDMA_DBUS_EXCEPTION_STS_OFFSET 0x1b4 |
| |
| #else |
| |
| #define BTDMA_ERR_STS_ALL_OFFSET 0x194 |
| #define BTDMA_TRIGGER_EXCEPTION_STS_OFFSET 0x198 |
| #define BTDMA_DESC_EXCEPTION_STS_OFFSET 0x19c |
| #define BTDMA_JOB_EXCEPTION_STS_OFFSET 0x1a0 |
| #define BTDMA_CRC_EXCEPTION_STS_OFFSET 0x1a4 |
| #define BTDMA_AXI_EXCEPTION_STS_OFFSET 0x1a8 |
| #define BTDMA_DBUS_EXCEPTION_STS_OFFSET 0x1ac |
| #endif |
| |
| |
| #define BTDMA_ERR_STS_ALL_ADDR (BTDMA_BASE_ADDR + BTDMA_ERR_STS_ALL_OFFSET) |
| #define BTDMA_TRIGGER_EXCEPTION_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_TRIGGER_EXCEPTION_STS_OFFSET) |
| #define BTDMA_DESC_EXCEPTION_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_DESC_EXCEPTION_STS_OFFSET) |
| #define BTDMA_JOB_EXCEPTION_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_JOB_EXCEPTION_STS_OFFSET) |
| #define BTDMA_CRC_EXCEPTION_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_CRC_EXCEPTION_STS_OFFSET) |
| #define BTDMA_AXI_EXCEPTION_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_AXI_EXCEPTION_STS_OFFSET) |
| #define BTDMA_DBUS_EXCEPTION_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_DBUS_EXCEPTION_STS_OFFSET) |
| |
| #define BTDMA_TRIGGER_BUSY_ERROR_POS 0 |
| #define BTDMA_TRIGGER_NO_JOB_ERROR_POS 8 |
| #define BTDMA_DESC_MPU_VIOLATE_ERR_POS 0 |
| #define BTDMA_DESC_MPU_OVERLAP_ERR_POS 8 |
| #define BTDMA_JOB_MPU_DEST_VIOLATE_ERR_POS 0 |
| #define BTDMA_JOB_MPU_SRC_VIOLATE_ERR_POS 8 |
| #define BTDMA_JOB_MPU_DEST_OVERLAP_ERR_POS 16 |
| #define BTDMA_JOB_MPU_SRC_OVERLAP_ERR_POS 24 |
| #define BTDMA_CRC_ERROR_POS 0 |
| |
| |
| |
| /*************************************************** |
| * |
| * |
| * Signal |
| * |
| * |
| ***************************************************/ |
| #if !defined(MT6297)//defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) |
| |
| |
| #define BTDMA_SIGNAL_CTRL0_OFFSET 0x184 |
| #define BTDMA_SIGNAL_CTRL1_OFFSET 0x188 |
| #define BTDMA_SIGNAL_CTRL2_OFFSET 0x18c |
| |
| #define BTDMA_BOOTDONE_STS_OFFSET 0x190 |
| #define BTDMA_COMPLETE_STS_OFFSET 0x194 |
| #define BTDMA_INTERRUPT_STS_OFFSET 0x198 |
| |
| |
| #define BTDMA_SIGNAL_CTRL0_ADDR (BTDMA_BASE_ADDR + BTDMA_SIGNAL_CTRL0_OFFSET) |
| #define BTDMA_SIGNAL_CTRL1_ADDR (BTDMA_BASE_ADDR + BTDMA_SIGNAL_CTRL1_OFFSET) |
| #define BTDMA_SIGNAL_CTRL2_ADDR (BTDMA_BASE_ADDR + BTDMA_SIGNAL_CTRL2_OFFSET) |
| |
| #define BTDMA_BOOTDONE_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_BOOTDONE_STS_OFFSET) |
| #define BTDMA_COMPLETE_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_COMPLETE_STS_OFFSET) |
| #define BTDMA_INTERRUPT_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_INTERRUPT_STS_OFFSET) |
| |
| |
| #else |
| #define BTDMA_SIGNAL_CTRL0_OFFSET 0x180 |
| #define BTDMA_SIGNAL_CTRL1_OFFSET 0x184 |
| |
| #define BTDMA_BOOTDONE_STS_OFFSET 0x188 |
| #define BTDMA_COMPLETE_STS_OFFSET 0x190 |
| #define BTDMA_INTERRUPT_STS_OFFSET 0x18c |
| |
| |
| |
| #define BTDMA_SIGNAL_CTRL0_ADDR (BTDMA_BASE_ADDR + BTDMA_SIGNAL_CTRL0_OFFSET) |
| #define BTDMA_SIGNAL_CTRL1_ADDR (BTDMA_BASE_ADDR + BTDMA_SIGNAL_CTRL1_OFFSET) |
| |
| #define BTDMA_BOOTDONE_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_BOOTDONE_STS_OFFSET) |
| #define BTDMA_COMPLETE_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_COMPLETE_STS_OFFSET) |
| #define BTDMA_INTERRUPT_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_INTERRUPT_STS_OFFSET) |
| #endif |
| |
| /*************************************************** |
| * |
| * |
| * Others |
| * |
| * |
| ***************************************************/ |
| #if !defined(MT6297)//defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) |
| |
| #define BTDMA_CRC_CTRL_OFFSET 0x88 |
| #define BTDMA_DMA_CTRL_OFFSET 0x8c |
| #define BTDMA_DMA_STS0_OFFSET 0x90 |
| #define BTDMA_DMA_STS1_OFFSET 0x94 |
| #else |
| #define BTDMA_CRC_CTRL_OFFSET 0x84 |
| #define BTDMA_DMA_CTRL_OFFSET 0x88 |
| #define BTDMA_DMA_STS0_OFFSET 0x8c |
| #define BTDMA_DMA_STS1_OFFSET 0x90 |
| |
| |
| #endif |
| #define BTDMA_CRC_CTRL_ADDR (BTDMA_BASE_ADDR + BTDMA_CRC_CTRL_OFFSET) |
| #define BTDMA_DMA_CTRL_ADDR (BTDMA_BASE_ADDR + BTDMA_DMA_CTRL_OFFSET) |
| #define BTDMA_DMA_STS0_ADDR (BTDMA_BASE_ADDR + BTDMA_DMA_STS0_OFFSET) |
| #define BTDMA_DMA_STS1_ADDR (BTDMA_BASE_ADDR + BTDMA_DMA_STS1_OFFSET) |
| |
| |
| |
| |
| #if !defined(MT6297)//defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) |
| |
| #define BTDMA_DESC_CTRL_0_PRI0_START_OFFSET 0xA4 |
| #define BTDMA_DESC_CTRL_0_PRI0_TRIG_OFFSET 0xC4 |
| |
| #define BTDMA_DESC_CTRL_0_PRI0_FETCH_OFFSET 0xE4 |
| #define BTDMA_DESC_CTRL_0_PRI0_ONGOING_OFFSET 0x104 |
| |
| #define BTMDA_DESC_CTRL_0_PRI0_R_DATA_TRAN_OFFSET 0x124 |
| #define BTMDA_DESC_CTRL_0_PRI0_W_DATA_TRAN_OFFSET 0x144 |
| #define BTDMA_DESC_STS_OFFSET 0x164 |
| #define BTDMA_DESC_STS_4_OFFSET 0x164 |
| |
| #else |
| #define BTDMA_DESC_CTRL_0_PRI0_START_OFFSET 0xA0 |
| #define BTDMA_DESC_CTRL_0_PRI0_TRIG_OFFSET 0xC0 |
| |
| #define BTDMA_DESC_CTRL_0_PRI0_FETCH_OFFSET 0xE0 |
| #define BTDMA_DESC_CTRL_0_PRI0_ONGOING_OFFSET 0x100 |
| |
| #define BTMDA_DESC_CTRL_0_PRI0_R_DATA_TRAN_OFFSET 0x120 |
| #define BTMDA_DESC_CTRL_0_PRI0_W_DATA_TRAN_OFFSET 0x140 |
| #define BTDMA_DESC_STS_OFFSET 0x160 |
| #define BTDMA_DESC_STS_4_OFFSET 0x160 |
| #endif |
| |
| |
| |
| |
| |
| #define BTDMA_DESC_CTRL_0_PRI0_START_ADDR (BTDMA_BASE_ADDR + BTDMA_DESC_CTRL_0_PRI0_START_OFFSET) |
| #define BTDMA_DESC_CTRL_0_PRI0_TRIG_ADDR (BTDMA_BASE_ADDR + BTDMA_DESC_CTRL_0_PRI0_TRIG_OFFSET) |
| |
| #define BTDMA_DESC_CTRL_0_PRI0_FETCH_ADDR (BTDMA_BASE_ADDR + BTDMA_DESC_CTRL_0_PRI0_FETCH_OFFSET) |
| #define BTDMA_DESC_CTRL_0_PRI0_ONGOING_ADDR (BTDMA_BASE_ADDR + BTDMA_DESC_CTRL_0_PRI0_ONGOING_OFFSET) |
| |
| #define BTMDA_DESC_CTRL_0_PRI0_R_DATA_TRAN_ADDR (BTDMA_BASE_ADDR + BTMDA_DESC_CTRL_0_PRI0_R_DATA_TRAN_OFFSET) |
| #define BTMDA_DESC_CTRL_0_PRI0_W_DATA_TRAN_ADDR (BTDMA_BASE_ADDR + BTMDA_DESC_CTRL_0_PRI0_W_DATA_TRAN_OFFSET) |
| #define BTDMA_DESC_STS_ADDR (BTDMA_BASE_ADDR + BTDMA_DESC_STS_OFFSET) |
| #define BTDMA_DESC_STS_4_ADDR (BTDMA_BASE_ADDR + BTDMA_DESC_STS_4_OFFSET) |
| |
| |
| #define BTDMA_DESC_STS_4_CMD_STS_POS 16 |
| #define BTDMA_BUFFER_SIZE 10 |
| #define BTDMA_IDLE_SIGNAL 0 |
| #define BTDMA_PRIO_CHAIN_NUM 8 |
| #define BTDMA_VALID_OWN 0xA5 |
| #define BTDMA_JOB_MAXIMUM_LEN 512 |
| |
| /******************************************************************* |
| * |
| * |
| * Marco about Number |
| * __________________________________________________________ |
| * | | | | | |
| * | Pattern | Priority | Number1 | Number2 | |
| * | (8-bit) | (3-bit) | (2-bit) | (19-bit) | |
| * |_________________|____________|___________|_______________| |
| * |
| *******************************************************************/ |
| #define BTDMA_NUMBER_NUMBER2_BIT_NUM 19 |
| #define BTDMA_NUMBER_NUMBER1_BIT_NUM 2 |
| #define BTDMA_NUMBER_PRIORITY_BIT_NUM 3 |
| #define BTDMA_NUMBER_PATTERN_BIT_NUM 8 |
| |
| #define BTDMA_NUMBER_NUMBER2_OFFSET 0 |
| #define BTDMA_NUMBER_NUMBER1_OFFSET 19 |
| #define BTDMA_NUMBER_PRIORITY_OFFSET 21 |
| #define BTDMA_NUMBER_PATTERN_OFFSET 24 |
| |
| #define BTDMA_NUMBER_NUMBER2_BIT_MASK 0x7FFFF |
| #define BTDMA_NUMBER_NUMBER1_BIT_MASK 0x180000 |
| #define BTDMA_NUMBER_PRIORITY_BIT_MASK 0xE00000 |
| #define BTDMA_NUMBER_PATTERN_BIT_MASK 0XFF000000 |
| |
| #endif |