| #include "elm.h" |
| #include "drv_comm.h" |
| #include "us_timer.h" |
| #include "kal_public_api.h" |
| #include "kal_hrt_api.h" |
| #include "intrCtrl.h" |
| #include "drv_mdap_interface.h" //for show MD_DVFS_CON in trace |
| |
| #if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__)) |
| // for profiling ELM log |
| #include "TrcMod.h" //for L1 Trace API |
| #endif |
| |
| /** ----- Register definition ------ **/ |
| |
| |
| // MDMCU ELM |
| #define REG_MCUSYS_EMI_ELM_CODA_VERSION (BASE_ADDR_MCUSYS_ELM_EMI+0x0) |
| #define REG_MCUSYS_EMI_ELM_EN_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x8) |
| #define REG_MCUSYS_EMI_ELM_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0xC) |
| #define ELM_MODE(x) ((x)<<4) |
| #define ELM_MODE_MASK 0x3 |
| #define ELM_AO_DECODE(x) ((x)<<13) |
| #define ELM_DECODE_FROM_AO 1 |
| #define ELM_DECODE_FROM_APB 0 |
| #define ELM_MODE_ID_SEL(x) (x<<8) |
| #define ELM_MODE_ID_MASK 0xC //clear ID2/3 only |
| #define ELM_ID_RW(rw, id) (rw<<id) //rw: 0->r; 1->w; id: 0, 1, 2, 3 |
| #define ELM_TOTAL_LAT_WEIGHT_BLOCK(x) (x<<20) //[22:20] |
| #define REG_MCUSYS_EMI_ELM_LAT_CNT_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x10) |
| #define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x20) |
| |
| #define ALEN(x) ((x)<<28) //4'hf |
| #define ASIZE(x) ((x)<<24) //3'h7 |
| #define AULTRA(x) ((x)<<20) //2'h3 |
| #define ABUST(x) ((x)<<16) //2'h3 |
| #define AID(x) ((x)<<0) //12'h1FFF |
| #define MASTER_DEFAULT_MASK 0x1FFF //defualt value |
| #define MASTER_ALL_MASK 0x3 //IA: 0x0, MMU: 0x1, USIP: 0x2 |
| #define MASTER_MDMCU 0x0 //MDMCU(Incluing IA & MMU) |
| #define MASTER_MDMCU_MASK 0x1FFD |
| #define MASTER_USIP 0x2 //USIP -> 0x2 |
| #define MASTER_USIP_MASK 0x1FFC |
| |
| |
| #define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x24) |
| #define ELM_AO_CONTROL_DEFAULT 0xF7331FFF |
| |
| #define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x28) |
| #define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x2C) |
| #define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x30) |
| #define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x34) |
| #define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x38) |
| #define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x3C) |
| #define REG_MCUSYS_EMI_ELM_ID0_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x40) |
| #define REG_MCUSYS_EMI_ELM_ID1_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x44) |
| #define REG_MCUSYS_EMI_ELM_CNT0 (BASE_ADDR_MCUSYS_ELM_EMI+0x50) |
| #define REG_MCUSYS_EMI_ELM_CNT1 (BASE_ADDR_MCUSYS_ELM_EMI+0x54) |
| #define REG_MCUSYS_EMI_ELM_CNT2 (BASE_ADDR_MCUSYS_ELM_EMI+0x58) |
| #define REG_MCUSYS_EMI_ELM_CNT3 (BASE_ADDR_MCUSYS_ELM_EMI+0x5C) |
| #define REG_MCUSYS_EMI_ELM_OVERRUN_CNT_ST (BASE_ADDR_MCUSYS_ELM_EMI+0x60) |
| #define REG_MCUSYS_EMI_ELM_INT_STATUS (BASE_ADDR_MCUSYS_ELM_EMI+0x64) |
| |
| #define REG_MCUSYS_EMI_ELM_ID0_URG_FLGA_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x700) |
| #define REG_MCUSYS_EMI_ELM_ID0_URG_FLGA_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x704) |
| #define REG_MCUSYS_EMI_ELM_ID1_URG_FLGA_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x70C) |
| #define REG_MCUSYS_EMI_ELM_ID1_URG_FLGA_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x710) |
| #define REG_MCUSYS_EMI_ELM_URG_IDLE_CLR_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x718) |
| |
| |
| |
| |
| |
| #define INT_MASK_ALL 0x3F |
| #define INT_MASK_LAT 0xF |
| #define INT_MASK_WC 0x30 |
| #define ID0_AVG_LAT_INT (1<<0) |
| #define ID0_TOT_LAT_INT (1<<1) |
| #define ID1_AVG_LAT_INT (1<<2) |
| #define ID1_TOT_LAT_INT (1<<3) |
| #define ID2_TOT_WC_INT (1<<4) |
| #define ID3_TOT_WC_INT (1<<5) |
| #define REG_MCUSYS_EMI_ELM_AO_STATUS0 (BASE_ADDR_MCUSYS_ELM_EMI+0x68) |
| #define DECODE_ID0(x) ((x)<<0) |
| #define ELM_READ (0<<4) |
| #define ELM_WRITE (1<<4) |
| #define ELM_ALL_MASTER (0<<2) |
| #define ELM_MDMCU_ONLY (1<<2) |
| #define ELM_USIP_ONLY (2<<2) |
| #define ELM_ALL_PRIO (0<<0) |
| #define ELM_PRE_ULTRA (1<<0) |
| #define ELM_ULTRA (2<<0) |
| #define LAT_TH_ID0_NORMAL(x) ((x)<<5) |
| #define LAT_TH_ID1_NORMAL(x) ((x)<<15) |
| #define ELM_ACCURACY(x) ((x)<<29) |
| #define ELM_unit_25us 2 |
| #define ELM_unit_100us 4 |
| #define ELM_ENABLE (1<<27) |
| #define ELM_DISABLE (0<<27) |
| #define ELM_IDLE_ENABLE (1<<28) |
| #define ELM_IDLE_DISABLE (0<<28) |
| #define REG_MCUSYS_EMI_ELM_AO_STATUS1 (BASE_ADDR_MCUSYS_ELM_EMI+0x6C) |
| #define ELM_INT_MASK(x) ((x)<<0) |
| #define LAT_INT_MASK_ALL 0xF |
| #define LAT_INT_UNMASK_ALL 0x0 |
| #define EMI_BLOCK(x) ((x)<<4) |
| #define E_NOT_MASK 0 |
| #define E_MASK 1 |
| #define ELM_DURATION(x) ((x-1)<<5) |
| #define DECODE_ID1(x) ((x)<<12) |
| /* #define usage same as DECODE_ID0 */ |
| #define ELM_EMI_TOP_BLOCK(x) ((x)<<31) |
| #define E_TOP_MASK 1 |
| #define E_TOP_NOT_MASK 0 |
| #define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x70) |
| #define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x74) |
| #define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x78) |
| #define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x7C) |
| #define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x80) |
| #define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x84) |
| #define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x88) |
| #define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x8C) |
| #define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x90) |
| #define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x94) |
| #define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x98) |
| #define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x9C) |
| #define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA0) |
| #define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA4) |
| #define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA8) |
| #define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xAC) |
| #define REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB0) |
| #define REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB4) |
| #define REG_MCUSYS_EMI_ELM_ID0_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xC0) |
| #define REG_MCUSYS_EMI_ELM_ID0_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xC4) |
| #define REG_MCUSYS_EMI_ELM_ID0_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xC8) |
| #define REG_MCUSYS_EMI_ELM_ID0_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xCC) |
| #define REG_MCUSYS_EMI_ELM_ID1_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xD0) |
| #define REG_MCUSYS_EMI_ELM_ID1_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xD4) |
| #define REG_MCUSYS_EMI_ELM_ID1_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xD8) |
| #define REG_MCUSYS_EMI_ELM_ID1_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xDC) |
| #define REG_MCUSYS_EMI_ELM_CNT4 (BASE_ADDR_MCUSYS_ELM_EMI+0xE0) |
| #define REG_MCUSYS_EMI_ELM_CNT5 (BASE_ADDR_MCUSYS_ELM_EMI+0xE4) |
| #define REG_MCUSYS_EMI_ELM_AO_STATUS2 (BASE_ADDR_MCUSYS_ELM_EMI+0xF0) |
| #define ELM_WC_INT_MASK(x) ((x)<<0) |
| #define WC_INT_MASK_ALL 0x3 |
| #define WC_INT_UNMASK_ALL 0x0 |
| #define LAT_TH_ID0_BLOCK(x) ((x)<<4) |
| #define LAT_TH_ID1_BLOCK(x) ((x)<<16) |
| #if 0 |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| #endif |
| #define REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x510) |
| #define REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x514) |
| #define REG_MCUSYS_EMI_ELM_WORDCNT_DURATION (BASE_ADDR_MCUSYS_ELM_EMI+0x528) |
| #define ELM_WC_ACCURACY(x) ((x)<<4) //[31:4] |
| #define ELM_WC_DURATION(x) ((x)<<0) // [3:0] |
| //wc duration length = (WORDCNT_DURATION+1)*(WORDCNT_ACCURACY+1) us |
| |
| #define REG_MCUSYS_EMI_ELM_INT_FRCVAL (BASE_ADDR_MCUSYS_ELM_EMI+0x530) |
| #define REG_MCUSYS_EMI_ELM_SUBWINDOW_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x534) |
| |
| #define REG_MCUSYS_EMI_ELM_ID0_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x538) |
| #define REG_MCUSYS_EMI_ELM_ID1_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x53C) |
| #define REG_MCUSYS_EMI_ELM_ID2_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x540) |
| #define REG_MCUSYS_EMI_ELM_ID3_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x544) |
| |
| #define REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x600) |
| #define REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x604) |
| #define REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x608) |
| #define REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x60C) |
| #define REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x610) |
| #define REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x614) |
| #define REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x618) |
| #define REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x61C) |
| #define REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL 0x3fff |
| // MDINFRA ELM_A |
| #define REG_MDINFRA_ELM_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0xC) |
| #define REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x70) |
| #define REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x74) |
| #define REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x78) |
| #define REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x7C) |
| #define REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x80) |
| #define REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x84) |
| #define REG_MDINFRA_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB0) |
| #define REG_MDINFRA_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB4) |
| #define REG_MDINFRA_ELM_ID0_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x40) |
| #define REG_MDINFRA_ELM_ID1_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x44) |
| #define REG_MDINFRA_ELM_INT_STATUS (BASE_ADDR_MDINFRA_ELM+0x64) |
| #define REG_MDINFRA_ELM_ID2_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x510) |
| #define REG_MDINFRA_ELM_ID3_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x514) |
| #define REG_MDINFRA_ELM_WORDCNT_DURATION (BASE_ADDR_MDINFRA_ELM+0x528) |
| #define REG_MDINFRA_ELM_INT_FRCVAL (BASE_ADDR_MDINFRA_ELM+0x530) |
| |
| //AO Register in MDPERIMISC |
| #define REG_MDMCU_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x70) //0xA0060070 |
| #define REG_MDMCU_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x74) //0xA0060074 |
| #define REG_MDMCU_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x90) //0xA0060090 |
| #define REG_MDINFRA_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x78) //0xA0060078 |
| #define REG_MDINFRA_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x7C) //0xA006007C |
| #define REG_MDINFRA_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x94) //0xA0060094 |
| |
| /** ----- AP debugging register definition ------ **/ |
| #if 1 //defined(MT3967) |
| #define AP_VCORE_DVFS_CURRENT (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD44) // current dvfsrc level |
| #define AP_VCORE_DVFS_TARGET (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD48) |
| #define AP_VCORE_DVFS_LAST (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xB08) // last dvfsrc level |
| |
| // SPM should sw config to record the time into register. Please double confirm with AP SPM owner in each project |
| #define AP_DVFS_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x630) |
| #define AP_DDREN_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x634) |
| #define AP_SYSTIMER_TICK (volatile kal_uint32 *)(0xC0006000+0x1B4) |
| #endif |
| |
| #include "sleepdrv_interface.h" |
| |
| // ELM Set Mode (HW/SW Mode) |
| enum { |
| ELM_MODE_0 = 0, // ID0 trans_cnt, ID1 trans_cnt, ID0_lat_cnt, ID1_lat_cnt, id2_word_cnt, id3_word_cnt |
| ELM_MODE_2 = 2, // ID0 trans_cnt, ID1 trans_cnt, ID2 trans_cnt, ID3 trans_cnt, NA, NA |
| }; |
| |
| //MCUSYS fixed clock 650/3 Mhz, 1T ~ 4.6ns |
| #define ELM_TRANS2NS(X) ((((((X)*1000)<<4)/(650/3))>>4)) |
| #define ELM_NS2TRAN(X) ((((X)*(650/3))/1000)) |
| |
| |
| //MDINFRA fixed clock 100Mhz, 1T = 10ns |
| #define ELM_MDINFRA_TRANS2NS(X) (((X)*10)) |
| #define ELM_MDINFRA_NS2TRAN(X) (((X)/10)) |
| |
| typedef enum { |
| E_ELM_WC_B = 0, |
| E_ELM_WC_KB = 1, |
| E_ELM_WC_MB = 2, |
| E_ELM_WC_GB = 3, |
| } ELM_WC_UNIT; |
| //XB, X can be K(KB), M(MB), G(GB), using ELM_WC_UNIT to represent it. |
| #define ELM_XB2WC(X, unit) (X<<(10*unit))>>2 |
| #define ELM_WC2XB(X, unit) ((X<<2)>>(10*unit)) |
| |
| //for assert information |
| #define KAL_ERROR_EMI_ELM_EXCEP 0x4100 |
| #define KAL_ERROR_INFRA_ELM_EXCEP 0x4102 |
| |
| #define KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD 0x4200 |
| |
| #if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__)) |
| #define __ELM_TRACE__ |
| #define ELM_IF_DEF_TRACE(def_statement, undef_statement) def_statement |
| #else /* __MCU_DORMANT_MODE__ */ |
| #define ELM_IF_DEF_TRACE(def_statement, undef_statement) undef_statement |
| #endif |
| |
| #define ELM_2ND_ASSERT_CHECK_DURATION 300 |
| |
| #ifdef __MTK_TARGET__ |
| |
| const kal_uint16 ELM_ACCURACY_TBL[] = {8,12,25,62,100,125,625,1000}; |
| |
| #ifdef ELM_AMIF_ENABLE |
| kal_uint32 elm_read_lat_threshold = 2000; |
| kal_uint32 elm_write_lat_threshold = 2000; |
| #else |
| kal_uint32 elm_read_lat_threshold = 450; |
| kal_uint32 elm_write_lat_threshold = 300; |
| #endif |
| ELM_WC_UNIT elm_read_wc_unit = E_ELM_WC_KB; |
| ELM_WC_UNIT elm_write_wc_unit = E_ELM_WC_KB; |
| kal_uint32 elm_read_wc_threshold = 300; |
| kal_uint32 elm_write_wc_threshold = 300; |
| kal_uint32 elm_wc_dur_in_us = 200; |
| |
| kal_uint32 elm_infra_read_lat_threshold = 2000; |
| kal_uint32 elm_infra_write_lat_threshold = 2000; |
| ELM_WC_UNIT elm_infra_read_wc_unit = E_ELM_WC_MB; |
| ELM_WC_UNIT elm_infra_write_wc_unit = E_ELM_WC_MB; |
| kal_uint32 elm_infra_read_wc_threshold = 15; |
| kal_uint32 elm_infra_write_wc_threshold = 15; |
| kal_uint32 elm_infra_wc_dur_in_us = 10*1000; // 10ms |
| |
| kal_uint32 elm_dynamic_lat_threshold_disable = 0; //0 enable, 1 disable |
| kal_uint32 elm_lat_accuracy = ELM_unit_25us ; |
| kal_uint32 elm_lat_duration = 200; |
| kal_uint32 elm_trans_threshold = 100; |
| kal_uint32 elm_mode = ELM_MODE_0; |
| kal_uint32 elm_id2_rw = ELM_RD; |
| kal_uint32 elm_id3_rw = ELM_WR; |
| kal_uint32 elm_id0_master = ELM_ALL_MASTER; |
| kal_uint32 elm_id0_rw = ELM_READ; |
| kal_uint32 elm_id0_prio = ELM_ALL_PRIO; |
| |
| kal_uint32 elm_id1_master = ELM_ALL_MASTER; |
| kal_uint32 elm_id1_rw = ELM_WRITE; |
| kal_uint32 elm_id1_prio = ELM_ALL_PRIO; |
| |
| kal_uint32 elm_ao_decode_cfg = ELM_DECODE_FROM_AO; |
| kal_uint32 elm_id0_value = 5; |
| kal_uint32 elm_id0_mask = ELM_AO_CONTROL_DEFAULT; |
| kal_uint32 elm_id1_value = 5; |
| kal_uint32 elm_id1_mask = ELM_AO_CONTROL_DEFAULT; |
| |
| // ID2/3 cnt default value target all transaction |
| kal_uint32 elm_id2_value = 0; |
| kal_uint32 elm_id2_mask = ELM_AO_CONTROL_DEFAULT; |
| kal_uint32 elm_id3_value = 0; |
| kal_uint32 elm_id3_mask = ELM_AO_CONTROL_DEFAULT; |
| |
| |
| #if defined(__PRODUCTION_RELEASE__) |
| elm_exception_type EMI_ELM_lat_irq_exception_type = ELM_NONE; //EMI latency irq default use trace |
| elm_exception_type EMI_ELM_wc_irq_exception_type = ELM_NONE; //EMI wc irq default use trace |
| elm_exception_type INFRA_ELM_lat_irq_exception_type = ELM_NONE; //INFRA latency irq default use trace |
| elm_exception_type INFRA_ELM_wc_irq_exception_type = ELM_NONE; //INFRA wc irq default use trace |
| #else |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| #endif |
| |
| |
| /*--- ELM history variable ---*/ |
| #define ELM_RUNTIME_HISTORY_SIZE 8 |
| |
| //EMI ELM |
| kal_uint32 emi_elm_runtime_lat_history_idx = 0; |
| ELM_RUNTIME_PROFILE_LAT_T emi_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE]; |
| kal_uint32 emi_elm_runtime_wc_history_idx = 0; |
| ELM_RUNTIME_PROFILE_WC_T emi_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE]; |
| //INFRA_A ELM |
| kal_uint32 infra_elm_runtime_lat_history_idx = 0; |
| ELM_RUNTIME_PROFILE_LAT_T infra_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE]; |
| kal_uint32 infra_elm_runtime_wc_history_idx = 0; |
| ELM_RUNTIME_PROFILE_WC_T infra_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE]; |
| |
| |
| |
| void elmtop_emi_isr_handler(); |
| void elm_infra_isr_handler(); |
| |
| |
| |
| #define ELM_HISTORY_SIZE 64 |
| kal_uint32 elm_profile_history_idx_0 = 0; |
| ELM_FULL_LOG_T elm_profile_history_0[ELM_HISTORY_SIZE]; |
| |
| |
| void ELM_INIT(void) |
| { |
| /*MDMCU EMI ELM*/ |
| //disable elm |
| DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); |
| //clear ELM interrupt |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); // clear ELM interrupt |
| //set to mode 0 |
| DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK)); // clear ELM mode |
| DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK & elm_mode)); // select ELM mode |
| //ID select for ID2/3 (ID0/1 by ao_reg later) |
| DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); |
| //set total latency weight for 2nd level detection (set to max-> DISABLE) |
| DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_TOTAL_LAT_WEIGHT_BLOCK(7)); |
| //ID0/1 trans count threshold |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_TH, elm_trans_threshold); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_TH, elm_trans_threshold); |
| // config ID2/3 setting (config ID0/1 by ao_reg later) |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask); |
| //set word count threshold to 1.5GB/sec (both read and write) |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_read_wc_threshold, elm_read_wc_unit)); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_write_wc_threshold, elm_write_wc_unit)); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_wc_dur_in_us-1)|ELM_WC_DURATION(1-1)); |
| //set ao_reg cfg1 (ID1 config) |
| DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, |
| ELM_EMI_TOP_BLOCK(E_TOP_MASK)| |
| DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| |
| ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])| |
| EMI_BLOCK(E_NOT_MASK)| |
| ELM_INT_MASK(LAT_INT_UNMASK_ALL)); |
| //set ao_reg cfg2 (threshold when emi blocking, wc int) |
| DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG2, |
| LAT_TH_ID1_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_write_lat_threshold)))| |
| LAT_TH_ID0_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_read_lat_threshold)))| |
| ELM_WC_INT_MASK(WC_INT_UNMASK_ALL)); |
| //subwindow enable; grand total mode |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_SUBWINDOW_CTRL, 1); |
| //set ao_reg cfg0 (ELM enable, ID0 config, threshold when emi normal) |
| DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, |
| ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)| |
| LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))| |
| LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| |
| DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); |
| |
| IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE); |
| /* MDINFRA_A EMI ELM*/ |
| //disable elm |
| DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE); |
| //clear ELM interrupt |
| DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL); |
| //set ID mode |
| //DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL |
| DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL |
| //set trans threshold |
| DRV_WriteReg32(REG_MDINFRA_ELM_ID0_TRANS_TH, elm_trans_threshold); |
| DRV_WriteReg32(REG_MDINFRA_ELM_ID1_TRANS_TH, elm_trans_threshold); |
| // config word_cnt window setting |
| DRV_WriteReg32(REG_MDINFRA_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_infra_read_wc_threshold, elm_infra_read_wc_unit)); |
| DRV_WriteReg32(REG_MDINFRA_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_infra_write_wc_threshold, elm_infra_write_wc_unit)); |
| DRV_WriteReg32(REG_MDINFRA_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_infra_wc_dur_in_us-1)|ELM_WC_DURATION(1-1)); |
| // set ao_reg cfg1 (ID1 csetting, duration, irq unmask) |
| DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG1, |
| ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_prio)| |
| ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])| |
| EMI_BLOCK(E_NOT_MASK)| |
| ELM_INT_MASK(LAT_INT_UNMASK_ALL)); |
| // set ao_reg cfg2 (threshold when emi blocking) |
| DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG2, |
| LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_write_lat_threshold)))| |
| LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_read_lat_threshold)))| |
| ELM_WC_INT_MASK(WC_INT_UNMASK_ALL)); |
| // set ao_reg cfg0 (elm enable, accuracy, threshold when emi normal, ID0 setting) |
| DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, |
| ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)| |
| LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))| |
| LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))| |
| DECODE_ID0(elm_id0_rw|elm_id0_prio)); |
| |
| |
| IRQUnmask(IRQ_ELM_DMA_IRQ_CODE); |
| |
| return ; |
| } |
| |
| void ELM_Config_DormantLeave(void) |
| { |
| kal_uint32 vpe_idx; |
| vpe_idx = kal_get_current_vpe_id(); |
| if(0 == vpe_idx) |
| { |
| ELM_INIT(); |
| emi_elm_runtime_lat_history_idx =0; |
| memset((void*)emi_elm_runtime_lat_history,0, sizeof(ELM_RUNTIME_PROFILE_LAT_T)*ELM_RUNTIME_HISTORY_SIZE); |
| } |
| } |
| |
| void ELM_Config_DormantEnter(void) |
| { |
| |
| } |
| |
| void ELM_GET_FULL_LOG(ELM_FULL_LOG_T* data) |
| { |
| if(NULL==data) |
| { |
| return; |
| } |
| |
| #ifdef __ELM_RUNTIME_PROFILE__ |
| elm_profile_history_0[elm_profile_history_idx_0].fma_stamp = ust_get_current_time(); |
| ELM_GET_LOG(0,elm_profile_history_0[elm_profile_history_idx_0]); |
| elm_profile_history_0[elm_profile_history_idx_0].r_lat_thr = elm_read_lat_threshold; |
| elm_profile_history_0[elm_profile_history_idx_0].w_lat_thr = elm_write_lat_threshold; |
| memcpy(data,&elm_profile_history_0[elm_profile_history_idx_0], sizeof(ELM_FULL_LOG_T)); |
| elm_profile_history_idx_0 = (elm_profile_history_idx_0 + 1) % ELM_HISTORY_SIZE ; |
| #else |
| data->fma_stamp = ust_get_current_time(); |
| ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, 0, &(data->w_trans)); |
| ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, 0, &(data->w_latency)); |
| ELM_GET_WC_CNT(ELM_WR, 0, &(data->w_wordcount)); |
| ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, 0, &(data->r_trans)); |
| ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, 0, &(data->r_latency)); |
| ELM_GET_WC_CNT(ELM_RD, 0, &(data->r_wordcount)); |
| #endif |
| |
| } |
| |
| kal_uint32 debug_emi_elm_runtime_counter = 0; |
| kal_uint32 debug_MDMCU_elm_last_INT_FRC = 0; |
| kal_uint32 debug_MDIFRA_elm_last_INT_FRC = 0; |
| |
| |
| |
| #define E_MAX16(x) ((x>0xFFFF)? 0xFFFF : x) |
| |
| kal_uint32 elm_md_dvfs_con = 0; |
| kal_uint32 elm_ap_vcore_dvfs_current = 0; |
| kal_uint32 elm_ap_vcore_dvfs_target = 0; |
| kal_uint32 elm_ap_vcore_dvfs_last = 0; |
| |
| void elmtop_emi_isr_handler() |
| { |
| kal_uint32 curr_frc = 0, enter_lisr_frc = 0; |
| kal_uint32 int_status = 0; |
| kal_uint32 read_trans_count = 0, write_trans_count = 0; |
| kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0; |
| kal_uint32 read_worst_alat_maxost = 0, write_worst_alat_maxost = 0; |
| kal_uint32 read_worst_wc = 0, write_worst_wc = 0; |
| kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0; |
| kal_uint32 ia_13m_tick = 0, dvfs_13m_tick = 0, ddren_13m_tick = 0; |
| enter_lisr_frc = ust_get_current_time(); |
| debug_emi_elm_runtime_counter++; |
| |
| //Mask cirq ELM interrupt |
| IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE); |
| //stop ELM |
| DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| |
| curr_frc = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_FRCVAL); |
| int_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS); |
| |
| /* Handling latency interrupt */ |
| if(int_status & INT_MASK_LAT) |
| { |
| read_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL); |
| write_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL); |
| read_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL) ); |
| write_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL) ); |
| read_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL) ); |
| write_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL) ); |
| read_worst_alat_maxost = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL); |
| write_worst_alat_maxost = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL); |
| |
| // Read AP side related debugging register |
| #if 1 |
| ia_13m_tick = *AP_SYSTIMER_TICK; //AP systimer |
| dvfs_13m_tick = *AP_DVFS_OCCUR_TICK;// last dvfs occur tick |
| ddren_13m_tick = *AP_DDREN_OCCUR_TICK;// last ddren occur tick |
| elm_ap_vcore_dvfs_current = *AP_VCORE_DVFS_CURRENT; |
| elm_ap_vcore_dvfs_target = *AP_VCORE_DVFS_TARGET; |
| elm_ap_vcore_dvfs_last = *AP_VCORE_DVFS_LAST; |
| #endif |
| |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].enter_lisr_frc= enter_lisr_frc; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat_maxost = read_worst_alat_maxost; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat_maxost = write_worst_alat_maxost; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_dvfs_tick = dvfs_13m_tick; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_ddren_tick = ddren_13m_tick; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].md_tick = ia_13m_tick; |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id0_subwindow_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_SUBWINDOW_STS); |
| emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id1_subwindow_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_SUBWINDOW_STS); |
| emi_elm_runtime_lat_history_idx++; |
| |
| elm_md_dvfs_con = drv_mdap_interface_hw_get_curr_scenario_reg(); |
| |
| switch(EMI_ELM_lat_irq_exception_type) |
| { |
| case ELM_NONE: |
| { |
| //read latency over criteria |
| if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT)) |
| { |
| ELM_IF_DEF_TRACE( \ |
| MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \ |
| elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \ |
| ); |
| } |
| //write latency over criteria |
| else |
| { |
| ELM_IF_DEF_TRACE( \ |
| MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \ |
| elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \ |
| ); |
| } |
| break; |
| } |
| case ELM_ASSERT: |
| { |
| if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT)) |
| { |
| EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \ |
| (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \ |
| (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status))); |
| } |
| else |
| { |
| EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \ |
| (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \ |
| (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status))); |
| } |
| break; |
| } |
| case ELM_ASSERT_AT_2nd: |
| { |
| // just show trace on first time over criteria in 300us |
| if(debug_MDMCU_elm_last_INT_FRC == 0) |
| { |
| debug_MDMCU_elm_last_INT_FRC = curr_frc; |
| if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT)) |
| { |
| ELM_IF_DEF_TRACE( \ |
| MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \ |
| elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \ |
| ); |
| } |
| else |
| { |
| ELM_IF_DEF_TRACE( \ |
| MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \ |
| elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \ |
| ); |
| } |
| } |
| else |
| { |
| if(ust_us_duration(debug_MDMCU_elm_last_INT_FRC, curr_frc) < ELM_2ND_ASSERT_CHECK_DURATION) |
| { |
| if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT)) |
| { |
| EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \ |
| (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \ |
| (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status))); |
| } |
| else |
| { |
| EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \ |
| (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \ |
| (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status))); |
| } |
| } |
| else |
| { |
| debug_MDMCU_elm_last_INT_FRC = curr_frc; |
| if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT)) |
| { |
| ELM_IF_DEF_TRACE( \ |
| MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \ |
| elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \ |
| ); |
| } |
| else |
| { |
| ELM_IF_DEF_TRACE( \ |
| MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \ |
| elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \ |
| ); |
| } |
| } |
| } |
| break; |
| } |
| default: |
| break; |
| } |
| |
| } |
| /* Handling word count interrupt */ |
| else |
| { |
| read_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT); |
| write_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT); |
| |
| emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc; |
| emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status; |
| emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc; |
| emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc; |
| emi_elm_runtime_wc_history_idx++; |
| |
| //check config mode: assertion or trace |
| switch(EMI_ELM_wc_irq_exception_type) |
| { |
| case ELM_NONE: |
| { |
| // Read wordcount violation |
| if(int_status & ID2_TOT_WC_INT) |
| { |
| ELM_IF_DEF_TRACE( \ |
| MD_TRC_EMI_ELM_R_BW_WARN(curr_frc, ELM_WC2XB(read_worst_wc, elm_read_wc_unit), ELM_WC2XB(elm_read_wc_threshold, elm_read_wc_unit), ELM_WC_UNIT_STRING(elm_read_wc_unit)), \ |
| ); |
| } |
| else |
| { |
| ELM_IF_DEF_TRACE( \ |
| MD_TRC_EMI_ELM_W_BW_WARN(curr_frc, ELM_WC2XB(write_worst_wc, elm_write_wc_unit), ELM_WC2XB(elm_write_wc_threshold, elm_write_wc_unit), ELM_WC_UNIT_STRING(elm_write_wc_unit)), \ |
| ); |
| } |
| break; |
| } |
| case ELM_ASSERT: |
| { |
| // Read wordcount violation |
| if(int_status & ID2_TOT_WC_INT) |
| { |
| EXT_ASSERT(0, ELM_WC2XB(read_worst_wc, elm_read_wc_unit), elm_read_wc_unit, 0); |
| } |
| else |
| { |
| EXT_ASSERT(0, ELM_WC2XB(write_worst_wc, elm_write_wc_unit), elm_write_wc_unit, 0); |
| |
| } |
| break; |
| } |
| default: |
| break; |
| } |
| } |
| |
| //Clear ELM interrupt after read irq type |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); |
| |
| //enable ELM |
| DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| |
| IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE); |
| return ; |
| |
| } |
| |
| void elm_infra_isr_handler() |
| { |
| kal_uint32 curr_frc = 0; |
| kal_uint32 int_status = 0; |
| |
| kal_uint32 read_trans_count = 0, write_trans_count = 0; |
| kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0; |
| kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0; |
| kal_uint32 read_worst_wc = 0, write_worst_wc = 0; |
| |
| //Mask cirq ELM interrupt |
| IRQMask(IRQ_ELM_DMA_IRQ_CODE); |
| |
| //stop elm |
| DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| |
| //curr_frc = ust_get_current_time(); |
| |
| //read INT status |
| int_status = DRV_Reg32(REG_MDINFRA_ELM_INT_STATUS); |
| |
| /* Handling latency interrupt */ |
| if(int_status & INT_MASK_LAT) |
| { |
| curr_frc = DRV_Reg32(REG_MDINFRA_ELM_INT_FRCVAL); |
| read_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL); |
| write_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL); |
| read_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL) ); |
| write_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL) ); |
| read_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL) ); |
| write_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL) ); |
| |
| infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc; |
| infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status; |
| infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns; |
| infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns; |
| infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count; |
| infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count; |
| infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns; |
| infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns; |
| infra_elm_runtime_lat_history_idx++; |
| |
| switch(INFRA_ELM_lat_irq_exception_type) |
| { |
| case ELM_NONE: |
| { |
| #ifdef __ELM_TRACE__ |
| if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT)) |
| { |
| MD_TRC_INFRA_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_infra_read_lat_threshold, read_total_latency_ns, read_trans_count); |
| } |
| else |
| { |
| MD_TRC_INFRA_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_infra_write_lat_threshold, write_total_latency_ns, write_trans_count); |
| } |
| #endif |
| break; |
| } |
| default: |
| break; |
| } |
| } |
| /* Handling word count interrupt */ |
| else if(int_status & INT_MASK_WC) |
| { |
| curr_frc = DRV_Reg32(REG_MDINFRA_ELM_INT_FRCVAL); |
| read_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID2_WORST_WORD_CNT); |
| write_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID3_WORST_WORD_CNT); |
| |
| infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc; |
| infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status; |
| infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc; |
| infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc; |
| infra_elm_runtime_wc_history_idx++; |
| |
| switch(INFRA_ELM_wc_irq_exception_type) |
| { |
| case ELM_NONE: |
| { |
| // Read wordcount violation |
| if(int_status & ID2_TOT_WC_INT) |
| { |
| ELM_IF_DEF_TRACE( \ |
| MD_TRC_INFRA_ELM_R_BW_WARN(curr_frc, ELM_WC2XB(read_worst_wc, elm_infra_read_wc_unit), ELM_WC2XB(elm_infra_read_wc_threshold, elm_infra_read_wc_unit), ELM_WC_UNIT_STRING(elm_infra_read_wc_unit)), \ |
| ); |
| } |
| else |
| { |
| ELM_IF_DEF_TRACE( \ |
| MD_TRC_INFRA_ELM_W_BW_WARN(curr_frc, ELM_WC2XB(write_worst_wc, elm_infra_write_wc_unit), ELM_WC2XB(elm_infra_write_wc_threshold, elm_infra_write_wc_unit), ELM_WC_UNIT_STRING(elm_infra_write_wc_unit)), \ |
| ); |
| } |
| break; |
| } |
| case ELM_ASSERT: |
| { |
| // Read wordcount violation |
| if(int_status & ID2_TOT_WC_INT) |
| { |
| EXT_ASSERT(0, ELM_WC2XB(read_worst_wc, elm_infra_read_wc_unit), elm_infra_read_wc_unit, 0); |
| } |
| else |
| { |
| EXT_ASSERT(0, ELM_WC2XB(write_worst_wc, elm_infra_write_wc_unit), elm_infra_write_wc_unit, 0); |
| } |
| break; |
| } |
| default: |
| break; |
| } |
| } |
| |
| |
| //Clear ELM interrupt after read irq type |
| DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL); //clear M4_A ELM interrupt |
| |
| //Enable ELM |
| DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| |
| IRQUnmask(IRQ_ELM_DMA_IRQ_CODE); |
| |
| } |
| |
| void ELM_MCU_threshold_change_lightweight(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us) |
| { |
| kal_uint32 mask_state=0; |
| |
| if(elm_dynamic_lat_threshold_disable) |
| { |
| return; |
| } |
| |
| mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE); |
| |
| //Mask cirq ELM interrupt |
| IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE); |
| |
| DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); //disable ELM |
| |
| // kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT); |
| |
| |
| elm_read_lat_threshold = read_avg_lat_ns; |
| elm_write_lat_threshold = write_avg_lat_ns; |
| elm_lat_duration= dur_us; |
| |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt |
| DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, |
| ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| |
| ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])| |
| EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL)); |
| DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, |
| ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)| |
| LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))| |
| LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| |
| DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); |
| |
| // kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK); |
| |
| if(!mask_state) |
| { |
| IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE); |
| } |
| } |
| |
| void ELM_MCU_threshold_change(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us) |
| { |
| kal_uint32 mask_state=0; |
| |
| if(elm_dynamic_lat_threshold_disable) |
| { |
| return; |
| } |
| |
| if((read_avg_lat_ns<200) || (write_avg_lat_ns<200) || (dur_us<200)) |
| { |
| kal_uint32 lr = 0; |
| kal_uint32 sub_error_code = 0; |
| GET_RETURN_ADDRESS(lr); |
| if(read_avg_lat_ns<200) |
| { |
| sub_error_code = 1; |
| } |
| else if(write_avg_lat_ns<200) |
| { |
| sub_error_code = 2; |
| } |
| else |
| { |
| sub_error_code = 3; |
| } |
| EXT_ASSERT(0, lr, KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD, sub_error_code); |
| } |
| |
| |
| |
| mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE); |
| |
| //Mask cirq ELM interrupt |
| IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE); |
| |
| DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); //disable ELM |
| |
| kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT); |
| |
| |
| elm_read_lat_threshold = read_avg_lat_ns; |
| elm_write_lat_threshold = write_avg_lat_ns; |
| elm_lat_duration= dur_us; |
| |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt |
| DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, |
| ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| |
| ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])| |
| EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL)); |
| DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, |
| ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)| |
| LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))| |
| LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| |
| DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); |
| |
| kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK); |
| |
| #ifdef __ELM_TRACE__ |
| { |
| // L1 trace |
| kal_uint32 curr_frc = 0; |
| curr_frc = ust_get_current_time(); |
| MD_TRC_EMI_ELM_SET_R_TH(curr_frc, elm_read_lat_threshold); |
| MD_TRC_EMI_ELM_SET_W_TH(curr_frc, elm_write_lat_threshold); |
| } |
| #endif |
| |
| if(!mask_state) |
| { |
| IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE); |
| } |
| |
| } |
| |
| #if 0//def __ELM_RUNTIME_PROFILE__ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| /* under construction !*/ |
| #endif |
| |
| kal_uint8 _ELM_latency_status(void) |
| { |
| #ifdef __ELM_RUNTIME_PROFILE__ |
| |
| //if emi_elm_runtime_lat_history_idx == 0, means that it didn't enter ELM isr handler once, it will all be zero |
| if(emi_elm_runtime_lat_history_idx != 0) |
| { |
| kal_uint32 int_status = 0; |
| int_status = emi_elm_runtime_lat_history[(emi_elm_runtime_lat_history_idx-1)%ELM_RUNTIME_HISTORY_SIZE].int_status; |
| |
| if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT)) |
| { |
| return 0xAE; //EMI read latency may be too long |
| } |
| else |
| { |
| return 0xBE; //EMI write latency may be too long |
| } |
| } |
| return 0xDE; // EMI read/write latency are OK. |
| #else |
| return 0xFF; //no ELM info |
| #endif |
| } |
| |
| /****************************************************************************** |
| * function : void set_emi_elm_exceptiontype(kal_bool lat_flag, kal_uint8 exception_type) |
| * description : this function is called when set emi elm read/write latency/wordcount exception type |
| * parameter : kal_uint8 exception_type: 0,1,2 |
| * return : void |
| ******************************************************************************/ |
| kal_bool Set_EMI_ELM_ExceptionType(kal_uint8 exception_type) |
| { |
| switch (exception_type) |
| { |
| case ELM_NONE: |
| { |
| EMI_ELM_lat_irq_exception_type = ELM_NONE; |
| break; |
| } |
| |
| case ELM_ASSERT: |
| { |
| EMI_ELM_lat_irq_exception_type = ELM_ASSERT; |
| break; |
| } |
| case ELM_ASSERT_AT_2nd: |
| { |
| EMI_ELM_lat_irq_exception_type = ELM_ASSERT_AT_2nd; |
| break; |
| } |
| default: |
| return KAL_FALSE; |
| break; |
| } |
| return KAL_TRUE; |
| } |
| |
| kal_bool Set_EMI_ELM_Threshold(kal_uint8 info, kal_uint32 threshold) |
| { |
| ELM_IF_DEF_TRACE(kal_uint32 curr_frc = 0,); |
| ELM_IF_DEF_TRACE(curr_frc = ust_get_current_time(),); |
| elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold |
| if((info&0xF0)) |
| { // infra |
| //Disable before re-configure |
| DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE); |
| |
| if( info & 0x01 ) |
| { |
| elm_infra_read_lat_threshold = threshold; |
| ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_R_TH(curr_frc, threshold),); |
| } |
| else |
| { |
| elm_infra_write_lat_threshold = threshold; |
| ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_W_TH(curr_frc, threshold),); |
| } |
| //M4_A ELM |
| DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, |
| ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)| |
| LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))| |
| LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))| |
| DECODE_ID0(elm_id0_rw|elm_id0_prio)); |
| } |
| else |
| { //mdmcu |
| |
| //Disable before re-configure |
| DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); |
| if( info & 0x01 ) |
| { |
| elm_read_lat_threshold = threshold; |
| ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_R_TH(curr_frc, threshold),); |
| } |
| else |
| { |
| elm_write_lat_threshold = threshold; |
| ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_W_TH(curr_frc, threshold),); |
| } |
| DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)| \ |
| LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \ |
| DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); |
| } |
| |
| |
| return KAL_TRUE; |
| } |
| |
| /****************************************************************************** |
| * function : kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw) |
| * description : ELM has 4 counters(ID 0,1,2,3), this function is used to set EMI ELM's |
| * counter to monitro read or write transaction and master. |
| * parameter : |
| * kal_uint8 id: 0, 1, 0xFF; |
| * -> Assume id 0,2 use same configuration(so does id 1,3), including read/write and masters. |
| * -> 0xFF is used for let all ID monitor same masters. |
| * return : void |
| ******************************************************************************/ |
| |
| //!!!! AXID RELATED API !!!! |
| kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw) |
| { |
| kal_bool rtn = KAL_TRUE; |
| |
| //Disable before re-configure |
| DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); |
| elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold |
| |
| if(id == 0) // id 0 (default read), assume id2 use same master as id 0 |
| { |
| elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK)); |
| if(m_sel==0) |
| { |
| elm_id0_master = ELM_ALL_MASTER; |
| |
| elm_id2_value = 0; |
| elm_id2_mask |= MASTER_DEFAULT_MASK; |
| } |
| else if(m_sel==1) |
| { |
| elm_id0_master = ELM_MDMCU_ONLY; |
| |
| elm_id2_value = MASTER_MDMCU; |
| elm_id2_mask |= MASTER_MDMCU_MASK; |
| } |
| else if(m_sel==2) |
| { |
| elm_id0_master = ELM_USIP_ONLY; |
| |
| elm_id2_value = MASTER_USIP; |
| elm_id2_mask |= MASTER_USIP_MASK; |
| } |
| else |
| { |
| rtn = KAL_FALSE; |
| } |
| |
| if(rw == 0) |
| { |
| elm_id0_rw = ELM_READ; |
| elm_id2_rw = ELM_RD; |
| } |
| else if(rw == 1) |
| { |
| elm_id0_rw = ELM_WRITE; |
| elm_id2_rw = ELM_WR; |
| } |
| else |
| { |
| rtn = KAL_FALSE; |
| } |
| } |
| else if( id == 1 ) // id 1 (default write), assume id3 use same master as id 1 |
| { |
| elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK)); |
| if(m_sel==0) |
| { |
| elm_id1_master = ELM_ALL_MASTER; |
| |
| elm_id3_value = 0; |
| elm_id3_mask |= MASTER_DEFAULT_MASK; |
| } |
| else if(m_sel==1) |
| { |
| elm_id1_master = ELM_MDMCU_ONLY; |
| |
| elm_id3_value = MASTER_MDMCU; |
| elm_id3_mask |= MASTER_MDMCU_MASK; |
| } |
| else if(m_sel==2) |
| { |
| elm_id1_master = ELM_USIP_ONLY; |
| |
| elm_id3_value = MASTER_USIP; |
| elm_id3_mask |= MASTER_USIP_MASK; |
| } |
| else |
| { |
| rtn = KAL_FALSE; |
| } |
| |
| if(rw == 0) |
| { |
| elm_id1_rw = ELM_READ; |
| elm_id3_rw = ELM_RD; |
| } |
| else if(rw == 1) |
| { |
| elm_id1_rw = ELM_WRITE; |
| elm_id3_rw = ELM_WR; |
| } |
| else |
| { |
| rtn = KAL_FALSE; |
| } |
| } |
| else if(id == 0xFF) // ID 0/1/2/3 are the same master, 0,2 for read, 1,3 for write |
| { |
| elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK)); |
| elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK)); |
| |
| elm_id0_rw = ELM_READ; |
| elm_id1_rw = ELM_WRITE; |
| elm_id2_rw = ELM_RD; |
| elm_id3_rw = ELM_WR; |
| if(m_sel==0) |
| { |
| elm_id0_master = ELM_ALL_MASTER; |
| elm_id1_master = ELM_ALL_MASTER; |
| |
| elm_id2_value = 0; |
| elm_id2_mask |= MASTER_DEFAULT_MASK; |
| elm_id3_value = 0; |
| elm_id3_mask |= MASTER_DEFAULT_MASK; |
| } |
| else if(m_sel==1) |
| { |
| elm_id0_master = ELM_MDMCU_ONLY; |
| elm_id1_master = ELM_MDMCU_ONLY; |
| |
| elm_id2_value = MASTER_MDMCU; |
| elm_id2_mask |= MASTER_MDMCU_MASK; |
| elm_id3_value = MASTER_MDMCU; |
| elm_id3_mask |= MASTER_MDMCU_MASK; |
| } |
| else if(m_sel==2) |
| { |
| elm_id0_master = ELM_USIP_ONLY; |
| elm_id1_master = ELM_USIP_ONLY; |
| |
| elm_id2_value = MASTER_USIP; |
| elm_id2_mask |= MASTER_USIP_MASK; |
| elm_id3_value = MASTER_USIP; |
| elm_id3_mask |= MASTER_USIP_MASK; |
| } |
| else |
| { |
| rtn = KAL_FALSE; |
| } |
| } |
| else |
| { |
| rtn = KAL_FALSE; |
| } |
| |
| DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL |
| DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask); |
| |
| DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1, |
| ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)| |
| ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])| |
| EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL)); |
| |
| DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, |
| ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)| |
| LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))| |
| LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| |
| DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio)); |
| return rtn; |
| } |
| |
| |
| kal_bool Set_EMI_ELM_Mode(kal_uint8 mode) |
| { |
| kal_bool rtn = KAL_TRUE; |
| //Disable elm |
| DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| |
| elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold |
| |
| if( mode == 0) |
| { |
| elm_mode = ELM_MODE_0; |
| } |
| else if( mode == 2) |
| { |
| elm_mode = ELM_MODE_2; |
| elm_ao_decode_cfg = ELM_DECODE_FROM_APB; |
| //mdmcu elm |
| DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode |
| DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode |
| //mdinfra_a elm |
| DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode |
| DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode |
| |
| } |
| else |
| { |
| rtn = KAL_FALSE; |
| } |
| //Set mode & enable elm |
| //mdmcu elm |
| DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode |
| DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode |
| DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| //mdinfra_a elm |
| DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode |
| DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode |
| DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| |
| return rtn; |
| } |
| |
| //!!!! AXID RELATED API !!!! |
| kal_bool Set_EMI_ELM_uSIP_Core(kal_uint8 id, kal_uint8 thread_val, kal_uint8 port_sel) |
| { |
| kal_bool rtn = KAL_TRUE; |
| kal_uint32 assembled_axid=0, assembled_axid_mask=0; // [13] |
| kal_uint16 usip_core=0, usip_thread=0 ; |
| |
| //Disable ELM |
| DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| //disable dynamic latency threshold |
| elm_dynamic_lat_threshold_disable = 1; |
| //elm id setting from apb |
| DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); |
| |
| usip_core = thread_val/2 ; |
| usip_thread = thread_val%2 ; |
| |
| if(usip_core==1){ |
| assembled_axid |= (1<<1) ; |
| } |
| assembled_axid |= (usip_thread<<4); |
| |
| switch(port_sel) |
| { |
| case 0: |
| assembled_axid_mask |= (1<<6) ; |
| break; |
| case 1: |
| assembled_axid |= (1<<3); |
| assembled_axid_mask |= (1<<6) ; |
| break; |
| case 2: |
| assembled_axid |= (1<<0); |
| assembled_axid_mask |= (0x7<<6); |
| break; |
| case 3: |
| assembled_axid |= (1<<0); |
| assembled_axid_mask |= (0x3<<6); |
| break; |
| default: //monitor all ports |
| assembled_axid_mask |= 0x1CD ; |
| break; |
| } |
| |
| assembled_axid = (assembled_axid<<2) | 0x2 ; |
| assembled_axid_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_DEFAULT_MASK)) | (assembled_axid_mask<<2) ; |
| //config AXID value/mask |
| if(id==0) |
| { |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, assembled_axid); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, assembled_axid_mask); |
| } |
| else if(id==1) |
| { |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, assembled_axid); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, assembled_axid_mask); |
| } |
| else if(id==2) |
| { |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, assembled_axid); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, assembled_axid_mask); |
| } |
| else |
| { |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, assembled_axid); |
| DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, assembled_axid_mask); |
| } |
| |
| //Enable ELM |
| DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| return rtn; |
| } |
| |
| //!!!! SIDEBAND RELATED API !!!! |
| kal_bool Set_EMI_ELM_VPE(kal_uint8 id, kal_uint8 vpe_sel) |
| { |
| kal_bool rtn = KAL_TRUE; |
| kal_uint32 sideband_val = 0 ; |
| //Disable ELM |
| DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| //disable dynamic latency threshold |
| elm_dynamic_lat_threshold_disable = 1; |
| //elm id setting from apb |
| DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); |
| |
| //calculate vpe sideband value |
| if(vpe_sel >= SYS_MCU_NUM_VPE) |
| { |
| return KAL_FALSE ; |
| } |
| else |
| { |
| kal_uint8 core_id= vpe_sel/(SYS_MCU_NUM_VPE/SYS_MCU_NUM_CORE); |
| kal_uint8 vpe_id = vpe_sel%(SYS_MCU_NUM_VPE/SYS_MCU_NUM_CORE); |
| sideband_val = (core_id<<6) | ((vpe_id+1)<<4) ; |
| } |
| |
| //config ID sideband value/mask |
| if(id==0) |
| { |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, sideband_val); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, 0); |
| } |
| else if(id==1) |
| { |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, sideband_val); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, 0); |
| } |
| else if(id==2) |
| { |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, sideband_val); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, 0); |
| } |
| else if(id==3) |
| { |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, sideband_val); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, 0); |
| } |
| else |
| { //reset to default |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, 0); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, 0); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, 0); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, 0); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL); |
| } |
| |
| //Enable ELM |
| DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| return rtn; |
| } |
| |
| kal_bool Set_EMI_ELM_ID_SIDEBAND(kal_uint16 sideband_val, kal_uint16 sideband_mask) |
| { |
| kal_bool rtn = KAL_TRUE; |
| //Disable before re-configure |
| DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| //disable dynamic latency threshold |
| elm_dynamic_lat_threshold_disable = 1; |
| //elm id setting from apb |
| DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); |
| |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, sideband_val);//REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, sideband_mask); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, sideband_val); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, sideband_mask); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, sideband_val); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, sideband_mask); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, sideband_val); |
| DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, sideband_mask); |
| |
| DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); |
| return rtn; |
| } |
| |
| #endif |