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#ifndef _BTDMA_PUBLIC_H_
#define _BTDMA_PUBLIC_H_
typedef kal_uint32 btdma_uint32;
typedef kal_int32 btdma_int32 ;
typedef kal_uint8 btdma_uint8 ;
typedef enum BTDMA_PRIORITY_CHAIN
{
PRIORITY_0 = 0,
PRIORITY_1 ,
PRIORITY_2 ,
PRIORITY_3 ,
PRIORITY_4 ,
PRIORITY_5 ,
PRIORITY_6 ,
PRIORITY_7
} btdma_priority_chain;
typedef enum BTDMA_IP
{
TTBIT = 0 ,
SFBIT ,
OTEBIT
} btdma_ip;
typedef enum BTDMA_CORE
{
UNGATE_VCORE = 0 ,
UNGATE_MCORE0 = 2 ,
UNGATE_MCORE1 = 3
} btdma_core;
typedef enum BTDMA_CALLBACK
{
#undef BTDMA_CALLBACK_REGISTER
#define BTDMA_CALLBACK_REGISTER(KEY,CALLBACK) KEY,
#include "btdma_callback_reg.h"
#undef BTDMA_CALLBACK_REGISTER
BTDMA_CALLBACK_NUM
} btdma_callback_index;
typedef struct BTDMA_DESCRIPTION
{
btdma_uint32 source_address ;
btdma_uint32 target_address ;
btdma_uint32 crc32 ;
btdma_uint32 length :19 ;
btdma_uint32 reserved_1 :5 ;
btdma_uint32 crc_enable :1 ;
btdma_ip src_ip :2 ;
btdma_ip dest_ip :2 ;
btdma_uint32 reserved_2 :3 ;
btdma_uint32 signal_enable :14 ;
btdma_uint32 reserved_5 :10 ;
btdma_uint32 axi_qos_r_ultra :2 ;
btdma_uint32 axi_qos_r_flush :2 ;
btdma_uint32 axi_qos_w_ultra :2 ;
btdma_uint32 axi_qos_w_flush :2 ;
btdma_callback_index callback_key ;
btdma_uint32 caller ;
btdma_uint8 job_num :4 ;
btdma_uint32 reserved_6 :20 ;
btdma_uint8 own ;
} btdma_description;
#define BTDMA_NO_SIGNAL_ENABLE (0)
#define BTDMA_MCORE0_BOOTDONE_ENABLE (1 << 0)
#define BTDMA_MCORE1_BOOTDONE_ENABLE (1 << 1)
#define BTDMA_VCORE0_BOOTDONE_ENABLE (1 << 2)
#define BTDMA_MCORE0_INTERRUPT_ENABLE (1 << 3)
#define BTDMA_MCORE1_INTERRUPT_ENABLE (1 << 4)
#define BTDMA_L1CORE_INTERRUPT_ENABLE (1 << 5)
#define BTDMA_MCORE0_TH0_COMPLETE_ENABLE (1 << 6)
#define BTDMA_MCORE1_TH0_COMPLETE_ENABLE (1 << 7)
#define BTDMA_MCORE0_TH1_COMPLETE_ENABLE (1 << 8)
#define BTDMA_MCORE1_TH1_COMPLETE_ENABLE (1 << 9)
#define BTDMA_MCORE0_TH2_COMPLETE_ENABLE (1 << 10)
#define BTDMA_MCORE1_TH2_COMPLETE_ENABLE (1 << 11)
#define BTDMA_MCORE0_TH3_COMPLETE_ENABLE (1 << 12)
#define BTDMA_MCORE1_TH3_COMPLETE_ENABLE (1 << 13)
#define BTDMA_MCORE_TH_COMPLETE_ENABLE (1 << 6)
#define BTDMA_Trigger_User(source_addr,source_ip,target_addr,target_ip,length,BTDMA_L1CORE_INTERRUPT_ENABLE,priority,callback_key)
void SS_BTDMA_Trigger(btdma_description* desc,
btdma_priority_chain priority,
btdma_callback_index callback_key);
void BTDMA_MPU_EMI_Region_Set(btdma_uint32 start_address,btdma_uint32 end_address);
void BTDMA_SW_Enable_Ungate_Signal(btdma_core core);
void BTDMA_SW_Disable_Ungate_Signal(btdma_core core);
void BTDMA_Init();
void BTDMA_Polling_Priority_idle(btdma_uint32 priority);
/***************************************************
*
*
* Marco for assign descriptor
*
*
***************************************************/
#define DESCRIPTION_ASSIGN(SA,TA,SIZE,SE) \
.source_address = SA , \
.target_address = TA , \
.crc32 = 0 , \
.length = SIZE , \
.signal_enable = SE , \
.src_ip = OTEBIT , \
.dest_ip = OTEBIT , \
.own = 0xA5
#define DESCRIPTION_ASSIGN_CRC(SA,SIP,TA,TIP,SIZE,SE,CRC) \
.source_address = SA , \
.target_address = TA , \
.crc32 = CRC , \
.length = SIZE , \
.signal_enable = SE , \
.crc_enable = 1 , \
.src_ip = SIP , \
.dest_ip = TIP , \
.own = 0xA5
#define DESCRIPTION_ASSIGN_NO_CRC(SA,SIP,TA,TIP,SIZE,SE) \
.source_address = SA , \
.target_address = TA , \
.length = SIZE , \
.signal_enable = SE , \
.crc_enable = 0 , \
.src_ip = SIP , \
.dest_ip = TIP , \
.own = 0xA5
#define DESCRIPTION_END \
.source_address = 0, \
.target_address = 0, \
.crc32 = 0, \
.length = 0, \
.crc_enable = 0, \
.src_ip = TTBIT, \
.dest_ip = TTBIT, \
.own = 0
#endif