| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2005 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
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| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| |
| /***************************************************************************** |
| * |
| * Filename: |
| * --------- |
| * sleepdrv_interface.h |
| * |
| * Project: |
| * -------- |
| * Maui_Software |
| * |
| * Description: |
| * ------------ |
| * This file is for the public access for sleep mode operation. |
| * |
| * Author: |
| * ------- |
| * ------- |
| * |
| *============================================================================ |
| * HISTORY |
| * Below this line, this part is controlled by ClearCase. DO NOT MODIFY!! |
| *------------------------------------------------------------------------------ |
| * $Log$ |
| * |
| * 02 11 2022 yuhao.ye |
| * [MOLY00764790] [FBC][FM350-GL][NA][NA][USB]fm350 iot USB suspend and resume problem |
| * |
| * . |
| * |
| * 08 11 2021 pj.chen |
| * [MOLY00681687] [FM350-GL][FM350-GL][Nick Zhang][memory dump][NA][NA][NA]md_self_detect_by_hmu_long_time_no_response modem dump |
| * Add MCF lock sleep enum |
| * |
| * 11 10 2020 pj.chen |
| * [MOLY00528192] [Colgin][Sleep Mode]Driver development |
| * Add lock sleep enum for LVTS whole system reset |
| * |
| * 04 15 2020 guo-huei.chang |
| * [MOLY00509323] [Gen97] Power Model |
| * Power model (Sleep Driver Part) |
| * global variable from UnCache to Cache |
| * |
| * 04 06 2020 guo-huei.chang |
| * [MOLY00509323] [Gen97] Power Model |
| * |
| * Power model (Sleep Driver Part) |
| * |
| * 12 02 2019 jack.tung |
| * [MOLY00462428] [VMOLY][Gen97 Petrus] Structure Reordering in Sleep Driver |
| * |
| * . |
| * |
| * 10 24 2019 lian-li.tsai |
| * [MOLY00452393] For Low power monitor, raw data modify |
| * [EWSP0000054581_R1] |
| * [EWSP0000054581] |
| * |
| * 08 08 2019 guo-huei.chang |
| * [MOLY00421978] [VMOLY]Sleep and low power modify |
| * add md low power monitor (OSTD part) |
| * |
| * 08 06 2019 owen.ho |
| * [MOLY00312416] [Gen97][Need Patch]Sleep driver development |
| * Solve build error for Mercury |
| * |
| * 07 18 2019 owen.ho |
| * [MOLY00312416] [Gen97][Need Patch]Sleep driver development |
| * Add compile option for MD97P |
| * |
| * 04 15 2019 owen.ho |
| * [MOLY00312416] [Gen97][Need Patch]Sleep driver development |
| * Add sleep control enum |
| * |
| * 04 11 2019 owen.ho |
| * [MOLY00312416] [Gen97][Need Patch]Sleep driver development |
| * 1.Add sleep comtrol enum |
| * 2.DDr_en settings |
| * 3.Wakeup event settings |
| * 4.Add wallclk define |
| * 5.Force on IA for early csys_req |
| * 6.Modify AT command |
| * |
| * 03 11 2019 che-wei.chang |
| * [MOLY00389209] [MT6297] topsm/ost for apollo dram power index |
| * |
| * 01 31 2019 guo-huei.chang |
| * [MOLY00353483] [GEN95] MD Low Power Monitor |
| * fix build error for GEN95 |
| * |
| * 01 31 2019 guo-huei.chang |
| * [MOLY00353483] [GEN95] MD Low Power Monitor |
| * |
| * merge MD Low Power Monitor from UMOLYE (OSTD & Sleep Driver Part) |
| * |
| * 11 22 2018 guo-huei.chang |
| * [MOLY00366073] [Lafite] MD part of OPPO P80 sleep information |
| * 1.add MD sleep time and sleep count to share memory |
| * 2.add iA idle time to MD low power monitor |
| * |
| * 10 30 2018 leon.yeh |
| * [MOLY00356811] [GEN95] MD Low Power Monitor L1 modulo fill data |
| * - add debug data |
| * . |
| * |
| * 10 15 2018 leon.yeh |
| * [MOLY00356811] [GEN95] MD Low Power Monitor L1 modulo fill data |
| * - 4G TX/RX path interface modify. |
| * |
| * 09 14 2018 jack.tung |
| * [MOLY00351968] [DFR][Gen95] Assertion Removal |
| * |
| * . |
| * |
| * 09 04 2018 ej.farn |
| * [MOLY00332776] [Gen95] MD Low Power Montior Development |
| * [Gen95] MD Low Power Monitor |
| * |
| * 08 30 2018 ej.farn |
| * [MOLY00332776] [Gen95] MD Low Power Montior Development |
| * [Gen95] MD Low Power Monitor |
| * |
| * 08 28 2018 ej.farn |
| * [MOLY00332776] [Gen95] MD Low Power Montior Development |
| * [Gen95] MD Low Power Monitor |
| * |
| * 01 08 2019 owen.ho |
| * [MOLY00312416] [Gen97][Need Patch]Sleep driver development |
| * Add SLEEP_CTL_MML1 for MD95. |
| * |
| * 01 07 2019 owen.ho |
| * [MOLY00312416] [Gen97][Need Patch]Sleep driver development |
| * Modify lock 26m interface |
| * |
| * 01 02 2019 owen.ho |
| * [MOLY00312416] [Gen97][Need Patch]Sleep driver development |
| * Add lock sleep control enum for 97 |
| * |
| * 09 18 2018 owen.ho |
| * [MOLY00312416] [Gen97][Need Patch]Sleep driver development |
| * Add enum for 5G NL1 |
| * |
| * 08 17 2018 owen.ho |
| * [MOLY00312416] [Gen97][Need Patch]Sleep driver development |
| * Integrate Gen97 driver from UMOYE.Gen97.DEV |
| * |
| * 05 18 2018 owen.ho |
| * [MOLY00312416] [Gen97] Sleep driver development |
| * Gen97 sleep driver |
| * Solve build error for Gen97 |
| * 06 14 2018 che-wei.chang |
| * [MOLY00333397] [TOPSM/OST] remove legacy code and log reduction |
| * |
| * 05 29 2018 guo-huei.chang |
| * [MOLY00327413] [UMOLYE]Low power monitor patch sync |
| * md low power monitor (ostd part) |
| * |
| * 04 26 2018 che-wei.chang |
| * [MOLY00318930] [Eiger] topsm/ost - add lock sleep enum id for sim3/sim4 |
| * |
| * 04 02 2018 leon.yeh |
| * [MOLY00316801] for legacy chips option and feature options cleanup |
| * |
| * . |
| * |
| * 09 28 2017 che-wei.chang |
| * [MOLY00281049] [93/95 re-arch] MD topsm/ost |
| * |
| * 09 08 2017 jack.tung |
| * [MOLY00274378] [MD Platform Low-Power] Check Flight Mode Condition on HW Status |
| * |
| * 08 15 2017 owen.ho |
| * [MOLY00266818] [BIANCO][MT6763][MTBF][C2K][SIM1:CTC][SIM2:CU][ASSERT] file:mcu/common/driver/devdrv/log_seq/src/logseq_drv.c line:1195 |
| * Force on usip API |
| * |
| * 06 28 2017 jack.tung |
| * [MOLY00257950] [Gen93] Flight Mode Debugging Information Improvement |
| * |
| * <saved by Perforce> |
| * |
| * 06 20 2017 owen.ho |
| * [MOLY00258341] [MT6763][Bianco][N1][E2][MD issue][TW] Assert on ulsp_mod_function with PLS mode |
| * |
| * Add sleep control enum for PLS |
| * |
| * 06 12 2017 jack.tung |
| * [MOLY00256211] [Gen93][UMOLYA][SleepDrv] Step-Logging Feature |
| * |
| * <saved by Perforce> |
| * |
| * 05 08 2017 owen.ho |
| * [MOLY00247811] [Bianco] Fatal Error (0xb34, 0x90f9c520, 0xcccccccc) - SQN_EL1 when enabling ostd sleep |
| * |
| * 05 05 2017 owen.ho |
| * [MOLY00246118] [BIANCO]Assert fail: wuldch.c 1439 0x0 0x0 0x0 - (LISR)UL1D_HISR_LISR |
| * |
| * Add sleep controller enumeration |
| * |
| * 03 31 2017 guo-huei.chang |
| * [MOLY00238980] [DHL] MET timer for sync between MET & ELT |
| * add SleepDrv_GetWallClk function |
| * |
| * 03 08 2017 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * |
| * 1.Update sleep_ctl_user enum |
| * 2.Porting EMM debug info function |
| * 3.Correct sleepDisable variable index |
| * |
| * 01 19 2017 kevin-kh.liu |
| * [MOLY00173902] [MT6293][Sleep Mode]sleep mode modification |
| * xL1SIM 2G Fixed AFC support - SM part |
| * |
| * 12 30 2016 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * Update SLEEP_CTL enum list |
| * |
| * 12 20 2016 owen.ho |
| * [MOLY00171832] [UMOLYA][Bianco] Update SLEEP_CTL enum list |
| * |
| * 12 19 2016 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * Update sleep_ctl enum and md power domain enum |
| * |
| * 12 14 2016 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * |
| * Update SLEEP_CTL enum |
| * |
| * 12 12 2016 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * |
| * Update SLEEP_CTL user enum |
| * |
| * 12 09 2016 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * |
| * Add SLEEP control user enum |
| * |
| * 12 02 2016 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * |
| * Update lock/unlock core sleep control user list |
| * |
| * 11 23 2016 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * |
| * 6293 sleep driver development (Modoify Lock/Unlock Sleep API) |
| * |
| * 11 09 2016 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * |
| * Solve build error |
| * |
| * 07 20 2016 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * |
| * Gen93 topsm/ostd driver develpement |
| * |
| * 07 06 2016 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * 6293 topsm/ostd driver development |
| * |
| * 06 24 2016 owen.ho |
| * [MOLY00171832] [UMOLYA] |
| * GEN93 md topsm/ostd driver development |
| * |
| * 03 31 2016 vmick.lin |
| * [MOLY00171891] [6293] sleep driver development |
| * |
| * . |
| * |
| * 03 30 2016 vmick.lin |
| * [MOLY00171891] [6293] sleep driver development |
| * |
| * . |
| * |
| * 03 15 2016 james.pan |
| * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation |
| * EL1-EL2 lock LMAC power Sleep Driver for EL1 part (without trigger CCIRQ) |
| * |
| * 03 14 2016 james.pan |
| * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation |
| * 1. MSBB Violation |
| * 2. Remove EL1D DVFS avtive window check |
| * 3. 4G sleep mode locker for DVFS drivers |
| * 4. Add Data Sync Barrier |
| * 5. Rename global veriable |
| * 6. LMAC locker API implement |
| * 7. EL1D Backup functions relocated |
| * |
| * 03 11 2016 james.pan |
| * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation |
| * Rollback CL2258329 CL2158833 CL2159108 |
| * |
| * 03 07 2016 james.pan |
| * [MOLY00166205] [6292][Sleep Mode][EL1SM] development and validation |
| * md_sm sleep_drv MSBB violation |
| * |
| * 02 23 2016 kevin-kh.liu |
| * [MOLY00163589] [6292][sleep mode] code merge from LR11 to UMOLY |
| * |
| * Sleep Mode Debug Shared Memory Mechanism |
| * |
| * 02 18 2016 leon.yeh |
| * [MOLY00165273] [6292][sleep mode] code merge from LR11 to UMOLY (fixAFC & 32K-less) - fix build error: INVALID_FREQ_OFF define changed to sleepdrv_interface.h |
| * |
| * 02 16 2016 dennis.chueh |
| * [MOLY00141188] [ELBRUS][FPGA] Add new features. |
| * Share memory debug functions: |
| * void SleepDrv_UpdatePSSlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value); |
| * void SleepDrv_UpdateL1SlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value); |
| * void SleepDrv_SlpDbgShmRingBufAdd(SLP_DBG_SHM_RING_BUFFER_INDEX index, kal_uint32 status, kal_uint32 dbg_info); |
| * |
| * 01 29 2016 jack.tung |
| * [MOLY00163331] MD-TOPSM API Atomicity Access Implementation |
| * Atomicity Operation Test and Implementation for TOPSM Software Force-On Control |
| * |
| * 01 20 2016 shengfu.tsai |
| * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus |
| * |
| * .fixed xl1sm build issue |
| * |
| * 01 19 2016 shengfu.tsai |
| * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus |
| * |
| * . modify l1sm\ul1sm include file to meet MSBB rule |
| * |
| * 11 03 2015 dennis.chueh |
| * [MOLY00141188] [ELBRUS][FPGA] Add new features. |
| * |
| * Add ENUM define for drvtest. |
| * Add Power down API. |
| * |
| * 11 02 2015 dennis.chueh |
| * [MOLY00141188] [ELBRUS][FPGA] Add new features. |
| * |
| * add MIPS_CPC_PowerOn to sleepdrv_interface.h. |
| * |
| * 10 30 2015 shengfu.tsai |
| * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus |
| * |
| * .merge some change from XL1SM branch |
| * |
| * 08 17 2015 dennis.chueh |
| * [MOLY00070771] [6291][FPGA]solve build error |
| * Solve build error after applying ELBRUS_FPGA. |
| * |
| * 08 16 2015 dennis.chueh |
| * [MOLY00070771] [6291][FPGA]solve build error |
| * Solve build error after applying ELBRUS make file. |
| * |
| * 08 13 2015 dennis.chueh |
| * [MOLY00070771] [6291][FPGA]solve build error |
| * Solve build error after merging back to UMOLY trunk. |
| * |
| * 08 13 2015 dennis.chueh |
| * [MOLY00070771] [6291][FPGA]solve build error |
| * Solve build error after merging back. |
| * |
| * 08 12 2015 shengfu.tsai |
| * [MOLY00124310] [6291 plus][sleep mode] code merge from UMOLY to 91plus |
| * .add SleepDrv_LockPcoreSleepMode and SleepDrv_LockLMACPower |
| * but these function need to modify in the future |
| * |
| * 08 04 2015 dennis.chueh |
| * [MOLY00070771] [6291][FPGA]solve build error |
| * SleepDrv_GetHandle() --> SleepDrv_GetHandle(SMP). |
| * |
| * 07 23 2015 guo-huei.chang |
| * [MOLY00131103] Sleep Mode Debug Shared Memory Mechanism Improvement |
| * 1. add CCIRQ CMD for L1core querying shared memory address |
| * 2. add fix pat API for PScore and L1core and ring buffer API for L1core |
| * 3. add fix pat in CheckSleep function |
| * 4. add declarion for DBM and PTPOD shared memory |
| * |
| * 06 11 2015 che-wei.chang |
| * [MOLY00089700] [TK6291][UMOLY] |
| * 1.add MT6755 flag for Jade |
| * 2.update ostd elt log |
| * 3.update SleepDrv_GetHandle return value for assert |
| * |
| * 05 05 2015 che-wei.chang |
| * [MOLY00089700] [TK6291][UMOLY] add enum PS_PLL_FORCEON_USER_SIB to PS_PLL_FORCEON_USER for SIB |
| * |
| * 04 29 2015 che-wei.chang |
| * [MOLY00089700] [TK6291][UMOLY] add a new API MD_TOPSM_PLL_SW_Control for force on PS side PLLs |
| * |
| * 04 29 2015 che-wei.chang |
| * [MOLY00089700] [TK6291][UMOLY] Sync vmick Cbr (Ccirq) |
| * |
| * 02 26 2015 che-wei.chang |
| * [MOLY00089700] [TK6291][UMOLY] Sync MT6291_DEV branch |
| * |
| * 02 10 2015 yu-hung.huang |
| * [MOLY00095165] [TK6291] Check in LITE GPT Driver and New Sleep API |
| * [UMOLY] 2-leve GPT solution: refine SRCLK (26M) force on/off API interface for multiple user |
| * |
| * 09 05 2014 yu-hung.huang |
| * [MOLY00078094] [UMOLY] Sleep Codes Sync from MOLY TRUNK to UMOLY TK6291_DEV |
| * [TK6291_DEV] Sync SD3 Sleep Driver Codes from MOLY TRUNK to UMOLY (Changelists before 2014/9/4 in MOLY TRUNK) |
| * |
| * 08 27 2014 vmick.lin |
| * [MOLY00075930] [MT6582LTE][CSFB DSDS][HQ][Ericsson][lwg bin] [ASSERT] file:rf_conflict_check.c line:97 |
| * . |
| * |
| * 08 27 2014 vmick.lin |
| * [MOLY00075930] [MT6582LTE][CSFB DSDS][HQ][Ericsson][lwg bin] [ASSERT] file:rf_conflict_check.c line:97 |
| * . |
| * |
| * 08 26 2014 vmick.lin |
| * [MOLY00075930] [MT6582LTE][CSFB DSDS][HQ][Ericsson][lwg bin] [ASSERT] file:rf_conflict_check.c line:97 |
| * . |
| * Add 99T 32K period while OST struggle in SETTLE state |
| * |
| * 10 25 2013 alvin.chen |
| * [MOLY00043719] [MT6290][MDTOPSM] Patch for Phone Field trial activity |
| * Integration change. |
| * |
| * 10 03 2013 alvin.chen |
| * [MOLY00040177] [MT6290][MD_TOPSM] Add FRC enable API for Early Stage Debug |
| * <saved by Perforce> |
| * |
| * 07 26 2013 barry.hong |
| * [MOLY00030921] [MT6290]Low Power Feature patch back from CBr |
| * Low Power Feature patch back from CBr |
| * |
| * 02 26 2013 jeff.lee |
| * reorg. header file. |
| * |
| * |
| * |
| *------------------------------------------------------------------------------ |
| * Upper this line, this part is controlled by ClearCase. DO NOT MODIFY!! |
| *============================================================================ |
| ****************************************************************************/ |
| |
| |
| |
| #ifndef __SLEEPDRV_INTERFACE_H__ |
| #define __SLEEPDRV_INTERFACE_H__ |
| |
| #include "kal_public_api.h" //MSBB change #include "kal_release.h" |
| #include "sleepdrv_common.h" |
| |
| |
| #if defined(__SMART_PHONE_MODEM__) && defined(__MODEM_CCCI_EXIST__) && defined(__HIF_SDIO_SUPPORT__) |
| #define PHONE_TYPE_FOR_HQA |
| #endif |
| |
| #define BIG_DAC_CHANGE_RECALIBRATION /* This compiler option is default defined in Moly branch to enable this feature */ |
| |
| #ifdef BIG_DAC_CHANGE_RECALIBRATION |
| #define FREQ_OFF_THR 11700 /* 13ppm freqeuncy offset based on 900MHz */ |
| #define FREQ_OFF_VALID 65528 /* Valid DAC frequency offset shall be below 8191x8=65528(Hz) */ |
| #define INVALID_FREQ_OFF 0x7FFFFFFF /* When L1D/UL1D detect the frequency error is unreliable, return 0x7FFFFFFF to sleep mode */ |
| #endif //BIG_DAC_CHANGE_RECALIBRATION |
| |
| typedef enum |
| { |
| PS_USIP_FORCEON_USER_AUDIO = 0, |
| PS_USIP_FORCEON_USER_LOG, |
| NUM_OF_USIP_FORCEON_USER |
| } PS_USIP_FORCEON_USER; |
| |
| typedef enum |
| { |
| SRCLK_FORCEON_USER_SIM = 0, |
| SRCLK_FORCEON_USER_USB, |
| #if defined(__MD97__) && defined(__MTK_TARGET__) && defined(MT6297) |
| SRCLK_FORCEON_USER_DRAM, |
| #endif |
| NUM_OF_SRCLK_FORCEON_USER |
| } SRCLK_FORCEON_USER; |
| |
| typedef enum |
| { |
| PS_PLL_FORCEON_USER_CTI = 0, |
| PS_PLL_FORCEON_USER_SIB, |
| NUM_OF_PLL_FORCEON_USER |
| } PS_PLL_FORCEON_USER; |
| |
| typedef enum |
| { |
| #if defined(__MD93__) |
| PS_TOPSM_MDCORE_PLL = 0, |
| PS_TOPSM_BUS2X_PLL, |
| PS_TOPSM_F208M_PLL, |
| PS_TOPSM_DBG_PLL, |
| PS_TOPSM_LOG_PLL, |
| PS_TOPSM_SDF_ATB_PLL, |
| NUM_OF_PS_TOPSM_PLL, |
| #elif defined(__MD95__) |
| PS_TOPSM_MDCORE_PLL = 0, |
| PS_TOPSM_BUS2X_PLL = 1, |
| PS_TOPSM_F208M_PLL = 2, |
| PS_TOPSM_DBG_PLL = 3, |
| PS_TOPSM_LOG_PLL = 4, |
| PS_TOPSM_SDF_ATB_PLL = 5, |
| PS_TOPSM_MML2_PLL = 6, |
| NUM_OF_PS_TOPSM_PLL = 7, |
| #elif defined(__MD97__) || defined(__MD97P__) |
| PS_TOPSM_MDCORE_PLL = 0, |
| PS_TOPSM_BUS4X_PLL = 1, |
| PS_TOPSM_F208M_PLL = 2, |
| PS_TOPSM_DBG_PLL = 3, |
| PS_TOPSM_LOG_PLL = 4, |
| PS_TOPSM_SDF_ATB_PLL = 5, |
| PS_TOPSM_MML2_PLL = 6, |
| PS_TOPSM_SHAOLIN_PLL = 7, |
| PS_TOPSM_IA_PLL = 8, |
| NUM_OF_PS_TOPSM_PLL = 9, |
| #else |
| #error "no chip match" |
| #endif |
| } PS_TOPSM_PLL; |
| |
| typedef enum |
| { |
| #if defined(__MD93__) |
| SLEEP_CTL_SLEEP_DRV = 0, // 0x00, Allow AT cmd to control cores' sleep function |
| SLEEP_CTL_SCC = 1, // 0x01, Disable sleep for PHY capture debug usage |
| SLEEP_CTL_MML2 = 2, // 0x02, For MML2 force on period, IA cannot sleep |
| SLEEP_CTL_LHIF = 3, // 0x03, For CLDMA uplink scenario |
| SLEEP_CTL_DVFS = 4, // 0x04, Keep MD awake while debugging gear changing and PLL ready interrupt |
| SLEEP_CTL_3G_FDD_UL1D = 5, // 0x05, L1 lock CORE1 sleep before sending L2P CCIRQ to core1 |
| SLEEP_CTL_USB = 6, // 0x06, To lock sleep when driver get rx gpd done event |
| SLEEP_CTL_ADT = 7, // 0x07, DL data by GDMA to ISPRAM0, we need to avoid power down core0 |
| SLEEP_CTL_L4 = 8, // 0x08, AT+ESLP to control sleep mode |
| SLEEP_CTL_3G_TDD_TL1 = 9, // 0x09, TL1 lock core0 sleep in TL1C/TL1D wake up state and unlock core0 sleep in TL1C/TL1D sleep state |
| SLEEP_CTL_USIM0 = 10, // 0x0A, |
| SLEEP_CTL_USIM1 = 11, // 0x0B, |
| SLEEP_CTL_USIM2 = 12, // 0x0C, |
| SLEEP_CTL_USIM3 = 13, // 0x0D, |
| SLEEP_CTL_C2K_1X = 14, // 0x0E, |
| SLEEP_CTL_C2K_DO = 15, // 0x0F, |
| SLEEP_CTL_C2K_SS = 16, // 0x10, |
| SLEEP_CTL_2G_TDD_MPAL = 17, // 0x11, GAS lock CORE1 sleep before sending msg to core1 |
| SLEEP_CTL_FM = 18, // 0x12, Lock sleep while do calibration |
| SLEEP_CTL_EL1SM = 19, // 0x13, To lock core0/core1 sleep when LTE timer wakeup |
| SLEEP_CTL_EL1SM_DEBUG = 20, // 0x14, Debug for LTE sleep mode verify |
| SLEEP_CTL_UL1SM = 21, // 0x15, To lock core0 sleep when 3G FDD timer wakeup |
| SLEEP_CTL_L1SM = 22, // 0x16, To lock core0 sleep when 2G timer wakeup |
| SLEEP_CTL_GCU = 23, // 0x17, |
| SLEEP_CTL_IDC = 24, // 0x18, Lock core until idc_uart tx confirms last two bytes of data was sent |
| SLEEP_CTL_SPEECH = 25, // 0x19, Lock core while MD speech is working |
| SLEEP_CTL_MTD_NAND = 26, // 0x1A, Not used in 93, but owner request to perserve for future use |
| SLEEP_CTL_RR_FDD = 27, // 0x1B, To Lock/Unlock MPAL sleep |
| SLEEP_CTL_2G_SMM_DPS = 28, // 0x1C, To Lock/Unlock 2G SMM in Dummy PS TASK |
| SLEEP_CTL_3G_SMM_DPS = 29, // 0x1D, To Lock/Unlock 3G SMM in Dummy PS TASK |
| SLEEP_CTL_3G_FDD_SLCE = 30, // 0x1E, To Lock CORE1 sleep when in 3G connected mode for stack 1 |
| SLEEP_CTL_3G_FDD_SLCE2 = 31, // 0x1F, To Lock CORE1 sleep when in 3G connected mode for stack 2 |
| SLEEP_CTL_3G_FDD_SLCE3 = 32, // 0x20, To Lock CORE1 sleep when in 3G connected mode for stack 3 |
| SLEEP_CTL_EL2 = 33, // 0x21, To ensure mcu awake until EL2 polling complete |
| SLEEP_CTL_ERRC = 34, // 0x22, Lock current core for avoiding delay when lower layer control |
| SLEEP_CTL_ERRC2 = 35, // 0x23, Because in the L+L architecture, ERRC1 and ERRC2 are in the same task, both has sleep mode control requirement |
| SLEEP_CTL_PLS = 36, // 0x24, Lock sleep to make sure the user's tag will succeed in the PLS logging mode. |
| SLEEP_CTL_SIM1 = 37, // 0x25, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| SLEEP_CTL_SIM2 = 38, // 0x26, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| SLEEP_CTL_SIM3 = 39, // 0x27, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| SLEEP_CTL_SIM4 = 40, // 0x28, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| MAX_SLEEP_HANDLE = 46 |
| #elif defined(__MD95__) |
| SLEEP_CTL_SLEEP_DRV = 0, // 0x00, Allow AT cmd to control cores' sleep function |
| SLEEP_CTL_SCC = 1, // 0x01, Disable sleep for PHY capture debug usage |
| SLEEP_CTL_MML2 = 2, // 0x02, For MML2 force on period, IA cannot sleep |
| SLEEP_CTL_LHIF = 3, // 0x03, For CLDMA uplink scenario |
| SLEEP_CTL_DVFS = 4, // 0x04, Keep MD awake while debugging gear changing and PLL ready interrupt |
| SLEEP_CTL_USB = 5, // 0x05, To lock sleep when driver get rx gpd done event |
| SLEEP_CTL_L4 = 6, // 0x06, AT+ESLP to control sleep mode |
| SLEEP_CTL_3G_TDD_TL1 = 7, // 0x07, TL1 lock core0 sleep in TL1C/TL1D wake up state and unlock core0 sleep in TL1C/TL1D sleep state |
| SLEEP_CTL_USIM0 = 8, // 0x08, |
| SLEEP_CTL_USIM1 = 9, // 0x09, |
| SLEEP_CTL_USIM2 = 10, // 0x0A, |
| SLEEP_CTL_USIM3 = 11, // 0x0B, |
| SLEEP_CTL_C2K_1X = 12, // 0x0C, |
| SLEEP_CTL_C2K_DO = 13, // 0x0D, |
| SLEEP_CTL_C2K_SS = 14, // 0x0E, |
| SLEEP_CTL_2G_TDD_MPAL = 15, // 0x0F, GAS lock CORE1 sleep before sending msg to core1 |
| SLEEP_CTL_FM = 16, // 0x10, Lock sleep while do calibration |
| SLEEP_CTL_EL1SM = 17, // 0x11, To lock core0/core1 sleep when LTE timer wakeup |
| SLEEP_CTL_EL1SM_DEBUG = 18, // 0x12, Debug for LTE sleep mode verify |
| SLEEP_CTL_UL1SM = 19, // 0x13, To lock core0 sleep when 3G FDD timer wakeup |
| SLEEP_CTL_L1SM = 20, // 0x14, To lock core0 sleep when 2G timer wakeup |
| SLEEP_CTL_IDC = 21, // 0x15, Lock core until idc_uart tx confirms last two bytes of data was sent |
| SLEEP_CTL_MTD_NAND = 22, // 0x16, Not used in 93, but owner request to perserve for future use |
| SLEEP_CTL_RR_FDD = 23, // 0x17, To Lock/Unlock MPAL sleep |
| SLEEP_CTL_2G_SMM_DPS = 24, // 0x18, To Lock/Unlock 2G SMM in Dummy PS TASK |
| SLEEP_CTL_3G_SMM_DPS = 25, // 0x19, To Lock/Unlock 3G SMM in Dummy PS TASK |
| SLEEP_CTL_3G_FDD_SLCE = 26, // 0x1A, To Lock CORE1 sleep when in 3G connected mode for stack 1 |
| SLEEP_CTL_3G_FDD_SLCE2 = 27, // 0x1B, To Lock CORE1 sleep when in 3G connected mode for stack 2 |
| SLEEP_CTL_3G_FDD_SLCE3 = 28, // 0x1C, To Lock CORE1 sleep when in 3G connected mode for stack 3 |
| SLEEP_CTL_ERRC = 29, // 0x1D, Lock current core for avoiding delay when lower layer control |
| SLEEP_CTL_ERRC2 = 30, // 0x1E, because in the L+L architecture, ERRC1 and ERRC2 are in the same task, both has sleep mode control requirement |
| SLEEP_CTL_PLS = 31, // 0x1F, lock sleep to make sure the user's tag will successd in PLS logging mode |
| SLEEP_CTL_SS = 32, // 0x20, for performance profiling |
| SLEEP_CTL_SOE = 33, // 0x21, lock CPU when using SOE |
| SLEEP_CTL_SPEECH = 34, // 0x22, reserved enum for speech |
| SLEEP_CTL_SIM1 = 35, // 0x23, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| SLEEP_CTL_SIM2 = 36, // 0x24, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| SLEEP_CTL_SIM3 = 37, // 0x25, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| SLEEP_CTL_SIM4 = 38, // 0x26, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| SLEEP_CTL_MML1 = 39, |
| MAX_SLEEP_HANDLE = 40 |
| #elif defined(__MD97__) || defined(__MD97P__) |
| SLEEP_CTL_SLEEP_DRV = 0, // 0x00, Allow AT cmd to control cores' sleep function |
| SLEEP_CTL_SCC = 1, // 0x01, Disable sleep for PHY capture debug usage |
| SLEEP_CTL_MML2 = 2, // 0x02, For MML2 force on period, IA cannot sleep |
| SLEEP_CTL_LHIF = 3, // 0x03, For CLDMA uplink scenario |
| SLEEP_CTL_DVFS = 4, // 0x04, Keep MD awake while debugging gear changing and PLL ready interrupt |
| SLEEP_CTL_USB = 5, // 0x05, To lock sleep when driver get rx gpd done event |
| SLEEP_CTL_L4 = 6, // 0x06, AT+ESLP to control sleep mode |
| SLEEP_CTL_3G_TDD_TL1 = 7, // 0x07, TL1 lock core0 sleep in TL1C/TL1D wake up state and unlock core0 sleep in TL1C/TL1D sleep state |
| SLEEP_CTL_USIM0 = 8, // 0x08 |
| SLEEP_CTL_USIM1 = 9, // 0x09 |
| SLEEP_CTL_USIM2 = 10, // 0x0A |
| SLEEP_CTL_USIM3 = 11, // 0x0B |
| SLEEP_CTL_C2K_1X = 12, // 0x0C |
| SLEEP_CTL_C2K_DO = 13, // 0x0D |
| SLEEP_CTL_C2K_SS = 14, // 0x0E |
| SLEEP_CTL_2G_TDD_MPAL = 15, // 0x0F, GAS lock CORE1 sleep before sending msg to core1 |
| SLEEP_CTL_FM = 16, // 0x10, Lock sleep while do calibration |
| SLEEP_CTL_EL1SM = 17, // 0x11, To lock core0/core1 sleep when LTE timer wakeup |
| SLEEP_CTL_EL1SM_DEBUG = 18, // 0x12, Debug for LTE sleep mode verify |
| SLEEP_CTL_UL1SM = 19, // 0x13, To lock core0 sleep when 3G FDD timer wakeup |
| SLEEP_CTL_L1SM = 20, // 0x14, To lock core0 sleep when 2G timer wakeup |
| SLEEP_CTL_IDC = 21, // 0x15, Lock core until idc_uart tx confirms last two bytes of data was sent |
| SLEEP_CTL_MTD_NAND = 22, // 0x16, Not used in 93, but owner request to perserve for future use |
| SLEEP_CTL_RR_FDD = 23, // 0x17, To Lock/Unlock MPAL sleep |
| SLEEP_CTL_2G_SMM_DPS = 24, // 0x18, To Lock/Unlock 2G SMM in Dummy PS TASK |
| SLEEP_CTL_3G_SMM_DPS = 25, // 0x19, To Lock/Unlock 3G SMM in Dummy PS TASK |
| SLEEP_CTL_3G_FDD_SLCE = 26, // 0x1A, To Lock CORE1 sleep when in 3G connected mode for stack 1 |
| SLEEP_CTL_3G_FDD_SLCE2 = 27, // 0x1B, To Lock CORE1 sleep when in 3G connected mode for stack 2 |
| SLEEP_CTL_3G_FDD_SLCE3 = 28, // 0x1C, To Lock CORE1 sleep when in 3G connected mode for stack 3 |
| SLEEP_CTL_ERRC = 29, // 0x1D, Lock current core for avoiding delay when lower layer control |
| SLEEP_CTL_ERRC2 = 30, // 0x1E, Because in the L+L architecture, ERRC1 and ERRC2 are in the same task, both has sleep mode control requirement |
| SLEEP_CTL_PLS = 31, // 0x1F, lock sleep to make sure the user's tag will successd in PLS logging mode |
| SLEEP_CTL_SS = 32, // 0x20, for performance profiling |
| SLEEP_CTL_SOE = 33, // 0x21, lock CPU when using SOE |
| SLEEP_CTL_SPEECH = 34, // 0x22, reserved enum for speech |
| SLEEP_CTL_SIM1 = 35, // 0x23, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| SLEEP_CTL_SIM2 = 36, // 0x24, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| SLEEP_CTL_SIM3 = 37, // 0x25, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| SLEEP_CTL_SIM4 = 38, // 0x26, For SIM Task will preempt OS for seconds, use it to notify OSTD it is running |
| SLEEP_CTL_NL1SM = 39, // 0x27 |
| SLEEP_CTL_NL1SM_DEBUG = 40, // 0x28 |
| SLEEP_CTL_MML1 = 41, // 0x29 |
| SLEEP_CTL_USB_2 = 42, // 0x2A |
| SLEEP_CTL_CLDMA = 43, // 0x2B |
| SLEEP_CTL_LVTS_RESET = 44, // 0x2C |
| SLEEP_CTL_MCF = 45, // 0x2D |
| SLEEP_CTL_USBCORE = 46, // 0x2E |
| MAX_SLEEP_HANDLE = 47 |
| #else |
| #error "no chip match" |
| #endif |
| |
| } SLEEP_CTL_USER; |
| |
| |
| typedef enum |
| { |
| MDLPM_VERSION = 0, //MDLPM_VERSION |
| MDLPM_REC_INDEX = 1, //MD RECORD INDEX |
| MDLPM_UTC_0 = 2, //UTC 0~31 bits |
| MDLPM_UTC_1 = 3, //UTC 32~63 bits |
| MDLPM_FRC = 4, //MD Free RUN Counter |
| MDLPM_TIMESTAMP = 5, //MD UTC Timestamp |
| MDLPM_WALL_CLK_0 = 6, //MD Wall Clock 0~31 bits |
| MDLPM_WALL_CLK_1 = 7, //MD Wall Clock 32~63 bits |
| MDLPM_MD_SLEEP_DUR = 8, //MD 26M Off tick |
| MDLPM_SOC_SLEEP_DUR = 9, //SOC 26M off tick |
| MDLPM_MD_TOPSM_PWR_RDY = 10, //MD_TOPSM PWR READY |
| MDLPM_MD_SW_LOCK_0 = 11, //SW Lock 0~31 bit |
| MDLPM_MD_SW_LOCK_1 = 12, //SW Lock 32~64 bit |
| MDLPM_MD_DATA13 = 13, //unused |
| MDLPM_MD_DATA14 = 14, //unused |
| MDLPM_MD_OST_F32_WAKEUP_0 = 15, //32k wakeup event 0~31 bit |
| MDLPM_MD_OST_F32_WAKEUP_1 = 16, //32k wakeup event 32~63 bit |
| MDLPM_MD_OST_26M_WAKEUP_0 = 17, //26m wakeup event 0~31 bit |
| MDLPM_MD_OST_26M_WAKEUP_1 = 18, //26m wakeup event 32~63 bit |
| MDLPM_MD_TOPSM_SLV_REQ_STA = 19, //MD_TOPSM SLV_REQ |
| MDLPM_MD_TOPSM_DBG_REQ_STA = 20, //MD_TOPSM DBG_REQ |
| MDLPM_MDMCU_IDLE_TIME = 21, //Reserve for MD_TOPSM extend |
| MDLPM_USIP_IDLE_TIME = 22, //Reserve for MD_TOPSM extend |
| MDLPM_DATA23 = 23, //Reserve for MD_TOPSM extend |
| |
| // AMIF & MD DVFS |
| MDLPM_AMIF_GROUP_0 = 24, //unused |
| MDLPM_AMIF_GROUP_1 = 25, //unused |
| MDLPM_AMIF_GROUP_2 = 26, //unused |
| MDLPM_AMIF_GROUP_3 = 27, //unused |
| MDLPM_AMIF_GROUP_4 = 28, //unused |
| MDLPM_AMIF_GROUP_5 = 29, //unused |
| MDLPM_AMIF_GROUP_6 = 30, //unused |
| MDLPM_AMIF_GROUP_7 = 31, //unused |
| MDLPM_MD_DVFS_GEAR_0 = 32, //MD DVFS |
| MDLPM_MD_DVFS_GEAR_1 = 33, //MD DVFS |
| MDLPM_MD_DVFS_GEAR_2 = 34, //MD DVFS |
| MDLPM_MD_DVFS_GEAR_3 = 35, //MD DVFS |
| MDLPM_MD_DVFS_GEAR_4 = 36, //MD DVFS |
| MDLPM_MD_DVFS_GEAR_5 = 37, //MD DVFS |
| MDLPM_MD_DVFS_GEAR_6 = 38, //MD DVFS |
| MDLPM_MD_DVFS_GEAR_7 = 39, //MD DVFS |
| |
| //Others |
| MDLPM_DATA40 = 40, //unused |
| MDLPM_DATA41 = 41, //unused |
| MDLPM_DATA42 = 42, //unused |
| MDLPM_DATA43 = 43, //unused |
| MDLPM_VOLTE_UL = 44, //VOLTE UL |
| MDLPM_VOLTE_DL = 45, //VOLTE DL |
| MDLPM_VOLTE_CODEC = 46, //VOLTE CODEC |
| MDLPM_DATA47 = 47, //unsued |
| |
| /* debug info in 93 adding */ |
| MDLPM_GL1_SLEEP_ACTIVE_DUR = 48, //2G acc sleep info. |
| MDLPM_GL1_SLEEP_STATUS = 49, //2G sleep status info. |
| MDLPM_UL1_SLEEP_ACTIVE_DUR = 50, //3G acc sleep info. |
| MDLPM_UL1_SLEEP_STATUS = 51, //2G sleep status info. |
| MDLPM_EL1_SLEEP_ACTIVE_DUR = 52, //3G acc sleep info. |
| MDLPM_EL1_SLEEP_STATUS = 53, //2G sleep status info. |
| MDLPM_MODEM_TOPSM_SM_TOPSM_APP_OUTCR_SET = 54, |
| MDLPM_MODEM_TOPSM_SM_DBG_REQ_STA = 55, |
| MDLPM_MODEM_TOPSM_DEBUG = 56, |
| /* debug info in 93 adding end */ |
| /* 2G L1 behavior list */ |
| MDLPM_GL1_BCCH = 57, |
| MDLPM_GL1_PAGING = 58, |
| MDLPM_GL1_CBCH = 59, |
| MDLPM_GL1_POWER_SCAN = 60, |
| MDLPM_GL1_BSIC_READ = 61, //FB/SB |
| MDLPM_GL1_STANDBY_GAP = 62, |
| MDLPM_GL1_ACCESS = 63, //Access mode is RACH in UL and listening AGCH/CCCH in DL |
| MDLPM_GL1_CS = 64, //dedicated mode circuit-switch |
| MDLPM_GL1_PS = 65, //dedicated mode packet-switch |
| /* 3G L1 behavior list */ |
| MDLPM_UL1_BCH = 66, //BCH channel such as SIB/SFN |
| MDLPM_UL1_PCH = 67, //PCH channel |
| MDLPM_UL1_CTCH = 68, //CTCH channel |
| MDLPM_UL1_FS = 69, //frequency scan or power scan |
| MDLPM_UL1_CS = 70, //cell search |
| MDLPM_UL1_CM = 71, //cell measurement |
| MDLPM_UL1_TAS = 72, //TAS/RAS feature |
| MDLPM_UL1_ACTIVE_GAP = 73, //active gap assignment |
| MDLPM_UL1_STANDBY_GAP = 74, //receive standby gap |
| MDLPM_UL1_FACH = 75, //FACH/RACH channel |
| MDLPM_UL1_DCH = 76, //DCH channel |
| MDLPM_UL1_R5R6 = 77, //R5/R6 channel |
| MDLPM_UL1_R7R8 = 78, //R7/R8 channel |
| MDLPM_UL1_OTHERS = 79, |
| MDLPM_UL1_RESOURCE = 80, //RTB or Inter-SIM resource |
| MDLPM_UL1_CC = 81, //channel/mode change |
| MDLPM_UL1_DDL = 82, //DDL |
| MDLPM_UL1_EM = 83, //EM |
| /* 4G L1 behavior list */ |
| MDLPM_EL1_MIB_SIB = 84, |
| MDLPM_EL1_PAGE = 85, |
| MDLPM_EL1_CSR = 86, |
| MDLPM_EL1_INTRA_CS = 87, |
| MDLPM_EL1_INTER_CS = 88, |
| MDLPM_EL1_INTRA_CM = 89, |
| MDLPM_EL1_INTER_CM = 90, |
| MDLPM_EL1_INTRA_POS = 91, |
| MDLPM_EL1_INTER_POS = 92, |
| MDLPM_EL1_MBMS = 93, |
| MDLPM_EL1_ACTIVE_GAP = 94, //active gap assignment |
| MDLPM_EL1_STANDBY_GAP = 95, //receive standby gap |
| MDLPM_EL1_CONNECT_START = 96, |
| MDLPM_EL1_CONNECT_END = 97, |
| MDLPM_EL1_CONNECT_DUR = 98, //accumulated connection duration |
| /* RAT L1 behavior list end */ |
| /* MLL1 activate RAT monitor data start*/ |
| MDLPM_SIM1_ACTIVATE_RAT = 99, //SIM1 activate RAT |
| MDLPM_SIM1_RAT_DRX = 100, //SIM1 activate RAT drx |
| MDLPM_SIM1_UPDATE_FRC = 101, //SIM1 info. update FRC |
| MDLPM_SIM2_ACTIVATE_RAT = 102, //SIM2 activate RAT |
| MDLPM_SIM2_RAT_DRX = 103, //SIM2 activate RAT drx |
| MDLPM_SIM2_UPDATE_FRC = 104, //SIM2 info. update FRC |
| MDLPM_SIM3_ACTIVATE_RAT = 105, //SIM3 activate RAT |
| MDLPM_SIM3_RAT_DRX = 106, //SIM3 activate RAT drx |
| MDLPM_SIM3_UPDATE_FRC = 107, //SIM3 info. update FRC |
| /* 2G monitor data start*/ |
| MDLPM_GL1_RX_WINDOW_DUR = 108, //2G RX window open duration |
| MDLPM_GL1_TX_WINDOW_DUR = 109, //2G TX window open duration |
| MDLPM_GL1_TX_POWER_REG1 = 110, //2G TX power region 1: 0 ~ 5dBm; [0, 5] |
| MDLPM_GL1_TX_POWER_REG2 = 111, //2G TX power region 2: 5 ~ 10dBm; (5, 10] |
| MDLPM_GL1_TX_POWER_REG3 = 112, //2G TX power region 3: 10 ~ 15dBm; (10, 15] |
| MDLPM_GL1_TX_POWER_REG4 = 113, //2G TX power region 4: 15 ~ 20dBm; (15, 20] |
| MDLPM_GL1_TX_POWER_REG5 = 114, //2G TX power region 5: 20 ~ 25dBm; (20, 25] |
| MDLPM_GL1_TX_POWER_REG6 = 115, //2G TX power region 6: 25 ~ 30dBm; (25, 30] |
| MDLPM_GL1_TX_POWER_REG7 = 116, //2G TX power region 7: 30 ~ 33dBm; (30, 33] |
| /* 2G monitor data end */ |
| /* 3G monitor data start */ |
| MDLPM_UL1_RX_WINDOW_START = 117, //3G RX window open start frc |
| MDLPM_UL1_TX_WINDOW_START = 118, //3G TX window open start frc |
| MDLPM_UL1_RX_PATH_USED = 119, //3G RX path used flag |
| MDLPM_UL1_TX_PATH_USED = 120, //3G TX path used flag |
| MDLPM_UL1_RX_PATH1_CNT = 121, //3G use RX path 1 used cnt |
| MDLPM_UL1_RX_PATH2_CNT = 122, //3G use RX path 2 used cnt |
| MDLPM_UL1_RX_PATH3_CNT = 123, //3G use RX path 3 used cnt |
| MDLPM_UL1_RX_PATH4_CNT = 124, //3G use RX path 4 used cnt |
| MDLPM_UL1_RX_PATH5_CNT = 125, //3G use RX path 5 used cnt |
| MDLPM_UL1_RX_PATH6_CNT = 126, //3G use RX path 6 used cnt |
| MDLPM_UL1_TX_PATH1_CNT = 127, //3G use TX path 1 used cnt |
| MDLPM_UL1_TX_PATH2_CNT = 128, //3G use TX path 2 used cnt |
| MDLPM_UL1_RX_WINDOW_DUR = 129, //3G RX window open duration |
| MDLPM_UL1_TX_WINDOW_DUR = 130, //3G TX window open duration |
| MDLPM_UL1_TX_POWER_REG1 = 131, //3G TX power region 1: <= -5dBm |
| MDLPM_UL1_TX_POWER_REG2 = 132, //3G TX power region 2: -5 ~ 1dBm; (-5, 1] |
| MDLPM_UL1_TX_POWER_REG3 = 133, //3G TX power region 3: 1 ~ 5dBm; (1,5] |
| MDLPM_UL1_TX_POWER_REG4 = 134, //3G TX power region 4: 5 ~ 10dBm; (5,10] |
| MDLPM_UL1_TX_POWER_REG5 = 135, //3G TX power region 5: 10 ~ 15dBm; (10,15] |
| MDLPM_UL1_TX_POWER_REG6 = 136, //3G TX power region 6: 15 ~ 20dBm; (15,20] |
| MDLPM_UL1_TX_POWER_REG7 = 137, //3G TX power region 7: 20 ~ 24dBm; (20,24] |
| MDLPM_UL1_LORX_MODE0 = 138, //3G LoRX mode 0 (LORX_OFF) cnt |
| MDLPM_UL1_LORX_MODE1 = 139, //3G LoRX mode 1 (LORX_ON) cnt |
| MDLPM_UL1_LORX_TRIG_FALSE = 140, //3G LoRX triger is false |
| MDLPM_UL1_LORX_TRIG_TRUE = 141, //3G LoRX triger is true |
| MDLPM_UL1_ARX_HPM = 142, //3G ARX mode 0 (HPM) cnt |
| MDLPM_UL1_ARX_LPM_VOICE = 143, //3G ARX mode 1 (LPM_VOICE) cnt |
| MDLPM_UL1_ARX_LPM_DATA = 144, //3G ARX mode 2 (LPM_DATA) cnt |
| MDLPM_UL1_RAS_1RX_INVALID = 145, //3G RAS mode 0 (1RX_INVALID) cnt |
| MDLPM_UL1_RAS_1RX_PATH_MAIN = 146, //3G RAS mode 1 (1RX_PATH_MAIN) cnt |
| MDLPM_UL1_RAS_2RX_PATH_BOTH = 147, //3G RAS mode 2 (2RX_PATH_BOTH) cnt |
| /* 3G monitor data end */ |
| /* 4G monitor data start */ |
| MDLPM_EL1_ACTIVE_1CC = 148, //active 1CC (Pcell only) cnt |
| MDLPM_EL1_ACTIVE_2CC = 149, //active 2CC cnt |
| MDLPM_EL1_ACTIVE_3CC = 150, //active 3CC cnt |
| MDLPM_EL1_ACTIVE_4CC = 151, //active 4CC cnt |
| MDLPM_EL1_ACTIVE_5CC = 152, //active 5CC cnt |
| MDLPM_EL1_CC_LAST = 153, //last active CC number |
| MDLPM_EL1_CC_LAST_FRC = 154, //last active CC number |
| MDLPM_EL1_RX_WINDOW_START = 155, //4G RX window open start frc |
| MDLPM_EL1_TX_WINDOW_START = 156, //4G TX window open start frc |
| MDLPM_EL1_RX_PATH_USED = 157, //4G RX path used flag |
| MDLPM_EL1_TX_PATH_USED = 158, //4G TX path used flag |
| MDLPM_EL1_RX_PATH1_CNT = 159, //4G use RX path 1 used cnt |
| MDLPM_EL1_RX_PATH2_CNT = 160, //4G use RX path 2 used cnt |
| MDLPM_EL1_RX_PATH3_CNT = 161, //4G use RX path 3 used cnt |
| MDLPM_EL1_RX_PATH4_CNT = 162, //4G use RX path 4 used cnt |
| MDLPM_EL1_RX_PATH5_CNT = 163, //4G use RX path 5 used cnt |
| MDLPM_EL1_TX_PATH1_CNT = 164, //4G use TX path 1 used cnt |
| MDLPM_EL1_TX_PATH2_CNT = 165, //4G use TX path 2 used cnt |
| MDLPM_EL1_RX_WINDOW_DUR = 166, //4G RX window open duration |
| MDLPM_EL1_TX_WINDOW_DUR = 167, //4G TX window open duration |
| MDLPM_EL1_TX_POWER_CC0_REG1 = 168, //4G CC0 TX power region 1: <= -5dBm |
| MDLPM_EL1_TX_POWER_CC0_REG2 = 169, //4G CC0 TX power region 2: -5 ~ 1dBm; (-5, 1] |
| MDLPM_EL1_TX_POWER_CC0_REG3 = 170, //4G CC0 TX power region 3: 1 ~ 5dBm; (1,5] |
| MDLPM_EL1_TX_POWER_CC0_REG4 = 171, //4G CC0 TX power region 4: 5 ~ 10dBm; (5,10] |
| MDLPM_EL1_TX_POWER_CC0_REG5 = 172, //4G CC0 TX power region 5: 10 ~ 15dBm; (10,15] |
| MDLPM_EL1_TX_POWER_CC0_REG6 = 173, //4G CC0 TX power region 6: 15 ~ 20dBm; (15,20] |
| MDLPM_EL1_TX_POWER_CC0_REG7 = 174, //4G CC0 TX power region 7: 20 ~ 23dBm; (20,23] |
| MDLPM_EL1_TX_POWER_CC0_REG8 = 175, //4G CC0 TX power region 8: 23 ~ 26dBm; (23,26] |
| MDLPM_EL1_TX_POWER_CC1_REG1 = 176, //4G CC1 TX power region 1: <= -5dBm |
| MDLPM_EL1_TX_POWER_CC1_REG2 = 177, //4G CC1 TX power region 2: -5 ~ 1dBm; (-5, 1] |
| MDLPM_EL1_TX_POWER_CC1_REG3 = 178, //4G CC1 TX power region 3: 1 ~ 5dBm; (1,5] |
| MDLPM_EL1_TX_POWER_CC1_REG4 = 179, //4G CC1 TX power region 4: 5 ~ 10dBm; (5,10] |
| MDLPM_EL1_TX_POWER_CC1_REG5 = 180, //4G CC1 TX power region 5: 10 ~ 15dBm; (10,15] |
| MDLPM_EL1_TX_POWER_CC1_REG6 = 181, //4G CC1 TX power region 6: 15 ~ 20dBm; (15,20] |
| MDLPM_EL1_TX_POWER_CC1_REG7 = 182, //4G CC1 TX power region 7: 20 ~ 23dBm; (20,23] |
| MDLPM_EL1_TX_POWER_CC1_REG8 = 183, //4G CC1 TX power region 8: 23 ~ 26dBm; (23,26] |
| MDLPM_EL1_TX_POWER_CC2_REG1 = 184, //4G CC2 TX power region 1: <= -5dBm |
| MDLPM_EL1_TX_POWER_CC2_REG2 = 185, //4G CC2 TX power region 2: -5 ~ 1dBm; (-5, 1] |
| MDLPM_EL1_TX_POWER_CC2_REG3 = 186, //4G CC2 TX power region 3: 1 ~ 5dBm; (1,5] |
| MDLPM_EL1_TX_POWER_CC2_REG4 = 187, //4G CC2 TX power region 4: 5 ~ 10dBm; (5,10] |
| MDLPM_EL1_TX_POWER_CC2_REG5 = 188, //4G CC2 TX power region 5: 10 ~ 15dBm; (10,15] |
| MDLPM_EL1_TX_POWER_CC2_REG6 = 189, //4G CC2 TX power region 6: 15 ~ 20dBm; (15,20] |
| MDLPM_EL1_TX_POWER_CC2_REG7 = 190, //4G CC2 TX power region 7: 20 ~ 23dBm; (20,23] |
| MDLPM_EL1_TX_POWER_CC2_REG8 = 191, //4G CC2 TX power region 8: 23 ~ 26dBm; (23,26] |
| MDLPM_EL1_TX_POWER_ALL_REG1 = 192, //4G total TX power region 1: <= -5dBm |
| MDLPM_EL1_TX_POWER_ALL_REG2 = 193, //4G total TX power region 2: -5 ~ 1dBm; (-5, 1] |
| MDLPM_EL1_TX_POWER_ALL_REG3 = 194, //4G total TX power region 3: 1 ~ 5dBm; (1,5] |
| MDLPM_EL1_TX_POWER_ALL_REG4 = 195, //4G total TX power region 4: 5 ~ 10dBm; (5,10] |
| MDLPM_EL1_TX_POWER_ALL_REG5 = 196, //4G total TX power region 5: 10 ~ 15dBm; (10,15] |
| MDLPM_EL1_TX_POWER_ALL_REG6 = 197, //4G total TX power region 6: 15 ~ 20dBm; (15,20] |
| MDLPM_EL1_TX_POWER_ALL_REG7 = 198, //4G total TX power region 7: 20 ~ 23dBm; (20,23] |
| MDLPM_EL1_TX_POWER_ALL_REG8 = 199, //4G total TX power region 8: 23 ~ 26dBm; (23,26] |
| MDLPM_EL1_LORX_MODE0 = 200, //4G LoRX mode 0 (LORX_OFF) cnt |
| MDLPM_EL1_LORX_MODE1 = 201, //4G LoRX mode 1 (LORX_TYPE1, symobol mode) cnt |
| MDLPM_EL1_LORX_MODE2 = 202, //4G LoRX mode 2 (LORX_TYPE2, PDCCH early stop) cnt |
| MDLPM_EL1_LORX_MODE3 = 203, //4G LoRX mode 3 (LORX_TYPE3, PDCCH early stop with sync) cnt |
| MDLPM_EL1_LOSX_CC0_ENABLE = 204, //4G LoSX CC0 enable cnt |
| MDLPM_EL1_LOSX_CC1_ENABLE = 205, //4G LoSX CC1 enable cnt |
| MDLPM_EL1_LOSX_CC2_ENABLE = 206, //4G LoSX CC2 enable cnt |
| MDLPM_EL1_LOSX_CC3_ENABLE = 207, //4G LoSX CC3 enable cnt |
| MDLPM_EL1_LOSX_CC4_ENABLE = 208, //4G LoSX CC4 enable cnt |
| MDLPM_EL1_LORX_TRIG_FALSE = 209, //4G LoRX triger is false |
| MDLPM_EL1_LORX_TRIG_TRUE = 210, //4G LoRX triger is true |
| MDLPM_EL1_LOSX_CC0_TRIG = 211, //4G LoSX CC0 triger cnt |
| MDLPM_EL1_LOSX_CC1_TRIG = 212, //4G LoSX CC1 triger cnt |
| MDLPM_EL1_LOSX_CC2_TRIG = 213, //4G LoSX CC2 triger cnt |
| MDLPM_EL1_LOSX_CC3_TRIG = 214, //4G LoSX CC3 triger cnt |
| MDLPM_EL1_LOSX_CC4_TRIG = 215, //4G LoSX CC4 triger cnt |
| MDLPM_EL1_CC0_ARX_HPM = 216, //4G ARX CC0 mode 0 (HPM) cnt |
| MDLPM_EL1_CC0_ARX_LPM_DATA = 217, //4G ARX CC0 mode 1 (LPM_DATA) cnt |
| MDLPM_EL1_CC0_ARX_LPM_LMCS = 218, //4G ARX CC0 mode 2 (LPM_LMCS) cnt |
| MDLPM_EL1_CC0_ARX_LPM_VOICE = 219, //4G ARX CC0 mode 3 (LPM_VOICE) cnt |
| MDLPM_EL1_CC0_ARX_LPM_HMCS = 220, //4G ARX CC0 mode 4 (LPM_HMCS) cnt |
| MDLPM_EL1_CC1_ARX_HPM = 221, //4G ARX CC1 mode 0 (HPM) cnt |
| MDLPM_EL1_CC1_ARX_LPM_DATA = 222, //4G ARX CC1 mode 1 (LPM_DATA) cnt |
| MDLPM_EL1_CC1_ARX_LPM_LMCS = 223, //4G ARX CC1 mode 2 (LPM_LMCS) cnt |
| MDLPM_EL1_CC1_ARX_LPM_VOICE = 224, //4G ARX CC1 mode 3 (LPM_VOICE) cnt |
| MDLPM_EL1_CC1_ARX_LPM_HMCS = 225, //4G ARX CC1 mode 4 (LPM_HMCS) cnt |
| MDLPM_EL1_CC2_ARX_HPM = 226, //4G ARX CC2 mode 0 (HPM) cnt |
| MDLPM_EL1_CC2_ARX_LPM_DATA = 227, //4G ARX CC2 mode 1 (LPM_DATA) cnt |
| MDLPM_EL1_CC2_ARX_LPM_LMCS = 228, //4G ARX CC2 mode 2 (LPM_LMCS) cnt |
| MDLPM_EL1_CC2_ARX_LPM_VOICE = 229, //4G ARX CC2 mode 3 (LPM_VOICE) cnt |
| MDLPM_EL1_CC2_ARX_LPM_HMCS = 230, //4G ARX CC2 mode 4 (LPM_HMCS) cnt |
| MDLPM_EL1_CC3_ARX_HPM = 231, //4G ARX CC3 mode 0 (HPM) cnt |
| MDLPM_EL1_CC3_ARX_LPM_DATA = 232, //4G ARX CC3 mode 1 (LPM_DATA) cnt |
| MDLPM_EL1_CC3_ARX_LPM_LMCS = 233, //4G ARX CC3 mode 2 (LPM_LMCS) cnt |
| MDLPM_EL1_CC3_ARX_LPM_VOICE = 234, //4G ARX CC3 mode 3 (LPM_VOICE) cnt |
| MDLPM_EL1_CC3_ARX_LPM_HMCS = 235, //4G ARX CC3 mode 4 (LPM_HMCS) cnt |
| MDLPM_EL1_CC4_ARX_HPM = 236, //4G ARX CC4 mode 0 (HPM) cnt |
| MDLPM_EL1_CC4_ARX_LPM_DATA = 237, //4G ARX CC4 mode 1 (LPM_DATA) cnt |
| MDLPM_EL1_CC4_ARX_LPM_LMCS = 238, //4G ARX CC4 mode 2 (LPM_LMCS) cnt |
| MDLPM_EL1_CC4_ARX_LPM_VOICE = 239, //4G ARX CC4 mode 3 (LPM_VOICE) cnt |
| MDLPM_EL1_CC4_ARX_LPM_HMCS = 240, //4G ARX CC4 mode 4 (LPM_HMCS) cnt |
| MDLPM_EL1_CC0_RAS_1RX = 241, //4G RAS CC0 mode 0 (1RX) cnt |
| MDLPM_EL1_CC0_RAS_2RX = 242, //4G RAS CC0 mode 1 (2RX) cnt |
| MDLPM_EL1_CC0_RAS_4RX = 243, //4G RAS CC0 mode 2 (4RX) cnt |
| MDLPM_EL1_CC1_RAS_1RX = 244, //4G RAS CC1 mode 0 (1RX) cnt |
| MDLPM_EL1_CC1_RAS_2RX = 245, //4G RAS CC1 mode 1 (2RX) cnt |
| MDLPM_EL1_CC1_RAS_4RX = 246, //4G RAS CC1 mode 2 (4RX) cnt |
| MDLPM_EL1_CC2_RAS_1RX = 247, //4G RAS CC2 mode 0 (1RX) cnt |
| MDLPM_EL1_CC2_RAS_2RX = 248, //4G RAS CC2 mode 1 (2RX) cnt |
| MDLPM_EL1_CC2_RAS_4RX = 249, //4G RAS CC2 mode 2 (4RX) cnt |
| MDLPM_EL1_CC3_RAS_1RX = 250, //4G RAS CC3 mode 0 (1RX) cnt |
| MDLPM_EL1_CC3_RAS_2RX = 251, //4G RAS CC3 mode 1 (2RX) cnt |
| MDLPM_EL1_CC3_RAS_4RX = 252, //4G RAS CC3 mode 2 (4RX) cnt |
| MDLPM_EL1_CC4_RAS_1RX = 253, //4G RAS CC4 mode 0 (1RX) cnt |
| MDLPM_EL1_CC4_RAS_2RX = 254, //4G RAS CC4 mode 1 (2RX) cnt |
| MDLPM_EL1_CC4_RAS_4RX = 255, //4G RAS CC4 mode 2 (4RX) cnt |
| /* 4G monitor data end */ |
| |
| /* 5G monitor data start */ |
| MDLPM_NL1_SLEEP_ACTIVE_DUR = 256, //5G acc sleep info. |
| MDLPM_NL1_SLEEP_STATUS = 257, //5G sleep status info. |
| MDLPM_NL1_MMW_SLEEP_ACTIVE_DUR = 258, //5G mmW acc sleep info. |
| MDLPM_NL1_MMW_SLEEP_STATUS = 259, //5G mmW sleep status info. |
| // RX/TX window related |
| MDLPM_NL1_RX_WINDOW_DUR = 260, //5G RX window acc. open duration |
| MDLPM_NL1_TX_WINDOW_DUR = 261, //5G TX window acc. open duration |
| MDLPM_NL1_CONNECT_DUR = 262, //5G connection duration |
| MDLPM_NL1_TX_POWER_TG0_CC0 = 263, //5G TX power info, 0=> below -5 , 1=>-5~1, 2=>1~5, 3=>5~10,4=>10~15,5=>15~20,6=>20~23,7=>23~26 |
| MDLPM_NL1_TX_POWER_TG1_CC0 = 264, //5G TX power info, 0=> below -5 , 1=>-5~1, 2=>1~5, 3=>5~10,4=>10~15,5=>15~20,6=>20~23,7=>23~26 |
| MDLPM_NL1_TX_POWER_TG2_CC0 = 265, //5G TX power info, 0=> below -5 , 1=>-5~1, 2=>1~5, 3=>5~10,4=>10~15,5=>15~20,6=>20~23,7=>23~26 |
| MDLPM_NL1_ARX_TG0_CC0 = 266, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS |
| MDLPM_NL1_ARX_TG1_CC0 = 267, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS |
| MDLPM_NL1_ARX_TG2_CC0 = 268, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS |
| MDLPM_NL1_ARX_TG0_CC1 = 269, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS |
| MDLPM_NL1_ARX_TG1_CC1 = 270, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS |
| MDLPM_NL1_ARX_TG2_CC1 = 271, //5G ARX info, 0=>HPM, 1=>DATA, 2=>LOW_MCS, 4=>H_MCS |
| MDLPM_NL1_ARX_TG0_CC0_CNT = 272, //5G ARX change counter info |
| MDLPM_NL1_ARX_TG1_CC0_CNT = 273, //5G ARX change counter info |
| MDLPM_NL1_ARX_TG2_CC0_CNT = 274, //5G ARX change counter info |
| MDLPM_NL1_ARX_TG0_CC1_CNT = 275, //5G ARX change counter info |
| MDLPM_NL1_ARX_TG1_CC1_CNT = 276, //5G ARX change counter info |
| MDLPM_NL1_ARX_TG2_CC1_CNT = 277, //5G ARX change counter info |
| MDLPM_NL1_RAS_TG0_CC0 = 278, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX |
| MDLPM_NL1_RAS_TG1_CC0 = 279, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX |
| MDLPM_NL1_RAS_TG2_CC0 = 280, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX |
| MDLPM_NL1_RAS_TG0_CC1 = 281, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX |
| MDLPM_NL1_RAS_TG1_CC1 = 282, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX |
| MDLPM_NL1_RAS_TG2_CC1 = 283, //5G RAS info, 1=>1RX, 2=>2RX, 4=>4RX |
| MDLPM_NL1_RAS_TG0_CC0_CNT = 284, //5G RAS change counter info |
| MDLPM_NL1_RAS_TG1_CC0_CNT = 285, //5G RAS change counter info |
| MDLPM_NL1_RAS_TG2_CC0_CNT = 286, //5G RAS change counter info |
| MDLPM_NL1_RAS_TG0_CC1_CNT = 287, //5G RAS change counter info |
| MDLPM_NL1_RAS_TG1_CC1_CNT = 288, //5G RAS change counter info |
| MDLPM_NL1_RAS_TG2_CC1_CNT = 289, //5G RAS change counter info |
| MDLPM_NL1_SLEEP_ACTIVE_DUR_TG0 = 290, //5G acc sleep info. |
| MDLPM_NL1_SLEEP_STATUS_TG0 = 291, //5G sleep status info. |
| MDLPM_NL1_SLEEP_ACTIVE_DUR_TG1 = 292, //5G acc sleep info. |
| MDLPM_NL1_SLEEP_STATUS_TG1 = 293, //5G sleep status info. |
| /* 5G monitor data end */ |
| MDLPM_MAX_ITEMS = 512 |
| } MDLPM_INDEX; |
| |
| #ifdef SMP |
| #undef SMP |
| #endif |
| |
| typedef enum |
| { |
| SMP = 0, |
| CORE0 = 0, |
| CORE1, |
| CORE2, |
| CORE3 |
| } SLPDRV_CORE_e; |
| |
| //#ifdef BIG_DAC_CHANGE_RECALIBRATION |
| |
| typedef enum |
| { |
| MODEM_TOPSM_INPUT_2G = 0, /* Input module is 2G */ |
| MODEM_TOPSM_INPUT_3G /* Input module is 3G */ |
| } MODEM_TOPSM_INPUT_MODULE; |
| |
| typedef enum |
| { |
| MODEM_TOPSM_RF1 = 0, |
| MODEM_TOPSM_RF2, |
| NUM_OF_CLOCK_SOURCE |
| } CLOCK_INPUT_SOURCE; |
| |
| //#endif |
| typedef enum{ |
| #if defined(__MD93__) |
| SLP_EMM_CORE0_SLP_SW_LOCK = 0, |
| SLP_EMM_CORE0_SLP_SW_EXT_LOCK, |
| SLP_EMM_CORE1_SLP_SW_LOCK, |
| SLP_EMM_CORE1_SLP_SW_EXT_LOCK, |
| SLP_EMM_CORE0_SLP_SW_LOCK_TIME, |
| SLP_EMM_CORE1_SLP_SW_LOCK_TIME, |
| SLP_EMM_CORE0_SLP_SW_UNLOCK_TIME, |
| SLP_EMM_CORE1_SLP_SW_UNLOCK_TIME, |
| SLP_EMM_SLP_INIFINITE_ENTER, |
| #elif defined(__MD95__) |
| SLP_EMM_CORE0_SLP_SW_LOCK = 0, |
| SLP_EMM_CORE0_SLP_SW_EXT_LOCK, |
| SLP_EMM_CORE1_SLP_SW_LOCK, |
| SLP_EMM_CORE1_SLP_SW_EXT_LOCK, |
| SLP_EMM_CORE2_SLP_SW_LOCK, |
| SLP_EMM_CORE2_SLP_SW_EXT_LOCK, |
| SLP_EMM_CORE0_SLP_SW_LOCK_TIME, |
| SLP_EMM_CORE1_SLP_SW_LOCK_TIME, |
| SLP_EMM_CORE2_SLP_SW_LOCK_TIME, |
| SLP_EMM_CORE0_SLP_SW_UNLOCK_TIME, |
| SLP_EMM_CORE1_SLP_SW_UNLOCK_TIME, |
| SLP_EMM_CORE2_SLP_SW_UNLOCK_TIME, |
| SLP_EMM_SLP_INIFINITE_ENTER, |
| #elif defined(__MD97__) || defined(__MD97P__) |
| SLP_EMM_CORE0_SLP_SW_LOCK = 0, |
| SLP_EMM_CORE0_SLP_SW_EXT_LOCK, |
| SLP_EMM_CORE1_SLP_SW_LOCK, |
| SLP_EMM_CORE1_SLP_SW_EXT_LOCK, |
| SLP_EMM_CORE2_SLP_SW_LOCK, |
| SLP_EMM_CORE2_SLP_SW_EXT_LOCK, |
| SLP_EMM_CORE3_SLP_SW_LOCK, |
| SLP_EMM_CORE3_SLP_SW_EXT_LOCK, |
| SLP_EMM_CORE0_SLP_SW_LOCK_TIME, |
| SLP_EMM_CORE1_SLP_SW_LOCK_TIME, |
| SLP_EMM_CORE2_SLP_SW_LOCK_TIME, |
| SLP_EMM_CORE3_SLP_SW_LOCK_TIME, |
| SLP_EMM_CORE0_SLP_SW_UNLOCK_TIME, |
| SLP_EMM_CORE1_SLP_SW_UNLOCK_TIME, |
| SLP_EMM_CORE2_SLP_SW_UNLOCK_TIME, |
| SLP_EMM_CORE3_SLP_SW_UNLOCK_TIME, |
| SLP_EMM_SLP_INIFINITE_ENTER, |
| #else |
| #error "no chip match" |
| #endif |
| }SLP_EMM_LOG_INDEX; |
| |
| void SleepDrv_LockSleep( SLEEP_CTL_USER user, kal_uint8 target_core); |
| void SleepDrv_UnlockSleep( SLEEP_CTL_USER user, kal_uint8 target_core); |
| |
| void Sleep_DrvLowPowerMonitorInit(void); |
| |
| void SleepDrv_LowPowerMonitorFlushCheck( void ); |
| void SleepDrv_LowPowerMonitorDelete(void); |
| void SleepDrv_LowPowerMonitorCreate(void); |
| void SleepDrv_LowPowerMonitorStart(void); |
| void SleepDrv_LowPowerMonitorStop(void); |
| kal_bool SleepDrv_LowPowerMonitorSetParameter(kal_uint32 data_len, kal_uint8 *data_str); |
| |
| void SleepDrv_UpdatePSSlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value); |
| void SleepDrv_UpdateL1SlpDbgShmFixBuf(SLP_DBG_SHM_FIX_REG_INDEX index, kal_uint32 value); |
| void SleepDrv_SlpDbgShmRingBufAdd(SLP_DBG_SHM_RING_BUFFER_INDEX index, kal_uint32 status, kal_uint32 dbg_info); |
| |
| extern kal_bool MD_TOPSM_StartLPM(kal_uint8 data_str0, kal_uint8 data_str1, kal_uint8 data_str2); |
| extern kal_bool MD_TOPSM_DumpLPM(void); |
| |
| |
| /* MDTOPSM Public API */ |
| extern kal_uint32 SleepDrv_GetWallClk(void); |
| extern kal_uint32 SleepDrv_GetWallClk_H(void); |
| extern void MD_TOPSM_EnableFRC(void); /* Enable FRC API for exception handling */ |
| extern kal_uint8 MD_TOPSM_SRCLK_SW_Control_GetHandle( kal_char* module_name ); /* Register the module as a SRCLK force on user */ |
| extern void MD_TOPSM_SRCLK_SW_Control( SRCLK_FORCEON_USER user, kal_bool fOn ); /* SW lock or unlock 26M */ |
| extern void MD_TOPSM_PLL_SW_Control(PS_PLL_FORCEON_USER USER,PS_TOPSM_PLL PLL, kal_bool fOn); |
| extern void MD_TOPSM_USIP_SW_Control(PS_USIP_FORCEON_USER USER, kal_bool fOn); |
| |
| #include "reg_base.h" |
| |
| |
| #define GET_TOPSM_FRC_VAL_R() (*(volatile kal_uint32 *)(BASE_ADDR_MDTOPSM+0x830)) |
| #define GET_TOPSM_FRC_SYNC_VAL_2G_US() |
| #define GET_TOPSM_FRC_SYNC_VAL_2G_26M() |
| #define GET_TOPSM_FRC_SYNC_VAL_3G_US() |
| #define GET_TOPSM_FRC_SYNC_VAL_3G_26M() |
| #define GET_TOPSM_FRC_SYNC_VAL_TDD_US() |
| #define GET_TOPSM_FRC_SYNC_VAL_TDD_26M() |
| #define SET_GPS_SYNC_TIME(_val) |
| |
| |
| |
| #ifdef BIG_DAC_CHANGE_RECALIBRATION |
| extern void MODEM_TOPSM_SetCurrentFreqOffset( kal_int32 freq_offset, MODEM_TOPSM_INPUT_MODULE module, CLOCK_INPUT_SOURCE clockSource ); |
| extern void MODEM_TOPSM_SetFreqOffsetBase( kal_int32 freq_offset, MODEM_TOPSM_INPUT_MODULE module, CLOCK_INPUT_SOURCE clockSource ); |
| #endif |
| |
| extern kal_uint32 MODEM_TOPSM_GetSSTA0(void); |
| extern kal_uint32 MODEM_TOPSM_GetSSTA1(void); |
| |
| extern kal_bool OSTD_Is3gEnabled (void); |
| |
| |
| #endif |