| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _CPH_1X_RXBRP_DMA_H_ |
| #define _CPH_1X_RXBRP_DMA_H_ |
| |
| |
| typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| |
| |
| #define RXBRP_C_1XRTT_DMA_REG_BASE (0x00000000) |
| |
| #define RXBRP_C_1XRTT_DMA_end (RXBRP_C_1XRTT_DMA_REG_BASE + 0x0010 + 1*4) |
| |
| |
| |
| #define DBRP_RTT_FCH_ET_PCG_CNT_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0000)) |
| #define DBRP_RTT_FCH_SCALE_PARAM_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0004)) |
| #define DBRP_RTT_FCH_SCALE_PARAM1_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0008)) |
| #define DBRP_RTT_SCH_SCALE_PARAM_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x000C)) |
| #define DBRP_RTT_SCH_SCALE_PARAM1_DMA ((APBADDR32)(RXBRP_C_1XRTT_DMA_REG_BASE + 0x0010)) |
| |
| |
| #define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_LSB (0) |
| #define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_WIDTH (4) |
| #define DBRP_RTT_FCH_ET_PCG_CNT_ET_PCG_CNT_MASK (0x0000000F) |
| |
| #define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0) |
| #define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (17) |
| #define DBRP_RTT_FCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x0001FFFF) |
| |
| #define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0) |
| #define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15) |
| #define DBRP_RTT_FCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF) |
| |
| #define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_LSB (0) |
| #define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_WIDTH (21) |
| #define DBRP_RTT_SCH_SCALE_PARAM_FRM_ABS_ACC_MASK (0x001FFFFF) |
| |
| #define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_LSB (0) |
| #define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_WIDTH (15) |
| #define DBRP_RTT_SCH_SCALE_PARAM1_VLD_DATA_NUM_MASK (0x00007FFF) |
| |
| |
| #endif //#ifndef _CPH_1X_RXBRP_DMA_H_ |