| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _CPH_1X_RXSLP_H_ |
| #define _CPH_1X_RXSLP_H_ |
| |
| |
| typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| |
| |
| #define ST1X_RX_SLP_REG_BASE (0x00000000) |
| |
| #define ST1X_RX_SLP_end (ST1X_RX_SLP_REG_BASE + 0xA60D0060 + 1*4) |
| |
| |
| |
| #define ST1X_SM_CON ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0000)) |
| #define ST1X_SM_PAUSE_TIME ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0004)) |
| #define ST1X_SM_STA ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0008)) |
| #define ST1X_SM_CFG ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D000C)) |
| #define ST1X_SM_START_TIME ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0010)) |
| #define ST1X_SM_SW_WAKE_CON ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0014)) |
| #define ST1X_SM_STEP_FRAC ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0018)) |
| #define ST1X_SM_SYSCNT_F32K_INT ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D001C)) |
| #define ST1X_SM_SYSCNT_F32K_FRAC ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0020)) |
| #define ST1X_SM_SUPFRM_F32K_L ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0024)) |
| #define ST1X_SM_SUPFRM_F32K_H ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0028)) |
| #define ST1X_SM_SLEEP_OFFSET ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D002C)) |
| #define ST1X_SM_TIME_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0030)) |
| #define ST1X_SM_SUPFRM_TIME_L_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0034)) |
| #define ST1X_SM_SUPFRM_TIME_H_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0038)) |
| #define ST1X_SM_TIME_SLTBD ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D003C)) |
| #define ST1X_SM_SUPFRM_TIME_L_SLTBD ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0040)) |
| #define ST1X_SM_SUPFRM_TIME_H_SLTBD ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0044)) |
| #define ST1X_SM_TIME_WAKEUP_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0048)) |
| #define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D004C)) |
| #define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0050)) |
| #define ST1X_SM_FINAL_PAUSE_DURATION ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0054)) |
| #define ST1X_SM_PRESLP_CNT ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0058)) |
| #define ST1X_SM_SLT_START_F32K ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D005C)) |
| #define ST1X_SM_WAKEUP_START_F32K ((APBADDR32)(ST1X_RX_SLP_REG_BASE + 0xA60D0060)) |
| |
| |
| #define ST1X_SM_CON_CLR_CNT_LSB (15) |
| #define ST1X_SM_CON_CLR_CNT_WIDTH (1) |
| #define ST1X_SM_CON_CLR_CNT_MASK (0x00008000) |
| #define ST1X_SM_CON_CLR_CNT_BIT (0x00008000) |
| |
| #define ST1X_SM_CON_PAUSE_START_LSB (1) |
| #define ST1X_SM_CON_PAUSE_START_WIDTH (1) |
| #define ST1X_SM_CON_PAUSE_START_MASK (0x00000002) |
| #define ST1X_SM_CON_PAUSE_START_BIT (0x00000002) |
| |
| #define ST1X_SM_CON_PAUSE_MODE_LSB (0) |
| #define ST1X_SM_CON_PAUSE_MODE_WIDTH (1) |
| #define ST1X_SM_CON_PAUSE_MODE_MASK (0x00000001) |
| #define ST1X_SM_CON_PAUSE_MODE_BIT (0x00000001) |
| |
| #define ST1X_SM_PAUSE_TIME_PAUSE_TIME_LSB (0) |
| #define ST1X_SM_PAUSE_TIME_PAUSE_TIME_WIDTH (32) |
| #define ST1X_SM_PAUSE_TIME_PAUSE_TIME_MASK (0xFFFFFFFF) |
| |
| #define ST1X_SM_STA_SLP_EXIT_CPL_LSB (7) |
| #define ST1X_SM_STA_SLP_EXIT_CPL_WIDTH (1) |
| #define ST1X_SM_STA_SLP_EXIT_CPL_MASK (0x00000080) |
| #define ST1X_SM_STA_SLP_EXIT_CPL_BIT (0x00000080) |
| |
| #define ST1X_SM_STA_PAUSE_CPL_LSB (6) |
| #define ST1X_SM_STA_PAUSE_CPL_WIDTH (1) |
| #define ST1X_SM_STA_PAUSE_CPL_MASK (0x00000040) |
| #define ST1X_SM_STA_PAUSE_CPL_BIT (0x00000040) |
| |
| #define ST1X_SM_CFG_SW_WAKE_EN_LSB (8) |
| #define ST1X_SM_CFG_SW_WAKE_EN_WIDTH (1) |
| #define ST1X_SM_CFG_SW_WAKE_EN_MASK (0x00000100) |
| #define ST1X_SM_CFG_SW_WAKE_EN_BIT (0x00000100) |
| |
| #define ST1X_SM_CFG_IRQ_EN_LSB (1) |
| #define ST1X_SM_CFG_IRQ_EN_WIDTH (1) |
| #define ST1X_SM_CFG_IRQ_EN_MASK (0x00000002) |
| #define ST1X_SM_CFG_IRQ_EN_BIT (0x00000002) |
| |
| #define ST1X_SM_START_TIME_SYSTEM_TIME_CNT_LSB (2) |
| #define ST1X_SM_START_TIME_SYSTEM_TIME_CNT_WIDTH (18) |
| #define ST1X_SM_START_TIME_SYSTEM_TIME_CNT_MASK (0x000FFFFC) |
| |
| #define ST1X_SM_SW_WAKE_CON_SW_EVENT_LSB (0) |
| #define ST1X_SM_SW_WAKE_CON_SW_EVENT_WIDTH (1) |
| #define ST1X_SM_SW_WAKE_CON_SW_EVENT_MASK (0x00000001) |
| #define ST1X_SM_SW_WAKE_CON_SW_EVENT_BIT (0x00000001) |
| |
| #define ST1X_SM_STEP_FRAC_STEP_INT_LSB (18) |
| #define ST1X_SM_STEP_FRAC_STEP_INT_WIDTH (9) |
| #define ST1X_SM_STEP_FRAC_STEP_INT_MASK (0x07FC0000) |
| |
| #define ST1X_SM_STEP_FRAC_STEP_FRAC_LSB (0) |
| #define ST1X_SM_STEP_FRAC_STEP_FRAC_WIDTH (18) |
| #define ST1X_SM_STEP_FRAC_STEP_FRAC_MASK (0x0003FFFF) |
| |
| #define ST1X_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_LSB (0) |
| #define ST1X_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_WIDTH (20) |
| #define ST1X_SM_SYSCNT_F32K_INT_SYSCNT_F32K_INT_MASK (0x000FFFFF) |
| |
| #define ST1X_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_LSB (0) |
| #define ST1X_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_WIDTH (18) |
| #define ST1X_SM_SYSCNT_F32K_FRAC_SYSCNT_F32K_FRAC_MASK (0x0003FFFF) |
| |
| #define ST1X_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_LSB (0) |
| #define ST1X_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_WIDTH (32) |
| #define ST1X_SM_SUPFRM_F32K_L_SUPFRM_CNT_F32K_MASK (0xFFFFFFFF) |
| |
| #define ST1X_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_LSB (0) |
| #define ST1X_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_WIDTH (4) |
| #define ST1X_SM_SUPFRM_F32K_H_SUPFRM_CNT_F32K_MASK (0x0000000F) |
| |
| #define ST1X_SM_SLEEP_OFFSET_CHIP_OFFSET_LSB (2) |
| #define ST1X_SM_SLEEP_OFFSET_CHIP_OFFSET_WIDTH (14) |
| #define ST1X_SM_SLEEP_OFFSET_CHIP_OFFSET_MASK (0x0000FFFC) |
| |
| #define ST1X_SM_TIME_START_SM_TIME_START_LSB (0) |
| #define ST1X_SM_TIME_START_SM_TIME_START_WIDTH (20) |
| #define ST1X_SM_TIME_START_SM_TIME_START_MASK (0x000FFFFF) |
| |
| #define ST1X_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_LSB (0) |
| #define ST1X_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_WIDTH (32) |
| #define ST1X_SM_SUPFRM_TIME_L_START_SM_SUPFRM_TIME_START_MASK (0xFFFFFFFF) |
| |
| #define ST1X_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_LSB (0) |
| #define ST1X_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_WIDTH (4) |
| #define ST1X_SM_SUPFRM_TIME_H_START_SM_SUPFRM_TIME_START_MASK (0x0000000F) |
| |
| #define ST1X_SM_TIME_SLTBD_SM_TIME_SLTBD_LSB (0) |
| #define ST1X_SM_TIME_SLTBD_SM_TIME_SLTBD_WIDTH (20) |
| #define ST1X_SM_TIME_SLTBD_SM_TIME_SLTBD_MASK (0x000FFFFF) |
| |
| #define ST1X_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0) |
| #define ST1X_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (32) |
| #define ST1X_SM_SUPFRM_TIME_L_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0xFFFFFFFF) |
| |
| #define ST1X_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_LSB (0) |
| #define ST1X_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_WIDTH (4) |
| #define ST1X_SM_SUPFRM_TIME_H_SLTBD_SM_SUPFRM_TIME_SLTBD_MASK (0x0000000F) |
| |
| #define ST1X_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_LSB (0) |
| #define ST1X_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_WIDTH (20) |
| #define ST1X_SM_TIME_WAKEUP_START_SM_TIME_WAKEUP_START_MASK (0x000FFFFF) |
| |
| #define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0) |
| #define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (32) |
| #define ST1X_SM_SUPFRM_TIME_L_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0xFFFFFFFF) |
| |
| #define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_LSB (0) |
| #define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_WIDTH (4) |
| #define ST1X_SM_SUPFRM_TIME_H_WAKEUP_START_SM_SUPFRM_WAKEUP_START_MASK (0x0000000F) |
| |
| #define ST1X_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_LSB (0) |
| #define ST1X_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_WIDTH (32) |
| #define ST1X_SM_FINAL_PAUSE_DURATION_FINAL_PAUSE_DURATION_MASK (0xFFFFFFFF) |
| |
| #define ST1X_SM_PRESLP_CNT_SM_PRESLP_CNT_LSB (0) |
| #define ST1X_SM_PRESLP_CNT_SM_PRESLP_CNT_WIDTH (6) |
| #define ST1X_SM_PRESLP_CNT_SM_PRESLP_CNT_MASK (0x0000003F) |
| |
| #define ST1X_SM_SLT_START_F32K_SM_SLT_START_F32K_LSB (0) |
| #define ST1X_SM_SLT_START_F32K_SM_SLT_START_F32K_WIDTH (6) |
| #define ST1X_SM_SLT_START_F32K_SM_SLT_START_F32K_MASK (0x0000003F) |
| |
| #define ST1X_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_LSB (0) |
| #define ST1X_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_WIDTH (32) |
| #define ST1X_SM_WAKEUP_START_F32K_SM_WAKEUP_START_F32K_MASK (0xFFFFFFFF) |
| |
| |
| #endif //#ifndef _CPH_1X_RXSLP_H_ |