| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _CPH_1X_TXBRP_H_ |
| #define _CPH_1X_TXBRP_H_ |
| |
| |
| typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| |
| |
| #if defined(__MD93__)||defined(__MD95__) |
| #define BRP_C2K_1XRTT_REG_BASE (0xa8020000) |
| #else |
| #define BRP_C2K_1XRTT_REG_BASE (0xa8820000) |
| #endif |
| #define BRP_C2K_1XRTT_end (BRP_C2K_1XRTT_REG_BASE + 0x03c8 + 1*4) |
| |
| |
| #define WORK_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0000)) |
| #define GLOBAL_IRQ ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0008)) |
| #define GLOBAL_IRQ_MASK ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x000c)) |
| #define GLOBAL_IRQ_CLR ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0010)) |
| #define RTT_IRQ ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0044)) |
| #define RTT_IRQ_MASK ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0048)) |
| #define RTT_IRQ_CLR ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x004c)) |
| #define TXBRP_SW_CKEN_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0050)) |
| #define TXBRP_CLK_CTRLSEL_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0054)) |
| #define DEBUG_REG_BANK_SEL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0058)) |
| #define MEM_TEST_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x005c)) |
| #define TRIGGER_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0060)) |
| #define DI_SWAP_EN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0064)) |
| #define DI_TEST_CFG ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0068)) |
| #define I_REG_ULTRA_PRE_EN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x006c)) |
| #define I_REG_BEGIN_ULTRA_CNT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0070)) |
| #define I_REG_ULTRA_WATER_MARK ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0074)) |
| #define DI_DEBUG ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0078)) |
| #define DEBUG_TRIG_SEL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x007c)) |
| #define ENC_FSM_STATE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0090)) |
| #define CRC_DBG_FLAG ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0094)) |
| #define INTLV_B_LWT_ST_0 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0098)) |
| #define INTLV_B_LWT_ST_1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x009c)) |
| #define UTXBRP_CTRL_FSM_STATE1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00a0)) |
| #define UTXBRP_CTRL_FSM_STATE2 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00a4)) |
| #define RM_FSM_STATE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00a8)) |
| #define RUMAP_FSM_STATE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00ac)) |
| #define UTXBRP_TEST_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00c4)) |
| #define CRP_SW_READ_CTRL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00c8)) |
| #define C2K_READ_RST ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00cc)) |
| #define RTT_START ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x00f0)) |
| #define TXA_INPUT_LEN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0110)) |
| #define TXA_PUNC ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0118)) |
| #define TXA_HA_MODE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x011c)) |
| #define TXA_INTRLV_PARM ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0120)) |
| #define TXA_FREP_L ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0124)) |
| #define CHL_TYPE ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0128)) |
| #define TXA_CRC ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x012c)) |
| #define TXA_FREP_LPML ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0130)) |
| #define TXA_FREP_MM1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0134)) |
| #define TXA_FREP_ACC0 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0138)) |
| #define TXA_PUNC_PAT0 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x013c)) |
| #define TXA_PUNC_PAT1 ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0140)) |
| #define TXA_FREP_LP ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0144)) |
| #define TXA_TST_CTRL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x0148)) |
| #define RTT_CHNL_BASE_ADDR ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x014c)) |
| #define TXBRP_DBG_CRC32_EN ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03bc)) |
| #define TXBRP_DBG_CRC32_RSLT_I_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03c0)) |
| #define TXBRP_DBG_CRC32_RSLT_Q_RTT ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03c4)) |
| #define DEBUG_CRC_SEL ((APBADDR32)(BRP_C2K_1XRTT_REG_BASE + 0x03c8)) |
| |
| |
| #define WORK_MODE_LSB (0) |
| #define WORK_MODE_WIDTH (5) |
| #define WORK_MODE_MASK (0x0000001F) |
| |
| #define GLOBAL_IRQ_DI_ERR_IRQ_LSB (3) |
| #define GLOBAL_IRQ_DI_ERR_IRQ_WIDTH (1) |
| #define GLOBAL_IRQ_DI_ERR_IRQ_MASK (0x00000008) |
| #define GLOBAL_IRQ_DI_ERR_IRQ_BIT (0x00000008) |
| |
| #define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_LSB (2) |
| #define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_WIDTH (1) |
| #define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_MASK (0x00000004) |
| #define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_BIT (0x00000004) |
| |
| #define GLOBAL_IRQ_MODE_SWITCH_IRQ_LSB (1) |
| #define GLOBAL_IRQ_MODE_SWITCH_IRQ_WIDTH (1) |
| #define GLOBAL_IRQ_MODE_SWITCH_IRQ_MASK (0x00000002) |
| #define GLOBAL_IRQ_MODE_SWITCH_IRQ_BIT (0x00000002) |
| |
| #define GLOBAL_IRQ_MODE_IRQ_LSB (0) |
| #define GLOBAL_IRQ_MODE_IRQ_WIDTH (1) |
| #define GLOBAL_IRQ_MODE_IRQ_MASK (0x00000001) |
| #define GLOBAL_IRQ_MODE_IRQ_BIT (0x00000001) |
| |
| #define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_LSB (3) |
| #define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_WIDTH (1) |
| #define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_MASK (0x00000008) |
| #define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_BIT (0x00000008) |
| |
| #define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_LSB (2) |
| #define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_WIDTH (1) |
| #define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_MASK (0x00000004) |
| #define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_BIT (0x00000004) |
| |
| #define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_LSB (1) |
| #define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_WIDTH (1) |
| #define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_MASK (0x00000002) |
| #define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_BIT (0x00000002) |
| |
| #define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_LSB (0) |
| #define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_WIDTH (1) |
| #define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_MASK (0x00000001) |
| #define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_BIT (0x00000001) |
| |
| #define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_LSB (3) |
| #define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_WIDTH (1) |
| #define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_MASK (0x00000008) |
| #define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_BIT (0x00000008) |
| |
| #define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_LSB (2) |
| #define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_WIDTH (1) |
| #define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_MASK (0x00000004) |
| #define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_BIT (0x00000004) |
| |
| #define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_LSB (1) |
| #define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_WIDTH (1) |
| #define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_MASK (0x00000002) |
| #define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_BIT (0x00000002) |
| |
| #define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_LSB (0) |
| #define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_WIDTH (1) |
| #define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_MASK (0x00000001) |
| #define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_BIT (0x00000001) |
| |
| #define RTT_IRQ_RTT_TRIG_ERR_LSB (3) |
| #define RTT_IRQ_RTT_TRIG_ERR_WIDTH (1) |
| #define RTT_IRQ_RTT_TRIG_ERR_MASK (0x00000008) |
| #define RTT_IRQ_RTT_TRIG_ERR_BIT (0x00000008) |
| |
| #define RTT_IRQ_RTT_CHNL1_RD_ERR_LSB (2) |
| #define RTT_IRQ_RTT_CHNL1_RD_ERR_WIDTH (1) |
| #define RTT_IRQ_RTT_CHNL1_RD_ERR_MASK (0x00000004) |
| #define RTT_IRQ_RTT_CHNL1_RD_ERR_BIT (0x00000004) |
| |
| #define RTT_IRQ_RTT_CHNL0_RD_ERR_LSB (1) |
| #define RTT_IRQ_RTT_CHNL0_RD_ERR_WIDTH (1) |
| #define RTT_IRQ_RTT_CHNL0_RD_ERR_MASK (0x00000002) |
| #define RTT_IRQ_RTT_CHNL0_RD_ERR_BIT (0x00000002) |
| |
| #define RTT_IRQ_RTT_DONE_LSB (0) |
| #define RTT_IRQ_RTT_DONE_WIDTH (1) |
| #define RTT_IRQ_RTT_DONE_MASK (0x00000001) |
| #define RTT_IRQ_RTT_DONE_BIT (0x00000001) |
| |
| #define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_LSB (3) |
| #define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_WIDTH (1) |
| #define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_MASK (0x00000008) |
| #define RTT_IRQ_MASK_RTT_TRIG_ERR_MASK_BIT (0x00000008) |
| |
| #define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_LSB (2) |
| #define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_WIDTH (1) |
| #define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_MASK (0x00000004) |
| #define RTT_IRQ_MASK_RTT_CHNL1_RD_ERR_MASK_BIT (0x00000004) |
| |
| #define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_LSB (1) |
| #define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_WIDTH (1) |
| #define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_MASK (0x00000002) |
| #define RTT_IRQ_MASK_RTT_CHNL0_RD_ERR_MASK_BIT (0x00000002) |
| |
| #define RTT_IRQ_MASK_RTT_DONE_MASK_LSB (0) |
| #define RTT_IRQ_MASK_RTT_DONE_MASK_WIDTH (1) |
| #define RTT_IRQ_MASK_RTT_DONE_MASK_MASK (0x00000001) |
| #define RTT_IRQ_MASK_RTT_DONE_MASK_BIT (0x00000001) |
| |
| #define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_LSB (3) |
| #define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_WIDTH (1) |
| #define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_MASK (0x00000008) |
| #define RTT_IRQ_CLR_RTT_TRIG_ERR_CLR_BIT (0x00000008) |
| |
| #define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_LSB (2) |
| #define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_WIDTH (1) |
| #define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_MASK (0x00000004) |
| #define RTT_IRQ_CLR_RTT_CHNL1_RD_ERR_CLR_BIT (0x00000004) |
| |
| #define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_LSB (1) |
| #define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_WIDTH (1) |
| #define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_MASK (0x00000002) |
| #define RTT_IRQ_CLR_RTT_CHNL0_RD_ERR_CLR_BIT (0x00000002) |
| |
| #define RTT_IRQ_CLR_RTT_DONE_CLR_LSB (0) |
| #define RTT_IRQ_CLR_RTT_DONE_CLR_WIDTH (1) |
| #define RTT_IRQ_CLR_RTT_DONE_CLR_MASK (0x00000001) |
| #define RTT_IRQ_CLR_RTT_DONE_CLR_BIT (0x00000001) |
| |
| #define TXBRP_SW_CKEN_TX3G_SW_CKEN_LSB (12) |
| #define TXBRP_SW_CKEN_TX3G_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_TX3G_SW_CKEN_MASK (0x00001000) |
| #define TXBRP_SW_CKEN_TX3G_SW_CKEN_BIT (0x00001000) |
| |
| #define TXBRP_SW_CKEN_TXSRP_SW_CKEN_LSB (11) |
| #define TXBRP_SW_CKEN_TXSRP_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_TXSRP_SW_CKEN_MASK (0x00000800) |
| #define TXBRP_SW_CKEN_TXSRP_SW_CKEN_BIT (0x00000800) |
| |
| #define TXBRP_SW_CKEN_APB_SW_CKEN_LSB (10) |
| #define TXBRP_SW_CKEN_APB_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_APB_SW_CKEN_MASK (0x00000400) |
| #define TXBRP_SW_CKEN_APB_SW_CKEN_BIT (0x00000400) |
| |
| #define TXBRP_SW_CKEN_OB_SW_CKEN_LSB (9) |
| #define TXBRP_SW_CKEN_OB_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_OB_SW_CKEN_MASK (0x00000200) |
| #define TXBRP_SW_CKEN_OB_SW_CKEN_BIT (0x00000200) |
| |
| #define TXBRP_SW_CKEN_RUMAP_SW_CKEN_LSB (8) |
| #define TXBRP_SW_CKEN_RUMAP_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_RUMAP_SW_CKEN_MASK (0x00000100) |
| #define TXBRP_SW_CKEN_RUMAP_SW_CKEN_BIT (0x00000100) |
| |
| #define TXBRP_SW_CKEN_INTL2_SW_CKEN_LSB (7) |
| #define TXBRP_SW_CKEN_INTL2_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_INTL2_SW_CKEN_MASK (0x00000080) |
| #define TXBRP_SW_CKEN_INTL2_SW_CKEN_BIT (0x00000080) |
| |
| #define TXBRP_SW_CKEN_INTL1_SW_CKEN_LSB (6) |
| #define TXBRP_SW_CKEN_INTL1_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_INTL1_SW_CKEN_MASK (0x00000040) |
| #define TXBRP_SW_CKEN_INTL1_SW_CKEN_BIT (0x00000040) |
| |
| #define TXBRP_SW_CKEN_SCR_SW_CKEN_LSB (5) |
| #define TXBRP_SW_CKEN_SCR_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_SCR_SW_CKEN_MASK (0x00000020) |
| #define TXBRP_SW_CKEN_SCR_SW_CKEN_BIT (0x00000020) |
| |
| #define TXBRP_SW_CKEN_RM_SW_CKEN_LSB (4) |
| #define TXBRP_SW_CKEN_RM_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_RM_SW_CKEN_MASK (0x00000010) |
| #define TXBRP_SW_CKEN_RM_SW_CKEN_BIT (0x00000010) |
| |
| #define TXBRP_SW_CKEN_ENC_SW_CKEN_LSB (3) |
| #define TXBRP_SW_CKEN_ENC_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_ENC_SW_CKEN_MASK (0x00000008) |
| #define TXBRP_SW_CKEN_ENC_SW_CKEN_BIT (0x00000008) |
| |
| #define TXBRP_SW_CKEN_CRC_SW_CKEN_LSB (2) |
| #define TXBRP_SW_CKEN_CRC_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_CRC_SW_CKEN_MASK (0x00000004) |
| #define TXBRP_SW_CKEN_CRC_SW_CKEN_BIT (0x00000004) |
| |
| #define TXBRP_SW_CKEN_DI_SW_CKEN_LSB (1) |
| #define TXBRP_SW_CKEN_DI_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_DI_SW_CKEN_MASK (0x00000002) |
| #define TXBRP_SW_CKEN_DI_SW_CKEN_BIT (0x00000002) |
| |
| #define TXBRP_SW_CKEN_TXBRP_SW_CKEN_LSB (0) |
| #define TXBRP_SW_CKEN_TXBRP_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_TXBRP_SW_CKEN_MASK (0x00000001) |
| #define TXBRP_SW_CKEN_TXBRP_SW_CKEN_BIT (0x00000001) |
| |
| #define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_LSB (12) |
| #define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_MASK (0x00001000) |
| #define TXBRP_CLK_CTRLSEL_TX3G_CLK_CTRLSEL_BIT (0x00001000) |
| |
| #define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_LSB (11) |
| #define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_MASK (0x00000800) |
| #define TXBRP_CLK_CTRLSEL_TXSRP_CLK_CTRLSEL_BIT (0x00000800) |
| |
| #define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_LSB (10) |
| #define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_MASK (0x00000400) |
| #define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_BIT (0x00000400) |
| |
| #define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_LSB (9) |
| #define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_MASK (0x00000200) |
| #define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_BIT (0x00000200) |
| |
| #define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_LSB (8) |
| #define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_MASK (0x00000100) |
| #define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_BIT (0x00000100) |
| |
| #define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_LSB (7) |
| #define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_MASK (0x00000080) |
| #define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_BIT (0x00000080) |
| |
| #define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_LSB (6) |
| #define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_MASK (0x00000040) |
| #define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_BIT (0x00000040) |
| |
| #define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_LSB (5) |
| #define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_MASK (0x00000020) |
| #define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_BIT (0x00000020) |
| |
| #define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_LSB (4) |
| #define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_MASK (0x00000010) |
| #define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_BIT (0x00000010) |
| |
| #define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_LSB (3) |
| #define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_MASK (0x00000008) |
| #define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_BIT (0x00000008) |
| |
| #define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_LSB (2) |
| #define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_MASK (0x00000004) |
| #define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_BIT (0x00000004) |
| |
| #define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_LSB (1) |
| #define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_MASK (0x00000002) |
| #define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_BIT (0x00000002) |
| |
| #define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_LSB (0) |
| #define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_MASK (0x00000001) |
| #define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_BIT (0x00000001) |
| |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_LSB (24) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_WIDTH (8) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_MASK (0xFF000000) |
| |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_LSB (16) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_WIDTH (8) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_MASK (0x00FF0000) |
| |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_LSB (8) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_WIDTH (8) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_MASK (0x0000FF00) |
| |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_LSB (0) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_WIDTH (8) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_MASK (0x000000FF) |
| |
| #define MEM_TEST_MODE_CRP_WR_MEM_EN_LSB (1) |
| #define MEM_TEST_MODE_CRP_WR_MEM_EN_WIDTH (1) |
| #define MEM_TEST_MODE_CRP_WR_MEM_EN_MASK (0x00000002) |
| #define MEM_TEST_MODE_CRP_WR_MEM_EN_BIT (0x00000002) |
| |
| #define MEM_TEST_MODE_MEM_TEST_MODE_LSB (0) |
| #define MEM_TEST_MODE_MEM_TEST_MODE_WIDTH (1) |
| #define MEM_TEST_MODE_MEM_TEST_MODE_MASK (0x00000001) |
| #define MEM_TEST_MODE_MEM_TEST_MODE_BIT (0x00000001) |
| |
| #define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_LSB (1) |
| #define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_WIDTH (1) |
| #define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_MASK (0x00000002) |
| #define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_BIT (0x00000002) |
| |
| #define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_LSB (0) |
| #define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_WIDTH (1) |
| #define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_MASK (0x00000001) |
| #define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_BIT (0x00000001) |
| |
| #define DI_SWAP_EN_LSB (0) |
| #define DI_SWAP_EN_WIDTH (3) |
| #define DI_SWAP_EN_MASK (0x00000007) |
| |
| #define DI_TEST_CFG_DI_TEST_MODE_EN_LSB (10) |
| #define DI_TEST_CFG_DI_TEST_MODE_EN_WIDTH (1) |
| #define DI_TEST_CFG_DI_TEST_MODE_EN_MASK (0x00000400) |
| #define DI_TEST_CFG_DI_TEST_MODE_EN_BIT (0x00000400) |
| |
| #define DI_TEST_CFG_DI_TEST_DATA_SEL_LSB (8) |
| #define DI_TEST_CFG_DI_TEST_DATA_SEL_WIDTH (2) |
| #define DI_TEST_CFG_DI_TEST_DATA_SEL_MASK (0x00000300) |
| |
| #define DI_TEST_CFG_DI_TEST_RAND_SEED_LSB (0) |
| #define DI_TEST_CFG_DI_TEST_RAND_SEED_WIDTH (8) |
| #define DI_TEST_CFG_DI_TEST_RAND_SEED_MASK (0x000000FF) |
| |
| #define I_REG_ULTRA_PRE_EN_LSB (0) |
| #define I_REG_ULTRA_PRE_EN_WIDTH (1) |
| #define I_REG_ULTRA_PRE_EN_MASK (0x00000001) |
| #define I_REG_ULTRA_PRE_EN_BIT (0x00000001) |
| |
| #define I_REG_BEGIN_ULTRA_CNT_LSB (0) |
| #define I_REG_BEGIN_ULTRA_CNT_WIDTH (3) |
| #define I_REG_BEGIN_ULTRA_CNT_MASK (0x00000007) |
| |
| #define I_REG_ULTRA_WATER_MARK_LSB (0) |
| #define I_REG_ULTRA_WATER_MARK_WIDTH (3) |
| #define I_REG_ULTRA_WATER_MARK_MASK (0x00000007) |
| |
| #define DI_DEBUG_DMA0_STATE_LSB (20) |
| #define DI_DEBUG_DMA0_STATE_WIDTH (2) |
| #define DI_DEBUG_DMA0_STATE_MASK (0x00300000) |
| |
| #define DI_DEBUG_RAM_RD_STATE_LSB (16) |
| #define DI_DEBUG_RAM_RD_STATE_WIDTH (2) |
| #define DI_DEBUG_RAM_RD_STATE_MASK (0x00030000) |
| |
| #define DI_DEBUG_O_DMA0_UTR_LSB (13) |
| #define DI_DEBUG_O_DMA0_UTR_WIDTH (1) |
| #define DI_DEBUG_O_DMA0_UTR_MASK (0x00002000) |
| #define DI_DEBUG_O_DMA0_UTR_BIT (0x00002000) |
| |
| #define DI_DEBUG_O_DMA0_PTR_UTR_LSB (12) |
| #define DI_DEBUG_O_DMA0_PTR_UTR_WIDTH (1) |
| #define DI_DEBUG_O_DMA0_PTR_UTR_MASK (0x00001000) |
| #define DI_DEBUG_O_DMA0_PTR_UTR_BIT (0x00001000) |
| |
| #define DI_DEBUG_O_DMA0_RD_REQ_LSB (10) |
| #define DI_DEBUG_O_DMA0_RD_REQ_WIDTH (1) |
| #define DI_DEBUG_O_DMA0_RD_REQ_MASK (0x00000400) |
| #define DI_DEBUG_O_DMA0_RD_REQ_BIT (0x00000400) |
| |
| #define DI_DEBUG_DMA_ALL_RDATA_DONE_LSB (9) |
| #define DI_DEBUG_DMA_ALL_RDATA_DONE_WIDTH (1) |
| #define DI_DEBUG_DMA_ALL_RDATA_DONE_MASK (0x00000200) |
| #define DI_DEBUG_DMA_ALL_RDATA_DONE_BIT (0x00000200) |
| |
| #define DI_DEBUG_RAM_FULL_LSB (8) |
| #define DI_DEBUG_RAM_FULL_WIDTH (1) |
| #define DI_DEBUG_RAM_FULL_MASK (0x00000100) |
| #define DI_DEBUG_RAM_FULL_BIT (0x00000100) |
| |
| #define DI_DEBUG_CHECK_DONE_LSB (7) |
| #define DI_DEBUG_CHECK_DONE_WIDTH (1) |
| #define DI_DEBUG_CHECK_DONE_MASK (0x00000080) |
| #define DI_DEBUG_CHECK_DONE_BIT (0x00000080) |
| |
| #define DI_DEBUG_DI_OUT_BIT_FINISH_LSB (6) |
| #define DI_DEBUG_DI_OUT_BIT_FINISH_WIDTH (1) |
| #define DI_DEBUG_DI_OUT_BIT_FINISH_MASK (0x00000040) |
| #define DI_DEBUG_DI_OUT_BIT_FINISH_BIT (0x00000040) |
| |
| #define DI_DEBUG_RAM_ALL_RDATA_READ_LSB (5) |
| #define DI_DEBUG_RAM_ALL_RDATA_READ_WIDTH (1) |
| #define DI_DEBUG_RAM_ALL_RDATA_READ_MASK (0x00000020) |
| #define DI_DEBUG_RAM_ALL_RDATA_READ_BIT (0x00000020) |
| |
| #define DI_DEBUG_DI_BUSY_LSB (4) |
| #define DI_DEBUG_DI_BUSY_WIDTH (1) |
| #define DI_DEBUG_DI_BUSY_MASK (0x00000010) |
| #define DI_DEBUG_DI_BUSY_BIT (0x00000010) |
| |
| #define DI_DEBUG_CRC_BUF_PING_EMPTY_LSB (3) |
| #define DI_DEBUG_CRC_BUF_PING_EMPTY_WIDTH (1) |
| #define DI_DEBUG_CRC_BUF_PING_EMPTY_MASK (0x00000008) |
| #define DI_DEBUG_CRC_BUF_PING_EMPTY_BIT (0x00000008) |
| |
| #define DI_DEBUG_CTC_BUF_PONG_EMPTY_LSB (2) |
| #define DI_DEBUG_CTC_BUF_PONG_EMPTY_WIDTH (1) |
| #define DI_DEBUG_CTC_BUF_PONG_EMPTY_MASK (0x00000004) |
| #define DI_DEBUG_CTC_BUF_PONG_EMPTY_BIT (0x00000004) |
| |
| #define DI_DEBUG_CRC_BUF_LOAD_SEL_LSB (1) |
| #define DI_DEBUG_CRC_BUF_LOAD_SEL_WIDTH (1) |
| #define DI_DEBUG_CRC_BUF_LOAD_SEL_MASK (0x00000002) |
| #define DI_DEBUG_CRC_BUF_LOAD_SEL_BIT (0x00000002) |
| |
| #define DI_DEBUG_CRC_BUF_OUT_SEL_LSB (0) |
| #define DI_DEBUG_CRC_BUF_OUT_SEL_WIDTH (1) |
| #define DI_DEBUG_CRC_BUF_OUT_SEL_MASK (0x00000001) |
| #define DI_DEBUG_CRC_BUF_OUT_SEL_BIT (0x00000001) |
| |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_LSB (8) |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_WIDTH (8) |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_MASK (0x0000FF00) |
| |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_LSB (0) |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_WIDTH (8) |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_MASK (0x000000FF) |
| |
| #define ENC_FSM_STATE_WT_CONV_STATE_LSB (17) |
| #define ENC_FSM_STATE_WT_CONV_STATE_WIDTH (3) |
| #define ENC_FSM_STATE_WT_CONV_STATE_MASK (0x000E0000) |
| |
| #define ENC_FSM_STATE_LTE_STATE_LSB (13) |
| #define ENC_FSM_STATE_LTE_STATE_WIDTH (4) |
| #define ENC_FSM_STATE_LTE_STATE_MASK (0x0001E000) |
| |
| #define ENC_FSM_STATE_CODEC_DIS_STATE_LSB (10) |
| #define ENC_FSM_STATE_CODEC_DIS_STATE_WIDTH (3) |
| #define ENC_FSM_STATE_CODEC_DIS_STATE_MASK (0x00001C00) |
| |
| #define ENC_FSM_STATE_CODEC_EN_STATE_LSB (6) |
| #define ENC_FSM_STATE_CODEC_EN_STATE_WIDTH (4) |
| #define ENC_FSM_STATE_CODEC_EN_STATE_MASK (0x000003C0) |
| |
| #define ENC_FSM_STATE_CODEC_W_STATE_LSB (3) |
| #define ENC_FSM_STATE_CODEC_W_STATE_WIDTH (3) |
| #define ENC_FSM_STATE_CODEC_W_STATE_MASK (0x00000038) |
| |
| #define ENC_FSM_STATE_CODEC_STATE_LSB (0) |
| #define ENC_FSM_STATE_CODEC_STATE_WIDTH (3) |
| #define ENC_FSM_STATE_CODEC_STATE_MASK (0x00000007) |
| |
| #define CRC_DBG_FLAG_CRC_LEN_DBG_LSB (26) |
| #define CRC_DBG_FLAG_CRC_LEN_DBG_WIDTH (5) |
| #define CRC_DBG_FLAG_CRC_LEN_DBG_MASK (0x7C000000) |
| |
| #define CRC_DBG_FLAG_RTT_RC_IDX_DBG_LSB (25) |
| #define CRC_DBG_FLAG_RTT_RC_IDX_DBG_WIDTH (1) |
| #define CRC_DBG_FLAG_RTT_RC_IDX_DBG_MASK (0x02000000) |
| #define CRC_DBG_FLAG_RTT_RC_IDX_DBG_BIT (0x02000000) |
| |
| #define CRC_DBG_FLAG_CQI_OR_DATA_DBG_LSB (24) |
| #define CRC_DBG_FLAG_CQI_OR_DATA_DBG_WIDTH (1) |
| #define CRC_DBG_FLAG_CQI_OR_DATA_DBG_MASK (0x01000000) |
| #define CRC_DBG_FLAG_CQI_OR_DATA_DBG_BIT (0x01000000) |
| |
| #define CRC_DBG_FLAG_CRC_STATE_DBG_LSB (16) |
| #define CRC_DBG_FLAG_CRC_STATE_DBG_WIDTH (6) |
| #define CRC_DBG_FLAG_CRC_STATE_DBG_MASK (0x003F0000) |
| |
| #define CRC_DBG_FLAG_BIT_CNT_DBG_LSB (0) |
| #define CRC_DBG_FLAG_BIT_CNT_DBG_WIDTH (15) |
| #define CRC_DBG_FLAG_BIT_CNT_DBG_MASK (0x00007FFF) |
| |
| #define INTLV_B_LWT_ST_0_LTE_WEN_ST_LSB (15) |
| #define INTLV_B_LWT_ST_0_LTE_WEN_ST_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_LTE_WEN_ST_MASK (0x00038000) |
| |
| #define INTLV_B_LWT_ST_0_TS_W_STATE_LSB (12) |
| #define INTLV_B_LWT_ST_0_TS_W_STATE_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_TS_W_STATE_MASK (0x00007000) |
| |
| #define INTLV_B_LWT_ST_0_TS_R_STATE_LSB (9) |
| #define INTLV_B_LWT_ST_0_TS_R_STATE_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_TS_R_STATE_MASK (0x00000E00) |
| |
| #define INTLV_B_LWT_ST_0_PP_W_STATE_UPA_LSB (6) |
| #define INTLV_B_LWT_ST_0_PP_W_STATE_UPA_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_PP_W_STATE_UPA_MASK (0x000001C0) |
| |
| #define INTLV_B_LWT_ST_0_PP_W_STATE_DCH_LSB (3) |
| #define INTLV_B_LWT_ST_0_PP_W_STATE_DCH_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_PP_W_STATE_DCH_MASK (0x00000038) |
| |
| #define INTLV_B_LWT_ST_0_SEC_INTLV_STATE_LSB (0) |
| #define INTLV_B_LWT_ST_0_SEC_INTLV_STATE_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_SEC_INTLV_STATE_MASK (0x00000007) |
| |
| #define INTLV_B_LWT_ST_1_CLM_CNT_LSB (25) |
| #define INTLV_B_LWT_ST_1_CLM_CNT_WIDTH (5) |
| #define INTLV_B_LWT_ST_1_CLM_CNT_MASK (0x3E000000) |
| |
| #define INTLV_B_LWT_ST_1_ROW_CNT_LSB (22) |
| #define INTLV_B_LWT_ST_1_ROW_CNT_WIDTH (3) |
| #define INTLV_B_LWT_ST_1_ROW_CNT_MASK (0x01C00000) |
| |
| #define INTLV_B_LWT_ST_1_BLK_CNT_LSB (14) |
| #define INTLV_B_LWT_ST_1_BLK_CNT_WIDTH (8) |
| #define INTLV_B_LWT_ST_1_BLK_CNT_MASK (0x003FC000) |
| |
| #define INTLV_B_LWT_ST_1_SEC_REQO_LSB (13) |
| #define INTLV_B_LWT_ST_1_SEC_REQO_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_SEC_REQO_MASK (0x00002000) |
| #define INTLV_B_LWT_ST_1_SEC_REQO_BIT (0x00002000) |
| |
| #define INTLV_B_LWT_ST_1_PPR_REQ_UPA_LSB (9) |
| #define INTLV_B_LWT_ST_1_PPR_REQ_UPA_WIDTH (4) |
| #define INTLV_B_LWT_ST_1_PPR_REQ_UPA__MASK (0x00001E00) |
| |
| #define INTLV_B_LWT_ST_1_PPR_READ_DONE_UPA_LSB (5) |
| #define INTLV_B_LWT_ST_1_PPR_READ_DONE_UPA_WIDTH (4) |
| #define INTLV_B_LWT_ST_1_PPR_READ_DONE_UPA_MASK (0x000001E0) |
| |
| #define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_LSB (4) |
| #define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_MASK (0x00000010) |
| #define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_UPA_BIT (0x00000010) |
| |
| #define INTLV_B_LWT_ST_1_PPR_REQ_DCH_LSB (3) |
| #define INTLV_B_LWT_ST_1_PPR_REQ_DCH_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_PPR_REQ_DCH_MASK (0x00000008) |
| #define INTLV_B_LWT_ST_1_PPR_REQ_DCH_BIT (0x00000008) |
| |
| #define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_LSB (2) |
| #define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_MASK (0x00000004) |
| #define INTLV_B_LWT_ST_1_PPR_READ_DONE_DCH_BIT (0x00000004) |
| |
| #define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_LSB (1) |
| #define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_MASK (0x00000002) |
| #define INTLV_B_LWT_ST_1_SECOND_INTLV_DONE_DCH_BIT (0x00000002) |
| |
| #define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_LSB (0) |
| #define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_MASK (0x00000001) |
| #define INTLV_B_LWT_ST_1_DCH_EDCH_MODE_BIT (0x00000001) |
| |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_LSB (20) |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_WIDTH (6) |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_MASK (0x03F00000) |
| |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_LSB (0) |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_WIDTH (20) |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_MASK (0x000FFFFF) |
| |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_LSB (16) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_WIDTH (4) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_MASK (0x000F0000) |
| |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_LSB (7) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_WIDTH (9) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_MASK (0x0000FF80) |
| |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_LSB (0) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_WIDTH (7) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_MASK (0x0000007F) |
| |
| #define RM_FSM_STATE_BIT_SEP_STATE_LSB (16) |
| #define RM_FSM_STATE_BIT_SEP_STATE_WIDTH (3) |
| #define RM_FSM_STATE_BIT_SEP_STATE_MASK (0x00070000) |
| |
| #define RM_FSM_STATE_BC_STATE_LSB (0) |
| #define RM_FSM_STATE_BC_STATE_WIDTH (16) |
| #define RM_FSM_STATE_BC_STATE_MASK (0x0000FFFF) |
| |
| #define RUMAP_FSM_STATE_BUF_STATE_LSB (5) |
| #define RUMAP_FSM_STATE_BUF_STATE_WIDTH (1) |
| #define RUMAP_FSM_STATE_BUF_STATE_MASK (0x00000020) |
| #define RUMAP_FSM_STATE_BUF_STATE_BIT (0x00000020) |
| |
| #define RUMAP_FSM_STATE_RU_MAP_STATE_LSB (0) |
| #define RUMAP_FSM_STATE_RU_MAP_STATE_WIDTH (5) |
| #define RUMAP_FSM_STATE_RU_MAP_STATE_MASK (0x0000001F) |
| |
| #define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_LSB (1) |
| #define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_WIDTH (1) |
| #define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_MASK (0x00000002) |
| #define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_BIT (0x00000002) |
| |
| #define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_LSB (0) |
| #define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_WIDTH (1) |
| #define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_MASK (0x00000001) |
| #define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_BIT (0x00000001) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_LSB (13) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_WIDTH (2) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_MASK (0x00006000) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_LSB (11) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_WIDTH (2) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_MASK (0x00001800) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_LSB (9) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_WIDTH (2) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_MASK (0x00000600) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_LSB (7) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_WIDTH (2) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_MASK (0x00000180) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_LSB (5) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_WIDTH (2) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_MASK (0x00000060) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_LSB (4) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_WIDTH (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_MASK (0x00000010) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_BIT (0x00000010) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_LSB (3) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_WIDTH (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_MASK (0x00000008) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_BIT (0x00000008) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_LSB (2) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_WIDTH (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_MASK (0x00000004) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_BIT (0x00000004) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_LSB (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_WIDTH (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_MASK (0x00000002) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_BIT (0x00000002) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_LSB (0) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_WIDTH (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_MASK (0x00000001) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_BIT (0x00000001) |
| |
| #define C2K_READ_RST_LSB (0) |
| #define C2K_READ_RST_WIDTH (1) |
| #define C2K_READ_RST_MASK (0x00000001) |
| #define C2K_READ_RST_BIT (0x00000001) |
| |
| #define RTT_START_LSB (0) |
| #define RTT_START_WIDTH (1) |
| #define RTT_START_MASK (0x00000001) |
| #define RTT_START_BIT (0x00000001) |
| |
| #define TXA_INPUT_LEN_LSB (0) |
| #define TXA_INPUT_LEN_WIDTH (13) |
| #define TXA_INPUT_LEN_MASK (0x00001FFF) |
| |
| #define TXA_PUNC_LSB (0) |
| #define TXA_PUNC_WIDTH (5) |
| #define TXA_PUNC_MASK (0x0000001F) |
| |
| #define TXA_HA_MODE_TX_SUP_CH_REP_LSB (10) |
| #define TXA_HA_MODE_TX_SUP_CH_REP_WIDTH (3) |
| #define TXA_HA_MODE_TX_SUP_CH_REP_MASK (0x00001C00) |
| |
| #define TXA_HA_MODE_TX_CLK_EN_LSB (9) |
| #define TXA_HA_MODE_TX_CLK_EN_WIDTH (1) |
| #define TXA_HA_MODE_TX_CLK_EN_MASK (0x00000200) |
| #define TXA_HA_MODE_TX_CLK_EN_BIT (0x00000200) |
| |
| #define TXA_HA_MODE_TURBO_TEST_LSB (8) |
| #define TXA_HA_MODE_TURBO_TEST_WIDTH (1) |
| #define TXA_HA_MODE_TURBO_TEST_MASK (0x00000100) |
| #define TXA_HA_MODE_TURBO_TEST_BIT (0x00000100) |
| |
| #define TXA_HA_MODE_INTRLV_RATE_LSB (6) |
| #define TXA_HA_MODE_INTRLV_RATE_WIDTH (2) |
| #define TXA_HA_MODE_INTRLV_RATE_MASK (0x000000C0) |
| |
| #define TXA_HA_MODE_INTRLV_TYPE_LSB (4) |
| #define TXA_HA_MODE_INTRLV_TYPE_WIDTH (2) |
| #define TXA_HA_MODE_INTRLV_TYPE_MASK (0x00000030) |
| |
| #define TXA_HA_MODE_ENC_RATE_LSB (2) |
| #define TXA_HA_MODE_ENC_RATE_WIDTH (2) |
| #define TXA_HA_MODE_ENC_RATE_MASK (0x0000000C) |
| |
| #define TXA_HA_MODE_ENC_TYPE_LSB (1) |
| #define TXA_HA_MODE_ENC_TYPE_WIDTH (1) |
| #define TXA_HA_MODE_ENC_TYPE_MASK (0x00000002) |
| #define TXA_HA_MODE_ENC_TYPE_BIT (0x00000002) |
| |
| #define TXA_HA_MODE_TX_HA_MEM_RST_LSB (0) |
| #define TXA_HA_MODE_TX_HA_MEM_RST_WIDTH (1) |
| #define TXA_HA_MODE_TX_HA_MEM_RST_MASK (0x00000001) |
| #define TXA_HA_MODE_TX_HA_MEM_RST_BIT (0x00000001) |
| |
| #define TXA_INTRLV_PARM_BLK_J1_LSB (9) |
| #define TXA_INTRLV_PARM_BLK_J1_WIDTH (3) |
| #define TXA_INTRLV_PARM_BLK_J1_MASK (0x00000E00) |
| |
| #define TXA_INTRLV_PARM_BLK_J0_LSB (6) |
| #define TXA_INTRLV_PARM_BLK_J0_WIDTH (3) |
| #define TXA_INTRLV_PARM_BLK_J0_MASK (0x000001C0) |
| |
| #define TXA_INTRLV_PARM_BLK_M_LSB (4) |
| #define TXA_INTRLV_PARM_BLK_M_WIDTH (2) |
| #define TXA_INTRLV_PARM_BLK_M_MASK (0x00000030) |
| |
| #define TXA_INTRLV_PARM_TURBO_N_LSB (0) |
| #define TXA_INTRLV_PARM_TURBO_N_WIDTH (3) |
| #define TXA_INTRLV_PARM_TURBO_N_MASK (0x00000007) |
| |
| #define TXA_FREP_L_LSB (0) |
| #define TXA_FREP_L_WIDTH (14) |
| #define TXA_FREP_L_MASK (0x00003FFF) |
| |
| #define CHL_TYPE_LSB (0) |
| #define CHL_TYPE_WIDTH (2) |
| #define CHL_TYPE_MASK (0x00000003) |
| |
| #define TXA_CRC_RTT_RC_IDX_LSB (5) |
| #define TXA_CRC_RTT_RC_IDX_WIDTH (1) |
| #define TXA_CRC_RTT_RC_IDX_MASK (0x00000020) |
| #define TXA_CRC_RTT_RC_IDX_BIT (0x00000020) |
| |
| #define TXA_CRC_TXA_CRC_LEN_LSB (0) |
| #define TXA_CRC_TXA_CRC_LEN_WIDTH (5) |
| #define TXA_CRC_TXA_CRC_LEN_MASK (0x0000001F) |
| |
| #define TXA_FREP_LPML_LSB (0) |
| #define TXA_FREP_LPML_WIDTH (15) |
| #define TXA_FREP_LPML_MASK (0x00007FFF) |
| |
| #define TXA_FREP_MM1_LSB (0) |
| #define TXA_FREP_MM1_WIDTH (15) |
| #define TXA_FREP_MM1_MASK (0x00007FFF) |
| |
| #define TXA_FREP_ACC0_LSB (0) |
| #define TXA_FREP_ACC0_WIDTH (15) |
| #define TXA_FREP_ACC0_MASK (0x00007FFF) |
| |
| #define TXA_PUNC_PAT0_LSB (0) |
| #define TXA_PUNC_PAT0_WIDTH (16) |
| #define TXA_PUNC_PAT0_MASK (0x0000FFFF) |
| |
| #define TXA_PUNC_PAT1_LSB (0) |
| #define TXA_PUNC_PAT1_WIDTH (16) |
| #define TXA_PUNC_PAT1_MASK (0x0000FFFF) |
| |
| #define TXA_FREP_LP_LSB (0) |
| #define TXA_FREP_LP_WIDTH (15) |
| #define TXA_FREP_LP_MASK (0x00007FFF) |
| |
| #define TXA_TST_CTRL_TXA_ADD_LSB (2) |
| #define TXA_TST_CTRL_TXA_ADD_WIDTH (11) |
| #define TXA_TST_CTRL_TXA_ADD_MASK (0x00001FFC) |
| |
| #define TXA_TST_CTRL_TXA_ADD_MD_LSB (1) |
| #define TXA_TST_CTRL_TXA_ADD_MD_WIDTH (1) |
| #define TXA_TST_CTRL_TXA_ADD_MD_MASK (0x00000002) |
| #define TXA_TST_CTRL_TXA_ADD_MD_BIT (0x00000002) |
| |
| #define TXA_TST_CTRL_TXA_TST_MD_LSB (0) |
| #define TXA_TST_CTRL_TXA_TST_MD_WIDTH (1) |
| #define TXA_TST_CTRL_TXA_TST_MD_MASK (0x00000001) |
| #define TXA_TST_CTRL_TXA_TST_MD_BIT (0x00000001) |
| |
| #define RTT_CHNL_BASE_ADDR_LSB (0) |
| #define RTT_CHNL_BASE_ADDR_WIDTH (32) |
| #define RTT_CHNL_BASE_ADDR_MASK (0xFFFFFFFF) |
| |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_LSB (2) |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_WIDTH (1) |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_MASK (0x00000004) |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_RST_BIT (0x00000004) |
| |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_LSB (1) |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_WIDTH (1) |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_MASK (0x00000002) |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_Q_EN_BIT (0x00000002) |
| |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_LSB (0) |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_WIDTH (1) |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_MASK (0x00000001) |
| #define TXBRP_DBG_CRC32_EN_TXBRP_DBG_WT_CRC_I_EN_BIT (0x00000001) |
| |
| #define TXBRP_DBG_CRC32_RSLT_I_LSB (0) |
| #define TXBRP_DBG_CRC32_RSLT_I_WIDTH (24) |
| #define TXBRP_DBG_CRC32_RSLT_I_MASK (0x00FFFFFF) |
| |
| #define TXBRP_DBG_CRC32_RSLT_Q_LSB (0) |
| #define TXBRP_DBG_CRC32_RSLT_Q_WIDTH (24) |
| #define TXBRP_DBG_CRC32_RSLT_Q_MASK (0x00FFFFFF) |
| |
| #define DEBUG_CRC_SEL_LSB (0) |
| #define DEBUG_CRC_SEL_WIDTH (4) |
| #define DEBUG_CRC_SEL_MASK (0x0000000F) |
| |
| #endif //#ifndef _CPH_1X_TXBRP_H_ |