| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _CPH_1X_TXCRP_H_ |
| #define _CPH_1X_TXCRP_H_ |
| |
| /** TBD: Common register read and write function, maybe replaced later */ |
| typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| |
| #if defined(__MD93__)||defined(__MD95__) |
| #define TXCRP_C_1XRTT_REG_BASE (0xa8160000) |
| #else |
| #define TXCRP_C_1XRTT_REG_BASE (0xa8960000) |
| #endif |
| #define TXCRP_C_1XRTT_end (TXCRP_C_1XRTT_REG_BASE + 0x0064 + 1*4) |
| |
| #define C1XTXCRP_ACK1_BIT ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0000)) |
| #define C1XTXCRP_CTRL ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0004)) |
| #define C1XTXCRP_PC_BIT_EPM ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0008)) |
| #define C1XTXCRP_FCH_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x000C)) |
| #define C1XTXCRP_SCH_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0010)) |
| #define C1XTXCRP_PILOT_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0014)) |
| #define C1XTXCRP_ACKCH1_SCALE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0018)) |
| #define C1XTXCRP_TEST_CTRL ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x001C)) |
| #define C1XTXCRP_LC_INIT_0 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0020)) |
| #define C1XTXCRP_LC_INIT_1 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0024)) |
| #define C1XTXCRP_LC_INIT_2 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0028)) |
| #define C1XTXCRP_LC_MASK_0 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x002C)) |
| #define C1XTXCRP_LC_MASK_1 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0030)) |
| #define C1XTXCRP_LC_MASK_2 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0034)) |
| #define C1XTXCRP_LC_SCRAMBLE ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0038)) |
| #define C1XTXCRP_ACTIVE_STOP ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x003C)) |
| #define C1XTXCRP_SC_INIT_PCG ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0040)) |
| #define C1XTXCRP_FCH_STATUS ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0044)) |
| #define C1XTXCRP_KS_START ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0048)) |
| #define C1XTXCRP_KS_SQUARE_DB_RESULT ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x004C)) |
| #define C1XTXCRP_PCG_INDEX_EPM ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0054)) |
| #define C1XTXCRP_TXBRP_MEM_END_EPM ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0058)) |
| #define C1XTXCRP_DEBUG_OB_0 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x005C)) |
| #define C1XTXCRP_DEBUG_OB_1 ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0060)) |
| #define C1XTXCRP_LATCH_SWITCH ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0064)) |
| //#define C1XTXCRP_SW_RESET ((APBADDR32)(TXCRP_C_1XRTT_REG_BASE + 0x0068)) |
| |
| /** Register filed definition */ |
| #define ACKCH1_RESULT_LSB (0) |
| #define ACKCH1_RESULT_WIDTH (1) |
| #define ACKCH1_RESULT_MASK (0x00000001) |
| #define ACKCH1_RESULT_BIT (0x00000001) |
| |
| #define ACKCH1_EN_LSB (8) |
| #define ACKCH1_EN_WIDTH (1) |
| #define ACKCH1_EN_MASK (0x00000100) |
| #define ACKCH1_EN_BIT (0x00000100) |
| |
| #define SCH_WALSH_COVER_LSB (6) |
| #define SCH_WALSH_COVER_WIDTH (2) |
| #define SCH_WALSH_COVER_MASK (0x000000C0) |
| |
| #define PILOT_EN_LSB (5) |
| #define PILOT_EN_WIDTH (1) |
| #define PILOT_EN_MASK (0x00000020) |
| #define PILOT_EN_BIT (0x00000020) |
| |
| #define SCH_EN_LSB (4) |
| #define SCH_EN_WIDTH (1) |
| #define SCH_EN_MASK (0x00000010) |
| #define SCH_EN_BIT (0x00000010) |
| |
| #define FCH_EN_LSB (2) |
| #define FCH_EN_WIDTH (1) |
| #define FCH_EN_MASK (0x00000004) |
| #define FCH_EN_BIT (0x00000004) |
| |
| #define IS95_EN_LSB (0) |
| #define IS95_EN_WIDTH (1) |
| #define IS95_EN_MASK (0x00000001) |
| #define IS95_EN_BIT (0x00000001) |
| |
| #define PC_BIT_MANUAL_LSB (1) |
| #define PC_BIT_MANUAL_WIDTH (1) |
| #define PC_BIT_MANUAL_MASK (0x00000002) |
| #define PC_BIT_MANUAL_BIT (0x00000002) |
| |
| #define PC_BIT_MANUAL_EN_LSB (0) |
| #define PC_BIT_MANUAL_EN_WIDTH (1) |
| #define PC_BIT_MANUAL_EN_MASK (0x00000001) |
| #define PC_BIT_MANUAL_EN_BIT (0x00000001) |
| |
| #define FCH_SCALE_LSB (0) |
| #define FCH_SCALE_WIDTH (9) |
| #define FCH_SCALE_MASK (0x000001FF) |
| |
| #define SCH_SCALE_LSB (0) |
| #define SCH_SCALE_WIDTH (9) |
| #define SCH_SCALE_MASK (0x000001FF) |
| |
| #define PILOT_SCALE_LSB (0) |
| #define PILOT_SCALE_WIDTH (9) |
| #define PILOT_SCALE_MASK (0x000001FF) |
| |
| #define ACKCH1_SCALE_LSB (0) |
| #define ACKCH1_SCALE_WIDTH (9) |
| #define ACKCH1_SCALE_MASK (0x000001FF) |
| |
| #define TESTCTRL_HW_CLKEN_BYP_LSB (1) |
| #define TESTCTRL_HW_CLKEN_BYP_WIDTH (1) |
| #define TESTCTRL_HW_CLKEN_BYP_MASK (0x00000002) |
| #define TESTCTRL_HW_CLKEN_BYP_BIT (0x00000002) |
| |
| #define TESTCTRL_CONJUGATE_LSB (0) |
| #define TESTCTRL_CONJUGATE_WIDTH (1) |
| #define TESTCTRL_CONJUGATE_MASK (0x00000001) |
| #define TESTCTRL_CONJUGATE_BIT (0x00000001) |
| |
| #define LC_INIT_VALUE_15_0_LSB (0) |
| #define LC_INIT_VALUE_15_0_WIDTH (16) |
| #define LC_INIT_VALUE_15_0_MASK (0x0000FFFF) |
| |
| #define LC_INIT_VALUE_31_16_LSB (0) |
| #define LC_INIT_VALUE_31_16_WIDTH (16) |
| #define LC_INIT_VALUE_31_16_MASK (0x0000FFFF) |
| |
| #define LC_INIT_VALUE_41_32_LSB (0) |
| #define LC_INIT_VALUE_41_32_WIDTH (10) |
| #define LC_INIT_VALUE_41_32_MASK (0x000003FF) |
| |
| #define LC_MASK_15_0_LSB (0) |
| #define LC_MASK_15_0_WIDTH (16) |
| #define LC_MASK_15_0_MASK (0x0000FFFF) |
| |
| #define LC_MASK_31_16_LSB (0) |
| #define LC_MASK_31_16_WIDTH (16) |
| #define LC_MASK_31_16_MASK (0x0000FFFF) |
| |
| #define LC_MASK_41_32_LSB (0) |
| #define LC_MASK_41_32_WIDTH (10) |
| #define LC_MASK_41_32_MASK (0x000003FF) |
| |
| #define LC_SCRAMBLE_LSB (0) |
| #define LC_SCRAMBLE_WIDTH (14) |
| #define LC_SCRAMBLE_MASK (0x00003FFF) |
| |
| #define ACTIVE_EN_LSB (1) |
| #define ACTIVE_EN_WIDTH (1) |
| #define ACTIVE_EN_MASK (0x00000002) |
| #define ACTIVE_EN_BIT (0x00000002) |
| |
| #define STOP_BY_PCG_LSB (0) |
| #define STOP_BY_PCG_WIDTH (1) |
| #define STOP_BY_PCG_MASK (0x00000001) |
| #define STOP_BY_PCG_BIT (0x00000001) |
| |
| #define SC_INIT_PCG_LSB (1) |
| #define SC_INIT_PCG_WIDTH (6) |
| #define SC_INIT_PCG_MASK (0x0000007E) |
| |
| #define SC_INIT_PCG_START_LSB (0) |
| #define SC_INIT_PCG_START_WIDTH (1) |
| #define SC_INIT_PCG_START_MASK (0x00000001) |
| #define SC_INIT_PCG_START_BIT (0x00000001) |
| |
| #define FCH_PREAMBLE_EN_LSB (1) |
| #define FCH_PREAMBLE_EN_WIDTH (1) |
| #define FCH_PREAMBLE_EN_MASK (0x00000002) |
| #define FCH_PREAMBLE_EN_BIT (0x00000002) |
| |
| #define FCH_GATING_EN_LSB (0) |
| #define FCH_GATING_EN_WIDTH (1) |
| #define FCH_GATING_EN_MASK (0x00000001) |
| #define FCH_GATING_EN_BIT (0x00000001) |
| |
| #define KS_CALC_START_LSB (1) |
| #define KS_CALC_START_WIDTH (1) |
| #define KS_CALC_START_MASK (0x00000002) |
| #define KS_CALC_START_BIT (0x00000002) |
| |
| #define KS_CALC_MANUAL_LSB (0) |
| #define KS_CALC_MANUAL_WIDTH (1) |
| #define KS_CALC_MANUAL_MASK (0x00000001) |
| #define KS_CALC_MANUAL_BIT (0x00000001) |
| |
| #define KS_CALC_RESULT_LSB (1) |
| #define KS_CALC_RESULT_WIDTH (13) |
| #define KS_CALC_RESULT_MASK (0x00003FFE) |
| |
| #define KS_CALC_FINISH_LSB (0) |
| #define KS_CALC_FINISH_WIDTH (1) |
| #define KS_CALC_FINISH_MASK (0x00000001) |
| #define KS_CALC_FINISH_BIT (0x00000001) |
| |
| #define PCG_INDEX_MANUAL_LSB (1) |
| #define PCG_INDEX_MANUAL_WIDTH (4) |
| #define PCG_INDEX_MANUAL_MASK (0x0000001E) |
| |
| #define PCG_INDEX_MANUAL_EN_LSB (0) |
| #define PCG_INDEX_MANUAL_EN_WIDTH (1) |
| #define PCG_INDEX_MANUAL_EN_MASK (0x00000001) |
| #define PCG_INDEX_MANUAL_EN_BIT (0x00000001) |
| |
| #define TXBRP_ADDR_2_MANUAL_EN_LSB (10) |
| #define TXBRP_ADDR_2_MANUAL_EN_WIDTH (10) |
| #define TXBRP_ADDR_2_MANUAL_EN_MASK (0x000FFC00) |
| |
| #define TXBRP_ADDR_1_MANUAL_EN_LSB (1) |
| #define TXBRP_ADDR_1_MANUAL_EN_WIDTH (9) |
| #define TXBRP_ADDR_1_MANUAL_EN_MASK (0x000003FE) |
| |
| #define TXBRP_ADDR_MANUAL_EN_LSB (0) |
| #define TXBRP_ADDR_MANUAL_EN_WIDTH (1) |
| #define TXBRP_ADDR_MANUAL_EN_MASK (0x00000001) |
| #define TXBRP_ADDR_MANUAL_EN_BIT (0x00000001) |
| |
| #define HW_DEBUG_OB_31_0_LSB (0) |
| #define HW_DEBUG_OB_31_0_WIDTH (32) |
| #define HW_DEBUG_OB_31_0_MASK (0xFFFFFFFF) |
| |
| #define HW_DEBUG_OB_63_32_LSB (0) |
| #define HW_DEBUG_OB_63_32_WIDTH (32) |
| #define HW_DEBUG_OB_63_32_MASK (0xFFFFFFFF) |
| |
| #define LATCH_SWITCH_LSB (0) |
| #define LATCH_SWITCH_WIDTH (1) |
| #define LATCH_SWITCH_MASK (0x00000001) |
| #define LATCH_SWITCH_BIT (0x00000001) |
| |
| #define SW_RST_LSB (0) |
| #define SW_RST_WIDTH (1) |
| #define SW_RST_MASK (0x00000001) |
| #define SW_RST_BIT (0x00000001) |
| |
| |
| #endif |