| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _CPH_EVDO_TXCRP_H_ |
| #define _CPH_EVDO_TXCRP_H_ |
| |
| |
| |
| /*---------------------------------------------------------------------------- |
| Global Typedefs |
| ----------------------------------------------------------------------------*/ |
| |
| typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| |
| #if defined(__MD93__)||defined(__MD95__) |
| #define TXCRP_C_EVDO_REG_BASE (0xA8100000) |
| #else |
| #define TXCRP_C_EVDO_REG_BASE (0xA8900000) |
| #endif |
| |
| #define TXCRP_C_EVDO_end (TXCRP_C_EVDO_REG_BASE + 0x50110 + 1*4) |
| |
| |
| |
| #define TXCRP_DO_RRI_DATA_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50000)) |
| #define TXCRP_DO_RRI_DATA_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50004)) |
| #define TXCRP_DO_RRI_DATA_2_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50008)) |
| #define TXCRP_DO_RRI_DATA_2_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5000C)) |
| #define TXCRP_DO_DRC_COVER_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50010)) |
| #define TXCRP_DO_DRC_COVER_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50014)) |
| #define TXCRP_DO_DSC_DATA_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50018)) |
| #define TXCRP_DO_DSC_DATA_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5001C)) |
| #define TXCRP_DO_TX_LONG_PN_INITIAL1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50020)) |
| #define TXCRP_DO_TX_LONG_PN_INITIAL2 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50024)) |
| #define TXCRP_DO_LD_OFFSET ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50028)) |
| #define TXCRP_DO_RD_BASE_ADDR_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5002C)) |
| #define TXCRP_DO_RD_BASE_ADDR_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50030)) |
| #define TXCRP_DO_CHNL_TYPE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50034)) |
| #define TXCRP_DO_PROTOCOL_SUBTYP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50038)) |
| #define TXCRP_DO_TX_ENABLE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5003C)) |
| #define TXCRP_DO_TX_IQ_INV ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50040)) |
| #define TXCRP_DO_TX_LONG_PN_MASK2 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50044)) |
| #define TXCRP_DO_TX_LONG_PN_MASK1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50048)) |
| #define TXCRP_DO_LONGPN_LOAD ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5004C)) |
| #define TXCRP_DO_DRC_BOOST_LEN ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50050)) |
| #define TXCRP_DO_DSC_BOOST_LEN ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50054)) |
| #define TXCRP_DO_AUXPLT_MINPYLD ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50058)) |
| #define TXCRP_DO_PLT_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5005C)) |
| #define TXCRP_DO_AUXPLT_SCALE_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50060)) |
| #define TXCRP_DO_AUXPLT_SCALE_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50064)) |
| #define TXCRP_DO_RRI_SCALE_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50068)) |
| #define TXCRP_DO_RRI_SCALE_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5006C)) |
| #define TXCRP_DO_DSC_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50070)) |
| #define TXCRP_DO_DSC_SCALE_BOOST ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50074)) |
| #define TXCRP_DO_DRC_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50078)) |
| #define TXCRP_DO_DRC_SCALE_BOOST ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5007C)) |
| #define TXCRP_DO_BOOST_SELECT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50080)) |
| #define TXCRP_DO_DSC_SCALE_INDICATE_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50084)) |
| #define TXCRP_DO_DSC_SCALE_INDICATE_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50088)) |
| #define TXCRP_DO_DRC_SCALE_INDICATE_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5008C)) |
| #define TXCRP_DO_DRC_SCALE_INDICATE_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50090)) |
| #define TXCRP_DO_ACK_SCALE_SUP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50094)) |
| #define TXCRP_DO_ACK_SCALE_MUP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50098)) |
| #define TXCRP_DO_DATA_SCALE0_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5009C)) |
| #define TXCRP_DO_DATA_SCALE1_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500A0)) |
| #define TXCRP_DO_DATA_SCALE2_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500A4)) |
| #define TXCRP_DO_DATA_SCALE3_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500A8)) |
| #define TXCRP_DO_DATA_SCALE0_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500AC)) |
| #define TXCRP_DO_DATA_SCALE1_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500B0)) |
| #define TXCRP_DO_DATA_SCALE2_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500B4)) |
| #define TXCRP_DO_DATA_SCALE3_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500B8)) |
| #define TXCRP_DO_KS_TRIGGER ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500BC)) |
| #define TXCRP_DO_TRIGGER_SELECT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500C0)) |
| #define TXCRP_DO_DRC_SELECT_0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500C4)) |
| #define TXCRP_DO_DRC_SELECT_1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500C8)) |
| #define TXCRP_DO_SW_RST ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500CC)) |
| #define TXCRP_DO_PREPLT_SCALE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500D0)) |
| #define TXCRP_DO_ACK_ENABLE_BIT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500D4)) |
| #define TXCRP_DO_ACK_DATA ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500D8)) |
| #define TXCRP_DO_DATA_SCALE_KS_ACK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500DC)) |
| #define TXCRP_DO_DATA_SCALE_KS_NAK ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500E0)) |
| #define TXCRP_DO_TX_FREEZE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500E4)) |
| #define TXCRP_DO_TIMER_TRIGGER ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500E8)) |
| #define TXCRP_DO_TX_TEST_MODE ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500EC)) |
| #define TXCRP_DO_TX_TEST0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500F0)) |
| #define TXCRP_DO_TX_TEST1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500F4)) |
| #define TXCRP_DO_DRC_LENGTH ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500F8)) |
| #define TXCRP_DO_DRC_GATING ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x500FC)) |
| #define TXCRP_STATE_Q ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50100)) |
| #define TXCRP_DO_TX_FSM ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50104)) |
| #define TXCRP_DRC_DATA_I ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50108)) |
| #define TXCRP_DOTXCRP_FSM_IS_BUSY ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5010C)) |
| #define TXCRP_CDO_CHIP_COUNT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50110)) |
| #define TXCRP_CDO_TICK_COUNT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50114)) |
| #define TXCRP_RAKE_TXCRP_REV_ACK_BIT ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50118)) |
| #define TXCRP_TXCRP_KS0 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x5011C)) |
| #define TXCRP_TXCRP_KS1 ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50120)) |
| #define TXCRP_CDO_KS_VALUE_EXP ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50124)) |
| #define TXCRP_CDO_KS_VALUE_MANTISSA ((APBADDR32)(TXCRP_C_EVDO_REG_BASE + 0x50128)) |
| |
| |
| #define DO_RRI_DATA_0_DO_RRI_DATA_0_LSB (0) |
| #define DO_RRI_DATA_0_DO_RRI_DATA_0_WIDTH (7) |
| #define DO_RRI_DATA_0_DO_RRI_DATA_0_MASK (0x0000007F) |
| |
| #define DO_RRI_DATA_1_DO_RRI_DATA_1_LSB (0) |
| #define DO_RRI_DATA_1_DO_RRI_DATA_1_WIDTH (7) |
| #define DO_RRI_DATA_1_DO_RRI_DATA_1_MASK (0x0000007F) |
| |
| #define DO_RRI_DATA_2_ACK_DO_RRI_DATA_2_ACK_LSB (0) |
| #define DO_RRI_DATA_2_ACK_DO_RRI_DATA_2_ACK_WIDTH (7) |
| #define DO_RRI_DATA_2_ACK_DO_RRI_DATA_2_ACK_MASK (0x0000007F) |
| |
| #define DO_RRI_DATA_2_NAK_DO_RRI_DATA_2_NAK_LSB (0) |
| #define DO_RRI_DATA_2_NAK_DO_RRI_DATA_2_NAK_WIDTH (7) |
| #define DO_RRI_DATA_2_NAK_DO_RRI_DATA_2_NAK_MASK (0x0000007F) |
| |
| #define DO_DRC_COVER_0_DO_DRC_COVER_0_LSB (0) |
| #define DO_DRC_COVER_0_DO_DRC_COVER_0_WIDTH (4) |
| #define DO_DRC_COVER_0_DO_DRC_COVER_0_MASK (0x0000000F) |
| |
| #define DO_DRC_COVER_1_DO_DRC_COVER_1_LSB (0) |
| #define DO_DRC_COVER_1_DO_DRC_COVER_1_WIDTH (4) |
| #define DO_DRC_COVER_1_DO_DRC_COVER_1_MASK (0x0000000F) |
| |
| #define DO_DSC_DATA_0_DO_DSC_DATA_0_LSB (0) |
| #define DO_DSC_DATA_0_DO_DSC_DATA_0_WIDTH (4) |
| #define DO_DSC_DATA_0_DO_DSC_DATA_0_MASK (0x0000000F) |
| |
| #define DO_DSC_DATA_1_DO_DSC_DATA_1_LSB (0) |
| #define DO_DSC_DATA_1_DO_DSC_DATA_1_WIDTH (4) |
| #define DO_DSC_DATA_1_DO_DSC_DATA_1_MASK (0x0000000F) |
| |
| #define DO_TX_LONG_PN_INITIAL1_DO_TX_LONG_PN_INITIAL1_LSB (0) |
| #define DO_TX_LONG_PN_INITIAL1_DO_TX_LONG_PN_INITIAL1_WIDTH (32) |
| #define DO_TX_LONG_PN_INITIAL1_DO_TX_LONG_PN_INITIAL1_MASK (0xFFFFFFFF) |
| |
| #define DO_TX_LONG_PN_INITIAL2_DO_TX_LONG_PN_INITIAL2_LSB (0) |
| #define DO_TX_LONG_PN_INITIAL2_DO_TX_LONG_PN_INITIAL2_WIDTH (10) |
| #define DO_TX_LONG_PN_INITIAL2_DO_TX_LONG_PN_INITIAL2_MASK (0x000003FF) |
| |
| #define DO_LD_OFFSET_DO_LD_OFFSET_LSB (0) |
| #define DO_LD_OFFSET_DO_LD_OFFSET_WIDTH (15) |
| #define DO_LD_OFFSET_DO_LD_OFFSET_MASK (0x00007FFF) |
| |
| #define DO_RD_BASE_ADDR_ACK_DO_RD_BASE_ADDR_ACK_LSB (0) |
| #define DO_RD_BASE_ADDR_ACK_DO_RD_BASE_ADDR_ACK_WIDTH (11) |
| #define DO_RD_BASE_ADDR_ACK_DO_RD_BASE_ADDR_ACK_MASK (0x000007FF) |
| |
| #define DO_RD_BASE_ADDR_NAK_DO_RD_BASE_ADDR_NAK_LSB (0) |
| #define DO_RD_BASE_ADDR_NAK_DO_RD_BASE_ADDR_NAK_WIDTH (11) |
| #define DO_RD_BASE_ADDR_NAK_DO_RD_BASE_ADDR_NAK_MASK (0x000007FF) |
| |
| #define DO_CHNL_TYPE_DO_CHNL_TYPE_LSB (0) |
| #define DO_CHNL_TYPE_DO_CHNL_TYPE_WIDTH (1) |
| #define DO_CHNL_TYPE_DO_CHNL_TYPE_MASK (0x00000001) |
| #define DO_CHNL_TYPE_DO_CHNL_TYPE_BIT (0x00000001) |
| |
| #define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_LSB (0) |
| #define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_WIDTH (1) |
| #define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_MASK (0x00000001) |
| #define DO_PROTOCOL_SUBTYP_DO_PROTOCOL_SUBTYP_BIT (0x00000001) |
| |
| #define DO_TX_ENABLE_DO_TX_ENABLE_LSB (0) |
| #define DO_TX_ENABLE_DO_TX_ENABLE_WIDTH (1) |
| #define DO_TX_ENABLE_DO_TX_ENABLE_MASK (0x00000001) |
| #define DO_TX_ENABLE_DO_TX_ENABLE_BIT (0x00000001) |
| |
| #define DO_TX_IQ_INV_DO_TX_IQ_INV_LSB (0) |
| #define DO_TX_IQ_INV_DO_TX_IQ_INV_WIDTH (1) |
| #define DO_TX_IQ_INV_DO_TX_IQ_INV_MASK (0x00000001) |
| #define DO_TX_IQ_INV_DO_TX_IQ_INV_BIT (0x00000001) |
| |
| #define DO_TX_LONG_PN_MASK2_DO_TX_LONG_PN_MASK2_LSB (0) |
| #define DO_TX_LONG_PN_MASK2_DO_TX_LONG_PN_MASK2_WIDTH (10) |
| #define DO_TX_LONG_PN_MASK2_DO_TX_LONG_PN_MASK2_MASK (0x000003FF) |
| |
| #define DO_TX_LONG_PN_MASK1_DO_TX_LONG_PN_MASK1_LSB (0) |
| #define DO_TX_LONG_PN_MASK1_DO_TX_LONG_PN_MASK1_WIDTH (32) |
| #define DO_TX_LONG_PN_MASK1_DO_TX_LONG_PN_MASK1_MASK (0xFFFFFFFF) |
| |
| #define DO_LONGPN_LOAD_DO_LONGPN_LOAD_LSB (0) |
| #define DO_LONGPN_LOAD_DO_LONGPN_LOAD_WIDTH (1) |
| #define DO_LONGPN_LOAD_DO_LONGPN_LOAD_MASK (0x00000001) |
| #define DO_LONGPN_LOAD_DO_LONGPN_LOAD_BIT (0x00000001) |
| |
| #define DO_DRC_BOOST_LEN_DO_DRC_BOOST_LEN_LSB (0) |
| #define DO_DRC_BOOST_LEN_DO_DRC_BOOST_LEN_WIDTH (6) |
| #define DO_DRC_BOOST_LEN_DO_DRC_BOOST_LEN_MASK (0x0000003F) |
| |
| #define DO_DSC_BOOST_LEN_DO_DSC_BOOST_LEN_LSB (0) |
| #define DO_DSC_BOOST_LEN_DO_DSC_BOOST_LEN_WIDTH (7) |
| #define DO_DSC_BOOST_LEN_DO_DSC_BOOST_LEN_MASK (0x0000007F) |
| |
| #define DO_AUXPLT_MINPYLD_DO_AUXPLT_MINPYLD_LSB (0) |
| #define DO_AUXPLT_MINPYLD_DO_AUXPLT_MINPYLD_WIDTH (4) |
| #define DO_AUXPLT_MINPYLD_DO_AUXPLT_MINPYLD_MASK (0x0000000F) |
| |
| #define DO_PLT_SCALE_DO_PLT_SCALE_LSB (0) |
| #define DO_PLT_SCALE_DO_PLT_SCALE_WIDTH (9) |
| #define DO_PLT_SCALE_DO_PLT_SCALE_MASK (0x000001FF) |
| |
| #define DO_AUXPLT_SCALE_ACK_DO_AUXPLT_SCALE_ACK_LSB (0) |
| #define DO_AUXPLT_SCALE_ACK_DO_AUXPLT_SCALE_ACK_WIDTH (13) |
| #define DO_AUXPLT_SCALE_ACK_DO_AUXPLT_SCALE_ACK_MASK (0x00001FFF) |
| |
| #define DO_AUXPLT_SCALE_NAK_DO_AUXPLT_SCALE_NAK_LSB (0) |
| #define DO_AUXPLT_SCALE_NAK_DO_AUXPLT_SCALE_NAK_WIDTH (13) |
| #define DO_AUXPLT_SCALE_NAK_DO_AUXPLT_SCALE_NAK_MASK (0x00001FFF) |
| |
| #define DO_RRI_SCALE_ACK_DO_RRI_SCALE_ACK_LSB (0) |
| #define DO_RRI_SCALE_ACK_DO_RRI_SCALE_ACK_WIDTH (9) |
| #define DO_RRI_SCALE_ACK_DO_RRI_SCALE_ACK_MASK (0x000001FF) |
| |
| #define DO_RRI_SCALE_NAK_DO_RRI_SCALE_NAK_LSB (0) |
| #define DO_RRI_SCALE_NAK_DO_RRI_SCALE_NAK_WIDTH (9) |
| #define DO_RRI_SCALE_NAK_DO_RRI_SCALE_NAK_MASK (0x000001FF) |
| |
| #define DO_DSC_SCALE_DO_DSC_SCALE_LSB (0) |
| #define DO_DSC_SCALE_DO_DSC_SCALE_WIDTH (9) |
| #define DO_DSC_SCALE_DO_DSC_SCALE_MASK (0x000001FF) |
| |
| #define DO_DSC_SCALE_BOOST_DO_DSC_SCALE_BOOST_LSB (0) |
| #define DO_DSC_SCALE_BOOST_DO_DSC_SCALE_BOOST_WIDTH (9) |
| #define DO_DSC_SCALE_BOOST_DO_DSC_SCALE_BOOST_MASK (0x000001FF) |
| |
| #define DO_DRC_SCALE_DO_DRC_SCALE_LSB (0) |
| #define DO_DRC_SCALE_DO_DRC_SCALE_WIDTH (9) |
| #define DO_DRC_SCALE_DO_DRC_SCALE_MASK (0x000001FF) |
| |
| #define DO_DRC_SCALE_BOOST_DO_DRC_SCALE_BOOST_LSB (0) |
| #define DO_DRC_SCALE_BOOST_DO_DRC_SCALE_BOOST_WIDTH (9) |
| #define DO_DRC_SCALE_BOOST_DO_DRC_SCALE_BOOST_MASK (0x000001FF) |
| |
| #define DO_BOOST_SELECT_DO_BOOST_SELECT_LSB (0) |
| #define DO_BOOST_SELECT_DO_BOOST_SELECT_WIDTH (2) |
| #define DO_BOOST_SELECT_DO_BOOST_SELECT_MASK (0x00000003) |
| |
| #define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_LSB (0) |
| #define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_WIDTH (1) |
| #define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_MASK (0x00000001) |
| #define DO_DSC_SCALE_INDICATE_0_DO_DSC_SCALE_INDICATE_0_BIT (0x00000001) |
| |
| #define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_LSB (0) |
| #define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_WIDTH (1) |
| #define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_MASK (0x00000001) |
| #define DO_DSC_SCALE_INDICATE_1_DO_DSC_SCALE_INDICATE_1_BIT (0x00000001) |
| |
| #define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_LSB (0) |
| #define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_WIDTH (1) |
| #define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_MASK (0x00000001) |
| #define DO_DRC_SCALE_INDICATE_0_DO_DRC_SCALE_INDICATE_0_BIT (0x00000001) |
| |
| #define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_LSB (0) |
| #define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_WIDTH (1) |
| #define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_MASK (0x00000001) |
| #define DO_DRC_SCALE_INDICATE_1_DO_DRC_SCALE_INDICATE_1_BIT (0x00000001) |
| |
| #define DO_ACK_SCALE_SUP_DO_ACK_SCALE_SUP_LSB (0) |
| #define DO_ACK_SCALE_SUP_DO_ACK_SCALE_SUP_WIDTH (9) |
| #define DO_ACK_SCALE_SUP_DO_ACK_SCALE_SUP_MASK (0x000001FF) |
| |
| #define DO_ACK_SCALE_MUP_DO_ACK_SCALE_MUP_LSB (0) |
| #define DO_ACK_SCALE_MUP_DO_ACK_SCALE_MUP_WIDTH (9) |
| #define DO_ACK_SCALE_MUP_DO_ACK_SCALE_MUP_MASK (0x000001FF) |
| |
| #define DO_DATA_SCALE0_ACK_DO_DATA_SCALE0_ACK_LSB (0) |
| #define DO_DATA_SCALE0_ACK_DO_DATA_SCALE0_ACK_WIDTH (11) |
| #define DO_DATA_SCALE0_ACK_DO_DATA_SCALE0_ACK_MASK (0x000007FF) |
| |
| #define DO_DATA_SCALE1_ACK_DO_DATA_SCALE1_ACK_LSB (0) |
| #define DO_DATA_SCALE1_ACK_DO_DATA_SCALE1_ACK_WIDTH (11) |
| #define DO_DATA_SCALE1_ACK_DO_DATA_SCALE1_ACK_MASK (0x000007FF) |
| |
| #define DO_DATA_SCALE2_ACK_DO_DATA_SCALE2_ACK_LSB (0) |
| #define DO_DATA_SCALE2_ACK_DO_DATA_SCALE2_ACK_WIDTH (11) |
| #define DO_DATA_SCALE2_ACK_DO_DATA_SCALE2_ACK_MASK (0x000007FF) |
| |
| #define DO_DATA_SCALE3_ACK_DO_DATA_SCALE3_ACK_LSB (0) |
| #define DO_DATA_SCALE3_ACK_DO_DATA_SCALE3_ACK_WIDTH (11) |
| #define DO_DATA_SCALE3_ACK_DO_DATA_SCALE3_ACK_MASK (0x000007FF) |
| |
| #define DO_DATA_SCALE0_NAK_DO_DATA_SCALE0_NAK_LSB (0) |
| #define DO_DATA_SCALE0_NAK_DO_DATA_SCALE0_NAK_WIDTH (11) |
| #define DO_DATA_SCALE0_NAK_DO_DATA_SCALE0_NAK_MASK (0x000007FF) |
| |
| #define DO_DATA_SCALE1_NAK_DO_DATA_SCALE1_NAK_LSB (0) |
| #define DO_DATA_SCALE1_NAK_DO_DATA_SCALE1_NAK_WIDTH (11) |
| #define DO_DATA_SCALE1_NAK_DO_DATA_SCALE1_NAK_MASK (0x000007FF) |
| |
| #define DO_DATA_SCALE2_NAK_DO_DATA_SCALE2_NAK_LSB (0) |
| #define DO_DATA_SCALE2_NAK_DO_DATA_SCALE2_NAK_WIDTH (11) |
| #define DO_DATA_SCALE2_NAK_DO_DATA_SCALE2_NAK_MASK (0x000007FF) |
| |
| #define DO_DATA_SCALE3_NAK_DO_DATA_SCALE3_NAK_LSB (0) |
| #define DO_DATA_SCALE3_NAK_DO_DATA_SCALE3_NAK_WIDTH (11) |
| #define DO_DATA_SCALE3_NAK_DO_DATA_SCALE3_NAK_MASK (0x000007FF) |
| |
| #define DO_KS_TRIGGER_DO_KS_TRIGGER_LSB (0) |
| #define DO_KS_TRIGGER_DO_KS_TRIGGER_WIDTH (1) |
| #define DO_KS_TRIGGER_DO_KS_TRIGGER_MASK (0x00000001) |
| #define DO_KS_TRIGGER_DO_KS_TRIGGER_BIT (0x00000001) |
| |
| #define DO_TRIGGER_SELECT_DO_TRIGGER_SELECT_LSB (0) |
| #define DO_TRIGGER_SELECT_DO_TRIGGER_SELECT_WIDTH (3) |
| #define DO_TRIGGER_SELECT_DO_TRIGGER_SELECT_MASK (0x00000007) |
| |
| #define DO_DRC_SELECT_0_DO_DRC_SELECT_0_LSB (0) |
| #define DO_DRC_SELECT_0_DO_DRC_SELECT_0_WIDTH (2) |
| #define DO_DRC_SELECT_0_DO_DRC_SELECT_0_MASK (0x00000003) |
| |
| #define DO_DRC_SELECT_1_DO_DRC_SELECT_1_LSB (0) |
| #define DO_DRC_SELECT_1_DO_DRC_SELECT_1_WIDTH (2) |
| #define DO_DRC_SELECT_1_DO_DRC_SELECT_1_MASK (0x00000003) |
| |
| #define DO_SW_RST_DO_SW_RST_LSB (0) |
| #define DO_SW_RST_DO_SW_RST_WIDTH (1) |
| #define DO_SW_RST_DO_SW_RST_MASK (0x00000001) |
| #define DO_SW_RST_DO_SW_RST_BIT (0x00000001) |
| |
| #define DO_PREPLT_SCALE_DO_PREPLT_SCALE_LSB (0) |
| #define DO_PREPLT_SCALE_DO_PREPLT_SCALE_WIDTH (9) |
| #define DO_PREPLT_SCALE_DO_PREPLT_SCALE_MASK (0x000001FF) |
| |
| #define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_LSB (0) |
| #define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_WIDTH (1) |
| #define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_MASK (0x00000001) |
| #define DO_ACK_ENABLE_BIT_DO_ACK_ENABLE_BIT_BIT (0x00000001) |
| |
| #define DO_ACK_DATA_DO_ACK_DATA_LSB (0) |
| #define DO_ACK_DATA_DO_ACK_DATA_WIDTH (2) |
| #define DO_ACK_DATA_DO_ACK_DATA_MASK (0x00000003) |
| |
| #define DO_DATA_SCALE_KS_ACK_DO_DATA_SCALE_KS_ACK_LSB (0) |
| #define DO_DATA_SCALE_KS_ACK_DO_DATA_SCALE_KS_ACK_WIDTH (11) |
| #define DO_DATA_SCALE_KS_ACK_DO_DATA_SCALE_KS_ACK_MASK (0x000007FF) |
| |
| #define DO_DATA_SCALE_KS_NAK_DO_DATA_SCALE_KS_NAK_LSB (0) |
| #define DO_DATA_SCALE_KS_NAK_DO_DATA_SCALE_KS_NAK_WIDTH (11) |
| #define DO_DATA_SCALE_KS_NAK_DO_DATA_SCALE_KS_NAK_MASK (0x000007FF) |
| |
| #define DO_TX_FREEZE_DO_TX_FREEZE_LSB (0) |
| #define DO_TX_FREEZE_DO_TX_FREEZE_WIDTH (1) |
| #define DO_TX_FREEZE_DO_TX_FREEZE_MASK (0x00000001) |
| #define DO_TX_FREEZE_DO_TX_FREEZE_BIT (0x00000001) |
| |
| #define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_LSB (0) |
| #define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_WIDTH (1) |
| #define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_MASK (0x00000001) |
| #define DO_TIMER_TRIGGER_DO_TIMER_TRIGGER_BIT (0x00000001) |
| |
| #define DO_TX_TEST_MODE_DO_TX_TEST_MODE_LSB (0) |
| #define DO_TX_TEST_MODE_DO_TX_TEST_MODE_WIDTH (3) |
| #define DO_TX_TEST_MODE_DO_TX_TEST_MODE_MASK (0x00000007) |
| |
| #define DO_TX_TEST0_DO_TX_TEST0_LSB (0) |
| #define DO_TX_TEST0_DO_TX_TEST0_WIDTH (1) |
| #define DO_TX_TEST0_DO_TX_TEST0_MASK (0x00000001) |
| #define DO_TX_TEST0_DO_TX_TEST0_BIT (0x00000001) |
| |
| #define DO_TX_TEST1_DO_TX_TEST1_LSB (0) |
| #define DO_TX_TEST1_DO_TX_TEST1_WIDTH (4) |
| #define DO_TX_TEST1_DO_TX_TEST1_MASK (0x0000000F) |
| |
| #define DO_DRC_LENGTH_DO_DRC_LENGTH_LSB (0) |
| #define DO_DRC_LENGTH_DO_DRC_LENGTH_WIDTH (2) |
| #define DO_DRC_LENGTH_DO_DRC_LENGTH_MASK (0x00000003) |
| |
| #define DO_DRC_GATING_DO_DRC_GATING_LSB (0) |
| #define DO_DRC_GATING_DO_DRC_GATING_WIDTH (1) |
| #define DO_DRC_GATING_DO_DRC_GATING_MASK (0x00000001) |
| #define DO_DRC_GATING_DO_DRC_GATING_BIT (0x00000001) |
| |
| #define STATE_Q_STATE_Q_LSB (0) |
| #define STATE_Q_STATE_Q_WIDTH (5) |
| #define STATE_Q_STATE_Q_MASK (0x0000001F) |
| |
| #define DO_TX_FSM_DO_TX_FSM_LSB (0) |
| #define DO_TX_FSM_DO_TX_FSM_WIDTH (7) |
| #define DO_TX_FSM_DO_TX_FSM_MASK (0x0000007F) |
| |
| #define DRC_DATA_I_DRC_DATA_I_LSB (0) |
| #define DRC_DATA_I_DRC_DATA_I_WIDTH (4) |
| #define DRC_DATA_I_DRC_DATA_I_MASK (0x0000000F) |
| |
| #define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_LSB (0) |
| #define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_WIDTH (1) |
| #define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_MASK (0x00000001) |
| #define DOTXCRP_FSM_IS_BUSY_DOTXCRP_FSM_IS_BUSY_BIT (0x00000001) |
| |
| #define CDO_CHIP_COUNT_CDO_CHIP_COUNT_LSB (0) |
| #define CDO_CHIP_COUNT_CDO_CHIP_COUNT_WIDTH (11) |
| #define CDO_CHIP_COUNT_CDO_CHIP_COUNT_MASK (0x000007FF) |
| |
| #define CDO_TICK_COUNT_CDO_TICK_COUNT_LSB (0) |
| #define CDO_TICK_COUNT_CDO_TICK_COUNT_WIDTH (6) |
| #define CDO_TICK_COUNT_CDO_TICK_COUNT_MASK (0x0000003F) |
| |
| #define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_LSB (0) |
| #define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_WIDTH (1) |
| #define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_MASK (0x00000001) |
| #define RAKE_TXCRP_REV_ACK_BIT_RAKE_TXCRP_REV_ACK_BIT_BIT (0x00000001) |
| |
| |
| /***************************************************************************** |
| * End of File |
| *****************************************************************************/ |
| |
| |
| #endif //#ifndef _CPH_EVDO_TXCRP_H_ |