| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _CPH_RX_MM_EVENT_GEN_H_ |
| #define _CPH_RX_MM_EVENT_GEN_H_ |
| |
| |
| typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| |
| |
| #define MM_RX_RF_EVENTGEN_REG_BASE (0x00000000) |
| |
| #define MM_RX_RF_EVENTGEN_end (MM_RX_RF_EVENTGEN_REG_BASE + 0x2014 + 32*4) |
| |
| |
| |
| #define MM_EVENTGEN_LTE_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0000)) |
| #define MM_EVENTGEN_FDD_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0004)) |
| #define MM_EVENTGEN_GSM_BSI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0008)) |
| #define MM_EVENTGEN_BSI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x000C)) |
| #define MM_EVENTGEN_BSI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0010)) |
| #define MM_EVENTGEN_BSI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x0014 + (n)*4)) //n is from 0 to 31 |
| #define MM_EVENTGEN_LTE_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1000)) |
| #define MM_EVENTGEN_FDD_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1004)) |
| #define MM_EVENTGEN_GSM_MIPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1008)) |
| #define MM_EVENTGEN_MIPI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x100C)) |
| #define MM_EVENTGEN_MIPI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1010)) |
| #define MM_EVENTGEN_MIPI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x1014 + (n)*4)) //n is from 0 to 31 |
| #define MM_EVENTGEN_LTE_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2000)) |
| #define MM_EVENTGEN_FDD_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2004)) |
| #define MM_EVENTGEN_GSM_BPI_BIAS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2008)) |
| #define MM_EVENTGEN_BPI_EVENT_STATUS ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x200C)) |
| #define MM_EVENTGEN_BPI_EVENT_STOP ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2010)) |
| #define MM_EVENTGEN_BPI_EVENT(n) ((APBADDR32)(MM_RX_RF_EVENTGEN_REG_BASE + 0x2014 + (n)*4)) //n is from 0 to 31 |
| |
| |
| #define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_LSB (0) |
| #define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_WIDTH (20) |
| #define MM_EVENTGEN_LTE_BSI_BIAS_LTE_BSI_BIAS_MASK (0x000FFFFF) |
| |
| #define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_LSB (0) |
| #define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_WIDTH (16) |
| #define MM_EVENTGEN_FDD_BSI_BIAS_FDD_BSI_BIAS_MASK (0x0000FFFF) |
| |
| #define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_LSB (0) |
| #define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_WIDTH (14) |
| #define MM_EVENTGEN_GSM_BSI_BIAS_GSM_BSI_BIAS_MASK (0x00003FFF) |
| |
| #define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_LSB (0) |
| #define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_WIDTH (32) |
| #define MM_EVENTGEN_BSI_EVENT_STATUS_BSI_EVENT_STATUS_MASK (0xFFFFFFFF) |
| |
| #define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_LSB (0) |
| #define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_WIDTH (32) |
| #define MM_EVENTGEN_BSI_EVENT_STOP_BSI_EVENT_STOP_MASK (0xFFFFFFFF) |
| |
| #define MM_EVENTGEN_BSI_EVENT_MODE_LSB (29) |
| #define MM_EVENTGEN_BSI_EVENT_MODE_WIDTH (3) |
| #define MM_EVENTGEN_BSI_EVENT_MODE_MASK (0xE0000000) |
| |
| #define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_LSB (0) |
| #define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_WIDTH (20) |
| #define MM_EVENTGEN_BSI_EVENT_BSI_EVENT_TIME_MASK (0x000FFFFF) |
| |
| #define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_LSB (0) |
| #define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_WIDTH (20) |
| #define MM_EVENTGEN_LTE_MIPI_BIAS_LTE_MIPI_BIAS_MASK (0x000FFFFF) |
| |
| #define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_LSB (0) |
| #define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_WIDTH (16) |
| #define MM_EVENTGEN_FDD_MIPI_BIAS_FDD_MIPI_BIAS_MASK (0x0000FFFF) |
| |
| #define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_LSB (0) |
| #define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_WIDTH (14) |
| #define MM_EVENTGEN_GSM_MIPI_BIAS_GSM_MIPI_BIAS_MASK (0x00003FFF) |
| |
| #define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_LSB (0) |
| #define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_WIDTH (32) |
| #define MM_EVENTGEN_MIPI_EVENT_STATUS_MIPI_EVENT_STATUS_MASK (0xFFFFFFFF) |
| |
| #define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_LSB (0) |
| #define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_WIDTH (32) |
| #define MM_EVENTGEN_MIPI_EVENT_STOP_MIPI_EVENT_STOP_MASK (0xFFFFFFFF) |
| |
| #define MM_EVENTGEN_MIPI_EVENT_MODE_LSB (29) |
| #define MM_EVENTGEN_MIPI_EVENT_MODE_WIDTH (3) |
| #define MM_EVENTGEN_MIPI_EVENT_MODE_MASK (0xE0000000) |
| |
| #define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_LSB (0) |
| #define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_WIDTH (20) |
| #define MM_EVENTGEN_MIPI_EVENT_MIPI_EVENT_TIME_MASK (0x000FFFFF) |
| |
| #define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_LSB (0) |
| #define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_WIDTH (20) |
| #define MM_EVENTGEN_LTE_BPI_BIAS_LTE_BPI_BIAS_MASK (0x000FFFFF) |
| |
| #define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_LSB (0) |
| #define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_WIDTH (16) |
| #define MM_EVENTGEN_FDD_BPI_BIAS_FDD_BPI_BIAS_MASK (0x0000FFFF) |
| |
| #define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_LSB (0) |
| #define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_WIDTH (14) |
| #define MM_EVENTGEN_GSM_BPI_BIAS_GSM_BPI_BIAS_MASK (0x00003FFF) |
| |
| #define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_LSB (0) |
| #define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_WIDTH (32) |
| #define MM_EVENTGEN_BPI_EVENT_STATUS_BPI_EVENT_STATUS_MASK (0xFFFFFFFF) |
| |
| #define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_LSB (0) |
| #define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_WIDTH (32) |
| #define MM_EVENTGEN_BPI_EVENT_STOP_BPI_EVENT_STOP_MASK (0xFFFFFFFF) |
| |
| #define MM_EVENTGEN_BPI_EVENT_MODE_LSB (29) |
| #define MM_EVENTGEN_BPI_EVENT_MODE_WIDTH (3) |
| #define MM_EVENTGEN_BPI_EVENT_MODE_MASK (0xE0000000) |
| |
| #define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_LSB (0) |
| #define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_WIDTH (20) |
| #define MM_EVENTGEN_BPI_EVENT_BPI_EVENT_TIME_MASK (0x000FFFFF) |
| |
| |
| #endif //#ifndef _CPH_RX_MM_EVENT_GEN_H_ |