| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
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| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
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| * |
| *****************************************************************************/ |
| |
| /***************************************************************************** |
| |
| FILE NAME: Cph1xsch.h |
| |
| DESCRIPTION: |
| |
| This include file provides searcher constants. |
| |
| *****************************************************************************/ |
| #ifndef _CPH1XSCH_H_ |
| #define _CPH1XSCH_H_ |
| |
| #include "kal_general_types.h" |
| |
| #if (defined(MTK_C2K_COSIM))||(defined(MTK_C2K_L1_TST)) |
| #define SR1X_MAX_PAGES 12 |
| #else |
| #define SR1X_MAX_PAGES 11 |
| #endif |
| /* default register assignment, TBD */ |
| #define DEFAULT_CTL_REG 0 |
| #define DEFAULT_CORR_REG 0 |
| #define DEFAULT_NCOH_REG 0 |
| #define DEFAULT_AUXPILOT_REG 0 |
| #define DEFAULT_WIN_REG 0 |
| #define DEFAULT_D1TH_REG 0 |
| #define DEFAULT_TEST_REG 0 |
| #define DEFAULT_OFFSET_REG 0 |
| |
| #define DWELL_LEN_MASK 0x3F |
| #define DWELL2_CORR_SHIFT 6 |
| #define DWELL2_CNT_SHIFT 6 |
| #define SR1X_SINGLE_BUF_SZ 1024 |
| #define SR1X_DOUBLE_BUF_SZ 2048 |
| |
| /* searcher constant */ |
| #define FULL_PN_CIR 32767 /* 2^15 - 1 */ |
| #define FULL_PN_CIR_2X 0 /* 2^16 = 0x10000 = (unit 16) 0 */ |
| #define SR1X_MAX_HITS 10 |
| #define DEFAULT_WIN_SIZ 32 |
| #define SR1X_SEARCHQ_SIZE 32 |
| #define SR1X_PN_BUF_SIZ 32 |
| #define SR1X_PN_BUF_SIZ_HALF (SR1X_PN_BUF_SIZ >> 1) |
| #define SR1X_CIAQ_WIN_SIZE 1 |
| #define SR1X_FFT_SIZE 128 |
| #define SR1X_FFT_BIN_WTH_HZ 600 |
| |
| /* Aflt Constant */ |
| #define SR1X_AFLT_SPY_PWR_BUF_SZ 55 // 1 + 3*10 + 3*8 |
| #define SR1X_AFLT_DBG_BUF_SZ (SYS_MAX_AFLT_LIST_PILOTS*9) |
| #define SR1X_AFLT_1CHIP_UNIT_IN_TC16 16 |
| #define SR1X_AFLT_1CHIP_MASK_IN_TC16 (1 * SR1X_AFLT_1CHIP_UNIT_IN_TC16 - 1) |
| #define SR1X_AFLT_2CHIP_MASK_IN_TC16 (2 * SR1X_AFLT_1CHIP_UNIT_IN_TC16 - 1) |
| #define SR1X_AFLT_3CHIP_MASK_IN_TC16 (3 * SR1X_AFLT_1CHIP_UNIT_IN_TC16 - 1) |
| |
| /* Different or Candidate Frequency Search */ |
| #define SR1X_CFS_SRCH_VALID_MSK 0xC000 |
| #define SR1X_CFS_RSLT_DBG_SZ 15 |
| |
| /** Input buffer test address, i.e. offset relative to input buffer start: valid value is 0~2047. */ |
| #define INBUF_TST_ADDR 0x0000 |
| |
| typedef enum |
| { |
| SCH_INPUT_SEL_C0A0, |
| SCH_INPUT_SEL_C0A1, |
| SCH_INPUT_SEL_C1A0, |
| SCH_INPUT_SEL_C1A1 |
| }SchInputSelT; |
| |
| typedef struct |
| { |
| SchInputSelT SchInputSel; |
| kal_uint32 SchCtrlRegVal; |
| kal_uint32 SchCorrRegVal; |
| kal_uint32 SchNCohRegVal; |
| kal_uint32 SchAuxPilotRegVal; |
| kal_uint32 SchD1ThreshRegVal; |
| kal_uint32 SchAuxOffRegVal; |
| kal_uint32 SchTestRegVal; |
| kal_uint32 SchTest2RegVal; |
| kal_uint32 SchCtrl2RegVal; |
| kal_uint32 SchStatusRegVal; |
| kal_uint32 SchThresRegVal; |
| kal_uint32 SchInBufTstCtrlRegVal; |
| kal_uint32 SchInBufTstDataRegVal; |
| }Cph1xSchHwCfgT; |
| |
| typedef struct |
| { |
| kal_uint32 SchStartPnOffset; |
| kal_uint32 SchWinSize; |
| }Cph1xSchWinCfgT; |
| |
| extern void Cph1xSchHwInit(kal_bool InitAll); |
| extern void Cph1xSchHwReset(kal_bool ResetAll); |
| extern void Cph1xSchHwCfg(Cph1xSchHwCfgT *AdsPtr); |
| extern void Cph1xSchWinCfg(kal_uint32 PnNum, Cph1xSchWinCfgT *AdsPtr); |
| extern void Cph1xSchFakeCfg(kal_bool Start); |
| extern void Cph1xSchDlyStartEnable(kal_bool Enable); |
| extern void Cph1xSchDlyStartTimeSet(kal_uint32 SysTime); |
| extern kal_uint8 Cph1xSchObfStateGet(void); |
| extern kal_uint8 Cph1xSchDoneStateGet(void); |
| extern void Cph1xSchDoneStateClr(void); |
| extern void Cph1xSchObfStateClr(void); |
| extern kal_uint8 Cph1xSchMemShareBitGet(void); |
| extern kal_bool Cph1xSchClockStateGet(void); |
| extern void Cph1xSchRsltRead(kal_bool InitialAcq, |
| kal_bool UseSorter, |
| kal_bool TimeDomain, |
| kal_uint8 SchMode, |
| kal_uint16 *Buf1Ptr, |
| kal_uint16 *Buf2Ptr); |
| extern void Cph1xSchIQDumpCfg(kal_uint16 StartOffset); |
| extern void Cph1xSchIQDump(kal_uint16 *BufPtr, kal_uint16 IQLength); |
| extern void Cph1xSchInputBufClr(void); |
| extern void Cph1xSchInputBufDump(void); |
| extern void Cph1xSchHwStallRegDump(void); |
| extern void Cph1xSchRegValDump(void); |
| #endif |