mcu/custom/service/nvram/nrrc_nvram_def.c

/*****************************************************************************
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#ifndef NVRAM_NOT_PRESENT

#ifdef __NR_RAT__
#include "kal_general_types.h"
#ifdef NVRAM_AUTO_GEN
#include "nvram_auto_gen.h"
#endif /* NVRAM_AUTO_GEN */

#include "nvram_enums.h"
#include "nvram_defs.h"

// LID Group Definition
#include "nrrc_nvram_def.h"
#include "nrrc_nvram_editor.h"

/********************************************
 *                  MACROS                  *
 ********************************************/


/********************************************
 *         TYPE DEFINITIONS & ENUMS         *
 ********************************************/


/********************************************
 *                VARIABLES                 *
 ********************************************/

// Default Values

nvram_ef_nr_cap_struct const NVRAM_EF_NR_CAP_DEFAULT[] =
{
    {
        0xF0, //nea_support
        0xF0, //nia_support
        0x00, //nras_power_class
#ifdef __ENDC__
        0x01  //endc_support
#else
        0x00  //endc_support
#endif
    }
};

nvram_ef_ue_nr_cap_struct const NVRAM_EF_UE_NR_CAP_DEFAULT[] =
{
    {
        { //mrdc_cap
            {  //general_params
#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
                { //common
                    0x01, //split_srb_with_one_ul_path
                    0x01, //split_drb_with_ul_both_mcg_scg
                    0x01, //srb3
                },
                { //fdd
                    0x00  //v2x_eutra
                },
                { //tdd
                    0x00  //v2x_eutra
                }
#else /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
                { //fdd
                    0x01, //split_srb_with_one_ul_path
                    0x01, //split_drb_with_ul_both_mcg_scg
                    0x01, //srb3
                    0x00  //v2x_eutra_v1530
                },
                { //tdd
                    0x01, //split_srb_with_one_ul_path
                    0x01, //split_drb_with_ul_both_mcg_scg
                    0x01, //srb3
                    0x00  //v2x_eutra_v1530
                }
#endif /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
            },
            { //pdcp_params
                0x01, //pdcp_duplication_split_srb
                0x01  //pdcp_duplication_split_drb
            }
        },
        { // nr_cap
            { //pdcp_params
                { //rohc_profiles
                    0x01, //profile_0x0001
                    0x01, //profile_0x0002
                    0x00, //profile_0x0003
                    0x01, //profile_0x0004
                    0x00, //profile_0x0006
                    0x00, //profile_0x0101
                    0x00, //profile_0x0102
                    0x00, //profile_0x0103
                    0x00  //profile_0x0104
                },
                16, //max_number_rohc_context_sessions
                0x00, //uplink_only_rohc_profiles
                0x00, //continue_rohc_context
                0x01, //out_of_order_delivery
                0x01, //short_sn
                0x01, //pdcp_duplication_srb
                0x01  //pdcp_duplication_mcg_or_scg_drb
            },
            { //rlc_params
                0x01, //am_with_short_sn
                0x01, //um_with_short_sn
                0x01  //um_with_long_sn
            },
            { //mac_params
                { //common
                    0x00, //lcp_restriction
                    0x00, //lch_to_scell_restriction
                    0x00, //recommended_bit_rate
                    0x00  //recommended_bit_rate_query
                },
                { //fdd
                    0x00, //skip_uplink_tx_dynamic
                    0x01, //logical_channel_sr_delay_timer
                    0x01, //long_drx_cycle
                    0x01, //short_drx_cycle
                    0x00, //multiple_sr_configurations
                    0x00  //multiple_configured_grants
                },
                { //tdd
                    0x00, //skip_uplink_tx_dynamic
                    0x01, //logical_channel_sr_delay_timer
                    0x01, //long_drx_cycle
                    0x01, //short_drx_cycle
                    0x00, //multiple_sr_configurations
                    0x00  //multiple_configured_grant_configurations
                }
            },
            { //meas_params
                { //common
                    0x01, //handover_fdd_tdd
                    0x01, //eutra_cgi_reporting
                    0x01  //nr_cgi_reporting
#if (CUR_MD_SPEC >= MD_SPEC_2019MAR)
                    ,0x01 //nr_cgi_reporting_endc
#endif /* (CUR_MD_SPEC >= MD_SPEC_2019MAR) */
                },
                { //fdd
                    0x01, //handover_inter_f
#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
                    0x01, //handover_lte_epc
                    0x00  //handover_lte_5gc
#else /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
                    0x01, //handover_lte
                    0x00  //handover_elte
#endif /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
                },
                { //tdd
                    0x01, //handover_inter_f
#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
                    0x01, //handover_lte_epc
                    0x00  //handover_lte_5gc
#else /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
                    0x01, //handover_lte
                    0x00  //handover_elte
#endif /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
                },
                { //fr1
                    0x01, //handover_inter_f
#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
                    0x01, //handover_lte_epc
                    0x00  //handover_lte_5gc
#else /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
                    0x01, //handover_lte
                    0x00  //handover_elte
#endif /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
                },
                { //fr2
                    0x01, //handover_inter_f
#if (CUR_MD_SPEC >= MD_SPEC_2019JUN)
                    0x01, //handover_lte_epc
                    0x00  //handover_lte_5gc
#else /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
                    0x01, //handover_lte
                    0x00  //handover_elte
#endif /* (CUR_MD_SPEC >= MD_SPEC_2019JUN) */
                }
            },
            { //ue_nr_capability_v1530
                { //inter_rat_params
                    { // eutra
                        { //common
                            0x01, //mfbi_eutra
                            0x01, //multi_ns_pmax_eutra
#ifdef __RS_SINR_MEAS_CAP__
                            0x01  //rs_sinr_meas_eutra
#else /* __RS_SINR_MEAS_CAP__ */
                            0x00  //rs_sinr_meas_eutra
#endif /* __RS_SINR_MEAS_CAP__ */
                        },
                        { //fdd
                            0x01  //rsrq_meas_wideband_eutra
                        },
                        { //tdd
                            0x01  //rsrq_meas_wideband_eutra
                        }
                    }
                },
                0x01, //inactive_state
            },
            { //ue_nr_capability_v1540
                { //sdap_params, the IE is changed to SBP configuration. To be removed.
                    0x01  //as_reflective_qos
                },
                { //ims_params
                    { //common
                        0x00  //voice_over_eutra_5gc
                    }
                },
            }
#if (CUR_MD_SPEC >= MD_SPEC_2019MAR)
            ,
            { //ue_nr_capability_v1550
                0x00  //reduced_cp_latency
            }
#endif /* (CUR_MD_SPEC >= MD_SPEC_2019MAR) */
        },
        0x00 // background_search_status_in_test_mode
    }
};

nvram_ef_nrrc_common_config_struct const NVRAM_EF_NRRC_COMMON_CONFIG_DEFAULT[] =
{
    {
        { //smart_idle
            0x3C,  //inactivity_timer_length
            0x12C, //inactivity_timer_length_drx
            0x00,  //fake_a2_report_sending_allowed
            0x3E8  //mru_oos_detection_timer_length
        },
        { //plmn_band_info
            { // plmn_band_list
                { // Record 1
                    {0x04, 0x06, 0x00, 0x00, 0x00, 0x0f}, // CMCC
                    { 3, 39, 40,  0,  0,  0,  0,  0,  0,  0}, // LTE bands
                    {41, 78, 79,  0,  0,  0,  0,  0,  0,  0}  // NR bands
                },
                { // Record 2
                    {0x04, 0x06, 0x00, 0x00, 0x03, 0x0f}, // CT
                    { 1,  3,  5,  8, 39, 40,  0,  0,  0,  0}, // LTE bands
                    { 1,  3,  5, 41, 78, 79,  0,  0,  0,  0}  // NR bands
                },
                { // Record 3
                    {0x04, 0x06, 0x00, 0x00, 0x01, 0x0f}, // CU
                    { 1,  3,  5,  8, 39, 40,  0,  0,  0,  0}, // LTE bands
                    { 1,  3,  8, 41, 78,  0,  0,  0,  0,  0}  // NR bands
                },
                { // Record 4
                    {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // unused
                    { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0}, // LTE bands
                    { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0}  // NR bands
                },
                { // Record 5
                    {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // unused
                    { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0}, // LTE bands
                    { 0,  0,  0,  0,  0,  0,  0,  0,  0,  0}  // NR bands
                }
            }
        },
        { //performance
            { //est_th
                0x0005, //srxlev
                0x0003  //squal
            }
        },
        {//meas_nl1mob_performance
            { //l4c_cus_bar_th
                0xFE28, //rsrp_th = -472 qdbm (-118dbm)
                0xFFD0  //rsrq_th = -48 qdb              
            },
            { //cus_qrxlevmin_adj
                0x00, //qrxlevmin_relax, defult 0 to NOT relax rxlevemin
                0xFFF1,  //rsrq_th = -15 db
                0xFFC7, //qrxlevmin_good = -57 (sib1 ie value; -114dbm = -456qdbm)
                0xFFCC //qrxlevmin_bad = -52 (sib1 ie value; -104dbm = -416qdbm)				
            },
            { //A3A4A5_ignore_th
                0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM, 0x20: A3 enable, 0x40: A4 enable, 0x80: A5 enable
                0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000  //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
            },
            { //A3A4A5_force_th
                0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM, 0x20: A3 enable, 0x40: A4 enable, 0x80: A5 enable
                0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000  //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
            },
            { //lte_B1_B2_ignore_th
                0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM, 0x40: B1 enable, 0x80: B2 enable
                0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000  //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
            },
            { //lte_B1_B2_ignore_th_serv_per_band_list
                {
                    {
                        //per_band_threshold[0]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[1]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[2]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[3]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[4]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000,  //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[5]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[6]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000,  //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[7]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[8]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000  //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    }
                }
            },
            { //lte_B1_B2_force_th
                0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM, 0x40: B1 enable, 0x80: B2 enable
                0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000  //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
            },
            { //lte_B1_B2_force_th_vonr
                0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM, 0x40: B1 enable, 0x80: B2 enable
                0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000  //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
            },
            { //lte_B1_B2_force_th_serv_per_band_list
                {
                    {
                        //per_band_threshold[0]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[1]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                            0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[2]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[3]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[4]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[5]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[6]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[7]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    },
                    {
                        //per_band_threshold[8]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000  //sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                    }
                }
            },
            { //nr_to_lte_resel_ignore_th
                0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM
                0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000  //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
            },
            { //nr_to_lte_resel_force_th
                0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable srv_th, 0x04: enable nbr_th, 0x08: disable on test SIM
                0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                0x8000, //nbr_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //nbr_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000  //nbr_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
            },
            0x0000,  // custom_enh_ind_update_period, unit: s , range: 3~65535, 0x0000: disable update
            { //ping_pong_parameter
                0xFF,  //ctrl_bmp, 0x01: enable pingpong_bar, 0x02: disable on test SIM
                0x12c, //ping-pong cell bar time(300s),      range: 60~600, disable: 0x8000
                0x14,  //ping-pong cell monitor period(20s), range: 10~30 , disable: 0x8000
                0x02,  //ping-pong hit count threshold,      range: 2~5   , disable: 0x80
            },
            { //nr_irat_ping_pong_parameter
                0xFF,  //ctrl_bmp, 0x01: enable nr irat pingpong_bar, 0x02: disable on test SIM
                0x12c, //irat ping-pong cell bar time(300s),      range: 60~600, disable: 0x8000
                0x3C,  //irat ping-pong cell monitor period(60s), range: 30~180, disable: 0x8000
                0x02,  //irat ping-pong hit count threshold,      range: 2~5   , disable: 0x80
            },
            { //a2_adjust_th
                0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable good_a2_rsrp_th, 0x04: enable bad_a2_rsrp_th, 0x08: disable on test SIM
                0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000            	
                0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
            	0x8000  //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
            },
            { //a2_adjust_th_vonr
                0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable good_a2_rsrp_th, 0x04: enable bad_a2_rsrp_th, 0x08: disable on test SIM
                0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000            	
                0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
            	0x8000  //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
            },
            { //a2_adjust_th_per_band_list
                {
                    {
                        //per_band_threshold[0]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                        0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                    },
                    {
                        //per_band_threshold[1]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                        0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                    },
                    {
                        //per_band_threshold[2]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                        0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                    },
                    {
                        //per_band_threshold[3]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                        0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                    },
                    {
                        //per_band_threshold[4]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                        0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                    },
                    {
                        //per_band_threshold[5]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                        0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                    },
                    {
                        //per_band_threshold[6]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                        0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                    },
                    {
                        //per_band_threshold[7]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                        0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                    },
                    {
                        //per_band_threshold[8]
                        0x0000, //band, range: 1~65535, disable: 0x0000
                        0x8000, //srv_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                        0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000
                        0x8000, //good_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                        0x8000  //bad_a2_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                    }
                }
            },
            { //cus_poor_sinr_th
                0xFFD8,  //sinr_th = -40 qdb
                0x3C,    //timer_th = 60 seconds 
                0x08     //sinr_hys = 8 qdb
            },
            { //A3A4A5_prefer_cell
                0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable th_for_offset, 0x04: enable th_for_ignore_rpt, 0x08: disable on test SIM, 0x20: A3 enable, 0x40: A4 enable, 0x80: A5 enable
                0xFF, //rpt_rsrp_offset, unit: qdBm, range: 0~40,  disable: 0xFF
                0x8000, //rsrp_th_for_offset, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //rsrq_th_for_offset, unit: qdB , range: -180~80, disable: 0x8000
                0x8000, //sinr_th_for_offset, unit: qdB , range: -100~160, disable: 0x8000
                0x8000, //rsrp_th_for_ignore_rpt, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //rsrq_th_for_ignore_rpt, unit: qdB , range: -180~80, disable: 0x8000
                0x8000  //sinr_th_for_ignore_rpt, unit: qdB , range: -100~160, disable: 0x8000
            },
            { //postpone_a2_for_b1b2
                0xFF, //ctrl_bmp, 0x01: disable on high speed, 0x02: enable a2_rsrp_th, 0x04: enable a2_rsrq_th, 0x08: disable on test SIM
                0x4B0, //timer_postpone_a2, unit: ms, default: 1200ms, disable: 0
                0xFE20, //srv_rsrp_th, unit: qdBm, range: -640~-120, default: -480, disable: 0x8000
                0x8000, //srv_rsrq_th, unit: qdB , range: -180~80, disable: 0x8000
                0x8000, //srv_sinr_th, unit: qdB , range: -100~160, disable: 0x8000 
            },
            { //nr_lte_prefer_rat_rsrp_th
                0xFF,  //ctrl_bmp, 0x01: enable nr_lte_prefer_rat_rsrp_th, 0x02: disable on test SIM
                0x8000, //nr_good_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //nr_bad_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
                0x8000, //lte_rsrp_th, unit: qdBm, range: -640~-120, disable: 0x8000
            },
            0xFE34 //game_nbr_bad_rsrp_th, unit: qdBm, range: -640~-120, default: -460, disable: 0x8000
        },
        { //scg_bar_info
            0x05,        //scg_bar_th
            0x1e,        //scg_bar_time (30second)
            0x0a         //bad_cell_watch_period (10 second)
        },
        { //ampr_mcc_list
            {0x03, 0x01, 0x00, 0xff, 0xff, 0xff}, // plmnid0:  310 xxx
            {0x03, 0x01, 0x01, 0xff, 0xff, 0xff}, // plmnid1:  311 xxx
            {0x03, 0x01, 0x02, 0xff, 0xff, 0xff}, // plmnid2:  312 xxx
            {0x03, 0x01, 0x03, 0xff, 0xff, 0xff}, // plmnid3:  313 xxx
            {0x03, 0x01, 0x04, 0xff, 0xff, 0xff}, // plmnid4:  314 xxx
            {0x03, 0x01, 0x05, 0xff, 0xff, 0xff}, // plmnid5:  315 xxx
            {0x03, 0x01, 0x06, 0xff, 0xff, 0xff}, // plmnid6:  316 xxx
            {0x03, 0x03, 0x00, 0xff, 0xff, 0xff}, // plmnid7:  330 xxx
            {0x03, 0x07, 0x06, 0xff, 0xff, 0xff}, // plmnid8:  376 xxx
            {0x05, 0x04, 0x04, 0xff, 0xff, 0xff}, // plmnid9:  544 xxx
            {0x03, 0x00, 0x02, 0xff, 0xff, 0xff}, // plmnid10: 302 xxx
            {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}  // plmnid11: xxx xxx
        },
        { //Connection establishment failure control parameters.
            0x04,  // Failure count (4)
            0x1E,  // Offset validity (30)
            0xFF   // Offset (infinity)
        },
        { //abnormal scenario recovery parameters
            0x03,  // offset counter(3)
            0x96,  // offset bar counter duration(150)
            0x12c, // offset bar_time(300)
            0x258, // offset monitor duration(600)
            0x02,  // nw_reject_with_long_wait_time_counter (2)
            0x3C,  // nw_reject_with_long_wait_time_monitoring_time (60)
            0x12c, // nw_reject_with_long_wait_time_bar_time (300)
            0x10   // nw_reject_with_long_wait_time_threshold (16)
        },
        { //nrrc_idle_param
            0x12c, // nr_tacless_bar_cell_timer (default: 300 seconds)
            { //nrrc_idle_custom_redir_param_info
                0x0, // offset_penalty (dB)
                0x0  // offset_time (s)
            }
        },
        { //nrrc_si_param
            {
               0x0,  // q_rx_lv_min.is_valid
               0x0,  // q_rx_lv_min.custom_val
               0x0,  // q_rx_lv_min.threshold_high
               0x0   // q_rx_lv_min.threshold_low
            },
            {
               0x0,  // q_qual_lv_min.is_valid
               0x0,  // q_qual_lv_min.custom_val
               0x0,  // q_qual_lv_min.threshold_high
               0x0   // q_qual_lv_min.threshold_low
            }
        },
        {//hst_cell_param
            0xFE48, //rsrp_th = -440 qdbm
            0xFFD8, //rsrq_th = -40 qdb
            0xFFEC  //sinr_th = -20 qdb
        }
    }
};

#ifdef __NVM_GLOBAL_CABC__
/* Record num from 0 to 200 */
nvram_nr_band_support_plmn_struct const NR_BAND_SUPPORT_PLMN_DEFAULT[] =
{
    { // Record 0
      // enable n3, n28, n41, n77 and n78 for KDDI
        {0x04, 0x04, 0x00, 0x05, 0x00, 0x0f}, // plmn_id
        // band_support_for_sa
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
        // band_support_for_endc
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
    },
    { // Record 1
      // enable n3, n28, n41, n77 and n78 for KDDI
        {0x04, 0x04, 0x00, 0x05, 0x01, 0x0f}, // plmn_id
        // band_support_for_sa
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
        // band_support_for_endc
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
    },
    { // Record 2
      // enable n3, n28, n41, n77 and n78 for KDDI
        {0x04, 0x04, 0x00, 0x05, 0x04, 0x0f}, // plmn_id
        // band_support_for_sa
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
        // band_support_for_endc
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
    },
    { // Record 3
      // Softbank has only following bands.  NR: n3, n28, n77
        {0x04, 0x04, 0x00, 0x00, 0x00, 0x0f}, // plmn_id
        // band_support_for_sa
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
        // band_support_for_endc
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
    },
    { // Record 4
      // Softbank has only following bands.  NR: n3, n28, n77
        {0x04, 0x04, 0x00, 0x02, 0x00, 0x0f}, // plmn_id
        // band_support_for_sa
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
        // band_support_for_endc
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
    },
    { // Record 5
      // Softbank has only following bands.  NR: n3, n28, n77      
        {0x04, 0x04, 0x01, 0x09, 0x00, 0x0f}, // plmn_id
        // band_support_for_sa
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
        // band_support_for_endc
        {0x04, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
    },
    { // Record 6
      // enable n78, n79, and n257 for SA under DoCoMo    
        {0x04, 0x04, 0x00, 0x01, 0x00, 0x0f}, // plmn_id
        // band_support_for_sa
        {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
        // band_support_for_endc (ENDC BC is not restricted)
        {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
         0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
         0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
         0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
         0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
         0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
         0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
         0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}
    }
};

void nvram_get_nrrc_default_value_to_write(nvram_lid_enum lid, kal_uint8 *buffer, kal_uint16 buffer_size)
{
    nvram_ef_nrrc_band_support_plmn_struct *p_nrrc_band_support_plmn = NULL;
    nvram_nr_band_support_plmn_struct *p_nvram_nr_band_support_plmn = NULL;
    const nvram_nr_band_support_plmn_struct *p_default_nr_band_support_plmn = NULL;
    kal_uint16 plmn_index = 0;
    kal_uint16 band_index = 0;
    buffer_size = buffer_size;

    switch (lid)
    {
        case NVRAM_EF_NRRC_BAND_SUPPORT_PLMN_LID:
            p_nrrc_band_support_plmn = (nvram_ef_nrrc_band_support_plmn_struct *)buffer;
            p_nrrc_band_support_plmn->feature_switch = KAL_TRUE;

            p_nrrc_band_support_plmn->num_of_plmn =
                sizeof(NR_BAND_SUPPORT_PLMN_DEFAULT)/sizeof(nvram_nr_band_support_plmn_struct);
            
            for (plmn_index = 0;
                 (plmn_index < p_nrrc_band_support_plmn->num_of_plmn) && (plmn_index < NVRAM_MAX_NR_BAND_SUPPORT_PLMN_NUM);
                 plmn_index++)
            {
                p_nvram_nr_band_support_plmn = &(p_nrrc_band_support_plmn->band_support_plmn[plmn_index]);
                p_default_nr_band_support_plmn = &(NR_BAND_SUPPORT_PLMN_DEFAULT[plmn_index]);

                p_nvram_nr_band_support_plmn->plmn_id.mcc1 = p_default_nr_band_support_plmn->plmn_id.mcc1;
                p_nvram_nr_band_support_plmn->plmn_id.mcc2 = p_default_nr_band_support_plmn->plmn_id.mcc2;
                p_nvram_nr_band_support_plmn->plmn_id.mcc3 = p_default_nr_band_support_plmn->plmn_id.mcc3;
                p_nvram_nr_band_support_plmn->plmn_id.mnc1 = p_default_nr_band_support_plmn->plmn_id.mnc1;
                p_nvram_nr_band_support_plmn->plmn_id.mnc2 = p_default_nr_band_support_plmn->plmn_id.mnc2;
                p_nvram_nr_band_support_plmn->plmn_id.mnc3 = p_default_nr_band_support_plmn->plmn_id.mnc3;

                for (band_index = 0; band_index < NVRAM_MAX_BYTE_NR_BAND_BITMASK; band_index++)
                {
                    p_nvram_nr_band_support_plmn->band_support_for_sa[band_index] =
                        p_default_nr_band_support_plmn->band_support_for_sa[band_index];
                    p_nvram_nr_band_support_plmn->band_support_for_endc[band_index] =
                        p_default_nr_band_support_plmn->band_support_for_endc[band_index];
                }
            }
            break;
        default:
            break;
    }
}
#endif /* __NVM_GLOBAL_CABC__ */

nvram_ef_nrrc_custom_endc_comb_list_struct const NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_DEFAULT[] =
{
    {
        "",  /* ENDC: white_list */
        "",  /* ENDC: black_list */
        "",  /* SA: white_list   */
        ""   /* SA: black_list   */
    }
};

nvram_ef_nrrc_nr_feature_ctrl_struct const NVRAM_EF_NRRC_NR_FEATURE_CTRL_DEFAULT[] =
{
    {
        {
         /* Byte 0 : bit [7..0]
          * bit 0: AT CMD control CDRX. 1 = enable, 0 = disable. (default: 1)
          * bit 1: Undefined
          * bit 2: Undefined
          * bit 3: Undefined
          * bit 4: Undefined
          * bit 5: Undefined
          * bit 6: Undefined
          * bit 7: Undefined
          */
         0x01,
         /* Byte 1 : bit [7..0]
          * bit 0: Undefined
          * bit 1: Undefined
          * bit 2: Undefined
          * bit 3: Undefined
          * bit 4: Undefined
          * bit 5: Undefined
          * bit 6: Undefined
          * bit 7: Reserved
          */
         0x00
        }
    }
};

static nvram_ef_nrrc_stored_operator_band_priority_struct const NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_DEFAULT[] = 
{
    /*operator_num*/
    0x00,
#if 0
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/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
/* under construction !*/
#endif
};


// LID Declaration
ltable_entry_struct logical_data_item_table_nrrc[] =
{
    {
        NVRAM_EF_UE_NR_CAP_LID,
        NVRAM_EF_UE_NR_CAP_TOTAL,
        NVRAM_EF_UE_NR_CAP_SIZE,
        NVRAM_NORMAL(NVRAM_EF_UE_NR_CAP_DEFAULT),
        NVRAM_CATEGORY_USER,
        NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
        "NR01",  // The first two characters of LID filename defined in nvram_enums.h
        VER(NVRAM_EF_UE_NR_CAP_LID)
    },
    {
        NVRAM_EF_NR_CAP_LID,
        NVRAM_EF_NR_CAP_TOTAL,
        NVRAM_EF_NR_CAP_SIZE,
        NVRAM_NORMAL(NVRAM_EF_NR_CAP_DEFAULT),
        NVRAM_CATEGORY_USER,
        NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
        "NR02",  // The first two characters of LID filename defined in nvram_enums.h
        VER(NVRAM_EF_NR_CAP_LID)
    },
    {
        NVRAM_EF_NR_STORED_INFO_LID,
        NVRAM_EF_NR_STORED_INFO_TOTAL,
        NVRAM_EF_NR_STORED_INFO_SIZE,
        NVRAM_NORMAL(NVRAM_EF_ZERO_DEFAULT),
        NVRAM_CATEGORY_USER,
        NVRAM_ATTR_OTA_RESET,
        "NR03",  // The first two characters of LID filename defined in nvram_enums.h
        VER(NVRAM_EF_NR_STORED_INFO_LID)
    },
    {
        NVRAM_EF_NRRC_COMMON_CONFIG_LID,
        NVRAM_EF_NRRC_COMMON_CONFIG_TOTAL,
        NVRAM_EF_NRRC_COMMON_CONFIG_SIZE,
        NVRAM_NORMAL(NVRAM_EF_NRRC_COMMON_CONFIG_DEFAULT),
        NVRAM_CATEGORY_USER,
        NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
        "NR04",  // The first two characters of LID filename defined in nvram_enums.h
        VER(NVRAM_EF_NRRC_COMMON_CONFIG_LID)
    },
#ifdef __NVM_GLOBAL_CABC__
    {
        NVRAM_EF_NRRC_BAND_SUPPORT_PLMN_LID,
        NVRAM_EF_NRRC_BAND_SUPPORT_PLMN_TOTAL,
        NVRAM_EF_NRRC_BAND_SUPPORT_PLMN_SIZE,
        NVRAM_DEFAULT_FUNC(nvram_get_nrrc_default_value_to_write),
        NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
        NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
        "NR08",                 // The first two characters of LID filename defined in nvram_enums.h
        VER(NVRAM_EF_NRRC_BAND_SUPPORT_PLMN_LID)
    },
#endif /* __NVM_GLOBAL_CABC__ */
    {
        NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_LID,
        NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_TOTAL,
        NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_SIZE,
        NVRAM_NORMAL(NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_DEFAULT),
        NVRAM_CATEGORY_USER,
        NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
        "NR06",     // The first two characters of LID filename defined in nvram_enums.h
        VER(NVRAM_EF_NRRC_CUSTOM_ENDC_COMB_LIST_LID)
    },
    {
        NVRAM_EF_NRRC_NR_FEATURE_CTRL_LID,
        NVRAM_EF_NRRC_NR_FEATURE_CTRL_TOTAL,
        NVRAM_EF_NRRC_NR_FEATURE_CTRL_SIZE,
        NVRAM_NORMAL(NVRAM_EF_NRRC_NR_FEATURE_CTRL_DEFAULT),
        NVRAM_CATEGORY_USER,
        NVRAM_ATTR_AVERAGE,
        "NR09",  // The first two characters of LID filename defined in nvram_enums.h
        VER(NVRAM_EF_NRRC_NR_FEATURE_CTRL_LID)
    },
	{
        NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_LID,
        NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_TOTAL,
        NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_SIZE,
        NVRAM_NORMAL(NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_DEFAULT),
        NVRAM_CATEGORY_USER,
        NVRAM_ATTR_AVERAGE | NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_MCF_OTA_BY_OP,
        "NR12",  // The first two characters of LID filename defined in nvram_enums.h
        VER(NVRAM_EF_NRRC_STORED_OPERATOR_BAND_PRIORITY_LID)
    },
    NVRAM_LTABLE_END
};

/********************************************
 *           FUNCTION DECLARATIONS          *
 ********************************************/


/********************************************
 *           FUNCTION DEFINITIONS           *
 ********************************************/

#endif /* __NR_RAT__ */

#endif /* NVRAM_NOT_PRESENT */