| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _CPH_DFESYS_GLBCON_CONFIG1_H_ |
| #define _CPH_DFESYS_GLBCON_CONFIG1_H_ |
| |
| |
| typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| |
| |
| #define DFESYS_GLB_CON_CONFIG1_REG_BASE (0xA8bd0000) |
| |
| #define DFESYS_GLB_CON_CONFIG1_end (DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0218 + 1*4) |
| |
| |
| |
| #define TXDFE_D_BSRP_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0008)) |
| #define TXDFE_D_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0010)) |
| #define TXDFE_D_F156M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0014)) |
| #define TXDFE_D_F26M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0018)) |
| #define TXDFE_D_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x001c)) |
| #define TPC_D_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0020)) |
| #define TPC_D_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0024)) |
| #define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0030)) |
| #define TDD_TTR_F6P5M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0040)) |
| #define LTE_TTR0_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0050)) |
| #define LTE_TTR1_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0054)) |
| #define LTE_TTR2_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0058)) |
| #define NR_TTR0_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0070)) |
| #define NR_TTR1_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0074)) |
| #define NR_TTR2_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0078)) |
| #define NR_TTR3_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x007c)) |
| #define SERDES_COS_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a0)) |
| #define SERDES_ACNT_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a4)) |
| #define SERDES_L3_TX_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a8)) |
| #define SERDES_L3_RX_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00ac)) |
| #define SERDES_MISC_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00b0)) |
| #define SERDES_GLB_OFF_BUS_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00b4)) |
| #define DIGRF_OFF_HW_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00bc)) |
| #define F312M_DEBUG_BUS ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c0)) |
| #define F312M_DEBUG_BUS2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c4)) |
| #define DFESYS_DEBUG_TRIG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c8)) |
| #define RXDFE_F312M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0100)) |
| #define RXDFE_F156M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0104)) |
| #define RXDFE_F26M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0108)) |
| #define SERDES_SWRST0_STARTB ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0200)) |
| #define SERDES_SWRST1_STARTB ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0204)) |
| #define DBG_FLAG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0208)) |
| #define DBG_TRIG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x020c)) |
| #define DFESYS_MAS_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0210)) |
| #define DFESYS_SLB_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0214)) |
| #define D_GDMA_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0218)) |
| |
| |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_LSB (6) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_WIDTH (1) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_MASK (0x00000040) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_BIT (0x00000040) |
| |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_LSB (5) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_WIDTH (1) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_MASK (0x00000020) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_BIT (0x00000020) |
| |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_LSB (4) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_WIDTH (1) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_MASK (0x00000010) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_BIT (0x00000010) |
| |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_LSB (3) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_WIDTH (1) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_MASK (0x00000008) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_BIT (0x00000008) |
| |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_LSB (2) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_WIDTH (1) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_MASK (0x00000004) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_BIT (0x00000004) |
| |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_LSB (1) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_WIDTH (1) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_MASK (0x00000002) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_BIT (0x00000002) |
| |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_LSB (0) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_WIDTH (1) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_MASK (0x00000001) |
| #define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_BIT (0x00000001) |
| |
| #define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_LSB (0) |
| #define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_WIDTH (1) |
| #define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_MASK (0x00000001) |
| #define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_BIT (0x00000001) |
| |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_LSB (6) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_WIDTH (1) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_MASK (0x00000040) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_BIT (0x00000040) |
| |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_LSB (5) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_WIDTH (1) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_MASK (0x00000020) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_BIT (0x00000020) |
| |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_LSB (4) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_WIDTH (1) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_MASK (0x00000010) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_BIT (0x00000010) |
| |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_LSB (3) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_WIDTH (1) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_MASK (0x00000008) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_BIT (0x00000008) |
| |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_LSB (2) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_WIDTH (1) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_MASK (0x00000004) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_BIT (0x00000004) |
| |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_LSB (1) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_WIDTH (1) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_MASK (0x00000002) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_BIT (0x00000002) |
| |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_LSB (0) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_WIDTH (1) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_MASK (0x00000001) |
| #define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_BIT (0x00000001) |
| |
| #define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_LSB (0) |
| #define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_WIDTH (1) |
| #define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_MASK (0x00000001) |
| #define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_BIT (0x00000001) |
| |
| #define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_LSB (0) |
| #define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_WIDTH (1) |
| #define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_MASK (0x00000001) |
| #define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_BIT (0x00000001) |
| |
| #define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_LSB (1) |
| #define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_WIDTH (1) |
| #define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_MASK (0x00000002) |
| #define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_BIT (0x00000002) |
| |
| #define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_LSB (0) |
| #define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_WIDTH (1) |
| #define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_MASK (0x00000001) |
| #define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_BIT (0x00000001) |
| |
| #define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_LSB (1) |
| #define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_WIDTH (1) |
| #define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_MASK (0x00000002) |
| #define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_BIT (0x00000002) |
| |
| #define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_LSB (0) |
| #define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_WIDTH (1) |
| #define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_MASK (0x00000001) |
| #define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_BIT (0x00000001) |
| |
| #define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_LSB (0) |
| #define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_WIDTH (1) |
| #define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_MASK (0x00000001) |
| #define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_BIT (0x00000001) |
| |
| #define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_LSB (0) |
| #define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_WIDTH (1) |
| #define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_MASK (0x00000001) |
| #define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_BIT (0x00000001) |
| |
| #define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_LSB (0) |
| #define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_WIDTH (1) |
| #define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_MASK (0x00000001) |
| #define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_BIT (0x00000001) |
| |
| #define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_LSB (0) |
| #define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_WIDTH (1) |
| #define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_MASK (0x00000001) |
| #define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_BIT (0x00000001) |
| |
| #define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_LSB (0) |
| #define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_WIDTH (1) |
| #define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_MASK (0x00000001) |
| #define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_BIT (0x00000001) |
| |
| #define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_LSB (0) |
| #define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_WIDTH (1) |
| #define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_MASK (0x00000001) |
| #define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_BIT (0x00000001) |
| |
| #define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_LSB (0) |
| #define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_WIDTH (1) |
| #define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_MASK (0x00000001) |
| #define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_BIT (0x00000001) |
| |
| #define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_LSB (0) |
| #define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_WIDTH (1) |
| #define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_MASK (0x00000001) |
| #define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_BIT (0x00000001) |
| |
| #define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_LSB (0) |
| #define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_WIDTH (1) |
| #define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_MASK (0x00000001) |
| #define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_BIT (0x00000001) |
| |
| #define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_LSB (0) |
| #define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_WIDTH (1) |
| #define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_MASK (0x00000001) |
| #define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_BIT (0x00000001) |
| |
| #define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_LSB (0) |
| #define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_WIDTH (1) |
| #define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_MASK (0x00000001) |
| #define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_BIT (0x00000001) |
| |
| #define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_LSB (0) |
| #define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_WIDTH (1) |
| #define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_MASK (0x00000001) |
| #define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_BIT (0x00000001) |
| |
| #define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_LSB (0) |
| #define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_WIDTH (1) |
| #define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_MASK (0x00000001) |
| #define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_BIT (0x00000001) |
| |
| #define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_LSB (0) |
| #define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_WIDTH (1) |
| #define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_MASK (0x00000001) |
| #define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_BIT (0x00000001) |
| |
| #define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_LSB (0) |
| #define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_WIDTH (1) |
| #define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_MASK (0x00000001) |
| #define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_BIT (0x00000001) |
| |
| #define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_LSB (0) |
| #define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_WIDTH (1) |
| #define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_MASK (0x00000001) |
| #define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_BIT (0x00000001) |
| |
| #define F312M_DEBUG_BUS_F312M_DEBUG_BUS_LSB (0) |
| #define F312M_DEBUG_BUS_F312M_DEBUG_BUS_WIDTH (32) |
| #define F312M_DEBUG_BUS_F312M_DEBUG_BUS_MASK (0xFFFFFFFF) |
| |
| #define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_LSB (0) |
| #define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_WIDTH (32) |
| #define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_MASK (0xFFFFFFFF) |
| |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_LSB (0) |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_WIDTH (5) |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_MASK (0x0000001F) |
| |
| #define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_LSB (0) |
| #define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_WIDTH (1) |
| #define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_MASK (0x00000001) |
| #define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_BIT (0x00000001) |
| |
| #define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_LSB (0) |
| #define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_WIDTH (1) |
| #define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_MASK (0x00000001) |
| #define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_BIT (0x00000001) |
| |
| #define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_LSB (0) |
| #define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_WIDTH (1) |
| #define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_MASK (0x00000001) |
| #define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_BIT (0x00000001) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_LSB (13) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_MASK (0x00002000) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_BIT (0x00002000) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_LSB (12) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_MASK (0x00001000) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_BIT (0x00001000) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_LSB (11) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_MASK (0x00000800) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_BIT (0x00000800) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_LSB (10) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_MASK (0x00000400) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_BIT (0x00000400) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_LSB (9) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_MASK (0x00000200) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_BIT (0x00000200) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_LSB (8) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_MASK (0x00000100) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_BIT (0x00000100) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_LSB (7) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_MASK (0x00000080) |
| #define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_BIT (0x00000080) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_LSB (6) |
| #define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_MASK (0x00000040) |
| #define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_BIT (0x00000040) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_LSB (5) |
| #define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_MASK (0x00000020) |
| #define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_BIT (0x00000020) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_LSB (4) |
| #define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_MASK (0x00000010) |
| #define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_BIT (0x00000010) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_LSB (3) |
| #define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_MASK (0x00000008) |
| #define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_BIT (0x00000008) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_LSB (2) |
| #define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_MASK (0x00000004) |
| #define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_BIT (0x00000004) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_LSB (1) |
| #define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_MASK (0x00000002) |
| #define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_BIT (0x00000002) |
| |
| #define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_LSB (0) |
| #define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_MASK (0x00000001) |
| #define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_BIT (0x00000001) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_LSB (15) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_MASK (0x00008000) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_BIT (0x00008000) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_LSB (14) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_MASK (0x00004000) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_BIT (0x00004000) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_LSB (13) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_MASK (0x00002000) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_BIT (0x00002000) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_LSB (12) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_MASK (0x00001000) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_BIT (0x00001000) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_LSB (11) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_MASK (0x00000800) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_BIT (0x00000800) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_LSB (10) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_MASK (0x00000400) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_BIT (0x00000400) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_LSB (9) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_MASK (0x00000200) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_BIT (0x00000200) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_LSB (8) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_MASK (0x00000100) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_BIT (0x00000100) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_LSB (7) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_MASK (0x00000080) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_BIT (0x00000080) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_LSB (6) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_MASK (0x00000040) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_BIT (0x00000040) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_LSB (5) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_MASK (0x00000020) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_BIT (0x00000020) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_LSB (4) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_MASK (0x00000010) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_BIT (0x00000010) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_LSB (3) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_MASK (0x00000008) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_BIT (0x00000008) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_LSB (2) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_MASK (0x00000004) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_BIT (0x00000004) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_LSB (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_MASK (0x00000002) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_BIT (0x00000002) |
| |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_LSB (0) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_WIDTH (1) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_MASK (0x00000001) |
| #define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_BIT (0x00000001) |
| |
| #define DBG_FLAG_SEL_DBG_FLAG3_SEL_LSB (24) |
| #define DBG_FLAG_SEL_DBG_FLAG3_SEL_WIDTH (8) |
| #define DBG_FLAG_SEL_DBG_FLAG3_SEL_MASK (0xFF000000) |
| |
| #define DBG_FLAG_SEL_DBG_FLAG2_SEL_LSB (16) |
| #define DBG_FLAG_SEL_DBG_FLAG2_SEL_WIDTH (8) |
| #define DBG_FLAG_SEL_DBG_FLAG2_SEL_MASK (0x00FF0000) |
| |
| #define DBG_FLAG_SEL_DBG_FLAG1_SEL_LSB (8) |
| #define DBG_FLAG_SEL_DBG_FLAG1_SEL_WIDTH (8) |
| #define DBG_FLAG_SEL_DBG_FLAG1_SEL_MASK (0x0000FF00) |
| |
| #define DBG_FLAG_SEL_DBG_FLAG0_SEL_LSB (0) |
| #define DBG_FLAG_SEL_DBG_FLAG0_SEL_WIDTH (8) |
| #define DBG_FLAG_SEL_DBG_FLAG0_SEL_MASK (0x000000FF) |
| |
| #define DBG_TRIG_SEL_DBG_TRIG_SEL_LSB (0) |
| #define DBG_TRIG_SEL_DBG_TRIG_SEL_WIDTH (8) |
| #define DBG_TRIG_SEL_DBG_TRIG_SEL_MASK (0x000000FF) |
| |
| #define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_LSB (0) |
| #define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_WIDTH (1) |
| #define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_MASK (0x00000001) |
| #define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_BIT (0x00000001) |
| |
| #define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_LSB (0) |
| #define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_WIDTH (1) |
| #define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_MASK (0x00000001) |
| #define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_BIT (0x00000001) |
| |
| #define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_LSB (0) |
| #define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_WIDTH (1) |
| #define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_MASK (0x00000001) |
| #define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_BIT (0x00000001) |
| |
| |
| #endif //#ifndef _EL1D_REG_ELBRUS_H_ |