| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _CPH_EVDO_TX_BRP_H_ |
| #define _CPH_EVDO_TX_BRP_H_ |
| |
| |
| |
| /*---------------------------------------------------------------------------- |
| Global Typedefs |
| ----------------------------------------------------------------------------*/ |
| |
| |
| typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| |
| #if defined(__MD93__)||defined(__MD95__) |
| #define TXBRP_EVDO_REG_BASE (0xa8018000) |
| #else |
| #define TXBRP_EVDO_REG_BASE (0xa8818000) |
| #endif |
| |
| #define TXBRP_EVDO_end (TXBRP_EVDO_REG_BASE + 0x0408 + 1*4) |
| |
| |
| |
| #define TXBRP_WORK_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0000)) |
| #define TXBRP_GLOBAL_IRQ ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0008)) |
| #define TXBRP_GLOBAL_IRQ_MASK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x000c)) |
| #define TXBRP_GLOBAL_IRQ_CLR ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0010)) |
| #define TXBRP_DO_IRQ ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0038)) |
| #define TXBRP_DO_IRQ_MASK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x003c)) |
| #define TXBRP_DO_IRQ_CLR ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0040)) |
| #define TXBRP_SW_CKEN ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0050)) |
| #define TXBRP_CLK_CTRLSEL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0054)) |
| #define TXBRP_DEBUG_REG_BANK_SEL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0058)) |
| #define TXBRP_MEM_TEST_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x005c)) |
| #define TXBRP_TRIGGER_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0060)) |
| #define TXBRP_DI_SWAP_EN ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0064)) |
| #define TXBRP_DI_TEST_CFG ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0068)) |
| #define TXBRP_I_REG_ULTRA_PRE_EN ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x006c)) |
| #define TXBRP_I_REG_BEGIN_ULTRA_CNT ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0070)) |
| #define TXBRP_I_REG_ULTRA_WATER_MARK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0074)) |
| #define TXBRP_DI_DEBUG ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0078)) |
| #define TXBRP_DEBUG_TRIG_SEL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x007c)) |
| #define TXBRP_DEBUG_0 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0080)) |
| #define TXBRP_DEBUG_1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0084)) |
| #define TXBRP_ENC_FSM_STATE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0090)) |
| #define TXBRP_CRC_DBG_FLAG ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0094)) |
| #define TXBRP_INTLV_B_LWT_ST_0 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0098)) |
| #define TXBRP_INTLV_B_LWT_ST_1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x009c)) |
| #define TXBRP_CTRL_FSM_STATE1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00a0)) |
| #define TXBRP_CTRL_FSM_STATE2 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00a4)) |
| #define TXBRP_RM_FSM_STATE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00a8)) |
| #define TXBRP_RUMAP_FSM_STATE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00ac)) |
| #define TXBRP_TEST_MODE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00c4)) |
| #define TXBRP_CRP_SW_READ_CTRL ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00c8)) |
| #define TXBRP_C2K_READ_RST ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00cc)) |
| #define TXBRP_EVDO_START ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x00ec)) |
| #define TXBRP_DO_TX_ENABLE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0110)) |
| #define TXBRP_DO_RRI_DATA_ACK0 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0114)) |
| #define TXBRP_DO_RRI_DATA_ACK1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0118)) |
| #define TXBRP_DO_RRI_DATA_ACK2 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x011c)) |
| #define TXBRP_DO_CHNL_TYPE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0124)) |
| #define TXBRP_DO_PROTOCOL_SUBTYP ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x012c)) |
| #define TXBRP_DO_TX_BYTE_SWAP ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0130)) |
| #define TXBRP_DO_TX_TEST3 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0134)) |
| #define TXBRP_EVDO_CHNL_BASE_ADDR ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x014c)) |
| #define TXBRP_DO_RRI_DATA_NAK ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0150)) |
| #define TXBRP_EVDO_CHNL_BASE_ADDR1 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0154)) |
| #define TXBRP_DO_INTERLACE ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0158)) |
| #define TXBRP_DBG_CRC32 ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x03bc)) |
| #define TXBRP_DBG_CRC32_RSLT_I ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x03c0)) |
| #define TXBRP_DBG_CRC32_RSLT_Q ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x03c4)) |
| #if defined(__MD93__)||defined(__MD95__) |
| #define TXBRP_EVDO_SUBTYPE2_HLARQ_RESULT ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0408)) |
| #else |
| #define TXBRP_EVDO_SUBTYPE2_HLARQ_RESULT ((APBADDR32)(TXBRP_EVDO_REG_BASE + 0x0404)) |
| #endif |
| |
| #define WORK_MODE_WORK_MODE_LSB (0) |
| #define WORK_MODE_WORK_MODE_WIDTH (5) |
| #define WORK_MODE_WORK_MODE_MASK (0x0000001F) |
| |
| #define GLOBAL_IRQ_DI_ERR_IRQ_LSB (3) |
| #define GLOBAL_IRQ_DI_ERR_IRQ_WIDTH (1) |
| #define GLOBAL_IRQ_DI_ERR_IRQ_MASK (0x00000008) |
| #define GLOBAL_IRQ_DI_ERR_IRQ_BIT (0x00000008) |
| |
| #define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_LSB (2) |
| #define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_WIDTH (1) |
| #define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_MASK (0x00000004) |
| #define GLOBAL_IRQ_MODE_REG_ADDR_MIS_IRQ_BIT (0x00000004) |
| |
| #define GLOBAL_IRQ_MODE_SWITCH_IRQ_LSB (1) |
| #define GLOBAL_IRQ_MODE_SWITCH_IRQ_WIDTH (1) |
| #define GLOBAL_IRQ_MODE_SWITCH_IRQ_MASK (0x00000002) |
| #define GLOBAL_IRQ_MODE_SWITCH_IRQ_BIT (0x00000002) |
| |
| #define GLOBAL_IRQ_MODE_IRQ_LSB (0) |
| #define GLOBAL_IRQ_MODE_IRQ_WIDTH (1) |
| #define GLOBAL_IRQ_MODE_IRQ_MASK (0x00000001) |
| #define GLOBAL_IRQ_MODE_IRQ_BIT (0x00000001) |
| |
| #define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_LSB (3) |
| #define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_WIDTH (1) |
| #define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_MASK (0x00000008) |
| #define GLOBAL_IRQ_MASK_DI_ERR_IRQ_MASK_BIT (0x00000008) |
| |
| #define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_LSB (2) |
| #define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_WIDTH (1) |
| #define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_MASK (0x00000004) |
| #define GLOBAL_IRQ_MASK_MODE_REG_ADDR_MIS_IRQ_MASK_BIT (0x00000004) |
| |
| #define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_LSB (1) |
| #define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_WIDTH (1) |
| #define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_MASK (0x00000002) |
| #define GLOBAL_IRQ_MASK_MODE_SWITCH_IRQ_MASK_BIT (0x00000002) |
| |
| #define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_LSB (0) |
| #define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_WIDTH (1) |
| #define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_MASK (0x00000001) |
| #define GLOBAL_IRQ_MASK_MODE_IRQ_MASK_BIT (0x00000001) |
| |
| #define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_LSB (3) |
| #define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_WIDTH (1) |
| #define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_MASK (0x00000008) |
| #define GLOBAL_IRQ_CLR_DI_ERR_IRQ_CLR_BIT (0x00000008) |
| |
| #define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_LSB (2) |
| #define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_WIDTH (1) |
| #define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_MASK (0x00000004) |
| #define GLOBAL_IRQ_CLR_MODE_REG_ADDR_MIS_IRQ_CLR_BIT (0x00000004) |
| |
| #define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_LSB (1) |
| #define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_WIDTH (1) |
| #define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_MASK (0x00000002) |
| #define GLOBAL_IRQ_CLR_MODE_SWITCH_IRQ_CLR_BIT (0x00000002) |
| |
| #define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_LSB (0) |
| #define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_WIDTH (1) |
| #define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_MASK (0x00000001) |
| #define GLOBAL_IRQ_CLR_MODE_IRQ_CLR_BIT (0x00000001) |
| |
| #define DO_IRQ_DO_TRIG_ERR_LSB (2) |
| #define DO_IRQ_DO_TRIG_ERR_WIDTH (1) |
| #define DO_IRQ_DO_TRIG_ERR_MASK (0x00000004) |
| #define DO_IRQ_DO_TRIG_ERR_BIT (0x00000004) |
| |
| #define DO_IRQ_DO_RD_ERR_LSB (1) |
| #define DO_IRQ_DO_RD_ERR_WIDTH (1) |
| #define DO_IRQ_DO_RD_ERR_MASK (0x00000002) |
| #define DO_IRQ_DO_RD_ERR_BIT (0x00000002) |
| |
| #define DO_IRQ_DO_DONE_LSB (0) |
| #define DO_IRQ_DO_DONE_WIDTH (1) |
| #define DO_IRQ_DO_DONE_MASK (0x00000001) |
| #define DO_IRQ_DO_DONE_BIT (0x00000001) |
| |
| #define DO_IRQ_MASK_DO_TRIG_ERR_MASK_LSB (2) |
| #define DO_IRQ_MASK_DO_TRIG_ERR_MASK_WIDTH (1) |
| #define DO_IRQ_MASK_DO_TRIG_ERR_MASK_MASK (0x00000004) |
| #define DO_IRQ_MASK_DO_TRIG_ERR_MASK_BIT (0x00000004) |
| |
| #define DO_IRQ_MASK_DO_RD_ERR_MASK_LSB (1) |
| #define DO_IRQ_MASK_DO_RD_ERR_MASK_WIDTH (1) |
| #define DO_IRQ_MASK_DO_RD_ERR_MASK_MASK (0x00000002) |
| #define DO_IRQ_MASK_DO_RD_ERR_MASK_BIT (0x00000002) |
| |
| #define DO_IRQ_MASK_DO_DONE_MASK_LSB (0) |
| #define DO_IRQ_MASK_DO_DONE_MASK_WIDTH (1) |
| #define DO_IRQ_MASK_DO_DONE_MASK_MASK (0x00000001) |
| #define DO_IRQ_MASK_DO_DONE_MASK_BIT (0x00000001) |
| |
| #define DO_IRQ_CLR_DO_TRIG_ERR_CLR_LSB (2) |
| #define DO_IRQ_CLR_DO_TRIG_ERR_CLR_WIDTH (1) |
| #define DO_IRQ_CLR_DO_TRIG_ERR_CLR_MASK (0x00000004) |
| #define DO_IRQ_CLR_DO_TRIG_ERR_CLR_BIT (0x00000004) |
| |
| #define DO_IRQ_CLR_DO_RD_ERR_CLR_LSB (1) |
| #define DO_IRQ_CLR_DO_RD_ERR_CLR_WIDTH (1) |
| #define DO_IRQ_CLR_DO_RD_ERR_CLR_MASK (0x00000002) |
| #define DO_IRQ_CLR_DO_RD_ERR_CLR_BIT (0x00000002) |
| |
| #define DO_IRQ_CLR_DO_DONE_CLR_LSB (0) |
| #define DO_IRQ_CLR_DO_DONE_CLR_WIDTH (1) |
| #define DO_IRQ_CLR_DO_DONE_CLR_MASK (0x00000001) |
| #define DO_IRQ_CLR_DO_DONE_CLR_BIT (0x00000001) |
| |
| #define TXBRP_SW_CKEN_APB_SW_CKEN_LSB (10) |
| #define TXBRP_SW_CKEN_APB_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_APB_SW_CKEN_MASK (0x00000400) |
| #define TXBRP_SW_CKEN_APB_SW_CKEN_BIT (0x00000400) |
| |
| #define TXBRP_SW_CKEN_OB_SW_CKEN_LSB (9) |
| #define TXBRP_SW_CKEN_OB_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_OB_SW_CKEN_MASK (0x00000200) |
| #define TXBRP_SW_CKEN_OB_SW_CKEN_BIT (0x00000200) |
| |
| #define TXBRP_SW_CKEN_RUMAP_SW_CKEN_LSB (8) |
| #define TXBRP_SW_CKEN_RUMAP_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_RUMAP_SW_CKEN_MASK (0x00000100) |
| #define TXBRP_SW_CKEN_RUMAP_SW_CKEN_BIT (0x00000100) |
| |
| #define TXBRP_SW_CKEN_INTL2_SW_CKEN_LSB (7) |
| #define TXBRP_SW_CKEN_INTL2_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_INTL2_SW_CKEN_MASK (0x00000080) |
| #define TXBRP_SW_CKEN_INTL2_SW_CKEN_BIT (0x00000080) |
| |
| #define TXBRP_SW_CKEN_INTL1_SW_CKEN_LSB (6) |
| #define TXBRP_SW_CKEN_INTL1_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_INTL1_SW_CKEN_MASK (0x00000040) |
| #define TXBRP_SW_CKEN_INTL1_SW_CKEN_BIT (0x00000040) |
| |
| #define TXBRP_SW_CKEN_SCR_SW_CKEN_LSB (5) |
| #define TXBRP_SW_CKEN_SCR_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_SCR_SW_CKEN_MASK (0x00000020) |
| #define TXBRP_SW_CKEN_SCR_SW_CKEN_BIT (0x00000020) |
| |
| #define TXBRP_SW_CKEN_RM_SW_CKEN_LSB (4) |
| #define TXBRP_SW_CKEN_RM_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_RM_SW_CKEN_MASK (0x00000010) |
| #define TXBRP_SW_CKEN_RM_SW_CKEN_BIT (0x00000010) |
| |
| #define TXBRP_SW_CKEN_ENC_SW_CKEN_LSB (3) |
| #define TXBRP_SW_CKEN_ENC_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_ENC_SW_CKEN_MASK (0x00000008) |
| #define TXBRP_SW_CKEN_ENC_SW_CKEN_BIT (0x00000008) |
| |
| #define TXBRP_SW_CKEN_CRC_SW_CKEN_LSB (2) |
| #define TXBRP_SW_CKEN_CRC_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_CRC_SW_CKEN_MASK (0x00000004) |
| #define TXBRP_SW_CKEN_CRC_SW_CKEN_BIT (0x00000004) |
| |
| #define TXBRP_SW_CKEN_DI_SW_CKEN_LSB (1) |
| #define TXBRP_SW_CKEN_DI_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_DI_SW_CKEN_MASK (0x00000002) |
| #define TXBRP_SW_CKEN_DI_SW_CKEN_BIT (0x00000002) |
| |
| #define TXBRP_SW_CKEN_TXBRP_SW_CKEN_LSB (0) |
| #define TXBRP_SW_CKEN_TXBRP_SW_CKEN_WIDTH (1) |
| #define TXBRP_SW_CKEN_TXBRP_SW_CKEN_MASK (0x00000001) |
| #define TXBRP_SW_CKEN_TXBRP_SW_CKEN_BIT (0x00000001) |
| |
| #define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_LSB (10) |
| #define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_MASK (0x00000400) |
| #define TXBRP_CLK_CTRLSEL_APB_CTRLSEL_BIT (0x00000400) |
| |
| #define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_LSB (9) |
| #define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_MASK (0x00000200) |
| #define TXBRP_CLK_CTRLSEL_OB_CTRLSEL_BIT (0x00000200) |
| |
| #define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_LSB (8) |
| #define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_MASK (0x00000100) |
| #define TXBRP_CLK_CTRLSEL_RUMAP_CTRLSEL_BIT (0x00000100) |
| |
| #define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_LSB (7) |
| #define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_MASK (0x00000080) |
| #define TXBRP_CLK_CTRLSEL_INTL2_CTRLSEL_BIT (0x00000080) |
| |
| #define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_LSB (6) |
| #define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_MASK (0x00000040) |
| #define TXBRP_CLK_CTRLSEL_INTL1_CTRLSEL_BIT (0x00000040) |
| |
| #define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_LSB (5) |
| #define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_MASK (0x00000020) |
| #define TXBRP_CLK_CTRLSEL_SCR_CTRLSEL_BIT (0x00000020) |
| |
| #define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_LSB (4) |
| #define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_MASK (0x00000010) |
| #define TXBRP_CLK_CTRLSEL_RM_CTRLSEL_BIT (0x00000010) |
| |
| #define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_LSB (3) |
| #define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_MASK (0x00000008) |
| #define TXBRP_CLK_CTRLSEL_ENC_CTRLSEL_BIT (0x00000008) |
| |
| #define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_LSB (2) |
| #define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_MASK (0x00000004) |
| #define TXBRP_CLK_CTRLSEL_CRC_CTRLSEL_BIT (0x00000004) |
| |
| #define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_LSB (1) |
| #define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_MASK (0x00000002) |
| #define TXBRP_CLK_CTRLSEL_DI_CTRLSEL_BIT (0x00000002) |
| |
| #define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_LSB (0) |
| #define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_WIDTH (1) |
| #define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_MASK (0x00000001) |
| #define TXBRP_CLK_CTRLSEL_TXBRP_CLK_CTRLSEL_BIT (0x00000001) |
| |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_LSB (24) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_WIDTH (8) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_3_MASK (0xFF000000) |
| |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_LSB (16) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_WIDTH (8) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_2_MASK (0x00FF0000) |
| |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_LSB (8) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_WIDTH (8) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_1_MASK (0x0000FF00) |
| |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_LSB (0) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_WIDTH (8) |
| #define DEBUG_REG_BANK_SEL_DEBUG_REG_BANK_SEL_0_MASK (0x000000FF) |
| |
| #define MEM_TEST_MODE_MEM_TEST_MODE_LSB (0) |
| #define MEM_TEST_MODE_MEM_TEST_MODE_WIDTH (1) |
| #define MEM_TEST_MODE_MEM_TEST_MODE_MASK (0x00000001) |
| #define MEM_TEST_MODE_MEM_TEST_MODE_BIT (0x00000001) |
| |
| #define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_LSB (1) |
| #define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_WIDTH (1) |
| #define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_MASK (0x00000002) |
| #define TXBRP_TRIGGER_MODE_TXBRP_trigger_enable_BIT (0x00000002) |
| |
| #define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_LSB (0) |
| #define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_WIDTH (1) |
| #define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_MASK (0x00000001) |
| #define TXBRP_TRIGGER_MODE_TXBRP_TRIGGER_MODE_BIT (0x00000001) |
| |
| #define DI_SWAP_EN_DI_SWAP_EN_LSB (0) |
| #define DI_SWAP_EN_DI_SWAP_EN_WIDTH (3) |
| #define DI_SWAP_EN_DI_SWAP_EN_MASK (0x00000007) |
| |
| #define DI_TEST_CFG_DI_TEST_MODE_EN_LSB (10) |
| #define DI_TEST_CFG_DI_TEST_MODE_EN_WIDTH (1) |
| #define DI_TEST_CFG_DI_TEST_MODE_EN_MASK (0x00000400) |
| #define DI_TEST_CFG_DI_TEST_MODE_EN_BIT (0x00000400) |
| |
| #define DI_TEST_CFG_DI_TEST_DATA_SEL_LSB (8) |
| #define DI_TEST_CFG_DI_TEST_DATA_SEL_WIDTH (2) |
| #define DI_TEST_CFG_DI_TEST_DATA_SEL_MASK (0x00000300) |
| |
| #define DI_TEST_CFG_DI_TEST_RAND_SEED_LSB (0) |
| #define DI_TEST_CFG_DI_TEST_RAND_SEED_WIDTH (8) |
| #define DI_TEST_CFG_DI_TEST_RAND_SEED_MASK (0x000000FF) |
| |
| #define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_LSB (0) |
| #define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_WIDTH (1) |
| #define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_MASK (0x00000001) |
| #define I_REG_ULTRA_PRE_EN_I_REG_ULTRA_PRE_EN_BIT (0x00000001) |
| |
| #define I_REG_BEGIN_ULTRA_CNT_I_REG_BEGIN_ULTRA_CNT_LSB (0) |
| #define I_REG_BEGIN_ULTRA_CNT_I_REG_BEGIN_ULTRA_CNT_WIDTH (3) |
| #define I_REG_BEGIN_ULTRA_CNT_I_REG_BEGIN_ULTRA_CNT_MASK (0x00000007) |
| |
| #define I_REG_ULTRA_WATER_MARK_I_REG_ULTRA_WATER_MARK_LSB (0) |
| #define I_REG_ULTRA_WATER_MARK_I_REG_ULTRA_WATER_MARK_WIDTH (3) |
| #define I_REG_ULTRA_WATER_MARK_I_REG_ULTRA_WATER_MARK_MASK (0x00000007) |
| |
| #define DI_DEBUG_DMA0_STATE_LSB (20) |
| #define DI_DEBUG_DMA0_STATE_WIDTH (2) |
| #define DI_DEBUG_DMA0_STATE_MASK (0x00300000) |
| |
| #define DI_DEBUG_RAM_RD_STATE_LSB (16) |
| #define DI_DEBUG_RAM_RD_STATE_WIDTH (2) |
| #define DI_DEBUG_RAM_RD_STATE_MASK (0x00030000) |
| |
| #define DI_DEBUG_O_DMA0_UTR_LSB (13) |
| #define DI_DEBUG_O_DMA0_UTR_WIDTH (1) |
| #define DI_DEBUG_O_DMA0_UTR_MASK (0x00002000) |
| #define DI_DEBUG_O_DMA0_UTR_BIT (0x00002000) |
| |
| #define DI_DEBUG_O_DMA0_PTR_UTR_LSB (12) |
| #define DI_DEBUG_O_DMA0_PTR_UTR_WIDTH (1) |
| #define DI_DEBUG_O_DMA0_PTR_UTR_MASK (0x00001000) |
| #define DI_DEBUG_O_DMA0_PTR_UTR_BIT (0x00001000) |
| |
| #define DI_DEBUG_O_DMA0_RD_REQ_LSB (10) |
| #define DI_DEBUG_O_DMA0_RD_REQ_WIDTH (1) |
| #define DI_DEBUG_O_DMA0_RD_REQ_MASK (0x00000400) |
| #define DI_DEBUG_O_DMA0_RD_REQ_BIT (0x00000400) |
| |
| #define DI_DEBUG_DMA_ALL_RDATA_DONE_LSB (9) |
| #define DI_DEBUG_DMA_ALL_RDATA_DONE_WIDTH (1) |
| #define DI_DEBUG_DMA_ALL_RDATA_DONE_MASK (0x00000200) |
| #define DI_DEBUG_DMA_ALL_RDATA_DONE_BIT (0x00000200) |
| |
| #define DI_DEBUG_RAM_FULL_LSB (8) |
| #define DI_DEBUG_RAM_FULL_WIDTH (1) |
| #define DI_DEBUG_RAM_FULL_MASK (0x00000100) |
| #define DI_DEBUG_RAM_FULL_BIT (0x00000100) |
| |
| #define DI_DEBUG_CHECK_DONE_LSB (7) |
| #define DI_DEBUG_CHECK_DONE_WIDTH (1) |
| #define DI_DEBUG_CHECK_DONE_MASK (0x00000080) |
| #define DI_DEBUG_CHECK_DONE_BIT (0x00000080) |
| |
| #define DI_DEBUG_DI_OUT_BIT_FINISH_LSB (6) |
| #define DI_DEBUG_DI_OUT_BIT_FINISH_WIDTH (1) |
| #define DI_DEBUG_DI_OUT_BIT_FINISH_MASK (0x00000040) |
| #define DI_DEBUG_DI_OUT_BIT_FINISH_BIT (0x00000040) |
| |
| #define DI_DEBUG_RAM_ALL_RDATA_READ_LSB (5) |
| #define DI_DEBUG_RAM_ALL_RDATA_READ_WIDTH (1) |
| #define DI_DEBUG_RAM_ALL_RDATA_READ_MASK (0x00000020) |
| #define DI_DEBUG_RAM_ALL_RDATA_READ_BIT (0x00000020) |
| |
| #define DI_DEBUG_DI_BUSY_LSB (4) |
| #define DI_DEBUG_DI_BUSY_WIDTH (1) |
| #define DI_DEBUG_DI_BUSY_MASK (0x00000010) |
| #define DI_DEBUG_DI_BUSY_BIT (0x00000010) |
| |
| #define DI_DEBUG_CRC_BUF_PING_EMPTY_LSB (3) |
| #define DI_DEBUG_CRC_BUF_PING_EMPTY_WIDTH (1) |
| #define DI_DEBUG_CRC_BUF_PING_EMPTY_MASK (0x00000008) |
| #define DI_DEBUG_CRC_BUF_PING_EMPTY_BIT (0x00000008) |
| |
| #define DI_DEBUG_CTC_BUF_PONG_EMPTY_LSB (2) |
| #define DI_DEBUG_CTC_BUF_PONG_EMPTY_WIDTH (1) |
| #define DI_DEBUG_CTC_BUF_PONG_EMPTY_MASK (0x00000004) |
| #define DI_DEBUG_CTC_BUF_PONG_EMPTY_BIT (0x00000004) |
| |
| #define DI_DEBUG_CRC_BUF_LOAD_SEL_LSB (1) |
| #define DI_DEBUG_CRC_BUF_LOAD_SEL_WIDTH (1) |
| #define DI_DEBUG_CRC_BUF_LOAD_SEL_MASK (0x00000002) |
| #define DI_DEBUG_CRC_BUF_LOAD_SEL_BIT (0x00000002) |
| |
| #define DI_DEBUG_CRC_BUF_OUT_SEL_LSB (0) |
| #define DI_DEBUG_CRC_BUF_OUT_SEL_WIDTH (1) |
| #define DI_DEBUG_CRC_BUF_OUT_SEL_MASK (0x00000001) |
| #define DI_DEBUG_CRC_BUF_OUT_SEL_BIT (0x00000001) |
| |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_LSB (8) |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_WIDTH (8) |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_1_MASK (0x0000FF00) |
| |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_LSB (0) |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_WIDTH (8) |
| #define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_0_MASK (0x000000FF) |
| |
| #define TXBRP_DEBUG_0_TXBRP_DEBUG_0_LSB (0) |
| #define TXBRP_DEBUG_0_TXBRP_DEBUG_0_WIDTH (32) |
| #define TXBRP_DEBUG_0_TXBRP_DEBUG_0_MASK (0xFFFFFFFF) |
| |
| #define TXBRP_DEBUG_1_TXBRP_DEBUG_1_LSB (0) |
| #define TXBRP_DEBUG_1_TXBRP_DEBUG_1_WIDTH (32) |
| #define TXBRP_DEBUG_1_TXBRP_DEBUG_1_MASK (0xFFFFFFFF) |
| |
| #define ENC_FSM_STATE_wt_conv_state_LSB (17) |
| #define ENC_FSM_STATE_wt_conv_state_WIDTH (3) |
| #define ENC_FSM_STATE_wt_conv_state_MASK (0x000E0000) |
| |
| #define ENC_FSM_STATE_lte_state_LSB (13) |
| #define ENC_FSM_STATE_lte_state_WIDTH (4) |
| #define ENC_FSM_STATE_lte_state_MASK (0x0001E000) |
| |
| #define ENC_FSM_STATE_codec_dis_state_LSB (10) |
| #define ENC_FSM_STATE_codec_dis_state_WIDTH (3) |
| #define ENC_FSM_STATE_codec_dis_state_MASK (0x00001C00) |
| |
| #define ENC_FSM_STATE_codec_en_state_LSB (6) |
| #define ENC_FSM_STATE_codec_en_state_WIDTH (4) |
| #define ENC_FSM_STATE_codec_en_state_MASK (0x000003C0) |
| |
| #define ENC_FSM_STATE_codec_w_state_LSB (3) |
| #define ENC_FSM_STATE_codec_w_state_WIDTH (3) |
| #define ENC_FSM_STATE_codec_w_state_MASK (0x00000038) |
| |
| #define ENC_FSM_STATE_codec_state_LSB (0) |
| #define ENC_FSM_STATE_codec_state_WIDTH (3) |
| #define ENC_FSM_STATE_codec_state_MASK (0x00000007) |
| |
| #define CRC_DBG_FLAG_crc_len_dbg_LSB (26) |
| #define CRC_DBG_FLAG_crc_len_dbg_WIDTH (5) |
| #define CRC_DBG_FLAG_crc_len_dbg_MASK (0x7C000000) |
| |
| #define CRC_DBG_FLAG_rtt_rc_idx_dbg_LSB (25) |
| #define CRC_DBG_FLAG_rtt_rc_idx_dbg_WIDTH (1) |
| #define CRC_DBG_FLAG_rtt_rc_idx_dbg_MASK (0x02000000) |
| #define CRC_DBG_FLAG_rtt_rc_idx_dbg_BIT (0x02000000) |
| |
| #define CRC_DBG_FLAG_cqi_or_data_dbg_LSB (24) |
| #define CRC_DBG_FLAG_cqi_or_data_dbg_WIDTH (1) |
| #define CRC_DBG_FLAG_cqi_or_data_dbg_MASK (0x01000000) |
| #define CRC_DBG_FLAG_cqi_or_data_dbg_BIT (0x01000000) |
| |
| #define CRC_DBG_FLAG_crc_state_dbg_LSB (16) |
| #define CRC_DBG_FLAG_crc_state_dbg_WIDTH (6) |
| #define CRC_DBG_FLAG_crc_state_dbg_MASK (0x003F0000) |
| |
| #define CRC_DBG_FLAG_bit_cnt_dbg_LSB (0) |
| #define CRC_DBG_FLAG_bit_cnt_dbg_WIDTH (15) |
| #define CRC_DBG_FLAG_bit_cnt_dbg_MASK (0x00007FFF) |
| |
| #define INTLV_B_LWT_ST_0_lte_wen_st_LSB (15) |
| #define INTLV_B_LWT_ST_0_lte_wen_st_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_lte_wen_st_MASK (0x00038000) |
| |
| #define INTLV_B_LWT_ST_0_ts_w_state_LSB (12) |
| #define INTLV_B_LWT_ST_0_ts_w_state_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_ts_w_state_MASK (0x00007000) |
| |
| #define INTLV_B_LWT_ST_0_ts_r_state_LSB (9) |
| #define INTLV_B_LWT_ST_0_ts_r_state_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_ts_r_state_MASK (0x00000E00) |
| |
| #define INTLV_B_LWT_ST_0_pp_w_state_upa_LSB (6) |
| #define INTLV_B_LWT_ST_0_pp_w_state_upa_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_pp_w_state_upa_MASK (0x000001C0) |
| |
| #define INTLV_B_LWT_ST_0_pp_w_state_dch_LSB (3) |
| #define INTLV_B_LWT_ST_0_pp_w_state_dch_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_pp_w_state_dch_MASK (0x00000038) |
| |
| #define INTLV_B_LWT_ST_0_sec_intlv_state_LSB (0) |
| #define INTLV_B_LWT_ST_0_sec_intlv_state_WIDTH (3) |
| #define INTLV_B_LWT_ST_0_sec_intlv_state_MASK (0x00000007) |
| |
| #define INTLV_B_LWT_ST_1_clm_cnt_LSB (25) |
| #define INTLV_B_LWT_ST_1_clm_cnt_WIDTH (5) |
| #define INTLV_B_LWT_ST_1_clm_cnt_MASK (0x3E000000) |
| |
| #define INTLV_B_LWT_ST_1_row_cnt_LSB (22) |
| #define INTLV_B_LWT_ST_1_row_cnt_WIDTH (3) |
| #define INTLV_B_LWT_ST_1_row_cnt_MASK (0x01C00000) |
| |
| #define INTLV_B_LWT_ST_1_blk_cnt_LSB (14) |
| #define INTLV_B_LWT_ST_1_blk_cnt_WIDTH (8) |
| #define INTLV_B_LWT_ST_1_blk_cnt_MASK (0x003FC000) |
| |
| #define INTLV_B_LWT_ST_1_sec_reqo_LSB (13) |
| #define INTLV_B_LWT_ST_1_sec_reqo_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_sec_reqo_MASK (0x00002000) |
| #define INTLV_B_LWT_ST_1_sec_reqo_BIT (0x00002000) |
| |
| #define INTLV_B_LWT_ST_1_ppr_req_upa_LSB (9) |
| #define INTLV_B_LWT_ST_1_ppr_req_upa_WIDTH (4) |
| #define INTLV_B_LWT_ST_1_ppr_req_upa_MASK (0x00001E00) |
| |
| #define INTLV_B_LWT_ST_1_ppr_read_done_upa_LSB (5) |
| #define INTLV_B_LWT_ST_1_ppr_read_done_upa_WIDTH (4) |
| #define INTLV_B_LWT_ST_1_ppr_read_done_upa_MASK (0x000001E0) |
| |
| #define INTLV_B_LWT_ST_1_second_intlv_done_upa_LSB (4) |
| #define INTLV_B_LWT_ST_1_second_intlv_done_upa_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_second_intlv_done_upa_MASK (0x00000010) |
| #define INTLV_B_LWT_ST_1_second_intlv_done_upa_BIT (0x00000010) |
| |
| #define INTLV_B_LWT_ST_1_ppr_req_dch_LSB (3) |
| #define INTLV_B_LWT_ST_1_ppr_req_dch_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_ppr_req_dch_MASK (0x00000008) |
| #define INTLV_B_LWT_ST_1_ppr_req_dch_BIT (0x00000008) |
| |
| #define INTLV_B_LWT_ST_1_ppr_read_done_dch_LSB (2) |
| #define INTLV_B_LWT_ST_1_ppr_read_done_dch_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_ppr_read_done_dch_MASK (0x00000004) |
| #define INTLV_B_LWT_ST_1_ppr_read_done_dch_BIT (0x00000004) |
| |
| #define INTLV_B_LWT_ST_1_second_intlv_done_dch_LSB (1) |
| #define INTLV_B_LWT_ST_1_second_intlv_done_dch_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_second_intlv_done_dch_MASK (0x00000002) |
| #define INTLV_B_LWT_ST_1_second_intlv_done_dch_BIT (0x00000002) |
| |
| #define INTLV_B_LWT_ST_1_dch_edch_mode_LSB (0) |
| #define INTLV_B_LWT_ST_1_dch_edch_mode_WIDTH (1) |
| #define INTLV_B_LWT_ST_1_dch_edch_mode_MASK (0x00000001) |
| #define INTLV_B_LWT_ST_1_dch_edch_mode_BIT (0x00000001) |
| |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_LSB (20) |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_WIDTH (6) |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_LTE_ST_MASK (0x03F00000) |
| |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_LSB (0) |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_WIDTH (20) |
| #define UTXBRP_CTRL_FSM_STATE1_UTXBRP_TOP_ST_MASK (0x000FFFFF) |
| |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_LSB (16) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_WIDTH (4) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_UT_ST_MASK (0x000F0000) |
| |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_LSB (7) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_WIDTH (9) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S2_ST_MASK (0x0000FF80) |
| |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_LSB (0) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_WIDTH (7) |
| #define UTXBRP_CTRL_FSM_STATE2_UTXBRP_S1_ST_MASK (0x0000007F) |
| |
| #define RM_FSM_STATE_BIT_SEP_STATE_LSB (16) |
| #define RM_FSM_STATE_BIT_SEP_STATE_WIDTH (3) |
| #define RM_FSM_STATE_BIT_SEP_STATE_MASK (0x00070000) |
| |
| #define RM_FSM_STATE_BC_STATE_LSB (0) |
| #define RM_FSM_STATE_BC_STATE_WIDTH (16) |
| #define RM_FSM_STATE_BC_STATE_MASK (0x0000FFFF) |
| |
| #define RUMAP_FSM_STATE_BUF_STATE_LSB (5) |
| #define RUMAP_FSM_STATE_BUF_STATE_WIDTH (1) |
| #define RUMAP_FSM_STATE_BUF_STATE_MASK (0x00000020) |
| #define RUMAP_FSM_STATE_BUF_STATE_BIT (0x00000020) |
| |
| #define RUMAP_FSM_STATE_RU_MAP_STATE_LSB (0) |
| #define RUMAP_FSM_STATE_RU_MAP_STATE_WIDTH (5) |
| #define RUMAP_FSM_STATE_RU_MAP_STATE_MASK (0x0000001F) |
| |
| #define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_LSB (1) |
| #define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_WIDTH (1) |
| #define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_MASK (0x00000002) |
| #define UTXBRP_TEST_MODE_UTXBRP_PWR_TEST_EN_BIT (0x00000002) |
| |
| #define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_LSB (0) |
| #define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_WIDTH (1) |
| #define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_MASK (0x00000001) |
| #define UTXBRP_TEST_MODE_UTXBRP_SELF_TEST_EN_BIT (0x00000001) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_LSB (13) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_WIDTH (2) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P4_MASK (0x00006000) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_LSB (11) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_WIDTH (2) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P3_MASK (0x00001800) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_LSB (9) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_WIDTH (2) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P2_MASK (0x00000600) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_LSB (7) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_WIDTH (2) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_P1_MASK (0x00000180) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_LSB (5) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_WIDTH (2) |
| #define CRP_SW_READ_CTRL_CRP_W_DATA_DCH_MASK (0x00000060) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_LSB (4) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_WIDTH (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_MASK (0x00000010) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P4_BIT (0x00000010) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_LSB (3) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_WIDTH (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_MASK (0x00000008) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P3_BIT (0x00000008) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_LSB (2) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_WIDTH (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_MASK (0x00000004) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P2_BIT (0x00000004) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_LSB (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_WIDTH (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_MASK (0x00000002) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_EDCH_P1_BIT (0x00000002) |
| |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_LSB (0) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_WIDTH (1) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_MASK (0x00000001) |
| #define CRP_SW_READ_CTRL_CRP_W_REQ_DCH_BIT (0x00000001) |
| |
| #define C2K_READ_RST_C2K_READ_RST_LSB (0) |
| #define C2K_READ_RST_C2K_READ_RST_WIDTH (1) |
| #define C2K_READ_RST_C2K_READ_RST_MASK (0x00000001) |
| #define C2K_READ_RST_C2K_READ_RST_BIT (0x00000001) |
| |
| #define EVDO_START_EVDO_START_LSB (0) |
| #define EVDO_START_EVDO_START_WIDTH (1) |
| #define EVDO_START_EVDO_START_MASK (0x00000001) |
| #define EVDO_START_EVDO_START_BIT (0x00000001) |
| |
| #define DO_TX_ENABLE_Transmitter_Enable_LSB (0) |
| #define DO_TX_ENABLE_Transmitter_Enable_WIDTH (1) |
| #define DO_TX_ENABLE_Transmitter_Enable_MASK (0x00000001) |
| #define DO_TX_ENABLE_Transmitter_Enable_BIT (0x00000001) |
| |
| #define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Payload_Index_LSB (3) |
| #define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Payload_Index_WIDTH (4) |
| #define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Payload_Index_MASK (0x00000078) |
| |
| #define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Channel_Rate_LSB (0) |
| #define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Channel_Rate_WIDTH (3) |
| #define DO_RRI_DATA_ACK0_DO_RRI_DATA_ACK0_Channel_Rate_MASK (0x00000007) |
| |
| #define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_Payload_Index_LSB (3) |
| #define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_Payload_Index_WIDTH (4) |
| #define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_Payload_Index_MASK (0x00000078) |
| |
| #define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_RRI_Symbol_rate_LSB (0) |
| #define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_RRI_Symbol_rate_WIDTH (3) |
| #define DO_RRI_DATA_ACK1_DO_RRI_DATA_ACK1_RRI_Symbol_rate_MASK (0x00000007) |
| |
| #define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_LSB (6) |
| #define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_WIDTH (1) |
| #define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_MASK (0x00000040) |
| #define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Reserved_BIT (0x00000040) |
| |
| #define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Payload_Index_LSB (2) |
| #define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Payload_Index_WIDTH (4) |
| #define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Payload_Index_MASK (0x0000003C) |
| |
| #define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Sub_packet_index_LSB (0) |
| #define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Sub_packet_index_WIDTH (2) |
| #define DO_RRI_DATA_ACK2_DO_RRI_DATA_ACK2_Sub_packet_index_MASK (0x00000003) |
| |
| #define DO_CHNL_TYPE_Channel_type_LSB (0) |
| #define DO_CHNL_TYPE_Channel_type_WIDTH (1) |
| #define DO_CHNL_TYPE_Channel_type_MASK (0x00000001) |
| #define DO_CHNL_TYPE_Channel_type_BIT (0x00000001) |
| |
| #define DO_PROTOCOL_SUBTYP_Protocol_Subtype_LSB (0) |
| #define DO_PROTOCOL_SUBTYP_Protocol_Subtype_WIDTH (1) |
| #define DO_PROTOCOL_SUBTYP_Protocol_Subtype_MASK (0x00000001) |
| #define DO_PROTOCOL_SUBTYP_Protocol_Subtype_BIT (0x00000001) |
| |
| #define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_LSB (0) |
| #define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_WIDTH (1) |
| #define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_MASK (0x00000001) |
| #define DO_TX_BYTE_SWAP_TXDO_Byte_Swap_BIT (0x00000001) |
| |
| #define DO_TX_TEST3_TX_ROW_ROT_LSB (0) |
| #define DO_TX_TEST3_TX_ROW_ROT_WIDTH (1) |
| #define DO_TX_TEST3_TX_ROW_ROT_MASK (0x00000001) |
| #define DO_TX_TEST3_TX_ROW_ROT_BIT (0x00000001) |
| |
| #define EVDO_CHNL_BASE_ADDR_EVDO_CHNL_BASE_ADDR_LSB (0) |
| #define EVDO_CHNL_BASE_ADDR_EVDO_CHNL_BASE_ADDR_WIDTH (32) |
| #define EVDO_CHNL_BASE_ADDR_EVDO_CHNL_BASE_ADDR_MASK (0xFFFFFFFF) |
| |
| #define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Payload_Index_LSB (2) |
| #define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Payload_Index_WIDTH (4) |
| #define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Payload_Index_MASK (0x0000003C) |
| |
| #define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Sub_packet_index_LSB (0) |
| #define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Sub_packet_index_WIDTH (2) |
| #define DO_RRI_DATA_NAK_DO_RRI_DATA_NAK_Sub_packet_index_MASK (0x00000003) |
| |
| #define EVDO_CHNL_BASE_ADDR1_EVDO_CHNL_BASE_ADDR1_LSB (0) |
| #define EVDO_CHNL_BASE_ADDR1_EVDO_CHNL_BASE_ADDR1_WIDTH (32) |
| #define EVDO_CHNL_BASE_ADDR1_EVDO_CHNL_BASE_ADDR1_MASK (0xFFFFFFFF) |
| |
| #define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_LSB (0) |
| #define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_WIDTH (1) |
| #define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_MASK (0x00000001) |
| #define EVDO_SUBTYPE2_HLARQ_RESULT_EVDO_SUBTYPE2_HLARQ_RESULT_BIT (0x00000001) |
| |
| |
| /***************************************************************************** |
| * End of File |
| *****************************************************************************/ |
| |
| |
| #endif //#ifndef _CPH_EVDO_TX_BRP_H_ |