| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _CPH_EVDO_TX_TIMER_H_ |
| #define _CPH_EVDO_TX_TIMER_H_ |
| |
| |
| typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| |
| #if defined(__MD93__)||defined(__MD95__) |
| #define DFE_W_TTR_DO_REG_BASE (0xA61B0000) |
| #else |
| #define DFE_W_TTR_DO_REG_BASE (0xA8190000) |
| #endif |
| #define DFE_W_TTR_end (DFE_W_TTR_DO_REG_BASE + 0x00F0) |
| |
| |
| #define TX_TIMER_DO_SR_OFFSET0 ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0000)) |
| #define TX_TIMER_DO_SR_OFFSET1 ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0004)) |
| #define TX_TIMER_DO_RX_TX_LOG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0050)) |
| #define TX_TIMER_DO_TX_TIME_MON2 ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0064)) |
| #define TX_TIMER_DO_FRAME_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0070)) |
| #define TX_TIMER_DO_TXRXDELAY ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0074)) |
| #define TX_TIMER_DO_RA_DLY ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0078)) |
| #define TX_TIMER_DO_CDO_TTR_CRP_WIN_ON ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0080)) |
| #define TX_TIMER_DO_CDO_TTR_CRP_WIN_OFF ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0084)) |
| #if defined(__MD93__)||defined(__MD95__) /* The registers deleted in 97E1, it is moved to Txdfe-die, configed by RFD */ |
| #define TX_TIMER_DO_CDO_TTR_TXDFE_WIN_ON_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0088)) |
| #define TX_TIMER_DO_CDO_TTR_TXDFE_WIN_OFF_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x008C)) |
| #endif |
| #define TX_TIMER_DO_CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0090)) |
| #define TX_TIMER_DO_CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0094)) |
| #if defined(__MD93__)||defined(__MD95__) /* The registers deleted in 97E1, it is moved to Txdfe-die, configed by RFD */ |
| #define TX_TIMER_DO_CDO_TTR_TXDAC_WIN_ON_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0098)) |
| #define TX_TIMER_DO_CDO_TTR_TXDAC_WIN_OFF_OFFSET ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x009C)) |
| #endif |
| #define TX_TIMER_DO_CDO_TTR_TXBRP_STR ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x00C0)) |
| #define TX_TIMER_DO_CDO_TTR_TXCRP_STR ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x00C4)) |
| #define TX_TIMER_DO_CDO_TTR_KS_STR ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x00C8)) |
| #if (!defined(__MD93__))&&(!defined(__MD95__)) |
| #define TX_TIMER_TTR_WIN_IMM_ON_OFF ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0100)) |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0110)) |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0114)) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0118)) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x011C)) |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0120)) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x0124)) |
| #define TX_TIMER_TTR_WIN_DBG ((APBADDR32)(DFE_W_TTR_DO_REG_BASE + 0x012c)) |
| #endif |
| |
| #define SR_Offset_SR_Offset_TRG_EN_LSB (20) |
| #define SR_Offset_SR_Offset_TRG_EN_WIDTH (1) |
| #define SR_Offset_SR_Offset_TRG_EN_MASK (0x00100000) |
| #define SR_Offset_SR_Offset_TRG_EN_BIT (0x00100000) |
| |
| #define SR_Offset_SR_Offset_LSB (0) |
| #define SR_Offset_SR_Offset_WIDTH (16) |
| #define SR_Offset_SR_Offset_MASK (0x0000FFFF) |
| |
| #define Frame_Offset_Frame_Offset_LSB (0) |
| #define Frame_Offset_Frame_Offset_WIDTH (20) |
| #define Frame_Offset_Frame_Offset_MASK (0x000FFFFF) |
| |
| #define TxRxDelay_TxRxDelay_LSB (0) |
| #define TxRxDelay_TxRxDelay_WIDTH (20) |
| #define TxRxDelay_TxRxDelay_MASK (0x000FFFFF) |
| |
| #define RA_Dly_TXCRP_FIFO_WIN_OFF_SUBCHIP_OFFSET_LSB (0) |
| #define RA_Dly_TXCRP_FIFO_WIN_OFF_SUBCHIP_OFFSET_WIDTH (3) |
| #define RA_Dly_TXCRP_FIFO_WIN_OFF_SUBCHIP_OFFSET_MASK (0x00000007) |
| |
| #define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_LSB (28) |
| #define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_WIDTH (1) |
| #define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_MASK (0x10000000) |
| #define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_CMPR_ON_BIT (0x10000000) |
| |
| #define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_LSB (20) |
| #define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_WIDTH (1) |
| #define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_MASK (0x00100000) |
| #define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_TRG_EN_BIT (0x00100000) |
| |
| #define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_LSB (0) |
| #define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_WIDTH (20) |
| #define CDO_TTR_CRP_WIN_ON_CRP_WIN_ON_MASK (0x000FFFFF) |
| |
| #define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_LSB (28) |
| #define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_WIDTH (1) |
| #define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_MASK (0x10000000) |
| #define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_CMPR_ON_BIT (0x10000000) |
| |
| #define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_LSB (20) |
| #define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_WIDTH (1) |
| #define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_MASK (0x00100000) |
| #define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_TRG_EN_BIT (0x00100000) |
| |
| #define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_LSB (0) |
| #define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_WIDTH (20) |
| #define CDO_TTR_CRP_WIN_OFF_CRP_WIN_OFF_MASK (0x000FFFFF) |
| |
| #if defined(__MD93__)||defined(__MD95__) |
| #define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_LSB (28) |
| #define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_WIDTH (1) |
| #define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_MASK (0x10000000) |
| #define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_CMPR_ON_BIT (0x10000000) |
| |
| #define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_LSB (20) |
| #define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_WIDTH (1) |
| #define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_MASK (0x00100000) |
| #define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_TRG_EN_BIT (0x00100000) |
| |
| #define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_SYSTEM_TIME_LSB (0) |
| #define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_SYSTEM_TIME_WIDTH (20) |
| #define CDO_TTR_TXDFE_WIN_ON_OFFSET_TXDFE_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF) |
| |
| #define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_LSB (28) |
| #define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_WIDTH (1) |
| #define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_MASK (0x10000000) |
| #define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_CMPR_ON_BIT (0x10000000) |
| |
| #define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_LSB (20) |
| #define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_WIDTH (1) |
| #define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_MASK (0x00100000) |
| #define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_TRG_EN_BIT (0x00100000) |
| |
| #define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_SYSTEM_TIME_LSB (0) |
| #define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_SYSTEM_TIME_WIDTH (12) |
| #define CDO_TTR_TXDFE_WIN_OFF_OFFSET_TXDFE_WIN_OFF_SYSTEM_TIME_MASK (0x00000FFF) |
| #endif |
| |
| #define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_LSB (28) |
| #define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_WIDTH (1) |
| #define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_MASK (0x10000000) |
| #define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_CMPR_ON_BIT (0x10000000) |
| |
| #define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_LSB (20) |
| #define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_WIDTH (1) |
| #define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_MASK (0x00100000) |
| #define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_TRG_EN_BIT (0x00100000) |
| |
| #define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_SYSTEM_TIME_LSB (0) |
| #define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_SYSTEM_TIME_WIDTH (20) |
| #define CDO_TTR_TXCRP_FIFO_WIN_ON_OFFSET_TXCRP_FIFO_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF) |
| |
| #define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_LSB (28) |
| #define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_WIDTH (1) |
| #define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_MASK (0x10000000) |
| #define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_CMPR_ON_BIT (0x10000000) |
| |
| #define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_LSB (20) |
| #define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_WIDTH (1) |
| #define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_MASK (0x00100000) |
| #define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_TRG_EN_BIT (0x00100000) |
| |
| #define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_LSB (0) |
| #define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_WIDTH (20) |
| #define CDO_TTR_TXCRP_FIFO_WIN_OFF_OFFSET_TXCRP_FIFO_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF) |
| |
| #if defined(__MD93__)||defined(__MD95__) |
| #define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_LSB (28) |
| #define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_WIDTH (1) |
| #define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_MASK (0x10000000) |
| #define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_CMPR_ON_BIT (0x10000000) |
| |
| #define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_LSB (20) |
| #define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_WIDTH (1) |
| #define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_MASK (0x00100000) |
| #define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_TRG_EN_BIT (0x00100000) |
| |
| #define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_SYSTEM_TIME_LSB (0) |
| #define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_SYSTEM_TIME_WIDTH (20) |
| #define CDO_TTR_TXDAC_WIN_ON_OFFSET_TXDAC_WIN_ON_SYSTEM_TIME_MASK (0x000FFFFF) |
| |
| #define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_LSB (28) |
| #define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_WIDTH (1) |
| #define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_MASK (0x10000000) |
| #define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_CMPR_ON_BIT (0x10000000) |
| |
| #define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_LSB (20) |
| #define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_WIDTH (1) |
| #define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_MASK (0x00100000) |
| #define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_TRG_EN_BIT (0x00100000) |
| |
| #define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_SYSTEM_TIME_LSB (0) |
| #define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_SYSTEM_TIME_WIDTH (20) |
| #define CDO_TTR_TXDAC_WIN_OFF_OFFSET_TXDAC_WIN_OFF_SYSTEM_TIME_MASK (0x000FFFFF) |
| #endif |
| |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_LSB (28) |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_WIDTH (1) |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_MASK (0x10000000) |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_CMPR_ON_BIT (0x10000000) |
| |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_LSB (22) |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_WIDTH (1) |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_MASK (0x00400000) |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_SINGLE_TRIGGER_BIT (0x00400000) |
| |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_AUTO_TRIGGER_LSB (20) |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_AUTO_TRIGGER_WIDTH (2) |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_AUTO_TRIGGER_MASK (0x00300000) |
| |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_SYSTEM_TIME_LSB (0) |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_SYSTEM_TIME_WIDTH (20) |
| #define CDO_TTR_TXBRP_STR_TXBRP_STR_SYSTEM_TIME_MASK (0x000FFFFF) |
| |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_LSB (28) |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_WIDTH (1) |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_MASK (0x10000000) |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_CMPR_ON_BIT (0x10000000) |
| |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_LSB (22) |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_WIDTH (1) |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_MASK (0x00400000) |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_SINGLE_TRIGGER_BIT (0x00400000) |
| |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_AUTO_TRIGGER_LSB (20) |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_AUTO_TRIGGER_WIDTH (2) |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_AUTO_TRIGGER_MASK (0x00300000) |
| |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_SYSTEM_TIME_LSB (0) |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_SYSTEM_TIME_WIDTH (12) |
| #define CDO_TTR_TXCRP_STR_TXCRP_STR_SYSTEM_TIME_MASK (0x00000FFF) |
| |
| |
| #define CDO_TTR_KS_STR_KS_STR_CMPR_ON_LSB (28) |
| #define CDO_TTR_KS_STR_KS_STR_CMPR_ON_WIDTH (1) |
| #define CDO_TTR_KS_STR_KS_STR_CMPR_ON_MASK (0x10000000) |
| #define CDO_TTR_KS_STR_KS_STR_CMPR_ON_BIT (0x10000000) |
| |
| #define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_LSB (22) |
| #define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_WIDTH (1) |
| #define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_MASK (0x00400000) |
| #define CDO_TTR_KS_STR_KS_STR_SINGLE_TRIGGER_BIT (0x00400000) |
| |
| #define CDO_TTR_KS_STR_KS_STR_AUTO_TRIGGER_LSB (20) |
| #define CDO_TTR_KS_STR_KS_STR_AUTO_TRIGGER_WIDTH (2) |
| #define CDO_TTR_KS_STR_KS_STR_AUTO_TRIGGER_MASK (0x00300000) |
| |
| |
| #define CDO_TTR_KS_STR_KS_STR_SYSTEM_TIME_LSB (0) |
| #define CDO_TTR_KS_STR_KS_STR_SYSTEM_TIME_WIDTH (12) |
| #define CDO_TTR_KS_STR_KS_STR_SYSTEM_TIME_MASK (0x00000FFF) |
| |
| #if (!defined(__MD93__))&&(!defined(__MD95__)) |
| #define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_LSB (1) |
| #define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_WIDTH (1) |
| #define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_MASK (0x00000002) |
| #define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_OFF_TRIG_BIT (0x00000002) |
| |
| #define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_LSB (0) |
| #define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_WIDTH (1) |
| #define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_MASK (0x00000001) |
| #define TX_TIMER_TTR_WIN_IMM_ON_OFF_TTR_WIN_IMM_ON_TRIG_BIT (0x00000001) |
| |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_LSB (1) |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_WIDTH (1) |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_MASK (0x00000002) |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_CMPR_ON_BIT (0x00000002) |
| |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_LSB (0) |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_WIDTH (1) |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_MASK (0x00000001) |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TRIG_TTR_WIN_SCH_ON_UCNT_TRIG_BIT (0x00000001) |
| |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_LSB (0) |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_WIDTH (32) |
| #define TX_TIMER_TTR_WIN_SCH_ON_UCNT_TTR_WIN_SCH_ON_UCNT_MASK (0xFFFFFFFF) |
| |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_LSB (1) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_WIDTH (1) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_MASK (0x00000002) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_CMPR_ON_BIT (0x00000002) |
| |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_LSB (0) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_WIDTH (1) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_MASK (0x00000001) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TRIG_TTR_WIN_SCH_OFF_UCNT_EN_BIT (0x00000001) |
| |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_LSB (0) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_WIDTH (32) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_UCNT_TTR_WIN_SCH_OFF_UCNT_MASK (0xFFFFFFFF) |
| |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_LSB (28) |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_WIDTH (1) |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_MASK (0x10000000) |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_CMPR_ON_BIT (0x10000000) |
| |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_LSB (27) |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_WIDTH (1) |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_MASK (0x08000000) |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_TRG_EN_BIT (0x08000000) |
| |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_LSB (0) |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_WIDTH (20) |
| #define TX_TIMER_TTR_WIN_SCH_ON_STIME_TTR_WIN_SCH_ON_SYSTEM_TIME_MASK (0x000FFFFF) |
| |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_LSB (28) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_WIDTH (1) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_MASK (0x10000000) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_CMPR_ON_BIT (0x10000000) |
| |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_LSB (27) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_WIDTH (1) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_MASK (0x08000000) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_TRG_EN_BIT (0x08000000) |
| |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_LSB (0) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_WIDTH (20) |
| #define TX_TIMER_TTR_WIN_SCH_OFF_STIME_TTR_WIN_SCH_OFF_SYSTEM_TIME_MASK (0x000FFFFF) |
| |
| #define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_LSB (0) |
| #define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_WIDTH (1) |
| #define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_MASK (0x00000001) |
| #define TX_TIMER_TTR_WIN_DBG_TTR_WIN_STATUS_BIT (0x00000001) |
| #endif |
| |
| #endif //#ifndef _CPH_EVDO_TX_TIMER_H_ |