| /***************************************************************************** |
| * Copyright Statement: |
| * -------------------- |
| * This software is protected by Copyright and the information contained |
| * herein is confidential. The software may not be copied and the information |
| * contained herein may not be used or disclosed except with the written |
| * permission of MediaTek Inc. (C) 2016 |
| * |
| * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| * |
| * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| * |
| * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| * |
| *****************************************************************************/ |
| #ifndef _CPH_RXBRP_BUS_CONFIG_H_ |
| #define _CPH_RXBRP_BUS_CONFIG_H_ |
| |
| |
| typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| |
| #if defined(__MD95__) |
| #define RXBRP_BUS_CONFIG_REG_BASE (0xAD160000) |
| #else |
| #define RXBRP_BUS_CONFIG_REG_BASE (0xAC960000) |
| #endif |
| |
| #define RXBRP_BUS_CONFIG_end (RXBRP_BUS_CONFIG_REG_BASE + 0x00a4 + 1*4) |
| |
| |
| |
| #define RXBRP_BUS_CONFIG0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0000)) |
| #define RXBRP_BUS_CONFIG1 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0004)) |
| #define RXBRP_BUS_CONFIG2 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0008)) |
| #define RXBRP_BUS_CONFIG3 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x000c)) |
| #define RXBRP_BUS_CONFIG4 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0010)) |
| #define RXBRP_BUS_CONFIG5 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0014)) |
| #define RXBRP_BUS_CONFIG6 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0018)) |
| #define RXBRP_BUS_CONFIG7 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x001c)) |
| #define RXBRP_BUS_CONFIG8 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0020)) |
| #define RXBRP_BUS_CONFIG9 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0024)) |
| #define RXBRP_BUS_CONFIG10 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0028)) |
| #define RXBRP_BUS_STATUS0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0030)) |
| #define RXBRP_BUS_STATUS1 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0034)) |
| #define RXBRP_BUS_STATUS2 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0038)) |
| #define RXBRP_BUS_CONFIG11 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0040)) |
| #define RXBRP_BUS_CONFIG12 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0044)) |
| #define RXBRP_BUS_CONFIG13 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0048)) |
| #define RXBRP_BUS_CONFIG14 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x004c)) |
| #define RXBRP_SLV_BUS_CONFIG0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x0080)) |
| #define RXBRP_SLV_BUS_STATUS0 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x00a0)) |
| #define RXBRP_SLV_BUS_STATUS1 ((APBADDR32)(RXBRP_BUS_CONFIG_REG_BASE + 0x00a4)) |
| |
| |
| #define RXBRP_BUS_CONFIG0_FLUSH_THRE_LSB (30) |
| #define RXBRP_BUS_CONFIG0_FLUSH_THRE_WIDTH (2) |
| #define RXBRP_BUS_CONFIG0_FLUSH_THRE_MASK (0xC0000000) |
| |
| #define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_LSB (29) |
| #define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_WIDTH (1) |
| #define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_MASK (0x20000000) |
| #define RXBRP_BUS_CONFIG0_MI_OSTD_EXT_EN_BIT (0x20000000) |
| |
| #define RXBRP_BUS_CONFIG0_MI_QOS_ON_LSB (28) |
| #define RXBRP_BUS_CONFIG0_MI_QOS_ON_WIDTH (1) |
| #define RXBRP_BUS_CONFIG0_MI_QOS_ON_MASK (0x10000000) |
| #define RXBRP_BUS_CONFIG0_MI_QOS_ON_BIT (0x10000000) |
| |
| #define RXBRP_BUS_CONFIG0_CG_DISABLE_LSB (27) |
| #define RXBRP_BUS_CONFIG0_CG_DISABLE_WIDTH (1) |
| #define RXBRP_BUS_CONFIG0_CG_DISABLE_MASK (0x08000000) |
| #define RXBRP_BUS_CONFIG0_CG_DISABLE_BIT (0x08000000) |
| |
| #define RXBRP_BUS_CONFIG0_DMA_MODE_LSB (26) |
| #define RXBRP_BUS_CONFIG0_DMA_MODE_WIDTH (1) |
| #define RXBRP_BUS_CONFIG0_DMA_MODE_MASK (0x04000000) |
| #define RXBRP_BUS_CONFIG0_DMA_MODE_BIT (0x04000000) |
| |
| #define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_LSB (25) |
| #define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_MASK (0x02000000) |
| #define RXBRP_BUS_CONFIG0_OST_EN_HRQ_W_W1_BIT (0x02000000) |
| |
| #define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_LSB (24) |
| #define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_MASK (0x01000000) |
| #define RXBRP_BUS_CONFIG0_OST_EN_HRQ_R_R1_BIT (0x01000000) |
| |
| #define RXBRP_BUS_CONFIG0_SPLIT_DIS_LSB (18) |
| #define RXBRP_BUS_CONFIG0_SPLIT_DIS_WIDTH (6) |
| #define RXBRP_BUS_CONFIG0_SPLIT_DIS_MASK (0x00FC0000) |
| |
| #define RXBRP_BUS_CONFIG0_CHNL_DISABLE_LSB (12) |
| #define RXBRP_BUS_CONFIG0_CHNL_DISABLE_WIDTH (6) |
| #define RXBRP_BUS_CONFIG0_CHNL_DISABLE_MASK (0x0003F000) |
| |
| #define RXBRP_BUS_CONFIG0_PRE_HIGH_PRIORITY_LSB (6) |
| #define RXBRP_BUS_CONFIG0_PRE_HIGH_PRIORITY_WIDTH (6) |
| #define RXBRP_BUS_CONFIG0_PRE_HIGH_PRIORITY_MASK (0x00000FC0) |
| |
| #define RXBRP_BUS_CONFIG0_HIGH_PRIORITY_LSB (0) |
| #define RXBRP_BUS_CONFIG0_HIGH_PRIORITY_WIDTH (6) |
| #define RXBRP_BUS_CONFIG0_HIGH_PRIORITY_MASK (0x0000003F) |
| |
| #define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_LSB (30) |
| #define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_WIDTH (1) |
| #define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_MASK (0x40000000) |
| #define RXBRP_BUS_CONFIG1_RG_OST_EN_TBO_BIT (0x40000000) |
| |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_LSB (29) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_MASK (0x20000000) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W1_BIT (0x20000000) |
| |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_LSB (28) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_WIDTH (1) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_MASK (0x10000000) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_W_BIT (0x10000000) |
| |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_LSB (27) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_MASK (0x08000000) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R1_BIT (0x08000000) |
| |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_LSB (26) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_WIDTH (1) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_MASK (0x04000000) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_LAST_EN_HRQ_R_BIT (0x04000000) |
| |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_LSB (25) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_MASK (0x02000000) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W1_BIT (0x02000000) |
| |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_LSB (24) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_WIDTH (1) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_MASK (0x01000000) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_W_BIT (0x01000000) |
| |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_LSB (23) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_MASK (0x00800000) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R1_BIT (0x00800000) |
| |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_LSB (22) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_WIDTH (1) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_MASK (0x00400000) |
| #define RXBRP_BUS_CONFIG1_HPRI_LAST_EN_HRQ_R_BIT (0x00400000) |
| |
| #define RXBRP_BUS_CONFIG1_RG_DBG_SEL_LSB (12) |
| #define RXBRP_BUS_CONFIG1_RG_DBG_SEL_WIDTH (8) |
| #define RXBRP_BUS_CONFIG1_RG_DBG_SEL_MASK (0x000FF000) |
| |
| #define RXBRP_BUS_CONFIG1_SLV_SYNC_SEL_LSB (10) |
| #define RXBRP_BUS_CONFIG1_SLV_SYNC_SEL_WIDTH (2) |
| #define RXBRP_BUS_CONFIG1_SLV_SYNC_SEL_MASK (0x00000C00) |
| |
| #define RXBRP_BUS_CONFIG1_MST_SYNC_SEL_LSB (8) |
| #define RXBRP_BUS_CONFIG1_MST_SYNC_SEL_WIDTH (2) |
| #define RXBRP_BUS_CONFIG1_MST_SYNC_SEL_MASK (0x00000300) |
| |
| #define RXBRP_BUS_CONFIG1_RXBRP_TOP_DBG_SEL_LSB (2) |
| #define RXBRP_BUS_CONFIG1_RXBRP_TOP_DBG_SEL_WIDTH (4) |
| #define RXBRP_BUS_CONFIG1_RXBRP_TOP_DBG_SEL_MASK (0x0000003C) |
| |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_LSB (1) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_WIDTH (1) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_MASK (0x00000002) |
| #define RXBRP_BUS_CONFIG1_PRE_HPRI_DIS_BIT (0x00000002) |
| |
| #define RXBRP_BUS_CONFIG1_HPRI_DIS_LSB (0) |
| #define RXBRP_BUS_CONFIG1_HPRI_DIS_WIDTH (1) |
| #define RXBRP_BUS_CONFIG1_HPRI_DIS_MASK (0x00000001) |
| #define RXBRP_BUS_CONFIG1_HPRI_DIS_BIT (0x00000001) |
| |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_LSB (23) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_MASK (0x00800000) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W1_BIT (0x00800000) |
| |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_LSB (22) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_MASK (0x00400000) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_W_BIT (0x00400000) |
| |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_LSB (21) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_MASK (0x00200000) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R1_BIT (0x00200000) |
| |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_LSB (20) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_MASK (0x00100000) |
| #define RXBRP_BUS_CONFIG2_AUTO_BW_LIMIT_EN_HARQ_R_BIT (0x00100000) |
| |
| #define RXBRP_BUS_CONFIG2_RG_ERROR_FLAG_SELECT_LSB (18) |
| #define RXBRP_BUS_CONFIG2_RG_ERROR_FLAG_SELECT_WIDTH (2) |
| #define RXBRP_BUS_CONFIG2_RG_ERROR_FLAG_SELECT_MASK (0x000C0000) |
| |
| #define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_LSB (17) |
| #define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_MASK (0x00020000) |
| #define RXBRP_BUS_CONFIG2_RG_RESET_ERROR_FLAG_BIT (0x00020000) |
| |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_LSB (16) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_MASK (0x00010000) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W1_BIT (0x00010000) |
| |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_LSB (15) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_MASK (0x00008000) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_W_BIT (0x00008000) |
| |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_LSB (14) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_MASK (0x00004000) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R1_BIT (0x00004000) |
| |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_LSB (13) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_MASK (0x00002000) |
| #define RXBRP_BUS_CONFIG2_REG_LATCH_MODE_R_BIT (0x00002000) |
| |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_LSB (12) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_MASK (0x00001000) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W1_BIT (0x00001000) |
| |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_LSB (11) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_MASK (0x00000800) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_W_BIT (0x00000800) |
| |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_LSB (10) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_MASK (0x00000400) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R1_BIT (0x00000400) |
| |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_LSB (9) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_MASK (0x00000200) |
| #define RXBRP_BUS_CONFIG2_USE_HARQ_MODE_R_BIT (0x00000200) |
| |
| #define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_LSB (8) |
| #define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_MASK (0x00000100) |
| #define RXBRP_BUS_CONFIG2_GALS_SW_ERR_RST_BIT (0x00000100) |
| |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_LSB (7) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_MASK (0x00000080) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W1_BIT (0x00000080) |
| |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_LSB (6) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_MASK (0x00000040) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_W_BIT (0x00000040) |
| |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_LSB (5) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_MASK (0x00000020) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R1_BIT (0x00000020) |
| |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_LSB (4) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_MASK (0x00000010) |
| #define RXBRP_BUS_CONFIG2_FORCE_HRQ_DROP_R_BIT (0x00000010) |
| |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_LSB (3) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_MASK (0x00000008) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W1_BIT (0x00000008) |
| |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_LSB (2) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_MASK (0x00000004) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_W_BIT (0x00000004) |
| |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_LSB (1) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_MASK (0x00000002) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R1_BIT (0x00000002) |
| |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_LSB (0) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_WIDTH (1) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_MASK (0x00000001) |
| #define RXBRP_BUS_CONFIG2_BANDWIDTH_LIMIT_EN_HRQ_R_BIT (0x00000001) |
| |
| #define RXBRP_BUS_CONFIG3_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R_LSB (0) |
| #define RXBRP_BUS_CONFIG3_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R_WIDTH (32) |
| #define RXBRP_BUS_CONFIG3_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_CONFIG4_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R1_LSB (0) |
| #define RXBRP_BUS_CONFIG4_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R1_WIDTH (32) |
| #define RXBRP_BUS_CONFIG4_BANDWIDTH_LIMIT_THRESHOLD_HRQ_R1_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_CONFIG5_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W_LSB (0) |
| #define RXBRP_BUS_CONFIG5_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W_WIDTH (32) |
| #define RXBRP_BUS_CONFIG5_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_CONFIG6_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W1_LSB (0) |
| #define RXBRP_BUS_CONFIG6_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W1_WIDTH (32) |
| #define RXBRP_BUS_CONFIG6_BANDWIDTH_LIMIT_THRESHOLD_HRQ_W1_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_CONFIG7_AUTO_BW_LIMIT_THRESHOLD_R_SRT_THRO_LSB (0) |
| #define RXBRP_BUS_CONFIG7_AUTO_BW_LIMIT_THRESHOLD_R_SRT_THRO_WIDTH (32) |
| #define RXBRP_BUS_CONFIG7_AUTO_BW_LIMIT_THRESHOLD_R_SRT_THRO_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_CONFIG8_AUTO_BW_LIMIT_THRESHOLD_W_SRT_THRO_LSB (0) |
| #define RXBRP_BUS_CONFIG8_AUTO_BW_LIMIT_THRESHOLD_W_SRT_THRO_WIDTH (32) |
| #define RXBRP_BUS_CONFIG8_AUTO_BW_LIMIT_THRESHOLD_W_SRT_THRO_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_CONFIG9_AUTO_BW_LIMIT_THRESHOLD_R1_SRT_THRO_LSB (0) |
| #define RXBRP_BUS_CONFIG9_AUTO_BW_LIMIT_THRESHOLD_R1_SRT_THRO_WIDTH (32) |
| #define RXBRP_BUS_CONFIG9_AUTO_BW_LIMIT_THRESHOLD_R1_SRT_THRO_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_CONFIG10_AUTO_BW_LIMIT_THRESHOLD_W1_SRT_THRO_LSB (0) |
| #define RXBRP_BUS_CONFIG10_AUTO_BW_LIMIT_THRESHOLD_W1_SRT_THRO_WIDTH (32) |
| #define RXBRP_BUS_CONFIG10_AUTO_BW_LIMIT_THRESHOLD_W1_SRT_THRO_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_STATUS0_STA0_LSB (0) |
| #define RXBRP_BUS_STATUS0_STA0_WIDTH (32) |
| #define RXBRP_BUS_STATUS0_STA0_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_STATUS1_STA1_LSB (0) |
| #define RXBRP_BUS_STATUS1_STA1_WIDTH (32) |
| #define RXBRP_BUS_STATUS1_STA1_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_STATUS2_STA2_LSB (0) |
| #define RXBRP_BUS_STATUS2_STA2_WIDTH (32) |
| #define RXBRP_BUS_STATUS2_STA2_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_CONFIG11_AUTO_BW_LIMIT_THRESHOLD_R_BW_STATUS_LSB (0) |
| #define RXBRP_BUS_CONFIG11_AUTO_BW_LIMIT_THRESHOLD_R_BW_STATUS_WIDTH (32) |
| #define RXBRP_BUS_CONFIG11_AUTO_BW_LIMIT_THRESHOLD_R_BW_STATUS_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_CONFIG12_AUTO_BW_LIMIT_THRESHOLD_W_BW_STATUS_LSB (0) |
| #define RXBRP_BUS_CONFIG12_AUTO_BW_LIMIT_THRESHOLD_W_BW_STATUS_WIDTH (32) |
| #define RXBRP_BUS_CONFIG12_AUTO_BW_LIMIT_THRESHOLD_W_BW_STATUS_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_CONFIG13_AUTO_BW_LIMIT_THRESHOLD_R1_BW_STATUS_LSB (0) |
| #define RXBRP_BUS_CONFIG13_AUTO_BW_LIMIT_THRESHOLD_R1_BW_STATUS_WIDTH (32) |
| #define RXBRP_BUS_CONFIG13_AUTO_BW_LIMIT_THRESHOLD_R1_BW_STATUS_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_BUS_CONFIG14_AUTO_BW_LIMIT_THRESHOLD_W1_BW_STATUS_LSB (0) |
| #define RXBRP_BUS_CONFIG14_AUTO_BW_LIMIT_THRESHOLD_W1_BW_STATUS_WIDTH (32) |
| #define RXBRP_BUS_CONFIG14_AUTO_BW_LIMIT_THRESHOLD_W1_BW_STATUS_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_LSB (5) |
| #define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_WIDTH (1) |
| #define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_MASK (0x00000020) |
| #define RXBRP_SLV_BUS_CONFIG0_SCQ_AXI2SRAM_BFABLE_EN_BIT (0x00000020) |
| |
| #define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_LSB (4) |
| #define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_WIDTH (1) |
| #define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_MASK (0x00000010) |
| #define RXBRP_SLV_BUS_CONFIG0_BUS_PWR_AWARE_EN_BIT (0x00000010) |
| |
| #define RXBRP_SLV_BUS_CONFIG0_SLV_SYNC_SEL_LSB (2) |
| #define RXBRP_SLV_BUS_CONFIG0_SLV_SYNC_SEL_WIDTH (2) |
| #define RXBRP_SLV_BUS_CONFIG0_SLV_SYNC_SEL_MASK (0x0000000C) |
| |
| #define RXBRP_SLV_BUS_CONFIG0_MST_SYNC_SEL_LSB (0) |
| #define RXBRP_SLV_BUS_CONFIG0_MST_SYNC_SEL_WIDTH (2) |
| #define RXBRP_SLV_BUS_CONFIG0_MST_SYNC_SEL_MASK (0x00000003) |
| |
| #define RXBRP_SLV_BUS_STATUS0_STA0_LSB (0) |
| #define RXBRP_SLV_BUS_STATUS0_STA0_WIDTH (32) |
| #define RXBRP_SLV_BUS_STATUS0_STA0_MASK (0xFFFFFFFF) |
| |
| #define RXBRP_SLV_BUS_STATUS1_STA1_LSB (0) |
| #define RXBRP_SLV_BUS_STATUS1_STA1_WIDTH (1) |
| #define RXBRP_SLV_BUS_STATUS1_STA1_MASK (0x00000001) |
| #define RXBRP_SLV_BUS_STATUS1_STA1_BIT (0x00000001) |
| |
| |
| #endif //#ifndef _CPH_RXBRP_BUS_CONFIG_H_ |