| #ifndef __L5_NVRAM_DEF_H__ |
| #define __L5_NVRAM_DEF_H__ |
| |
| #ifdef __cplusplus |
| extern "C" |
| { |
| #endif /* __cplusplus */ |
| |
| |
| #include "nvram_defs.h" |
| #include "nvram_enums.h" |
| #include "ps_public_enum.h" |
| #include "device.h" |
| // LID Enums |
| |
| typedef enum |
| { |
| NVRAM_EF_L5_IA_APNINFO_LID = NVRAM_LID_GRP_L5(0), |
| NVRAM_EF_L5_APNINFO_LID = NVRAM_LID_GRP_L5(1), |
| NVRAM_EF_L5_NW_ROAMING_TXT_LID = NVRAM_LID_GRP_L5(2), |
| NVRAM_EF_L5_NW_CONFIG_LID = NVRAM_LID_GRP_L5(3), |
| NVRAM_EF_L5_FCC_LOCK_CONFIG_LID = NVRAM_LID_GRP_L5(4), |
| NVRAM_EF_L5_FCC_LOCK_STATE_LID = NVRAM_LID_GRP_L5(5), |
| NVRAM_EF_L5_SS_CLIR_VALUE_LID = NVRAM_LID_GRP_L5(6), |
| NVRAM_EF_L5_SS_TBCW_STATE_LID = NVRAM_LID_GRP_L5(7), |
| NVRAM_EF_L5_CC_ECC_LIST_OM_LID = NVRAM_LID_GRP_L5(8), |
| NVRAM_EF_L5_CC_ECC_LIST_OP01_LID = NVRAM_LID_GRP_L5(9), |
| NVRAM_EF_L5_CC_ECC_LIST_OP02_LID = NVRAM_LID_GRP_L5(10), |
| NVRAM_EF_L5_CC_ECC_LIST_OP09_LID = NVRAM_LID_GRP_L5(11), |
| NVRAM_EF_L5_CC_ECC_LIST_OP12_LID = NVRAM_LID_GRP_L5(12), |
| NVRAM_EF_L5_CC_ECC_LIST_OP17_LID = NVRAM_LID_GRP_L5(13), |
| NVRAM_EF_L5_CC_ECC_LIST_OP18_LID = NVRAM_LID_GRP_L5(14), |
| NVRAM_EF_L5_CC_ECC_LIST_OP20_LID = NVRAM_LID_GRP_L5(15), |
| NVRAM_EF_L5_THERMAL_LID = NVRAM_LID_GRP_L5(16), |
| NVRAM_EF_L5_SLOTS_MAP_LID = NVRAM_LID_GRP_L5(17), |
| NVRAM_EF_L5_SIM_ENABLE_LID = NVRAM_LID_GRP_L5(19), |
| NVRAM_EF_L5_MD_VERSION_LID = NVRAM_LID_GRP_L5(20), |
| NVRAM_EF_L5_IO_CONFIG_LID = NVRAM_LID_GRP_L5(21), |
| NVRAM_EF_L5_NW_RAT_CONFIG_LID = NVRAM_LID_GRP_L5(22), |
| NVRAM_EF_L5_IMS_CAPA_LID = NVRAM_LID_GRP_L5(24), |
| NVRAM_EF_L5_ECALL_DOMAIN_SELECT_MODE_LID = NVRAM_LID_GRP_L5(25), |
| NVRAM_EF_L5_NITZ_OPER_LID = NVRAM_LID_GRP_L5(28), |
| NVRAM_EF_L5_SYS_SLEEP_LEFT_TIMER_LID = NVRAM_LID_GRP_L5(31), |
| NVRAM_EF_L5_ECALL_TIMER_INTERVAL_LID = NVRAM_LID_GRP_L5(34) |
| } nvram_lid_l5_enum; |
| |
| //VERNO |
| #define NVRAM_EF_L5_IA_APNINFO_LID_VERNO "003" |
| #define NVRAM_EF_L5_APNINFO_LID_VERNO "006" |
| #define NVRAM_EF_L5_NW_ROAMING_TXT_LID_VERNO "000" |
| #define NVRAM_EF_L5_NW_CONFIG_LID_VERNO "000" |
| #define NVRAM_EF_L5_FCC_LOCK_CONFIG_LID_VERNO "000" |
| #define NVRAM_EF_L5_FCC_LOCK_STATE_LID_VERNO "000" |
| #define NVRAM_EF_L5_SS_CLIR_VALUE_LID_VERNO "000" |
| #define NVRAM_EF_L5_SS_TBCW_STATE_LID_VERNO "000" |
| #define NVRAM_EF_L5_CC_ECC_LIST_OM_LID_VERNO "000" |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP01_LID_VERNO "000" |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP02_LID_VERNO "000" |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP09_LID_VERNO "000" |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP12_LID_VERNO "000" |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP17_LID_VERNO "000" |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP18_LID_VERNO "000" |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP20_LID_VERNO "000" |
| #define NVRAM_EF_L5_THERMAL_LID_VERNO "000" |
| #define NVRAM_EF_L5_SLOTS_MAP_LID_VERNO "000" |
| #define NVRAM_EF_L5_SIM_ENABLE_LID_VERNO "000" |
| #define NVRAM_EF_L5_MD_VERSION_LID_VERNO "000" |
| #define NVRAM_EF_L5_IO_CONFIG_LID_VERNO "000" |
| #define NVRAM_EF_L5_NW_RAT_CONFIG_LID_VERNO "000" |
| #define NVRAM_EF_L5_IMS_CAPA_LID_VERNO "000" |
| #define NVRAM_EF_L5_ECALL_DOMAIN_SELECT_MODE_LID_VERNO "000" |
| #define NVRAM_EF_L5_NITZ_OPER_LID_VERNO "000" |
| #define NVRAM_EF_L5_SYS_SLEEP_LEFT_TIMER_LID_VERNO "000" |
| #define NVRAM_EF_L5_ECALL_TIMER_INTERVAL_LID_VERNO "000" |
| |
| #define NVRAM_EF_L5_IA_APNINFO_LID_HASH 0xE362A470 |
| #define NVRAM_EF_L5_APNINFO_LID_HASH 0x3C18C781 |
| #define NVRAM_EF_L5_NW_ROAMING_TXT_LID_HASH 0xA2FE4AE3 |
| #define NVRAM_EF_L5_NW_CONFIG_LID_HASH 0xF912D038 |
| #define NVRAM_EF_L5_FCC_LOCK_CONFIG_LID_HASH 0x27E6017C |
| #define NVRAM_EF_L5_FCC_LOCK_STATE_LID_HASH 0x24911DF5 |
| #define NVRAM_EF_L5_SS_CLIR_VALUE_LID_HASH 0x1EAD86C8 |
| #define NVRAM_EF_L5_SS_TBCW_STATE_LID_HASH 0x0C50ED19 |
| #define NVRAM_EF_L5_CC_ECC_LIST_OM_LID_HASH 0x64E9F5EC |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP01_LID_HASH 0x5CD8DF7E |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP02_LID_HASH 0x72EE7427 |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP09_LID_HASH 0x11A1A094 |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP12_LID_HASH 0x2B5E03EC |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP17_LID_HASH 0x7B066815 |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP18_LID_HASH 0x04AA9016 |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP20_LID_HASH 0xAF067F99 |
| #define NVRAM_EF_L5_THERMAL_LID_HASH 0x51E51DF2 |
| #define NVRAM_EF_L5_SLOTS_MAP_LID_HASH 0xF0237451 |
| #define NVRAM_EF_L5_SIM_ENABLE_LID_HASH 0x0ED7610A |
| #define NVRAM_EF_L5_MD_VERSION_LID_HASH 0x38D71462 |
| #define NVRAM_EF_L5_IO_CONFIG_LID_HASH 0xEE38D50E |
| #define NVRAM_EF_L5_NW_RAT_CONFIG_LID_HASH 0x1149512C |
| #define NVRAM_EF_L5_IMS_CAPA_LID_HASH 0xE9650386 |
| #define NVRAM_EF_L5_ECALL_DOMAIN_SELECT_MODE_LID_HASH 0x1E5C3925 |
| #define NVRAM_EF_L5_NITZ_OPER_LID_HASH 0x2D46D0D0 |
| #define NVRAM_EF_L5_SYS_SLEEP_LEFT_TIMER_LID_HASH 0x8BCF5348 |
| #define NVRAM_EF_L5_ECALL_TIMER_INTERVAL_LID_HASH 0x39EFF28D |
| |
| typedef struct |
| { |
| kal_uint8 apn[100]; |
| kal_int32 apn_idx; // apn index in apn setting table |
| kal_uint8 pdp_type; |
| kal_uint8 roam_prot; |
| kal_uint8 auth_type; |
| kal_uint8 userid[64]; |
| kal_uint8 password[64]; |
| kal_uint32 bearer_bitmask; |
| kal_uint8 compression; |
| kal_uint8 ia_roaming_control; |
| kal_uint8 ia_source; |
| kal_uint8 plmn_id[7]; |
| kal_uint8 mbim_ip; |
| kal_uint8 imsi[32]; |
| kal_uint8 gid1[32]; |
| kal_uint8 gid2[32]; |
| kal_uint8 iccid[32]; |
| }nvram_l5updn_ia_apn_struct; |
| |
| typedef struct |
| { |
| kal_uint8 sim_id; |
| kal_uint8 ia_apn_count; |
| kal_uint8 ia_set_source; |
| nvram_l5updn_ia_apn_struct ia_apn[10]; |
| } nvram_l5updn_ia_apninfo_struct; |
| |
| typedef struct { |
| kal_uint8 sst_present; |
| kal_uint8 sst; |
| kal_uint8 sd_present; |
| kal_uint8 padding; |
| kal_uint32 sd; |
| kal_uint8 mapped_sst_present; |
| kal_uint8 mapped_sst; |
| kal_uint8 mapped_sd_present; |
| kal_uint8 padding2; |
| kal_uint32 mapped_sd; |
| } nvram_l5updn_s_nssai_struct; |
| |
| typedef struct |
| { |
| kal_uint32 id; |
| kal_uint8 plmn_id[7]; |
| kal_uint8 mbim_ip; |
| kal_uint8 apn[100]; |
| kal_uint32 apn_idx; |
| kal_uint8 username[64]; |
| kal_uint8 passwd[64]; |
| kal_uint32 bearer_bitmask; |
| kal_uint32 apn_type; |
| kal_uint8 pdp_type; |
| kal_uint8 roam_prot; |
| kal_uint8 auth_type; |
| kal_uint8 compression; |
| kal_uint8 source; |
| kal_uint8 roaming_control; |
| kal_uint8 media_type; |
| kal_uint8 profile_status; |
| kal_uint8 mbim_apn_type[16]; |
| kal_uint8 ssc_mode; |
| kal_bool s_nssai_present; |
| nvram_l5updn_s_nssai_struct s_nssai; |
| kal_uint8 pref_access_type; |
| }nvram_l5updn_apn_struct; |
| |
| typedef struct |
| { |
| kal_uint8 sim_id; |
| kal_uint8 apn_count; |
| nvram_l5updn_apn_struct apn[10]; |
| } nvram_l5updn_apninfo_struct; |
| |
| typedef struct { |
| kal_uint16 mbim_buildin_apn_filter; |
| } nvram_l5io_config_struct; |
| |
| typedef struct { |
| kal_uint8 txt[128]; |
| } nvram_l5unw_roaming_txt_struct; |
| |
| typedef struct { |
| kal_uint8 oper[8]; |
| kal_uint8 reg_mode; |
| } nvram_l5unw_config_struct; |
| |
| typedef struct { |
| kal_uint8 mode; |
| kal_uint8 model[10][4]; |
| } nvram_l5_fcc_lock_config_struct; |
| |
| typedef struct { |
| kal_uint8 unlocked; |
| } nvram_l5_fcc_lock_state_struct; |
| |
| typedef struct { |
| kal_uint8 clir_n; |
| } nvram_l5_ss_clir_value_struct; |
| |
| typedef struct { |
| kal_uint8 tbcw_status; |
| kal_uint8 tbcw_mode; |
| } nvram_l5_ss_tbcw_state_struct; |
| |
| typedef struct { |
| kal_uint32 left_timer; |
| } nvram_l5_sys_sleep_left_timer_struct; |
| |
| #define NVRAM_L5_MAX_ECC_NUM_LEN 10 |
| #define NVRAM_L5_MAX_PLMN_ID_LEN 7 |
| #define NVRAM_L5_MAX_PLMN_OPER_NAME_LEN 50 |
| #define NVRAM_L5_MAX_ECC_NUM_OM_RECORD 256 |
| #define NVRAM_L5_MAX_ECC_NUM_OP01_RECORD 32 |
| #define NVRAM_L5_MAX_ECC_NUM_OP02_RECORD 16 |
| #define NVRAM_L5_MAX_ECC_NUM_OP09_RECORD 16 |
| #define NVRAM_L5_MAX_ECC_NUM_OP12_RECORD 8 |
| #define NVRAM_L5_MAX_ECC_NUM_OP17_RECORD 8 |
| #define NVRAM_L5_MAX_ECC_NUM_OP18_RECORD 8 |
| #define NVRAM_L5_MAX_ECC_NUM_OP20_RECORD 8 |
| |
| |
| |
| |
| |
| typedef struct { |
| kal_char ecc_num[NVRAM_L5_MAX_ECC_NUM_LEN]; |
| kal_uint8 cat; |
| kal_uint8 condition; |
| kal_char plmn[NVRAM_L5_MAX_PLMN_ID_LEN]; |
| } nvram_l5_cc_ecc_number_struct; |
| |
| |
| typedef struct { |
| nvram_l5_cc_ecc_number_struct ecc[NVRAM_L5_MAX_ECC_NUM_OM_RECORD]; |
| } nvram_l5_cc_ecc_list_om_struct; |
| |
| typedef struct { |
| nvram_l5_cc_ecc_number_struct ecc[NVRAM_L5_MAX_ECC_NUM_OP01_RECORD]; |
| } nvram_l5_cc_ecc_list_op01_struct; |
| |
| typedef struct { |
| nvram_l5_cc_ecc_number_struct ecc[NVRAM_L5_MAX_ECC_NUM_OP02_RECORD]; |
| } nvram_l5_cc_ecc_list_op02_struct; |
| |
| typedef struct { |
| nvram_l5_cc_ecc_number_struct ecc[NVRAM_L5_MAX_ECC_NUM_OP09_RECORD]; |
| } nvram_l5_cc_ecc_list_op09_struct; |
| |
| typedef struct { |
| nvram_l5_cc_ecc_number_struct ecc[NVRAM_L5_MAX_ECC_NUM_OP12_RECORD]; |
| } nvram_l5_cc_ecc_list_op12_struct; |
| |
| typedef struct { |
| nvram_l5_cc_ecc_number_struct ecc[NVRAM_L5_MAX_ECC_NUM_OP17_RECORD]; |
| } nvram_l5_cc_ecc_list_op17_struct; |
| |
| typedef struct { |
| nvram_l5_cc_ecc_number_struct ecc[NVRAM_L5_MAX_ECC_NUM_OP18_RECORD]; |
| } nvram_l5_cc_ecc_list_op18_struct; |
| |
| typedef struct { |
| nvram_l5_cc_ecc_number_struct ecc[NVRAM_L5_MAX_ECC_NUM_OP20_RECORD]; |
| } nvram_l5_cc_ecc_list_op20_struct; |
| |
| typedef struct { |
| kal_uint8 magic[4]; |
| kal_uint8 mode; |
| } nvram_l5_thermal_struct; |
| |
| typedef struct { |
| kal_bool slots_mapping_ongoing; |
| kal_uint8 efun; |
| kal_uint8 main_slot;//0-based, 0 for slot 0, 1 for slot 1 |
| }nvram_l5_slots_map_struct; |
| |
| typedef struct { |
| kal_bool multi_sim_support; |
| kal_uint8 single_sim_slot; |
| kal_uint8 flags[4]; //bit 0 means FIXED |
| } nvram_l5_sim_enable_struct; |
| |
| typedef struct { |
| kal_uint16 device_support_ver; |
| kal_uint16 device_support_ext_ver; |
| } nvram_l5_device_support_ver_struct; |
| |
| typedef struct { |
| kal_uint8 sim_id; |
| kal_uint32 bit_rat; |
| kal_uint32 prefer_rat; |
| kal_bool disable_2G; |
| } nvram_l5_nw_rat_info_struct; |
| |
| typedef struct { |
| nvram_l5_nw_rat_info_struct rat_info[MAX_SIM_NUM]; |
| kal_uint8 c_protocol; |
| } nvram_l5_nw_rat_config_struct; |
| |
| typedef struct { |
| kal_bool is_valid; |
| kal_uint8 volte_cap; |
| kal_uint8 vilte_cap; |
| kal_uint8 vowifi_cap; |
| kal_uint8 viwifi_cap; |
| kal_uint8 ims_sms_cap; |
| kal_uint8 ims_cap; |
| } nvram_l5_ims_capa_struct; |
| |
| typedef struct { |
| kal_uint8 mode; |
| } nvram_l5_ecall_domain_select_mode_struct; |
| |
| typedef struct { |
| kal_char plmn[NVRAM_L5_MAX_PLMN_ID_LEN]; |
| kal_char oper_long[NVRAM_L5_MAX_PLMN_OPER_NAME_LEN]; |
| kal_char oper_short[NVRAM_L5_MAX_PLMN_OPER_NAME_LEN]; |
| } nvram_l5_nitz_oper_struct; |
| |
| typedef struct { |
| //Manually initiated eCall (MIeC) false triggering cancellation period. (not supported now) |
| kal_uint16 timer1; |
| |
| //IVS Call Cleardown Fallback Timer (CCFT). |
| //time value range(second): 0(default), timer disabled; |
| // 1-43200seconds, timer enabled with this value; default value 3600s(1h). |
| kal_uint16 timer2; |
| |
| //IVS INITIATION signal duration, always enabled in MD with default 2s and cannot be changed. |
| kal_uint16 timer3; |
| |
| //IVS wait for SEND MSD period. |
| //time value range(second): 0(default), timer disabled; |
| // 1-43200seconds, timer enabled with this value; default value 5s. |
| kal_uint16 timer5; |
| |
| //IVS wait for AL-ACK period. |
| //time value range(second): 0(default), timer disabled; |
| // 1-43200seconds, timer enabled with this value; default value 5s. |
| kal_uint16 timer6; |
| |
| //IVS MSD maximum transmission time. |
| //time value range(second): 0(default), timer disabled; |
| // 1-43200seconds, timer enabled with this value; default value 20s. |
| kal_uint16 timer7; |
| |
| //IVS NAD minimum network registration period, default 3600s.(not supported now) |
| kal_uint16 timer9; |
| |
| //IVS NAD network 'Deregistration Fallback Timer' (DTF), only for 'eCall only'. |
| //time value range (minute): |
| // 1-720 minutes, timer enabled with this value; default value 720min(12h). |
| kal_uint16 timer10; |
| } nvram_l5_ecall_timer_interval_struct; |
| |
| // Size and Total |
| #define NVRAM_EF_L5_IA_APNINFO_SIZE sizeof(nvram_l5updn_ia_apninfo_struct) |
| #define NVRAM_EF_L5_IA_APNINFO_TOTAL (1*MAX_SIM_NUM) |
| #define NVRAM_EF_L5_APNINFO_SIZE sizeof(nvram_l5updn_apninfo_struct) |
| #define NVRAM_EF_L5_APNINFO_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_NW_ROAMING_TXT_SIZE sizeof(nvram_l5unw_roaming_txt_struct) |
| #define NVRAM_EF_L5_NW_ROAMING_TXT_TOTAL (1) |
| #define NVRAM_EF_L5_NW_CONFIG_SIZE sizeof(nvram_l5unw_config_struct) |
| #define NVRAM_EF_L5_NW_CONFIG_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_FCC_LOCK_CONFIG_SIZE sizeof(nvram_l5_fcc_lock_config_struct) |
| #define NVRAM_EF_L5_FCC_LOCK_CONFIG_TOTAL (1) |
| #define NVRAM_EF_L5_FCC_LOCK_STATE_SIZE sizeof(nvram_l5_fcc_lock_state_struct) |
| #define NVRAM_EF_L5_FCC_LOCK_STATE_TOTAL (1) |
| |
| #define NVRAM_EF_L5_SS_CLIR_VALUE_SIZE sizeof(nvram_l5_ss_clir_value_struct) |
| #define NVRAM_EF_L5_SS_CLIR_VALUE_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_SS_TBCW_STATE_SIZE sizeof(nvram_l5_ss_tbcw_state_struct) |
| #define NVRAM_EF_L5_SS_TBCW_STATE_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_SYS_SLEEP_LEFT_TIMER_SIZE sizeof(nvram_l5_sys_sleep_left_timer_struct) |
| #define NVRAM_EF_L5_SYS_SLEEP_LEFT_TIMER_TOTAL (1) |
| |
| #define NVRAM_EF_L5_CC_ECC_LIST_OM_SIZE sizeof(nvram_l5_cc_ecc_list_om_struct) |
| #define NVRAM_EF_L5_CC_ECC_LIST_OM_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP01_SIZE sizeof(nvram_l5_cc_ecc_list_op01_struct) |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP01_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP02_SIZE sizeof(nvram_l5_cc_ecc_list_op02_struct) |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP02_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP09_SIZE sizeof(nvram_l5_cc_ecc_list_op09_struct) |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP09_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP12_SIZE sizeof(nvram_l5_cc_ecc_list_op12_struct) |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP12_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP17_SIZE sizeof(nvram_l5_cc_ecc_list_op17_struct) |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP17_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP18_SIZE sizeof(nvram_l5_cc_ecc_list_op18_struct) |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP18_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP20_SIZE sizeof(nvram_l5_cc_ecc_list_op20_struct) |
| #define NVRAM_EF_L5_CC_ECC_LIST_OP20_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_THERMAL_SIZE sizeof(nvram_l5_thermal_struct) |
| #define NVRAM_EF_L5_THERMAL_TOTAL (1) |
| |
| #define NVRAM_EF_L5_SLOTS_MAP_SIZE sizeof(nvram_l5_slots_map_struct) |
| #define NVRAM_EF_L5_SLOTS_MAP_TOTAL (1) |
| |
| #define NVRAM_EF_L5_SIM_ENABLE_SIZE sizeof(nvram_l5_sim_enable_struct) |
| #define NVRAM_EF_L5_SIM_ENABLE_TOTAL (1) |
| |
| #define NVRAM_EF_L5_MD_VERSION_SIZE sizeof(nvram_l5_device_support_ver_struct) |
| #define NVRAM_EF_L5_MD_VERSION_TOTAL (1) |
| |
| #define NVRAM_EF_L5_IO_CONFIG_SIZE sizeof(nvram_l5io_config_struct) |
| #define NVRAM_EF_L5_IO_CONFIG_TOTAL (1) |
| |
| #define NVRAM_EF_L5_NW_RAT_CONFIG_SIZE sizeof(nvram_l5_nw_rat_config_struct) |
| #define NVRAM_EF_L5_NW_RAT_CONFIG_TOTAL (1) |
| |
| #define NVRAM_EF_L5_IMS_CAPA_SIZE sizeof(nvram_l5_ims_capa_struct) |
| #define NVRAM_EF_L5_IMS_CAPA_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_ECALL_DOMAIN_SELECT_MODE_SIZE sizeof(nvram_l5_ecall_domain_select_mode_struct) |
| #define NVRAM_EF_L5_ECALL_DOMAIN_SELECT_MODE_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_NITZ_OPER_SIZE sizeof(nvram_l5_nitz_oper_struct) |
| #define NVRAM_EF_L5_NITZ_OPER_TOTAL (1*MAX_SIM_NUM) |
| |
| #define NVRAM_EF_L5_ECALL_TIMER_INTERVAL_SIZE sizeof(nvram_l5_ecall_timer_interval_struct) |
| #define NVRAM_EF_L5_ECALL_TIMER_INTERVAL_TOTAL (1*MAX_SIM_NUM) |
| |
| #ifdef __cplusplus |
| } |
| #endif |
| |
| #endif /* __L5UPDN_NVRAM_DEF_H__ */ |
| |
| |