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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / custom / service / nvram / td_nvram_def.c
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2005
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * td_nvram_def.c
41 *
42 * Project:
43 * --------
44 * MAUI
45 *
46 * Description:
47 * ------------
48 *
49 *
50 * Author:
51 * -------
52 *
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 *
60 * removed!
61 * removed!
62 *
63 * removed!
64 * removed!
65 * removed!
66 *
67 * removed!
68 * removed!
69 *
70 * removed!
71 * removed!
72 *
73 * removed!
74 * removed!
75 *
76 * removed!
77 * removed!
78 *
79 * removed!
80 * removed!
81 * removed!
82 *
83 *------------------------------------------------------------------------------
84 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
85 *============================================================================
86 ****************************************************************************/
87
88#ifndef NVRAM_NOT_PRESENT
89
90#include "kal_general_types.h"
91#ifdef NVRAM_AUTO_GEN
92#include "nvram_auto_gen.h"
93#endif
94
95#include "nvram_enums.h"
96#include "nvram_defs.h"
97
98/*
99 * User Headers & Default value
100 */
101#include "td_nvram_def.h"
102#include "td_nvram_editor.h"
103
104// Default Values
105#ifdef __AST_TL1_TDD__
106/*Nan Shen:Temp solution for fixing build error*/
107extern kal_uint16 const NVRAM_EF_AST_TL1_TEMP_DAC_DATA_DEFAULT[];
108extern kal_uint16 const NVRAM_EF_AST_TL1_AFC_DATA_DEFAULT[];
109extern kal_int16 const NVRAM_EF_AST_TL1_PATHLOSS_33_35_37_39_DEFAULT[];
110extern kal_int16 const NVRAM_EF_AST_TL1_PATHLOSS_34_DEFAULT[];
111extern kal_int16 const NVRAM_EF_AST_TL1_TXDAC_33_35_37_39_DEFAULT[];
112extern kal_int16 const NVRAM_EF_AST_TL1_TXDAC_34_DEFAULT[];
113extern kal_int16 const NVRAM_EF_AST_TL1_TXDAC_40_DEFAULT[];
114extern kal_int16 const NVRAM_EF_AST_TL1_ABB_CAL_DEFAULT[];
115extern kal_int16 const NVRAM_EF_AST_TL1_TXCLPC_34_DEFAULT[];
116extern kal_int16 const NVRAM_EF_AST_TL1_TXCLPC_39_DEFAULT[];
117extern kal_int16 const NVRAM_EF_AST_TL1_TXCLPC_40_DEFAULT[];
118#if !defined(__AST1001__) && !defined(__AST2001__)
119extern kal_uint32 const NVRAM_EF_AST_TL1_CAP_DATA_DEFAULT[];
120#endif
121
122#ifdef __TDD_RF_CUSTOM_TOOL_SUPPORT__
123extern T_TD_CUSTOMIZATION_STRUCT TD_CUST_CONST NVRAM_EF_AST_TL1_RF_PARAMETER_DEFAULT[];
124#endif
125#endif
126
127#ifdef __AST_TL1_TDD__
128extern void nvram_get_tL1_default_value_to_write(nvram_lid_enum lid, kal_uint8 *buffer, kal_uint16 buffer_size);
129#endif
130
131// LID Declaration
132ltable_entry_struct logical_data_item_table_td[] =
133{
134#ifdef __AST_TL1_TDD__
135 {
136 NVRAM_EF_AST_TL1_TEMP_DAC_LID,
137 NVRAM_EF_AST_TL1_TEMP_DAC_TOTAL,
138 NVRAM_EF_AST_TL1_TEMP_DAC_SIZE,
139 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_TEMP_DAC_DATA_DEFAULT),
140 NVRAM_CATEGORY_CALIBRAT,
141 NVRAM_ATTR_AVERAGE,
142 "TD2A",
143 VER(NVRAM_EF_AST_TL1_TEMP_DAC_LID)
144 },
145
146 {
147 NVRAM_EF_AST_TL1_AFC_DATA_LID,
148 NVRAM_EF_AST_TL1_AFC_DATA_TOTAL,
149 NVRAM_EF_AST_TL1_AFC_DATA_SIZE,
150 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_AFC_DATA_DEFAULT),
151 NVRAM_CATEGORY_CALIBRAT,
152 NVRAM_ATTR_AVERAGE,
153 "TD2B",
154 VER(NVRAM_EF_AST_TL1_AFC_DATA_LID)
155 },
156
157 {
158 NVRAM_EF_AST_TL1_PATHLOSS_BAND33_35_37_39_LID,
159 NVRAM_EF_AST_TL1_PATHLOSS_BAND_TOTAL,
160 NVRAM_EF_AST_TL1_PATHLOSS_BAND_SIZE,
161 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_PATHLOSS_33_35_37_39_DEFAULT),
162 NVRAM_CATEGORY_CALIBRAT,
163 NVRAM_ATTR_AVERAGE,
164 "TD2C",
165 VER(NVRAM_EF_AST_TL1_PATHLOSS_BAND33_35_37_39_LID)
166 },
167
168 {
169 NVRAM_EF_AST_TL1_PATHLOSS_BAND34_LID,
170 NVRAM_EF_AST_TL1_PATHLOSS_BAND_TOTAL,
171 NVRAM_EF_AST_TL1_PATHLOSS_BAND_SIZE,
172 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_PATHLOSS_34_DEFAULT),
173 NVRAM_CATEGORY_CALIBRAT,
174 NVRAM_ATTR_AVERAGE,
175 "TD2D",
176 VER(NVRAM_EF_AST_TL1_PATHLOSS_BAND34_LID)
177 },
178
179 {
180 NVRAM_EF_AST_TL1_PATHLOSS_BAND36_LID,
181 NVRAM_EF_AST_TL1_PATHLOSS_BAND_TOTAL,
182 NVRAM_EF_AST_TL1_PATHLOSS_BAND_SIZE,
183 NVRAM_NORMAL(NVRAM_EF_ZERO_DEFAULT),
184 NVRAM_CATEGORY_CALIBRAT,
185 NVRAM_ATTR_AVERAGE,
186 "TD2E",
187 VER(NVRAM_EF_AST_TL1_PATHLOSS_BAND36_LID)
188 },
189
190 {
191 NVRAM_EF_AST_TL1_PATHLOSS_BAND38_LID,
192 NVRAM_EF_AST_TL1_PATHLOSS_BAND_TOTAL,
193 NVRAM_EF_AST_TL1_PATHLOSS_BAND_SIZE,
194 NVRAM_NORMAL(NVRAM_EF_ZERO_DEFAULT),
195 NVRAM_CATEGORY_CALIBRAT,
196 NVRAM_ATTR_AVERAGE,
197 "TD2F",
198 VER(NVRAM_EF_AST_TL1_PATHLOSS_BAND38_LID)
199 },
200
201 {
202 NVRAM_EF_AST_TL1_PATHLOSS_BAND40_LID,
203 NVRAM_EF_AST_TL1_PATHLOSS_BAND_TOTAL,
204 NVRAM_EF_AST_TL1_PATHLOSS_BAND_SIZE,
205 NVRAM_NORMAL(NVRAM_EF_ZERO_DEFAULT),
206 NVRAM_CATEGORY_CALIBRAT,
207 NVRAM_ATTR_AVERAGE,
208 "TD2G",
209 VER(NVRAM_EF_AST_TL1_PATHLOSS_BAND40_LID)
210 },
211
212 {
213 NVRAM_EF_AST_TL1_TXDAC_BAND33_35_37_39_LID,
214 NVRAM_EF_AST_TL1_TXDAC_BAND_TOTAL,
215 NVRAM_EF_AST_TL1_TXDAC_BAND_SIZE,
216 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_TXDAC_33_35_37_39_DEFAULT),
217 NVRAM_CATEGORY_CALIBRAT,
218 NVRAM_ATTR_AVERAGE,
219 "TD2H",
220 VER(NVRAM_EF_AST_TL1_TXDAC_BAND33_35_37_39_LID)
221 },
222
223 {
224 NVRAM_EF_AST_TL1_TXDAC_BAND34_LID,
225 NVRAM_EF_AST_TL1_TXDAC_BAND_TOTAL,
226 NVRAM_EF_AST_TL1_TXDAC_BAND_SIZE,
227 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_TXDAC_34_DEFAULT),
228 NVRAM_CATEGORY_CALIBRAT,
229 NVRAM_ATTR_AVERAGE,
230 "TD2I",
231 VER(NVRAM_EF_AST_TL1_TXDAC_BAND34_LID)
232 },
233
234 {
235 NVRAM_EF_AST_TL1_TXDAC_BAND36_LID,
236 NVRAM_EF_AST_TL1_TXDAC_BAND_TOTAL,
237 NVRAM_EF_AST_TL1_TXDAC_BAND_SIZE,
238 NVRAM_NORMAL(NVRAM_EF_ZERO_DEFAULT),
239 NVRAM_CATEGORY_CALIBRAT,
240 NVRAM_ATTR_AVERAGE,
241 "TD2J",
242 VER(NVRAM_EF_AST_TL1_TXDAC_BAND36_LID)
243 },
244
245 {
246 NVRAM_EF_AST_TL1_TXDAC_BAND38_LID,
247 NVRAM_EF_AST_TL1_TXDAC_BAND_TOTAL,
248 NVRAM_EF_AST_TL1_TXDAC_BAND_SIZE,
249 NVRAM_NORMAL(NVRAM_EF_ZERO_DEFAULT),
250 NVRAM_CATEGORY_CALIBRAT,
251 NVRAM_ATTR_AVERAGE,
252 "TD2K",
253 VER(NVRAM_EF_AST_TL1_TXDAC_BAND38_LID)
254 },
255
256 {
257 NVRAM_EF_AST_TL1_TXDAC_BAND40_LID,
258 NVRAM_EF_AST_TL1_TXDAC_BAND_TOTAL,
259 NVRAM_EF_AST_TL1_TXDAC_BAND_SIZE,
260 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_TXDAC_40_DEFAULT),
261 NVRAM_CATEGORY_CALIBRAT,
262 NVRAM_ATTR_AVERAGE,
263 "TD2L",
264 VER(NVRAM_EF_AST_TL1_TXDAC_BAND40_LID)
265 },
266//CYLEN??
267 {
268 NVRAM_EF_AST_TL1_ABB_CAL_LID,
269 NVRAM_EF_AST_TL1_ABB_CAL_TOTAL,
270 NVRAM_EF_AST_TL1_ABB_CAL_SIZE,
271 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_ABB_CAL_DEFAULT),
272 NVRAM_CATEGORY_USER, /// this is auto calibrated in first time mcu power on (or the data loss case), don't need backup & restore
273 NVRAM_ATTR_AVERAGE,
274 "TD2P", // be very careful, MT2M, MT2N, MT2O is used by RF calibration history in MAUI, 10A branch
275 VER(NVRAM_EF_AST_TL1_ABB_CAL_LID)
276 },
277 {
278 NVRAM_EF_AST_TL1_TXCLPC_BAND34_LID,
279 NVRAM_EF_AST_TL1_TXCLPC_BAND_TOTAL,
280 NVRAM_EF_AST_TL1_TXCLPC_BAND_SIZE,
281 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_TXCLPC_34_DEFAULT),
282 NVRAM_CATEGORY_CALIBRAT,
283 NVRAM_ATTR_AVERAGE,
284 "TD2W", // be very careful, MT2M, MT2N, MT2O is used by RF calibration history in MAUI, 10A branch
285 VER(NVRAM_EF_AST_TL1_TXCLPC_BAND34_LID)
286 },
287
288 {
289 NVRAM_EF_AST_TL1_TXCLPC_BAND33_35_37_39_LID,
290 NVRAM_EF_AST_TL1_TXCLPC_BAND_TOTAL,
291 NVRAM_EF_AST_TL1_TXCLPC_BAND_SIZE,
292 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_TXCLPC_33_35_37_39_DEFAULT),
293 NVRAM_CATEGORY_CALIBRAT,
294 NVRAM_ATTR_AVERAGE,
295 "TD2X", // be very careful, MT2M, MT2N, MT2O is used by RF calibration history in MAUI, 10A branch
296 VER(NVRAM_EF_AST_TL1_TXCLPC_BAND33_35_37_39_LID)
297 },
298
299 {
300 NVRAM_EF_AST_TL1_TXCLPC_BAND36_LID,
301 NVRAM_EF_AST_TL1_TXCLPC_BAND_TOTAL,
302 NVRAM_EF_AST_TL1_TXCLPC_BAND_SIZE,
303 NVRAM_NORMAL(NVRAM_EF_ZERO_DEFAULT),
304 NVRAM_CATEGORY_CALIBRAT,
305 NVRAM_ATTR_AVERAGE,
306 "TD2Y",
307 VER(NVRAM_EF_AST_TL1_TXCLPC_BAND36_LID)
308 },
309
310 {
311 NVRAM_EF_AST_TL1_TXCLPC_BAND38_LID,
312 NVRAM_EF_AST_TL1_TXCLPC_BAND_TOTAL,
313 NVRAM_EF_AST_TL1_TXCLPC_BAND_SIZE,
314 NVRAM_NORMAL(NVRAM_EF_ZERO_DEFAULT),
315 NVRAM_CATEGORY_CALIBRAT,
316 NVRAM_ATTR_AVERAGE,
317 "TD2Z",
318 VER(NVRAM_EF_AST_TL1_TXCLPC_BAND38_LID)
319 },
320
321 {
322 NVRAM_EF_AST_TL1_TXCLPC_BAND40_LID,
323 NVRAM_EF_AST_TL1_TXCLPC_BAND_TOTAL,
324 NVRAM_EF_AST_TL1_TXCLPC_BAND_SIZE,
325 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_TXCLPC_40_DEFAULT),
326 NVRAM_CATEGORY_CALIBRAT,
327 NVRAM_ATTR_AVERAGE,
328 "TD0A", // be very careful, MT2M, MT2N, MT2O is used by RF calibration history in MAUI, 10A branch
329 VER(NVRAM_EF_AST_TL1_TXCLPC_BAND40_LID)
330 },
331 {
332 NVRAM_EF_AST_TL1_POC_PARAM_LID,
333 NVRAM_EF_AST_TL1_POC_PARAM_TOTAL,
334 NVRAM_EF_AST_TL1_POC_PARAM_SIZE,
335 NVRAM_NORMAL_NOT_GEN(&NVRAM_EF_AST_TL1_POCDATA_3439_DEFAULT),
336 NVRAM_CATEGORY_CALIBRAT,
337 NVRAM_ATTR_AVERAGE,
338 "TD0B",
339 VER(NVRAM_EF_AST_TL1_POC_PARAM_LID)
340 },
341
342 {
343 NVRAM_EF_AST_TL1_RF_PARAM_LID,
344 NVRAM_EF_AST_TL1_RF_PARAM_TOTAL,
345 NVRAM_EF_AST_TL1_RF_PARAM_SIZE,
346 NVRAM_DEFAULT_FUNC(nvram_get_tL1_default_value_to_write),
347 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT, /// this is auto calibrated in first time mcu power on (or the data loss case), don't need backup & restore
348 (NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_OTA_RESET) | NVRAM_ATTR_GEN_DEFAULT,
349 "TL10",
350 VER(NVRAM_EF_AST_TL1_RF_PARAM_LID),
351 },
352
353 {
354 NVRAM_EF_AST_TL1_RFFE_PARAM_LID,
355 NVRAM_EF_AST_TL1_RFFE_PARAM_TOTAL,
356 NVRAM_EF_AST_TL1_RFFE_PARAM_SIZE,
357 NVRAM_DEFAULT_FUNC(nvram_get_tL1_default_value_to_write),
358 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT, /// this is auto calibrated in first time mcu power on (or the data loss case), don't need backup & restore
359 NVRAM_ATTR_OTA_RESET | NVRAM_ATTR_GEN_DEFAULT,
360 "TL11",
361 VER(NVRAM_EF_AST_TL1_RFFE_PARAM_LID)
362 },
363
364// DRDI INIT STATUS FOR NVRAM
365 {
366 NVRAM_EF_AST_CUSTOM_DYNAMIC_INIT_LID,
367 NVRAM_EF_AST_CUSTOM_DYNAMIC_INIT_TOTAL,
368 NVRAM_EF_AST_CUSTOM_DYNAMIC_INIT_SIZE,
369 NVRAM_NORMAL(NVRAM_EF_ZERO_DEFAULT), //NVRAM_NORMAL(TDS_DRDI_STATUS_DEFAULT),
370 NVRAM_CATEGORY_USER,
371 NVRAM_ATTR_OTA_RESET,
372 "TL12",
373 VER(NVRAM_EF_AST_CUSTOM_DYNAMIC_INIT_LID),
374 },
375// DRDI DEBUG INFO. FOR NVRAM
376 {
377 NVRAM_EF_AST_CUSTOM_DYNAMIC_INIT_DEBUG_LID,
378 NVRAM_EF_AST_CUSTOM_DYNAMIC_INIT_DEBUG_TOTAL,
379 NVRAM_EF_AST_CUSTOM_DYNAMIC_INIT_DEBUG_SIZE,
380 NVRAM_NORMAL(NVRAM_EF_ZERO_DEFAULT),
381 NVRAM_CATEGORY_USER,
382 NVRAM_ATTR_OTA_RESET,
383 "TL13",
384 VER(NVRAM_EF_AST_CUSTOM_DYNAMIC_INIT_DEBUG_LID),
385 },
386
387// RF TIME SEQUENCE INFO. FOR NVRAM
388 {
389 NVRAM_EF_AST_TL1_RF_TIMESEQ_LID,
390 NVRAM_EF_AST_TL1_RF_TIMESEQ_TOTAL,
391 NVRAM_EF_AST_TL1_RF_TIMESEQ_SIZE,
392 NVRAM_DEFAULT_FUNC(nvram_get_tL1_default_value_to_write),
393 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
394 (NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_OTA_RESET) | NVRAM_ATTR_GEN_DEFAULT,
395 "TL14",
396 VER(NVRAM_EF_AST_TL1_RF_TIMESEQ_LID),
397 },
398#if defined(__TAS_SUPPORT__)
399 {
400 NVRAM_EF_AST_TL1_TAS_CUSTOM_PARAMES_LID,
401 NVRAM_EF_AST_TL1_TAS_CUSTOM_PARAMES_TOTAL,
402 NVRAM_EF_AST_TL1_TAS_CUSTOM_PARAMES_SIZE,
403 NVRAM_DEFAULT_FUNC(nvram_get_tL1_default_value_to_write),
404 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
405 (NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_OTA_RESET) | NVRAM_ATTR_GEN_DEFAULT,
406 "TL15",
407 VER(NVRAM_EF_AST_TL1_TAS_CUSTOM_PARAMES_LID),
408 },
409#endif
410
411 {
412 NVRAM_EF_AST_TL1_DAT_PARAM_LID,
413 NVRAM_EF_AST_TL1_DAT_PARAM_TOTAL,
414 NVRAM_EF_AST_TL1_DAT_PARAM_SIZE,
415 NVRAM_DEFAULT_FUNC(nvram_get_tL1_default_value_to_write),
416 NVRAM_CATEGORY_USER | NVRAM_CATEGORY_FUNC_DEFAULT,
417 (NVRAM_ATTR_MCF_OTA | NVRAM_ATTR_OTA_RESET) | NVRAM_ATTR_GEN_DEFAULT,
418 "TL16",
419 VER(NVRAM_EF_AST_TL1_DAT_PARAM_LID),
420 },
421
422 {
423 NVRAM_EF_AST_TL1_CAP_DATA_LID,
424 NVRAM_EF_AST_TL1_CAP_DATA_TOTAL,
425 NVRAM_EF_AST_TL1_CAP_DATA_SIZE,
426 NVRAM_NORMAL_NOT_GEN(NVRAM_EF_AST_TL1_CAP_DATA_DEFAULT),
427 NVRAM_CATEGORY_CALIBRAT,
428 NVRAM_ATTR_AVERAGE,
429 "TD6Z",
430 VER(NVRAM_EF_AST_TL1_CAP_DATA_LID)
431 },
432#endif // #if defined(__AST_TL1_TDD__)
433
434 NVRAM_LTABLE_END
435};
436
437#endif /* NVRAM_NOT_PRESENT */