| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | #ifndef __DRV_D2D_H__ |
| 2 | #define __DRV_D2D_H__ |
| 3 | |
| 4 | #include "sync_data.h" |
| 5 | #include "drv_comm.h" |
| 6 | #include "reg_base.h" |
| 7 | #include "d2d_public.h" |
| 8 | |
| 9 | /******************************************************************************* |
| 10 | * CSIF CR Definition |
| 11 | *******************************************************************************/ |
| 12 | |
| 13 | #define D2D_MC1_BANK_A_BASE (BASE_MADDR_MCORE1_D2D) |
| 14 | #define D2D_MC1_BANK_B_BASE (BASE_NADDR_MCORE1_D2D) |
| 15 | |
| 16 | #define D2D_DSR_BASE (CSIF_BANK_A_BASE) |
| 17 | |
| 18 | #define D2D_RWDATA_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x0) |
| 19 | #define D2D_RWDATA_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x0) |
| 20 | |
| 21 | #define D2D_TADDR_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x10) |
| 22 | #define D2D_TADDR_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x10) |
| 23 | |
| 24 | #define D2D_LENGTH_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x14) |
| 25 | #define D2D_LENGTH_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x14) |
| 26 | |
| 27 | #define D2D_TUSER_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x18) |
| 28 | #define D2D_TUSER_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x18) |
| 29 | #define D2D_TUSER_TUSER_OFFSET (0x0) |
| 30 | #define D2D_TUSER_TMODE_OFFSET (0x8) |
| 31 | #define D2D_TUSER_TAUX_OFFSET (0x10) |
| 32 | |
| 33 | #define D2D_SIGCTRL_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x1C) |
| 34 | #define D2D_SIGCTRL_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x1C) |
| 35 | #define D2D_SIGCTRL_TADDRMOD_OFFSET (0x0) |
| 36 | #define D2D_SIGCTRL_TRW_OFFSET (0x2) |
| 37 | #define D2D_SIGCTRL_ALIGN_OFFSET (0x3) |
| 38 | #define D2D_SIGCTRL_TSIZE_OFFSET (0x4) |
| 39 | #define D2D_SIGCTRL_TRIGMOD_OFFSET (0x8) |
| 40 | |
| 41 | #define D2D_TRIGCTRL_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x20) |
| 42 | #define D2D_TRIGCTRL_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x20) |
| 43 | |
| 44 | #define D2D_DBGCTRL_CR_BANK_A_BASE (D2D_MC1_BANK_A_BASE + 0x24) |
| 45 | #define D2D_DBGCTRL_CR_BANK_B_BASE (D2D_MC1_BANK_B_BASE + 0x24) |
| 46 | #define D2D_DBGCTRL_IDLE_OFFSET (0x0) |
| 47 | #define D2D_DBGCTRL_ERR_TX_EN_OFFSET (0x1) |
| 48 | #define D2D_DBGCTRL_ABORT_OFFSET (0x2) |
| 49 | #define D2D_DBGCTRL_FORCE_ABORT_OFFSET (0x3) |
| 50 | #define D2D_DBGCTRL_USE_DBG_TID_OFFSET (0x4) |
| 51 | #define D2D_DBGCTRL_REPLACE_MOD_OFFSET (0x6) |
| 52 | #define D2D_DBGCTRL_DBG_PATH_EN_OFFSET (0x7) |
| 53 | |
| 54 | |
| 55 | |
| 56 | // TADDRMOD =0, Fixed-address |
| 57 | // TRW =1, write |
| 58 | // ALIGN =1 |
| 59 | // TSIZE =2, 4 byte |
| 60 | // TRIGRMODE =1, triggered based |
| 61 | #define D2D_SIGCTRL_WRITE32_CMD (0x12C) |
| 62 | // TADDRMOD =0, Fixed-address |
| 63 | // TRW =0, read |
| 64 | // ALIGN =1 |
| 65 | // TSIZE =2, 4 byte |
| 66 | // TRIGRMODE =1, triggered based |
| 67 | #define D2D_SIGCTRL_READ32_CMD (0x128) |
| 68 | |
| 69 | /******************************************************************************* |
| 70 | * Macros |
| 71 | *******************************************************************************/ |
| 72 | |
| 73 | /* Read/Write macros */ |
| 74 | #define D2D_REG(addr) DRV_Reg32(addr) |
| 75 | #define D2D_REG_WRITE(addr, data) DRV_WriteReg32(addr, data); |
| 76 | |
| 77 | /* Sync macros */ |
| 78 | #define D2D_MO_SYNC() MO_Sync(); |
| 79 | |
| 80 | #endif /* __DRV_D2D_H__ */ |