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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / devdrv / elm / src / md97 / elm.c
blob: a9a08d53086c300d53eea8f36c041e888212072b [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1#include "elm.h"
2#include "drv_comm.h"
3#include "us_timer.h"
4#include "kal_public_api.h"
5#include "kal_hrt_api.h"
6#include "intrCtrl.h"
7#include "drv_mdap_interface.h" //for show MD_DVFS_CON in trace
8#include "spv_service.h" // for __SPV_MPB_MEMSET_MEMCPY_M3_BW_CORRELATION__
9#include <math.h>
10
11#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
12// for profiling ELM log
13#include "TrcMod.h" //for L1 Trace API
14#endif
15
16#if defined(__ELM_MD97__) && !defined(MT6297)
17#define ID2_SET_TO_RW
18kal_bool id2_rw_enable = KAL_TRUE;
19#else
20kal_bool id2_rw_enable = KAL_FALSE;
21#endif
22
23static kal_bool emi_elm_urgent_enable = KAL_TRUE ;
24
25/** ----- Register definition ------ **/
26
27
28// MDMCU ELM
29#define REG_MCUSYS_EMI_ELM_CODA_VERSION (BASE_ADDR_MCUSYS_ELM_EMI+0x0)
30#define REG_MCUSYS_EMI_ELM_EN_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x8)
31#define REG_MCUSYS_EMI_ELM_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0xC)
32 #define ELM_MODE(x) ((x)<<4)
33 #define ELM_MODE_MASK 0x3
34 #define ELM_AO_DECODE(x) ((x)<<13)
35 #define ELM_DECODE_FROM_AO 1
36 #define ELM_DECODE_FROM_APB 0
37 #define ELM_MODE_ID_SEL(x) (x<<8)
38 #define ELM_MODE_ID_MASK 0xC //clear ID2/3 only
39 #define ELM_ID_RW(rw, id) (rw<<id) //rw: 0->r; 1->w; id: 0, 1, 2, 3
40 #define ELM_TOTAL_LAT_WEIGHT_BLOCK(x) (x<<20) //[22:20]
41#define REG_MCUSYS_EMI_ELM_LAT_CNT_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x10)
42#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x20)
43
44 #define ALEN(x) ((x)<<28) //4'hf
45 #define ASIZE(x) ((x)<<24) //3'h7
46 #define AULTRA(x) ((x)<<20) //2'h3
47 #define ABUST(x) ((x)<<16) //2'h3
48 #define AID(x) ((x)<<0) //12'h1FFF
49 #define MASTER_DEFAULT_MASK 0x1FFF //defualt value
50 #define MASTER_ALL_MASK 0x3 //IA: 0x0, MMU: 0x1, USIP: 0x2
51 #define MASTER_MDMCU 0x0 //MDMCU(Incluing IA & MMU)
52 #define MASTER_MDMCU_MASK 0x1FFD
53 #define MASTER_USIP 0x2 //USIP -> 0x2
54 #define MASTER_USIP_MASK 0x1FFC
55 #define MASTER_MCORE 0x3
56 #define MASTER_MCORE_MASK 0x1FFC
57
58
59#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x24)
60#define ELM_AO_CONTROL_DEFAULT 0xF7331FFF
61
62#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x28)
63#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x2C)
64#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x30)
65#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x34)
66#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x38)
67#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x3C)
68#define REG_MCUSYS_EMI_ELM_ID0_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x40)
69#define REG_MCUSYS_EMI_ELM_ID1_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x44)
70#define REG_MCUSYS_EMI_ELM_CNT0 (BASE_ADDR_MCUSYS_ELM_EMI+0x50)
71#define REG_MCUSYS_EMI_ELM_CNT1 (BASE_ADDR_MCUSYS_ELM_EMI+0x54)
72#define REG_MCUSYS_EMI_ELM_CNT2 (BASE_ADDR_MCUSYS_ELM_EMI+0x58)
73#define REG_MCUSYS_EMI_ELM_CNT3 (BASE_ADDR_MCUSYS_ELM_EMI+0x5C)
74#define REG_MCUSYS_EMI_ELM_OVERRUN_CNT_ST (BASE_ADDR_MCUSYS_ELM_EMI+0x60)
75#define REG_MCUSYS_EMI_ELM_INT_STATUS (BASE_ADDR_MCUSYS_ELM_EMI+0x64)
76
77#define REG_MCUSYS_EMI_ELM_ID0_URG_FLGA_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x700)
78#define REG_MCUSYS_EMI_ELM_ID0_URG_FLGA_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x704)
79#define REG_MCUSYS_EMI_ELM_ID1_URG_FLGA_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x70C)
80#define REG_MCUSYS_EMI_ELM_ID1_URG_FLGA_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x710)
81#define REG_MCUSYS_EMI_ELM_URG_IDLE_CLR_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x718)
82
83
84
85
86
87 #define INT_MASK_ALL 0x3F
88 #define INT_MASK_LAT 0xF
89 #define INT_MASK_LAT_TOT 0xA
90 #define INT_MASK_LAT_AVG 0x5
91 #define INT_MASK_WC 0x30
92 #define ID0_AVG_LAT_INT (1<<0)
93 #define ID0_TOT_LAT_INT (1<<1)
94 #define ID1_AVG_LAT_INT (1<<2)
95 #define ID1_TOT_LAT_INT (1<<3)
96 #define ID2_TOT_WC_INT (1<<4)
97 #define ID3_TOT_WC_INT (1<<5)
98#define REG_MCUSYS_EMI_ELM_AO_STATUS0 (BASE_ADDR_MCUSYS_ELM_EMI+0x68)
99 #define DECODE_ID0(x) ((x)<<0)
100 #define ELM_READ (0<<4)
101 #define ELM_WRITE (1<<4)
102 #define ELM_ALL_MASTER (0<<2)
103 #define ELM_MDMCU_ONLY (1<<2)
104 #define ELM_USIP_ONLY (2<<2)
105 #define ELM_ALL_PRIO (0<<0)
106 #define ELM_PRE_ULTRA (1<<0)
107 #define ELM_ULTRA (2<<0)
108 #define LAT_TH_ID0_NORMAL(x) ((x)<<5)
109 #define LAT_TH_ID1_NORMAL(x) ((x)<<15)
110 #define ELM_ACCURACY(x) ((x)<<29)
111 #define ELM_unit_25us 2
112 #define ELM_unit_100us 4
113 #define ELM_ENABLE (1<<27)
114 #define ELM_DISABLE (0<<27)
115 #define ELM_IDLE_ENABLE (1<<28)
116 #define ELM_IDLE_DISABLE (0<<28)
117#define REG_MCUSYS_EMI_ELM_AO_STATUS1 (BASE_ADDR_MCUSYS_ELM_EMI+0x6C)
118 #define ELM_INT_MASK(x) ((x)<<0)
119 #define LAT_INT_MASK_ALL 0xF
120 #define LAT_INT_UNMASK_ALL 0x0
121 #define EMI_BLOCK(x) ((x)<<4)
122 #define E_NOT_MASK 0
123 #define E_MASK 1
124 #define ELM_DURATION(x) ((x-1)<<5)
125 #define DECODE_ID1(x) ((x)<<12)
126 /* #define usage same as DECODE_ID0 */
127 #define ELM_EMI_TOP_BLOCK(x) ((x)<<31)
128 #define E_TOP_MASK 1
129 #define E_TOP_NOT_MASK 0
130#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x70)
131#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x74)
132#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x78)
133#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x7C)
134#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x80)
135#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x84)
136#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x88)
137#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x8C)
138#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x90)
139#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x94)
140#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x98)
141#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x9C)
142#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA0)
143#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA4)
144#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA8)
145#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xAC)
146#define REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB0)
147#define REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB4)
148#define REG_MCUSYS_EMI_ELM_ID0_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xC0)
149#define REG_MCUSYS_EMI_ELM_ID0_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xC4)
150#define REG_MCUSYS_EMI_ELM_ID0_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xC8)
151#define REG_MCUSYS_EMI_ELM_ID0_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xCC)
152#define REG_MCUSYS_EMI_ELM_ID1_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xD0)
153#define REG_MCUSYS_EMI_ELM_ID1_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xD4)
154#define REG_MCUSYS_EMI_ELM_ID1_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xD8)
155#define REG_MCUSYS_EMI_ELM_ID1_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xDC)
156#define REG_MCUSYS_EMI_ELM_CNT4 (BASE_ADDR_MCUSYS_ELM_EMI+0xE0)
157#define REG_MCUSYS_EMI_ELM_CNT5 (BASE_ADDR_MCUSYS_ELM_EMI+0xE4)
158#define REG_MCUSYS_EMI_ELM_AO_STATUS2 (BASE_ADDR_MCUSYS_ELM_EMI+0xF0)
159 #define ELM_WC_INT_MASK(x) ((x)<<0)
160 #define WC_INT_MASK_ALL 0x3
161 #define WC_INT_UNMASK_ALL 0x0
162 #define LAT_TH_ID0_BLOCK(x) ((x)<<4)
163 #define LAT_TH_ID1_BLOCK(x) ((x)<<16)
164#if 0
165/* under construction !*/
166/* under construction !*/
167/* under construction !*/
168/* under construction !*/
169/* under construction !*/
170/* under construction !*/
171/* under construction !*/
172#endif
173#define REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x510)
174#define REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x514)
175#define REG_MCUSYS_EMI_ELM_WORDCNT_DURATION (BASE_ADDR_MCUSYS_ELM_EMI+0x528)
176 #define ELM_WC_ACCURACY(x) ((x)<<4) //[31:4]
177 #define ELM_WC_DURATION(x) ((x)<<0) // [3:0]
178 //wc duration length = (WORDCNT_DURATION+1)*(WORDCNT_ACCURACY+1) us
179
180#define REG_MCUSYS_EMI_ELM_INT_FRCVAL (BASE_ADDR_MCUSYS_ELM_EMI+0x530)
181#define REG_MCUSYS_EMI_ELM_SUBWINDOW_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x534)
182
183#define REG_MCUSYS_EMI_ELM_ID0_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x538)
184#define REG_MCUSYS_EMI_ELM_ID1_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x53C)
185#define REG_MCUSYS_EMI_ELM_ID2_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x540)
186#define REG_MCUSYS_EMI_ELM_ID3_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x544)
187
188#define REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x600)
189#define REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x604)
190#define REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x608)
191#define REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x60C)
192#define REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x610)
193#define REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x614)
194#define REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x618)
195#define REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x61C)
196 #define REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL 0x3fff
197
198#define REG_MCUSYS_EMI_ID0_URG_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x700)
199#define REG_MCUSYS_EMI_ID0_URG_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x704)
200#define REG_MCUSYS_EMI_ID0_URG_CTRL2 (BASE_ADDR_MCUSYS_ELM_EMI+0x708)
201#define REG_MCUSYS_EMI_ID1_URG_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x70c)
202#define REG_MCUSYS_EMI_ID1_URG_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x710)
203#define REG_MCUSYS_EMI_ID1_URG_CTRL2 (BASE_ADDR_MCUSYS_ELM_EMI+0x714)
204#define REG_MCUSYS_EMI_URG_IDLE_CLR_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x718)
205
206
207// MDINFRA ELM_A
208#define REG_MDINFRA_ELM_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0xC)
209#define REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x30)
210#define REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x34)
211#define REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0x38)
212#define REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MDINFRA_ELM+0x3C)
213#define REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x70)
214#define REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x74)
215#define REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x78)
216#define REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x7C)
217#define REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x80)
218#define REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x84)
219#define REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x88)
220#define REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x8C)
221
222#define REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_BLOCK (BASE_ADDR_MDINFRA_ELM+0x90)
223#define REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_BLOCK (BASE_ADDR_MDINFRA_ELM+0x94)
224#define REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_BLOCK (BASE_ADDR_MDINFRA_ELM+0x98)
225#define REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_BLOCK (BASE_ADDR_MDINFRA_ELM+0x9C)
226#define REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MDINFRA_ELM+0xA0)
227#define REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MDINFRA_ELM+0xA4)
228#define REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MDINFRA_ELM+0xA8)
229#define REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MDINFRA_ELM+0xAC)
230
231#define REG_MDINFRA_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB0)
232#define REG_MDINFRA_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB4)
233#define REG_MDINFRA_ELM_ID0_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x40)
234#define REG_MDINFRA_ELM_ID1_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x44)
235#define REG_MDINFRA_ELM_INT_STATUS (BASE_ADDR_MDINFRA_ELM+0x64)
236#define REG_MDINFRA_ELM_ID2_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x510)
237#define REG_MDINFRA_ELM_ID3_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x514)
238#define REG_MDINFRA_ELM_WORDCNT_DURATION (BASE_ADDR_MDINFRA_ELM+0x528)
239#define REG_MDINFRA_ELM_INT_FRCVAL (BASE_ADDR_MDINFRA_ELM+0x530)
240
241#define REG_MDINFRA_ELM_ID0_SUBWINDOW_STS (BASE_ADDR_MDINFRA_ELM+0x538)
242#define REG_MDINFRA_ELM_ID1_SUBWINDOW_STS (BASE_ADDR_MDINFRA_ELM+0x53C)
243#define REG_MDINFRA_ELM_ID2_SUBWINDOW_STS (BASE_ADDR_MDINFRA_ELM+0x540)
244#define REG_MDINFRA_ELM_ID3_SUBWINDOW_STS (BASE_ADDR_MDINFRA_ELM+0x544)
245
246
247//AO Register in MDPERIMISC
248#define REG_MDMCU_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x70) //0xA0060070
249#define REG_MDMCU_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x74) //0xA0060074
250#define REG_MDMCU_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x90) //0xA0060090
251#define REG_MDINFRA_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x78) //0xA0060078
252#define REG_MDINFRA_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x7C) //0xA006007C
253#define REG_MDINFRA_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x94) //0xA0060094
254
255/** ----- AP debugging register definition ------ **/
256#if defined(__MD97__) && !defined(MT6297)
257
258#define AP_VCORE_DVFS_CURRENT (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD44) // current dvfsrc level
259#define AP_VCORE_DVFS_TARGET (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD48)
260#define AP_VCORE_DVFS_LAST (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xAE4) // last dvfsrc level
261// SPM should sw config to record the time into register. Please double confirm with AP SPM owner in each project
262#define AP_DVFS_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x780)
263#define AP_DDREN_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x784)
264//#define AP_SYSTIMER_TICK (volatile kal_uint32 *)(0xC0006000+0x1B4)
265
266#else // Apollo
267#define AP_VCORE_DVFS_CURRENT (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD44) // current dvfsrc level
268#define AP_VCORE_DVFS_TARGET (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD48)
269#define AP_VCORE_DVFS_LAST (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xB08) // last dvfsrc level
270
271// SPM should sw config to record the time into register. Please double confirm with AP SPM owner in each project
272#define AP_DVFS_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x630)
273#define AP_DDREN_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x634)
274//#define AP_SYSTIMER_TICK (volatile kal_uint32 *)(0xC0006000+0x1B4)
275#endif
276
277#define AP_VCORE_MD_SCEN (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x700)
278#define AP_VCORE_MD_HRT_REQ (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x70C)
279#define AP_VCORE_TOT_HRT_REQ (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0x710)
280
281
282#include "sleepdrv_interface.h"
283
284// ELM Set Mode (HW/SW Mode)
285enum {
286 ELM_MODE_0 = 0, // ID0 trans_cnt, ID1 trans_cnt, ID0_lat_cnt, ID1_lat_cnt, id2_word_cnt, id3_word_cnt
287 ELM_MODE_2 = 2, // ID0 trans_cnt, ID1 trans_cnt, ID2 trans_cnt, ID3 trans_cnt, NA, NA
288};
289
290// (MT6297) MCUSYS/MDINFRA fixed clock 208Mhz, 1T ~ 4.8ns ; (97 others) MCUSYS fixed clock 650/3 Mhz, 1T ~ 4.6ns
291#if defined(MT6297)
292#define ELM_TRANS2NS(X) ((((((X)*1000)<<4)/208)>>4))
293#define ELM_NS2TRAN(X) ((((X)*208)/1000))
294#define ELM_MDINFRA_TRANS2NS(X) ((((((X)*1000)<<4)/208)>>4))
295#define ELM_MDINFRA_NS2TRAN(X) ((((X)*208)/1000))
296
297#else
298#define ELM_TRANS2NS(X) ((((((X)*1000)<<4)/(650/3))>>4))
299#define ELM_NS2TRAN(X) ((((X)*(650/3))/1000))
300#define ELM_MDINFRA_TRANS2NS(X) ((((((X)*1000)<<4)/(650/3))>>4))
301#define ELM_MDINFRA_NS2TRAN(X) ((((X)*(650/3))/1000))
302
303#endif
304
305
306
307typedef enum {
308 E_ELM_WC_B = 0,
309 E_ELM_WC_KB = 1,
310 E_ELM_WC_MB = 2,
311 E_ELM_WC_GB = 3,
312} ELM_WC_UNIT;
313//XB, X can be K(KB), M(MB), G(GB), using ELM_WC_UNIT to represent it.
314#define ELM_XB2WC(X, unit) (X<<(10*unit))>>2
315#define ELM_WC2XB(X, unit) ((X<<2)>>(10*unit))
316
317//for assert information
318#define KAL_ERROR_EMI_ELM_EXCEP 0x4100
319#define KAL_ERROR_INFRA_ELM_EXCEP 0x4102
320
321#define KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD 0x4200
322
323#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
324 #define __ELM_TRACE__
325 #define ELM_IF_DEF_TRACE(def_statement, undef_statement) def_statement
326#else /* __MCU_DORMANT_MODE__ */
327 #define ELM_IF_DEF_TRACE(def_statement, undef_statement) undef_statement
328#endif
329
330#define ELM_2ND_ASSERT_CHECK_DURATION 300
331
332#ifdef __MTK_TARGET__
333
334const kal_uint16 ELM_ACCURACY_TBL[] = {8,12,25,62,100,125,625,1000};
335
336#define ELM_WINDOW_COUNT 3
337const kal_uint32 ELM_WORD_CNT_WINDOW_TABLE[ELM_WINDOW_COUNT] = {200, 1000, 10000};
338// trace of BW warning threshold depends on ESL result: r+w 200us 1.6GB/s (5x)
339// 1ms: 3x, 10ms: 2x
340const kal_uint32 MDMCU_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[ELM_WINDOW_COUNT] = {320, 960, 6400};
341const kal_uint32 MDINFRA_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[ELM_WINDOW_COUNT] = {320, 960, 6400};
342kal_uint32 elm_mdmcu_window_select_idx = 0;
343kal_uint32 elm_mdinfra_window_select_idx = 0;
344
345static kal_uint32 current_elm_mdinfra_axid_sel_idx=0;
346kal_uint32 elm_mdinfra_axid_sel_idx = 0;
347#define M4_ELM_AXID_GRP_IDX 9
348kal_uint32 const m4_elm_axid_grp[M4_ELM_AXID_GRP_IDX*2] = { 0,0xf73307ff,//All
349 0,0xf733003f,//NRL2
350 0x100,0xf7330007,//RXDBRP_NR
351 0x200,0xF733007F,//MCORE
352 0x300,0xF733007F,//DFESYS
353 0x200,0xf7330007,//bigram
354 0x500,0xF733001F,//BRP0
355 0x600,0xF733003b,//log_top
356 0x604,0xF73300fb //trace_top,pppha,ipsec,gdma,dbgsys
357 };
358
359
360
361#ifdef ELM_AMIF_ENABLE
362kal_uint32 elm_read_lat_threshold = 2000;
363kal_uint32 elm_write_lat_threshold = 2000;
364#else
365kal_uint32 elm_read_lat_threshold = 450;
366kal_uint32 elm_write_lat_threshold = 300;
367#endif
368
369kal_uint8 emi_blocking_weight = 7;
370kal_uint32 elm_write_lat_2nd_threshold = 550;
371
372ELM_WC_UNIT elm_read_wc_unit = E_ELM_WC_KB;
373ELM_WC_UNIT elm_write_wc_unit = E_ELM_WC_KB;
374kal_uint32 elm_read_wc_threshold = 320;
375kal_uint32 elm_write_wc_threshold = 320;
376kal_uint32 elm_wc_dur_in_us = 200; // 200us
377
378kal_uint32 elm_infra_read_lat_threshold = 2000;
379kal_uint32 elm_infra_write_lat_threshold = 2000;
380ELM_WC_UNIT elm_infra_read_wc_unit = E_ELM_WC_KB;
381ELM_WC_UNIT elm_infra_write_wc_unit = E_ELM_WC_KB;
382kal_uint32 elm_infra_read_wc_threshold = 320;
383kal_uint32 elm_infra_write_wc_threshold = 320;
384kal_uint32 elm_infra_wc_dur_in_us = 200;
385
386kal_uint32 elm_dynamic_lat_threshold_disable = 0; //0 enable, 1 disable
387kal_uint32 elm_lat_accuracy = ELM_unit_25us ;
388kal_uint32 elm_lat_duration = 200;
389kal_uint32 elm_infra_lat_accuracy = ELM_unit_100us ;
390kal_uint32 elm_infra_lat_duration = 1000;
391kal_uint32 elm_trans_threshold = 100;
392kal_uint32 elm_mode = ELM_MODE_0;
393kal_uint32 elm_id2_rw = ELM_RD;
394kal_uint32 elm_id3_rw = ELM_WR;
395kal_uint32 elm_id0_master = ELM_ALL_MASTER;
396kal_uint32 elm_id0_rw = ELM_READ;
397kal_uint32 elm_id0_prio = ELM_ALL_PRIO;
398
399kal_uint32 elm_id1_master = ELM_ALL_MASTER;
400kal_uint32 elm_id1_rw = ELM_WRITE;
401kal_uint32 elm_id1_prio = ELM_ALL_PRIO;
402
403kal_uint32 elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
404kal_uint32 elm_id0_value = 5;
405kal_uint32 elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
406kal_uint32 elm_id1_value = 5;
407kal_uint32 elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
408
409// ID2/3 cnt default value target all transaction
410kal_uint32 elm_id2_value = 0;
411kal_uint32 elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
412kal_uint32 elm_id3_value = 0;
413kal_uint32 elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
414
415
416#if defined(__PRODUCTION_RELEASE__)
417elm_exception_type EMI_ELM_lat_irq_exception_type = ELM_NONE; //EMI latency irq default use trace
418elm_exception_type EMI_ELM_wc_irq_exception_type = ELM_NONE; //EMI wc irq default use trace
419elm_exception_type INFRA_ELM_lat_irq_exception_type = ELM_NONE; //INFRA latency irq default use trace
420elm_exception_type INFRA_ELM_wc_irq_exception_type = ELM_NONE; //INFRA wc irq default use trace
421#else
422/* under construction !*/
423/* under construction !*/
424/* under construction !*/
425/* under construction !*/
426#endif
427
428
429/*--- ELM history variable ---*/
430#define ELM_RUNTIME_HISTORY_SIZE 8
431
432//EMI ELM
433kal_uint32 emi_elm_runtime_lat_history_idx = 0;
434ELM_RUNTIME_PROFILE_LAT_T emi_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
435kal_uint32 emi_elm_runtime_wc_history_idx = 0;
436ELM_RUNTIME_PROFILE_WC_T emi_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
437//INFRA_A ELM
438kal_uint32 infra_elm_runtime_lat_history_idx = 0;
439ELM_RUNTIME_PROFILE_LAT_T infra_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
440kal_uint32 infra_elm_runtime_wc_history_idx = 0;
441ELM_RUNTIME_PROFILE_WC_T infra_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
442#if defined(MT6297)
443//INFRA_B ELM
444kal_uint32 infra_b_elm_runtime_lat_history_idx = 0;
445ELM_RUNTIME_PROFILE_LAT_T infra_b_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
446kal_uint32 infra_b_elm_runtime_wc_history_idx = 0;
447ELM_RUNTIME_PROFILE_WC_T infra_b_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
448#endif
449
450
451void elmtop_emi_isr_handler();
452void elm_infra_isr_handler();
453
454void Drv_ELM_Reset_Mdinfra_AXID_MASK()
455{
456 elm_dynamic_lat_threshold_disable = 1;
457 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_REG, m4_elm_axid_grp[0]);
458 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_REG, m4_elm_axid_grp[0]);
459 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_MASK, m4_elm_axid_grp[1]);
460 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_MASK, m4_elm_axid_grp[1]);
461
462 return ;
463}
464
465void Drv_ELM_Toggle(kal_uint8 info)
466{
467 elm_dynamic_lat_threshold_disable = 1;
468 if(info==0){
469 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
470 DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
471 }else{
472 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
473 DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
474 }
475 return ;
476}
477
478void Drv_ELM_Change_WC_Threshold(kal_uint8 info, kal_uint32 wc)
479{
480 kal_uint32 flag = ((info&0xF0)==0x0) ? 0 : 1;
481 kal_uint32 id23 = ((info&0xF)==0x0) ? 0 : 1;
482
483 elm_dynamic_lat_threshold_disable = 1;
484 if(flag==0)// mdmcu elm
485 {
486 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
487 if(id23==0)// id2
488 {
489 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH, wc);
490 }
491 else // id3
492 {
493 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH, wc);
494 }
495 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
496 }
497 else// mdinfra elm
498 {
499 DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
500 if(id23==0)// id2
501 {
502 DRV_WriteReg32(REG_MDINFRA_ELM_ID2_WORDCNT_TH, wc);
503 }
504 else // id3
505 {
506 DRV_WriteReg32(REG_MDINFRA_ELM_ID3_WORDCNT_TH, wc);
507 }
508 DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
509 }
510
511 return;
512}
513
514#define ELM_HISTORY_SIZE 64
515kal_uint32 elm_profile_history_idx_0 = 0;
516ELM_FULL_LOG_T elm_profile_history_0[ELM_HISTORY_SIZE];
517
518void Drv_ELM_Set_ID2_RW(kal_bool flag, kal_bool elm_toggle)
519{
520 if(flag)
521 {
522 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, 1<<23);
523 DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, 1<<23);
524 }
525 else
526 {
527 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, 1<<23);
528 DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, 1<<23);
529
530 //disable bigdata trace due to the trace type is determined by option
531 elm_dynamic_lat_threshold_disable = 1 ;
532 }
533
534 if(elm_toggle)
535 {
536 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
537 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
538 DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
539 DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
540 }
541}
542
543#define ELM_URGENT_READ_NS 300
544#define ELM_URGENT_WRITE_NS 200
545//the setting is based on sub-window = 25us
546#define ELM_URGENT_TRANS 10
547#define ELM_URGENT_SUBWIN 1
548
549void ELM_urgent_config()
550{
551 //set ID0 CTRL1 RG
552 DRV_WriteReg32(REG_MCUSYS_EMI_ID0_URG_CTRL1,
553 (ELM_NS2TRAN(ELM_URGENT_READ_NS)<<20)|
554 (ELM_URGENT_TRANS<<8)|(0x0<<4)|
555 (ELM_URGENT_SUBWIN<<2)|(1<<0));
556 //set ID1 CTRL1 RG
557 DRV_WriteReg32(REG_MCUSYS_EMI_ID1_URG_CTRL1,
558 (ELM_NS2TRAN(ELM_URGENT_WRITE_NS)<<20)|
559 (ELM_URGENT_TRANS<<8)|(0x0<<4)|
560 (ELM_URGENT_SUBWIN<<2)|(1<<0));
561 //keep urgent function enable when elm irq assert
562 DRV_WriteReg32(REG_MCUSYS_EMI_URG_IDLE_CLR_CTRL, 0x00030001);
563 return ;
564}
565
566void ELM_INIT(void)
567{
568/*MDMCU EMI ELM*/
569 //disable elm
570 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
571 //clear ELM interrupt
572 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); // clear ELM interrupt
573 //set to mode 0
574 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK)); // clear ELM mode
575 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK & elm_mode)); // select ELM mode
576 //ID select for ID2/3 (ID0/1 by ao_reg later)
577 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3)));
578 //set total latency weight for 2nd level detection (set to max-> DISABLE)
579 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_TOTAL_LAT_WEIGHT_BLOCK(emi_blocking_weight));
580 //ID0/1 trans count threshold
581 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_TH, elm_trans_threshold);
582 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_TH, elm_trans_threshold);
583 // config ID2/3 setting (config ID0/1 by ao_reg later)
584 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
585 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
586 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
587 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
588 //set word count threshold to 1.5GB/sec (both read and write)
589 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_read_wc_threshold, elm_read_wc_unit));
590 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_write_wc_threshold, elm_write_wc_unit));
591 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
592 //set ao_reg cfg1 (ID1 config)
593 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
594 ELM_EMI_TOP_BLOCK(E_TOP_MASK)|
595 DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
596 ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
597 EMI_BLOCK(E_NOT_MASK)|
598 ELM_INT_MASK(LAT_INT_UNMASK_ALL));
599 //set ao_reg cfg2 (threshold when emi blocking, wc int)
600 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG2,
601 LAT_TH_ID1_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_write_lat_threshold)))|
602 LAT_TH_ID0_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_read_lat_threshold)))|
603 ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
604 //subwindow enable; grand total mode
605 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_SUBWINDOW_CTRL, 1);
606
607 //set emi elm urgent
608 if(emi_elm_urgent_enable)
609 {
610 ELM_urgent_config();
611 }
612
613 //set ao_reg cfg0 (ELM enable, ID0 config, threshold when emi normal)
614 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG0,
615 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
616 LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
617 LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
618 DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
619
620#if 0 //IRQ register is done by IRQ centralization
621/* under construction !*/
622/* under construction !*/
623#endif
624 IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
625/* MDINFRA_A EMI ELM*/
626 //disable elm
627 DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
628 //clear ELM interrupt
629 DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL);
630 //set ID mode
631 //DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
632 DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
633 DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_TOTAL_LAT_WEIGHT_BLOCK(emi_blocking_weight));
634 //set trans threshold
635 DRV_WriteReg32(REG_MDINFRA_ELM_ID0_TRANS_TH, elm_trans_threshold);
636 DRV_WriteReg32(REG_MDINFRA_ELM_ID1_TRANS_TH, elm_trans_threshold);
637 // config word_cnt window setting
638 DRV_WriteReg32(REG_MDINFRA_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_infra_read_wc_threshold, elm_infra_read_wc_unit));
639 DRV_WriteReg32(REG_MDINFRA_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_infra_write_wc_threshold, elm_infra_write_wc_unit));
640 DRV_WriteReg32(REG_MDINFRA_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_infra_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
641 // set ao_reg cfg1 (ID1 csetting, duration, irq unmask)
642 DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG1,
643 ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_prio)|
644 ELM_DURATION(elm_infra_lat_duration/ELM_ACCURACY_TBL[elm_infra_lat_accuracy])|
645 EMI_BLOCK(E_NOT_MASK)|
646 ELM_INT_MASK(LAT_INT_UNMASK_ALL));
647 // set ao_reg cfg2 (threshold when emi blocking)
648 DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG2,
649 LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_write_lat_threshold)))|
650 LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_read_lat_threshold)))|
651 ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
652
653 kal_uint32 tmp_idx = (current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX)*2;
654 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_REG, m4_elm_axid_grp[tmp_idx]);
655 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_REG, m4_elm_axid_grp[tmp_idx]);
656 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_MASK, m4_elm_axid_grp[tmp_idx+1]);
657 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_MASK, m4_elm_axid_grp[tmp_idx+1]);
658
659 // set ao_reg cfg0 (elm enable, accuracy, threshold when emi normal, ID0 setting)
660 DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0,
661 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_infra_lat_accuracy)|
662 LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
663 LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
664 DECODE_ID0(elm_id0_rw|elm_id0_prio));
665#if defined(MT6297)
666/* MDINFRA_B EMI ELM */
667 //disable elm
668 DRV_ClrReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);// ao_cfg0
669 //clear ELM interrupt
670 DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x64, INT_MASK_ALL);
671 //set ID mode
672 //DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
673 DRV_SetReg32(BASE_ADDR_MDINFRA_ELM_B+0xc, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
674 //set trans threshold
675 DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x40, elm_trans_threshold);
676 DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x44, elm_trans_threshold);
677 // config word_cnt window setting
678 DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x510, ELM_XB2WC(elm_infra_read_wc_threshold, elm_infra_read_wc_unit));
679 DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x514, ELM_XB2WC(elm_infra_write_wc_threshold, elm_infra_write_wc_unit));
680 DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x528, ELM_WC_ACCURACY(elm_infra_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
681 // set ao_reg cfg1 (ID1 csetting, duration, irq unmask)
682 DRV_WriteReg32(BASE_ADDR_MDPERIMISC+0x584, ELM_EMI_TOP_BLOCK(E_TOP_MASK)|
683 DECODE_ID1(elm_id1_rw|elm_id1_prio)|
684 ELM_DURATION(elm_infra_lat_duration/ELM_ACCURACY_TBL[elm_infra_lat_accuracy])|
685 EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
686 // set ao_reg cfg2 (threshold when emi blocking)
687 DRV_WriteReg32(BASE_ADDR_MDPERIMISC+0x588,
688 LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_write_lat_threshold)))|
689 LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_read_lat_threshold)))|
690 ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
691 // set ao_reg cfg0 (elm enable, accuracy, threshold when emi normal, ID0 setting)
692 DRV_WriteReg32_NPW(BASE_ADDR_MDPERIMISC+0x580,
693 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_infra_lat_accuracy)|
694 LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
695 LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
696 DECODE_ID0(elm_id0_rw|elm_id0_prio));
697#endif
698
699#if 0 //IRQ register is done by ISR centralization
700/* under construction !*/
701/* under construction !*/
702#endif
703
704#ifdef ID2_SET_TO_RW
705 Drv_ELM_Set_ID2_RW(id2_rw_enable, KAL_TRUE);
706#endif
707
708 IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
709
710 return ;
711}
712
713void ELM_Config_DormantLeave(void)
714{
715 kal_uint32 vpe_idx;
716 vpe_idx = kal_get_current_vpe_id();
717 if(0 == vpe_idx)
718 {
719 ELM_INIT();
720 emi_elm_runtime_lat_history_idx =0;
721 memset((void*)emi_elm_runtime_lat_history,0, sizeof(ELM_RUNTIME_PROFILE_LAT_T)*ELM_RUNTIME_HISTORY_SIZE);
722 }
723}
724
725void ELM_Config_DormantEnter(void)
726{
727
728}
729
730void ELM_GET_FULL_LOG(ELM_FULL_LOG_T* data)
731{
732 if(NULL==data)
733 {
734 return;
735 }
736
737#ifdef __ELM_RUNTIME_PROFILE__
738 elm_profile_history_0[elm_profile_history_idx_0].fma_stamp = ust_get_current_time();
739 ELM_GET_LOG(0,elm_profile_history_0[elm_profile_history_idx_0]);
740 elm_profile_history_0[elm_profile_history_idx_0].r_lat_thr = elm_read_lat_threshold;
741 elm_profile_history_0[elm_profile_history_idx_0].w_lat_thr = elm_write_lat_threshold;
742 memcpy(data,&elm_profile_history_0[elm_profile_history_idx_0], sizeof(ELM_FULL_LOG_T));
743 elm_profile_history_idx_0 = (elm_profile_history_idx_0 + 1) % ELM_HISTORY_SIZE ;
744#else
745 data->fma_stamp = ust_get_current_time();
746 ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, 0, &(data->w_trans));
747 ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, 0, &(data->w_latency));
748 ELM_GET_WC_CNT(ELM_WR, 0, &(data->w_wordcount));
749 ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, 0, &(data->r_trans));
750 ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, 0, &(data->r_latency));
751 ELM_GET_WC_CNT(ELM_RD, 0, &(data->r_wordcount));
752#endif
753
754}
755
756kal_uint32 debug_emi_elm_runtime_counter = 0;
757kal_uint32 debug_MDMCU_elm_last_INT_FRC = 0;
758kal_uint32 debug_MDIFRA_elm_last_INT_FRC = 0;
759
760
761
762#define E_MAX16(x) ((x>0xFFFF)? 0xFFFF : x)
763
764kal_uint32 elm_md_dvfs_con = 0;
765kal_uint32 elm_ap_vcore_dvfs_current = 0;
766kal_uint32 elm_ap_vcore_dvfs_target = 0;
767kal_uint32 elm_ap_vcore_dvfs_last = 0;
768kal_uint32 elm_ap_vcore_md_scen = 0;
769kal_uint32 elm_ap_vcore_md_hrt_req = 0;
770kal_uint32 elm_ap_vcore_tot_hrt_req = 0;
771
772void elmtop_emi_isr_handler()
773{
774 kal_uint32 curr_frc = 0, enter_lisr_frc = 0;
775 kal_uint32 int_status = 0;
776 kal_uint32 read_trans_count = 0, write_trans_count = 0;
777 kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
778 kal_uint32 read_worst_ostd_cnt = 0, write_worst_ostd_cnt = 0;
779 kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
780 kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
781 kal_uint32 ia_13m_tick = 0, dvfs_13m_tick = 0, ddren_13m_tick = 0;
782 enter_lisr_frc = ust_get_current_time();
783 debug_emi_elm_runtime_counter++;
784
785 //Mask cirq ELM interrupt
786 IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
787 //stop ELM
788 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
789
790 curr_frc = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_FRCVAL);
791 int_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS);
792
793 /* Handling latency interrupt */
794 if(int_status & INT_MASK_LAT)
795 {
796 read_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
797 write_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
798 read_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL) );
799 write_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL) );
800 read_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL) );
801 write_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL) );
802 read_worst_ostd_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL);
803 write_worst_ostd_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL);
804
805 kal_uint32 emi_blocking = 0 ;
806 if((int_status & INT_MASK_LAT_AVG) &&
807 read_worst_latency_ns<elm_read_lat_threshold && write_worst_latency_ns<elm_write_lat_threshold)
808 {
809 read_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_BLOCK) );
810 write_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_BLOCK) );
811 read_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK);
812 write_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK);
813 read_worst_ostd_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK);
814 write_worst_ostd_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK);
815 emi_blocking = 1;
816 }
817 else if(int_status & INT_MASK_LAT_TOT)
818 {
819 read_trans_count = 0; write_trans_count = 0;
820 read_worst_ostd_cnt = 0; write_worst_ostd_cnt=0;
821 if(read_total_latency_ns<elm_read_lat_threshold*pow(2,emi_blocking_weight) &&
822 write_total_latency_ns<elm_write_lat_threshold*pow(2,emi_blocking_weight))
823 {
824 read_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_BLOCK) );
825 write_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_BLOCK) );
826 emi_blocking = 1;
827 }
828 }
829
830// Read AP side related debugging register
831#if defined(__ELM_MD97__)
832 ia_13m_tick = SleepDrv_GetWallClk(); //AP systimer
833 dvfs_13m_tick = *AP_DVFS_OCCUR_TICK;// last dvfs occur tick
834 ddren_13m_tick = *AP_DDREN_OCCUR_TICK;// last ddren occur tick
835 elm_ap_vcore_dvfs_current = *AP_VCORE_DVFS_CURRENT;
836 elm_ap_vcore_dvfs_target = *AP_VCORE_DVFS_TARGET;
837 elm_ap_vcore_dvfs_last = *AP_VCORE_DVFS_LAST;
838 elm_ap_vcore_md_scen = *AP_VCORE_MD_SCEN;
839 elm_ap_vcore_md_hrt_req = *AP_VCORE_MD_HRT_REQ;
840 elm_ap_vcore_tot_hrt_req = *AP_VCORE_TOT_HRT_REQ;
841#endif
842
843 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
844 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].enter_lisr_frc= enter_lisr_frc;
845 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
846 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
847 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
848 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
849 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat_maxost = read_worst_ostd_cnt;
850 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
851 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat_maxost = write_worst_ostd_cnt;
852 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
853 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
854 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_dvfs_tick = dvfs_13m_tick;
855 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_ddren_tick = ddren_13m_tick;
856 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].md_tick = ia_13m_tick;
857 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id0_subwindow_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_SUBWINDOW_STS);
858 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id1_subwindow_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_SUBWINDOW_STS);
859 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].emi_blocking = emi_blocking;
860 emi_elm_runtime_lat_history_idx++;
861
862 elm_md_dvfs_con = drv_mdap_interface_hw_get_curr_scenario_reg();
863
864 //for meta mode, there is no any l1 hrt check. change to trace mode anyway
865 //for spv usage, check elm_dynamic_lat_threshold_disable==1 to indicate local spv testing
866 if(kal_query_boot_mode()==FACTORY_BOOT && elm_dynamic_lat_threshold_disable==0)
867 {
868 EMI_ELM_lat_irq_exception_type = ELM_NONE;
869 }
870
871 switch(EMI_ELM_lat_irq_exception_type)
872 {
873 case ELM_NONE:
874 {
875 //read latency over criteria
876 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
877 {
878 ELM_IF_DEF_TRACE( \
879 MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
880 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
881 dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
882 );
883 }
884 //write latency over criteria
885 else
886 {
887 ELM_IF_DEF_TRACE( \
888 MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
889 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
890 dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
891 );
892 }
893 break;
894 }
895 case ELM_ASSERT:
896 {
897 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
898 {
899 EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
900 (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
901 (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
902 }
903 else
904 {
905 EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
906 (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
907 (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
908 }
909 break;
910 }
911 case ELM_ASSERT_AT_2nd:
912 {
913 // just show trace on first time over criteria in 300us
914 if(debug_MDMCU_elm_last_INT_FRC == 0)
915 {
916 debug_MDMCU_elm_last_INT_FRC = curr_frc;
917 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
918 {
919 ELM_IF_DEF_TRACE( \
920 MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
921 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
922 dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
923 );
924 }
925 else
926 {
927 ELM_IF_DEF_TRACE( \
928 MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
929 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
930 dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
931 );
932 }
933 }
934 else
935 {
936 if(ust_us_duration(debug_MDMCU_elm_last_INT_FRC, curr_frc) < ELM_2ND_ASSERT_CHECK_DURATION)
937 {
938 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
939 {
940 EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
941 (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
942 (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
943 }
944 else
945 {
946 //bypass 2nd assertion for write latency violation on swift tool env
947 //the violation latency is about 300~400ns but no any performance issue occurred
948 //bypass the assertion to let SQC stable and analyze offline
949 if(write_worst_latency_ns>=elm_write_lat_2nd_threshold){
950 EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
951 (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
952 (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
953 }else{
954 ELM_IF_DEF_TRACE( \
955 MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
956 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
957 dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
958 );
959 }
960 }
961 }
962 else
963 {
964 debug_MDMCU_elm_last_INT_FRC = curr_frc;
965 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
966 {
967 ELM_IF_DEF_TRACE( \
968 MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
969 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
970 dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
971 );
972 }
973 else
974 {
975 ELM_IF_DEF_TRACE( \
976 MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
977 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last,\
978 dvfs_13m_tick, ddren_13m_tick, ia_13m_tick, emi_blocking), \
979 );
980 }
981 }
982 }
983 break;
984 }
985 default:
986 break;
987 }
988
989 }
990 /* Handling word count interrupt */
991 else
992 {
993#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
994 kal_uint32 infra_elm_irq_status = DRV_Reg32(REG_MDINFRA_ELM_INT_STATUS);
995 kal_uint32 infra_elm_id2_worst_wc=0, infra_elm_id3_worst_wc=0;
996
997 //stop infra elm for bigdata
998 if(!(infra_elm_irq_status & INT_MASK_WC))
999 {
1000 DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1001 infra_elm_id2_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID2_WORST_WORD_CNT);
1002 infra_elm_id3_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID3_WORST_WORD_CNT);
1003 DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1004 }
1005#endif
1006 read_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT);
1007 write_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT);
1008
1009 kal_uint32 R_BW_in_MB = read_worst_wc*4/elm_wc_dur_in_us;
1010 kal_uint32 W_BW_in_MB = write_worst_wc*4/elm_wc_dur_in_us;
1011
1012 emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
1013 emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
1014 emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
1015 emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
1016 emi_elm_runtime_wc_history_idx++;
1017
1018 //check config mode: assertion or trace
1019 switch(EMI_ELM_wc_irq_exception_type)
1020 {
1021 case ELM_NONE:
1022 {
1023 // Read wordcount violation
1024 if(int_status & ID2_TOT_WC_INT)
1025 {
1026 if(id2_rw_enable)
1027 {
1028 ELM_IF_DEF_TRACE( \
1029 MD_TRC_EMI_ELM_RW_BW_WARN(curr_frc, R_BW_in_MB, elm_read_wc_threshold*1000/elm_wc_dur_in_us, elm_wc_dur_in_us,\
1030 infra_elm_id2_worst_wc, infra_elm_id3_worst_wc, W_BW_in_MB), \
1031 );
1032#if defined(__SPV_MPB_MEMSET_MEMCPY_M3_BW_CORRELATION__)
1033 spv_mpb_m3_bw_warn_cb(curr_frc, elm_wc_dur_in_us, R_BW_in_MB);
1034#endif
1035 }
1036 else
1037 {
1038 ELM_IF_DEF_TRACE( \
1039 MD_TRC_EMI_ELM_R_BW_WARN(curr_frc, R_BW_in_MB, elm_read_wc_threshold*1000/elm_wc_dur_in_us, elm_wc_dur_in_us,\
1040 infra_elm_id2_worst_wc, infra_elm_id3_worst_wc), \
1041 );
1042 }
1043 }
1044 else
1045 {
1046 ELM_IF_DEF_TRACE( \
1047 MD_TRC_EMI_ELM_W_BW_WARN(curr_frc, W_BW_in_MB, elm_write_wc_threshold*1000/elm_wc_dur_in_us, elm_wc_dur_in_us,\
1048 infra_elm_id2_worst_wc, infra_elm_id3_worst_wc), \
1049 );
1050 }
1051 break;
1052 }
1053 case ELM_ASSERT:
1054 {
1055 // Read wordcount violation
1056 if(int_status & ID2_TOT_WC_INT)
1057 {
1058 EXT_ASSERT(0, curr_frc, R_BW_in_MB, elm_read_wc_threshold*1000/elm_wc_dur_in_us);
1059 }
1060 else
1061 {
1062 EXT_ASSERT(0, curr_frc, W_BW_in_MB, elm_write_wc_threshold*1000/elm_wc_dur_in_us);
1063
1064 }
1065 break;
1066 }
1067 default:
1068 break;
1069 }
1070 }
1071
1072 //Clear ELM interrupt after read irq type
1073 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL);
1074
1075 //enable ELM
1076 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1077
1078 IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
1079 return ;
1080
1081}
1082
1083void elm_infra_isr_handler()
1084{
1085 kal_uint32 curr_frc = 0;
1086 kal_uint32 int_status = 0;
1087#if defined(MT6297)
1088 kal_uint32 int_status_b = 0;
1089#endif
1090 kal_uint32 read_trans_count = 0, write_trans_count = 0;
1091 kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
1092 kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
1093 kal_uint32 read_worst_ostd_cnt = 0, write_worst_ostd_cnt = 0;
1094
1095 kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
1096
1097 //Mask cirq ELM interrupt
1098 IRQMask(IRQ_ELM_DMA_IRQ_CODE);
1099
1100 //stop elm
1101 DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1102#if defined(MT6297)
1103 DRV_ClrReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
1104#endif
1105 //curr_frc = ust_get_current_time();
1106
1107 //read INT status
1108 int_status = DRV_Reg32(REG_MDINFRA_ELM_INT_STATUS);
1109#if defined(MT6297)
1110 int_status_b = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x64);
1111#endif
1112
1113 /* Handling latency interrupt */
1114 if(int_status & INT_MASK_LAT)
1115 {
1116 curr_frc = DRV_Reg32(REG_MDINFRA_ELM_INT_FRCVAL);
1117 read_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
1118 write_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
1119 read_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL) );
1120 write_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL) );
1121 read_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL) );
1122 write_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL) );
1123 read_worst_ostd_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL);
1124 write_worst_ostd_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL);
1125
1126 kal_uint32 emi_blocking = 0;
1127 if(int_status&INT_MASK_LAT_AVG &&
1128 read_worst_latency_ns<elm_infra_read_lat_threshold && write_worst_latency_ns<elm_infra_write_lat_threshold)
1129 {
1130 read_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK);
1131 write_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK);
1132 read_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_BLOCK) );
1133 write_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_BLOCK) );
1134 read_worst_ostd_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK);
1135 write_worst_ostd_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK);
1136 emi_blocking = 1;
1137 }
1138 else if(int_status&INT_MASK_LAT_TOT)
1139 {
1140 read_trans_count = 0; write_trans_count = 0;
1141 read_worst_ostd_cnt = 0; write_worst_ostd_cnt = 0;
1142 if(read_total_latency_ns<elm_infra_read_lat_threshold*pow(2,emi_blocking_weight) &&
1143 write_total_latency_ns<elm_infra_write_lat_threshold*pow(2,emi_blocking_weight))
1144 {
1145 read_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_BLOCK) );
1146 write_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_BLOCK) );
1147 emi_blocking = 1;
1148 }
1149 }
1150
1151 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
1152 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
1153 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
1154 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
1155 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
1156 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
1157 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
1158 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
1159 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat_maxost = read_worst_ostd_cnt;
1160 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat_maxost = write_worst_ostd_cnt;
1161 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id0_subwindow_status = DRV_Reg32(REG_MDINFRA_ELM_ID0_SUBWINDOW_STS);
1162 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id1_subwindow_status = DRV_Reg32(REG_MDINFRA_ELM_ID1_SUBWINDOW_STS);
1163 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].emi_blocking = emi_blocking;
1164 infra_elm_runtime_lat_history_idx++;
1165
1166 switch(INFRA_ELM_lat_irq_exception_type)
1167 {
1168 case ELM_NONE:
1169 {
1170#ifdef __ELM_TRACE__
1171 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
1172 {
1173 MD_TRC_INFRA_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_infra_read_lat_threshold, read_total_latency_ns, read_trans_count,
1174 read_worst_ostd_cnt, emi_blocking);
1175 }
1176 else
1177 {
1178 MD_TRC_INFRA_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_infra_write_lat_threshold, write_total_latency_ns, write_trans_count,
1179 write_worst_ostd_cnt, emi_blocking);
1180 }
1181#endif
1182 break;
1183 }
1184 default:
1185 break;
1186 }
1187 }
1188 /* Handling word count interrupt */
1189 else if(int_status & INT_MASK_WC)
1190 {
1191#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
1192 kal_uint32 mcu_elm_irq_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS);
1193 kal_uint32 mcu_elm_id2_worst_wc=0, mcu_elm_id3_worst_wc=0;
1194 //stop mcu elm for bigdata
1195 if(!(mcu_elm_irq_status & INT_MASK_WC))
1196 {
1197 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1198 mcu_elm_id2_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT);
1199 mcu_elm_id3_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT);
1200 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1201 }
1202#endif
1203 curr_frc = DRV_Reg32(REG_MDINFRA_ELM_INT_FRCVAL);
1204 read_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID2_WORST_WORD_CNT);
1205 write_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID3_WORST_WORD_CNT);
1206
1207 kal_uint32 R_BW_in_MB = read_worst_wc*4/elm_infra_wc_dur_in_us;
1208 kal_uint32 W_BW_in_MB = write_worst_wc*4/elm_infra_wc_dur_in_us;
1209
1210 infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
1211 infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
1212 infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
1213 infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
1214 infra_elm_runtime_wc_history_idx++;
1215
1216 switch(INFRA_ELM_wc_irq_exception_type)
1217 {
1218 case ELM_NONE:
1219 {
1220 // Read wordcount violation
1221 if(int_status & ID2_TOT_WC_INT)
1222 {
1223 if(id2_rw_enable)
1224 {
1225 ELM_IF_DEF_TRACE( \
1226 MD_TRC_INFRA_ELM_RW_BW_WARN(curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us,\
1227 mcu_elm_id2_worst_wc, mcu_elm_id3_worst_wc, MDINFRA_ELM_AXID_GRP(current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX), W_BW_in_MB),\
1228 );
1229 }
1230 else
1231 {
1232 ELM_IF_DEF_TRACE( \
1233 MD_TRC_INFRA_ELM_R_BW_WARN(curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us,\
1234 mcu_elm_id2_worst_wc, mcu_elm_id3_worst_wc, MDINFRA_ELM_AXID_GRP(current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX)), \
1235 );
1236 }
1237 }
1238 else
1239 {
1240 ELM_IF_DEF_TRACE( \
1241 MD_TRC_INFRA_ELM_W_BW_WARN(curr_frc, W_BW_in_MB, elm_infra_write_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us,\
1242 mcu_elm_id2_worst_wc, mcu_elm_id3_worst_wc, MDINFRA_ELM_AXID_GRP(current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX)), \
1243 );
1244 }
1245 break;
1246 }
1247 case ELM_ASSERT:
1248 {
1249 // Read wordcount violation
1250 if(int_status & ID2_TOT_WC_INT)
1251 {
1252 EXT_ASSERT(0, curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us);
1253 }
1254 else
1255 {
1256 EXT_ASSERT(0, curr_frc, W_BW_in_MB, elm_infra_write_wc_threshold*1000/elm_infra_wc_dur_in_us);
1257 }
1258 break;
1259 }
1260 default:
1261 break;
1262 }
1263 }
1264
1265#if defined(MT6297)
1266 if(int_status_b & INT_MASK_LAT)
1267 {
1268 curr_frc = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x530);
1269 read_trans_count = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x80);
1270 write_trans_count = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x84);
1271 read_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x70) );
1272 write_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x78) );
1273 read_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x74) );
1274 write_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x7c) );
1275
1276 infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
1277 infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status_b;
1278 infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
1279 infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
1280 infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
1281 infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
1282 infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
1283 infra_b_elm_runtime_lat_history[infra_b_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
1284 infra_b_elm_runtime_lat_history_idx++;
1285 switch(INFRA_ELM_lat_irq_exception_type)
1286 {
1287 case ELM_NONE:
1288 {
1289#ifdef __ELM_TRACE__
1290 if(int_status_b & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
1291 {
1292 MD_TRC_INFRA_ELM_B_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_infra_read_lat_threshold, read_total_latency_ns, read_trans_count);
1293 }
1294 else
1295 {
1296 MD_TRC_INFRA_ELM_B_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_infra_write_lat_threshold, write_total_latency_ns, write_trans_count);
1297 }
1298#endif
1299 break;
1300 }
1301 default:
1302 break;
1303 }
1304 }
1305 else if(int_status_b & INT_MASK_WC)
1306 {
1307 curr_frc = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x530);
1308 read_worst_wc = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0xb0);
1309 write_worst_wc = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0xb4);
1310
1311 kal_uint32 R_BW_in_MB = read_worst_wc*4/elm_infra_wc_dur_in_us;
1312 kal_uint32 W_BW_in_MB = write_worst_wc*4/elm_infra_wc_dur_in_us;
1313
1314 infra_b_elm_runtime_wc_history[infra_b_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
1315 infra_b_elm_runtime_wc_history[infra_b_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status_b;
1316 infra_b_elm_runtime_wc_history[infra_b_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
1317 infra_b_elm_runtime_wc_history[infra_b_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
1318 infra_b_elm_runtime_wc_history_idx++;
1319
1320 switch(INFRA_ELM_wc_irq_exception_type)
1321 {
1322 case ELM_NONE:
1323 {
1324 // Read wordcount violation
1325 if(int_status_b & ID2_TOT_WC_INT)
1326 {
1327 if(id2_rw_enable)
1328 {
1329 ELM_IF_DEF_TRACE( \
1330 MD_TRC_INFRA_ELM_B_RW_BW_WARN(curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us), \
1331 );
1332 }
1333 else
1334 {
1335 ELM_IF_DEF_TRACE( \
1336 MD_TRC_INFRA_ELM_B_R_BW_WARN(curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us), \
1337 );
1338 }
1339 }
1340 else
1341 {
1342 ELM_IF_DEF_TRACE( \
1343 MD_TRC_INFRA_ELM_B_W_BW_WARN(curr_frc, W_BW_in_MB, elm_infra_write_wc_threshold*1000/elm_infra_wc_dur_in_us, elm_infra_wc_dur_in_us), \
1344 );
1345 }
1346 break;
1347 }
1348 case ELM_ASSERT:
1349 {
1350 // Read wordcount violation
1351 if(int_status_b & ID2_TOT_WC_INT)
1352 {
1353 EXT_ASSERT(0, curr_frc, R_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us);
1354 }
1355 else
1356 {
1357 EXT_ASSERT(0, curr_frc, W_BW_in_MB, elm_infra_read_wc_threshold*1000/elm_infra_wc_dur_in_us);
1358 }
1359 break;
1360 }
1361 default:
1362 break;
1363 }
1364 }
1365#endif
1366
1367
1368 //Clear ELM interrupt after read irq type
1369 DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL); //clear M4_A ELM interrupt
1370#if defined(MT6297)
1371 DRV_WriteReg32(BASE_ADDR_MDINFRA_ELM_B+0x64, INT_MASK_ALL); //clear M4_B ELM interrupt
1372#endif
1373
1374 //Enable ELM
1375 DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1376#if defined(MT6297)
1377 DRV_SetReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
1378#endif
1379
1380 IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
1381
1382}
1383
1384void ELM_MCU_threshold_change_lightweight(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
1385{
1386 kal_uint32 mask_state=0;
1387
1388 if(elm_dynamic_lat_threshold_disable)
1389 {
1390 return;
1391 }
1392
1393 mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
1394
1395 //Mask cirq ELM interrupt
1396 IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
1397
1398 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); //disable ELM
1399
1400 // kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
1401
1402
1403 elm_read_lat_threshold = read_avg_lat_ns;
1404 elm_write_lat_threshold = write_avg_lat_ns;
1405 elm_lat_duration= dur_us;
1406
1407 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
1408 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG2,
1409 LAT_TH_ID1_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_write_lat_threshold)))|
1410 LAT_TH_ID0_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_read_lat_threshold)))|
1411 ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
1412 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
1413 ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
1414 ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
1415 EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
1416 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
1417 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
1418 LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
1419 LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
1420 DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
1421
1422 // kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
1423
1424 if(!mask_state)
1425 {
1426 IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
1427 }
1428}
1429
1430void ELM_MCU_threshold_change(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
1431{
1432 kal_uint32 mask_state=0;
1433
1434 if(elm_dynamic_lat_threshold_disable)
1435 {
1436 return;
1437 }
1438
1439 if((read_avg_lat_ns<200) || (write_avg_lat_ns<200) || (dur_us<200))
1440 {
1441 kal_uint32 lr = 0;
1442 kal_uint32 sub_error_code = 0;
1443 GET_RETURN_ADDRESS(lr);
1444 if(read_avg_lat_ns<200)
1445 {
1446 sub_error_code = 1;
1447 }
1448 else if(write_avg_lat_ns<200)
1449 {
1450 sub_error_code = 2;
1451 }
1452 else
1453 {
1454 sub_error_code = 3;
1455 }
1456 EXT_ASSERT(0, lr, KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD, sub_error_code);
1457 }
1458
1459
1460
1461 mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
1462
1463 //Mask cirq ELM interrupt
1464 IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
1465
1466 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE); //disable ELM
1467
1468 kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
1469
1470
1471 elm_read_lat_threshold = read_avg_lat_ns;
1472 elm_write_lat_threshold = write_avg_lat_ns;
1473 elm_lat_duration= dur_us;
1474
1475 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
1476 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG2,
1477 LAT_TH_ID1_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_write_lat_threshold)))|
1478 LAT_TH_ID0_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_read_lat_threshold)))|
1479 ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
1480 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
1481 ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
1482 ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
1483 EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
1484 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
1485 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
1486 LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
1487 LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
1488 DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
1489
1490 kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
1491
1492#ifdef __ELM_TRACE__
1493 {
1494 // L1 trace
1495 kal_uint32 curr_frc = 0;
1496 curr_frc = ust_get_current_time();
1497 MD_TRC_EMI_ELM_SET_R_TH(curr_frc, elm_read_lat_threshold);
1498 MD_TRC_EMI_ELM_SET_W_TH(curr_frc, elm_write_lat_threshold);
1499 }
1500#endif
1501
1502 if(!mask_state)
1503 {
1504 IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
1505 }
1506
1507}
1508
1509#if 0//def __ELM_RUNTIME_PROFILE__
1510/* under construction !*/
1511/* under construction !*/
1512/* under construction !*/
1513/* under construction !*/
1514/* under construction !*/
1515/* under construction !*/
1516/* under construction !*/
1517/* under construction !*/
1518/* under construction !*/
1519/* under construction !*/
1520/* under construction !*/
1521/* under construction !*/
1522/* under construction !*/
1523/* under construction !*/
1524/* under construction !*/
1525/* under construction !*/
1526/* under construction !*/
1527/* under construction !*/
1528/* under construction !*/
1529/* under construction !*/
1530/* under construction !*/
1531/* under construction !*/
1532/* under construction !*/
1533/* under construction !*/
1534/* under construction !*/
1535/* under construction !*/
1536/* under construction !*/
1537/* under construction !*/
1538/* under construction !*/
1539/* under construction !*/
1540/* under construction !*/
1541/* under construction !*/
1542#endif
1543
1544kal_uint8 _ELM_latency_status(void)
1545{
1546#ifdef __ELM_RUNTIME_PROFILE__
1547
1548 //if emi_elm_runtime_lat_history_idx == 0, means that it didn't enter ELM isr handler once, it will all be zero
1549 if(emi_elm_runtime_lat_history_idx != 0)
1550 {
1551 kal_uint32 int_status = 0;
1552 int_status = emi_elm_runtime_lat_history[(emi_elm_runtime_lat_history_idx-1)%ELM_RUNTIME_HISTORY_SIZE].int_status;
1553
1554 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
1555 {
1556 return 0xAE; //EMI read latency may be too long
1557 }
1558 else
1559 {
1560 return 0xBE; //EMI write latency may be too long
1561 }
1562 }
1563 return 0xDE; // EMI read/write latency are OK.
1564#else
1565 return 0xFF; //no ELM info
1566#endif
1567}
1568
1569/******************************************************************************
1570* function : void set_emi_elm_exceptiontype(kal_bool lat_flag, kal_uint8 exception_type)
1571* description : this function is called when set emi elm read/write latency/wordcount exception type
1572* parameter : kal_uint8 exception_type: 0,1,2
1573* return : void
1574******************************************************************************/
1575kal_bool Set_EMI_ELM_ExceptionType(kal_uint8 exception_type)
1576{
1577 switch (exception_type)
1578 {
1579 case ELM_NONE:
1580 {
1581 EMI_ELM_lat_irq_exception_type = ELM_NONE;
1582 break;
1583 }
1584
1585 case ELM_ASSERT:
1586 {
1587 EMI_ELM_lat_irq_exception_type = ELM_ASSERT;
1588 break;
1589 }
1590 case ELM_ASSERT_AT_2nd:
1591 {
1592 EMI_ELM_lat_irq_exception_type = ELM_ASSERT_AT_2nd;
1593 break;
1594 }
1595 default:
1596 return KAL_FALSE;
1597 break;
1598 }
1599 return KAL_TRUE;
1600}
1601
1602kal_bool Set_EMI_ELM_Threshold(kal_uint8 info, kal_uint32 threshold)
1603{
1604 ELM_IF_DEF_TRACE(kal_uint32 curr_frc = 0,);
1605 ELM_IF_DEF_TRACE(curr_frc = ust_get_current_time(),);
1606 elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
1607 if((info&0xF0))
1608 { // infra
1609 //Disable before re-configure
1610 DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
1611#if defined(MT6297)
1612 DRV_WriteReg32_NPW(BASE_ADDR_MDINFRA_ELM_B+0x580, ELM_DISABLE);
1613#endif
1614 if( info & 0x01 )
1615 {
1616 elm_infra_read_lat_threshold = threshold;
1617 ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_R_TH(curr_frc, threshold),);
1618 }
1619 else
1620 {
1621 elm_infra_write_lat_threshold = threshold;
1622 ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_W_TH(curr_frc, threshold),);
1623 }
1624 //M4_A ELM
1625
1626 //set block latency threshold
1627 DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG2,
1628 LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
1629 LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
1630 ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
1631 //set normal latency threshold to target and enable elm
1632 DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0,
1633 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
1634 LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
1635 LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
1636 DECODE_ID0(elm_id0_rw|elm_id0_prio));
1637
1638#if defined(MT6297)
1639 //set block latency threshold
1640 DRV_WriteReg32_NPW(BASE_ADDR_MDPERIMISC+0x558,
1641 LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
1642 LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
1643 ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
1644 //M4_B ELM
1645 DRV_WriteReg32_NPW(BASE_ADDR_MDPERIMISC+0x580,
1646 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
1647 LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
1648 LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
1649 DECODE_ID0(elm_id0_rw|elm_id0_prio));
1650#endif
1651 }
1652 else
1653 { //mdmcu
1654
1655 //Disable before re-configure
1656 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1657 if( info & 0x01 )
1658 {
1659 elm_read_lat_threshold = threshold;
1660 ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_R_TH(curr_frc, threshold),);
1661 }
1662 else
1663 {
1664 elm_write_lat_threshold = threshold;
1665 ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_W_TH(curr_frc, threshold),);
1666 }
1667 //set block latency threshold
1668 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG2,
1669 LAT_TH_ID1_BLOCK(ELM_NS2TRAN(elm_write_lat_threshold))|
1670 LAT_TH_ID0_BLOCK(ELM_NS2TRAN(elm_read_lat_threshold))|
1671 ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
1672 //set normal latency threshold to target and enable elm
1673 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)| \
1674 LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
1675 DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
1676 }
1677
1678
1679 return KAL_TRUE;
1680}
1681
1682/******************************************************************************
1683* function : kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
1684* description : ELM has 4 counters(ID 0,1,2,3), this function is used to set EMI ELM's
1685* counter to monitro read or write transaction and master.
1686* parameter :
1687* kal_uint8 id: 0, 1, 0xFF;
1688* -> Assume id 0,2 use same configuration(so does id 1,3), including read/write and masters.
1689* -> 0xFF is used for let all ID monitor same masters.
1690* return : void
1691******************************************************************************/
1692
1693//!!!! AXID RELATED API !!!!
1694kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
1695{
1696 kal_bool rtn = KAL_TRUE;
1697
1698 //Disable before re-configure
1699 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1700 elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
1701
1702 if(id == 0) // id 0 (default read), assume id2 use same master as id 0
1703 {
1704 elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
1705 if(m_sel==0)
1706 {
1707 elm_id0_master = ELM_ALL_MASTER;
1708
1709 elm_id2_value = 0;
1710 elm_id2_mask |= MASTER_DEFAULT_MASK;
1711 }
1712 else if(m_sel==1)
1713 {
1714 elm_id0_master = ELM_MDMCU_ONLY;
1715
1716 elm_id2_value = MASTER_MDMCU;
1717 elm_id2_mask |= MASTER_MDMCU_MASK;
1718 }
1719 else if(m_sel==2)
1720 {
1721 elm_id0_master = ELM_USIP_ONLY;
1722
1723 elm_id2_value = MASTER_USIP;
1724 elm_id2_mask |= MASTER_USIP_MASK;
1725 }
1726 else
1727 {
1728 rtn = KAL_FALSE;
1729 }
1730
1731 if(rw == 0)
1732 {
1733 elm_id0_rw = ELM_READ;
1734 elm_id2_rw = ELM_RD;
1735 }
1736 else if(rw == 1)
1737 {
1738 elm_id0_rw = ELM_WRITE;
1739 elm_id2_rw = ELM_WR;
1740 }
1741 else
1742 {
1743 rtn = KAL_FALSE;
1744 }
1745 }
1746 else if( id == 1 ) // id 1 (default write), assume id3 use same master as id 1
1747 {
1748 elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
1749 if(m_sel==0)
1750 {
1751 elm_id1_master = ELM_ALL_MASTER;
1752
1753 elm_id3_value = 0;
1754 elm_id3_mask |= MASTER_DEFAULT_MASK;
1755 }
1756 else if(m_sel==1)
1757 {
1758 elm_id1_master = ELM_MDMCU_ONLY;
1759
1760 elm_id3_value = MASTER_MDMCU;
1761 elm_id3_mask |= MASTER_MDMCU_MASK;
1762 }
1763 else if(m_sel==2)
1764 {
1765 elm_id1_master = ELM_USIP_ONLY;
1766
1767 elm_id3_value = MASTER_USIP;
1768 elm_id3_mask |= MASTER_USIP_MASK;
1769 }
1770 else
1771 {
1772 rtn = KAL_FALSE;
1773 }
1774
1775 if(rw == 0)
1776 {
1777 elm_id1_rw = ELM_READ;
1778 elm_id3_rw = ELM_RD;
1779 }
1780 else if(rw == 1)
1781 {
1782 elm_id1_rw = ELM_WRITE;
1783 elm_id3_rw = ELM_WR;
1784 }
1785 else
1786 {
1787 rtn = KAL_FALSE;
1788 }
1789 }
1790 else if(id == 0xFF) // ID 0/1/2/3 are the same master, 0,2 for read, 1,3 for write
1791 {
1792 elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
1793 elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
1794
1795 elm_id0_rw = ELM_READ;
1796 elm_id1_rw = ELM_WRITE;
1797 elm_id2_rw = ELM_RD;
1798 elm_id3_rw = ELM_WR;
1799 if(m_sel==0)
1800 {
1801 elm_id0_master = ELM_ALL_MASTER;
1802 elm_id1_master = ELM_ALL_MASTER;
1803 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_AO_DECODE(ELM_DECODE_FROM_AO));
1804
1805 elm_id2_value = 0;
1806 elm_id2_mask |= MASTER_DEFAULT_MASK;
1807 elm_id3_value = 0;
1808 elm_id3_mask |= MASTER_DEFAULT_MASK;
1809 }
1810 else if(m_sel==1)
1811 {
1812 elm_id0_master = ELM_MDMCU_ONLY;
1813 elm_id1_master = ELM_MDMCU_ONLY;
1814 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_AO_DECODE(ELM_DECODE_FROM_AO));
1815
1816 elm_id2_value = MASTER_MDMCU;
1817 elm_id2_mask |= MASTER_MDMCU_MASK;
1818 elm_id3_value = MASTER_MDMCU;
1819 elm_id3_mask |= MASTER_MDMCU_MASK;
1820 }
1821 else if(m_sel==2)
1822 {
1823 elm_id0_master = ELM_USIP_ONLY;
1824 elm_id1_master = ELM_USIP_ONLY;
1825 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_AO_DECODE(ELM_DECODE_FROM_AO));
1826
1827 elm_id2_value = MASTER_USIP;
1828 elm_id2_mask |= MASTER_USIP_MASK;
1829 elm_id3_value = MASTER_USIP;
1830 elm_id3_mask |= MASTER_USIP_MASK;
1831 }
1832 else if(m_sel==3)
1833 {
1834 elm_id2_value = MASTER_MCORE;
1835 elm_id2_mask |= MASTER_MCORE_MASK;
1836 elm_id3_value = MASTER_MCORE;
1837 elm_id3_mask |= MASTER_MCORE_MASK;
1838
1839 //id0/1 filter do not have mcore option. Use APB mode
1840 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, elm_id2_value);
1841 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, elm_id2_mask);
1842 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, elm_id3_value);
1843 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, elm_id3_mask);
1844 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_AO_DECODE(ELM_DECODE_FROM_AO));
1845 }
1846 else
1847 {
1848 rtn = KAL_FALSE;
1849 }
1850 }
1851 else
1852 {
1853 rtn = KAL_FALSE;
1854 }
1855
1856 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
1857 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
1858 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
1859 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
1860 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
1861 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
1862
1863 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
1864 ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
1865 ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
1866 EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
1867
1868 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
1869 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
1870 LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
1871 LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
1872 DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
1873 return rtn;
1874}
1875
1876
1877kal_bool Set_EMI_ELM_Mode(kal_uint8 mode)
1878{
1879 kal_bool rtn = KAL_TRUE;
1880 //Disable elm
1881 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1882 DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1883#if defined(MT6297)
1884 DRV_ClrReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
1885#endif
1886 elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
1887
1888 if( mode == 0)
1889 {
1890 elm_mode = ELM_MODE_0;
1891 }
1892 else if( mode == 2)
1893 {
1894 elm_mode = ELM_MODE_2;
1895 elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
1896 //mdmcu elm
1897 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
1898 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
1899 //mdinfra_a elm
1900 DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
1901 DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
1902#if defined(MT6297)
1903 //mdinfra_b elm
1904 DRV_ClrReg32(BASE_ADDR_MDINFRA_ELM_B+0xc, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
1905 DRV_SetReg32(BASE_ADDR_MDINFRA_ELM_B+0xc, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
1906#endif
1907 }
1908 else
1909 {
1910 rtn = KAL_FALSE;
1911 }
1912 //Set mode & enable elm
1913 //mdmcu elm
1914 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
1915 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
1916 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1917 //mdinfra_a elm
1918 DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
1919 DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
1920 DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1921 //mdinfra_b elm
1922#if defined(MT6297)
1923 DRV_ClrReg32(BASE_ADDR_MDINFRA_ELM_B+0xc, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
1924 DRV_SetReg32(BASE_ADDR_MDINFRA_ELM_B+0xc, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
1925 DRV_SetReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
1926#endif
1927 return rtn;
1928}
1929
1930//!!!! AXID RELATED API !!!!
1931kal_bool Set_EMI_ELM_uSIP_Core(kal_uint8 id, kal_uint8 thread_val, kal_uint8 port_sel)
1932{
1933 kal_bool rtn = KAL_TRUE;
1934 kal_uint32 assembled_axid=0, assembled_axid_mask=0; // [13]
1935 kal_uint16 usip_core=0, usip_thread=0 ;
1936
1937 //Disable ELM
1938 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1939 //disable dynamic latency threshold
1940 elm_dynamic_lat_threshold_disable = 1;
1941 //elm id setting from apb
1942 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
1943
1944 usip_core = thread_val/2 ;
1945 usip_thread = thread_val%2 ;
1946
1947 if(usip_core==1){
1948 assembled_axid |= (1<<1) ;
1949 }
1950 assembled_axid |= (usip_thread<<4);
1951
1952 switch(port_sel)
1953 {
1954 case 0:
1955 assembled_axid_mask |= (1<<6) ;
1956 break;
1957 case 1:
1958 assembled_axid |= (1<<3);
1959 assembled_axid_mask |= (1<<6) ;
1960 break;
1961 case 2:
1962 assembled_axid |= (1<<0);
1963 assembled_axid_mask |= (0x7<<6);
1964 break;
1965 case 3:
1966 assembled_axid |= (1<<0);
1967 assembled_axid_mask |= (0x3<<6);
1968 break;
1969 default: //monitor all ports
1970 assembled_axid_mask |= 0x1CD ;
1971 break;
1972 }
1973
1974 assembled_axid = (assembled_axid<<2) | 0x2 ;
1975 assembled_axid_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_DEFAULT_MASK)) | (assembled_axid_mask<<2) ;
1976 //config AXID value/mask
1977 if(id==0)
1978 {
1979 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, assembled_axid);
1980 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, assembled_axid_mask);
1981 }
1982 else if(id==1)
1983 {
1984 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, assembled_axid);
1985 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, assembled_axid_mask);
1986 }
1987 else if(id==2)
1988 {
1989 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, assembled_axid);
1990 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, assembled_axid_mask);
1991 }
1992 else
1993 {
1994 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, assembled_axid);
1995 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, assembled_axid_mask);
1996 }
1997
1998 //Enable ELM
1999 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
2000 return rtn;
2001}
2002
2003//!!!! SIDEBAND RELATED API !!!!
2004kal_bool Set_EMI_ELM_VPE(kal_uint8 id, kal_uint8 vpe_sel)
2005{
2006 kal_bool rtn = KAL_TRUE;
2007 kal_uint32 sideband_val = 0 ;
2008 //Disable ELM
2009 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
2010 //disable dynamic latency threshold
2011 elm_dynamic_lat_threshold_disable = 1;
2012 //elm id setting from apb
2013 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
2014
2015 //calculate vpe sideband value
2016 if(vpe_sel >= SYS_MCU_NUM_VPE)
2017 {
2018 return KAL_FALSE ;
2019 }
2020 else
2021 {
2022 kal_uint8 core_id= vpe_sel/(SYS_MCU_NUM_VPE/SYS_MCU_NUM_CORE);
2023 kal_uint8 vpe_id = vpe_sel%(SYS_MCU_NUM_VPE/SYS_MCU_NUM_CORE);
2024 sideband_val = (core_id<<6) | ((vpe_id+1)<<4) ;
2025 }
2026
2027 //config ID sideband value/mask
2028 if(id==0)
2029 {
2030 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, sideband_val);
2031 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, 0);
2032 }
2033 else if(id==1)
2034 {
2035 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, sideband_val);
2036 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, 0);
2037 }
2038 else if(id==2)
2039 {
2040 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, sideband_val);
2041 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, 0);
2042 }
2043 else if(id==3)
2044 {
2045 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, sideband_val);
2046 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, 0);
2047 }
2048 else
2049 { //reset to default
2050 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, 0);
2051 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
2052 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, 0);
2053 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
2054 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, 0);
2055 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
2056 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, 0);
2057 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
2058 }
2059
2060 //Enable ELM
2061 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
2062 return rtn;
2063}
2064
2065kal_bool Set_EMI_ELM_ID_SIDEBAND(kal_uint16 sideband_val, kal_uint16 sideband_mask)
2066{
2067 kal_bool rtn = KAL_TRUE;
2068 //Disable before re-configure
2069 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
2070 //disable dynamic latency threshold
2071 elm_dynamic_lat_threshold_disable = 1;
2072 //elm id setting from apb
2073 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
2074
2075 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, sideband_val);//REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL
2076 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, sideband_mask);
2077 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, sideband_val);
2078 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, sideband_mask);
2079 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, sideband_val);
2080 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, sideband_mask);
2081 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, sideband_val);
2082 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, sideband_mask);
2083
2084 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
2085 return rtn;
2086}
2087
2088void EMI_ELM_GET_MAX_LOG(ELM_MAX_LOG_T *st)
2089{
2090#if !defined(__MPB_DISABLE__)
2091 if(elm_dynamic_lat_threshold_disable==1){
2092 return ;
2093 }
2094
2095 st->m3_max_r_word_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT);
2096 st->m3_max_w_word_cnt = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT);
2097 st->m4_max_r_word_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID2_WORST_WORD_CNT);
2098 st->m4_max_w_word_cnt = DRV_Reg32(REG_MDINFRA_ELM_ID3_WORST_WORD_CNT);
2099#if defined(MT6297)
2100 st->m4b_max_r_word_cnt = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x80);
2101 st->m4b_max_w_word_cnt = DRV_Reg32(BASE_ADDR_MDINFRA_ELM_B+0x84);
2102#endif
2103#endif
2104 return;
2105}
2106#if !defined(__MPB_DISABLE__)
2107static kal_uint32 current_elm_mdmcu_window_select_idx=0;
2108static kal_uint32 current_elm_mdinfra_window_select_idx=0;
2109#endif
2110void EMI_ELM_AMIF_SCENARIO_CHANGE_LOGGING(ELM_MAX_LOG_T t)
2111{
2112#if !defined(__MPB_DISABLE__)
2113
2114 kal_uint32 int_status;
2115 if(elm_dynamic_lat_threshold_disable==1){
2116 return ;
2117 }
2118
2119#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
2120 kal_uint32 mdmcu_elm_wrost_rlat = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL) );;
2121 kal_uint32 mdmcu_elm_wrost_wlat = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL) );;
2122 kal_uint32 mdinfra_elm_wrost_rlat = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL) );
2123 kal_uint32 mdinfra_elm_wrost_wlat = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL) );
2124#endif
2125
2126 //print trace
2127#ifdef ID2_SET_TO_RW
2128 ELM_IF_DEF_TRACE( \
2129 MD_TRC_EMI_ELM_RW_AMIF_SCEN_CHANGE_LOG(t.m3_max_r_word_cnt, t.m3_max_w_word_cnt, elm_wc_dur_in_us, mdmcu_elm_wrost_rlat,mdmcu_elm_wrost_wlat, elm_lat_duration), \
2130 );
2131 ELM_IF_DEF_TRACE( \
2132 MD_TRC_INFRA_ELM_RW_AMIF_SCEN_CHANGE_LOG(t.m4_max_r_word_cnt, t.m4_max_w_word_cnt, elm_infra_wc_dur_in_us, mdinfra_elm_wrost_rlat, mdinfra_elm_wrost_wlat,MDINFRA_ELM_AXID_GRP(current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX), elm_infra_lat_duration), \
2133 );
2134#endif
2135
2136#if defined(MT6297)
2137 ELM_IF_DEF_TRACE( \
2138 MD_TRC_INFRA_B_ELM_AMIF_SCEN_CHANGE_LOG(t.m4b_max_r_word_cnt, t.m4b_max_w_word_cnt, elm_infra_wc_dur_in_us), \
2139 );
2140#endif
2141
2142 //check elm int status to ensure no reset when latency problem happen
2143 //toggle elm to reset max value
2144 int_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS) ;
2145 if(int_status == 0)
2146 {
2147 //disable mdmcu elm
2148 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
2149 //change word count window:
2150 if(current_elm_mdmcu_window_select_idx != elm_mdmcu_window_select_idx){
2151 kal_uint32 tmp_idx = current_elm_mdmcu_window_select_idx%ELM_WINDOW_COUNT;
2152 // change elm global variable
2153 elm_wc_dur_in_us = ELM_WORD_CNT_WINDOW_TABLE[tmp_idx];
2154 elm_read_wc_threshold = MDMCU_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[tmp_idx];
2155 elm_write_wc_threshold = MDMCU_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[tmp_idx];
2156 // change elm register
2157 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_read_wc_threshold, elm_read_wc_unit));
2158 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_write_wc_threshold, elm_write_wc_unit));
2159 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
2160
2161 current_elm_mdmcu_window_select_idx = elm_mdmcu_window_select_idx ;
2162 }
2163
2164 //enable mdmcu elm
2165 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
2166
2167 //disable infra elm
2168 DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
2169 //change word count window
2170 if(current_elm_mdinfra_window_select_idx != elm_mdinfra_window_select_idx){
2171 kal_uint32 tmp_idx = current_elm_mdinfra_window_select_idx%ELM_WINDOW_COUNT;
2172 // change elm global variable
2173 elm_infra_wc_dur_in_us = ELM_WORD_CNT_WINDOW_TABLE[tmp_idx];
2174 elm_infra_read_wc_threshold = MDINFRA_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[tmp_idx];
2175 elm_infra_write_wc_threshold = MDINFRA_ELM_WORD_CNT_THRESHOLD_IN_WINDOW[tmp_idx];
2176 // change elm register
2177 DRV_WriteReg32(REG_MDINFRA_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_infra_read_wc_threshold, elm_infra_read_wc_unit));
2178 DRV_WriteReg32(REG_MDINFRA_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_infra_write_wc_threshold, elm_infra_write_wc_unit));
2179 DRV_WriteReg32(REG_MDINFRA_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_infra_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
2180
2181 current_elm_mdinfra_window_select_idx = elm_mdinfra_window_select_idx ;
2182 }
2183
2184 if(current_elm_mdinfra_axid_sel_idx != elm_mdinfra_axid_sel_idx)
2185 {
2186 current_elm_mdinfra_axid_sel_idx = elm_mdinfra_axid_sel_idx ;
2187 kal_uint32 tmp_idx = (current_elm_mdinfra_axid_sel_idx%M4_ELM_AXID_GRP_IDX)*2;
2188 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_REG, m4_elm_axid_grp[tmp_idx]);
2189 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_REG, m4_elm_axid_grp[tmp_idx]);
2190 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID2_CTRL_MASK, m4_elm_axid_grp[tmp_idx+1]);
2191 DRV_WriteReg32(REG_MDINFRA_EMI_ELM_AXI_ID3_CTRL_MASK, m4_elm_axid_grp[tmp_idx+1]);
2192 }
2193
2194 // enable infra elm
2195 DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
2196#if defined(MT6297)
2197 DRV_ClrReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
2198 DRV_SetReg32(BASE_ADDR_MDPERIMISC+0x580, ELM_ENABLE);
2199#endif
2200 }
2201
2202#endif
2203 return ;
2204}
2205#endif