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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / devdrv / elm / src / md97p / elm.c
blob: 3a648e3297ca794f830488fe56e150b4603dcc6e [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1#include "elm.h"
2#include "drv_comm.h"
3#include "us_timer.h"
4#include "kal_public_api.h"
5#include "kal_hrt_api.h"
6#include "intrCtrl.h"
7#include "drv_mdap_interface.h" //for show MD_DVFS_CON in trace
8
9#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
10// for profiling ELM log
11#include "TrcMod.h" //for L1 Trace API
12#endif
13
14/** ----- Register definition ------ **/
15
16
17// MDMCU ELM
18#define REG_MCUSYS_EMI_ELM_CODA_VERSION (BASE_ADDR_MCUSYS_ELM_EMI+0x0)
19#define REG_MCUSYS_EMI_ELM_EN_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x8)
20#define REG_MCUSYS_EMI_ELM_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0xC)
21 #define ELM_MODE(x) ((x)<<4)
22 #define ELM_MODE_MASK 0x3
23 #define ELM_AO_DECODE(x) ((x)<<13)
24 #define ELM_DECODE_FROM_AO 1
25 #define ELM_DECODE_FROM_APB 0
26 #define ELM_MODE_ID_SEL(x) (x<<8)
27 #define ELM_MODE_ID_MASK 0xC //clear ID2/3 only
28 #define ELM_ID_RW(rw, id) (rw<<id) //rw: 0->r; 1->w; id: 0, 1, 2, 3
29 #define ELM_TOTAL_LAT_WEIGHT_BLOCK(x) (x<<20) //[22:20]
30#define REG_MCUSYS_EMI_ELM_LAT_CNT_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x10)
31#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x20)
32
33 #define ALEN(x) ((x)<<28) //4'hf
34 #define ASIZE(x) ((x)<<24) //3'h7
35 #define AULTRA(x) ((x)<<20) //2'h3
36 #define ABUST(x) ((x)<<16) //2'h3
37 #define AID(x) ((x)<<0) //12'h1FFF
38 #define MASTER_DEFAULT_MASK 0x1FFF //defualt value
39 #define MASTER_ALL_MASK 0x3 //IA: 0x0, MMU: 0x1, USIP: 0x2
40 #define MASTER_MDMCU 0x0 //MDMCU(Incluing IA & MMU)
41 #define MASTER_MDMCU_MASK 0x1FFD
42 #define MASTER_USIP 0x2 //USIP -> 0x2
43 #define MASTER_USIP_MASK 0x1FFC
44
45
46#define REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x24)
47#define ELM_AO_CONTROL_DEFAULT 0xF7331FFF
48
49#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x28)
50#define REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x2C)
51#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x30)
52#define REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x34)
53#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG (BASE_ADDR_MCUSYS_ELM_EMI+0x38)
54#define REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK (BASE_ADDR_MCUSYS_ELM_EMI+0x3C)
55#define REG_MCUSYS_EMI_ELM_ID0_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x40)
56#define REG_MCUSYS_EMI_ELM_ID1_TRANS_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x44)
57#define REG_MCUSYS_EMI_ELM_CNT0 (BASE_ADDR_MCUSYS_ELM_EMI+0x50)
58#define REG_MCUSYS_EMI_ELM_CNT1 (BASE_ADDR_MCUSYS_ELM_EMI+0x54)
59#define REG_MCUSYS_EMI_ELM_CNT2 (BASE_ADDR_MCUSYS_ELM_EMI+0x58)
60#define REG_MCUSYS_EMI_ELM_CNT3 (BASE_ADDR_MCUSYS_ELM_EMI+0x5C)
61#define REG_MCUSYS_EMI_ELM_OVERRUN_CNT_ST (BASE_ADDR_MCUSYS_ELM_EMI+0x60)
62#define REG_MCUSYS_EMI_ELM_INT_STATUS (BASE_ADDR_MCUSYS_ELM_EMI+0x64)
63
64#define REG_MCUSYS_EMI_ELM_ID0_URG_FLGA_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x700)
65#define REG_MCUSYS_EMI_ELM_ID0_URG_FLGA_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x704)
66#define REG_MCUSYS_EMI_ELM_ID1_URG_FLGA_CTRL0 (BASE_ADDR_MCUSYS_ELM_EMI+0x70C)
67#define REG_MCUSYS_EMI_ELM_ID1_URG_FLGA_CTRL1 (BASE_ADDR_MCUSYS_ELM_EMI+0x710)
68#define REG_MCUSYS_EMI_ELM_URG_IDLE_CLR_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x718)
69
70
71
72
73
74 #define INT_MASK_ALL 0x3F
75 #define INT_MASK_LAT 0xF
76 #define INT_MASK_WC 0x30
77 #define ID0_AVG_LAT_INT (1<<0)
78 #define ID0_TOT_LAT_INT (1<<1)
79 #define ID1_AVG_LAT_INT (1<<2)
80 #define ID1_TOT_LAT_INT (1<<3)
81 #define ID2_TOT_WC_INT (1<<4)
82 #define ID3_TOT_WC_INT (1<<5)
83#define REG_MCUSYS_EMI_ELM_AO_STATUS0 (BASE_ADDR_MCUSYS_ELM_EMI+0x68)
84 #define DECODE_ID0(x) ((x)<<0)
85 #define ELM_READ (0<<4)
86 #define ELM_WRITE (1<<4)
87 #define ELM_ALL_MASTER (0<<2)
88 #define ELM_MDMCU_ONLY (1<<2)
89 #define ELM_USIP_ONLY (2<<2)
90 #define ELM_ALL_PRIO (0<<0)
91 #define ELM_PRE_ULTRA (1<<0)
92 #define ELM_ULTRA (2<<0)
93 #define LAT_TH_ID0_NORMAL(x) ((x)<<5)
94 #define LAT_TH_ID1_NORMAL(x) ((x)<<15)
95 #define ELM_ACCURACY(x) ((x)<<29)
96 #define ELM_unit_25us 2
97 #define ELM_unit_100us 4
98 #define ELM_ENABLE (1<<27)
99 #define ELM_DISABLE (0<<27)
100 #define ELM_IDLE_ENABLE (1<<28)
101 #define ELM_IDLE_DISABLE (0<<28)
102#define REG_MCUSYS_EMI_ELM_AO_STATUS1 (BASE_ADDR_MCUSYS_ELM_EMI+0x6C)
103 #define ELM_INT_MASK(x) ((x)<<0)
104 #define LAT_INT_MASK_ALL 0xF
105 #define LAT_INT_UNMASK_ALL 0x0
106 #define EMI_BLOCK(x) ((x)<<4)
107 #define E_NOT_MASK 0
108 #define E_MASK 1
109 #define ELM_DURATION(x) ((x-1)<<5)
110 #define DECODE_ID1(x) ((x)<<12)
111 /* #define usage same as DECODE_ID0 */
112 #define ELM_EMI_TOP_BLOCK(x) ((x)<<31)
113 #define E_TOP_MASK 1
114 #define E_TOP_NOT_MASK 0
115#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x70)
116#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x74)
117#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x78)
118#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x7C)
119#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x80)
120#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x84)
121#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x88)
122#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL (BASE_ADDR_MCUSYS_ELM_EMI+0x8C)
123#define REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x90)
124#define REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x94)
125#define REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x98)
126#define REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0x9C)
127#define REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA0)
128#define REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA4)
129#define REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xA8)
130#define REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_BLOCK (BASE_ADDR_MCUSYS_ELM_EMI+0xAC)
131#define REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB0)
132#define REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xB4)
133#define REG_MCUSYS_EMI_ELM_ID0_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xC0)
134#define REG_MCUSYS_EMI_ELM_ID0_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xC4)
135#define REG_MCUSYS_EMI_ELM_ID0_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xC8)
136#define REG_MCUSYS_EMI_ELM_ID0_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xCC)
137#define REG_MCUSYS_EMI_ELM_ID1_LAST_FLAG (BASE_ADDR_MCUSYS_ELM_EMI+0xD0)
138#define REG_MCUSYS_EMI_ELM_ID1_LAST_AVG_LAT (BASE_ADDR_MCUSYS_ELM_EMI+0xD4)
139#define REG_MCUSYS_EMI_ELM_ID1_LAST_TRANS_CNT (BASE_ADDR_MCUSYS_ELM_EMI+0xD8)
140#define REG_MCUSYS_EMI_ELM_ID1_LAST_MAXOST (BASE_ADDR_MCUSYS_ELM_EMI+0xDC)
141#define REG_MCUSYS_EMI_ELM_CNT4 (BASE_ADDR_MCUSYS_ELM_EMI+0xE0)
142#define REG_MCUSYS_EMI_ELM_CNT5 (BASE_ADDR_MCUSYS_ELM_EMI+0xE4)
143#define REG_MCUSYS_EMI_ELM_AO_STATUS2 (BASE_ADDR_MCUSYS_ELM_EMI+0xF0)
144 #define ELM_WC_INT_MASK(x) ((x)<<0)
145 #define WC_INT_MASK_ALL 0x3
146 #define WC_INT_UNMASK_ALL 0x0
147 #define LAT_TH_ID0_BLOCK(x) ((x)<<4)
148 #define LAT_TH_ID1_BLOCK(x) ((x)<<16)
149#if 0
150/* under construction !*/
151/* under construction !*/
152/* under construction !*/
153/* under construction !*/
154/* under construction !*/
155/* under construction !*/
156/* under construction !*/
157#endif
158#define REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x510)
159#define REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH (BASE_ADDR_MCUSYS_ELM_EMI+0x514)
160#define REG_MCUSYS_EMI_ELM_WORDCNT_DURATION (BASE_ADDR_MCUSYS_ELM_EMI+0x528)
161 #define ELM_WC_ACCURACY(x) ((x)<<4) //[31:4]
162 #define ELM_WC_DURATION(x) ((x)<<0) // [3:0]
163 //wc duration length = (WORDCNT_DURATION+1)*(WORDCNT_ACCURACY+1) us
164
165#define REG_MCUSYS_EMI_ELM_INT_FRCVAL (BASE_ADDR_MCUSYS_ELM_EMI+0x530)
166#define REG_MCUSYS_EMI_ELM_SUBWINDOW_CTRL (BASE_ADDR_MCUSYS_ELM_EMI+0x534)
167
168#define REG_MCUSYS_EMI_ELM_ID0_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x538)
169#define REG_MCUSYS_EMI_ELM_ID1_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x53C)
170#define REG_MCUSYS_EMI_ELM_ID2_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x540)
171#define REG_MCUSYS_EMI_ELM_ID3_SUBWINDOW_STS (BASE_ADDR_MCUSYS_ELM_EMI+0x544)
172
173#define REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x600)
174#define REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x604)
175#define REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x608)
176#define REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x60C)
177#define REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x610)
178#define REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x614)
179#define REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x618)
180#define REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1 (BASE_ADDR_MCUSYS_ELM_EMI+0x61C)
181 #define REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL 0x3fff
182// MDINFRA ELM_A
183#define REG_MDINFRA_ELM_CTRL_REG (BASE_ADDR_MDINFRA_ELM+0xC)
184#define REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x70)
185#define REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x74)
186#define REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x78)
187#define REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL (BASE_ADDR_MDINFRA_ELM+0x7C)
188#define REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x80)
189#define REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL (BASE_ADDR_MDINFRA_ELM+0x84)
190#define REG_MDINFRA_ELM_ID2_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB0)
191#define REG_MDINFRA_ELM_ID3_WORST_WORD_CNT (BASE_ADDR_MDINFRA_ELM+0xB4)
192#define REG_MDINFRA_ELM_ID0_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x40)
193#define REG_MDINFRA_ELM_ID1_TRANS_TH (BASE_ADDR_MDINFRA_ELM+0x44)
194#define REG_MDINFRA_ELM_INT_STATUS (BASE_ADDR_MDINFRA_ELM+0x64)
195#define REG_MDINFRA_ELM_ID2_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x510)
196#define REG_MDINFRA_ELM_ID3_WORDCNT_TH (BASE_ADDR_MDINFRA_ELM+0x514)
197#define REG_MDINFRA_ELM_WORDCNT_DURATION (BASE_ADDR_MDINFRA_ELM+0x528)
198#define REG_MDINFRA_ELM_INT_FRCVAL (BASE_ADDR_MDINFRA_ELM+0x530)
199
200//AO Register in MDPERIMISC
201#define REG_MDMCU_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x70) //0xA0060070
202#define REG_MDMCU_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x74) //0xA0060074
203#define REG_MDMCU_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x90) //0xA0060090
204#define REG_MDINFRA_ELM_AO_STATUS_CFG0 (BASE_ADDR_MDPERIMISC+0x78) //0xA0060078
205#define REG_MDINFRA_ELM_AO_STATUS_CFG1 (BASE_ADDR_MDPERIMISC+0x7C) //0xA006007C
206#define REG_MDINFRA_ELM_AO_STATUS_CFG2 (BASE_ADDR_MDPERIMISC+0x94) //0xA0060094
207
208/** ----- AP debugging register definition ------ **/
209#if 1 //defined(MT3967)
210#define AP_VCORE_DVFS_CURRENT (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD44) // current dvfsrc level
211#define AP_VCORE_DVFS_TARGET (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xD48)
212#define AP_VCORE_DVFS_LAST (volatile kal_uint32 *)(BASE_ADDR_AP_VCORE_DVFS+0xB08) // last dvfsrc level
213
214// SPM should sw config to record the time into register. Please double confirm with AP SPM owner in each project
215#define AP_DVFS_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x630)
216#define AP_DDREN_OCCUR_TICK (volatile kal_uint32 *)(0xC0006000+0x634)
217#define AP_SYSTIMER_TICK (volatile kal_uint32 *)(0xC0006000+0x1B4)
218#endif
219
220#include "sleepdrv_interface.h"
221
222// ELM Set Mode (HW/SW Mode)
223enum {
224 ELM_MODE_0 = 0, // ID0 trans_cnt, ID1 trans_cnt, ID0_lat_cnt, ID1_lat_cnt, id2_word_cnt, id3_word_cnt
225 ELM_MODE_2 = 2, // ID0 trans_cnt, ID1 trans_cnt, ID2 trans_cnt, ID3 trans_cnt, NA, NA
226};
227
228//MCUSYS fixed clock 650/3 Mhz, 1T ~ 4.6ns
229#define ELM_TRANS2NS(X) ((((((X)*1000)<<4)/(650/3))>>4))
230#define ELM_NS2TRAN(X) ((((X)*(650/3))/1000))
231
232
233//MDINFRA fixed clock 100Mhz, 1T = 10ns
234#define ELM_MDINFRA_TRANS2NS(X) (((X)*10))
235#define ELM_MDINFRA_NS2TRAN(X) (((X)/10))
236
237typedef enum {
238 E_ELM_WC_B = 0,
239 E_ELM_WC_KB = 1,
240 E_ELM_WC_MB = 2,
241 E_ELM_WC_GB = 3,
242} ELM_WC_UNIT;
243//XB, X can be K(KB), M(MB), G(GB), using ELM_WC_UNIT to represent it.
244#define ELM_XB2WC(X, unit) (X<<(10*unit))>>2
245#define ELM_WC2XB(X, unit) ((X<<2)>>(10*unit))
246
247//for assert information
248#define KAL_ERROR_EMI_ELM_EXCEP 0x4100
249#define KAL_ERROR_INFRA_ELM_EXCEP 0x4102
250
251#define KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD 0x4200
252
253#if (defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__))
254 #define __ELM_TRACE__
255 #define ELM_IF_DEF_TRACE(def_statement, undef_statement) def_statement
256#else /* __MCU_DORMANT_MODE__ */
257 #define ELM_IF_DEF_TRACE(def_statement, undef_statement) undef_statement
258#endif
259
260#define ELM_2ND_ASSERT_CHECK_DURATION 300
261
262#ifdef __MTK_TARGET__
263
264const kal_uint16 ELM_ACCURACY_TBL[] = {8,12,25,62,100,125,625,1000};
265
266#ifdef ELM_AMIF_ENABLE
267kal_uint32 elm_read_lat_threshold = 2000;
268kal_uint32 elm_write_lat_threshold = 2000;
269#else
270kal_uint32 elm_read_lat_threshold = 450;
271kal_uint32 elm_write_lat_threshold = 300;
272#endif
273ELM_WC_UNIT elm_read_wc_unit = E_ELM_WC_KB;
274ELM_WC_UNIT elm_write_wc_unit = E_ELM_WC_KB;
275kal_uint32 elm_read_wc_threshold = 300;
276kal_uint32 elm_write_wc_threshold = 300;
277kal_uint32 elm_wc_dur_in_us = 200;
278
279kal_uint32 elm_infra_read_lat_threshold = 2000;
280kal_uint32 elm_infra_write_lat_threshold = 2000;
281ELM_WC_UNIT elm_infra_read_wc_unit = E_ELM_WC_MB;
282ELM_WC_UNIT elm_infra_write_wc_unit = E_ELM_WC_MB;
283kal_uint32 elm_infra_read_wc_threshold = 15;
284kal_uint32 elm_infra_write_wc_threshold = 15;
285kal_uint32 elm_infra_wc_dur_in_us = 10*1000; // 10ms
286
287kal_uint32 elm_dynamic_lat_threshold_disable = 0; //0 enable, 1 disable
288kal_uint32 elm_lat_accuracy = ELM_unit_25us ;
289kal_uint32 elm_lat_duration = 200;
290kal_uint32 elm_trans_threshold = 100;
291kal_uint32 elm_mode = ELM_MODE_0;
292kal_uint32 elm_id2_rw = ELM_RD;
293kal_uint32 elm_id3_rw = ELM_WR;
294kal_uint32 elm_id0_master = ELM_ALL_MASTER;
295kal_uint32 elm_id0_rw = ELM_READ;
296kal_uint32 elm_id0_prio = ELM_ALL_PRIO;
297
298kal_uint32 elm_id1_master = ELM_ALL_MASTER;
299kal_uint32 elm_id1_rw = ELM_WRITE;
300kal_uint32 elm_id1_prio = ELM_ALL_PRIO;
301
302kal_uint32 elm_ao_decode_cfg = ELM_DECODE_FROM_AO;
303kal_uint32 elm_id0_value = 5;
304kal_uint32 elm_id0_mask = ELM_AO_CONTROL_DEFAULT;
305kal_uint32 elm_id1_value = 5;
306kal_uint32 elm_id1_mask = ELM_AO_CONTROL_DEFAULT;
307
308// ID2/3 cnt default value target all transaction
309kal_uint32 elm_id2_value = 0;
310kal_uint32 elm_id2_mask = ELM_AO_CONTROL_DEFAULT;
311kal_uint32 elm_id3_value = 0;
312kal_uint32 elm_id3_mask = ELM_AO_CONTROL_DEFAULT;
313
314
315#if defined(__PRODUCTION_RELEASE__)
316elm_exception_type EMI_ELM_lat_irq_exception_type = ELM_NONE; //EMI latency irq default use trace
317elm_exception_type EMI_ELM_wc_irq_exception_type = ELM_NONE; //EMI wc irq default use trace
318elm_exception_type INFRA_ELM_lat_irq_exception_type = ELM_NONE; //INFRA latency irq default use trace
319elm_exception_type INFRA_ELM_wc_irq_exception_type = ELM_NONE; //INFRA wc irq default use trace
320#else
321/* under construction !*/
322/* under construction !*/
323/* under construction !*/
324/* under construction !*/
325#endif
326
327
328/*--- ELM history variable ---*/
329#define ELM_RUNTIME_HISTORY_SIZE 8
330
331//EMI ELM
332kal_uint32 emi_elm_runtime_lat_history_idx = 0;
333ELM_RUNTIME_PROFILE_LAT_T emi_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
334kal_uint32 emi_elm_runtime_wc_history_idx = 0;
335ELM_RUNTIME_PROFILE_WC_T emi_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
336//INFRA_A ELM
337kal_uint32 infra_elm_runtime_lat_history_idx = 0;
338ELM_RUNTIME_PROFILE_LAT_T infra_elm_runtime_lat_history[ELM_RUNTIME_HISTORY_SIZE];
339kal_uint32 infra_elm_runtime_wc_history_idx = 0;
340ELM_RUNTIME_PROFILE_WC_T infra_elm_runtime_wc_history[ELM_RUNTIME_HISTORY_SIZE];
341
342
343
344void elmtop_emi_isr_handler();
345void elm_infra_isr_handler();
346
347
348
349#define ELM_HISTORY_SIZE 64
350kal_uint32 elm_profile_history_idx_0 = 0;
351ELM_FULL_LOG_T elm_profile_history_0[ELM_HISTORY_SIZE];
352
353
354void ELM_INIT(void)
355{
356/*MDMCU EMI ELM*/
357 //disable elm
358 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
359 //clear ELM interrupt
360 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); // clear ELM interrupt
361 //set to mode 0
362 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK)); // clear ELM mode
363 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE(ELM_MODE_MASK & elm_mode)); // select ELM mode
364 //ID select for ID2/3 (ID0/1 by ao_reg later)
365 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3)));
366 //set total latency weight for 2nd level detection (set to max-> DISABLE)
367 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_TOTAL_LAT_WEIGHT_BLOCK(7));
368 //ID0/1 trans count threshold
369 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_TH, elm_trans_threshold);
370 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_TH, elm_trans_threshold);
371 // config ID2/3 setting (config ID0/1 by ao_reg later)
372 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
373 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
374 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
375 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
376 //set word count threshold to 1.5GB/sec (both read and write)
377 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_read_wc_threshold, elm_read_wc_unit));
378 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_write_wc_threshold, elm_write_wc_unit));
379 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
380 //set ao_reg cfg1 (ID1 config)
381 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
382 ELM_EMI_TOP_BLOCK(E_TOP_MASK)|
383 DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
384 ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
385 EMI_BLOCK(E_NOT_MASK)|
386 ELM_INT_MASK(LAT_INT_UNMASK_ALL));
387 //set ao_reg cfg2 (threshold when emi blocking, wc int)
388 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG2,
389 LAT_TH_ID1_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_write_lat_threshold)))|
390 LAT_TH_ID0_BLOCK(ELM_NS2TRAN((kal_uint32)(1.5*elm_read_lat_threshold)))|
391 ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
392 //subwindow enable; grand total mode
393 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_SUBWINDOW_CTRL, 1);
394 //set ao_reg cfg0 (ELM enable, ID0 config, threshold when emi normal)
395 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG0,
396 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
397 LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
398 LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
399 DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
400
401 IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
402/* MDINFRA_A EMI ELM*/
403 //disable elm
404 DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
405 //clear ELM interrupt
406 DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL);
407 //set ID mode
408 //DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
409 DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
410 //set trans threshold
411 DRV_WriteReg32(REG_MDINFRA_ELM_ID0_TRANS_TH, elm_trans_threshold);
412 DRV_WriteReg32(REG_MDINFRA_ELM_ID1_TRANS_TH, elm_trans_threshold);
413 // config word_cnt window setting
414 DRV_WriteReg32(REG_MDINFRA_ELM_ID2_WORDCNT_TH, ELM_XB2WC(elm_infra_read_wc_threshold, elm_infra_read_wc_unit));
415 DRV_WriteReg32(REG_MDINFRA_ELM_ID3_WORDCNT_TH, ELM_XB2WC(elm_infra_write_wc_threshold, elm_infra_write_wc_unit));
416 DRV_WriteReg32(REG_MDINFRA_ELM_WORDCNT_DURATION, ELM_WC_ACCURACY(elm_infra_wc_dur_in_us-1)|ELM_WC_DURATION(1-1));
417 // set ao_reg cfg1 (ID1 csetting, duration, irq unmask)
418 DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG1,
419 ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_prio)|
420 ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
421 EMI_BLOCK(E_NOT_MASK)|
422 ELM_INT_MASK(LAT_INT_UNMASK_ALL));
423 // set ao_reg cfg2 (threshold when emi blocking)
424 DRV_WriteReg32(REG_MDINFRA_ELM_AO_STATUS_CFG2,
425 LAT_TH_ID1_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_write_lat_threshold)))|
426 LAT_TH_ID0_BLOCK(ELM_MDINFRA_NS2TRAN((kal_uint32)(1.5*elm_infra_read_lat_threshold)))|
427 ELM_WC_INT_MASK(WC_INT_UNMASK_ALL));
428 // set ao_reg cfg0 (elm enable, accuracy, threshold when emi normal, ID0 setting)
429 DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0,
430 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
431 LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
432 LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
433 DECODE_ID0(elm_id0_rw|elm_id0_prio));
434
435
436 IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
437
438 return ;
439}
440
441void ELM_Config_DormantLeave(void)
442{
443 kal_uint32 vpe_idx;
444 vpe_idx = kal_get_current_vpe_id();
445 if(0 == vpe_idx)
446 {
447 ELM_INIT();
448 emi_elm_runtime_lat_history_idx =0;
449 memset((void*)emi_elm_runtime_lat_history,0, sizeof(ELM_RUNTIME_PROFILE_LAT_T)*ELM_RUNTIME_HISTORY_SIZE);
450 }
451}
452
453void ELM_Config_DormantEnter(void)
454{
455
456}
457
458void ELM_GET_FULL_LOG(ELM_FULL_LOG_T* data)
459{
460 if(NULL==data)
461 {
462 return;
463 }
464
465#ifdef __ELM_RUNTIME_PROFILE__
466 elm_profile_history_0[elm_profile_history_idx_0].fma_stamp = ust_get_current_time();
467 ELM_GET_LOG(0,elm_profile_history_0[elm_profile_history_idx_0]);
468 elm_profile_history_0[elm_profile_history_idx_0].r_lat_thr = elm_read_lat_threshold;
469 elm_profile_history_0[elm_profile_history_idx_0].w_lat_thr = elm_write_lat_threshold;
470 memcpy(data,&elm_profile_history_0[elm_profile_history_idx_0], sizeof(ELM_FULL_LOG_T));
471 elm_profile_history_idx_0 = (elm_profile_history_idx_0 + 1) % ELM_HISTORY_SIZE ;
472#else
473 data->fma_stamp = ust_get_current_time();
474 ELM_GET_CNT(ELM_WR, ELM_TYPE_TRANS, 0, &(data->w_trans));
475 ELM_GET_CNT(ELM_WR, ELM_TYPE_LATENCY, 0, &(data->w_latency));
476 ELM_GET_WC_CNT(ELM_WR, 0, &(data->w_wordcount));
477 ELM_GET_CNT(ELM_RD, ELM_TYPE_TRANS, 0, &(data->r_trans));
478 ELM_GET_CNT(ELM_RD, ELM_TYPE_LATENCY, 0, &(data->r_latency));
479 ELM_GET_WC_CNT(ELM_RD, 0, &(data->r_wordcount));
480#endif
481
482}
483
484kal_uint32 debug_emi_elm_runtime_counter = 0;
485kal_uint32 debug_MDMCU_elm_last_INT_FRC = 0;
486kal_uint32 debug_MDIFRA_elm_last_INT_FRC = 0;
487
488
489
490#define E_MAX16(x) ((x>0xFFFF)? 0xFFFF : x)
491
492kal_uint32 elm_md_dvfs_con = 0;
493kal_uint32 elm_ap_vcore_dvfs_current = 0;
494kal_uint32 elm_ap_vcore_dvfs_target = 0;
495kal_uint32 elm_ap_vcore_dvfs_last = 0;
496
497void elmtop_emi_isr_handler()
498{
499 kal_uint32 curr_frc = 0, enter_lisr_frc = 0;
500 kal_uint32 int_status = 0;
501 kal_uint32 read_trans_count = 0, write_trans_count = 0;
502 kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
503 kal_uint32 read_worst_alat_maxost = 0, write_worst_alat_maxost = 0;
504 kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
505 kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
506 kal_uint32 ia_13m_tick = 0, dvfs_13m_tick = 0, ddren_13m_tick = 0;
507 enter_lisr_frc = ust_get_current_time();
508 debug_emi_elm_runtime_counter++;
509
510 //Mask cirq ELM interrupt
511 IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
512 //stop ELM
513 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
514
515 curr_frc = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_FRCVAL);
516 int_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_INT_STATUS);
517
518 /* Handling latency interrupt */
519 if(int_status & INT_MASK_LAT)
520 {
521 read_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
522 write_trans_count = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
523 read_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_AVG_LAT_NORMAL) );
524 write_worst_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_AVG_LAT_NORMAL) );
525 read_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_WORST_TOT_LAT_NORMAL) );
526 write_total_latency_ns = ELM_TRANS2NS( DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_WORST_TOT_LAT_NORMAL) );
527 read_worst_alat_maxost = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_MAXOST_IN_WORST_AVG_NORMAL);
528 write_worst_alat_maxost = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_MAXOST_IN_WORST_AVG_NORMAL);
529
530// Read AP side related debugging register
531#if 1
532 ia_13m_tick = *AP_SYSTIMER_TICK; //AP systimer
533 dvfs_13m_tick = *AP_DVFS_OCCUR_TICK;// last dvfs occur tick
534 ddren_13m_tick = *AP_DDREN_OCCUR_TICK;// last ddren occur tick
535 elm_ap_vcore_dvfs_current = *AP_VCORE_DVFS_CURRENT;
536 elm_ap_vcore_dvfs_target = *AP_VCORE_DVFS_TARGET;
537 elm_ap_vcore_dvfs_last = *AP_VCORE_DVFS_LAST;
538#endif
539
540 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
541 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].enter_lisr_frc= enter_lisr_frc;
542 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
543 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
544 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
545 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
546 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat_maxost = read_worst_alat_maxost;
547 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
548 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat_maxost = write_worst_alat_maxost;
549 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
550 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
551 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_dvfs_tick = dvfs_13m_tick;
552 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].ap_ddren_tick = ddren_13m_tick;
553 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].md_tick = ia_13m_tick;
554 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id0_subwindow_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID0_SUBWINDOW_STS);
555 emi_elm_runtime_lat_history[emi_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].id1_subwindow_status = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID1_SUBWINDOW_STS);
556 emi_elm_runtime_lat_history_idx++;
557
558 elm_md_dvfs_con = drv_mdap_interface_hw_get_curr_scenario_reg();
559
560 switch(EMI_ELM_lat_irq_exception_type)
561 {
562 case ELM_NONE:
563 {
564 //read latency over criteria
565 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
566 {
567 ELM_IF_DEF_TRACE( \
568 MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
569 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
570 );
571 }
572 //write latency over criteria
573 else
574 {
575 ELM_IF_DEF_TRACE( \
576 MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
577 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
578 );
579 }
580 break;
581 }
582 case ELM_ASSERT:
583 {
584 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
585 {
586 EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
587 (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
588 (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
589 }
590 else
591 {
592 EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
593 (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
594 (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
595 }
596 break;
597 }
598 case ELM_ASSERT_AT_2nd:
599 {
600 // just show trace on first time over criteria in 300us
601 if(debug_MDMCU_elm_last_INT_FRC == 0)
602 {
603 debug_MDMCU_elm_last_INT_FRC = curr_frc;
604 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
605 {
606 ELM_IF_DEF_TRACE( \
607 MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
608 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
609 );
610 }
611 else
612 {
613 ELM_IF_DEF_TRACE( \
614 MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
615 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
616 );
617 }
618 }
619 else
620 {
621 if(ust_us_duration(debug_MDMCU_elm_last_INT_FRC, curr_frc) < ELM_2ND_ASSERT_CHECK_DURATION)
622 {
623 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
624 {
625 EXT_ASSERT(0,(E_MAX16(elm_read_lat_threshold)<<16)|(E_MAX16(read_worst_latency_ns)), \
626 (E_MAX16(read_trans_count)<<16)|(E_MAX16(read_total_latency_ns)), \
627 (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
628 }
629 else
630 {
631 EXT_ASSERT(0,(E_MAX16(elm_write_lat_threshold)<<16)|(E_MAX16(write_worst_latency_ns)), \
632 (E_MAX16(write_trans_count)<<16)|(E_MAX16(write_total_latency_ns)), \
633 (E_MAX16(drv_mdap_interface_hw_get_curr_scenario_reg())<<16)|(E_MAX16(int_status)));
634 }
635 }
636 else
637 {
638 debug_MDMCU_elm_last_INT_FRC = curr_frc;
639 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
640 {
641 ELM_IF_DEF_TRACE( \
642 MD_TRC_EMI_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_read_lat_threshold, read_total_latency_ns, read_trans_count, \
643 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
644 );
645 }
646 else
647 {
648 ELM_IF_DEF_TRACE( \
649 MD_TRC_EMI_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_write_lat_threshold, write_total_latency_ns, write_trans_count, \
650 elm_md_dvfs_con, elm_ap_vcore_dvfs_current, elm_ap_vcore_dvfs_last), \
651 );
652 }
653 }
654 }
655 break;
656 }
657 default:
658 break;
659 }
660
661 }
662 /* Handling word count interrupt */
663 else
664 {
665 read_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID2_WORST_WORD_CNT);
666 write_worst_wc = DRV_Reg32(REG_MCUSYS_EMI_ELM_ID3_WORST_WORD_CNT);
667
668 emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
669 emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
670 emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
671 emi_elm_runtime_wc_history[emi_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
672 emi_elm_runtime_wc_history_idx++;
673
674 //check config mode: assertion or trace
675 switch(EMI_ELM_wc_irq_exception_type)
676 {
677 case ELM_NONE:
678 {
679 // Read wordcount violation
680 if(int_status & ID2_TOT_WC_INT)
681 {
682 ELM_IF_DEF_TRACE( \
683 MD_TRC_EMI_ELM_R_BW_WARN(curr_frc, ELM_WC2XB(read_worst_wc, elm_read_wc_unit), ELM_WC2XB(elm_read_wc_threshold, elm_read_wc_unit), ELM_WC_UNIT_STRING(elm_read_wc_unit)), \
684 );
685 }
686 else
687 {
688 ELM_IF_DEF_TRACE( \
689 MD_TRC_EMI_ELM_W_BW_WARN(curr_frc, ELM_WC2XB(write_worst_wc, elm_write_wc_unit), ELM_WC2XB(elm_write_wc_threshold, elm_write_wc_unit), ELM_WC_UNIT_STRING(elm_write_wc_unit)), \
690 );
691 }
692 break;
693 }
694 case ELM_ASSERT:
695 {
696 // Read wordcount violation
697 if(int_status & ID2_TOT_WC_INT)
698 {
699 EXT_ASSERT(0, ELM_WC2XB(read_worst_wc, elm_read_wc_unit), elm_read_wc_unit, 0);
700 }
701 else
702 {
703 EXT_ASSERT(0, ELM_WC2XB(write_worst_wc, elm_write_wc_unit), elm_write_wc_unit, 0);
704
705 }
706 break;
707 }
708 default:
709 break;
710 }
711 }
712
713 //Clear ELM interrupt after read irq type
714 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL);
715
716 //enable ELM
717 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
718
719 IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
720 return ;
721
722}
723
724void elm_infra_isr_handler()
725{
726 kal_uint32 curr_frc = 0;
727 kal_uint32 int_status = 0;
728
729 kal_uint32 read_trans_count = 0, write_trans_count = 0;
730 kal_uint32 read_worst_latency_ns = 0, write_worst_latency_ns = 0;
731 kal_uint32 read_total_latency_ns = 0, write_total_latency_ns = 0;
732 kal_uint32 read_worst_wc = 0, write_worst_wc = 0;
733
734 //Mask cirq ELM interrupt
735 IRQMask(IRQ_ELM_DMA_IRQ_CODE);
736
737 //stop elm
738 DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
739
740 //curr_frc = ust_get_current_time();
741
742 //read INT status
743 int_status = DRV_Reg32(REG_MDINFRA_ELM_INT_STATUS);
744
745 /* Handling latency interrupt */
746 if(int_status & INT_MASK_LAT)
747 {
748 curr_frc = DRV_Reg32(REG_MDINFRA_ELM_INT_FRCVAL);
749 read_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID0_TRANS_IN_WORST_AVG_NORMAL);
750 write_trans_count = DRV_Reg32(REG_MDINFRA_ELM_ID1_TRANS_IN_WORST_AVG_NORMAL);
751 read_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_AVG_LAT_NORMAL) );
752 write_worst_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_AVG_LAT_NORMAL) );
753 read_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID0_WORST_TOT_LAT_NORMAL) );
754 write_total_latency_ns = ELM_MDINFRA_TRANS2NS( DRV_Reg32(REG_MDINFRA_ELM_ID1_WORST_TOT_LAT_NORMAL) );
755
756 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
757 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
758 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_alat = read_worst_latency_ns;
759 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_alat = write_worst_latency_ns;
760 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_trans = read_trans_count;
761 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_trans = write_trans_count;
762 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_l2_tot_lat = read_total_latency_ns;
763 infra_elm_runtime_lat_history[infra_elm_runtime_lat_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_l2_tot_lat = write_total_latency_ns;
764 infra_elm_runtime_lat_history_idx++;
765
766 switch(INFRA_ELM_lat_irq_exception_type)
767 {
768 case ELM_NONE:
769 {
770#ifdef __ELM_TRACE__
771 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
772 {
773 MD_TRC_INFRA_ELM_R_LAT_WARN(curr_frc, read_worst_latency_ns, elm_infra_read_lat_threshold, read_total_latency_ns, read_trans_count);
774 }
775 else
776 {
777 MD_TRC_INFRA_ELM_W_LAT_WARN(curr_frc, write_worst_latency_ns, elm_infra_write_lat_threshold, write_total_latency_ns, write_trans_count);
778 }
779#endif
780 break;
781 }
782 default:
783 break;
784 }
785 }
786 /* Handling word count interrupt */
787 else if(int_status & INT_MASK_WC)
788 {
789 curr_frc = DRV_Reg32(REG_MDINFRA_ELM_INT_FRCVAL);
790 read_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID2_WORST_WORD_CNT);
791 write_worst_wc = DRV_Reg32(REG_MDINFRA_ELM_ID3_WORST_WORD_CNT);
792
793 infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].cur_frc = curr_frc;
794 infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].int_status= int_status;
795 infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].r_wc = read_worst_wc;
796 infra_elm_runtime_wc_history[infra_elm_runtime_wc_history_idx%ELM_RUNTIME_HISTORY_SIZE].w_wc = write_worst_wc;
797 infra_elm_runtime_wc_history_idx++;
798
799 switch(INFRA_ELM_wc_irq_exception_type)
800 {
801 case ELM_NONE:
802 {
803 // Read wordcount violation
804 if(int_status & ID2_TOT_WC_INT)
805 {
806 ELM_IF_DEF_TRACE( \
807 MD_TRC_INFRA_ELM_R_BW_WARN(curr_frc, ELM_WC2XB(read_worst_wc, elm_infra_read_wc_unit), ELM_WC2XB(elm_infra_read_wc_threshold, elm_infra_read_wc_unit), ELM_WC_UNIT_STRING(elm_infra_read_wc_unit)), \
808 );
809 }
810 else
811 {
812 ELM_IF_DEF_TRACE( \
813 MD_TRC_INFRA_ELM_W_BW_WARN(curr_frc, ELM_WC2XB(write_worst_wc, elm_infra_write_wc_unit), ELM_WC2XB(elm_infra_write_wc_threshold, elm_infra_write_wc_unit), ELM_WC_UNIT_STRING(elm_infra_write_wc_unit)), \
814 );
815 }
816 break;
817 }
818 case ELM_ASSERT:
819 {
820 // Read wordcount violation
821 if(int_status & ID2_TOT_WC_INT)
822 {
823 EXT_ASSERT(0, ELM_WC2XB(read_worst_wc, elm_infra_read_wc_unit), elm_infra_read_wc_unit, 0);
824 }
825 else
826 {
827 EXT_ASSERT(0, ELM_WC2XB(write_worst_wc, elm_infra_write_wc_unit), elm_infra_write_wc_unit, 0);
828 }
829 break;
830 }
831 default:
832 break;
833 }
834 }
835
836
837 //Clear ELM interrupt after read irq type
838 DRV_WriteReg32(REG_MDINFRA_ELM_INT_STATUS, INT_MASK_ALL); //clear M4_A ELM interrupt
839
840 //Enable ELM
841 DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
842
843 IRQUnmask(IRQ_ELM_DMA_IRQ_CODE);
844
845}
846
847void ELM_MCU_threshold_change_lightweight(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
848{
849 kal_uint32 mask_state=0;
850
851 if(elm_dynamic_lat_threshold_disable)
852 {
853 return;
854 }
855
856 mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
857
858 //Mask cirq ELM interrupt
859 IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
860
861 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); //disable ELM
862
863 // kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
864
865
866 elm_read_lat_threshold = read_avg_lat_ns;
867 elm_write_lat_threshold = write_avg_lat_ns;
868 elm_lat_duration= dur_us;
869
870 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
871 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
872 ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
873 ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
874 EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
875 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
876 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
877 LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
878 LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
879 DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
880
881 // kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
882
883 if(!mask_state)
884 {
885 IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
886 }
887}
888
889void ELM_MCU_threshold_change(kal_uint32 read_avg_lat_ns, kal_uint32 write_avg_lat_ns, kal_uint32 dur_us)
890{
891 kal_uint32 mask_state=0;
892
893 if(elm_dynamic_lat_threshold_disable)
894 {
895 return;
896 }
897
898 if((read_avg_lat_ns<200) || (write_avg_lat_ns<200) || (dur_us<200))
899 {
900 kal_uint32 lr = 0;
901 kal_uint32 sub_error_code = 0;
902 GET_RETURN_ADDRESS(lr);
903 if(read_avg_lat_ns<200)
904 {
905 sub_error_code = 1;
906 }
907 else if(write_avg_lat_ns<200)
908 {
909 sub_error_code = 2;
910 }
911 else
912 {
913 sub_error_code = 3;
914 }
915 EXT_ASSERT(0, lr, KAL_ERROR_EMI_ELM_CHANGE_THRESHOLD, sub_error_code);
916 }
917
918
919
920 mask_state = IRQMask_Status(IRQ_ELMTOP_EMI_IRQ_CODE);
921
922 //Mask cirq ELM interrupt
923 IRQMask(IRQ_ELMTOP_EMI_IRQ_CODE);
924
925 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE); //disable ELM
926
927 kal_hrt_take_itc_lock(KAL_ITC_ELM_LOCK, KAL_INFINITE_WAIT);
928
929
930 elm_read_lat_threshold = read_avg_lat_ns;
931 elm_write_lat_threshold = write_avg_lat_ns;
932 elm_lat_duration= dur_us;
933
934 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_INT_STATUS, INT_MASK_ALL); //clear ELM interrupt
935 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
936 ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
937 ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
938 EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
939 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
940 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
941 LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
942 LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
943 DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
944
945 kal_hrt_give_itc_lock(KAL_ITC_ELM_LOCK);
946
947#ifdef __ELM_TRACE__
948 {
949 // L1 trace
950 kal_uint32 curr_frc = 0;
951 curr_frc = ust_get_current_time();
952 MD_TRC_EMI_ELM_SET_R_TH(curr_frc, elm_read_lat_threshold);
953 MD_TRC_EMI_ELM_SET_W_TH(curr_frc, elm_write_lat_threshold);
954 }
955#endif
956
957 if(!mask_state)
958 {
959 IRQUnmask(IRQ_ELMTOP_EMI_IRQ_CODE);
960 }
961
962}
963
964#if 0//def __ELM_RUNTIME_PROFILE__
965/* under construction !*/
966/* under construction !*/
967/* under construction !*/
968/* under construction !*/
969/* under construction !*/
970/* under construction !*/
971/* under construction !*/
972/* under construction !*/
973/* under construction !*/
974/* under construction !*/
975/* under construction !*/
976/* under construction !*/
977/* under construction !*/
978/* under construction !*/
979/* under construction !*/
980/* under construction !*/
981/* under construction !*/
982/* under construction !*/
983/* under construction !*/
984/* under construction !*/
985/* under construction !*/
986/* under construction !*/
987/* under construction !*/
988/* under construction !*/
989/* under construction !*/
990/* under construction !*/
991/* under construction !*/
992/* under construction !*/
993/* under construction !*/
994/* under construction !*/
995/* under construction !*/
996/* under construction !*/
997#endif
998
999kal_uint8 _ELM_latency_status(void)
1000{
1001#ifdef __ELM_RUNTIME_PROFILE__
1002
1003 //if emi_elm_runtime_lat_history_idx == 0, means that it didn't enter ELM isr handler once, it will all be zero
1004 if(emi_elm_runtime_lat_history_idx != 0)
1005 {
1006 kal_uint32 int_status = 0;
1007 int_status = emi_elm_runtime_lat_history[(emi_elm_runtime_lat_history_idx-1)%ELM_RUNTIME_HISTORY_SIZE].int_status;
1008
1009 if(int_status & (ID0_AVG_LAT_INT|ID0_TOT_LAT_INT))
1010 {
1011 return 0xAE; //EMI read latency may be too long
1012 }
1013 else
1014 {
1015 return 0xBE; //EMI write latency may be too long
1016 }
1017 }
1018 return 0xDE; // EMI read/write latency are OK.
1019#else
1020 return 0xFF; //no ELM info
1021#endif
1022}
1023
1024/******************************************************************************
1025* function : void set_emi_elm_exceptiontype(kal_bool lat_flag, kal_uint8 exception_type)
1026* description : this function is called when set emi elm read/write latency/wordcount exception type
1027* parameter : kal_uint8 exception_type: 0,1,2
1028* return : void
1029******************************************************************************/
1030kal_bool Set_EMI_ELM_ExceptionType(kal_uint8 exception_type)
1031{
1032 switch (exception_type)
1033 {
1034 case ELM_NONE:
1035 {
1036 EMI_ELM_lat_irq_exception_type = ELM_NONE;
1037 break;
1038 }
1039
1040 case ELM_ASSERT:
1041 {
1042 EMI_ELM_lat_irq_exception_type = ELM_ASSERT;
1043 break;
1044 }
1045 case ELM_ASSERT_AT_2nd:
1046 {
1047 EMI_ELM_lat_irq_exception_type = ELM_ASSERT_AT_2nd;
1048 break;
1049 }
1050 default:
1051 return KAL_FALSE;
1052 break;
1053 }
1054 return KAL_TRUE;
1055}
1056
1057kal_bool Set_EMI_ELM_Threshold(kal_uint8 info, kal_uint32 threshold)
1058{
1059 ELM_IF_DEF_TRACE(kal_uint32 curr_frc = 0,);
1060 ELM_IF_DEF_TRACE(curr_frc = ust_get_current_time(),);
1061 elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
1062 if((info&0xF0))
1063 { // infra
1064 //Disable before re-configure
1065 DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_DISABLE);
1066
1067 if( info & 0x01 )
1068 {
1069 elm_infra_read_lat_threshold = threshold;
1070 ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_R_TH(curr_frc, threshold),);
1071 }
1072 else
1073 {
1074 elm_infra_write_lat_threshold = threshold;
1075 ELM_IF_DEF_TRACE(MD_TRC_INFRA_ELM_SET_W_TH(curr_frc, threshold),);
1076 }
1077 //M4_A ELM
1078 DRV_WriteReg32_NPW(REG_MDINFRA_ELM_AO_STATUS_CFG0,
1079 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
1080 LAT_TH_ID1_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_write_lat_threshold))|
1081 LAT_TH_ID0_NORMAL(ELM_MDINFRA_NS2TRAN(elm_infra_read_lat_threshold))|
1082 DECODE_ID0(elm_id0_rw|elm_id0_prio));
1083 }
1084 else
1085 { //mdmcu
1086
1087 //Disable before re-configure
1088 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
1089 if( info & 0x01 )
1090 {
1091 elm_read_lat_threshold = threshold;
1092 ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_R_TH(curr_frc, threshold),);
1093 }
1094 else
1095 {
1096 elm_write_lat_threshold = threshold;
1097 ELM_IF_DEF_TRACE(MD_TRC_EMI_ELM_SET_W_TH(curr_frc, threshold),);
1098 }
1099 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)| \
1100 LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))| \
1101 DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
1102 }
1103
1104
1105 return KAL_TRUE;
1106}
1107
1108/******************************************************************************
1109* function : kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
1110* description : ELM has 4 counters(ID 0,1,2,3), this function is used to set EMI ELM's
1111* counter to monitro read or write transaction and master.
1112* parameter :
1113* kal_uint8 id: 0, 1, 0xFF;
1114* -> Assume id 0,2 use same configuration(so does id 1,3), including read/write and masters.
1115* -> 0xFF is used for let all ID monitor same masters.
1116* return : void
1117******************************************************************************/
1118
1119//!!!! AXID RELATED API !!!!
1120kal_bool Set_EMI_ELM_Config(kal_uint8 id, kal_uint8 m_sel, kal_uint8 rw)
1121{
1122 kal_bool rtn = KAL_TRUE;
1123
1124 //Disable before re-configure
1125 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_DISABLE);
1126 elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
1127
1128 if(id == 0) // id 0 (default read), assume id2 use same master as id 0
1129 {
1130 elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
1131 if(m_sel==0)
1132 {
1133 elm_id0_master = ELM_ALL_MASTER;
1134
1135 elm_id2_value = 0;
1136 elm_id2_mask |= MASTER_DEFAULT_MASK;
1137 }
1138 else if(m_sel==1)
1139 {
1140 elm_id0_master = ELM_MDMCU_ONLY;
1141
1142 elm_id2_value = MASTER_MDMCU;
1143 elm_id2_mask |= MASTER_MDMCU_MASK;
1144 }
1145 else if(m_sel==2)
1146 {
1147 elm_id0_master = ELM_USIP_ONLY;
1148
1149 elm_id2_value = MASTER_USIP;
1150 elm_id2_mask |= MASTER_USIP_MASK;
1151 }
1152 else
1153 {
1154 rtn = KAL_FALSE;
1155 }
1156
1157 if(rw == 0)
1158 {
1159 elm_id0_rw = ELM_READ;
1160 elm_id2_rw = ELM_RD;
1161 }
1162 else if(rw == 1)
1163 {
1164 elm_id0_rw = ELM_WRITE;
1165 elm_id2_rw = ELM_WR;
1166 }
1167 else
1168 {
1169 rtn = KAL_FALSE;
1170 }
1171 }
1172 else if( id == 1 ) // id 1 (default write), assume id3 use same master as id 1
1173 {
1174 elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
1175 if(m_sel==0)
1176 {
1177 elm_id1_master = ELM_ALL_MASTER;
1178
1179 elm_id3_value = 0;
1180 elm_id3_mask |= MASTER_DEFAULT_MASK;
1181 }
1182 else if(m_sel==1)
1183 {
1184 elm_id1_master = ELM_MDMCU_ONLY;
1185
1186 elm_id3_value = MASTER_MDMCU;
1187 elm_id3_mask |= MASTER_MDMCU_MASK;
1188 }
1189 else if(m_sel==2)
1190 {
1191 elm_id1_master = ELM_USIP_ONLY;
1192
1193 elm_id3_value = MASTER_USIP;
1194 elm_id3_mask |= MASTER_USIP_MASK;
1195 }
1196 else
1197 {
1198 rtn = KAL_FALSE;
1199 }
1200
1201 if(rw == 0)
1202 {
1203 elm_id1_rw = ELM_READ;
1204 elm_id3_rw = ELM_RD;
1205 }
1206 else if(rw == 1)
1207 {
1208 elm_id1_rw = ELM_WRITE;
1209 elm_id3_rw = ELM_WR;
1210 }
1211 else
1212 {
1213 rtn = KAL_FALSE;
1214 }
1215 }
1216 else if(id == 0xFF) // ID 0/1/2/3 are the same master, 0,2 for read, 1,3 for write
1217 {
1218 elm_id2_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
1219 elm_id3_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_ALL_MASK));
1220
1221 elm_id0_rw = ELM_READ;
1222 elm_id1_rw = ELM_WRITE;
1223 elm_id2_rw = ELM_RD;
1224 elm_id3_rw = ELM_WR;
1225 if(m_sel==0)
1226 {
1227 elm_id0_master = ELM_ALL_MASTER;
1228 elm_id1_master = ELM_ALL_MASTER;
1229
1230 elm_id2_value = 0;
1231 elm_id2_mask |= MASTER_DEFAULT_MASK;
1232 elm_id3_value = 0;
1233 elm_id3_mask |= MASTER_DEFAULT_MASK;
1234 }
1235 else if(m_sel==1)
1236 {
1237 elm_id0_master = ELM_MDMCU_ONLY;
1238 elm_id1_master = ELM_MDMCU_ONLY;
1239
1240 elm_id2_value = MASTER_MDMCU;
1241 elm_id2_mask |= MASTER_MDMCU_MASK;
1242 elm_id3_value = MASTER_MDMCU;
1243 elm_id3_mask |= MASTER_MDMCU_MASK;
1244 }
1245 else if(m_sel==2)
1246 {
1247 elm_id0_master = ELM_USIP_ONLY;
1248 elm_id1_master = ELM_USIP_ONLY;
1249
1250 elm_id2_value = MASTER_USIP;
1251 elm_id2_mask |= MASTER_USIP_MASK;
1252 elm_id3_value = MASTER_USIP;
1253 elm_id3_mask |= MASTER_USIP_MASK;
1254 }
1255 else
1256 {
1257 rtn = KAL_FALSE;
1258 }
1259 }
1260 else
1261 {
1262 rtn = KAL_FALSE;
1263 }
1264
1265 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_MODE_ID_MASK)); // clear ELM_MODE_ID_SEL
1266 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, ELM_MODE_ID_SEL(ELM_ID_RW(elm_id2_rw, 2)|ELM_ID_RW(elm_id3_rw, 3))); // set ELM_MODE_ID_SEL
1267 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, elm_id2_value);
1268 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, elm_id2_mask);
1269 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, elm_id3_value);
1270 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, elm_id3_mask);
1271
1272 DRV_WriteReg32(REG_MDMCU_ELM_AO_STATUS_CFG1,
1273 ELM_EMI_TOP_BLOCK(E_TOP_MASK)|DECODE_ID1(elm_id1_rw|elm_id1_master|elm_id1_prio)|
1274 ELM_DURATION(elm_lat_duration/ELM_ACCURACY_TBL[elm_lat_accuracy])|
1275 EMI_BLOCK(E_NOT_MASK)|ELM_INT_MASK(LAT_INT_UNMASK_ALL));
1276
1277 DRV_WriteReg32_NPW(REG_MDMCU_ELM_AO_STATUS_CFG0,
1278 ELM_IDLE_ENABLE|ELM_ENABLE|ELM_ACCURACY(elm_lat_accuracy)|
1279 LAT_TH_ID1_NORMAL(ELM_NS2TRAN(elm_write_lat_threshold))|
1280 LAT_TH_ID0_NORMAL(ELM_NS2TRAN(elm_read_lat_threshold))|
1281 DECODE_ID0(elm_id0_rw|elm_id0_master|elm_id0_prio));
1282 return rtn;
1283}
1284
1285
1286kal_bool Set_EMI_ELM_Mode(kal_uint8 mode)
1287{
1288 kal_bool rtn = KAL_TRUE;
1289 //Disable elm
1290 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1291 DRV_ClrReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1292
1293 elm_dynamic_lat_threshold_disable = 1; //disable dynamic latency threshold
1294
1295 if( mode == 0)
1296 {
1297 elm_mode = ELM_MODE_0;
1298 }
1299 else if( mode == 2)
1300 {
1301 elm_mode = ELM_MODE_2;
1302 elm_ao_decode_cfg = ELM_DECODE_FROM_APB;
1303 //mdmcu elm
1304 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
1305 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
1306 //mdinfra_a elm
1307 DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO))); // clear AO decode
1308 DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_AO_DECODE(elm_ao_decode_cfg))); // set AO decode
1309
1310 }
1311 else
1312 {
1313 rtn = KAL_FALSE;
1314 }
1315 //Set mode & enable elm
1316 //mdmcu elm
1317 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
1318 DRV_SetReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
1319 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1320 //mdinfra_a elm
1321 DRV_ClrReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK))); // clear ELM mode
1322 DRV_SetReg32(REG_MDINFRA_ELM_CTRL_REG, (ELM_MODE(ELM_MODE_MASK & elm_mode)));//select ELM mode
1323 DRV_SetReg32(REG_MDINFRA_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1324
1325 return rtn;
1326}
1327
1328//!!!! AXID RELATED API !!!!
1329kal_bool Set_EMI_ELM_uSIP_Core(kal_uint8 id, kal_uint8 thread_val, kal_uint8 port_sel)
1330{
1331 kal_bool rtn = KAL_TRUE;
1332 kal_uint32 assembled_axid=0, assembled_axid_mask=0; // [13]
1333 kal_uint16 usip_core=0, usip_thread=0 ;
1334
1335 //Disable ELM
1336 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1337 //disable dynamic latency threshold
1338 elm_dynamic_lat_threshold_disable = 1;
1339 //elm id setting from apb
1340 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
1341
1342 usip_core = thread_val/2 ;
1343 usip_thread = thread_val%2 ;
1344
1345 if(usip_core==1){
1346 assembled_axid |= (1<<1) ;
1347 }
1348 assembled_axid |= (usip_thread<<4);
1349
1350 switch(port_sel)
1351 {
1352 case 0:
1353 assembled_axid_mask |= (1<<6) ;
1354 break;
1355 case 1:
1356 assembled_axid |= (1<<3);
1357 assembled_axid_mask |= (1<<6) ;
1358 break;
1359 case 2:
1360 assembled_axid |= (1<<0);
1361 assembled_axid_mask |= (0x7<<6);
1362 break;
1363 case 3:
1364 assembled_axid |= (1<<0);
1365 assembled_axid_mask |= (0x3<<6);
1366 break;
1367 default: //monitor all ports
1368 assembled_axid_mask |= 0x1CD ;
1369 break;
1370 }
1371
1372 assembled_axid = (assembled_axid<<2) | 0x2 ;
1373 assembled_axid_mask = (ELM_AO_CONTROL_DEFAULT & ~(MASTER_DEFAULT_MASK)) | (assembled_axid_mask<<2) ;
1374 //config AXID value/mask
1375 if(id==0)
1376 {
1377 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_REG, assembled_axid);
1378 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID0_CTRL_MASK, assembled_axid_mask);
1379 }
1380 else if(id==1)
1381 {
1382 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_REG, assembled_axid);
1383 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID1_CTRL_MASK, assembled_axid_mask);
1384 }
1385 else if(id==2)
1386 {
1387 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_REG, assembled_axid);
1388 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID2_CTRL_MASK, assembled_axid_mask);
1389 }
1390 else
1391 {
1392 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_REG, assembled_axid);
1393 DRV_WriteReg32(REG_MCUSYS_EMI_ELM_AXI_ID3_CTRL_MASK, assembled_axid_mask);
1394 }
1395
1396 //Enable ELM
1397 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1398 return rtn;
1399}
1400
1401//!!!! SIDEBAND RELATED API !!!!
1402kal_bool Set_EMI_ELM_VPE(kal_uint8 id, kal_uint8 vpe_sel)
1403{
1404 kal_bool rtn = KAL_TRUE;
1405 kal_uint32 sideband_val = 0 ;
1406 //Disable ELM
1407 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1408 //disable dynamic latency threshold
1409 elm_dynamic_lat_threshold_disable = 1;
1410 //elm id setting from apb
1411 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
1412
1413 //calculate vpe sideband value
1414 if(vpe_sel >= SYS_MCU_NUM_VPE)
1415 {
1416 return KAL_FALSE ;
1417 }
1418 else
1419 {
1420 kal_uint8 core_id= vpe_sel/(SYS_MCU_NUM_VPE/SYS_MCU_NUM_CORE);
1421 kal_uint8 vpe_id = vpe_sel%(SYS_MCU_NUM_VPE/SYS_MCU_NUM_CORE);
1422 sideband_val = (core_id<<6) | ((vpe_id+1)<<4) ;
1423 }
1424
1425 //config ID sideband value/mask
1426 if(id==0)
1427 {
1428 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, sideband_val);
1429 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, 0);
1430 }
1431 else if(id==1)
1432 {
1433 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, sideband_val);
1434 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, 0);
1435 }
1436 else if(id==2)
1437 {
1438 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, sideband_val);
1439 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, 0);
1440 }
1441 else if(id==3)
1442 {
1443 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, sideband_val);
1444 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, 0);
1445 }
1446 else
1447 { //reset to default
1448 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, 0);
1449 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
1450 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, 0);
1451 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
1452 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, 0);
1453 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
1454 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, 0);
1455 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL);
1456 }
1457
1458 //Enable ELM
1459 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1460 return rtn;
1461}
1462
1463kal_bool Set_EMI_ELM_ID_SIDEBAND(kal_uint16 sideband_val, kal_uint16 sideband_mask)
1464{
1465 kal_bool rtn = KAL_TRUE;
1466 //Disable before re-configure
1467 DRV_ClrReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1468 //disable dynamic latency threshold
1469 elm_dynamic_lat_threshold_disable = 1;
1470 //elm id setting from apb
1471 DRV_ClrReg32(REG_MCUSYS_EMI_ELM_CTRL_REG, (ELM_AO_DECODE(ELM_DECODE_FROM_AO)));
1472
1473 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_REG_1, sideband_val);//REG_MCUSYS_EMI_AXI_SIDEBANK_MASK_ALL
1474 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID0_CTRL_MASK_1, sideband_mask);
1475 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_REG_1, sideband_val);
1476 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID1_CTRL_MASK_1, sideband_mask);
1477 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_REG_1, sideband_val);
1478 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID2_CTRL_MASK_1, sideband_mask);
1479 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_REG_1, sideband_val);
1480 DRV_WriteReg32(REG_MCUSYS_EMI_AXI_ID3_CTRL_MASK_1, sideband_mask);
1481
1482 DRV_SetReg32(REG_MDMCU_ELM_AO_STATUS_CFG0, ELM_ENABLE);
1483 return rtn;
1484}
1485
1486#endif