Gitiles
Code Review Sign In
192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / devdrv / emi / inc / emimpu.h
blob: c6862216e49605c61d3321cde9cfea8808bcb072 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2001
8*
9*****************************************************************************/
10
11/*****************************************************************************
12 *
13 * Filename:
14 * ---------
15 * emimpu.h
16 *
17 * Project:
18 * --------
19 * UMOLY
20 *
21 * Description:
22 * ------------
23 * Header file for EMIMPU.
24 *
25 * Author:
26 * -------
27 * -------
28 *
29 *============================================================================
30 * HISTORY
31 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
32 *------------------------------------------------------------------------------
33 * removed!
34 * removed!
35 * removed!
36 *
37 * removed!
38 * removed!
39 * removed!
40 *
41 * removed!
42 * removed!
43 * removed!
44 *
45 *------------------------------------------------------------------------------
46 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
47 *============================================================================
48 ****************************************************************************/
49#ifndef __MOD_EMIMPU_H__
50#define __MOD_EMIMPU_H__
51
52/* Region & Domain Definition */
53#define MAX_EMI_MPU_REGION_NUM 16
54#define MAX_EMI_MPU_DOMAIN_NUM 8
55
56#define EMI_MPU_DOMAIN_AP 0
57#define EMI_MPU_DOMAIN_MD 1
58#define EMI_MPU_DOMAIN_2 2
59#define EMI_MPU_DOMAIN_3 3
60#define EMI_MPU_DOMAIN_4 4
61#define EMI_MPU_DOMAIN_5 5
62#define EMI_MPU_DOMAIN_6 6
63#define EMI_MPU_DOMAIN_7 7
64
65/* EMI Memory Protect Unit */
66#define EMI_MPUA (BASE_MADDR_EMI + 0x0160)
67#define EMI_MPU_ADDR_SET_REGBASE(region) (EMI_MPUA + (((region)&0x7) << 3) + ((region&0x8)?0x100:0))
68 // EMI MPU start addr and end addr are from EMI_MPUA to EMI_MPUH
69 #define EMI_MPU_START_ADDR_MASK (0xFFFF << 16)
70 #define EMI_MPU_START_ADDR(addr) (((addr) << 16) & EMI_MPU_START_ADDR_MASK)
71 #define EMI_MPU_STOP_ADDR_MASK (0xFFFF << 16)
72 #define EMI_MPU_STOP_ADDR(addr) (((addr) << 16) & EMI_MPU_STOP_ADDR_MASK)
73#define EMI_MPUB (BASE_MADDR_EMI + 0x0168)
74#define EMI_MPUC (BASE_MADDR_EMI + 0x0170)
75#define EMI_MPUD (BASE_MADDR_EMI + 0x0178)
76#define EMI_MPUE (BASE_MADDR_EMI + 0x0180)
77#define EMI_MPUF (BASE_MADDR_EMI + 0x0188)
78#define EMI_MPUG (BASE_MADDR_EMI + 0x0190)
79#define EMI_MPUH (BASE_MADDR_EMI + 0x0198)
80#define EMI_MPUI (BASE_MADDR_EMI + 0x01A0)
81#define EMI_MPU_APC_SET_REGBASE(region, domain) (EMI_MPUI + ((domain)&0x4) + ((((region)>>1)&0x3) << 3) + ((region&0x8)?0x100:0))
82 #define EMI_MPUI_RLOCK(r) (1 << ((r & 0x1)?31:15))
83 #define EMI_MPUI_APC_OFST(r,d) (((r & 0x1) << 4) + ((d & 0x3) * 3))
84 #define EMI_MPUI_APC_MASK (0x7)
85 #define EMI_MPU_APC_REGION_LOCK(lock, rgion) ((lock) << (15+(((region)&0x1)?16:0)))
86 typedef enum {
87 EMI_MPU_APC_NONE = 0,
88 EMI_MPU_APC_SEC_RW,
89 EMI_MPU_APC_SEC_RW_NSEC_R,
90 EMI_MPU_APC_SEC_RW_NSEC_W,
91 EMI_MPU_APC_SEC_R_NSEC_R,
92 EMI_MPU_APC_FORBID,
93 EMI_MPU_APC_SEC_R_NSEC_RW
94 } emi_mpu_prot_attr;
95
96typedef struct EMI_MPU_VIO_INFO_T
97{
98 kal_uint32 address; /* Magic pattern to check if this dump data is valid */
99 kal_uint32 status; /* Setting for each region */
100} EMI_MPU_VIO_INFO;
101
102 #define EMI_MPU_APC(attr, region, domain) ( \
103 ((attr) & 0x7) << \
104 ( \
105 ( ((region)&0x1)?16:0 ) + \
106 ( ((domain)&0x3)*3 ) \
107 ) \
108 )
109#define EMI_MPUI_2ND (BASE_MADDR_EMI + 0x01A4)
110#define EMI_MPUJ (BASE_MADDR_EMI + 0x01A8)
111#define EMI_MPUJ_2ND (BASE_MADDR_EMI + 0x01AC)
112#define EMI_MPUK (BASE_MADDR_EMI + 0x01B0)
113#define EMI_MPUK_2ND (BASE_MADDR_EMI + 0x01B4)
114#define EMI_MPUL (BASE_MADDR_EMI + 0x01B8)
115#define EMI_MPUL_2ND (BASE_MADDR_EMI + 0x01BC)
116#define EMI_MPUM (BASE_MADDR_EMI + 0x01C0)
117#define EMI_MPU_DOMAIN_CTL_REGBASE(domain) (EMI_MPUM + (((domain)&0x3) << 3) + (((0x3==(domain)&0x3))?0x28:0) + (((domain)&0x4)?0x100:0))
118 #define EMI_MPUM_DLOCK (1 << 31)
119 #define EMI_MPUM_DSEC (1 << 30)
120 #define EMI_MPUM_REP (1 << 28)
121 #define EMI_MPUM_OOR_MASK (1 << 9)
122 #define EMI_MPUM_APB_MASK (1 << 8)
123 #define EMI_MPUM_R_MASK(r) (1 << ((r & 0x8) + r))
124#define EMI_MPUN (BASE_MADDR_EMI + 0x01C8)
125#define EMI_MPUO (BASE_MADDR_EMI + 0x01D0)
126#define EMI_MPUP (BASE_MADDR_EMI + 0x01D8)
127#define EMI_MPU_VIO_STA_REGBASE(domain) (EMI_MPUP + (((domain)&0x3) << 3) + (((0x3==(domain)&0x3))?0x30:0) + (((domain)&0x4)?0x100:0))
128 #define EMI_MPUP_OOR_VIO (1 << 9)
129 #define EMI_MPUP_APB_VIO (1 << 8)
130 #define EMI_MPUP_REGION_VIO(r) (1 << ((r & 0x8) + r))
131#define EMI_MPUQ (BASE_MADDR_EMI + 0x01E0)
132#define EMI_MPUR (BASE_MADDR_EMI + 0x01E8)
133#define EMI_MPUS (BASE_MADDR_EMI + 0x01F0)
134 #define EMI_MPUS_CLR (1 << 31)
135 #define EMI_MPUS_R_VIO (1 << 29)
136 #define EMI_MPUS_W_VIO (1 << 28)
137 #define EMI_MPUS_FIX_ABT (1 << 25)
138 #define EMI_MPUS_APB_ABT (1 << 24)
139 #define EMI_MPUS_DOMAIN_ID_OFFSET (21)
140 #define EMI_MPUS_DOMAIN_ID_MASK (0x7 << EMI_MPUS_DOMAIN_ID_OFFSET)
141 #define EMI_MPUS_REGION_OFFSET (16)
142 #define EMI_MPUS_REGION_MASK (0xF << EMI_MPUS_REGION_OFFSET)
143 #define EMI_MPUS_MASTER_ID_OFFSET (0)
144 #define EMI_MPUS_MASTER_ID_MASK (0xFFFF << EMI_MPUS_MASTER_ID_OFFSET)
145#define EMI_MPUT (BASE_MADDR_EMI + 0x01F8)
146#define EMI_MPUU (BASE_MADDR_EMI + 0x0200)
147#define EMI_MPUY (BASE_MADDR_EMI + 0x0220)
148#define EMI_MPUA2 (BASE_MADDR_EMI + 0x0260)
149#define EMI_MPUB2 (BASE_MADDR_EMI + 0x0268)
150#define EMI_MPUC2 (BASE_MADDR_EMI + 0x0270)
151#define EMI_MPUD2 (BASE_MADDR_EMI + 0x0278)
152#define EMI_MPUE2 (BASE_MADDR_EMI + 0x0280)
153#define EMI_MPUF2 (BASE_MADDR_EMI + 0x0288)
154#define EMI_MPUG2 (BASE_MADDR_EMI + 0x0290)
155#define EMI_MPUH2 (BASE_MADDR_EMI + 0x0298)
156#define EMI_MPUI2 (BASE_MADDR_EMI + 0x02A0)
157#define EMI_MPUI2_2ND (BASE_MADDR_EMI + 0x02A4)
158#define EMI_MPUJ2 (BASE_MADDR_EMI + 0x02A8)
159#define EMI_MPUJ2_2ND (BASE_MADDR_EMI + 0x02AC)
160#define EMI_MPUK2 (BASE_MADDR_EMI + 0x02B0)
161#define EMI_MPUK2_2ND (BASE_MADDR_EMI + 0x02B4)
162#define EMI_MPUL2 (BASE_MADDR_EMI + 0x02B8)
163#define EMI_MPUL2_2ND (BASE_MADDR_EMI + 0x02BC)
164#define EMI_MPUM2 (BASE_MADDR_EMI + 0x02C0)
165#define EMI_MPUN2 (BASE_MADDR_EMI + 0x02C8)
166#define EMI_MPUO2 (BASE_MADDR_EMI + 0x02D0)
167#define EMI_MPUP2 (BASE_MADDR_EMI + 0x02D8)
168#define EMI_MPUQ2 (BASE_MADDR_EMI + 0x02E0)
169#define EMI_MPUR2 (BASE_MADDR_EMI + 0x02E8)
170#define EMI_MPUU2 (BASE_MADDR_EMI + 0x0300)
171#define EMI_MPUY2 (BASE_MADDR_EMI + 0x0320)
172
173#define EMI_MPU_DOMAIN_RW (0x0)
174#define EMI_MPU_DOMAIN_SRW (0x1)
175#define EMI_MPU_DOMAIN_SRW_NR (0x2)
176#define EMI_MPU_DOMAIN_SRW_NW (0x3)
177#define EMI_MPU_DOMAIN_R (0x4)
178#define EMI_MPU_DOMAIN_NA (0x5)
179#define EMI_MPU_DOMAIN_SR_NRW (0x6)
180
181/* Define access permission */
182#define NO_PROTECTION EMI_MPU_DOMAIN_RW
183#define SEC_RW EMI_MPU_DOMAIN_SRW
184#define SEC_RW_NSEC_R EMI_MPU_DOMAIN_SRW_NR
185#define SEC_RW_NSEC_W EMI_MPU_DOMAIN_SRW_NW
186#define SEC_R_NSEC_R EMI_MPU_DOMAIN_R
187#define FORBIDDEN EMI_MPU_DOMAIN_NA
188
189/*Domain2, Domain1, Domain0*/
190#define SET_ACCESS_PERMISSON(d2, d1, d0) ((d2 << 6) | (d1 << 3) | (d0))
191/*Domain7 ~ Domain0*/
192#define SET_ACCESS_PERMISSON2(d7, d6, d5, d4, d3, d2, d1, d0) ((d7 << 21) | (d6 << 18) | (d5 << 15) | (d4 << 12) | (d3 << 9) | (d2 << 6) | (d1 << 3) | (d0))
193
194#endif /* !__MOD_EMIMPU_H__ */