mcu/driver/devdrv/pll/src/pll_gen97p.c

/*****************************************************************************
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*****************************************************************************/

/*******************************************************************************
 * Filename:
 * ---------
 *   pll_gen97.c
 *
 * Project:
 * --------
 *   UMOLYE
 *
 * Description:
 * ------------
 *   PLL Related Functions
 *
 * Author:
 * -------
 * -------
 *
 * ==========================================================================
 * $Log$
 *
 *
 *
 ****************************************************************************/
//wolf: the code below is not ready, just for build pass~  
#ifdef __MTK_TARGET__ /* should NOT be compiled on MODIS */

/*******************************************************************************
 * Locally Used Options
 *******************************************************************************/

/*******************************************************************************
 * Include header files
 *******************************************************************************/

#include "pll.h"
#include "kal_public_api.h"
#include "sync_data.h"
#include "us_timer.h"
#include "sleepdrv_common.h"

#define PLL_FM_WIMDOW       (0x1FF)

/* Below for debugging */
const char PLL_FM_clock[PLL_FM_NUM][32] =
{
    "AD_MDNRPLL5",            /* 0 */
    "AD_MDNRPLL4_1",
    "AD_MDNRPLL4_0",
    "AD_MDNRPLL3",
    "AD_MDNRPLL2",
    "AD_MDNRPLL1",            /* 5 */
    "AD_MDNRPLL0",
    "MDSYS_NRL2_CLOCK",	
    "MDRXSYS_DFESYNC_CLOCK",
    "MDTOP_F216P7M_CLOCK",
    "TRACE_MON_CLOCK",        /* 10 */
    "MDSYS_216P7M_CLOCK",	  
    "MDRXSYS_RAKE_CLOCK",	
    "MDRXSYS_BRP_CLOCK",		
    "MDRXSYS_VDSP_CLOCK",	
    "MDTOP_LOG_ATB_CLOCK",    /* 15 */
    "FESYS_CSYS_CLOCK",	
    "MDSYS_SHAOLIN_CLOCK",		
    "FESYS_BSI_CLOCK",	
    "MDSYS_MDCORE_CLOCK",		
    "MDSYS_BUS2X_NODCM_CLOCK",/* 20 */
    "MDSYS_BUS4X_CLOCK",	
    "MDTOP_DBG_CLOCK",	
    "AD_MDBPI_PLL_D7",		
    "AD_MDBPI_PLL_D5",
    "AD_MDBPI_PLL_D4",        /* 25 */
    "AD_MDBPI_PLL_D3",	
    "AD_MDBPI_PLL_D2",	
    "AD_MDBRP_PLL",		
    "AD_MDVDSP_PLL",
    "AD_MDMCU_PLL",	          /* 30 */	
    "DFESYS_RXDFE_BB_CORE_CLOCK",
    "AD_MDNRPLL4_2",  
    "MDTOP_BUS4X_FIXED_CLOCK",
    "DA_DRF_26M_CLOCK",      
    "MDTOP_BUS4X_CLOCK",	  /* 35 */
    "RXCPC_CPC_CLOCK",		
    "RXDDMBRP_RXDBRP_CLOCK",
    "RXDDMBRP_RXDDM_CLOCK",	  	
    "MCORE_MCORE_CLOCK",	
    "VCOREHRAM_VCORE_CLOCK",  /* 40 */	
    "VCOREHRAM_HRAM_CLOCK",		
    "FESYS_TXBSRP_CLOCK",
    "FESYS_MDPLL_CLOCK",	  
    "TX_CS_NR_RXT2F_NR_CLOCK",	
    "TX_CS_NR_TXBSRP_NR_CLOCK",/* 45 */
    "TX_CS_NR_CM_NR_CLOCK",		
    "TX_CS_NR_CS_NR_CLOCK" 
    /* we couldn't add more PLL here... */
};

PLL_CLK_INFO g_pll_info = {0};

/* Above for debugging */

/**
 * This function is used to detect ASIC or FPGA version of Palladium
 */
__PLL_CODE_IN_BOOT__ kal_bool PLL_FPGA_IS_ASIC(void)
{
#if defined(__FPGA__)
    kal_uint32 asic_flag = *((volatile kal_uint32 *)(0xA0000018)) & (0x1 << 7);

    if (asic_flag == 0)
        return KAL_TRUE;
    else
        return KAL_FALSE;
#else
    return KAL_TRUE;
#endif
}

__PLL_CODE_IN_BOOT__ void INT_SetPLL_Gen97P(void)
{

}

__PLL_CODE_IN_BOOT__ kal_uint8 pll_get_current_vpe_id(void)
{
    unsigned int vpe_id = 0;

    __asm__ __volatile__(
        "mfc0 %0, $15, 1" \
        : "=r" (vpe_id) \
        :);

    return (vpe_id & 0xF);
}

/*************************************************************************
 * FUNCTION
 *  INT_SetPLL
 *
 * DESCRIPTION
 *  This function dedicates for PLL setting.
 *
 * PARAMETERS
 *  Init mode of PLL
 *
 * RETURNS
 * Note    :    This function would only call by MD. 
 *************************************************************************/
__PLL_CODE_IN_BOOT__ void INT_SetPLL(void)
{
#if !defined(__COSIM_BYPASS__) && !defined(__ESL_MASE__)
    if ((pll_get_current_vpe_id() == 0)) 
    {
        if (*REG_MDTOP_PLLMIXED_PLL_DUMMY != MD_PLL_MAGIC_NUM) 
        {/* PLL didn't init by BootRom */
            PLL_MD_Pll_Init();

            // Make a record that means MD pll has init by MD. 
            *REG_MDTOP_PLLMIXED_PLL_DUMMY = MD_PLL_MAGIC_MD;           
        }
    }
#endif // __COSIM_BYPASS__
}

/*************************************************************************
 * FUNCTION
 *  PLL_MD_Pll_Init
 *
 * DESCRIPTION
 *  This function dedicates for PLL setting.
 *
 * PARAMETERS
 *  Init mode of PLL
 *
 * RETURNS
 * Note    :    This function would call by BootRom and MD!! 
 *************************************************************************/
__PLL_CODE_IN_BOOT__ void PLL_MD_Pll_Init(void)
{
#if !defined(__COSIM_BYPASS__) && !defined(__ESL_MASE__)
    INT_SetPLL_Gen97P();
#endif // __COSIM_BYPASS__
}

 /*------------------------------------------------------------------------
 * void    PLL_Check_26M_ACK_Status
 * Purpose:	Check 26M ACK Status to know 26M is ready.
 * Parameters:
 *    Input:	kal_uint32 identifier: Any value to let us confirm the caller.
 *              
 *    Output:	None.
 *              
 * returns :	void.
 * Note    :    This function would call by Idle_Service_Handler()
 *               
 *------------------------------------------------------------------------
 */ 
void PLL_Check_26M_ACK_Status(kal_uint32 identifier)
{   
  #if defined(__PRODUCTION_RELEASE__) || defined(__MAUI_BASIC__) || defined(__MODEM_ONLY__)
    /* Do nothing. */
  #else
/* under construction !*/
  #endif
}

 /*------------------------------------------------------------------------
 * void    PLL_Set_CLK_To_26M
 * Purpose:	Re-configure all the module clocks from PLL to 26M.
 * Parameters:
 *    Input:	None.
 *              
 *    Output:	None.
 *              
 * returns :	void.
 * Note    :    This function would call by BootRom!!
 *               
 *------------------------------------------------------------------------
 */ 
__PLL_CODE_IN_BOOT__ void PLL_Set_CLK_To_26M(void)
{   
    *REG_MDTOP_CLKSW_CLKON_CTL = 0x10001;       // set to default value 
    *REG_MDTOP_CLKSW_CLKSEL_CTL = 0x14000;      //switch all clock to XTAL frequency
    *REG_MDTOP_CLKSW_CLKSEL_CTL_2 = 0x0;        //switch all clock to XTAL frequency
    *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL = 0x100001; // switch SDF clock to XTAL frequency

    MO_Sync();
    // Make a record that means MD pll has been changed to 26M. 
    *REG_MDTOP_PLLMIXED_PLL_DUMMY = MD_PLL_MAGIC_26M;   
}

 /*------------------------------------------------------------------------
 * void    PLL_FrequencyMeter_GetFreq
 * Purpose:	Get specified PLL/module's clock(Mhz).
 * Parameters:
 *    Input:	PLL_FM_SOURCE index: The module you want to measure.
 *              
 *    Output:	None.
 *              
 * returns :	The PLL/module's clock(Mhz).
 * Note    :    This function would spend at least 20us to measure the clock.
 *               
 *------------------------------------------------------------------------
 */ 
kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index)
{
    kal_uint32 count = 5000, output = 0;

    if ((index < PLL_FM_SOURCE_START) || (index > PLL_FM_SOURCE_END))
        return 0; 

    *REG_MDTOP_CLKSW_CKMON_CTL = PLL_FM_MDSYS_BUS4X_CLOCK; //select source to a valid clock to let reset success.

    *REG_MDTOP_CLKSW_FREQ_METER_CTL = 0;        //reset frequency meter

    MO_Sync(); 
    ust_us_busyloop(2);//let Frequency Meter reset done   
    
    *REG_MDTOP_CLKSW_CKMON_CTL = 0x300 | index; //divided by 8 and select source
    *REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT = PLL_FM_WIMDOW;
    *REG_MDTOP_CLKSW_FREQ_METER_CTL = 1;        //enable frequency meter
    MO_Sync();

    // wait measure done or timeout
    while (((*REG_MDTOP_CLKSW_FREQ_METER_CTL) & (1 << 1)) == 0) 
    {
        count--;
        if (count == 0)
            break;
    }

    if (count == 0)
        return 0;

    output = *REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT * 26 * 8 / (PLL_FM_WIMDOW+3);

    *REG_MDTOP_CLKSW_CKMON_CTL = 0;        //select source to NULL to save power in flip-flop, save about 0.07mA in 6293

    *REG_MDTOP_CLKSW_FREQ_METER_CTL = 0;        //reset frequency meter

    return output;
}

void PLL_exception_dump(void)
{ 
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}


/****************************************************************
    Function for SDF module. (SIB)
****************************************************************/
 /*------------------------------------------------------------------------
 * void    PLL_CLKSW_SDF_SRC_CKSEL_Get
 * Purpose:	Get the selection of SDF source clock.
 * Parameters:
 *    Input:    None.
 *              
 *    Output:   None.
 *
 * returns :    The selection of SDF source clock.
 *              
 * Note    :    
 *               
 *------------------------------------------------------------------------
 */
kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get()
{
    if((*REG_MDTOP_CLKSW_SDF_ATB_CK_CTL&(1<<4))==0)
    {
        return CLKSW_SDF_SRC_26M;
    }
    else
    {
        return (((*REG_MDTOP_CLKSW_SDF_ATB_CK_CTL) & 0x00000180) >> 7);
    }   
}

 /*------------------------------------------------------------------------
 * void    PLL_CLKSW_SDF_SRC_CKSEL_Div_Get
 * Purpose:	Get the selection of SDF source clock Div.
 * Parameters:
 *    Input:    None.
 *              
 *    Output:   None.
 *
 * returns :    The selection of SDF source clock Div
 *              
 * Note    :    
 *               
 *------------------------------------------------------------------------
 */
kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Div_Get()
{
    return (((*REG_MDTOP_CLKSW_SDF_ATB_CK_CTL) & 0x00000060) >> 5);   
}

 /*------------------------------------------------------------------------
 * void    PLL_CLKSW_SDF_SRC_CKSEL_Set
 * Purpose:	Set the selection of SDF source clock.
 * Parameters:
 *    Input:    PLL_CLKSW_SDF_SRC src_ck:      CLKSW_SDF_SRC_xxx in "Pll_gen97.h", src_clk index.
 *              PLL_CLKSW_SDF_SRC_DIV src_div: CLKSW_SDF_SRC_xxx in "Pll_gen97.h", src_div index.
 *    Output:   None.
 *
 * returns :    KAL_TRUE/KAL_FALSE
 *              
 * Note    :    Porting from LR12's PLL_SDF_SRC_CKSEL_SET().
 *               
 *------------------------------------------------------------------------
 */
kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_clk, PLL_CLKSW_SDF_SRC_DIV src_div)
{
    kal_uint32 /*caller_LR, */tmp = 0;
    //GET_RETURN_ADDRESS(caller_LR);
    
    if (src_clk >= CLKSW_SDF_SRC_END)
    {
        //EXT_ASSERT(0, caller_LR, src_clk, 0);
        return KAL_FALSE;
    }

    if(src_clk == CLKSW_SDF_SRC_26M)
    {/* Restore to default setting */
        
        // SDF clock switch to 26Mhz
        *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL &= ~(1<<4);

        //restore SDF clock source
        *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL = ((*REG_MDTOP_CLKSW_SDF_ATB_CK_CTL) & 0xFFFFFC1F);        
    }
    else
    {
        // SDF clock switch to 26Mhz
        *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL &= ~(1<<4);
    
        //set SDF clock source
        tmp = (src_clk<<7) | (src_div<<5);
        *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL = ((*REG_MDTOP_CLKSW_SDF_ATB_CK_CTL) & 0xFFFFFC1F) | (tmp);
    
        // SDF clock switch to full speed
        *REG_MDTOP_CLKSW_SDF_ATB_CK_CTL |= (1<<4);
    }

    MO_Sync();

    return KAL_TRUE;
}

#endif /* should NOT be compiled on MODIS */