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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / devdrv / pmic / src / dcl_pmic6325.c
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2014
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * dcl_pmic6325.c
41 *
42 * Project:
43 * --------
44 * MOLY Software
45 *
46 * Description:
47 * ------------
48 * This file is for PMIC 6325
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 * removed!
60 * removed!
61 *
62 * removed!
63 * removed!
64 * removed!
65 * removed!
66 *
67 * removed!
68 * removed!
69 * removed!
70 *
71 * removed!
72 * removed!
73 * removed!
74 *
75 * removed!
76 * removed!
77 * removed!
78 *
79 * removed!
80 * removed!
81 * removed!
82 *
83 * removed!
84 * removed!
85 * removed!
86 *
87 * removed!
88 * removed!
89 * removed!
90 *------------------------------------------------------------------------------
91 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
92 *============================================================================
93 ****************************************************************************/
94
95#if defined(FPGA_CTP)
96#include <common.h>
97#endif
98
99#include "reg_base.h"
100#include "drv_comm.h"
101#include "init.h"
102#include "dcl.h"
103#include "dcl_pmu_sw.h"
104#include "pmic_wrap.h"
105#include "kal_public_api.h"
106#include "us_timer.h"
107#include "dhl_trace.h"
108#if defined(PMIC_6325_REG_API)
109
110// Start PMIC_UNIT_TEST
111//#define PMIC_UNIT_TEST
112// ARM Section RW/RO/ZI Use Internal SRAM
113//#define PMIC_INTERNAL_SRAM
114#if !defined(__FUE__)
115#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
116#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
117#else /*defined(__FUE__)*/
118#define SAVEANDSETIRQMASK() 0
119#define RESTOREIRQMASK(mask) {}
120#endif /*defined(__FUE__)*/
121
122#define BANKS_NUM 1
123#define PMIC6325_MAX_REG_NUM 0x0F50 // 0x0000~0x0F48
124//#define PMIC_MAX_REG_NUM 0x40FF // Register BUCK1, Register ANALDO, Register DIGLDO (0x0470)
125
126#define MT6325_HW_CID_E1 0x2510
127#define MT6325_HW_CID_E2 0x2520
128#define MT6325_HW_CID_E3 0x2530
129#define MT6325_SW_CID_E1 0x2510
130#define MT6325_SW_CID_E2 0x2520
131#define MT6325_SW_CID_E3 0x2530
132
133#define PMIC_READ 0
134#define PMIC_WRITE 1
135
136#define PMIC_6325 0x6325
137
138//////////////////////////////////////////////////
139// Exported APIs //
140//////////////////////////////////////////////////
141extern kal_bool pmic6325_reg_write(kal_uint16 reg, kal_uint16 val);
142extern kal_bool pmic6325_reg_read(kal_uint16 reg, kal_uint16 *pVal);
143
144extern DCL_BOOL dcl_pmic_init_done_query(void);
145typedef enum
146{
147 AUXADC_READ_INIT = 0,
148 AUXADC_READ_REQUEST = 1,
149 AUXADC_READ_READY = 2,
150 AUXADC_READ_BUSY = 3,
151 AUXADC_READ_DATA = 4
152}AUXADC_FSM;
153
154typedef struct
155{
156 kal_uint32 command_flag;
157 kal_uint32 reg_before_write;
158 kal_uint32 write_value;
159 kal_uint32 address_offset;
160 kal_uint32 reg_mask;
161 kal_uint32 reg_shift;
162 kal_uint32 reg_addr;
163 kal_uint32 reg_data;
164}PMIC_REG_LOG;
165
166AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
167PMIC_REG_LOG pmic_reg_log;
168
169//#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
170//__attribute__ ((zero_init))
171//#endif /* __MTK_TARGET__ */
172kal_uint8 pmic6325_hw_version;
173kal_uint8 pmic6325_sw_version;
174kal_uint16 pmic6325_reg[PMIC6325_MAX_REG_NUM];
175DCL_BOOL pmic_init_done = DCL_FALSE;
176
177const PMIC_FLAG_TABLE_ENTRY pmic6325_flags_table[] =
178{
179 {MT6325_HWCID, MT6325_HWCID_MASK, MT6325_HWCID_SHIFT, },
180 {MT6325_SWCID, MT6325_SWCID_MASK, MT6325_SWCID_SHIFT, },
181 {MT6325_VPA_ANA_CON1, MT6325_RG_VPA_MODESET_MASK, MT6325_RG_VPA_MODESET_SHIFT, },
182 {MT6325_VRF18_0_ANA_CON1, MT6325_RG_VRF18_0_MODESET_MASK, MT6325_RG_VRF18_0_MODESET_SHIFT, },
183 {MT6325_VRF18_0_CON7, MT6325_VRF18_0_EN_CTRL_MASK, MT6325_VRF18_0_EN_CTRL_SHIFT, },
184 {MT6325_VRF18_0_CON7, MT6325_VRF18_0_VOSEL_CTRL_MASK, MT6325_VRF18_0_VOSEL_CTRL_SHIFT, },
185 {MT6325_VRF18_0_CON8, MT6325_VRF18_0_EN_SEL_MASK, MT6325_VRF18_0_EN_SEL_SHIFT, },
186 {MT6325_VRF18_0_CON8, MT6325_VRF18_0_VOSEL_SEL_MASK, MT6325_VRF18_0_VOSEL_SEL_SHIFT, },
187 {MT6325_VRF18_0_CON9, MT6325_VRF18_0_EN_MASK, MT6325_VRF18_0_EN_SHIFT, },
188 {MT6325_VRF18_0_CON11, MT6325_VRF18_0_VOSEL_MASK, MT6325_VRF18_0_VOSEL_SHIFT, },
189 {MT6325_VRF18_0_CON12, MT6325_VRF18_0_VOSEL_ON_MASK, MT6325_VRF18_0_VOSEL_ON_SHIFT, },
190 {MT6325_VRF18_0_CON13, MT6325_VRF18_0_VOSEL_SLEEP_MASK, MT6325_VRF18_0_VOSEL_SLEEP_SHIFT, },
191 {MT6325_VRF18_0_CON18, MT6325_VRF18_0_VSLEEP_EN_MASK, MT6325_VRF18_0_VSLEEP_EN_SHIFT, },
192 {MT6325_VPA_CON8, MT6325_VPA_EN_SEL_MASK, MT6325_VPA_EN_SEL_SHIFT, },
193 {MT6325_VPA_CON8, MT6325_VPA_VOSEL_SEL_MASK, MT6325_VPA_VOSEL_SEL_SHIFT, },
194 {MT6325_VPA_CON9, MT6325_VPA_EN_MASK, MT6325_VPA_EN_SHIFT, },
195 {MT6325_VPA_CON11, MT6325_VPA_VOSEL_MASK, MT6325_VPA_VOSEL_SHIFT, },
196 {MT6325_VPA_CON12, MT6325_VPA_VOSEL_ON_MASK, MT6325_VPA_VOSEL_ON_SHIFT, },
197 {MT6325_VPA_CON13, MT6325_VPA_VOSEL_SLEEP_MASK, MT6325_VPA_VOSEL_SLEEP_SHIFT, },
198 {MT6325_LDO_CON0, MT6325_RG_VTCXO0_MODE_SET_MASK, MT6325_RG_VTCXO0_MODE_SET_SHIFT, },
199 {MT6325_LDO_CON0, MT6325_RG_VTCXO0_EN_MASK, MT6325_RG_VTCXO0_EN_SHIFT, },
200 {MT6325_LDO_CON0, MT6325_RG_VTCXO0_MODE_CTRL_MASK, MT6325_RG_VTCXO0_MODE_CTRL_SHIFT, },
201 {MT6325_LDO_CON0, MT6325_RG_VTCXO0_ON_CTRL_MASK, MT6325_RG_VTCXO0_ON_CTRL_SHIFT, },
202 {MT6325_LDO_CON0, MT6325_RG_VTCXO0_SRCLK_MODE_SEL_MASK, MT6325_RG_VTCXO0_SRCLK_MODE_SEL_SHIFT, },
203 {MT6325_LDO_CON0, MT6325_QI_VTCXO0_MODE_MASK, MT6325_QI_VTCXO0_MODE_SHIFT, },
204 {MT6325_LDO_CON1, MT6325_RG_VTCXO1_MODE_SET_MASK, MT6325_RG_VTCXO1_MODE_SET_SHIFT, },
205 {MT6325_LDO_CON1, MT6325_RG_VTCXO1_EN_MASK, MT6325_RG_VTCXO1_EN_SHIFT, },
206 {MT6325_LDO_CON1, MT6325_RG_VTCXO1_MODE_CTRL_MASK, MT6325_RG_VTCXO1_MODE_CTRL_SHIFT, },
207 {MT6325_LDO_CON1, MT6325_RG_VTCXO1_ON_CTRL_MASK, MT6325_RG_VTCXO1_ON_CTRL_SHIFT, },
208 {MT6325_LDO_CON1, MT6325_RG_VTCXO1_SRCLK_MODE_SEL_MASK, MT6325_RG_VTCXO1_SRCLK_MODE_SEL_SHIFT, },
209 {MT6325_LDO_CON1, MT6325_QI_VTCXO1_MODE_MASK, MT6325_QI_VTCXO1_MODE_SHIFT, },
210 {MT6325_LDO_CON8, MT6325_RG_VRF18_1_MODE_SET_MASK, MT6325_RG_VRF18_1_MODE_SET_SHIFT, },
211 {MT6325_LDO_CON8, MT6325_RG_VRF18_1_EN_MASK, MT6325_RG_VRF18_1_EN_SHIFT, },
212 {MT6325_LDO_CON8, MT6325_RG_VRF18_1_MODE_CTRL_MASK, MT6325_RG_VRF18_1_MODE_CTRL_SHIFT, },
213 {MT6325_LDO_CON8, MT6325_RG_VRF18_1_ON_CTRL_MASK, MT6325_RG_VRF18_1_ON_CTRL_SHIFT, },
214 {MT6325_LDO_CON8, MT6325_RG_VRF18_1_SRCLK_MODE_SEL_MASK, MT6325_RG_VRF18_1_SRCLK_MODE_SEL_SHIFT, },
215 {MT6325_LDO_CON8, MT6325_QI_VRF18_1_MODE_MASK, MT6325_QI_VRF18_1_MODE_SHIFT, },
216 {MT6325_LDO_CON8, MT6325_RG_VRF18_1_SRCLK_EN_SEL_MASK, MT6325_RG_VRF18_1_SRCLK_EN_SEL_SHIFT, },
217 {MT6325_LDO_CON17, MT6325_RG_VSIM1_MODE_SET_MASK, MT6325_RG_VSIM1_MODE_SET_SHIFT, },
218 {MT6325_LDO_CON17, MT6325_RG_VSIM1_EN_MASK, MT6325_RG_VSIM1_EN_SHIFT, },
219 {MT6325_LDO_CON17, MT6325_RG_VSIM1_MODE_CTRL_MASK, MT6325_RG_VSIM1_MODE_CTRL_SHIFT, },
220 {MT6325_LDO_CON17, MT6325_RG_VSIM1_ON_CTRL_MASK, MT6325_RG_VSIM1_ON_CTRL_SHIFT, },
221 {MT6325_LDO_CON17, MT6325_RG_VSIM1_SRCLK_MODE_SEL_MASK, MT6325_RG_VSIM1_SRCLK_MODE_SEL_SHIFT, },
222 {MT6325_LDO_CON17, MT6325_QI_VSIM1_MODE_MASK, MT6325_QI_VSIM1_MODE_SHIFT, },
223 {MT6325_LDO_CON17, MT6325_RG_VSIM1_STBTD_MASK, MT6325_RG_VSIM1_STBTD_SHIFT, },
224 {MT6325_LDO_CON17, MT6325_RG_VSIM1_SRCLK_EN_SEL_MASK, MT6325_RG_VSIM1_SRCLK_EN_SEL_SHIFT, },
225 {MT6325_LDO_CON18, MT6325_RG_VSIM2_MODE_SET_MASK, MT6325_RG_VSIM2_MODE_SET_SHIFT, },
226 {MT6325_LDO_CON18, MT6325_RG_VSIM2_EN_MASK, MT6325_RG_VSIM2_EN_SHIFT, },
227 {MT6325_LDO_CON18, MT6325_RG_VSIM2_MODE_CTRL_MASK, MT6325_RG_VSIM2_MODE_CTRL_SHIFT, },
228 {MT6325_LDO_CON18, MT6325_RG_VSIM2_ON_CTRL_MASK, MT6325_RG_VSIM2_ON_CTRL_SHIFT, },
229 {MT6325_LDO_CON18, MT6325_RG_VSIM2_SRCLK_MODE_SEL_MASK, MT6325_RG_VSIM2_SRCLK_MODE_SEL_SHIFT, },
230 {MT6325_LDO_CON18, MT6325_QI_VSIM2_MODE_MASK, MT6325_QI_VSIM2_MODE_SHIFT, },
231 {MT6325_LDO_CON18, MT6325_RG_VSIM2_STBTD_MASK, MT6325_RG_VSIM2_STBTD_SHIFT, },
232 {MT6325_LDO_CON18, MT6325_RG_VSIM2_SRCLK_EN_SEL_MASK, MT6325_RG_VSIM2_SRCLK_EN_SEL_SHIFT, },
233 {MT6325_LDO_CON18, MT6325_QI_VSIM2_STB_MASK, MT6325_QI_VSIM2_STB_SHIFT, },
234 {MT6325_LDO_CON18, MT6325_QI_VSIM2_EN_MASK, MT6325_QI_VSIM2_EN_SHIFT, },
235 {MT6325_LDO_CON19, MT6325_RG_VMIPI_MODE_SET_MASK, MT6325_RG_VMIPI_MODE_SET_SHIFT, },
236 {MT6325_LDO_CON19, MT6325_RG_VMIPI_EN_MASK, MT6325_RG_VMIPI_EN_SHIFT, },
237 {MT6325_LDO_CON19, MT6325_RG_VMIPI_MODE_CTRL_MASK, MT6325_RG_VMIPI_MODE_CTRL_SHIFT, },
238 {MT6325_LDO_CON19, MT6325_RG_VMIPI_ON_CTRL_MASK, MT6325_RG_VMIPI_ON_CTRL_SHIFT, },
239 {MT6325_LDO_CON19, MT6325_RG_VMIPI_SRCLK_MODE_SEL_MASK, MT6325_RG_VMIPI_SRCLK_MODE_SEL_SHIFT, },
240 {MT6325_LDO_CON19, MT6325_QI_VMIPI_MODE_MASK, MT6325_QI_VMIPI_MODE_SHIFT, },
241 {MT6325_LDO_CON19, MT6325_RG_VMIPI_STBTD_MASK, MT6325_RG_VMIPI_STBTD_SHIFT, },
242 {MT6325_LDO_CON19, MT6325_RG_VMIPI_SRCLK_EN_SEL_MASK, MT6325_RG_VMIPI_SRCLK_EN_SEL_SHIFT, },
243 {MT6325_LDO_CON19, MT6325_QI_VMIPI_EN_MASK, MT6325_QI_VMIPI_EN_SHIFT, },
244 {MT6325_LDO_VCON9, MT6325_RG_VSIM2_VOSEL_MASK, MT6325_RG_VSIM2_VOSEL_SHIFT, },
245 {MT6325_LDO_VCON9, MT6325_RG_VSIM1_VOSEL_MASK, MT6325_RG_VSIM1_VOSEL_SHIFT, },
246 {MT6325_LDO_OCFB1, MT6325_RG_VSIM2_OCFB_EN_MASK, MT6325_RG_VSIM2_OCFB_EN_SHIFT, },
247 {MT6325_LDO_OCFB1, MT6325_RG_VSIM1_OCFB_EN_MASK, MT6325_RG_VSIM1_OCFB_EN_SHIFT, },
248 {MT6325_SPK_CON8, MT6325_RG_SPK_CCODE_MASK, MT6325_RG_SPK_CCODE_SHIFT, },
249 {MT6325_SPK_CON8, MT6325_RG_SPK_EN_VIEW_VCM_MASK, MT6325_RG_SPK_EN_VIEW_VCM_SHIFT, },
250 {MT6325_SPK_CON8, MT6325_RG_SPK_FBRC_EN_MASK, MT6325_RG_SPK_FBRC_EN_SHIFT, },
251 {MT6325_SPK_CON9, MT6325_SPK_TEST_MODE0_MASK, MT6325_SPK_TEST_MODE0_SHIFT, },
252 {MT6325_SPK_CON10, MT6325_SPK_TD_DONE_MASK, MT6325_SPK_TD_DONE_SHIFT, },
253 {MT6325_AUXADC_RQST1_SET, MT6325_AUXADC_RQST1_SET_MASK, MT6325_AUXADC_RQST1_SET_SHIFT, },
254 {MT6325_AUXADC_RQST1_CLR, MT6325_AUXADC_RQST1_CLR_MASK, MT6325_AUXADC_RQST1_CLR_SHIFT, },
255 {MT6325_AUXADC_ADC15, MT6325_RG_ADC_OUT_MD_MASK, MT6325_RG_ADC_OUT_MD_SHIFT, },
256 {MT6325_AUXADC_ADC16, MT6325_RG_ADC_RDY_MD_MASK, MT6325_RG_ADC_RDY_MD_SHIFT, },
257 {MT6325_AUXADC_CON20, MT6325_RG_MD_RQST_MASK, MT6325_RG_MD_RQST_SHIFT, },
258 {MT6325_AUXADC_CON27, MT6325_RG_VREF18_ENB_MD_MASK, MT6325_RG_VREF18_ENB_MD_SHIFT, },
259};
260//////////////////////////////////////////////////
261// WRITE APIs //
262//////////////////////////////////////////////////
263
264// Write Whole Bytes
265void dcl_pmic6325_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
266{
267 kal_uint32 savedMask = 0;
268#if !defined(__UBL__) && !defined(__FUE__)
269 savedMask = SaveAndSetIRQMask();
270#endif //#if !defined(__UBL__) && !defined(__FUE__)
271
272#if defined(DCL_PMIC_ACCESS_TIME_LOG)
273 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
274#endif
275
276 pmic6325_reg[addr] = val;
277
278 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
279
280#if defined(DCL_PMIC_ACCESS_TIME_LOG)
281 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
282 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
283#endif
284
285#if !defined(__UBL__) && !defined(__FUE__)
286 RestoreIRQMask(savedMask);
287#endif //#if !defined(__UBL__) && !defined(__FUE__)
288}
289
290// Write register field
291void dcl_pmic6325_field_write(PMIC6325_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
292{
293 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6325_flags_table;
294 kal_uint32 savedMask = 0;
295#if !defined(__UBL__) && !defined(__FUE__)
296 savedMask = SaveAndSetIRQMask();
297#endif //#if !defined(__UBL__) && !defined(__FUE__)
298
299#if defined(DCL_PMIC_ACCESS_TIME_LOG)
300 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
301#endif
302
303 pmic_reg_log.command_flag = flag;
304 pmic_reg_log.reg_before_write = pmic6325_reg[pTable[flag].offset];
305
306 pmic6325_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
307 pmic6325_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
308
309 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic6325_reg[pTable[flag].offset], 0x00);
310
311 pmic_reg_log.write_value = sel;
312 pmic_reg_log.address_offset = pTable[flag].offset;
313 pmic_reg_log.reg_mask = pTable[flag].mask;
314 pmic_reg_log.reg_shift = pTable[flag].shift;
315 pmic_reg_log.reg_addr = pTable[flag].offset;
316 pmic_reg_log.reg_data = pmic6325_reg[pTable[flag].offset];
317
318#if defined(DCL_PMIC_ACCESS_TIME_LOG)
319 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
320 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
321#endif
322
323#if !defined(__UBL__) && !defined(__FUE__)
324 RestoreIRQMask(savedMask);
325#endif //#if !defined(__UBL__) && !defined(__FUE__)
326}
327
328//////////////////////////////////////////////////
329// READ APIs //
330//////////////////////////////////////////////////
331
332// Read Whole Bytes
333DCL_UINT16 dcl_pmic6325_byte_return(DCL_UINT16 addr)
334{
335 DCL_UINT16 reg_temp;
336 kal_uint32 savedMask = 0;
337
338#if !defined(__UBL__) && !defined(__FUE__)
339 savedMask = SaveAndSetIRQMask();
340#endif //#if !defined(__UBL__) && !defined(__FUE__)
341
342#if defined(DCL_PMIC_ACCESS_TIME_LOG)
343 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
344#endif
345
346 DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
347
348 pmic6325_reg[addr] = reg_temp;
349
350#if defined(DCL_PMIC_ACCESS_TIME_LOG)
351 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
352 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
353#endif
354
355#if !defined(__UBL__) && !defined(__FUE__)
356 RestoreIRQMask(savedMask);
357#endif //#if !defined(__UBL__) && !defined(__FUE__)
358
359 return reg_temp;
360}
361
362// Read register field
363DCL_UINT16 dcl_pmic6325_field_read(PMIC6325_FLAGS_LIST_ENUM flag)
364{
365 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6325_flags_table;
366 kal_uint32 savedMask = 0;
367 DCL_UINT16 reg_return = 0;
368
369#if !defined(__UBL__) && !defined(__FUE__)
370 savedMask = SaveAndSetIRQMask();
371#endif //#if !defined(__UBL__) && !defined(__FUE__)
372
373#if defined(DCL_PMIC_ACCESS_TIME_LOG)
374 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
375#endif
376
377 DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic6325_reg[pTable[flag].offset]);
378
379 reg_return = ((pmic6325_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
380
381#if defined(DCL_PMIC_ACCESS_TIME_LOG)
382 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
383 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
384#endif
385
386#if !defined(__UBL__) && !defined(__FUE__)
387 RestoreIRQMask(savedMask);
388#endif //#if !defined(__UBL__) && !defined(__FUE__)
389
390 return reg_return;
391}
392
393
394// Exported for EM used
395void pmic6325_EM_reg_write(kal_uint16 reg, kal_uint16 val){
396 dcl_pmic6325_byte_write(reg, val);
397}
398
399kal_uint16 pmic6325_EM_reg_read(kal_uint16 reg){
400 return dcl_pmic6325_byte_return(reg);
401}
402
403PMU_CTRL_PMIC_ECO_VERSION_ENUM pmic6325_get_HW_ECO_version(void)
404{
405 return pmic6325_hw_version;
406}
407
408PMU_CTRL_PMIC_ECO_VERSION_ENUM pmic6325_get_SW_version(void)
409{
410 return pmic6325_sw_version;
411}
412
413/*
414const DCL_UINT32 vpa_vosel[] =
415{
416 PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V,
417 PMU_VOLT_00_700000_V, PMU_VOLT_00_750000_V, PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V,
418 PMU_VOLT_00_900000_V, PMU_VOLT_00_950000_V, PMU_VOLT_01_000000_V, PMU_VOLT_01_050000_V,
419 PMU_VOLT_01_100000_V, PMU_VOLT_01_150000_V, PMU_VOLT_01_200000_V, PMU_VOLT_01_250000_V,
420 PMU_VOLT_01_300000_V, PMU_VOLT_01_350000_V, PMU_VOLT_01_400000_V, PMU_VOLT_01_450000_V,
421 PMU_VOLT_01_500000_V, PMU_VOLT_01_550000_V, PMU_VOLT_01_600000_V, PMU_VOLT_01_650000_V,
422 PMU_VOLT_01_700000_V, PMU_VOLT_01_750000_V, PMU_VOLT_01_800000_V, PMU_VOLT_01_850000_V,
423 PMU_VOLT_01_900000_V, PMU_VOLT_01_950000_V, PMU_VOLT_02_000000_V, PMU_VOLT_02_050000_V,
424 PMU_VOLT_02_100000_V, PMU_VOLT_02_150000_V, PMU_VOLT_02_200000_V, PMU_VOLT_02_250000_V,
425 PMU_VOLT_02_300000_V, PMU_VOLT_02_350000_V, PMU_VOLT_02_400000_V, PMU_VOLT_02_450000_V,
426 PMU_VOLT_02_500000_V, PMU_VOLT_02_550000_V, PMU_VOLT_02_600000_V, PMU_VOLT_02_650000_V,
427 PMU_VOLT_02_700000_V, PMU_VOLT_02_750000_V, PMU_VOLT_02_800000_V, PMU_VOLT_02_850000_V,
428 PMU_VOLT_02_900000_V, PMU_VOLT_02_950000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_050000_V,
429 PMU_VOLT_03_100000_V, PMU_VOLT_03_150000_V, PMU_VOLT_03_200000_V, PMU_VOLT_03_250000_V,
430 PMU_VOLT_03_300000_V, PMU_VOLT_03_350000_V, PMU_VOLT_03_400000_V, PMU_VOLT_03_450000_V,
431 PMU_VOLT_03_500000_V, PMU_VOLT_03_550000_V, PMU_VOLT_03_600000_V, PMU_VOLT_03_650000_V,
432
433};
434*/
435
436const DCL_UINT32 vpa_vosel[] =
437{
438 PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
439 PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
440 PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
441 PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
442 PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
443 PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
444 PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
445 PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
446 PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
447 PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
448 PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
449 PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
450 PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
451 PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
452 PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
453 PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
454
455};
456
457// 3'b001: 1.65, 3'b010: 1.8 V, 3'b011: 1.85 V, 3'b101: 2.75V, 3'b110: 3.0 V, 3'b111: 3.1 V
458const DCL_UINT32 vsim1_vosel[] =
459{
460 PMU_VOLT_INVALID, PMU_VOLT_01_650000_V, PMU_VOLT_01_800000_V, PMU_VOLT_01_850000_V,
461 PMU_VOLT_INVALID, PMU_VOLT_02_750000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_100000_V,
462};
463
464PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
465{
466 {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
467 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
468 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
469};
470
471extern PMU_CONTROL_HANDLER pmu_control_handler;
472
473DCL_UINT16 pmu_parameter_size = 0;
474
475DCL_STATUS PMIC6325_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
476{
477 DCL_UINT16 regVal;
478 DCL_INT32 return_val = STATUS_FAIL;
479
480 switch(cmd)
481 {
482 case LDO_BUCK_SET_EN:
483 {
484 PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
485
486 switch(pLdoBuckCtrl->mod)
487 {
488 case VRF18_1:
489 {
490 dcl_pmic6325_field_write(MT6325_VRF18_0_EN, pLdoBuckCtrl->enable);
491 return_val = STATUS_OK;
492 }
493 break;
494
495 case VRF18_2:
496 {
497 dcl_pmic6325_field_write(MT6325_RG_VRF18_1_EN, pLdoBuckCtrl->enable);
498 return_val = STATUS_OK;
499 }
500 break;
501
502 case VSIM1:
503 {
504 dcl_pmic6325_field_write(MT6325_RG_VSIM1_EN, pLdoBuckCtrl->enable);
505 return_val = STATUS_OK;
506 }
507 break;
508
509 case VSIM2:
510 {
511 dcl_pmic6325_field_write(MT6325_RG_VSIM2_EN, pLdoBuckCtrl->enable);
512 return_val = STATUS_OK;
513 }
514 break;
515
516 case VMIPI:
517 {
518 dcl_pmic6325_field_write(MT6325_RG_VMIPI_EN, pLdoBuckCtrl->enable);
519 return_val = STATUS_OK;
520 }
521 break;
522
523 case VPA_SW:
524 {
525 dcl_pmic6325_field_write(MT6325_VPA_EN, pLdoBuckCtrl->enable);
526 return_val = STATUS_OK;
527 }
528 break;
529
530 default:
531 return_val = STATUS_UNSUPPORTED;
532 break;
533 }
534 }
535 break;
536
537 case LDO_BUCK_SET_LP_MODE_SET:
538 {
539 PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
540
541 switch(pLdoBuckCtrl->mod)
542 {
543 case VSIM1:
544 {
545 // 1'b0:Normal mode, 1'b1:Low power mode
546 dcl_pmic6325_field_write(MT6325_RG_VSIM1_MODE_SET, pLdoBuckCtrl->enable);
547 return_val = STATUS_OK;
548 }
549 break;
550
551 case VSIM2:
552 {
553 // 1'b0:Normal mode, 1'b1:Low power mode
554 dcl_pmic6325_field_write(MT6325_RG_VSIM2_MODE_SET, pLdoBuckCtrl->enable);
555 return_val = STATUS_OK;
556 }
557 break;
558
559 case VRF18_2:
560 {
561 dcl_pmic6325_field_write(MT6325_RG_VRF18_1_MODE_SET, pLdoBuckCtrl->enable);
562 return_val = STATUS_OK;
563 }
564 break;
565
566 default:
567 return_val = STATUS_UNSUPPORTED;
568 break;
569 }
570 }
571 break;
572
573 case LDO_BUCK_SET_LP_SEL:
574 {
575 PMU_CTRL_LDO_BUCK_SET_LP_SEL *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpSel);
576
577 switch(pLdoBuckCtrl->mod)
578 {
579 case VSIM1:
580 {
581 // 1'b0: SW control by VSIM1_MODE_SET, 1'b1: HW control by SRCLKEN
582 dcl_pmic6325_field_write(MT6325_RG_VSIM1_MODE_CTRL, pLdoBuckCtrl->onSel);
583 return_val = STATUS_OK;
584 }
585 break;
586
587 case VSIM2:
588 {
589 dcl_pmic6325_field_write(MT6325_RG_VSIM2_MODE_CTRL, pLdoBuckCtrl->onSel);
590 return_val = STATUS_OK;
591 }
592 break;
593
594 default:
595 return_val = STATUS_UNSUPPORTED;
596 break;
597 }
598 }
599 break;
600
601 case LDO_BUCK_SET_VOLTAGE:
602 {
603 PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
604 regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
605
606 switch(pLdoBuckCtrl->mod)
607 {
608 case VSIM1:
609 {
610 dcl_pmic6325_field_write(MT6325_RG_VSIM1_VOSEL, regVal);
611 return_val = STATUS_OK;
612 }
613 break;
614
615 case VSIM2:
616 {
617 dcl_pmic6325_field_write(MT6325_RG_VSIM2_VOSEL, regVal);
618 return_val = STATUS_OK;
619 }
620 break;
621
622 case VPA_SW:
623 {
624 dcl_pmic6325_field_write(MT6325_VPA_VOSEL, regVal);
625 return_val = STATUS_OK;
626 }
627 break;
628
629 default:
630 return_val = STATUS_UNSUPPORTED;
631 break;
632 }
633 }
634 break;
635
636 case LDO_BUCK_SET_EN_CTRL:
637 {
638 PMU_CTRL_LDO_BUCK_SET_EN_CTRL *pLdoBuckCtrl = &(data->rPMULdoBuckSetEnCtrl);
639
640 switch(pLdoBuckCtrl->mod)
641 {
642 case VRF18_1:
643 {
644 // 0: SW control1: HW control
645 dcl_pmic6325_field_write(MT6325_VRF18_0_EN_CTRL, pLdoBuckCtrl->mode);
646 return_val = STATUS_OK;
647 }
648 break;
649
650 case VRF18_2:
651 {
652 dcl_pmic6325_field_write(MT6325_RG_VRF18_1_ON_CTRL, pLdoBuckCtrl->mode);
653 return_val = STATUS_OK;
654 }
655 break;
656
657 case VMIPI:
658 {
659 // 0: SW control, 1: HW
660 dcl_pmic6325_field_write(MT6325_RG_VMIPI_ON_CTRL, pLdoBuckCtrl->mode);
661 return_val = STATUS_OK;
662 }
663 break;
664
665 default:
666 return_val = STATUS_UNSUPPORTED;
667 break;
668 }
669 }
670 break;
671
672 case LDO_BUCK_SET_OCFB_EN:
673 {
674 PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
675
676 switch(pLdoBuckCtrl->mod)
677 {
678 case VSIM1:
679 {
680 dcl_pmic6325_field_write(MT6325_RG_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
681 return_val = STATUS_OK;
682 }
683 break;
684
685 case VSIM2:
686 {
687 dcl_pmic6325_field_write(MT6325_RG_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
688 return_val = STATUS_OK;
689 }
690 break;
691
692 default:
693 return_val = STATUS_UNSUPPORTED;
694 break;
695 }
696 }
697 break;
698
699
700 case LDO_BUCK_SET_EN_SEL:
701 {
702 PMU_CTRL_LDO_BUCK_SET_EN_SEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetEnSel);
703
704 switch(pLdoBuckCtrl->mod)
705 {
706 case VRF18_1:
707 {
708 dcl_pmic6325_field_write(MT6325_VRF18_0_EN_SEL, pLdoBuckCtrl->sel);
709 return_val = STATUS_OK;
710 }
711 break;
712
713 case VRF18_2:
714 {
715 dcl_pmic6325_field_write(MT6325_RG_VRF18_1_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
716 return_val = STATUS_OK;
717 }
718 break;
719
720 case VSIM1:
721 {
722 dcl_pmic6325_field_write(MT6325_RG_VSIM1_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
723 return_val = STATUS_OK;
724 }
725 break;
726
727 case VSIM2:
728 {
729 dcl_pmic6325_field_write(MT6325_RG_VSIM2_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
730 return_val = STATUS_OK;
731 }
732 break;
733
734 case VMIPI:
735 {
736 dcl_pmic6325_field_write(MT6325_RG_VMIPI_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
737 return_val = STATUS_OK;
738 }
739 break;
740
741 default:
742 return_val = STATUS_UNSUPPORTED;
743 break;
744 }
745 }
746 break;
747
748 case LDO_BUCK_SET_SRCLK_MODE_SEL:
749 {
750 PMU_CTRL_LDO_BUCK_SET_SRCLK_MODE_SEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetSrclkModeSel);
751
752 switch(pLdoBuckCtrl->mod)
753 {
754 case VSIM1:
755 {
756 dcl_pmic6325_field_write(MT6325_RG_VSIM1_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
757 return_val = STATUS_OK;
758 }
759 break;
760
761 case VSIM2:
762 {
763 dcl_pmic6325_field_write(MT6325_RG_VSIM2_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
764 return_val = STATUS_OK;
765 }
766 break;
767
768 default:
769 return_val = STATUS_UNSUPPORTED;
770 break;
771 }
772 }
773 break;
774
775 case LDO_BUCK_SET_MODESET:
776 {
777 PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
778
779 switch(pLdoBuckCtrl->mod)
780 {
781 case VPA_SW:
782 {
783 dcl_pmic6325_field_write(MT6325_RG_VPA_MODESET, pLdoBuckCtrl->mode);
784 return_val = STATUS_OK;
785 }
786 break;
787
788 case VRF18_1:
789 {
790 dcl_pmic6325_field_write(MT6325_RG_VRF18_0_MODESET, pLdoBuckCtrl->mode);
791 return_val = STATUS_OK;
792 }
793 break;
794
795 default:
796 return_val = STATUS_UNSUPPORTED;
797 break;
798 }
799 }
800 break;
801
802 case VPA_SET_EN:
803 {
804 PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
805 dcl_pmic6325_field_write(MT6325_VPA_EN, pVpaSetEn->enable);
806 return_val = STATUS_OK;
807 }
808 break;
809
810 case VPA_GET_VOLTAGE_LIST:
811 {
812 PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
813 pVpaCtrl->pVoltageList = vpa_vosel;
814 pVpaCtrl->number = GETARRNUM(vpa_vosel);
815 return_val = STATUS_OK;
816 }
817 break;
818
819
820 case ADC_SET_RQST:
821 {
822 PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
823 if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
824 {
825 ASSERT(0);
826 }
827
828 dcl_pmic6325_byte_write(MT6325_TOP_CLKSQ_SET, (0x1 << 3));
829 dcl_pmic6325_byte_write(MT6325_AUXADC_CON27, (0x0 << MT6325_RG_VREF18_ENB_MD_SHIFT));
830 dcl_pmic6325_field_write(MT6325_RG_MD_RQST, 0x0); // Need Set 0 first
831
832 dcl_pmic6325_field_write(MT6325_RG_MD_RQST, pAdcCtrl->enable);
833 AUXADC_Status = AUXADC_READ_REQUEST;
834 return_val = STATUS_OK;
835 }
836 break;
837
838 case ADC_GET_RDY_MD:
839 {
840 PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
841
842 pAdcCtrl->status = (DCL_BOOL)dcl_pmic6325_field_read(MT6325_RG_ADC_RDY_MD);
843 if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
844 {
845 ASSERT(0);
846 }
847
848 if(pAdcCtrl->status == DCL_TRUE)
849 {
850 AUXADC_Status = AUXADC_READ_READY;
851 }
852 else
853 {
854 AUXADC_Status = AUXADC_READ_BUSY;
855 }
856
857 return_val = STATUS_OK;
858 }
859 break;
860
861 case ADC_GET_OUT_MD:
862 {
863 PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
864 if(AUXADC_Status != AUXADC_READ_READY)
865 {
866 ASSERT(0);
867 }
868 pAdcCtrl->data = (DCL_UINT32)dcl_pmic6325_field_read(MT6325_RG_ADC_OUT_MD);
869 AUXADC_Status = AUXADC_READ_DATA;
870 dcl_pmic6325_field_write(MT6325_RG_MD_RQST, 0x0);
871 dcl_pmic6325_byte_write(MT6325_TOP_CLKSQ_CLR, (0x1 << 3));
872 dcl_pmic6325_byte_write(MT6325_AUXADC_CON27, (0x1 << MT6325_RG_VREF18_ENB_MD_SHIFT));
873
874 return_val = STATUS_OK;
875 }
876 break;
877
878 case MISC_GET_HW_VERSION:
879 {
880 PMU_CTRL_MISC_GET_HW_VERSION *pMiscCtrl = &(data->rPMUMiscGetHwVersion);
881 if(pMiscCtrl->chip_name == PMIC_MT_6325)
882 {
883 pMiscCtrl->version = pmic6325_hw_version;
884 }
885 return_val = STATUS_OK;
886 }
887 break;
888 case MISC_SET_REGISTER_VALUE:
889 {
890 PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
891 pmic6325_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
892 return_val = STATUS_OK;
893 }
894 break;
895
896 case MISC_GET_REGISTER_VALUE:
897 {
898 PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
899 pChrCtrl->value = pmic6325_EM_reg_read(pChrCtrl->offset);
900 return_val = STATUS_OK;
901 }
902 break;
903
904 default:
905 return_val = STATUS_UNSUPPORTED;
906 break;
907 }
908
909 return return_val;
910
911}
912
913extern void dcl_pmic6325_modem_only_init(void);
914extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
915extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
916extern kal_uint32 PMIC_Config_Interface(kal_bool action, kal_uint32 address, kal_uint32 wdata, kal_uint32 *rdata, kal_uint32 chip_name);
917extern void PMIC_Read_All(void);
918#if defined(PMIC_UNIT_TEST)
919extern void PMIC_Read_All(void);
920extern void PMIC_Unit_Test(void);
921#endif
922
923
924void dcl_pmic6325_internal_init(void)
925{
926}
927
928#if defined(__DHL_MODULE__)
929extern kal_bool dhl_register_custom_mem_read(DHL_CUSTOM_MEM_TYPE mem_type, DHL_CUSTOM_READ_MEM_CALLBACK read_cb);
930extern kal_bool dhl_register_custom_mem_write(DHL_CUSTOM_MEM_TYPE mem_type, DHL_CUSTOM_WRITE_MEM_CALLBACK write_cb);
931extern void PMIC_Read_Callback_For_DHL(void* read_addr, kal_uint32 len, kal_uint32 option, void** read_buffer_addr, kal_uint32 *read_buffer_len);
932extern void PMIC_Write_Callback_For_DHL(void* write_addr, kal_uint32 len, kal_uint32 option, void* write_buffer_addr);
933#endif
934
935void dcl_pmic6325_init(void){
936 extern void pmic_wrap_dump_init(void);
937 pmu_control_handler = PMIC6325_control_handler;
938 pmu_parameter_size = GETARRNUM(pmu_parameter_table);
939#if defined(__DHL_MODULE__)
940 dhl_register_custom_mem_read(DHL_CUSTOM_MEM_PMIC, PMIC_Read_Callback_For_DHL);
941 dhl_register_custom_mem_write(DHL_CUSTOM_MEM_PMIC, PMIC_Write_Callback_For_DHL);
942#endif
943 pmic_wrap_dump_init();
944
945#if !defined(__SMART_PHONE_MODEM__)
946 DrvPWRAP_Init();
947#endif
948 pmic6325_hw_version = PMIC_ECO_E1;
949 pmic6325_sw_version = PMIC_ECO_E1;
950
951 // Get MT6325 ECO version
952 {
953 kal_uint16 pmic6325_hw_eco_version = 0;
954 kal_uint16 pmic6325_sw_eco_version = 0;
955 pmic6325_hw_eco_version = dcl_pmic6325_byte_return(MT6325_HWCID);
956 pmic6325_sw_eco_version = dcl_pmic6325_byte_return(MT6325_SWCID);
957
958 if (pmic6325_hw_eco_version == MT6325_HW_CID_E1)
959 {
960 pmic6325_hw_version = PMIC_ECO_E1;
961 }
962 else
963 {
964 pmic6325_hw_version = PMIC_ECO_E2;
965 }
966
967 if (pmic6325_sw_eco_version == MT6325_SW_CID_E1)
968 {
969 pmic6325_sw_version = PMIC_ECO_E1;
970 }
971 else
972 {
973 pmic6325_sw_version = PMIC_ECO_E2;
974 }
975 }
976
977 PMIC_Read_All();
978
979#if !defined(__SMART_PHONE_MODEM__)
980 dcl_pmic6325_modem_only_init();
981#endif
982 dcl_pmic6325_internal_init();
983
984 // pmic6325_customization_init();
985#if defined(PMIC_UNIT_TEST)
986 PMIC_Read_All();
987 PMIC_Unit_Test();
988 PMIC_Read_All();
989#endif
990 pmic_init_done = DCL_TRUE;
991
992}
993
994#if defined(__DHL_MODULE__)
995kal_uint32 pmic_read_data;
996void PMIC_Read_Callback_For_DHL(void* read_addr, kal_uint32 len, kal_uint32 option, void** read_buffer_addr, kal_uint32 *read_buffer_len)
997{
998 kal_uint32 write_buffer_addr = 0;
999 kal_uint32 read_data_addr = (kal_uint32)read_addr;
1000 // Write Workaround
1001 if(read_data_addr & 0x00000001)
1002 {
1003 write_buffer_addr = (read_data_addr & 0xFFFF0000) >> 16;
1004 read_data_addr = (read_data_addr & 0x0000FFFE);
1005 PMIC_Config_Interface(PMIC_WRITE, read_data_addr, (kal_uint32)write_buffer_addr, NULL, option);
1006 }
1007 PMIC_Config_Interface(PMIC_READ, read_data_addr, 0, &pmic_read_data, option);
1008 *read_buffer_addr = (kal_uint32*)&pmic_read_data;
1009 *read_buffer_len = 4;
1010}
1011
1012void PMIC_Write_Callback_For_DHL(void* write_addr, kal_uint32 len, kal_uint32 option, void* write_buffer_addr)
1013{
1014 PMIC_Config_Interface(PMIC_WRITE, (kal_uint32)write_addr, (kal_uint32)write_buffer_addr, NULL, option);
1015}
1016#endif // End of #if defined(__DHL_MODULE__)
1017kal_uint32 PMIC_Config_Interface(kal_bool action, kal_uint32 address, kal_uint32 wdata, kal_uint32 *rdata, kal_uint32 chip_name)
1018{
1019 // Check argument validation
1020 if((action & ~(0x1)) != 0) return 0; // Write should be 1 bit
1021 if((address & ~(0xffff)) != 0) return 0; // Address should no larger than 0xFFFF
1022 if((wdata & ~(0xffff)) != 0) return 0; // Write DATA should be no larger than 0xFFFF
1023
1024 if(action == PMIC_READ)
1025 {
1026 if(chip_name == PMIC_6325)
1027 {
1028 *rdata = (kal_uint32)DRV_Read_PMIC_Data(address);
1029 }
1030 else
1031 {
1032 ASSERT(0);
1033 }
1034 }
1035 else if(action == PMIC_WRITE)
1036 {
1037 if(chip_name == PMIC_6325)
1038 {
1039 DRV_Write_PMIC_Data(address, wdata);
1040 }
1041 else
1042 {
1043 ASSERT(0);
1044 }
1045 }
1046 return 1;
1047}
1048
1049DCL_BOOL dcl_pmic_init_done_query(void)
1050{
1051 if(pmic_init_done == DCL_TRUE)
1052 {
1053 return DCL_TRUE;
1054 }
1055 else
1056 {
1057 return DCL_FALSE;
1058 }
1059}
1060
1061DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
1062{
1063 return dcl_pmic6325_byte_return(pmic_addr);
1064}
1065
1066void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
1067{
1068 dcl_pmic6325_byte_write(pmic_addr, value);
1069}
1070
1071void PMIC_Read_All(void)
1072{
1073 volatile kal_uint32 i;
1074 for (i = 0; i < PMIC6325_MAX_REG_NUM; i += 2){
1075 pmic6325_reg[i] = dcl_pmic6325_byte_return(i);
1076 }
1077}
1078
1079#if defined(PMIC_UNIT_TEST)
1080void PMIC_Unit_Test(void)
1081{
1082{
1083DCL_HANDLE handle;
1084PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
1085handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1086val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
1087val.mod = VMIPI;
1088DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
1089DclPMU_Close(handle);
1090}
1091{
1092DCL_HANDLE handle;
1093PMU_CTRL_LDO_BUCK_SET_EN val;
1094handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1095val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1096val.mod = VMIPI;
1097DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1098DclPMU_Close(handle);
1099}
1100{
1101DCL_HANDLE handle;
1102PMU_CTRL_LDO_BUCK_SET_EN val;
1103handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1104val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1105val.mod = VPA_SW;
1106DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1107DclPMU_Close(handle);
1108}
1109{
1110DCL_HANDLE handle;
1111PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
1112handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1113val.mod=VPA_SW;
1114val.voltage = PMU_VOLT_01_800000_V;
1115/* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
1116 PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
1117 PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
1118 PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
1119 PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
1120 PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
1121 PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
1122 PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
1123 PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
1124 PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
1125 PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
1126 PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
1127 PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
1128 PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
1129 PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
1130 PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
1131DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
1132DclPMU_Close(handle);
1133}
1134{
1135DCL_HANDLE handle;
1136PMU_CTRL_LDO_BUCK_SET_MODESET val;
1137handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1138val.mod = VPA_SW;
1139val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
1140DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
1141DclPMU_Close(handle);
1142}
1143{
1144DCL_HANDLE handle;
1145PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
1146handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1147val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
1148val.mod = VRF1;
1149DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
1150DclPMU_Close(handle);
1151}
1152{
1153DCL_HANDLE handle;
1154PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
1155handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1156val.sel = SRCLKEN_IN1_SEL;
1157/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
1158 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
1159val.mod = VRF1;
1160DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
1161DclPMU_Close(handle);
1162}
1163{
1164DCL_HANDLE handle;
1165PMU_CTRL_LDO_BUCK_SET_MODESET val;
1166handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1167val.mod = VRF1;
1168val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
1169DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
1170DclPMU_Close(handle);
1171}
1172{
1173DCL_HANDLE handle;
1174PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
1175handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1176val.regval = 0x7; // (0x0~0xF)
1177DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
1178DclPMU_Close(handle);
1179}
1180{
1181DCL_HANDLE handle;
1182PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
1183handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1184val.regval = 0x7; // (0x0~0xF)
1185DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
1186DclPMU_Close(handle);
1187}
1188{
1189DCL_HANDLE handle;
1190PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
1191handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1192// val.regval will be your request value ( no need do any shift)
1193DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
1194DclPMU_Close(handle);
1195}
1196{
1197DCL_HANDLE handle;
1198PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
1199handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1200val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
1201val.mod = VRF2;
1202DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
1203DclPMU_Close(handle);
1204}
1205{
1206DCL_HANDLE handle;
1207PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
1208handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1209val.sel = SRCLKEN_IN1_SEL;
1210/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
1211 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
1212val.mod = VRF2;
1213DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
1214DclPMU_Close(handle);
1215}
1216{
1217DCL_HANDLE handle;
1218PMU_CTRL_LDO_BUCK_SET_EN val;
1219handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1220val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1221val.mod = VRF2;
1222DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1223DclPMU_Close(handle);
1224}
1225{
1226DCL_HANDLE handle;
1227PMU_CTRL_LDO_BUCK_SET_MODESET val;
1228handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1229val.mod = VRF1;
1230val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
1231DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
1232DclPMU_Close(handle);
1233}
1234{
1235DCL_HANDLE handle;
1236PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
1237handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1238val.sel = SRCLKEN_IN1_SEL;
1239/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
1240 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
1241val.mod = VMIPI;
1242DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
1243DclPMU_Close(handle);
1244}
1245{
1246DCL_HANDLE handle;
1247PMU_CTRL_LDO_BUCK_SET_EN val;
1248handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1249val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1250val.mod = VSIM1;
1251DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1252DclPMU_Close(handle);
1253}
1254{
1255DCL_HANDLE handle;
1256PMU_CTRL_LDO_BUCK_SET_EN val;
1257handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1258val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1259val.mod = VSIM2;
1260DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1261DclPMU_Close(handle);
1262}
1263{
1264DCL_HANDLE handle;
1265PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
1266handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1267val.mod=VSIM1;
1268val.voltage = PMU_VOLT_01_800000_V;
1269/* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
1270DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
1271DclPMU_Close(handle);
1272}
1273{
1274DCL_HANDLE handle;
1275PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
1276handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1277val.mod=VSIM2;
1278val.voltage = PMU_VOLT_01_800000_V;
1279/* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
1280DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
1281DclPMU_Close(handle);
1282}
1283}
1284#endif // End of #if defined(PMIC_UNIT_TEST)
1285
1286#endif // End of #if defined(PMIC_6325_REG_API)
1287