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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / devdrv / pmic / src / dcl_pmic6339.c
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2011
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * dcl_pmic6339.c
41 *
42 * Project:
43 * --------
44 * MOLY
45 *
46 * Description:
47 * ------------
48 * This is pmic6339 driver
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 ****************************************************************************/
56
57#include "reg_base.h"
58#include "intrCtrl.h"
59#include "dcl.h"
60#include "dcl_pmu_sw.h"
61#include "kal_public_api.h"
62#include "drv_bsi.h"
63#include "i2c_pmic.h"
64
65#define PMIC_MAX_REG_NUM PMIC_REG_NUM
66
67#ifdef PMIC_6339_DEBUG
68static kal_uint16 pmic6339_reg[PMIC_MAX_REG_NUM];
69#endif
70
71static const DCL_UINT32 vio28_vosel[] =
72{
73 PMU_VOLT_01_200000_V, PMU_VOLT_01_300000_V, PMU_VOLT_01_500000_V, PMU_VOLT_01_800000_V,
74 PMU_VOLT_02_500000_V, PMU_VOLT_02_800000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_300000_V,
75};
76
77static const DCL_UINT32 vcore_vosel[]=
78{
79 PMU_VOLT_00_700000_V, PMU_VOLT_00_725000_V, PMU_VOLT_00_775000_V, PMU_VOLT_00_750000_V,
80 PMU_VOLT_00_875000_V, PMU_VOLT_00_850000_V, PMU_VOLT_00_800000_V, PMU_VOLT_00_825000_V,
81 PMU_VOLT_01_075000_V, PMU_VOLT_01_050000_V, PMU_VOLT_01_000000_V, PMU_VOLT_01_025000_V,
82 PMU_VOLT_00_900000_V, PMU_VOLT_00_925000_V, PMU_VOLT_00_975000_V, PMU_VOLT_00_950000_V,
83 PMU_VOLT_01_475000_V, PMU_VOLT_01_450000_V, PMU_VOLT_01_400000_V, PMU_VOLT_01_425000_V,
84 PMU_VOLT_01_300000_V, PMU_VOLT_01_325000_V, PMU_VOLT_01_375000_V, PMU_VOLT_01_350000_V,
85 PMU_VOLT_01_100000_V, PMU_VOLT_01_125000_V, PMU_VOLT_01_175000_V, PMU_VOLT_01_150000_V,
86 PMU_VOLT_01_275000_V, PMU_VOLT_01_250000_V, PMU_VOLT_01_200000_V, PMU_VOLT_01_225000_V,
87};
88
89static const DCL_UINT32 vsim_vosel[] =
90{
91 PMU_VOLT_01_200000_V, PMU_VOLT_01_300000_V, PMU_VOLT_01_500000_V, PMU_VOLT_01_800000_V,
92 PMU_VOLT_02_500000_V, PMU_VOLT_02_800000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_300000_V,
93};
94
95static const DCL_UINT32 vmc_io_vosel[] =
96{
97 PMU_VOLT_01_200000_V, PMU_VOLT_01_300000_V, PMU_VOLT_01_500000_V, PMU_VOLT_01_800000_V,
98 PMU_VOLT_02_000000_V, PMU_VOLT_02_800000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_300000_V,
99};
100
101static const DCL_UINT32 vmch_vosel[] =
102{
103 PMU_VOLT_01_200000_V, PMU_VOLT_01_300000_V, PMU_VOLT_01_500000_V, PMU_VOLT_01_800000_V,
104 PMU_VOLT_02_500000_V, PMU_VOLT_02_800000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_300000_V,
105};
106
107static const DCL_UINT32 vpa_vosel[] =
108{
109 PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
110 PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
111 PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
112 PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
113 PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
114 PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
115 PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
116 PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
117 PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
118 PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
119 PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
120 PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
121 PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
122 PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
123 PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
124 PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
125
126};
127
128PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
129{
130 {ENC(LDO_BUCK_SET_VOLTAGE, VIO28), vio28_vosel, NULL, GETARRNUM(vio28_vosel)},
131 {ENC(LDO_BUCK_SET_VOLTAGE, VCORE), vcore_vosel, NULL, GETARRNUM(vcore_vosel)},
132 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM), vsim_vosel, NULL, GETARRNUM(vsim_vosel)},
133 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim_vosel, NULL, GETARRNUM(vsim_vosel)},
134 {ENC(LDO_BUCK_SET_VOLTAGE, VMC), vmc_io_vosel, NULL, GETARRNUM(vmc_io_vosel) },
135 {ENC(LDO_BUCK_SET_VOLTAGE, VMCH), vmch_vosel, NULL, GETARRNUM(vmch_vosel) },
136 {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
137 {ENC(VPA_SET_VOLTAGE_SELECTION_TABLE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
138};
139DCL_UINT16 pmu_parameter_size=0;
140DCL_UINT16 pmic_CID0 = 0xFFFF;
141DCL_UINT16 pmic_ECO_VERSION = 0xFFFF;
142
143
144const PMU_FLAG_TABLE_ENTRY pmic_flags_table[] =
145{
146 {CID0, CID0_ADDR, CID0_MASK, CID0_SHIFT},
147 {ECO_VERSION, ECO_VERSION_ADDR, ECO_VERSION_MASK, ECO_VERSION_SHIFT},
148 {RG_VIO28_VOSEL, RG_VIO28_VOSEL_ADDR, RG_VIO28_VOSEL_MASK, RG_VIO28_VOSEL_SHIFT},
149 {RG_VIO28_EN, RG_VIO28_EN_ADDR, RG_VIO28_EN_MASK, RG_VIO28_EN_SHIFT},
150 {RG_VUSB11_EN, RG_VUSB11_EN_ADDR, RG_VUSB11_EN_MASK, RG_VUSB11_EN_SHIFT},
151 {RG_VCORE_VOSEL, RG_VCORE_VOSEL_ADDR, RG_VCORE_VOSEL_MASK, RG_VCORE_VOSEL_SHIFT},
152 {RG_VRF18_MODESET, RG_VRF18_MODESET_ADDR, RG_VRF18_MODESET_MASK, RG_VRF18_MODESET_SHIFT},
153 {RG_VRF18_ON_CTRL, RG_VRF18_ON_CTRL_ADDR, RG_VRF18_ON_CTRL_MASK, RG_VRF18_ON_CTRL_SHIFT},
154 {RG_VRF18_EN, RG_VRF18_EN_ADDR, RG_VRF18_EN_MASK, RG_VRF18_EN_SHIFT},
155 {VRF18_srclken_sel, VRF18_srclken_sel_ADDR, VRF18_srclken_sel_MASK, VRF18_srclken_sel_SHIFT},
156 {RG_VRF18_2_MODESET, RG_VRF18_2_MODESET_ADDR, RG_VRF18_2_MODESET_MASK, RG_VRF18_2_MODESET_SHIFT},
157 {RG_VRF18_2_ON_CTRL, RG_VRF18_2_ON_CTRL_ADDR, RG_VRF18_2_ON_CTRL_MASK, RG_VRF18_2_ON_CTRL_SHIFT},
158 {RG_VRF18_2_EN, RG_VRF18_2_EN_ADDR, RG_VRF18_2_EN_MASK, RG_VRF18_2_EN_SHIFT},
159 {VRF18_2_srclken_sel, VRF18_2_srclken_sel_ADDR, VRF18_2_srclken_sel_MASK, VRF18_2_srclken_sel_SHIFT},
160 {RG_VPA_MODESET, RG_VPA_MODESET_ADDR, RG_VPA_MODESET_MASK, RG_VPA_MODESET_SHIFT},
161 {VPA_VOSEL_MAP_EN, VPA_VOSEL_MAP_EN_ADDR, VPA_VOSEL_MAP_EN_MASK, VPA_VOSEL_MAP_EN_SHIFT},
162 {RG_VPA_EN, RG_VPA_EN_ADDR, RG_VPA_EN_MASK, RG_VPA_EN_SHIFT},
163 {VPA_VOSEL, VPA_VOSEL_ADDR, VPA_VOSEL_MASK, VPA_VOSEL_SHIFT},
164 {RG_VRF18_BK_LDO, RG_VRF18_BK_LDO_ADDR, RG_VRF18_BK_LDO_MASK, RG_VRF18_BK_LDO_SHIFT},
165 {RG_VRF18_2_BK_LDO, RG_VRF18_2_BK_LDO_ADDR, RG_VRF18_2_BK_LDO_MASK, RG_VRF18_2_BK_LDO_SHIFT},
166 {RG_VSIM1_EN, RG_VSIM1_EN_ADDR, RG_VSIM1_EN_MASK, RG_VSIM1_EN_SHIFT},
167 {RG_VSIM2_EN, RG_VSIM2_EN_ADDR, RG_VSIM2_EN_MASK, RG_VSIM2_EN_SHIFT},
168 {RG_VSIM1_VOSEL, RG_VSIM1_VOSEL_ADDR, RG_VSIM1_VOSEL_MASK, RG_VSIM1_VOSEL_SHIFT},
169 {RG_VSIM2_VOSEL, RG_VSIM2_VOSEL_ADDR, RG_VSIM2_VOSEL_MASK, RG_VSIM2_VOSEL_SHIFT},
170 {RG_VMC_VOSEL, RG_VMC_VOSEL_ADDR, RG_VMC_VOSEL_MASK, RG_VMC_VOSEL_SHIFT},
171 {RG_VMC_EN, RG_VMC_EN_ADDR, RG_VMC_EN_MASK, RG_VMC_EN_SHIFT},
172 {RG_VMCH_VOSEL, RG_VMCH_VOSEL_ADDR, RG_VMCH_VOSEL_MASK, RG_VMCH_VOSEL_SHIFT},
173 {RG_VMCH_EN, RG_VMCH_EN_ADDR, RG_VMCH_EN_MASK, RG_VMCH_EN_SHIFT},
174 {RG_VMIPI_EN, RG_VMIPI_EN_ADDR, RG_VMIPI_EN_MASK, RG_VMIPI_EN_SHIFT},
175 {VPA_TABLE0, VPA_TABLE0_ADDR, VPA_TABLE0_MASK, VPA_TABLE0_SHIFT},
176 {VPA_TABLE1, VPA_TABLE1_ADDR, VPA_TABLE1_MASK, VPA_TABLE1_SHIFT},
177 {VPA_TABLE2, VPA_TABLE2_ADDR, VPA_TABLE2_MASK, VPA_TABLE2_SHIFT},
178 {VPA_TABLE3, VPA_TABLE3_ADDR, VPA_TABLE3_MASK, VPA_TABLE3_SHIFT},
179 {VPA_TABLE4, VPA_TABLE4_ADDR, VPA_TABLE4_MASK, VPA_TABLE4_SHIFT},
180 {VPA_TABLE5, VPA_TABLE5_ADDR, VPA_TABLE5_MASK, VPA_TABLE5_SHIFT},
181 {VPA_TABLE6, VPA_TABLE6_ADDR, VPA_TABLE6_MASK, VPA_TABLE6_SHIFT},
182 {VPA_TABLE7, VPA_TABLE7_ADDR, VPA_TABLE7_MASK, VPA_TABLE7_SHIFT},
183 {VPA_MAP_SEL, VPA_MAP_SEL_ADDR, VPA_MAP_SEL_MASK, VPA_MAP_SEL_SHIFT},
184};
185
186//////////////////////////////////////////////////
187// WRITE APIs //
188//////////////////////////////////////////////////
189// Write Whole Bytes
190static void dcl_pmic6339_write_reg(DCL_UINT8 addr, DCL_UINT16 val)
191{
192 drv_bsi_pmic6339_reg_write(addr,val);
193 #ifdef PMIC_6339_DEBUG
194 pmic6339_reg[addr]=val;
195 #endif
196}
197
198//////////////////////////////////////////////////
199// READ APIs //
200//////////////////////////////////////////////////
201
202// Read Whole Bytes
203static DCL_UINT16 dcl_pmic6339_read_reg(DCL_UINT8 addr)
204{
205 kal_uint16 val;
206 val=drv_bsi_pmic6339_reg_read(addr);
207 #ifdef PMIC_6339_DEBUG
208 pmic6339_reg[addr]=val;
209 #endif
210 return val;
211}
212
213// Write register field
214static void dcl_pmic6339_field_write(PMU_FLAGS_LIST_ENUM flag, kal_uint16 sel)
215{
216 kal_uint32 i, table_size = 0,mask;
217 kal_uint16 val;
218
219 table_size = GETARRNUM(pmic_flags_table);
220 for (i = 0; i < table_size; i++)
221 {
222 if (flag == pmic_flags_table[i].flagname)
223 {
224 break;
225 }
226 }
227 if (i >= table_size){ ASSERT(0); }// Flag Unknown
228
229 mask=SaveAndSetIRQMask();
230 val=dcl_pmic6339_read_reg(pmic_flags_table[i].offset)&(~(pmic_flags_table[i].mask));
231 val|=(sel<<pmic_flags_table[i].shift)&pmic_flags_table[i].mask;
232 dcl_pmic6339_write_reg(pmic_flags_table[i].offset,val);
233 RestoreIRQMask(mask);
234 return;
235}
236DCL_STATUS PMIC6339_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
237{
238 DCL_UINT16 regVal;
239 DCL_INT32 return_val = STATUS_FAIL;
240 switch(cmd)
241 {
242 case LDO_BUCK_SET_EN:
243 {
244 PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
245
246 switch(pLdoBuckCtrl->mod)
247 {
248 case VRF18:
249 {
250 dcl_pmic6339_field_write(RG_VRF18_EN, pLdoBuckCtrl->enable);
251 return_val = STATUS_OK;
252 }
253 break;
254 case VRF18_2:
255 {
256 dcl_pmic6339_field_write(RG_VRF18_2_EN, pLdoBuckCtrl->enable);
257 return_val = STATUS_OK;
258 }
259 break;
260 case VSIM:
261 {
262 dcl_pmic6339_field_write(RG_VSIM1_EN, pLdoBuckCtrl->enable);
263 return_val = STATUS_OK;
264 }
265 break;
266 case VSIM2:
267 {
268 dcl_pmic6339_field_write(RG_VSIM2_EN, pLdoBuckCtrl->enable);
269 return_val = STATUS_OK;
270 }
271 break;
272 case VMC:
273 {
274 dcl_pmic6339_field_write(RG_VMC_EN, pLdoBuckCtrl->enable);
275 return_val = STATUS_OK;
276 }
277 break;
278 case VMCH:
279 {
280 dcl_pmic6339_field_write(RG_VMCH_EN, pLdoBuckCtrl->enable);
281 return_val = STATUS_OK;
282 }
283 break;
284 case VMIPI:
285 {
286 dcl_pmic6339_field_write(RG_VMIPI_EN, pLdoBuckCtrl->enable);
287 return_val = STATUS_OK;
288 }
289 break;
290 default:
291 return_val = STATUS_UNSUPPORTED;
292 break;
293 }
294 }
295 break;
296 case LDO_BUCK_SET_VOLTAGE:
297 {
298 PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
299 regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
300 switch(pLdoBuckCtrl->mod)
301 {
302 case VIO28:
303 {
304 dcl_pmic6339_field_write(RG_VIO28_VOSEL, regVal);
305 return_val = STATUS_OK;
306 }
307 break;
308 case VCORE:
309 {
310 dcl_pmic6339_field_write(RG_VCORE_VOSEL, regVal);
311 return_val = STATUS_OK;
312 }
313 break;
314 case VSIM:
315 {
316 dcl_pmic6339_field_write(RG_VSIM1_VOSEL, regVal);
317 return_val = STATUS_OK;
318 }
319 break;
320 case VSIM2:
321 {
322 dcl_pmic6339_field_write(RG_VSIM2_VOSEL, regVal);
323 return_val = STATUS_OK;
324 }
325 break;
326 case VMC:
327 {
328 dcl_pmic6339_field_write(RG_VMC_VOSEL, regVal);
329 return_val = STATUS_OK;
330 }
331 break;
332 case VMCH:
333 {
334 dcl_pmic6339_field_write(RG_VMCH_VOSEL, regVal);
335 return_val = STATUS_OK;
336 }
337 break;
338 case VPA:
339 {
340 dcl_pmic6339_field_write(VPA_VOSEL, regVal);
341 return_val = STATUS_OK;
342 }
343 break;
344 default:
345 return_val = STATUS_UNSUPPORTED;
346 break;
347 }
348 }
349 break;
350 case VRF18_SET_BUCK_LDO_MODE:
351 {
352 PMU_CTRL_VRF18_SET_BUCK_LDO_MODE *pVrf18Ctrl = &(data->rPMUVrf18SetBuckLdoMode);
353 switch(pVrf18Ctrl->vrf18Idx)
354 {
355 case PMIC_VRF18_1:
356 {
357 dcl_pmic6339_field_write(RG_VRF18_BK_LDO, pVrf18Ctrl->mode);
358 return_val = STATUS_OK;
359 }
360 break;
361 case PMIC_VRF18_2:
362 {
363 dcl_pmic6339_field_write(RG_VRF18_2_BK_LDO, pVrf18Ctrl->mode);
364 return_val = STATUS_OK;
365 }
366 break;
367 default:
368 return_val = STATUS_UNSUPPORTED;
369 break;
370 }
371 }
372 break;
373 case VRF18_SET_FPWM:
374 {
375 PMU_CTRL_VRF18_SET_FPWM *pVrf18SetFpwm = (PMU_CTRL_VRF18_SET_FPWM *)data;
376 dcl_pmic6339_field_write(RG_VRF18_MODESET, pVrf18SetFpwm->enable);
377 return_val = STATUS_OK;
378 }
379 break;
380 case VRF18_2_SET_FPWM:
381 {
382 PMU_CTRL_VRF18_SET_FPWM *pVrf18SetFpwm = (PMU_CTRL_VRF18_SET_FPWM *)data;
383 dcl_pmic6339_field_write(RG_VRF18_2_MODESET, pVrf18SetFpwm->enable);
384 return_val = STATUS_OK;
385 }
386 break;
387 case VPA_SET_FPWM:
388 {
389 PMU_CTRL_VPA_SET_FPWM *pVpaSetFpwm = (PMU_CTRL_VPA_SET_FPWM *)data;
390 dcl_pmic6339_field_write(RG_VPA_MODESET, pVpaSetFpwm->enable);
391 return_val = STATUS_OK;
392 }
393 break;
394 case LDO_BUCK_SET_ON_SEL:
395 {
396 PMU_CTRL_LDO_BUCK_SET_ON_SEL *pLdoBuckCtrl=&(data->rPMULdoBuckSetOnSel);
397 switch(pLdoBuckCtrl->mod)
398 {
399 case VRF18:
400 {
401 // ENABLE_WITH_SRCLKEN = 0, but 6329 SRCLKEN = 1, therefore we need NOT pLdoBuckCtrl->onsel
402 dcl_pmic6339_field_write(RG_VRF18_ON_CTRL, !(pLdoBuckCtrl->onSel));
403 return_val = STATUS_OK;
404 }
405 break;
406 case VRF18_2:
407 {
408 // ENABLE_WITH_SRCLKEN = 0, but 6329 SRCLKEN = 1, therefore we need NOT pLdoBuckCtrl->onsel
409 dcl_pmic6339_field_write(RG_VRF18_2_ON_CTRL, !(pLdoBuckCtrl->onSel));
410 return_val = STATUS_OK;
411 }
412 break;
413 default:
414 return_val = STATUS_UNSUPPORTED;
415 break;
416 }
417 }
418 break;
419 case LDO_BUCK_SET_SRCLKEN_SEL:
420 {
421 PMU_CTRL_LDO_BUCK_SET_SRCLKEN_SEL *pLdoBuckCtrl=&(data->rPMULdoBuckSetSrclkenSel);
422 switch(pLdoBuckCtrl->mod)
423 {
424 case VRF18:
425 {
426 dcl_pmic6339_field_write(VRF18_srclken_sel, pLdoBuckCtrl->SrclkenSel);
427 return_val = STATUS_OK;
428 }
429 break;
430 case VRF18_2:
431 {
432 dcl_pmic6339_field_write(VRF18_2_srclken_sel, pLdoBuckCtrl->SrclkenSel);
433 return_val = STATUS_OK;
434 }
435 break;
436 default:
437 return_val = STATUS_UNSUPPORTED;
438 break;
439 }
440 }
441 break;
442 case VPA_SET_EN:
443 {
444 PMU_CTRL_VPA_SET_EN *pVpaCtrl = &(data->rPMUVpaSetEn);
445 dcl_pmic6339_field_write(RG_VPA_EN, pVpaCtrl->enable);
446 return_val = STATUS_OK;
447 }
448 break;
449 case VPA_SET_VOSEL_MAP_EN:
450 {
451 PMU_CTRL_VPA_SET_VOSEL_MAP_EN *pVpaCtrl = &(data->rPMUVpaSetVoselMapEn);
452 dcl_pmic6339_field_write(VPA_VOSEL_MAP_EN, pVpaCtrl->enable);
453 return_val = STATUS_OK;
454 }
455 break;
456
457 case VPA_GET_VOLTAGE_LIST:
458 {
459 PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
460 pVpaCtrl->pVoltageList = vpa_vosel;
461 pVpaCtrl->number = GETARRNUM(vpa_vosel);
462 return_val = STATUS_OK;
463 }
464 break;
465 case VPA_SET_VOLTAGE_SELECTION_TABLE:
466 {
467 PMU_CTRL_VPA_SET_VOLTAGE_SELECTION_TABLE *pVpaCtrl = &(data->rPMUVpaSetVoltageSelectionTable);
468 regVal = PMU_Parameter_to_Value(ENC(VPA_SET_VOLTAGE_SELECTION_TABLE, VPA), pVpaCtrl->voltage);
469 switch(pVpaCtrl->table_entry)
470 {
471 case PMU_VPA0:
472 {
473 dcl_pmic6339_field_write(VPA_TABLE0, regVal);
474 return_val = STATUS_OK;
475 }
476 break;
477 case PMU_VPA1:
478 {
479 dcl_pmic6339_field_write(VPA_TABLE1, regVal);
480 return_val = STATUS_OK;
481 }
482 break;
483 case PMU_VPA2:
484 {
485 dcl_pmic6339_field_write(VPA_TABLE2, regVal);
486 return_val = STATUS_OK;
487 }
488 break;
489
490 case PMU_VPA3:
491 {
492 dcl_pmic6339_field_write(VPA_TABLE3, regVal);
493 return_val = STATUS_OK;
494 }
495
496 break;
497 case PMU_VPA4:
498 {
499 dcl_pmic6339_field_write(VPA_TABLE4, regVal);
500 return_val = STATUS_OK;
501 }
502 break;
503 case PMU_VPA5:
504 {
505 dcl_pmic6339_field_write(VPA_TABLE5, regVal);
506 return_val = STATUS_OK;
507 }
508 break;
509 case PMU_VPA6:
510 {
511 dcl_pmic6339_field_write(VPA_TABLE6, regVal);
512 return_val = STATUS_OK;
513 }
514 break;
515 case PMU_VPA7:
516 {
517 dcl_pmic6339_field_write(VPA_TABLE7, regVal);
518 return_val = STATUS_OK;
519 }
520 break;
521
522 default:
523 return_val = STATUS_UNSUPPORTED;
524 break;
525 }
526
527 }
528 break;
529
530 case VPA_SET_MAP_SEL:
531 {
532 PMU_CTRL_VPA_SET_MAP_SEL *pVpaCtrl = &(data->rPMUVpaSetMapSel);
533 dcl_pmic6339_field_write(VPA_MAP_SEL, pVpaCtrl->table_entry);
534 }
535 break;
536
537
538/* case VPA_SET_VOLTAGE: // VPA voltage will be auto set by HW, this command is not necessary for HW driver
539 {
540 PMU_CTRL_VPA_SET_VOLTAGE *pVpaCtrl = &(data->rPMUVpaSetVoltage);
541
542 regVal = PMU_Parameter_to_Value(ENC(cmd,0), pVpaCtrl->voltage);
543 dcl_pmic6339_field_write(VPA_VOSEL, regVal);
544 }
545 break;*/
546 case MISC_GET_CID:
547 {
548 PMU_CTRL_MISC_GET_CID *pMiscCtrl = &(data->rPMUMiscGetCid);
549 pMiscCtrl->cid_value = pmic_CID0;
550 return_val = STATUS_OK;
551 }
552 break;
553
554 case MISC_GET_ECO_VERSION:
555 {
556 PMU_CTRL_MISC_GET_ECO_VERSION *pMiscCtrl = &(data->rPMUMiscGetEcoVersion);
557 pMiscCtrl->eco_version = pmic_ECO_VERSION;
558 return_val = STATUS_OK;
559 }
560 break;
561
562 case MISC_SET_REGISTER_VALUE:
563 {
564 PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
565 dcl_pmic6339_write_reg(pChrCtrl->offset, pChrCtrl->value);
566 return_val = STATUS_OK;
567 }
568 break;
569
570 case MISC_GET_REGISTER_VALUE:
571 {
572 PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
573 pChrCtrl->value = dcl_pmic6339_read_reg(pChrCtrl->offset);
574 return_val = STATUS_OK;
575 }
576 break;
577 default:
578 return_val = STATUS_UNSUPPORTED;
579 break;
580 }
581 return return_val;
582
583}
584
585// extern void dcl_pmic6339_internal_init(void); // Move to bootloader
586extern void pmu_drv_tool_customization_init(void);
587extern void PMIC_Read_All(void);
588extern void PMIC_VCORE_INIT(kal_uint32 value, kal_uint32 ver);
589
590extern PMU_CONTROL_HANDLER pmu_control_handler;
591//DCL_UINT16 pmu_parameter_size=0;
592
593void dcl_pmic6339_init(void){
594 static kal_uint8 pmic6339_init=0;
595 if(0==pmic6339_init){
596 pmu_control_handler = PMIC6339_control_handler;
597 pmu_parameter_size = GETARRNUM(pmu_parameter_table);
598 pmic6339_init=1;
599 drv_bsi_pmic_init();//init BSI
600 pmic_CID0 = dcl_pmic6339_read_reg(CID0_ADDR);
601 pmic_ECO_VERSION = dcl_pmic6339_read_reg(ECO_VERSION_ADDR);
602 if(pmic_ECO_VERSION == 0x01)
603 {
604 // Turn on VIO28_EN as long as E1.
605 dcl_pmic6339_field_write(RG_VIO28_EN, 0x01);
606 }
607#if defined(PMIC_INIT_PHONE)
608#if !defined(MT6290M_SP_BB) && !defined(MT6290ME2_SP)
609 // Turn off VUSB11 for Custom Phone Project
610 dcl_pmic6339_field_write(RG_VUSB11_EN, 0x00);
611#endif
612#endif
613 // dcl_pmic6339_internal_init(); // Move to bootloader
614// pmic6339_customization_init();
615 pmu_drv_tool_customization_init();
616 #ifdef PMIC_6339_DEBUG
617 {
618 kal_uint32 i;
619 for (i = 0;i < PMIC_MAX_REG_NUM;i++){
620 pmic6339_reg[i] = dcl_pmic6339_read_reg(i);
621 }
622 }
623 #endif
624 }
625}
626
627
628void PMIC_Read_All(void)
629{
630 volatile kal_uint32 i;
631 for (i = 0; i < PMIC_MAX_REG_NUM; i++){
632 pmic6339_reg[i] = dcl_pmic6339_read_reg(i);
633 }
634}
635#if defined(MT6290_DEMO_BB) || defined(MT6290M_DEMO_BB) || defined(MT6290E2_EVB) || defined(MT6290ME2_EVB) // EVB
636void PMIC_VCORE_INIT(kal_uint32 value, kal_uint32 ver)
637{
638 value = 0;
639 ver = 0;
640}
641#else
642extern const char EXTbuck_i2cdev_exist;
643void PMIC_VCORE_INIT(kal_uint32 value, kal_uint32 ver)
644{
645#include "i2c_pmic.h"
646#define NCP6335_SLAVE_ADDR 0x1C
647 kal_uint8 val;
648 I2C_STATUS sts;
649 int gpio15;
650 GPIO_CTRL_READ_T data;
651 DCL_HANDLE handle = DclGPIO_Open(DCL_GPIO, EXTbuck_i2cdev_exist & (~0x80));
652 DclGPIO_Control(handle, GPIO_CMD_READ, (DCL_CTRL_DATA_T *)&data);
653 gpio15 = data.u1IOData;
654
655 if(gpio15 == 1)
656 {
657 DclGPIO_Control(handle,GPIO_CMD_SET_PULL_HIGH, (DCL_CTRL_DATA_T *)&data);
658 }
659 /* read NCP6335 reg 0*/
660 sts = i2c_pmic_reg_read(NCP6335_SLAVE_ADDR , 0x0 , &val);
661 if (sts == I2C_ACKERR)
662 {
663 /*
664 * Error Handing.
665 * ¨Ò¦p ¦pªG¬OACK_ERR , ¥i¥H¦AŪ¤@¦¸double check ¤@¤U ¡A ¦pªGÁÙ¬OACK_ERR , ¥i»{¬° slave ¤£¦s¦b
666 */
667 sts = i2c_pmic_reg_read(NCP6335_SLAVE_ADDR , 0x0 , &val);
668 if(sts == I2C_ACKERR)
669 {
670 if(ver == 1 && gpio15 == 1)
671 {
672 ASSERT(0);
673 }
674 else
675 {
676 // NCP6335 Not Exist
677 switch(value)
678 {
679 case 0:
680 case 1:
681 dcl_pmic6339_write_reg(0x65, 0x09); // 1.05V
682 break;
683 case 2:
684 case 3:
685 dcl_pmic6339_write_reg(0x65, 0x0A); // 1.0V
686 break;
687 default:
688 break;
689 }
690 }
691 }
692 else
693 {
694 ASSERT(0);
695 }
696 }
697 else if(sts == I2C_PASS)
698 {
699 // NCP6335 Exist
700 // 1.05V, Depend on binning IC E-fuse
701 i2c_pmic_reg_write(NCP6335_SLAVE_ADDR, 0x10, 0xC8);
702 // 0.85V, initial setting
703 i2c_pmic_reg_write(NCP6335_SLAVE_ADDR, 0x11, 0xA8);
704 // Common register initial
705 i2c_pmic_reg_write(NCP6335_SLAVE_ADDR, 0x14, 0x01);
706 switch(value)
707 {
708 case 0:
709 case 1:
710 i2c_pmic_reg_write(NCP6335_SLAVE_ADDR, 0x10, 0xC8); // 1.05V
711 dcl_pmic6339_write_reg(0x65, 0x09); // 1.05V
712 //dcl_pmic6339_write_reg(0x63, 0x00); // Shutdown VCORE
713 break;
714 case 2:
715 case 3:
716 i2c_pmic_reg_write(NCP6335_SLAVE_ADDR, 0x10, 0xC0); // 1.00V
717 dcl_pmic6339_write_reg(0x65, 0x0A); // 1.0V
718 //dcl_pmic6339_write_reg(0x63, 0x00); // Shutdown VCORE
719 break;
720 default:
721 break;
722 }
723 }
724 else if(sts == I2C_FAIL)
725 {
726 ASSERT(0);
727 }
728
729}
730#endif // End of #if defined(MT6290_DEMO_BB) || defined(MT6290M_DEMO_BB) || defined(MT6290E2_EVB) || defined(MT6290ME2_EVB) // EVB