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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / devdrv / pmic / src / dcl_pmic6351.c
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2014
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * dcl_pmic6351.c
41 *
42 * Project:
43 * --------
44 * MOLY Software
45 *
46 * Description:
47 * ------------
48 * This file is for PMIC 6351
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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140 *------------------------------------------------------------------------------
141 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
142 *============================================================================
143 ****************************************************************************/
144
145#if defined(FPGA_CTP)
146#include <common.h>
147#endif
148
149#include "reg_base.h"
150#include "drv_comm.h"
151#include "init.h"
152#include "dcl.h"
153#include "dcl_pmu_sw.h"
154#include "pmic_wrap.h"
155#include "kal_public_api.h"
156#include "us_timer.h"
157#include "dhl_trace.h"
158#if defined(PMIC_6351_REG_API)
159
160// Start PMIC_UNIT_TEST
161//#define PMIC_UNIT_TEST
162// ARM Section RW/RO/ZI Use Internal SRAM
163//#define PMIC_INTERNAL_SRAM
164#if !defined(__FUE__)
165#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
166#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
167#else /*defined(__FUE__)*/
168#define SAVEANDSETIRQMASK() 0
169#define RESTOREIRQMASK(mask) {}
170#endif /*defined(__FUE__)*/
171
172#define BANKS_NUM 1
173#define PMIC6351_MAX_REG_NUM 0x0FF0 // 0x0000~0x0F48
174//#define PMIC_MAX_REG_NUM 0x40FF // Register BUCK1, Register ANALDO, Register DIGLDO (0x0470)
175
176#define MT6351_HW_CID_E1 0x5110
177#define MT6351_HW_CID_E2 0x5120
178#define MT6351_HW_CID_E3 0x5130
179#define MT6351_SW_CID_E1 0x5110
180#define MT6351_SW_CID_E2 0x5120
181#define MT6351_SW_CID_E3 0x5130
182
183#define PMIC_READ 0
184#define PMIC_WRITE 1
185
186#define PMIC_6351 0x6351
187
188//////////////////////////////////////////////////
189// Exported APIs //
190//////////////////////////////////////////////////
191extern kal_bool pmic6351_reg_write(kal_uint16 reg, kal_uint16 val);
192extern kal_bool pmic6351_reg_read(kal_uint16 reg, kal_uint16 *pVal);
193
194extern DCL_BOOL dcl_pmic_init_done_query(void);
195typedef enum
196{
197 AUXADC_READ_INIT = 0,
198 AUXADC_READ_REQUEST = 1,
199 AUXADC_READ_READY = 2,
200 AUXADC_READ_BUSY = 3,
201 AUXADC_READ_DATA = 4
202}AUXADC_FSM;
203
204typedef struct
205{
206 kal_uint32 command_flag;
207 kal_uint32 reg_before_write;
208 kal_uint32 write_value;
209 kal_uint32 address_offset;
210 kal_uint32 reg_mask;
211 kal_uint32 reg_shift;
212 kal_uint32 reg_addr;
213 kal_uint32 reg_data;
214}PMIC_REG_LOG;
215
216AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
217PMIC_REG_LOG pmic_reg_log;
218
219//#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
220//__attribute__ ((zero_init))
221//#endif /* __MTK_TARGET__ */
222kal_uint8 pmic6351_hw_version;
223kal_uint8 pmic6351_sw_version;
224kal_uint16 pmic6351_reg[PMIC6351_MAX_REG_NUM];
225DCL_BOOL pmic_init_done = DCL_FALSE;
226
227const PMIC_FLAG_TABLE_ENTRY pmic6351_flags_table[] =
228{
229 {MT6351_HWCID, MT6351_HWCID_MASK, MT6351_HWCID_SHIFT, },
230 {MT6351_SWCID, MT6351_SWCID_MASK, MT6351_SWCID_SHIFT, },
231 {MT6351_VPA_ANA_CON0, MT6351_RG_VPA_MODESET_MASK, MT6351_RG_VPA_MODESET_SHIFT, },
232 {MT6351_BUCK_VMODEM_CON0, MT6351_BUCK_VMODEM_EN_CTRL_MASK, MT6351_BUCK_VMODEM_EN_CTRL_SHIFT, },
233 {MT6351_BUCK_VMODEM_CON0, MT6351_BUCK_VMODEM_VOSEL_CTRL_MASK, MT6351_BUCK_VMODEM_VOSEL_CTRL_SHIFT, },
234 {MT6351_BUCK_VMODEM_CON2, MT6351_BUCK_VMODEM_EN_MASK, MT6351_BUCK_VMODEM_EN_SHIFT, },
235 {MT6351_BUCK_VMODEM_CON2, MT6351_DA_QI_VMODEM_EN_MASK, MT6351_DA_QI_VMODEM_EN_SHIFT, },
236 {MT6351_BUCK_VMODEM_CON4, MT6351_BUCK_VMODEM_VOSEL_MASK, MT6351_BUCK_VMODEM_VOSEL_SHIFT, },
237 {MT6351_BUCK_VMODEM_CON5, MT6351_BUCK_VMODEM_VOSEL_ON_MASK, MT6351_BUCK_VMODEM_VOSEL_ON_SHIFT, },
238 {MT6351_BUCK_VMODEM_CON6, MT6351_BUCK_VMODEM_VOSEL_SLEEP_MASK, MT6351_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
239 {MT6351_BUCK_VMODEM_CON8, MT6351_DA_NI_VMODEM_VOSEL_SYNC_MASK, MT6351_DA_NI_VMODEM_VOSEL_SYNC_SHIFT, },
240 {MT6351_BUCK_VMD1_CON0, MT6351_BUCK_VMD1_EN_CTRL_MASK, MT6351_BUCK_VMD1_EN_CTRL_SHIFT, },
241 {MT6351_BUCK_VMD1_CON0, MT6351_BUCK_VMD1_VOSEL_CTRL_MASK, MT6351_BUCK_VMD1_VOSEL_CTRL_SHIFT, },
242 {MT6351_BUCK_VMD1_CON2, MT6351_BUCK_VMD1_EN_MASK, MT6351_BUCK_VMD1_EN_SHIFT, },
243 {MT6351_BUCK_VMD1_CON2, MT6351_DA_QI_VMD1_EN_MASK, MT6351_DA_QI_VMD1_EN_SHIFT, },
244 {MT6351_BUCK_VMD1_CON4, MT6351_BUCK_VMD1_VOSEL_MASK, MT6351_BUCK_VMD1_VOSEL_SHIFT, },
245 {MT6351_BUCK_VMD1_CON5, MT6351_BUCK_VMD1_VOSEL_ON_MASK, MT6351_BUCK_VMD1_VOSEL_ON_SHIFT, },
246 {MT6351_BUCK_VMD1_CON6, MT6351_BUCK_VMD1_VOSEL_SLEEP_MASK, MT6351_BUCK_VMD1_VOSEL_SLEEP_SHIFT, },
247 {MT6351_BUCK_VMD1_CON8, MT6351_DA_NI_VMD1_VOSEL_SYNC_MASK, MT6351_DA_NI_VMD1_VOSEL_SYNC_SHIFT, },
248 {MT6351_BUCK_VSRAM_MD_CON0, MT6351_BUCK_VSRAM_MD_EN_CTRL_MASK, MT6351_BUCK_VSRAM_MD_EN_CTRL_SHIFT, },
249 {MT6351_BUCK_VSRAM_MD_CON0, MT6351_BUCK_VSRAM_MD_VOSEL_CTRL_MASK, MT6351_BUCK_VSRAM_MD_VOSEL_CTRL_SHIFT, },
250 {MT6351_BUCK_VSRAM_MD_CON2, MT6351_BUCK_VSRAM_MD_EN_MASK, MT6351_BUCK_VSRAM_MD_EN_SHIFT, },
251 {MT6351_BUCK_VSRAM_MD_CON2, MT6351_DA_QI_VSRAM_MD_EN_MASK, MT6351_DA_QI_VSRAM_MD_EN_SHIFT, },
252 {MT6351_BUCK_VSRAM_MD_CON4, MT6351_BUCK_VSRAM_MD_VOSEL_MASK, MT6351_BUCK_VSRAM_MD_VOSEL_SHIFT, },
253 {MT6351_BUCK_VSRAM_MD_CON5, MT6351_BUCK_VSRAM_MD_VOSEL_ON_MASK, MT6351_BUCK_VSRAM_MD_VOSEL_ON_SHIFT, },
254 {MT6351_BUCK_VSRAM_MD_CON6, MT6351_BUCK_VSRAM_MD_VOSEL_SLEEP_MASK, MT6351_BUCK_VSRAM_MD_VOSEL_SLEEP_SHIFT, },
255 {MT6351_BUCK_VSRAM_MD_CON8, MT6351_DA_NI_VSRAM_MD_VOSEL_SYNC_MASK, MT6351_DA_NI_VSRAM_MD_VOSEL_SYNC_SHIFT, },
256 {MT6351_BUCK_VPA_CON0, MT6351_BUCK_VPA_EN_CTRL_MASK, MT6351_BUCK_VPA_EN_CTRL_SHIFT, },
257 {MT6351_BUCK_VPA_CON0, MT6351_BUCK_VPA_VOSEL_CTRL_MASK, MT6351_BUCK_VPA_VOSEL_CTRL_SHIFT, },
258 {MT6351_BUCK_VPA_CON1, MT6351_BUCK_VPA_EN_SEL_MASK, MT6351_BUCK_VPA_EN_SEL_SHIFT, },
259 {MT6351_BUCK_VPA_CON1, MT6351_BUCK_VPA_VOSEL_SEL_MASK, MT6351_BUCK_VPA_VOSEL_SEL_SHIFT, },
260 {MT6351_BUCK_VPA_CON2, MT6351_BUCK_VPA_EN_MASK, MT6351_BUCK_VPA_EN_SHIFT, },
261 {MT6351_BUCK_VPA_CON4, MT6351_BUCK_VPA_VOSEL_MASK, MT6351_BUCK_VPA_VOSEL_SHIFT, },
262 {MT6351_BUCK_VPA_CON5, MT6351_BUCK_VPA_VOSEL_ON_MASK, MT6351_BUCK_VPA_VOSEL_ON_SHIFT, },
263 {MT6351_BUCK_VPA_CON6, MT6351_BUCK_VPA_VOSEL_SLEEP_MASK, MT6351_BUCK_VPA_VOSEL_SLEEP_SHIFT, },
264 {MT6351_BUCK_VPA_CON8, MT6351_DA_NI_VPA_VOSEL_SYNC_MASK, MT6351_DA_NI_VPA_VOSEL_SYNC_SHIFT, },
265 {MT6351_BUCK_VPA_CON9, MT6351_DA_QI_VPA_DVS_EN_MASK, MT6351_DA_QI_VPA_DVS_EN_SHIFT, },
266 {MT6351_BUCK_VPA_CON9, MT6351_BUCK_VPA_VSLEEP_EN_MASK, MT6351_BUCK_VPA_VSLEEP_EN_SHIFT, },
267 {MT6351_BUCK_VPA_CON9, MT6351_BUCK_VPA_R2R_PDN_MASK, MT6351_BUCK_VPA_R2R_PDN_SHIFT, },
268 {MT6351_BUCK_VPA_CON9, MT6351_BUCK_VPA_VSLEEP_SEL_MASK, MT6351_BUCK_VPA_VSLEEP_SEL_SHIFT, },
269 {MT6351_LDO_VA18_CON0, MT6351_RG_VA18_MODE_CTRL_MASK, MT6351_RG_VA18_MODE_CTRL_SHIFT, },
270 {MT6351_LDO_VA18_CON0, MT6351_RG_VA18_ON_CTRL_MASK, MT6351_RG_VA18_ON_CTRL_SHIFT, },
271 {MT6351_LDO_VA18_CON0, MT6351_RG_VA18_SRCLK_MODE_SEL_MASK, MT6351_RG_VA18_SRCLK_MODE_SEL_SHIFT, },
272 {MT6351_LDO_VA18_CON0, MT6351_DA_QI_VA18_MODE_MASK, MT6351_DA_QI_VA18_MODE_SHIFT, },
273 {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_MODE_SET_MASK, MT6351_RG_VTCXO24_MODE_SET_SHIFT, },
274 {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_EN_MASK, MT6351_RG_VTCXO24_EN_SHIFT, },
275 {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_MODE_CTRL_MASK, MT6351_RG_VTCXO24_MODE_CTRL_SHIFT, },
276 {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_ON_CTRL_MASK, MT6351_RG_VTCXO24_ON_CTRL_SHIFT, },
277 {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_SWITCH_MASK, MT6351_RG_VTCXO24_SWITCH_SHIFT, },
278 {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_SRCLK_MODE_SEL_MASK, MT6351_RG_VTCXO24_SRCLK_MODE_SEL_SHIFT, },
279 {MT6351_LDO_VTCXO24_CON0, MT6351_DA_QI_VTCXO24_MODE_MASK, MT6351_DA_QI_VTCXO24_MODE_SHIFT, },
280 {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_STBTD_MASK, MT6351_RG_VTCXO24_STBTD_SHIFT, },
281 {MT6351_LDO_VTCXO24_CON0, MT6351_RG_VTCXO24_SRCLK_EN_SEL_MASK, MT6351_RG_VTCXO24_SRCLK_EN_SEL_SHIFT, },
282 {MT6351_LDO_VTCXO24_CON0, MT6351_DA_QI_VTCXO24_EN_MASK, MT6351_DA_QI_VTCXO24_EN_SHIFT, },
283 {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_MODE_SET_MASK, MT6351_RG_VTCXO28_MODE_SET_SHIFT, },
284 {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_EN_MASK, MT6351_RG_VTCXO28_EN_SHIFT, },
285 {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_MODE_CTRL_MASK, MT6351_RG_VTCXO28_MODE_CTRL_SHIFT, },
286 {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_ON_CTRL_MASK, MT6351_RG_VTCXO28_ON_CTRL_SHIFT, },
287 {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_SRCLK_MODE_SEL_MASK, MT6351_RG_VTCXO28_SRCLK_MODE_SEL_SHIFT, },
288 {MT6351_LDO_VTCXO28_CON0, MT6351_DA_QI_VTCXO28_MODE_MASK, MT6351_DA_QI_VTCXO28_MODE_SHIFT, },
289 {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_STBTD_MASK, MT6351_RG_VTCXO28_STBTD_SHIFT, },
290 {MT6351_LDO_VTCXO28_CON0, MT6351_RG_VTCXO28_SRCLK_EN_SEL_MASK, MT6351_RG_VTCXO28_SRCLK_EN_SEL_SHIFT, },
291 {MT6351_LDO_VTCXO28_CON0, MT6351_DA_QI_VTCXO28_EN_MASK, MT6351_DA_QI_VTCXO28_EN_SHIFT, },
292 {MT6351_LDO_VTCXO28_CON1, MT6351_DA_QI_VTCXO28_OCFB_EN_MASK, MT6351_DA_QI_VTCXO28_OCFB_EN_SHIFT, },
293 {MT6351_LDO_VCAMA_CON0, MT6351_RG_VCAMA_ON_CTRL_MASK, MT6351_RG_VCAMA_ON_CTRL_SHIFT, },
294 {MT6351_LDO_VCAMA_CON1, MT6351_RG_VCAMA_OCFB_EN_MASK, MT6351_RG_VCAMA_OCFB_EN_SHIFT, },
295 {MT6351_LDO_VCAMA_CON1, MT6351_DA_QI_VCAMA_OCFB_EN_MASK, MT6351_DA_QI_VCAMA_OCFB_EN_SHIFT, },
296 {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_MODE_SET_MASK, MT6351_RG_VSIM1_MODE_SET_SHIFT, },
297 {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_EN_MASK, MT6351_RG_VSIM1_EN_SHIFT, },
298 {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_MODE_CTRL_MASK, MT6351_RG_VSIM1_MODE_CTRL_SHIFT, },
299 {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_ON_CTRL_MASK, MT6351_RG_VSIM1_ON_CTRL_SHIFT, },
300 {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_SRCLK_MODE_SEL_MASK, MT6351_RG_VSIM1_SRCLK_MODE_SEL_SHIFT, },
301 {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_STBTD_MASK, MT6351_RG_VSIM1_STBTD_SHIFT, },
302 {MT6351_LDO_VSIM1_CON0, MT6351_RG_VSIM1_SRCLK_EN_SEL_MASK, MT6351_RG_VSIM1_SRCLK_EN_SEL_SHIFT, },
303 {MT6351_LDO_VSIM1_CON1, MT6351_RG_VSIM1_OCFB_EN_MASK, MT6351_RG_VSIM1_OCFB_EN_SHIFT, },
304 {MT6351_LDO_VSIM1_CON1, MT6351_DA_QI_VSIM1_OCFB_EN_MASK, MT6351_DA_QI_VSIM1_OCFB_EN_SHIFT, },
305 {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_MODE_SET_MASK, MT6351_RG_VSIM2_MODE_SET_SHIFT, },
306 {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_EN_MASK, MT6351_RG_VSIM2_EN_SHIFT, },
307 {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_MODE_CTRL_MASK, MT6351_RG_VSIM2_MODE_CTRL_SHIFT, },
308 {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_ON_CTRL_MASK, MT6351_RG_VSIM2_ON_CTRL_SHIFT, },
309 {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_SRCLK_MODE_SEL_MASK, MT6351_RG_VSIM2_SRCLK_MODE_SEL_SHIFT, },
310 {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_STBTD_MASK, MT6351_RG_VSIM2_STBTD_SHIFT, },
311 {MT6351_LDO_VSIM2_CON0, MT6351_RG_VSIM2_SRCLK_EN_SEL_MASK, MT6351_RG_VSIM2_SRCLK_EN_SEL_SHIFT, },
312 {MT6351_LDO_VSIM2_CON1, MT6351_RG_VSIM2_OCFB_EN_MASK, MT6351_RG_VSIM2_OCFB_EN_SHIFT, },
313 {MT6351_LDO_VSIM2_CON1, MT6351_DA_QI_VSIM2_OCFB_EN_MASK, MT6351_DA_QI_VSIM2_OCFB_EN_SHIFT, },
314 {MT6351_LDO_VIBR_CON0, MT6351_RG_VIBR_MODE_SET_MASK, MT6351_RG_VIBR_MODE_SET_SHIFT, },
315 {MT6351_LDO_VIBR_CON0, MT6351_RG_VIBR_EN_MASK, MT6351_RG_VIBR_EN_SHIFT, },
316 {MT6351_LDO_VIBR_CON0, MT6351_RG_VIBR_MODE_CTRL_MASK, MT6351_RG_VIBR_MODE_CTRL_SHIFT, },
317 {MT6351_LDO_VIBR_CON0, MT6351_RG_VIBR_ON_CTRL_MASK, MT6351_RG_VIBR_ON_CTRL_SHIFT, },
318 {MT6351_LDO_VIBR_CON0, MT6351_RG_VIBR_THER_SDN_EN_MASK, MT6351_RG_VIBR_THER_SDN_EN_SHIFT, },
319 {MT6351_LDO_VIBR_CON1, MT6351_RG_VIBR_OCFB_EN_MASK, MT6351_RG_VIBR_OCFB_EN_SHIFT, },
320 {MT6351_LDO_VIBR_CON2, MT6351_RG_VIBR_DUMMY_LOAD_MASK, MT6351_RG_VIBR_DUMMY_LOAD_SHIFT, },
321 {MT6351_LDO_VIBR_CON2, MT6351_DA_QI_VIBR_DUMMY_LOAD_MASK, MT6351_DA_QI_VIBR_DUMMY_LOAD_SHIFT, },
322 {MT6351_LDO_VCAMD_CON0, MT6351_RG_VCAMD_MODE_SET_MASK, MT6351_RG_VCAMD_MODE_SET_SHIFT, },
323 {MT6351_LDO_VCAMD_CON0, MT6351_RG_VCAMD_EN_MASK, MT6351_RG_VCAMD_EN_SHIFT, },
324 {MT6351_LDO_VCAMD_CON0, MT6351_RG_VCAMD_STBTD_MASK, MT6351_RG_VCAMD_STBTD_SHIFT, },
325 {MT6351_LDO_VCAMD_CON0, MT6351_DA_QI_VCAMD_STB_MASK, MT6351_DA_QI_VCAMD_STB_SHIFT, },
326 {MT6351_LDO_VCAMD_CON0, MT6351_DA_QI_VCAMD_EN_MASK, MT6351_DA_QI_VCAMD_EN_SHIFT, },
327 {MT6351_LDO_VCAMD_CON1, MT6351_DA_QI_VCAMD_OCFB_EN_MASK, MT6351_DA_QI_VCAMD_OCFB_EN_SHIFT, },
328 {MT6351_LDO_VCAMD_CON2, MT6351_RG_VCAMD_DUMMY_LOAD_SRCLKEN_SEL_MASK, MT6351_RG_VCAMD_DUMMY_LOAD_SRCLKEN_SEL_SHIFT, },
329 {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_MODE_SET_MASK, MT6351_RG_VRF18_MODE_SET_SHIFT, },
330 {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_EN_MASK, MT6351_RG_VRF18_EN_SHIFT, },
331 {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_MODE_CTRL_MASK, MT6351_RG_VRF18_MODE_CTRL_SHIFT, },
332 {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_ON_CTRL_MASK, MT6351_RG_VRF18_ON_CTRL_SHIFT, },
333 {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_SRCLK_MODE_SEL_MASK, MT6351_RG_VRF18_SRCLK_MODE_SEL_SHIFT, },
334 {MT6351_LDO_VRF18_CON0, MT6351_DA_QI_VRF18_MODE_MASK, MT6351_DA_QI_VRF18_MODE_SHIFT, },
335 {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_STBTD_MASK, MT6351_RG_VRF18_STBTD_SHIFT, },
336 {MT6351_LDO_VRF18_CON0, MT6351_RG_VRF18_SRCLK_EN_SEL_MASK, MT6351_RG_VRF18_SRCLK_EN_SEL_SHIFT, },
337 {MT6351_LDO_VRF18_CON0, MT6351_DA_QI_VRF18_STB_MASK, MT6351_DA_QI_VRF18_STB_SHIFT, },
338 {MT6351_LDO_VRF18_CON0, MT6351_DA_QI_VRF18_EN_MASK, MT6351_DA_QI_VRF18_EN_SHIFT, },
339 {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_MODE_SET_MASK, MT6351_RG_VRF12_MODE_SET_SHIFT, },
340 {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_EN_MASK, MT6351_RG_VRF12_EN_SHIFT, },
341 {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_MODE_CTRL_MASK, MT6351_RG_VRF12_MODE_CTRL_SHIFT, },
342 {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_ON_CTRL_MASK, MT6351_RG_VRF12_ON_CTRL_SHIFT, },
343 {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_SRCLK_MODE_SEL_MASK, MT6351_RG_VRF12_SRCLK_MODE_SEL_SHIFT, },
344 {MT6351_LDO_VRF12_CON0, MT6351_DA_QI_VRF12_MODE_MASK, MT6351_DA_QI_VRF12_MODE_SHIFT, },
345 {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_STBTD_MASK, MT6351_RG_VRF12_STBTD_SHIFT, },
346 {MT6351_LDO_VRF12_CON0, MT6351_RG_VRF12_SRCLK_EN_SEL_MASK, MT6351_RG_VRF12_SRCLK_EN_SEL_SHIFT, },
347 {MT6351_LDO_VRF12_CON0, MT6351_DA_QI_VRF12_EN_MASK, MT6351_DA_QI_VRF12_EN_SHIFT, },
348 {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_MODE_SET_MASK, MT6351_RG_VMIPI_MODE_SET_SHIFT, },
349 {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_EN_MASK, MT6351_RG_VMIPI_EN_SHIFT, },
350 {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_MODE_CTRL_MASK, MT6351_RG_VMIPI_MODE_CTRL_SHIFT, },
351 {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_ON_CTRL_MASK, MT6351_RG_VMIPI_ON_CTRL_SHIFT, },
352 {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_SRCLK_MODE_SEL_MASK, MT6351_RG_VMIPI_SRCLK_MODE_SEL_SHIFT, },
353 {MT6351_LDO_VMIPI_CON0, MT6351_DA_QI_VMIPI_MODE_MASK, MT6351_DA_QI_VMIPI_MODE_SHIFT, },
354 {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_STBTD_MASK, MT6351_RG_VMIPI_STBTD_SHIFT, },
355 {MT6351_LDO_VMIPI_CON0, MT6351_RG_VMIPI_SRCLK_EN_SEL_MASK, MT6351_RG_VMIPI_SRCLK_EN_SEL_SHIFT, },
356 {MT6351_LDO_VMIPI_CON0, MT6351_DA_QI_VMIPI_EN_MASK, MT6351_DA_QI_VMIPI_EN_SHIFT, },
357 {MT6351_LDO_VMIPI_CON1, MT6351_DA_QI_VMIPI_OCFB_EN_MASK, MT6351_DA_QI_VMIPI_OCFB_EN_SHIFT, },
358 {MT6351_VTCXO28_ANA_CON0, MT6351_RG_VTCXO28_VOSEL_MASK, MT6351_RG_VTCXO28_VOSEL_SHIFT, },
359 {MT6351_VTCXO24_ANA_CON0, MT6351_RG_VTCXO24_VOSEL_MASK, MT6351_RG_VTCXO24_VOSEL_SHIFT, },
360 {MT6351_VSIM1_ANA_CON0, MT6351_RG_VSIM1_VOSEL_MASK, MT6351_RG_VSIM1_VOSEL_SHIFT, },
361 {MT6351_VSIM2_ANA_CON0, MT6351_RG_VSIM2_CAL_MASK, MT6351_RG_VSIM2_CAL_SHIFT, },
362 {MT6351_VSIM2_ANA_CON0, MT6351_RG_VSIM2_VOSEL_MASK, MT6351_RG_VSIM2_VOSEL_SHIFT, },
363 {MT6351_VSIM2_ANA_CON1, MT6351_RG_VSIM2_STB_SEL_MASK, MT6351_RG_VSIM2_STB_SEL_SHIFT, },
364 {MT6351_VSIM2_ANA_CON1, MT6351_RG_VSIM2_OC_TRIM_MASK, MT6351_RG_VSIM2_OC_TRIM_SHIFT, },
365 {MT6351_VEFUSE_ANA_CON0, MT6351_RG_VEFUSE_CAL_MASK, MT6351_RG_VEFUSE_CAL_SHIFT, },
366 {MT6351_VEFUSE_ANA_CON1, MT6351_RG_VEFUSE_STB_SEL_MASK, MT6351_RG_VEFUSE_STB_SEL_SHIFT, },
367 {MT6351_VEFUSE_ANA_CON1, MT6351_RG_VEFUSE_OC_TRIM_MASK, MT6351_RG_VEFUSE_OC_TRIM_SHIFT, },
368 {MT6351_VRF18_ANA_CON0, MT6351_RG_VRF18_VOSEL_MASK, MT6351_RG_VRF18_VOSEL_SHIFT, },
369 {MT6351_VRF12_ANA_CON0, MT6351_RG_VRF12_VOSEL_MASK, MT6351_RG_VRF12_VOSEL_SHIFT, },
370 {MT6351_VMIPI_ANA_CON0, MT6351_RG_VMIPI_VOSEL_MASK, MT6351_RG_VMIPI_VOSEL_SHIFT, },
371 {MT6351_BIF_CON30, MT6351_BIF_TEST_MODE0_MASK, MT6351_BIF_TEST_MODE0_SHIFT, },
372 {MT6351_BIF_CON30, MT6351_BIF_TEST_MODE4_MASK, MT6351_BIF_TEST_MODE4_SHIFT, },
373 {MT6351_BIF_CON30, MT6351_BIF_TEST_MODE5_MASK, MT6351_BIF_TEST_MODE5_SHIFT, },
374 {MT6351_BIF_CON30, MT6351_BIF_BAT_LOST_SW_MASK, MT6351_BIF_BAT_LOST_SW_SHIFT, },
375 {MT6351_BIF_CON31, MT6351_BIF_IRQ_MASK, MT6351_BIF_IRQ_SHIFT, },
376 {MT6351_BIF_CON31, MT6351_BIF_TIMEOUT_MASK, MT6351_BIF_TIMEOUT_SHIFT, },
377 {MT6351_AUXADC_ADC17, MT6351_AUXADC_ADC_OUT_CH7_BY_MD_MASK, MT6351_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
378 {MT6351_AUXADC_ADC17, MT6351_AUXADC_ADC_RDY_CH7_BY_MD_MASK, MT6351_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
379 {MT6351_AUXADC_ADC19, MT6351_AUXADC_ADC_OUT_CH4_BY_MD_MASK, MT6351_AUXADC_ADC_OUT_CH4_BY_MD_SHIFT, },
380 {MT6351_AUXADC_ADC19, MT6351_AUXADC_ADC_RDY_CH4_BY_MD_MASK, MT6351_AUXADC_ADC_RDY_CH4_BY_MD_SHIFT, },
381 {MT6351_AUXADC_ADC22, MT6351_AUXADC_ADC_OUT_CH0_BY_MD_MASK, MT6351_AUXADC_ADC_OUT_CH0_BY_MD_SHIFT, },
382 {MT6351_AUXADC_ADC22, MT6351_AUXADC_ADC_RDY_CH0_BY_MD_MASK, MT6351_AUXADC_ADC_RDY_CH0_BY_MD_SHIFT, },
383 {MT6351_AUXADC_ADC24, MT6351_AUXADC_ADC_OUT_CH1_BY_MD_MASK, MT6351_AUXADC_ADC_OUT_CH1_BY_MD_SHIFT, },
384 {MT6351_AUXADC_ADC24, MT6351_AUXADC_ADC_RDY_CH1_BY_MD_MASK, MT6351_AUXADC_ADC_RDY_CH1_BY_MD_SHIFT, },
385 {MT6351_AUXADC_ADC36, MT6351_AUXADC_ADC_OUT_DCXO_BY_MD_MASK, MT6351_AUXADC_ADC_OUT_DCXO_BY_MD_SHIFT, },
386 {MT6351_AUXADC_ADC36, MT6351_AUXADC_ADC_RDY_DCXO_BY_MD_MASK, MT6351_AUXADC_ADC_RDY_DCXO_BY_MD_SHIFT, },
387 {MT6351_AUXADC_RQST1, MT6351_AUXADC_RQST_CH0_BY_MD_MASK, MT6351_AUXADC_RQST_CH0_BY_MD_SHIFT, },
388 {MT6351_AUXADC_RQST1, MT6351_AUXADC_RQST_CH1_BY_MD_MASK, MT6351_AUXADC_RQST_CH1_BY_MD_SHIFT, },
389 {MT6351_AUXADC_RQST1, MT6351_AUXADC_RQST_CH4_BY_MD_MASK, MT6351_AUXADC_RQST_CH4_BY_MD_SHIFT, },
390 {MT6351_AUXADC_RQST1, MT6351_AUXADC_RQST_CH7_BY_MD_MASK, MT6351_AUXADC_RQST_CH7_BY_MD_SHIFT, },
391 {MT6351_AUXADC_RQST1, MT6351_AUXADC_RQST_DCXO_BY_MD_MASK, MT6351_AUXADC_RQST_DCXO_BY_MD_SHIFT, },
392 {MT6351_AUXADC_RQST1_SET, MT6351_AUXADC_RQST1_SET_MASK, MT6351_AUXADC_RQST1_SET_SHIFT, },
393 {MT6351_AUXADC_RQST1_CLR, MT6351_AUXADC_RQST1_CLR_MASK, MT6351_AUXADC_RQST1_CLR_SHIFT, },
394};
395//////////////////////////////////////////////////
396// WRITE APIs //
397//////////////////////////////////////////////////
398
399// Write Whole Bytes
400void dcl_pmic6351_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
401{
402 kal_uint32 savedMask = 0;
403#if !defined(__UBL__) && !defined(__FUE__)
404 savedMask = SaveAndSetIRQMask();
405#endif //#if !defined(__UBL__) && !defined(__FUE__)
406
407#if defined(DCL_PMIC_ACCESS_TIME_LOG)
408 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
409#endif
410 if(addr <= PMIC6351_MAX_REG_NUM)
411 {
412 pmic6351_reg[addr] = val;
413 }
414
415 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
416
417#if defined(DCL_PMIC_ACCESS_TIME_LOG)
418 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
419 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
420#endif
421
422#if !defined(__UBL__) && !defined(__FUE__)
423 RestoreIRQMask(savedMask);
424#endif //#if !defined(__UBL__) && !defined(__FUE__)
425}
426
427// Write register field
428void dcl_pmic6351_field_write(PMIC6351_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
429{
430 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6351_flags_table;
431 kal_uint32 savedMask = 0;
432#if !defined(__UBL__) && !defined(__FUE__)
433 savedMask = SaveAndSetIRQMask();
434#endif //#if !defined(__UBL__) && !defined(__FUE__)
435
436#if defined(DCL_PMIC_ACCESS_TIME_LOG)
437 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
438#endif
439
440 pmic_reg_log.command_flag = flag;
441 pmic_reg_log.reg_before_write = pmic6351_reg[pTable[flag].offset];
442
443 pmic6351_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
444 pmic6351_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
445
446 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic6351_reg[pTable[flag].offset], 0x00);
447
448 pmic_reg_log.write_value = sel;
449 pmic_reg_log.address_offset = pTable[flag].offset;
450 pmic_reg_log.reg_mask = pTable[flag].mask;
451 pmic_reg_log.reg_shift = pTable[flag].shift;
452 pmic_reg_log.reg_addr = pTable[flag].offset;
453 pmic_reg_log.reg_data = pmic6351_reg[pTable[flag].offset];
454
455#if defined(DCL_PMIC_ACCESS_TIME_LOG)
456 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
457 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
458#endif
459
460#if !defined(__UBL__) && !defined(__FUE__)
461 RestoreIRQMask(savedMask);
462#endif //#if !defined(__UBL__) && !defined(__FUE__)
463}
464
465//////////////////////////////////////////////////
466// READ APIs //
467//////////////////////////////////////////////////
468
469// Read Whole Bytes
470DCL_UINT16 dcl_pmic6351_byte_return(DCL_UINT16 addr)
471{
472 DCL_UINT16 reg_temp;
473 kal_uint32 savedMask = 0;
474
475#if !defined(__UBL__) && !defined(__FUE__)
476 savedMask = SaveAndSetIRQMask();
477#endif //#if !defined(__UBL__) && !defined(__FUE__)
478
479#if defined(DCL_PMIC_ACCESS_TIME_LOG)
480 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
481#endif
482
483 DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
484
485 if(addr <= PMIC6351_MAX_REG_NUM)
486 {
487 pmic6351_reg[addr] = reg_temp;
488 }
489
490#if defined(DCL_PMIC_ACCESS_TIME_LOG)
491 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
492 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
493#endif
494
495#if !defined(__UBL__) && !defined(__FUE__)
496 RestoreIRQMask(savedMask);
497#endif //#if !defined(__UBL__) && !defined(__FUE__)
498
499 return reg_temp;
500}
501
502// Read register field
503DCL_UINT16 dcl_pmic6351_field_read(PMIC6351_FLAGS_LIST_ENUM flag)
504{
505 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic6351_flags_table;
506 kal_uint32 savedMask = 0;
507 DCL_UINT16 reg_return = 0;
508
509#if !defined(__UBL__) && !defined(__FUE__)
510 savedMask = SaveAndSetIRQMask();
511#endif //#if !defined(__UBL__) && !defined(__FUE__)
512
513#if defined(DCL_PMIC_ACCESS_TIME_LOG)
514 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time = ust_get_current_time();
515#endif
516
517 DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic6351_reg[pTable[flag].offset]);
518
519 reg_return = ((pmic6351_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
520
521#if defined(DCL_PMIC_ACCESS_TIME_LOG)
522 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time = ust_get_current_time();
523 pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].duration_time = ust_us_duration(pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].start_time, pmic_access_duration_log[PMIC_INTERFACE_DBG][pmic_access_duration_index].end_time);
524#endif
525
526#if !defined(__UBL__) && !defined(__FUE__)
527 RestoreIRQMask(savedMask);
528#endif //#if !defined(__UBL__) && !defined(__FUE__)
529
530 return reg_return;
531}
532
533
534// Exported for EM used
535void pmic6351_EM_reg_write(kal_uint16 reg, kal_uint16 val){
536 dcl_pmic6351_byte_write(reg, val);
537}
538
539kal_uint16 pmic6351_EM_reg_read(kal_uint16 reg){
540 return dcl_pmic6351_byte_return(reg);
541}
542
543PMU_CTRL_PMIC_ECO_VERSION_ENUM pmic6351_get_HW_ECO_version(void)
544{
545 return pmic6351_hw_version;
546}
547
548PMU_CTRL_PMIC_ECO_VERSION_ENUM pmic6351_get_SW_version(void)
549{
550 return pmic6351_sw_version;
551}
552
553const DCL_UINT32 vpa_vosel[] =
554{
555 PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
556 PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
557 PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
558 PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
559 PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
560 PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
561 PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
562 PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
563 PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
564 PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
565 PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
566 PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
567 PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
568 PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
569 PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
570 PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
571
572};
573
574const DCL_UINT32 vsim1_vosel[] =
575{
576 PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
577 PMU_VOLT_01_860000_V, PMU_VOLT_02_760000_V, PMU_VOLT_03_000000_V, PMU_VOLT_03_100000_V,
578};
579
580PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
581{
582 {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
583 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
584 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
585};
586
587extern PMU_CONTROL_HANDLER pmu_control_handler;
588
589DCL_UINT16 pmu_parameter_size = 0;
590
591DCL_STATUS PMIC6351_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
592{
593 DCL_UINT16 regVal;
594 DCL_INT32 return_val = STATUS_FAIL;
595
596 switch(cmd)
597 {
598 case LDO_BUCK_SET_EN:
599 {
600 PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
601
602 switch(pLdoBuckCtrl->mod)
603 {
604 case VRF18:
605// case VRF18_1:
606 {
607 dcl_pmic6351_field_write(MT6351_RG_VRF18_EN, pLdoBuckCtrl->enable);
608 return_val = STATUS_OK;
609 }
610 break;
611
612 case VRF12:
613// case VRF18_2:
614 {
615 dcl_pmic6351_field_write(MT6351_RG_VRF12_EN, pLdoBuckCtrl->enable);
616 return_val = STATUS_OK;
617 }
618 break;
619
620 case VSIM1:
621 {
622 dcl_pmic6351_field_write(MT6351_RG_VSIM1_EN, pLdoBuckCtrl->enable);
623 return_val = STATUS_OK;
624 }
625 break;
626
627 case VSIM2:
628 {
629 dcl_pmic6351_field_write(MT6351_RG_VSIM2_EN, pLdoBuckCtrl->enable);
630 return_val = STATUS_OK;
631 }
632 break;
633
634 case VMIPI:
635 {
636 dcl_pmic6351_field_write(MT6351_RG_VMIPI_EN, pLdoBuckCtrl->enable);
637 return_val = STATUS_OK;
638 }
639 break;
640
641 case VPA_SW:
642 {
643 dcl_pmic6351_field_write(MT6351_BUCK_VPA_EN, pLdoBuckCtrl->enable);
644 return_val = STATUS_OK;
645 }
646 break;
647
648 case VSRAM_MD:
649 {
650 dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_EN, pLdoBuckCtrl->enable);
651 return_val = STATUS_OK;
652 }
653 break;
654
655 case VMD1:
656 {
657 dcl_pmic6351_field_write(MT6351_BUCK_VMD1_EN, pLdoBuckCtrl->enable);
658 return_val = STATUS_OK;
659 }
660 break;
661
662 case VMODEM:
663 {
664 dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
665 return_val = STATUS_OK;
666 }
667 break;
668
669 case VTCXO24:
670 {
671 dcl_pmic6351_field_write(MT6351_RG_VTCXO24_EN, pLdoBuckCtrl->enable);
672 return_val = STATUS_OK;
673 }
674 break;
675
676 case VTCXO28:
677 {
678 dcl_pmic6351_field_write(MT6351_RG_VTCXO28_EN, pLdoBuckCtrl->enable);
679 return_val = STATUS_OK;
680 }
681 break;
682 default:
683 return_val = STATUS_UNSUPPORTED;
684 break;
685 }
686 }
687 break;
688
689 case LDO_BUCK_SET_OCFB_EN:
690 {
691 PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
692
693 switch(pLdoBuckCtrl->mod)
694 {
695 case VSIM1:
696 {
697 dcl_pmic6351_field_write(MT6351_RG_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
698 return_val = STATUS_OK;
699 }
700 break;
701
702 case VSIM2:
703 {
704 dcl_pmic6351_field_write(MT6351_RG_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
705 return_val = STATUS_OK;
706 }
707 break;
708
709 default:
710 return_val = STATUS_UNSUPPORTED;
711 break;
712 }
713 }
714 break;
715
716 case LDO_BUCK_SET_LP_MODE_SET:
717 {
718 PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
719
720 switch(pLdoBuckCtrl->mod)
721 {
722 case VRF18:
723// case VRF18_1:
724 {
725 // 1'b0:Normal mode, 1'b1:Low power mode
726 dcl_pmic6351_field_write(MT6351_RG_VRF18_MODE_SET, pLdoBuckCtrl->enable);
727 return_val = STATUS_OK;
728 }
729 break;
730
731 case VRF12:
732// case VRF18_2:
733 {
734 // 1'b0:Normal mode, 1'b1:Low power mode
735 dcl_pmic6351_field_write(MT6351_RG_VRF12_MODE_SET, pLdoBuckCtrl->enable);
736 return_val = STATUS_OK;
737 }
738 break;
739
740 case VSIM1:
741 {
742 // 1'b0:Normal mode, 1'b1:Low power mode
743 dcl_pmic6351_field_write(MT6351_RG_VSIM1_MODE_SET, pLdoBuckCtrl->enable);
744 return_val = STATUS_OK;
745 }
746 break;
747
748 case VSIM2:
749 {
750 // 1'b0:Normal mode, 1'b1:Low power mode
751 dcl_pmic6351_field_write(MT6351_RG_VSIM2_MODE_SET, pLdoBuckCtrl->enable);
752 return_val = STATUS_OK;
753 }
754 break;
755
756 case VMIPI:
757 {
758 // 1'b0:Normal mode, 1'b1:Low power mode
759 dcl_pmic6351_field_write(MT6351_RG_VMIPI_MODE_SET, pLdoBuckCtrl->enable);
760 return_val = STATUS_OK;
761 }
762 break;
763
764 case VTCXO24:
765 {
766 dcl_pmic6351_field_write(MT6351_RG_VTCXO24_MODE_SET, pLdoBuckCtrl->enable);
767 return_val = STATUS_OK;
768 }
769 break;
770
771 case VTCXO28:
772 {
773 dcl_pmic6351_field_write(MT6351_RG_VTCXO28_MODE_SET, pLdoBuckCtrl->enable);
774 return_val = STATUS_OK;
775 }
776 break;
777 default:
778 return_val = STATUS_UNSUPPORTED;
779 break;
780 }
781 }
782 break;
783
784 case LDO_BUCK_SET_LP_SEL:
785 {
786 PMU_CTRL_LDO_BUCK_SET_LP_SEL *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpSel);
787
788 switch(pLdoBuckCtrl->mod)
789 {
790 case VRF18:
791// case VRF18_1:
792 {
793 // 1'b0: SW control by VSIM1_MODE_SET, 1'b1: HW control by SRCLKEN
794 dcl_pmic6351_field_write(MT6351_RG_VRF18_MODE_CTRL, pLdoBuckCtrl->onSel);
795 return_val = STATUS_OK;
796 }
797 break;
798 case VRF12:
799// case VRF18_2:
800 {
801 dcl_pmic6351_field_write(MT6351_RG_VRF12_MODE_CTRL, pLdoBuckCtrl->onSel);
802 return_val = STATUS_OK;
803 }
804 break;
805
806
807 case VSIM1:
808 {
809 // 1'b0: SW control by VSIM1_MODE_SET, 1'b1: HW control by SRCLKEN
810 dcl_pmic6351_field_write(MT6351_RG_VSIM1_MODE_CTRL, pLdoBuckCtrl->onSel);
811 return_val = STATUS_OK;
812 }
813 break;
814
815 case VSIM2:
816 {
817 dcl_pmic6351_field_write(MT6351_RG_VSIM2_MODE_CTRL, pLdoBuckCtrl->onSel);
818 return_val = STATUS_OK;
819 }
820 break;
821
822 case VMIPI:
823 {
824 dcl_pmic6351_field_write(MT6351_RG_VMIPI_MODE_CTRL, pLdoBuckCtrl->onSel);
825 return_val = STATUS_OK;
826 }
827 break;
828
829 case VTCXO24:
830 {
831 dcl_pmic6351_field_write(MT6351_RG_VTCXO24_MODE_CTRL, pLdoBuckCtrl->onSel);
832 return_val = STATUS_OK;
833 }
834 break;
835
836 case VTCXO28:
837 {
838 dcl_pmic6351_field_write(MT6351_RG_VTCXO28_MODE_CTRL, pLdoBuckCtrl->onSel);
839 return_val = STATUS_OK;
840 }
841 break;
842 default:
843 return_val = STATUS_UNSUPPORTED;
844 break;
845 }
846 }
847 break;
848
849 case LDO_BUCK_SET_VOLTAGE:
850 {
851 PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
852 regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
853
854 switch(pLdoBuckCtrl->mod)
855 {
856 case VSIM1:
857 {
858 dcl_pmic6351_field_write(MT6351_RG_VSIM1_VOSEL, regVal);
859 return_val = STATUS_OK;
860 }
861 break;
862
863 case VSIM2:
864 {
865 dcl_pmic6351_field_write(MT6351_RG_VSIM2_VOSEL, regVal);
866 return_val = STATUS_OK;
867 }
868 break;
869
870 case VPA_SW:
871 {
872 dcl_pmic6351_field_write(MT6351_BUCK_VPA_VOSEL, regVal);
873 return_val = STATUS_OK;
874 }
875 break;
876
877 case VTCXO24:
878 {
879 dcl_pmic6351_field_write(MT6351_RG_VTCXO24_VOSEL, regVal);
880 return_val = STATUS_OK;
881 }
882 break;
883
884 case VTCXO28:
885 {
886 dcl_pmic6351_field_write(MT6351_RG_VTCXO28_VOSEL, regVal);
887 return_val = STATUS_OK;
888 }
889 break;
890 default:
891 return_val = STATUS_UNSUPPORTED;
892 break;
893 }
894 }
895 break;
896
897 case LDO_BUCK_GET_VOLTAGE:
898 {
899 PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
900
901 switch(pLdoBuckCtrl->mod)
902 {
903 case VSRAM_MD:
904 {
905 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_DA_NI_VSRAM_MD_VOSEL_SYNC);
906 return_val = STATUS_OK;
907 }
908 break;
909
910 case VMD1:
911 {
912 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_DA_NI_VMD1_VOSEL_SYNC);
913 return_val = STATUS_OK;
914 }
915 break;
916
917 case VMODEM:
918 {
919 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_DA_NI_VMODEM_VOSEL_SYNC);
920 return_val = STATUS_OK;
921 }
922 break;
923
924 default:
925 return_val = STATUS_UNSUPPORTED;
926 break;
927 }
928 }
929 break;
930
931 case LDO_BUCK_GET_VOSEL_CTRL:
932 {
933 PMU_CTRL_LDO_BUCK_GET_VOSEL_CTRL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselCtrl);
934
935 switch(pLdoBuckCtrl->mod)
936 {
937 case VSRAM_MD:
938 {
939 pLdoBuckCtrl->mode = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VSRAM_MD_VOSEL_CTRL);
940 return_val = STATUS_OK;
941 }
942 break;
943 case VMD1:
944 {
945 pLdoBuckCtrl->mode = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMD1_VOSEL_CTRL);
946 return_val = STATUS_OK;
947 }
948 break;
949 case VMODEM:
950 {
951 pLdoBuckCtrl->mode = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMODEM_VOSEL_CTRL);
952 return_val = STATUS_OK;
953 }
954 break;
955 default:
956 return_val = STATUS_UNSUPPORTED;
957 break;
958 }
959 }
960 break;
961
962 case LDO_BUCK_GET_VOSEL:
963 {
964 PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
965
966 switch(pLdoBuckCtrl->mod)
967 {
968 case VSRAM_MD:
969 {
970 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VSRAM_MD_VOSEL);
971 return_val = STATUS_OK;
972 }
973 break;
974
975 case VMD1:
976 {
977 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMD1_VOSEL);
978 return_val = STATUS_OK;
979 }
980 break;
981
982 case VMODEM:
983 {
984 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMODEM_VOSEL);
985 return_val = STATUS_OK;
986 }
987 break;
988
989 default:
990 return_val = STATUS_UNSUPPORTED;
991 break;
992 }
993 }
994 break;
995
996 case LDO_BUCK_GET_VOSEL_ON:
997 {
998 PMU_CTRL_LDO_BUCK_GET_VOSEL_ON *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselOn);
999
1000 switch(pLdoBuckCtrl->mod)
1001 {
1002 case VSRAM_MD:
1003 {
1004 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VSRAM_MD_VOSEL_ON);
1005 return_val = STATUS_OK;
1006 }
1007 break;
1008
1009 case VMD1:
1010 {
1011 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMD1_VOSEL_ON);
1012 return_val = STATUS_OK;
1013 }
1014 break;
1015
1016 case VMODEM:
1017 {
1018 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMODEM_VOSEL_ON);
1019 return_val = STATUS_OK;
1020 }
1021 break;
1022
1023 default:
1024 return_val = STATUS_UNSUPPORTED;
1025 break;
1026 }
1027 }
1028 break;
1029
1030 case LDO_BUCK_GET_VOSEL_SLEEP:
1031 {
1032 PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
1033
1034 switch(pLdoBuckCtrl->mod)
1035 {
1036 case VSRAM_MD:
1037 {
1038 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VSRAM_MD_VOSEL_SLEEP);
1039 return_val = STATUS_OK;
1040 }
1041 break;
1042
1043 case VMD1:
1044 {
1045 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMD1_VOSEL_SLEEP);
1046 return_val = STATUS_OK;
1047 }
1048 break;
1049
1050 case VMODEM:
1051 {
1052 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_BUCK_VMODEM_VOSEL_SLEEP);
1053 return_val = STATUS_OK;
1054 }
1055 break;
1056
1057
1058 default:
1059 return_val = STATUS_UNSUPPORTED;
1060 break;
1061 }
1062 }
1063 break;
1064
1065 case LDO_BUCK_SET_VOSEL_CTRL:
1066 {
1067 PMU_CTRL_LDO_BUCK_SET_VOSEL_CTRL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselCtrl);
1068
1069 switch(pLdoBuckCtrl->mod)
1070 {
1071 case VSRAM_MD:
1072 {
1073 // 0: SW control, 1: HW
1074 dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_VOSEL_CTRL, pLdoBuckCtrl->mode);
1075 return_val = STATUS_OK;
1076 }
1077 break;
1078 case VMD1:
1079 {
1080 // 0: SW control, 1: HW
1081 dcl_pmic6351_field_write(MT6351_BUCK_VMD1_VOSEL_CTRL, pLdoBuckCtrl->mode);
1082 return_val = STATUS_OK;
1083 }
1084 break;
1085 case VMODEM:
1086 {
1087 // 0: SW control, 1: HW
1088 dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_VOSEL_CTRL, pLdoBuckCtrl->mode);
1089 return_val = STATUS_OK;
1090 }
1091 break;
1092 default:
1093 return_val = STATUS_UNSUPPORTED;
1094 break;
1095 }
1096 }
1097 break;
1098
1099 case LDO_BUCK_SET_VOSEL:
1100 {
1101 PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
1102
1103 switch(pLdoBuckCtrl->mod)
1104 {
1105 case VSRAM_MD:
1106 {
1107 dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_VOSEL, pLdoBuckCtrl->code);
1108 return_val = STATUS_OK;
1109 }
1110 break;
1111
1112 case VMD1:
1113 {
1114 dcl_pmic6351_field_write(MT6351_BUCK_VMD1_VOSEL, pLdoBuckCtrl->code);
1115 return_val = STATUS_OK;
1116 }
1117 break;
1118
1119 case VMODEM:
1120 {
1121 dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
1122 return_val = STATUS_OK;
1123 }
1124 break;
1125
1126 default:
1127 return_val = STATUS_UNSUPPORTED;
1128 break;
1129 }
1130 }
1131 break;
1132
1133 case LDO_BUCK_SET_VOSEL_ON:
1134 {
1135 PMU_CTRL_LDO_BUCK_SET_VOSEL_ON *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselOn);
1136
1137 switch(pLdoBuckCtrl->mod)
1138 {
1139 case VSRAM_MD:
1140 {
1141 dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_VOSEL_ON, pLdoBuckCtrl->code);
1142 return_val = STATUS_OK;
1143 }
1144 break;
1145
1146 case VMD1:
1147 {
1148 dcl_pmic6351_field_write(MT6351_BUCK_VMD1_VOSEL_ON, pLdoBuckCtrl->code);
1149 return_val = STATUS_OK;
1150 }
1151 break;
1152
1153 case VMODEM:
1154 {
1155 dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_VOSEL_ON, pLdoBuckCtrl->code);
1156 return_val = STATUS_OK;
1157 }
1158 break;
1159
1160 default:
1161 return_val = STATUS_UNSUPPORTED;
1162 break;
1163 }
1164 }
1165 break;
1166
1167 case LDO_BUCK_SET_VOSEL_SLEEP:
1168 {
1169 PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
1170
1171 switch(pLdoBuckCtrl->mod)
1172 {
1173 case VSRAM_MD:
1174 {
1175 dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_VOSEL_SLEEP, pLdoBuckCtrl->code);
1176 return_val = STATUS_OK;
1177 }
1178 break;
1179
1180 case VMD1:
1181 {
1182 dcl_pmic6351_field_write(MT6351_BUCK_VMD1_VOSEL_SLEEP, pLdoBuckCtrl->code);
1183 return_val = STATUS_OK;
1184 }
1185 break;
1186
1187 case VMODEM:
1188 {
1189 dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
1190 return_val = STATUS_OK;
1191 }
1192 break;
1193
1194 default:
1195 return_val = STATUS_UNSUPPORTED;
1196 break;
1197 }
1198 }
1199 break;
1200
1201 case LDO_BUCK_SET_EN_CTRL:
1202 {
1203 PMU_CTRL_LDO_BUCK_SET_EN_CTRL *pLdoBuckCtrl = &(data->rPMULdoBuckSetEnCtrl);
1204
1205 switch(pLdoBuckCtrl->mod)
1206 {
1207 case VRF18:
1208// case VRF18_1:
1209 {
1210 // 0: SW control1: HW control
1211 dcl_pmic6351_field_write(MT6351_RG_VRF18_ON_CTRL, pLdoBuckCtrl->mode);
1212 return_val = STATUS_OK;
1213 }
1214 break;
1215
1216 case VRF12:
1217// case VRF18_2:
1218 {
1219 dcl_pmic6351_field_write(MT6351_RG_VRF12_ON_CTRL, pLdoBuckCtrl->mode);
1220 return_val = STATUS_OK;
1221 }
1222 break;
1223
1224 case VMIPI:
1225 {
1226 // 0: SW control, 1: HW
1227 dcl_pmic6351_field_write(MT6351_RG_VMIPI_ON_CTRL, pLdoBuckCtrl->mode);
1228 return_val = STATUS_OK;
1229 }
1230 break;
1231
1232 case VSRAM_MD:
1233 {
1234 // 0: SW control, 1: HW
1235 dcl_pmic6351_field_write(MT6351_BUCK_VSRAM_MD_EN_CTRL, pLdoBuckCtrl->mode);
1236 return_val = STATUS_OK;
1237 }
1238 break;
1239 case VMD1:
1240 {
1241 // 0: SW control, 1: HW
1242 dcl_pmic6351_field_write(MT6351_BUCK_VMD1_EN_CTRL, pLdoBuckCtrl->mode);
1243 return_val = STATUS_OK;
1244 }
1245 break;
1246 case VMODEM:
1247 {
1248 // 0: SW control, 1: HW
1249 dcl_pmic6351_field_write(MT6351_BUCK_VMODEM_EN_CTRL, pLdoBuckCtrl->mode);
1250 return_val = STATUS_OK;
1251 }
1252 break;
1253 case VTCXO24:
1254 {
1255 // 0: SW control, 1: HW
1256 dcl_pmic6351_field_write(MT6351_RG_VTCXO24_ON_CTRL, pLdoBuckCtrl->mode);
1257 return_val = STATUS_OK;
1258 }
1259 break;
1260 case VTCXO28:
1261 {
1262 // 0: SW control, 1: HW
1263 dcl_pmic6351_field_write(MT6351_RG_VTCXO28_ON_CTRL, pLdoBuckCtrl->mode);
1264 return_val = STATUS_OK;
1265 }
1266 break;
1267 default:
1268 return_val = STATUS_UNSUPPORTED;
1269 break;
1270 }
1271 }
1272 break;
1273
1274
1275
1276 case LDO_BUCK_SET_EN_SEL:
1277 {
1278 PMU_CTRL_LDO_BUCK_SET_EN_SEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetEnSel);
1279
1280 switch(pLdoBuckCtrl->mod)
1281 {
1282 case VRF18:
1283// case VRF18_1:
1284 {
1285 dcl_pmic6351_field_write(MT6351_RG_VRF18_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
1286 return_val = STATUS_OK;
1287 }
1288 break;
1289
1290 case VRF12:
1291// case VRF18_2:
1292 {
1293 dcl_pmic6351_field_write(MT6351_RG_VRF12_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
1294 return_val = STATUS_OK;
1295 }
1296 break;
1297
1298 case VSIM1:
1299 {
1300 dcl_pmic6351_field_write(MT6351_RG_VSIM1_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
1301 return_val = STATUS_OK;
1302 }
1303 break;
1304
1305 case VSIM2:
1306 {
1307 dcl_pmic6351_field_write(MT6351_RG_VSIM2_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
1308 return_val = STATUS_OK;
1309 }
1310 break;
1311
1312 case VMIPI:
1313 {
1314 dcl_pmic6351_field_write(MT6351_RG_VMIPI_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
1315 return_val = STATUS_OK;
1316 }
1317 break;
1318
1319 case VTCXO24:
1320 {
1321 dcl_pmic6351_field_write(MT6351_RG_VTCXO24_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
1322 return_val = STATUS_OK;
1323 }
1324 break;
1325
1326 case VTCXO28:
1327 {
1328 dcl_pmic6351_field_write(MT6351_RG_VTCXO28_SRCLK_EN_SEL, pLdoBuckCtrl->sel);
1329 return_val = STATUS_OK;
1330 }
1331 break;
1332 default:
1333 return_val = STATUS_UNSUPPORTED;
1334 break;
1335 }
1336 }
1337 break;
1338
1339 case LDO_BUCK_SET_SRCLK_MODE_SEL:
1340 {
1341 PMU_CTRL_LDO_BUCK_SET_SRCLK_MODE_SEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetSrclkModeSel);
1342
1343 switch(pLdoBuckCtrl->mod)
1344 {
1345 case VRF18:
1346// case VRF18_1:
1347 {
1348 dcl_pmic6351_field_write(MT6351_RG_VRF18_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
1349 return_val = STATUS_OK;
1350 }
1351 break;
1352 case VRF12:
1353// case VRF18_2:
1354 {
1355 dcl_pmic6351_field_write(MT6351_RG_VRF12_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
1356 return_val = STATUS_OK;
1357 }
1358 break;
1359
1360 case VSIM1:
1361 {
1362 dcl_pmic6351_field_write(MT6351_RG_VSIM1_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
1363 return_val = STATUS_OK;
1364 }
1365 break;
1366
1367 case VSIM2:
1368 {
1369 dcl_pmic6351_field_write(MT6351_RG_VSIM2_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
1370 return_val = STATUS_OK;
1371 }
1372 break;
1373
1374 case VMIPI:
1375 {
1376 dcl_pmic6351_field_write(MT6351_RG_VMIPI_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
1377 return_val = STATUS_OK;
1378 }
1379 break;
1380
1381 case VTCXO24:
1382 {
1383 dcl_pmic6351_field_write(MT6351_RG_VTCXO24_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
1384 return_val = STATUS_OK;
1385 }
1386 break;
1387
1388 case VTCXO28:
1389 {
1390 dcl_pmic6351_field_write(MT6351_RG_VTCXO28_SRCLK_MODE_SEL, pLdoBuckCtrl->sel);
1391 return_val = STATUS_OK;
1392 }
1393 break;
1394 default:
1395 return_val = STATUS_UNSUPPORTED;
1396 break;
1397 }
1398 }
1399 break;
1400
1401 case LDO_BUCK_SET_VTCXO24_SWITCH:
1402 {
1403 PMU_CTRL_LDO_SET_VTCXO24_SWITCH_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetVtcxoSwith);
1404
1405 switch(pLdoBuckCtrl->mod)
1406 {
1407
1408 case VTCXO24:
1409 {
1410 dcl_pmic6351_field_write(MT6351_RG_VTCXO24_SWITCH, pLdoBuckCtrl->enable);
1411 return_val = STATUS_OK;
1412 }
1413 break;
1414 default:
1415 return_val = STATUS_UNSUPPORTED;
1416 break;
1417 }
1418 }
1419 break;
1420 case LDO_BUCK_SET_MODESET:
1421 {
1422 PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
1423
1424
1425 switch(pLdoBuckCtrl->mod)
1426 {
1427 case VPA_SW:
1428 {
1429 dcl_pmic6351_field_write(MT6351_RG_VPA_MODESET, pLdoBuckCtrl->mode);
1430 return_val = STATUS_OK;
1431 }
1432 break;
1433
1434#if 0
1435/* under construction !*/
1436/* under construction !*/
1437/* under construction !*/
1438/* under construction !*/
1439/* under construction !*/
1440/* under construction !*/
1441#endif
1442 default:
1443 return_val = STATUS_UNSUPPORTED;
1444 break;
1445 }
1446 }
1447 break;
1448
1449 case VPA_SET_EN:
1450 {
1451 PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
1452 dcl_pmic6351_field_write(MT6351_BUCK_VPA_EN, pVpaSetEn->enable);
1453 return_val = STATUS_OK;
1454 }
1455 break;
1456
1457 case VPA_GET_VOLTAGE_LIST:
1458 {
1459 PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
1460 pVpaCtrl->pVoltageList = vpa_vosel;
1461 pVpaCtrl->number = GETARRNUM(vpa_vosel);
1462 return_val = STATUS_OK;
1463 }
1464 break;
1465
1466 /*
1467 1. AUXADC_RQST1_CLR[7] 1'h1
1468 2. AUXADC_RQST1_SET[7] 1'h1
1469 3. After 10us
1470 4. Polling ready, AUXADC_ADC_RDY_Ch7_BY_MD
1471 5. After AUXADC_ADC_RDY_Ch7_BY_MD = 1, get data by AUXADC_ADC_OUT_CH7_BY_MD
1472 6. AUXADC_RQST1_CLR[7] 1'h1
1473 */
1474 case ADC_SET_RQST:
1475 {
1476 PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
1477 if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
1478 {
1479 ASSERT(0);
1480 }
1481 // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
1482 dcl_pmic6351_byte_write(MT6351_TOP_CLKSQ_SET, (0x1 << 3));
1483 dcl_pmic6351_byte_write(MT6351_AUXADC_RQST1_CLR, (pAdcCtrl->enable << 7));
1484 dcl_pmic6351_byte_write(MT6351_AUXADC_RQST1_SET, (0x1 << 7));
1485 AUXADC_Status = AUXADC_READ_REQUEST;
1486 return_val = STATUS_OK;
1487 }
1488 break;
1489
1490 case ADC_GET_RDY_MD:
1491 {
1492 PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
1493
1494 pAdcCtrl->status = (DCL_BOOL)dcl_pmic6351_field_read(MT6351_AUXADC_ADC_RDY_CH7_BY_MD);
1495 if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
1496 {
1497 ASSERT(0);
1498 }
1499
1500 if(pAdcCtrl->status == DCL_TRUE)
1501 {
1502 AUXADC_Status = AUXADC_READ_READY;
1503 }
1504 else
1505 {
1506 AUXADC_Status = AUXADC_READ_BUSY;
1507 }
1508
1509 return_val = STATUS_OK;
1510 }
1511 break;
1512
1513 case ADC_GET_OUT_MD:
1514 {
1515 PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
1516 if(AUXADC_Status != AUXADC_READ_READY)
1517 {
1518 ASSERT(0);
1519 }
1520 pAdcCtrl->data = (DCL_UINT32)dcl_pmic6351_field_read(MT6351_AUXADC_ADC_OUT_CH7_BY_MD);
1521 AUXADC_Status = AUXADC_READ_DATA;
1522 dcl_pmic6351_byte_write(MT6351_AUXADC_RQST1_CLR, (0x1 << 7));
1523 // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
1524 dcl_pmic6351_byte_write(MT6351_TOP_CLKSQ_CLR, (0x1 << 3));
1525
1526 return_val = STATUS_OK;
1527 }
1528 break;
1529
1530 case MISC_GET_HW_VERSION:
1531 {
1532 PMU_CTRL_MISC_GET_HW_VERSION *pMiscCtrl = &(data->rPMUMiscGetHwVersion);
1533 if(pMiscCtrl->chip_name == PMIC_6351)
1534 {
1535 pMiscCtrl->version = pmic6351_hw_version;
1536 }
1537 return_val = STATUS_OK;
1538 }
1539 break;
1540 case MISC_SET_REGISTER_VALUE:
1541 {
1542 PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
1543 pmic6351_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
1544 return_val = STATUS_OK;
1545 }
1546 break;
1547
1548 case MISC_GET_REGISTER_VALUE:
1549 {
1550 PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
1551 pChrCtrl->value = pmic6351_EM_reg_read(pChrCtrl->offset);
1552 return_val = STATUS_OK;
1553 }
1554 break;
1555
1556 default:
1557 return_val = STATUS_UNSUPPORTED;
1558 break;
1559 }
1560
1561 return return_val;
1562}
1563
1564extern void dcl_pmic6351_modem_only_init(void);
1565extern DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr);
1566extern void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value);
1567extern kal_uint32 PMIC_Config_Interface(kal_bool action, kal_uint32 address, kal_uint32 wdata, kal_uint32 *rdata, kal_uint32 chip_name);
1568extern void PMIC_Read_All(void);
1569#if defined(PMIC_UNIT_TEST)
1570extern void PMIC_Read_All(void);
1571extern void PMIC_Unit_Test(void);
1572#endif
1573
1574
1575void dcl_pmic6351_internal_init(void)
1576{
1577}
1578
1579#if defined(__DHL_MODULE__)
1580extern kal_bool dhl_register_custom_mem_read(DHL_CUSTOM_MEM_TYPE mem_type, DHL_CUSTOM_READ_MEM_CALLBACK read_cb);
1581extern kal_bool dhl_register_custom_mem_write(DHL_CUSTOM_MEM_TYPE mem_type, DHL_CUSTOM_WRITE_MEM_CALLBACK write_cb);
1582extern void PMIC_Read_Callback_For_DHL(void* read_addr, kal_uint32 len, kal_uint32 option, void** read_buffer_addr, kal_uint32 *read_buffer_len);
1583extern void PMIC_Write_Callback_For_DHL(void* write_addr, kal_uint32 len, kal_uint32 option, void* write_buffer_addr);
1584#endif
1585
1586void dcl_pmic6351_init(void){
1587 extern void pmic_wrap_dump_init(void);
1588 pmu_control_handler = PMIC6351_control_handler;
1589 pmu_parameter_size = GETARRNUM(pmu_parameter_table);
1590#if defined(__DHL_MODULE__)
1591 dhl_register_custom_mem_read(DHL_CUSTOM_MEM_PMIC, PMIC_Read_Callback_For_DHL);
1592 dhl_register_custom_mem_write(DHL_CUSTOM_MEM_PMIC, PMIC_Write_Callback_For_DHL);
1593#endif
1594 pmic_wrap_dump_init();
1595
1596#if !defined(__SMART_PHONE_MODEM__)
1597 DrvPWRAP_Init();
1598#endif
1599 pmic6351_hw_version = PMIC_ECO_E1;
1600 pmic6351_sw_version = PMIC_ECO_E1;
1601
1602 // Get MT6351 ECO version
1603 {
1604 kal_uint16 pmic6351_hw_eco_version = 0;
1605 kal_uint16 pmic6351_sw_eco_version = 0;
1606 pmic6351_hw_eco_version = dcl_pmic6351_byte_return(MT6351_HWCID);
1607 pmic6351_sw_eco_version = dcl_pmic6351_byte_return(MT6351_SWCID);
1608
1609 if (pmic6351_hw_eco_version == MT6351_HW_CID_E1)
1610 {
1611 pmic6351_hw_version = PMIC_ECO_E1;
1612 }
1613 else if (pmic6351_hw_eco_version == MT6351_HW_CID_E2)
1614 {
1615 pmic6351_hw_version = PMIC_ECO_E2;
1616 }
1617 else
1618 {
1619 pmic6351_hw_version = PMIC_ECO_E3;
1620 }
1621
1622 if (pmic6351_sw_eco_version == MT6351_SW_CID_E1)
1623 {
1624 pmic6351_sw_version = PMIC_ECO_E1;
1625 }
1626 else if (pmic6351_sw_eco_version == MT6351_SW_CID_E2)
1627 {
1628 pmic6351_sw_version = PMIC_ECO_E2;
1629 }
1630 else
1631 {
1632 pmic6351_sw_version = PMIC_ECO_E3;
1633 }
1634 }
1635
1636 PMIC_Read_All();
1637
1638#if !defined(__SMART_PHONE_MODEM__)
1639 dcl_pmic6351_modem_only_init();
1640#endif
1641 dcl_pmic6351_internal_init();
1642
1643 // pmic6351_customization_init();
1644#if defined(PMIC_UNIT_TEST)
1645 PMIC_Read_All();
1646 PMIC_Unit_Test();
1647 PMIC_Read_All();
1648#endif
1649 pmic_init_done = DCL_TRUE;
1650
1651}
1652
1653#if defined(__DHL_MODULE__)
1654kal_uint32 pmic_read_data;
1655void PMIC_Read_Callback_For_DHL(void* read_addr, kal_uint32 len, kal_uint32 option, void** read_buffer_addr, kal_uint32 *read_buffer_len)
1656{
1657 kal_uint32 write_buffer_addr = 0;
1658 kal_uint32 read_data_addr = (kal_uint32)read_addr;
1659 // Write Workaround
1660 if(read_data_addr & 0x00000001)
1661 {
1662 write_buffer_addr = (read_data_addr & 0xFFFF0000) >> 16;
1663 read_data_addr = (read_data_addr & 0x0000FFFE);
1664 PMIC_Config_Interface(PMIC_WRITE, read_data_addr, (kal_uint32)write_buffer_addr, NULL, option);
1665 }
1666 PMIC_Config_Interface(PMIC_READ, read_data_addr, 0, &pmic_read_data, option);
1667 *read_buffer_addr = (kal_uint32*)&pmic_read_data;
1668 *read_buffer_len = 4;
1669}
1670
1671void PMIC_Write_Callback_For_DHL(void* write_addr, kal_uint32 len, kal_uint32 option, void* write_buffer_addr)
1672{
1673 PMIC_Config_Interface(PMIC_WRITE, (kal_uint32)write_addr, (kal_uint32)write_buffer_addr, NULL, option);
1674}
1675#endif // End of #if defined(__DHL_MODULE__)
1676kal_uint32 PMIC_Config_Interface(kal_bool action, kal_uint32 address, kal_uint32 wdata, kal_uint32 *rdata, kal_uint32 chip_name)
1677{
1678 // Check argument validation
1679 if((action & ~(0x1)) != 0) return 0; // Write should be 1 bit
1680 if((address & ~(0xffff)) != 0) return 0; // Address should no larger than 0xFFFF
1681 if((wdata & ~(0xffff)) != 0) return 0; // Write DATA should be no larger than 0xFFFF
1682
1683 if(action == PMIC_READ)
1684 {
1685 if(chip_name == PMIC_6351)
1686 {
1687 *rdata = (kal_uint32)DRV_Read_PMIC_Data(address);
1688 }
1689 else
1690 {
1691 ASSERT(0);
1692 }
1693 }
1694 else if(action == PMIC_WRITE)
1695 {
1696 if(chip_name == PMIC_6351)
1697 {
1698 DRV_Write_PMIC_Data(address, wdata);
1699 }
1700 else
1701 {
1702 ASSERT(0);
1703 }
1704 }
1705 return 1;
1706}
1707
1708DCL_BOOL dcl_pmic_init_done_query(void)
1709{
1710 if(pmic_init_done == DCL_TRUE)
1711 {
1712 return DCL_TRUE;
1713 }
1714 else
1715 {
1716 return DCL_FALSE;
1717 }
1718}
1719
1720DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
1721{
1722 return dcl_pmic6351_byte_return(pmic_addr);
1723}
1724
1725void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
1726{
1727 dcl_pmic6351_byte_write(pmic_addr, value);
1728}
1729
1730void PMIC_Read_All(void)
1731{
1732 volatile kal_uint32 i;
1733 for (i = 0; i < PMIC6351_MAX_REG_NUM; i += 2){
1734 pmic6351_reg[i] = dcl_pmic6351_byte_return(i);
1735 }
1736}
1737
1738#if defined(PMIC_UNIT_TEST)
1739void PMIC_Unit_Test(void)
1740{
1741{
1742DCL_HANDLE handle;
1743PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
1744handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1745val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
1746val.mod = VMIPI;
1747DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
1748DclPMU_Close(handle);
1749}
1750{
1751DCL_HANDLE handle;
1752PMU_CTRL_LDO_BUCK_SET_EN val;
1753handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1754val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1755val.mod = VMIPI;
1756DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1757DclPMU_Close(handle);
1758}
1759{
1760DCL_HANDLE handle;
1761PMU_CTRL_LDO_BUCK_SET_EN val;
1762handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1763val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1764val.mod = VPA_SW;
1765DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1766DclPMU_Close(handle);
1767}
1768{
1769DCL_HANDLE handle;
1770PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
1771handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1772val.mod=VPA_SW;
1773val.voltage = PMU_VOLT_01_800000_V;
1774/* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
1775 PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
1776 PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
1777 PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
1778 PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
1779 PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
1780 PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
1781 PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
1782 PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
1783 PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
1784 PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
1785 PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
1786 PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
1787 PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
1788 PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
1789 PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
1790DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
1791DclPMU_Close(handle);
1792}
1793{
1794DCL_HANDLE handle;
1795PMU_CTRL_LDO_BUCK_SET_MODESET val;
1796handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1797val.mod = VPA_SW;
1798val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
1799DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
1800DclPMU_Close(handle);
1801}
1802{
1803DCL_HANDLE handle;
1804PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
1805handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1806val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
1807val.mod = VRF1;
1808DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
1809DclPMU_Close(handle);
1810}
1811{
1812DCL_HANDLE handle;
1813PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
1814handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1815val.sel = SRCLKEN_IN1_SEL;
1816/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
1817 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
1818val.mod = VRF1;
1819DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
1820DclPMU_Close(handle);
1821}
1822{
1823DCL_HANDLE handle;
1824PMU_CTRL_LDO_BUCK_SET_MODESET val;
1825handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1826val.mod = VRF1;
1827val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
1828DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
1829DclPMU_Close(handle);
1830}
1831{
1832DCL_HANDLE handle;
1833PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
1834handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1835val.regval = 0x7; // (0x0~0xF)
1836DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
1837DclPMU_Close(handle);
1838}
1839{
1840DCL_HANDLE handle;
1841PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
1842handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1843val.regval = 0x7; // (0x0~0xF)
1844DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
1845DclPMU_Close(handle);
1846}
1847{
1848DCL_HANDLE handle;
1849PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
1850handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1851// val.regval will be your request value ( no need do any shift)
1852DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
1853DclPMU_Close(handle);
1854}
1855{
1856DCL_HANDLE handle;
1857PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
1858handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1859val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
1860val.mod = VRF2;
1861DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
1862DclPMU_Close(handle);
1863}
1864{
1865DCL_HANDLE handle;
1866PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
1867handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1868val.sel = SRCLKEN_IN1_SEL;
1869/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
1870 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
1871val.mod = VRF2;
1872DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
1873DclPMU_Close(handle);
1874}
1875{
1876DCL_HANDLE handle;
1877PMU_CTRL_LDO_BUCK_SET_EN val;
1878handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1879val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1880val.mod = VRF2;
1881DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1882DclPMU_Close(handle);
1883}
1884{
1885DCL_HANDLE handle;
1886PMU_CTRL_LDO_BUCK_SET_MODESET val;
1887handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1888val.mod = VRF1;
1889val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
1890DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
1891DclPMU_Close(handle);
1892}
1893{
1894DCL_HANDLE handle;
1895PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
1896handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1897val.sel = SRCLKEN_IN1_SEL;
1898/* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
1899 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
1900val.mod = VMIPI;
1901DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
1902DclPMU_Close(handle);
1903}
1904{
1905DCL_HANDLE handle;
1906PMU_CTRL_LDO_BUCK_SET_EN val;
1907handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1908val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1909val.mod = VSIM1;
1910DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1911DclPMU_Close(handle);
1912}
1913{
1914DCL_HANDLE handle;
1915PMU_CTRL_LDO_BUCK_SET_EN val;
1916handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1917val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1918val.mod = VSIM2;
1919DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1920DclPMU_Close(handle);
1921}
1922{
1923DCL_HANDLE handle;
1924PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
1925handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1926val.mod=VSIM1;
1927val.voltage = PMU_VOLT_01_800000_V;
1928/* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
1929DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
1930DclPMU_Close(handle);
1931}
1932{
1933DCL_HANDLE handle;
1934PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
1935handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1936val.mod=VSIM2;
1937val.voltage = PMU_VOLT_01_800000_V;
1938/* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
1939DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
1940DclPMU_Close(handle);
1941}
1942{
1943DCL_HANDLE handle;
1944PMU_CTRL_LDO_SET_VTCXO24_SWITCH_EN val;
1945handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1946val.mod = VTCXO24;
1947val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1948DclPMU_Control(handle, LDO_BUCK_SET_VTCXO24_SWITCH, (DCL_CTRL_DATA_T *)&val);
1949DclPMU_Close(handle);
1950}
1951}
1952#endif // End of #if defined(PMIC_UNIT_TEST)
1953
1954#endif // End of #if defined(PMIC_6351_REG_API)
1955