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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / devdrv / pmic / src / dcl_pmic6356.c
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2013
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * dcl_pmic6355_37.c
41 *
42 * Project:
43 * --------
44 * MOLY Software
45 *
46 * Description:
47 * ------------
48 * This file is for PMIC 6355
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
58 * removed!
59 * removed!
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131 *
132 * removed!
133 *------------------------------------------------------------------------------
134 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
135 *============================================================================
136 ****************************************************************************/
137
138#if defined(FPGA_CTP)
139#include <common.h>
140#endif
141
142#include "reg_base.h"
143#include "drv_comm.h"
144#include "init.h"
145#include "dcl.h"
146#include "dcl_pmu_sw.h"
147#include "pmic_wrap.h"
148#include "kal_public_api.h"
149#include "us_timer.h"
150
151#if defined(PMIC_6356_REG_API)
152
153// Start PMIC_UNIT_TEST
154//#define PMIC_UNIT_TEST
155// ARM Section RW/RO/ZI Use Internal SRAM
156#define PMIC_INTERNAL_SRAM
157
158#if !defined(__FUE__)
159#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
160#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
161#else /*defined(__FUE__)*/
162#define SAVEANDSETIRQMASK() 0
163#define RESTOREIRQMASK(mask) {}
164#endif /*defined(__FUE__)*/
165
166#define PMIC_MAX_REG_NUM 0x3a00 // 0x0000~0x3a00
167
168//////////////////////////////////////////////////
169// Exported APIs //
170//////////////////////////////////////////////////
171
172extern DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr);
173extern DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr);
174extern void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val);
175extern void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val);
176extern DCL_BOOL dcl_pmic_init_done_query(void);
177typedef enum
178{
179 AUXADC_READ_INIT = 0,
180 AUXADC_READ_REQUEST = 1,
181 AUXADC_READ_READY = 2,
182 AUXADC_READ_BUSY = 3,
183 AUXADC_READ_DATA = 4
184}AUXADC_FSM;
185
186typedef struct
187{
188 kal_uint32 command_flag;
189 kal_uint32 reg_before_write;
190 kal_uint32 write_value;
191 kal_uint32 address_offset;
192 kal_uint32 reg_mask;
193 kal_uint32 reg_shift;
194 kal_uint32 reg_addr;
195 kal_uint32 reg_data;
196}PMIC_REG_LOG;
197
198AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
199PMIC_REG_LOG pmic_reg_log;
200
201#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
202__attribute__ ((zero_init))
203#endif /* __MTK_TARGET__ */
204
205kal_uint8 pmic_hw_version;
206kal_uint8 pmic_sw_version;
207kal_uint16 pmic_reg[PMIC_MAX_REG_NUM];
208DCL_BOOL pmic_init_done = DCL_FALSE;
209
210kal_spinlockid dcl_pmic_access_spinlock;
211extern kal_spinlockid dcl_pmic_control_spinlock;
212
213const PMIC_FLAG_TABLE_ENTRY pmic_flags_table[] =
214{
215 {MT6356_HWCID, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT, },
216 {MT6356_SWCID, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT, },
217 {MT6356_TOP_CON, PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT, },
218 {MT6356_TOP_CON, PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT, },
219 {MT6356_TOP_CON, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
220 {MT6356_TOP_CON, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
221 {MT6356_BUCK_TOP_ELR1, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_SHIFT, },
222 {MT6356_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_SHIFT, },
223 {MT6356_BUCK_VCORE_CON1, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_SHIFT, },
224 {MT6356_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_MASK, PMIC_DA_VCORE_VOSEL_SHIFT, },
225 {MT6356_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_GRAY_MASK, PMIC_DA_VCORE_VOSEL_GRAY_SHIFT, },
226 {MT6356_BUCK_VCORE_ELR0, PMIC_RG_BUCK_VCORE_VOSEL_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SHIFT, },
227 {MT6356_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_EN_MASK, PMIC_RG_BUCK_VMODEM_EN_SHIFT, },
228 {MT6356_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_LP_MASK, PMIC_RG_BUCK_VMODEM_LP_SHIFT, },
229 {MT6356_BUCK_VMODEM_CON1, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
230 {MT6356_BUCK_VMODEM_ELR0, PMIC_RG_BUCK_VMODEM_VOSEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT, },
231 {MT6356_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
232 {MT6356_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
233 {MT6356_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
234 {MT6356_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
235 {MT6356_BUCK_VMODEM_OP_EN_SET, PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
236 {MT6356_BUCK_VMODEM_OP_EN_CLR, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
237 {MT6356_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
238 {MT6356_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
239 {MT6356_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
240 {MT6356_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_ON_OP_MASK, PMIC_RG_BUCK_VMODEM_ON_OP_SHIFT, },
241 {MT6356_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_LP_OP_MASK, PMIC_RG_BUCK_VMODEM_LP_OP_SHIFT, },
242 {MT6356_BUCK_VMODEM_OP_CFG_SET, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
243 {MT6356_BUCK_VMODEM_OP_CFG_CLR, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
244 {MT6356_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_MASK, PMIC_DA_VMODEM_VOSEL_SHIFT, },
245 {MT6356_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_GRAY_MASK, PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT, },
246 {MT6356_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_EN_MASK, PMIC_DA_VMODEM_EN_SHIFT, },
247 {MT6356_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_STB_MASK, PMIC_DA_VMODEM_STB_SHIFT, },
248 {MT6356_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_VSLEEP_SEL_MASK, PMIC_DA_VMODEM_VSLEEP_SEL_SHIFT, },
249 {MT6356_BUCK_VS1_VOTER, PMIC_RG_BUCK_VS1_VOTER_EN_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT, },
250 {MT6356_BUCK_VS1_VOTER_SET, PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT, },
251 {MT6356_BUCK_VS1_VOTER_CLR, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT, },
252 {MT6356_BUCK_VS1_VOTER_CFG, PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT, },
253 {MT6356_BUCK_VS2_CON1, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VS2_VOSEL_SLEEP_SHIFT, },
254 {MT6356_BUCK_VS2_VOTER, PMIC_RG_BUCK_VS2_VOTER_EN_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SHIFT, },
255 {MT6356_BUCK_VS2_VOTER_SET, PMIC_RG_BUCK_VS2_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_SET_SHIFT, },
256 {MT6356_BUCK_VS2_VOTER_CLR, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS2_VOTER_EN_CLR_SHIFT, },
257 {MT6356_BUCK_VS2_VOTER_CFG, PMIC_RG_BUCK_VS2_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOTER_VOSEL_SHIFT, },
258 {MT6356_BUCK_VS2_ELR0, PMIC_RG_BUCK_VS2_VOSEL_MASK, PMIC_RG_BUCK_VS2_VOSEL_SHIFT, },
259 {MT6356_BUCK_VPA_CON0, PMIC_RG_BUCK_VPA_EN_MASK, PMIC_RG_BUCK_VPA_EN_SHIFT, },
260 {MT6356_BUCK_VPA_CON1, PMIC_RG_BUCK_VPA_VOSEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_SHIFT, },
261 {MT6356_SMPS_ANA_CON1, PMIC_RG_VCORE_SLEEP_VOLTAGE_MASK, PMIC_RG_VCORE_SLEEP_VOLTAGE_SHIFT, },
262 {MT6356_SMPS_ANA_CON1, PMIC_RG_VMODEM_SLEEP_VOLTAGE_MASK, PMIC_RG_VMODEM_SLEEP_VOLTAGE_SHIFT, },
263 {MT6356_VCORE_VPROC_ANA_CON0, PMIC_RG_VCORE_FPWM_MASK, PMIC_RG_VCORE_FPWM_SHIFT, },
264 {MT6356_VCORE_VPROC_ANA_CON0, PMIC_RG_VPROC_FPWM_MASK, PMIC_RG_VPROC_FPWM_SHIFT, },
265 {MT6356_VMODEM_ANA_CON0, PMIC_RG_VMODEM_MODESET_MASK, PMIC_RG_VMODEM_MODESET_SHIFT, },
266 {MT6356_VS2_ANA_CON2, PMIC_RG_VS2_MODESET_MASK, PMIC_RG_VS2_MODESET_SHIFT, },
267 {MT6356_VPA_ANA_CON0, PMIC_RG_VPA_MODESET_MASK, PMIC_RG_VPA_MODESET_SHIFT, },
268 {MT6356_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_EN_MASK, PMIC_RG_LDO_VSIM1_EN_SHIFT, },
269 {MT6356_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_LP_MASK, PMIC_RG_LDO_VSIM1_LP_SHIFT, },
270 {MT6356_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT, },
271 {MT6356_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT, },
272 {MT6356_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT, },
273 {MT6356_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT, },
274 {MT6356_LDO_VSIM1_OP_EN_SET, PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT, },
275 {MT6356_LDO_VSIM1_OP_EN_CLR, PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT, },
276 {MT6356_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT, },
277 {MT6356_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT, },
278 {MT6356_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT, },
279 {MT6356_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_ON_OP_MASK, PMIC_RG_LDO_VSIM1_ON_OP_SHIFT, },
280 {MT6356_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_LP_OP_MASK, PMIC_RG_LDO_VSIM1_LP_OP_SHIFT, },
281 {MT6356_LDO_VSIM1_OP_CFG_SET, PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT, },
282 {MT6356_LDO_VSIM1_OP_CFG_CLR, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT, },
283 {MT6356_LDO_VSIM1_CON2, PMIC_RG_LDO_VSIM1_OCFB_EN_MASK, PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT, },
284 {MT6356_LDO_VSIM1_CON2, PMIC_DA_VSIM1_OCFB_EN_MASK, PMIC_DA_VSIM1_OCFB_EN_SHIFT, },
285 {MT6356_VSIM1_ANA_CON0, PMIC_RG_VSIM1_VOSEL_MASK, PMIC_RG_VSIM1_VOSEL_SHIFT, },
286 {MT6356_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_EN_MASK, PMIC_RG_LDO_VSIM2_EN_SHIFT, },
287 {MT6356_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_LP_MASK, PMIC_RG_LDO_VSIM2_LP_SHIFT, },
288 {MT6356_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT, },
289 {MT6356_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT, },
290 {MT6356_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT, },
291 {MT6356_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT, },
292 {MT6356_LDO_VSIM2_OP_EN_SET, PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT, },
293 {MT6356_LDO_VSIM2_OP_EN_CLR, PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT, },
294 {MT6356_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT, },
295 {MT6356_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT, },
296 {MT6356_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT, },
297 {MT6356_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_ON_OP_MASK, PMIC_RG_LDO_VSIM2_ON_OP_SHIFT, },
298 {MT6356_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_LP_OP_MASK, PMIC_RG_LDO_VSIM2_LP_OP_SHIFT, },
299 {MT6356_LDO_VSIM2_OP_CFG_SET, PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT, },
300 {MT6356_LDO_VSIM2_OP_CFG_CLR, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT, },
301 {MT6356_LDO_VSIM2_CON2, PMIC_RG_LDO_VSIM2_OCFB_EN_MASK, PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT, },
302 {MT6356_LDO_VSIM2_CON2, PMIC_DA_VSIM2_OCFB_EN_MASK, PMIC_DA_VSIM2_OCFB_EN_SHIFT, },
303 {MT6356_VSIM2_ANA_CON0, PMIC_RG_VSIM2_VOSEL_MASK, PMIC_RG_VSIM2_VOSEL_SHIFT, },
304 {MT6356_LDO_VMIPI_CON0, PMIC_RG_LDO_VMIPI_EN_MASK, PMIC_RG_LDO_VMIPI_EN_SHIFT, },
305 {MT6356_LDO_VMIPI_CON0, PMIC_RG_LDO_VMIPI_LP_MASK, PMIC_RG_LDO_VMIPI_LP_SHIFT, },
306 {MT6356_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_SW_OP_EN_MASK, PMIC_RG_LDO_VMIPI_SW_OP_EN_SHIFT, },
307 {MT6356_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW0_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW0_OP_EN_SHIFT, },
308 {MT6356_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW1_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW1_OP_EN_SHIFT, },
309 {MT6356_LDO_VMIPI_OP_EN, PMIC_RG_LDO_VMIPI_HW2_OP_EN_MASK, PMIC_RG_LDO_VMIPI_HW2_OP_EN_SHIFT, },
310 {MT6356_LDO_VMIPI_OP_EN_SET, PMIC_RG_LDO_VMIPI_OP_EN_SET_MASK, PMIC_RG_LDO_VMIPI_OP_EN_SET_SHIFT, },
311 {MT6356_LDO_VMIPI_OP_EN_CLR, PMIC_RG_LDO_VMIPI_OP_EN_CLR_MASK, PMIC_RG_LDO_VMIPI_OP_EN_CLR_SHIFT, },
312 {MT6356_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW0_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW0_OP_CFG_SHIFT, },
313 {MT6356_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW1_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW1_OP_CFG_SHIFT, },
314 {MT6356_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_HW2_OP_CFG_MASK, PMIC_RG_LDO_VMIPI_HW2_OP_CFG_SHIFT, },
315 {MT6356_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_ON_OP_MASK, PMIC_RG_LDO_VMIPI_ON_OP_SHIFT, },
316 {MT6356_LDO_VMIPI_OP_CFG, PMIC_RG_LDO_VMIPI_LP_OP_MASK, PMIC_RG_LDO_VMIPI_LP_OP_SHIFT, },
317 {MT6356_LDO_VMIPI_OP_CFG_SET, PMIC_RG_LDO_VMIPI_OP_CFG_SET_MASK, PMIC_RG_LDO_VMIPI_OP_CFG_SET_SHIFT, },
318 {MT6356_LDO_VMIPI_OP_CFG_CLR, PMIC_RG_LDO_VMIPI_OP_CFG_CLR_MASK, PMIC_RG_LDO_VMIPI_OP_CFG_CLR_SHIFT, },
319 {MT6356_LDO_VMIPI_CON1, PMIC_DA_VMIPI_MODE_MASK, PMIC_DA_VMIPI_MODE_SHIFT, },
320 {MT6356_LDO_VMIPI_CON1, PMIC_DA_VMIPI_EN_MASK, PMIC_DA_VMIPI_EN_SHIFT, },
321 {MT6356_LDO_VMIPI_CON2, PMIC_RG_LDO_VMIPI_OCFB_EN_MASK, PMIC_RG_LDO_VMIPI_OCFB_EN_SHIFT, },
322 {MT6356_LDO_VMIPI_CON2, PMIC_DA_VMIPI_OCFB_EN_MASK, PMIC_DA_VMIPI_OCFB_EN_SHIFT, },
323 {MT6356_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_EN_MASK, PMIC_RG_LDO_VFE28_EN_SHIFT, },
324 {MT6356_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_LP_MASK, PMIC_RG_LDO_VFE28_LP_SHIFT, },
325 {MT6356_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_SW_OP_EN_MASK, PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT, },
326 {MT6356_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT, },
327 {MT6356_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT, },
328 {MT6356_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT, },
329 {MT6356_LDO_VFE28_OP_EN_SET, PMIC_RG_LDO_VFE28_OP_EN_SET_MASK, PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT, },
330 {MT6356_LDO_VFE28_OP_EN_CLR, PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK, PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT, },
331 {MT6356_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT, },
332 {MT6356_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT, },
333 {MT6356_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT, },
334 {MT6356_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_ON_OP_MASK, PMIC_RG_LDO_VFE28_ON_OP_SHIFT, },
335 {MT6356_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_LP_OP_MASK, PMIC_RG_LDO_VFE28_LP_OP_SHIFT, },
336 {MT6356_LDO_VFE28_OP_CFG_SET, PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK, PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT, },
337 {MT6356_LDO_VFE28_OP_CFG_CLR, PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK, PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT, },
338 {MT6356_LDO_VFE28_CON1, PMIC_DA_VFE28_MODE_MASK, PMIC_DA_VFE28_MODE_SHIFT, },
339 {MT6356_LDO_VFE28_CON1, PMIC_DA_VFE28_EN_MASK, PMIC_DA_VFE28_EN_SHIFT, },
340 {MT6356_LDO_VFE28_CON2, PMIC_RG_LDO_VFE28_OCFB_EN_MASK, PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT, },
341 {MT6356_LDO_VFE28_CON2, PMIC_DA_VFE28_OCFB_EN_MASK, PMIC_DA_VFE28_OCFB_EN_SHIFT, },
342 {MT6356_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_EN_MASK, PMIC_RG_LDO_VRF18_EN_SHIFT, },
343 {MT6356_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_LP_MASK, PMIC_RG_LDO_VRF18_LP_SHIFT, },
344 {MT6356_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_SW_OP_EN_SHIFT, },
345 {MT6356_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW0_OP_EN_SHIFT, },
346 {MT6356_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW1_OP_EN_SHIFT, },
347 {MT6356_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW2_OP_EN_SHIFT, },
348 {MT6356_LDO_VRF18_OP_EN_SET, PMIC_RG_LDO_VRF18_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_OP_EN_SET_SHIFT, },
349 {MT6356_LDO_VRF18_OP_EN_CLR, PMIC_RG_LDO_VRF18_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_OP_EN_CLR_SHIFT, },
350 {MT6356_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW0_OP_CFG_SHIFT, },
351 {MT6356_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW1_OP_CFG_SHIFT, },
352 {MT6356_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW2_OP_CFG_SHIFT, },
353 {MT6356_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_ON_OP_MASK, PMIC_RG_LDO_VRF18_ON_OP_SHIFT, },
354 {MT6356_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_LP_OP_MASK, PMIC_RG_LDO_VRF18_LP_OP_SHIFT, },
355 {MT6356_LDO_VRF18_OP_CFG_SET, PMIC_RG_LDO_VRF18_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_OP_CFG_SET_SHIFT, },
356 {MT6356_LDO_VRF18_OP_CFG_CLR, PMIC_RG_LDO_VRF18_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_OP_CFG_CLR_SHIFT, },
357 {MT6356_LDO_VRF18_CON1, PMIC_DA_VRF18_MODE_MASK, PMIC_DA_VRF18_MODE_SHIFT, },
358 {MT6356_LDO_VRF18_CON1, PMIC_DA_VRF18_EN_MASK, PMIC_DA_VRF18_EN_SHIFT, },
359 {MT6356_LDO_VRF18_CON2, PMIC_RG_LDO_VRF18_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_OCFB_EN_SHIFT, },
360 {MT6356_LDO_VRF18_CON2, PMIC_DA_VRF18_OCFB_EN_MASK, PMIC_DA_VRF18_OCFB_EN_SHIFT, },
361 {MT6356_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_EN_MASK, PMIC_RG_LDO_VRF12_EN_SHIFT, },
362 {MT6356_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_LP_MASK, PMIC_RG_LDO_VRF12_LP_SHIFT, },
363 {MT6356_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_SW_OP_EN_MASK, PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT, },
364 {MT6356_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT, },
365 {MT6356_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT, },
366 {MT6356_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT, },
367 {MT6356_LDO_VRF12_OP_EN_SET, PMIC_RG_LDO_VRF12_OP_EN_SET_MASK, PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT, },
368 {MT6356_LDO_VRF12_OP_EN_CLR, PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT, },
369 {MT6356_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT, },
370 {MT6356_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT, },
371 {MT6356_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT, },
372 {MT6356_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_ON_OP_MASK, PMIC_RG_LDO_VRF12_ON_OP_SHIFT, },
373 {MT6356_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_LP_OP_MASK, PMIC_RG_LDO_VRF12_LP_OP_SHIFT, },
374 {MT6356_LDO_VRF12_OP_CFG_SET, PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT, },
375 {MT6356_LDO_VRF12_OP_CFG_CLR, PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT, },
376 {MT6356_LDO_VRF12_CON1, PMIC_DA_VRF12_MODE_MASK, PMIC_DA_VRF12_MODE_SHIFT, },
377 {MT6356_LDO_VRF12_CON1, PMIC_DA_VRF12_EN_MASK, PMIC_DA_VRF12_EN_SHIFT, },
378 {MT6356_LDO_VRF12_CON2, PMIC_RG_LDO_VRF12_OCFB_EN_MASK, PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT, },
379 {MT6356_LDO_VRF12_CON2, PMIC_DA_VRF12_OCFB_EN_MASK, PMIC_DA_VRF12_OCFB_EN_SHIFT, },
380 {MT6356_VXO22_ANA_CON0, PMIC_RG_VXO22_VOSEL_MASK, PMIC_RG_VXO22_VOSEL_SHIFT, },
381 {MT6356_DCXO_CW00, PMIC_XO_EXTBUF1_MODE_MASK, PMIC_XO_EXTBUF1_MODE_SHIFT, },
382 {MT6356_DCXO_CW00, PMIC_XO_EXTBUF1_EN_M_MASK, PMIC_XO_EXTBUF1_EN_M_SHIFT, },
383 {MT6356_DCXO_CW00, PMIC_XO_EXTBUF2_MODE_MASK, PMIC_XO_EXTBUF2_MODE_SHIFT, },
384 {MT6356_DCXO_CW00, PMIC_XO_EXTBUF2_EN_M_MASK, PMIC_XO_EXTBUF2_EN_M_SHIFT, },
385 {MT6356_DCXO_CW00, PMIC_XO_EXTBUF3_MODE_MASK, PMIC_XO_EXTBUF3_MODE_SHIFT, },
386 {MT6356_DCXO_CW00, PMIC_XO_EXTBUF3_EN_M_MASK, PMIC_XO_EXTBUF3_EN_M_SHIFT, },
387 {MT6356_DCXO_CW00, PMIC_XO_EXTBUF4_MODE_MASK, PMIC_XO_EXTBUF4_MODE_SHIFT, },
388 {MT6356_DCXO_CW00, PMIC_XO_EXTBUF4_EN_M_MASK, PMIC_XO_EXTBUF4_EN_M_SHIFT, },
389 {MT6356_DCXO_CW00, PMIC_XO_BB_LPM_EN_MASK, PMIC_XO_BB_LPM_EN_SHIFT, },
390 {MT6356_DCXO_CW00, PMIC_XO_ENBB_MAN_MASK, PMIC_XO_ENBB_MAN_SHIFT, },
391 {MT6356_DCXO_CW00, PMIC_XO_ENBB_EN_M_MASK, PMIC_XO_ENBB_EN_M_SHIFT, },
392 {MT6356_DCXO_CW00, PMIC_XO_CLKSEL_MAN_MASK, PMIC_XO_CLKSEL_MAN_SHIFT, },
393 {MT6356_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_MASK, PMIC_DCXO_CW00_SET_SHIFT, },
394 {MT6356_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_MASK, PMIC_DCXO_CW00_CLR_SHIFT, },
395 {MT6356_DCXO_CW02, PMIC_XO_EN32K_MAN_MASK, PMIC_XO_EN32K_MAN_SHIFT, },
396 {MT6356_DCXO_CW02, PMIC_XO_EN32K_M_MASK, PMIC_XO_EN32K_M_SHIFT, },
397 {MT6356_DCXO_CW02, PMIC_XO_XMODE_MAN_MASK, PMIC_XO_XMODE_MAN_SHIFT, },
398 {MT6356_DCXO_CW02, PMIC_XO_XMODE_M_MASK, PMIC_XO_XMODE_M_SHIFT, },
399 {MT6356_DCXO_CW02, PMIC_XO_STRUP_MODE_MASK, PMIC_XO_STRUP_MODE_SHIFT, },
400 {MT6356_DCXO_CW02, PMIC_XO_AAC_FPM_TIME_MASK, PMIC_XO_AAC_FPM_TIME_SHIFT, },
401 {MT6356_DCXO_CW02, PMIC_XO_AAC_MODE_LPM_MASK, PMIC_XO_AAC_MODE_LPM_SHIFT, },
402 {MT6356_DCXO_CW02, PMIC_XO_AAC_MODE_FPM_MASK, PMIC_XO_AAC_MODE_FPM_SHIFT, },
403 {MT6356_DCXO_CW02, PMIC_XO_EN26M_OFFSQ_EN_MASK, PMIC_XO_EN26M_OFFSQ_EN_SHIFT, },
404 {MT6356_DCXO_CW02, PMIC_XO_LDOCAL_EN_MASK, PMIC_XO_LDOCAL_EN_SHIFT, },
405 {MT6356_DCXO_CW02, PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT, },
406 {MT6356_DCXO_CW02, PMIC_XO_26MLP_MAN_EN_MASK, PMIC_XO_26MLP_MAN_EN_SHIFT, },
407 {MT6356_DCXO_CW02, PMIC_XO_BUFLDOK_EN_MASK, PMIC_XO_BUFLDOK_EN_SHIFT, },
408 {MT6356_DCXO_CW04, PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT, },
409 {MT6356_DCXO_CW04, PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT, },
410 {MT6356_DCXO_CW05, PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT, },
411 {MT6356_DCXO_CW05, PMIC_XO_COFST_FPM_MASK, PMIC_XO_COFST_FPM_SHIFT, },
412 {MT6356_DCXO_CW06, PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT, },
413 {MT6356_DCXO_CW06, PMIC_XO_COFST_LPM_MASK, PMIC_XO_COFST_LPM_SHIFT, },
414 {MT6356_DCXO_CW07, PMIC_XO_CORE_MAN_MASK, PMIC_XO_CORE_MAN_SHIFT, },
415 {MT6356_DCXO_CW07, PMIC_XO_CORE_EN_M_MASK, PMIC_XO_CORE_EN_M_SHIFT, },
416 {MT6356_DCXO_CW07, PMIC_XO_CORE_TURBO_EN_M_MASK, PMIC_XO_CORE_TURBO_EN_M_SHIFT, },
417 {MT6356_DCXO_CW07, PMIC_XO_CORE_AAC_EN_M_MASK, PMIC_XO_CORE_AAC_EN_M_SHIFT, },
418 {MT6356_DCXO_CW07, PMIC_XO_STARTUP_EN_M_MASK, PMIC_XO_STARTUP_EN_M_SHIFT, },
419 {MT6356_DCXO_CW07, PMIC_XO_CORE_VBFPM_EN_M_MASK, PMIC_XO_CORE_VBFPM_EN_M_SHIFT, },
420 {MT6356_DCXO_CW07, PMIC_XO_CORE_VBLPM_EN_M_MASK, PMIC_XO_CORE_VBLPM_EN_M_SHIFT, },
421 {MT6356_DCXO_CW07, PMIC_XO_LPMBIAS_EN_M_MASK, PMIC_XO_LPMBIAS_EN_M_SHIFT, },
422 {MT6356_DCXO_CW07, PMIC_XO_VTCGEN_EN_M_MASK, PMIC_XO_VTCGEN_EN_M_SHIFT, },
423 {MT6356_DCXO_CW07, PMIC_XO_IAAC_COMP_EN_M_MASK, PMIC_XO_IAAC_COMP_EN_M_SHIFT, },
424 {MT6356_DCXO_CW07, PMIC_XO_IFPM_COMP_EN_M_MASK, PMIC_XO_IFPM_COMP_EN_M_SHIFT, },
425 {MT6356_DCXO_CW07, PMIC_XO_ILPM_COMP_EN_M_MASK, PMIC_XO_ILPM_COMP_EN_M_SHIFT, },
426 {MT6356_DCXO_CW07, PMIC_XO_CORE_BYPCAS_FPM_MASK, PMIC_XO_CORE_BYPCAS_FPM_SHIFT, },
427 {MT6356_DCXO_CW07, PMIC_XO_CORE_GMX2_FPM_MASK, PMIC_XO_CORE_GMX2_FPM_SHIFT, },
428 {MT6356_DCXO_CW07, PMIC_XO_CORE_IDAC_FPM_MASK, PMIC_XO_CORE_IDAC_FPM_SHIFT, },
429 {MT6356_DCXO_CW09, PMIC_XO_CORE_BYPCAS_LPM_MASK, PMIC_XO_CORE_BYPCAS_LPM_SHIFT, },
430 {MT6356_DCXO_CW09, PMIC_XO_CORE_GMX2_LPM_MASK, PMIC_XO_CORE_GMX2_LPM_SHIFT, },
431 {MT6356_DCXO_CW09, PMIC_XO_CORE_IDAC_LPM_MASK, PMIC_XO_CORE_IDAC_LPM_SHIFT, },
432 {MT6356_DCXO_CW09, PMIC_XO_AAC_COMP_HV_LPM_MASK, PMIC_XO_AAC_COMP_HV_LPM_SHIFT, },
433 {MT6356_DCXO_CW09, PMIC_XO_AAC_VSEL_LPM_MASK, PMIC_XO_AAC_VSEL_LPM_SHIFT, },
434 {MT6356_DCXO_CW09, PMIC_XO_AAC_HV_LPM_MASK, PMIC_XO_AAC_HV_LPM_SHIFT, },
435 {MT6356_DCXO_CW09, PMIC_XO_AAC_IBIAS_LPM_MASK, PMIC_XO_AAC_IBIAS_LPM_SHIFT, },
436 {MT6356_DCXO_CW09, PMIC_XO_AAC_VOFST_LPM_MASK, PMIC_XO_AAC_VOFST_LPM_SHIFT, },
437 {MT6356_DCXO_CW09, PMIC_XO_AAC_FPM_SWEN_MASK, PMIC_XO_AAC_FPM_SWEN_SHIFT, },
438 {MT6356_DCXO_CW09, PMIC_XO_SWRST_MASK, PMIC_XO_SWRST_SHIFT, },
439 {MT6356_DCXO_CW18, PMIC_XO_STATIC_AUXOUT_SEL_MASK, PMIC_XO_STATIC_AUXOUT_SEL_SHIFT, },
440 {MT6356_DCXO_CW18, PMIC_XO_AUXOUT_SEL_MASK, PMIC_XO_AUXOUT_SEL_SHIFT, },
441 {MT6356_DCXO_CW19, PMIC_XO_STATIC_AUXOUT_MASK, PMIC_XO_STATIC_AUXOUT_SHIFT, },
442 {MT6356_AUXADC_ADC17, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
443 {MT6356_AUXADC_ADC17, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
444 {MT6356_AUXADC_RQST1_SET, PMIC_AUXADC_RQST1_SET_MASK, PMIC_AUXADC_RQST1_SET_SHIFT, },
445 {MT6356_AUXADC_RQST1_CLR, PMIC_AUXADC_RQST1_CLR_MASK, PMIC_AUXADC_RQST1_CLR_SHIFT, },
446};
447#if defined(DCL_PMIC_MODULE_CONTROL)
448DCL_HANDLE current_dcl_handle = 0;
449#endif
450
451//#define DCL_PMIC_PERMISSION_CONTROL
452#if defined(DCL_PMIC_PERMISSION_CONTROL)
453PMU_CTRL_MISC_SET_REGISTER_VALUE illegal_misc_set_register_value = {0};
454#endif
455
456//////////////////////////////////////////////////
457// WRITE APIs //
458//////////////////////////////////////////////////
459#if defined(DCL_PMIC_PERMISSION_CONTROL)
460DCL_BOOL dcl_pmic_check_permission(kal_uint16 offset)
461{
462 DCL_BOOL ret = DCL_FALSE;
463 kal_uint8 c = ((offset>>8) & 0xFF);
464
465 switch(c)
466 {
467 case 0x82:
468 {
469 //CLK : TOP_CLKSQ_SET (0x8226),TOP_CKPDN_CON0_CLR (0x8204),TOP_CLKSQ(0x8224)
470 if(offset == 0x8226 || offset == 0x8204 || offset == 0x8224)
471 ret=DCL_TRUE;
472 }
473 break;
474
475 case 0x90:
476 {
477 //LDO_DIG: 0x901A,0x901C, 0x9006, 0x9008
478 if(offset == 0x901A || offset == 0x901C || offset == 0x9006 || offset == 0x9008)
479 ret=DCL_TRUE;
480 }
481 break;
482
483 case 0x98:
484 {
485 //Audio Analog : 0x9800~0x9852
486 if(offset >= 0x9800 && offset <= 0x9852)
487 ret=DCL_TRUE;
488 }
489 break;
490
491 case 0x9A:
492 {
493 //Audio DRE : 0x9A00 ~0x9A0A
494 if(offset >= 0x9A00 && offset <= 0x9A0A)
495 ret=DCL_TRUE;
496 }
497 break;
498
499 case 0xE0:
500 case 0xE1:
501 {
502 //Audio digital : 0xE000 ~0xE138
503 if(offset >= 0xE000 && offset <= 0xE138)
504 ret=DCL_TRUE;
505 }
506 break;
507
508 default:
509 ret=DCL_FALSE;
510 break;
511 }
512 return ret;
513}
514#endif
515// Write Whole Bytes
516void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
517{
518 DCL_UINT32 idx, type;
519
520 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
521
522 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
523 idx = pmic_access_duration_index[type];
524
525
526#if defined(DCL_PMIC_ACCESS_TIME_LOG)
527 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
528#endif
529 if(addr < PMIC_MAX_REG_NUM)
530 {
531 pmic_reg[addr] = val;
532 }
533
534 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
535
536#if defined(DCL_PMIC_ACCESS_TIME_LOG)
537 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
538 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
539 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
540#endif
541 kal_give_spinlock(dcl_pmic_access_spinlock);
542}
543
544// Write Whole Bytes
545void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val)
546{
547 DCL_UINT32 idx, type;
548
549 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
550 type = PMIC_LOG_TYPE_HRT_DOMAIN;
551 else
552 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
553
554 idx = pmic_access_duration_index[type];
555
556#if defined(DCL_PMIC_ACCESS_TIME_LOG)
557 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
558#endif
559
560
561 if(addr < PMIC_MAX_REG_NUM)
562 {
563 pmic_reg[addr] = val;
564 }
565
566// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
567 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
568// else
569// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
570
571#if defined(DCL_PMIC_ACCESS_TIME_LOG)
572 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
573 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
574 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
575#endif
576
577}
578
579// Write register field
580void dcl_pmic_field_write(PMIC6356_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
581{
582 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
583 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
584 DCL_UINT32 idx = pmic_access_duration_index[type];
585
586 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
587#if defined(DCL_PMIC_ACCESS_TIME_LOG)
588 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
589#endif
590
591 pmic_reg_log.command_flag = flag;
592 pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
593
594 pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
595 pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
596
597// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
598 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
599// else
600// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
601
602 pmic_reg_log.write_value = sel;
603 pmic_reg_log.address_offset = pTable[flag].offset;
604 pmic_reg_log.reg_mask = pTable[flag].mask;
605 pmic_reg_log.reg_shift = pTable[flag].shift;
606 pmic_reg_log.reg_addr = pTable[flag].offset;
607 pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
608
609#if defined(DCL_PMIC_ACCESS_TIME_LOG)
610 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
611 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
612#endif
613
614 kal_give_spinlock(dcl_pmic_access_spinlock);
615}
616
617// Write register field
618void dcl_pmic_field_write_nolock(PMIC6356_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
619{
620 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
621 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
622 DCL_UINT32 idx = pmic_access_duration_index[type];
623
624#if defined(DCL_PMIC_ACCESS_TIME_LOG)
625 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
626#endif
627
628 pmic_reg_log.command_flag = flag;
629 pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
630
631 pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
632 pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
633
634// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
635 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
636// else
637// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
638
639 pmic_reg_log.write_value = sel;
640 pmic_reg_log.address_offset = pTable[flag].offset;
641 pmic_reg_log.reg_mask = pTable[flag].mask;
642 pmic_reg_log.reg_shift = pTable[flag].shift;
643 pmic_reg_log.reg_addr = pTable[flag].offset;
644 pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
645
646#if defined(DCL_PMIC_ACCESS_TIME_LOG)
647 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
648 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
649#endif
650
651}
652//////////////////////////////////////////////////
653// READ APIs //
654//////////////////////////////////////////////////
655
656// Read Whole Bytes
657DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr)
658{
659 DCL_UINT16 reg_temp;
660 DCL_UINT32 idx, type;
661
662 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
663
664 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
665 idx = pmic_access_duration_index[type];
666
667#if defined(DCL_PMIC_ACCESS_TIME_LOG)
668 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
669#endif
670
671// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
672 DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
673// else
674// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
675
676 if(addr < PMIC_MAX_REG_NUM)
677 {
678 pmic_reg[addr] = reg_temp;
679 }
680
681#if defined(DCL_PMIC_ACCESS_TIME_LOG)
682 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
683 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
684#endif
685
686 kal_give_spinlock(dcl_pmic_access_spinlock);
687
688 return reg_temp;
689}
690
691// Read Whole Bytes
692DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr)
693{
694 DCL_UINT16 reg_temp;
695 DCL_UINT32 idx, type;
696
697 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
698 type = PMIC_LOG_TYPE_HRT_DOMAIN;
699 else
700 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
701
702 idx = pmic_access_duration_index[type];
703
704#if defined(DCL_PMIC_ACCESS_TIME_LOG)
705 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
706#endif
707
708// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
709 DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
710// else
711// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
712
713 if(addr < PMIC_MAX_REG_NUM)
714 {
715 pmic_reg[addr] = reg_temp;
716 }
717
718#if defined(DCL_PMIC_ACCESS_TIME_LOG)
719 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
720 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
721#endif
722
723 return reg_temp;
724}
725
726// Read register field
727DCL_UINT16 dcl_pmic_field_read(PMIC6356_FLAGS_LIST_ENUM flag)
728{
729 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
730 DCL_UINT16 reg_return = 0;
731 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
732 DCL_UINT32 idx = pmic_access_duration_index[type];
733
734 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
735 type = PMIC_LOG_TYPE_HRT_DOMAIN;
736 else
737 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
738
739 idx = pmic_access_duration_index[type];
740
741
742#if defined(DCL_PMIC_ACCESS_TIME_LOG)
743 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
744#endif
745
746// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
747 DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
748// else
749// DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
750
751 reg_return = ((pmic_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
752
753#if defined(DCL_PMIC_ACCESS_TIME_LOG)
754 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
755 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
756 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
757#endif
758
759 return reg_return;
760}
761
762// Exported for EM used
763void pmic_EM_reg_write(kal_uint16 reg, kal_uint16 val){
764 dcl_pmic_byte_write_nolock(reg, val);
765// dcl_pmic_byte_write(reg, val);
766}
767
768kal_uint16 pmic_EM_reg_read(kal_uint16 reg){
769 return dcl_pmic_byte_return_nolock(reg);
770}
771
772const DCL_UINT32 vpa_vosel[] =
773{
774 PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
775 PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
776 PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
777 PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
778 PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
779 PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
780 PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
781 PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
782 PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
783 PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
784 PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
785 PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
786 PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
787 PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
788 PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
789 PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
790};
791
792const DCL_UINT32 vsim1_vosel[] =
793{
794 PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V,
795 PMU_VOLT_01_800000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
796 PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V,
797 PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
798};
799
800const DCL_UINT32 vxo22_vosel[] =
801{
802 PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
803 PMU_VOLT_02_200000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
804};
805
806const DCL_UINT32 vmodem_vosel[] =
807{
808 PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_750000_V,
809 PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
810};
811
812#if 0
813/* under construction !*/
814/* under construction !*/
815/* under construction !*/
816/* under construction !*/
817#endif
818
819const DCL_UINT32 vsram_vmd_vosel[] =
820{
821 PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V, PMU_VOLT_00_750000_V,
822 PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
823};
824
825PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
826{
827 {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
828 {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
829 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
830 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
831 {ENC(LDO_BUCK_SET_VOLTAGE, VXO22), vxo22_vosel, NULL, GETARRNUM(vxo22_vosel) },
832 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
833 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_MD), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
834};
835
836
837extern PMU_CONTROL_HANDLER pmu_control_handler;
838
839DCL_UINT16 pmu_parameter_size = 0;
840
841DCL_STATUS PMIC_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
842{
843 DCL_UINT16 regVal;
844 DCL_INT32 return_val = STATUS_FAIL;
845#if defined(DCL_PMIC_MODULE_CONTROL)
846 current_dcl_handle = handle;
847#endif
848 switch(cmd)
849 {
850 case LDO_BUCK_SET_EN: //Enable control in SW mode
851 {
852 PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
853
854 switch(pLdoBuckCtrl->mod)
855 {
856 case VMODEM:
857 {
858 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
859 return_val = STATUS_OK;
860 }
861 break;
862
863 case VPA_SW:
864 {
865 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_EN, pLdoBuckCtrl->enable);
866 return_val = STATUS_OK;
867 }
868 break;
869
870 case VMIPI:
871 {
872 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_EN, pLdoBuckCtrl->enable);
873 return_val = STATUS_OK;
874 }
875 break;
876
877 case VSIM1:
878 {
879 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_EN, pLdoBuckCtrl->enable);
880 return_val = STATUS_OK;
881 }
882 break;
883
884 case VSIM2:
885 {
886 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_EN, pLdoBuckCtrl->enable);
887 return_val = STATUS_OK;
888 }
889 break;
890
891 case VFE28:
892 {
893 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_EN, pLdoBuckCtrl->enable);
894 return_val = STATUS_OK;
895 }
896 break;
897
898 case VRF18:
899 {
900 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_EN, pLdoBuckCtrl->enable);
901 return_val = STATUS_OK;
902 }
903 break;
904
905 case VRF12:
906 {
907 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_EN, pLdoBuckCtrl->enable);
908 return_val = STATUS_OK;
909 }
910 break;
911
912 case VS1:
913 {
914 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_EN, pLdoBuckCtrl->enable);
915 return_val = STATUS_OK;
916 }
917 break;
918
919 case VS2:
920 {
921 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_EN, pLdoBuckCtrl->enable);
922 return_val = STATUS_OK;
923 }
924 break;
925
926 default:
927 return_val = STATUS_UNSUPPORTED;
928 break;
929 }
930 }
931 break;
932
933 case LDO_BUCK_SET_LP_MODE_SET:
934 {
935 PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
936
937 switch(pLdoBuckCtrl->mod)
938 {
939 case VMODEM:
940 { // 1'b0:Normal mode, 1'b1:Low power mode
941 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_LP, pLdoBuckCtrl->enable);
942 return_val = STATUS_OK;
943 }
944 break;
945
946 case VSIM1:
947 { // 1'b0:Normal mode, 1'b1:Low power mode
948 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_LP, pLdoBuckCtrl->enable);
949 return_val = STATUS_OK;
950 }
951 break;
952
953 case VSIM2:
954 { // 1'b0:Normal mode, 1'b1:Low power mode
955 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_LP, pLdoBuckCtrl->enable);
956 return_val = STATUS_OK;
957 }
958 break;
959
960 case VMIPI:
961 { // 1'b0:Normal mode, 1'b1:Low power mode
962 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_LP, pLdoBuckCtrl->enable);
963 return_val = STATUS_OK;
964 }
965 break;
966
967 case VFE28:
968 { // 1'b0:Normal mode, 1'b1:Low power mode
969 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_LP, pLdoBuckCtrl->enable);
970 return_val = STATUS_OK;
971 }
972 break;
973
974 case VRF18:
975 { // 1'b0:Normal mode, 1'b1:Low power mode
976 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_LP, pLdoBuckCtrl->enable);
977 return_val = STATUS_OK;
978 }
979 break;
980
981 case VRF12:
982 { // 1'b0:Normal mode, 1'b1:Low power mode
983 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_LP, pLdoBuckCtrl->enable);
984 return_val = STATUS_OK;
985 }
986 break;
987
988 default:
989 return_val = STATUS_UNSUPPORTED;
990 break;
991 }
992 }
993 break;
994
995 case LDO_BUCK_SET_OCFB_EN:
996 {
997 PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
998
999 switch(pLdoBuckCtrl->mod)
1000 {
1001 case VSIM1:
1002 {
1003 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
1004 return_val = STATUS_OK;
1005 }
1006 break;
1007
1008 case VSIM2:
1009 {
1010 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
1011 return_val = STATUS_OK;
1012 }
1013 break;
1014
1015 default:
1016 return_val = STATUS_UNSUPPORTED;
1017 break;
1018 }
1019 }
1020 break;
1021
1022 case LDO_BUCK_GET_VOSEL:
1023 {
1024 PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
1025
1026 switch(pLdoBuckCtrl->mod)
1027 {
1028 case VMODEM:
1029 {
1030 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL);
1031 return_val = STATUS_OK;
1032 }
1033 break;
1034
1035 case VS1:
1036 {
1037 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL);
1038 return_val = STATUS_OK;
1039 }
1040 break;
1041
1042 case VS2:
1043 {
1044 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL);
1045 return_val = STATUS_OK;
1046 }
1047 break;
1048
1049 default:
1050 return_val = STATUS_UNSUPPORTED;
1051 break;
1052 }
1053 }
1054 break;
1055
1056 case LDO_BUCK_SET_VOSEL:
1057 {
1058 PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
1059
1060 switch(pLdoBuckCtrl->mod)
1061 {
1062 case VMODEM:
1063 {
1064 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
1065 return_val = STATUS_OK;
1066 }
1067 break;
1068
1069 case VS1:
1070 {
1071 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL, pLdoBuckCtrl->code);
1072 return_val = STATUS_OK;
1073 }
1074 break;
1075
1076 case VS2:
1077 {
1078 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS2_VOTER_VOSEL, pLdoBuckCtrl->code);
1079 return_val = STATUS_OK;
1080 }
1081 break;
1082
1083 default:
1084 return_val = STATUS_UNSUPPORTED;
1085 break;
1086 }
1087 }
1088 break;
1089
1090 case LDO_BUCK_GET_VOSEL_SLEEP:
1091 {
1092 PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
1093
1094 switch(pLdoBuckCtrl->mod)
1095 {
1096 case VMODEM:
1097 {
1098 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP);
1099 return_val = STATUS_OK;
1100 }
1101 break;
1102
1103 default:
1104 return_val = STATUS_UNSUPPORTED;
1105 break;
1106 }
1107 }
1108 break;
1109
1110 case LDO_BUCK_SET_VOSEL_SLEEP:
1111 {
1112 PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
1113
1114 switch(pLdoBuckCtrl->mod)
1115 {
1116 case VMODEM:
1117 {
1118 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
1119 return_val = STATUS_OK;
1120 }
1121 break;
1122
1123 default:
1124 return_val = STATUS_UNSUPPORTED;
1125 break;
1126 }
1127 }
1128 break;
1129
1130 case LDO_BUCK_SET_MODESET:
1131 {
1132 PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
1133
1134 switch(pLdoBuckCtrl->mod)
1135 {
1136 case VPA_SW:
1137 {
1138 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VPA_MODESET, pLdoBuckCtrl->mode);
1139 return_val = STATUS_OK;
1140 }
1141 break;
1142
1143 case VMODEM:
1144 {
1145 dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_MODESET, pLdoBuckCtrl->mode);
1146 return_val = STATUS_OK;
1147 }
1148 break;
1149
1150 case VS2:
1151 {
1152 dcl_pmic_field_write(PMIC_ENUM_RG_VS2_MODESET, pLdoBuckCtrl->mode);
1153 return_val = STATUS_OK;
1154 }
1155 break;
1156
1157 default:
1158 return_val = STATUS_UNSUPPORTED;
1159 break;
1160 }
1161 }
1162 break;
1163
1164 case LDO_BUCK_SET_OP_EN:
1165 {
1166 PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
1167
1168 kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
1169 (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
1170
1171 switch(pLdoBuckCtrl->mod)
1172 {
1173 case VMODEM:
1174 {
1175 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_SET_ADDR, mode);
1176 return_val = STATUS_OK;
1177 }
1178 break;
1179
1180 case VSIM1:
1181 {
1182 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_SET_ADDR, mode);
1183 return_val = STATUS_OK;
1184 }
1185 break;
1186
1187 case VSIM2:
1188 {
1189 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_SET_ADDR, mode);
1190 return_val = STATUS_OK;
1191 }
1192 break;
1193
1194 case VMIPI:
1195 {
1196 pmic_EM_reg_write(PMIC_RG_LDO_VMIPI_OP_EN_SET_ADDR, mode);
1197 return_val = STATUS_OK;
1198 }
1199 break;
1200
1201 case VFE28:
1202 {
1203 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_SET_ADDR, mode);
1204 return_val = STATUS_OK;
1205 }
1206 break;
1207
1208 case VRF18:
1209 {
1210 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_SET_ADDR, mode);
1211 return_val = STATUS_OK;
1212 }
1213 break;
1214
1215 case VRF12:
1216 {
1217 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_SET_ADDR, mode);
1218 return_val = STATUS_OK;
1219 }
1220 break;
1221
1222 default:
1223 return_val = STATUS_UNSUPPORTED;
1224 break;
1225 }
1226 }
1227 break;
1228
1229 case LDO_BUCK_CLR_OP_EN:
1230 {
1231 PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
1232
1233 kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
1234 (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
1235
1236 switch(pLdoBuckCtrl->mod)
1237 {
1238 case VMODEM:
1239 {
1240 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_CLR_ADDR, mode);
1241 return_val = STATUS_OK;
1242 }
1243 break;
1244
1245 case VSIM1:
1246 {
1247 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_CLR_ADDR, mode);
1248 return_val = STATUS_OK;
1249 }
1250 break;
1251
1252 case VSIM2:
1253 {
1254 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_CLR_ADDR, mode);
1255 return_val = STATUS_OK;
1256 }
1257 break;
1258
1259 case VMIPI:
1260 {
1261 pmic_EM_reg_write(PMIC_RG_LDO_VMIPI_OP_EN_CLR_ADDR, mode);
1262 return_val = STATUS_OK;
1263 }
1264 break;
1265
1266 case VFE28:
1267 {
1268 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_CLR_ADDR, mode);
1269 return_val = STATUS_OK;
1270 }
1271 break;
1272
1273 case VRF18:
1274 {
1275 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_CLR_ADDR, mode);
1276 return_val = STATUS_OK;
1277 }
1278 break;
1279
1280 case VRF12:
1281 {
1282 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_CLR_ADDR, mode);
1283 return_val = STATUS_OK;
1284 }
1285 break;
1286
1287 default:
1288 return_val = STATUS_UNSUPPORTED;
1289 break;
1290 }
1291 }
1292 break;
1293
1294 case LDO_BUCK_SET_HW_OP_CFG:
1295 {
1296 PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckSetHwOp);
1297
1298 kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
1299 (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
1300 (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
1301
1302 switch(pLdoBuckCtrl->mod)
1303 {
1304 case VMODEM:
1305 {
1306 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_SET_ADDR, value);
1307 return_val = STATUS_OK;
1308 }
1309 break;
1310
1311 case VSIM1:
1312 {
1313 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_SET_ADDR, value);
1314 return_val = STATUS_OK;
1315 }
1316 break;
1317
1318 case VSIM2:
1319 {
1320 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_SET_ADDR, value);
1321 return_val = STATUS_OK;
1322 }
1323 break;
1324
1325 case VMIPI:
1326 {
1327 pmic_EM_reg_write(PMIC_RG_LDO_VMIPI_OP_CFG_SET_ADDR, value);
1328 return_val = STATUS_OK;
1329 }
1330 break;
1331
1332 case VFE28:
1333 {
1334 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_SET_ADDR, value);
1335 return_val = STATUS_OK;
1336 }
1337 break;
1338
1339 case VRF18:
1340 {
1341 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_SET_ADDR, value);
1342 return_val = STATUS_OK;
1343 }
1344 break;
1345
1346 case VRF12:
1347 {
1348 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_SET_ADDR, value);
1349 return_val = STATUS_OK;
1350 }
1351 break;
1352
1353 default:
1354 return_val = STATUS_UNSUPPORTED;
1355 break;
1356 }
1357 }
1358 break;
1359
1360 case LDO_BUCK_CLR_HW_OP_CFG:
1361 {
1362 PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckClrHwOp);
1363
1364 kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
1365 (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
1366 (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
1367
1368 switch(pLdoBuckCtrl->mod)
1369 {
1370 case VMODEM:
1371 {
1372 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_ADDR, value);
1373 return_val = STATUS_OK;
1374 }
1375 break;
1376
1377 case VSIM1:
1378 {
1379 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_CLR_ADDR, value);
1380 return_val = STATUS_OK;
1381 }
1382 break;
1383
1384 case VSIM2:
1385 {
1386 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_CLR_ADDR, value);
1387 return_val = STATUS_OK;
1388 }
1389 break;
1390
1391 case VMIPI:
1392 {
1393 pmic_EM_reg_write(PMIC_RG_LDO_VMIPI_OP_CFG_CLR_ADDR, value);
1394 return_val = STATUS_OK;
1395 }
1396 break;
1397
1398 case VFE28:
1399 {
1400 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_CLR_ADDR, value);
1401 return_val = STATUS_OK;
1402 }
1403 break;
1404
1405 case VRF18:
1406 {
1407 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_CLR_ADDR, value);
1408 return_val = STATUS_OK;
1409 }
1410 break;
1411
1412 case VRF12:
1413 {
1414 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_CLR_ADDR, value);
1415 return_val = STATUS_OK;
1416 }
1417 break;
1418
1419 default:
1420 return_val = STATUS_UNSUPPORTED;
1421 break;
1422 }
1423 }
1424 break;
1425
1426 case LDO_BUCK_SET_GO_ON_OP:
1427 {
1428 PMU_CTRL_LDO_BUCK_SET_GO_ON_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoOnOp);
1429
1430 switch(pLdoBuckCtrl->mod)
1431 {
1432 case VMODEM:
1433 {
1434 if(pLdoBuckCtrl->mode == Prefer_OFF)
1435 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1436 else
1437 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1438 return_val = STATUS_OK;
1439 }
1440 break;
1441
1442 case VSIM1:
1443 {
1444 if(pLdoBuckCtrl->mode == Prefer_OFF)
1445 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1446 else
1447 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1448 return_val = STATUS_OK;
1449 }
1450 break;
1451
1452 case VSIM2:
1453 {
1454 if(pLdoBuckCtrl->mode == Prefer_OFF)
1455 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1456 else
1457 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1458 return_val = STATUS_OK;
1459 }
1460 break;
1461
1462 case VMIPI:
1463 {
1464 if(pLdoBuckCtrl->mode == Prefer_OFF)
1465 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1466 else
1467 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1468 return_val = STATUS_OK;
1469 }
1470 break;
1471
1472 case VFE28:
1473 {
1474 if(pLdoBuckCtrl->mode == Prefer_OFF)
1475 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1476 else
1477 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1478 return_val = STATUS_OK;
1479 }
1480 break;
1481
1482 case VRF18:
1483 {
1484 if(pLdoBuckCtrl->mode == Prefer_OFF)
1485 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1486 else
1487 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1488 return_val = STATUS_OK;
1489 }
1490 break;
1491
1492 case VRF12:
1493 {
1494 if(pLdoBuckCtrl->mode == Prefer_OFF)
1495 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1496 else
1497 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1498 return_val = STATUS_OK;
1499 }
1500 break;
1501
1502 default:
1503 return_val = STATUS_UNSUPPORTED;
1504 break;
1505 }
1506 }
1507 break;
1508
1509 case LDO_BUCK_SET_GO_LP_OP:
1510 {
1511 PMU_CTRL_LDO_BUCK_SET_GO_LP_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoLpOp);
1512
1513 switch(pLdoBuckCtrl->mod)
1514 {
1515 case VMODEM:
1516 {
1517 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1518 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1519 else
1520 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1521 return_val = STATUS_OK;
1522 }
1523 break;
1524
1525 case VSIM1:
1526 {
1527 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1528 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1529 else
1530 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1531 return_val = STATUS_OK;
1532 }
1533 break;
1534
1535 case VSIM2:
1536 {
1537 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1538 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1539 else
1540 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1541 return_val = STATUS_OK;
1542 }
1543 break;
1544
1545 case VMIPI:
1546 {
1547 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1548 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1549 else
1550 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VMIPI_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1551 return_val = STATUS_OK;
1552 }
1553 break;
1554
1555 case VFE28:
1556 {
1557 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1558 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1559 else
1560 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1561 return_val = STATUS_OK;
1562 }
1563 break;
1564
1565 case VRF18:
1566 {
1567 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1568 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1569 else
1570 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1571 return_val = STATUS_OK;
1572 }
1573 break;
1574
1575 case VRF12:
1576 {
1577 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1578 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1579 else
1580 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1581 return_val = STATUS_OK;
1582 }
1583 break;
1584
1585 default:
1586 return_val = STATUS_UNSUPPORTED;
1587 break;
1588 }
1589 }
1590 break;
1591
1592
1593 case LDO_BUCK_SET_VOLTAGE:
1594 {
1595 PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
1596 regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
1597
1598 switch(pLdoBuckCtrl->mod)
1599 {
1600 case VSIM1:
1601 {
1602 dcl_pmic_field_write(PMIC_ENUM_RG_VSIM1_VOSEL, regVal);
1603 return_val = STATUS_OK;
1604 }
1605 break;
1606
1607 case VSIM2:
1608 {
1609 dcl_pmic_field_write(PMIC_ENUM_RG_VSIM2_VOSEL, regVal);
1610 return_val = STATUS_OK;
1611 }
1612 break;
1613
1614 case VPA_SW:
1615 {
1616 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_VOSEL, regVal);
1617 return_val = STATUS_OK;
1618 }
1619 break;
1620
1621 case VXO22:
1622 {
1623 dcl_pmic_field_write(PMIC_ENUM_RG_VXO22_VOSEL, regVal);
1624 return_val = STATUS_OK;
1625 }
1626 break;
1627
1628 default:
1629 return_val = STATUS_UNSUPPORTED;
1630 break;
1631 }
1632 }
1633 break;
1634
1635
1636 case LDO_BUCK_GET_VOLTAGE:
1637 {
1638 PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
1639
1640 switch(pLdoBuckCtrl->mod)
1641 {
1642 case VMODEM:
1643 {
1644 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VMODEM_VOSEL);
1645 return_val = STATUS_OK;
1646 }
1647 break;
1648
1649 default:
1650 return_val = STATUS_UNSUPPORTED;
1651 break;
1652 }
1653 }
1654 break;
1655
1656 case LDO_BUCK_SET_SLEEP_VOLTAGE:
1657 {
1658 PMU_CTRL_LDO_BUCK_SET_SLEEP_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckSetSleepVoltage);
1659 regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->sleepVoltage);
1660
1661 switch(pLdoBuckCtrl->mod)
1662 {
1663 case VCORE:
1664 {
1665 dcl_pmic_field_write(PMIC_ENUM_RG_VCORE_SLEEP_VOLTAGE, regVal);
1666 return_val = STATUS_OK;
1667 }
1668 break;
1669
1670 case VMODEM:
1671 {
1672 dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_SLEEP_VOLTAGE, regVal);
1673 return_val = STATUS_OK;
1674 }
1675 break;
1676
1677 default:
1678 return_val = STATUS_UNSUPPORTED;
1679 break;
1680 }
1681 }
1682 break;
1683
1684 /*
1685 case VPA_SET_EN:
1686 {
1687 PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
1688 dcl_pmic6332_field_write(MT6332_VPA_EN, pVpaSetEn->enable);
1689 return_val = STATUS_OK;
1690 }
1691 break;
1692 */
1693
1694 case VPA_GET_VOLTAGE_LIST:
1695 {
1696 PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
1697 pVpaCtrl->pVoltageList = vpa_vosel;
1698 pVpaCtrl->number = GETARRNUM(vpa_vosel);
1699 return_val = STATUS_OK;
1700 }
1701 break;
1702
1703 case ADC_SET_RQST:
1704 {
1705 PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
1706 if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
1707 {
1708 ASSERT(0);
1709 }
1710 // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
1711 pmic_EM_reg_write(PMIC_TOP_CLKSQ_SET_ADDR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
1712 pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR_ADDR, (pAdcCtrl->enable << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
1713 pmic_EM_reg_write(PMIC_AUXADC_RQST1_SET_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
1714 AUXADC_Status = AUXADC_READ_REQUEST;
1715 return_val = STATUS_OK;
1716 }
1717 break;
1718
1719
1720 case ADC_GET_RDY_MD:
1721 {
1722 PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
1723 pAdcCtrl->status = (DCL_BOOL)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_RDY_CH7_BY_MD);
1724 if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
1725 {
1726 ASSERT(0);
1727 }
1728
1729 if(pAdcCtrl->status == DCL_TRUE)
1730 {
1731 AUXADC_Status = AUXADC_READ_READY;
1732 }
1733 else
1734 {
1735 AUXADC_Status = AUXADC_READ_BUSY;
1736 }
1737
1738 return_val = STATUS_OK;
1739 }
1740 break;
1741
1742 case ADC_GET_OUT_MD:
1743 {
1744 PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
1745 if(AUXADC_Status != AUXADC_READ_READY)
1746 {
1747 ASSERT(0);
1748 }
1749 pAdcCtrl->data = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_OUT_CH7_BY_MD);
1750 AUXADC_Status = AUXADC_READ_DATA;
1751 pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
1752 // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
1753 pmic_EM_reg_write(PMIC_TOP_CLKSQ_CLR_ADDR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
1754
1755 return_val = STATUS_OK;
1756 }
1757 break;
1758
1759 case TOP_SET_SRCLKEN_IN_EN:
1760 {
1761 PMU_CTRL_TOP_SET_SRCLKEN_IN_EN *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInEn);
1762
1763 switch(pTopSrclkenCtrl->mod)
1764 {
1765 case PMIC_SRCLKEN_IN0:
1766 {
1767 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_EN, pTopSrclkenCtrl->mode);
1768 return_val = STATUS_OK;
1769 }
1770 break;
1771
1772 case PMIC_SRCLKEN_IN1:
1773 {
1774 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_EN, pTopSrclkenCtrl->mode);
1775 return_val = STATUS_OK;
1776 }
1777 break;
1778
1779 default:
1780 return_val = STATUS_UNSUPPORTED;
1781 break;
1782 }
1783 }
1784 break;
1785
1786 case TOP_SET_SRCLKEN_IN_MODE:
1787 {
1788 PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInMode);
1789
1790 switch(pTopSrclkenCtrl->mod)
1791 {
1792 case PMIC_SRCLKEN_IN0:
1793 {
1794 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_HW_MODE, pTopSrclkenCtrl->mode);
1795 return_val = STATUS_OK;
1796 }
1797 break;
1798
1799 case PMIC_SRCLKEN_IN1:
1800 {
1801 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_HW_MODE, pTopSrclkenCtrl->mode);
1802 return_val = STATUS_OK;
1803 }
1804 break;
1805
1806 default:
1807 return_val = STATUS_UNSUPPORTED;
1808 break;
1809 }
1810 }
1811 break;
1812
1813 case DCXO_SET_REGISTER_VALUE:
1814 {
1815 PMU_CTRL_DCXO_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUDcxoSetRegisterValue);
1816
1817 pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
1818 return_val = STATUS_OK;
1819
1820#if 0
1821/* under construction !*/
1822/* under construction !*/
1823/* under construction !*/
1824/* under construction !*/
1825/* under construction !*/
1826/* under construction !*/
1827/* under construction !*/
1828/* under construction !*/
1829/* under construction !*/
1830#endif
1831 }
1832 break;
1833
1834 case DCXO_GET_REGISTER_VALUE:
1835 {
1836 PMU_CTRL_DCXO_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUDcxoGetRegisterValue);
1837 pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
1838 return_val = STATUS_OK;
1839 }
1840 break;
1841
1842 case MISC_SET_REGISTER_VALUE:
1843 {
1844 PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
1845#if defined(DCL_PMIC_PERMISSION_CONTROL)
1846 if(dcl_pmic_check_permission(pChrCtrl->offset)== DCL_TRUE)
1847#endif
1848 {
1849 pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
1850 return_val = STATUS_OK;
1851 }
1852#if defined(DCL_PMIC_PERMISSION_CONTROL)
1853 else
1854 {
1855 illegal_misc_set_register_value.offset = pChrCtrl->offset;
1856 illegal_misc_set_register_value.value = pChrCtrl->value;
1857 ASSERT(0);
1858 }
1859#endif
1860 }
1861 break;
1862
1863 case MISC_GET_REGISTER_VALUE:
1864 {
1865 PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
1866 pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
1867 return_val = STATUS_OK;
1868 }
1869 break;
1870
1871 default:
1872 return_val = STATUS_UNSUPPORTED;
1873 break;
1874 }
1875#if defined(DCL_PMIC_MODULE_CONTROL)
1876 current_dcl_handle = 0;
1877#endif
1878 return return_val;
1879
1880}
1881
1882extern void dcl_pmic_modem_only_init(void);
1883extern void PMIC_Read_All(void);
1884#if defined(PMIC_UNIT_TEST)
1885extern void PMIC_Read_All(void);
1886extern void PMIC_Unit_Test(void);
1887#endif
1888DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
1889{
1890 return dcl_pmic_byte_return(pmic_addr);
1891}
1892
1893void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
1894{
1895 dcl_pmic_byte_write(pmic_addr, value);
1896}
1897
1898void dcl_pmic_init(void){
1899 extern void pmic_wrap_dump_init(void);
1900 pmu_control_handler = PMIC_control_handler;
1901 pmu_parameter_size = GETARRNUM(pmu_parameter_table);
1902
1903 pmic_wrap_dump_init();
1904
1905 dcl_pmic_access_spinlock = kal_create_spinlock("pmic access");
1906 dcl_pmic_control_spinlock = kal_create_spinlock("pmic control");
1907
1908#if !defined(__SMART_PHONE_MODEM__)
1909 DrvPWRAP_Init();
1910#endif
1911 pmic_hw_version = dcl_pmic_byte_return(MT6356_HWCID);
1912 if (pmic_hw_version == 0x0)
1913 ASSERT(0);
1914
1915 PMIC_Read_All();
1916
1917#if !defined(__SMART_PHONE_MODEM__)
1918
1919/*
1920 if(DrvPWRAP_CheckCIPHER() == 1)
1921 dcl_pmic6355_modem_only_init();
1922 else
1923*/
1924 dcl_pmic_modem_only_init();
1925
1926#endif
1927
1928#if defined(PMIC_UNIT_TEST)
1929 PMIC_Read_All();
1930 PMIC_Unit_Test();
1931 PMIC_Read_All();
1932#endif
1933 pmic_init_done = DCL_TRUE;
1934
1935}
1936
1937void PMIC_Read_All(void)
1938{
1939 volatile kal_uint32 i,j;
1940 j=0;
1941 for (i = 0; i < PMIC_MAX_REG_NUM; i += 2){
1942 pmic_reg[i] = dcl_pmic_byte_return(i);
1943 while(j!=0x200){j++;}
1944 j=0;
1945 }
1946}
1947#if defined(PMIC_UNIT_TEST)
1948void PMIC_Unit_Test(void)
1949{
1950 {
1951 DCL_HANDLE handle;
1952 PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
1953 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1954 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
1955 val.mod = VMIPI;
1956 DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
1957 DclPMU_Close(handle);
1958 }
1959
1960 {
1961 DCL_HANDLE handle;
1962 PMU_CTRL_LDO_BUCK_SET_EN val;
1963 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1964 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1965 val.mod = VMIPI;
1966 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1967 DclPMU_Close(handle);
1968 }
1969
1970 {
1971 DCL_HANDLE handle;
1972 PMU_CTRL_LDO_BUCK_SET_EN val;
1973 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1974 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
1975 val.mod = VPA_SW;
1976 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
1977 DclPMU_Close(handle);
1978 }
1979
1980 {
1981 DCL_HANDLE handle;
1982 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
1983 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
1984 val.mod=VPA_SW;
1985 val.voltage = PMU_VOLT_01_800000_V;
1986 /* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
1987 PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
1988 PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
1989 PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
1990 PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
1991 PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
1992 PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
1993 PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
1994 PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
1995 PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
1996 PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
1997 PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
1998 PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
1999 PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
2000 PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
2001 PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
2002 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
2003 DclPMU_Close(handle);
2004 }
2005
2006 {
2007 DCL_HANDLE handle;
2008 PMU_CTRL_LDO_BUCK_SET_MODESET val;
2009 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2010 val.mod = VPA_SW;
2011 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
2012 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
2013 DclPMU_Close(handle);
2014 }
2015 {
2016 DCL_HANDLE handle;
2017 PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
2018 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2019 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
2020 val.mod = VRF1;
2021 DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
2022 DclPMU_Close(handle);
2023 }
2024
2025 {
2026 DCL_HANDLE handle;
2027 PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
2028 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2029 val.sel = SRCLKEN_IN1_SEL;
2030 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
2031 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
2032 val.mod = VRF1;
2033 DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
2034 DclPMU_Close(handle);
2035 }
2036
2037 {
2038 DCL_HANDLE handle;
2039 PMU_CTRL_LDO_BUCK_SET_MODESET val;
2040 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2041 val.mod = VRF1;
2042 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
2043 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
2044 DclPMU_Close(handle);
2045 }
2046
2047 {
2048 DCL_HANDLE handle;
2049 PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
2050 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2051 val.regval = 0x7; // (0x0~0xF)
2052 DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
2053 DclPMU_Close(handle);
2054 }
2055
2056 {
2057 DCL_HANDLE handle;
2058 PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
2059 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2060 val.regval = 0x7; // (0x0~0xF)
2061 DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
2062 DclPMU_Close(handle);
2063 }
2064
2065 {
2066 DCL_HANDLE handle;
2067 PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
2068 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2069 // val.regval will be your request value ( no need do any shift)
2070 DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
2071 DclPMU_Close(handle);
2072 }
2073
2074 {
2075 DCL_HANDLE handle;
2076 PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
2077 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2078 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
2079 val.mod = VRF2;
2080 DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
2081 DclPMU_Close(handle);
2082 }
2083
2084 {
2085 DCL_HANDLE handle;
2086 PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
2087 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2088 val.sel = SRCLKEN_IN1_SEL;
2089 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
2090 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
2091 val.mod = VRF2;
2092 DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
2093 DclPMU_Close(handle);
2094 }
2095
2096 {
2097 DCL_HANDLE handle;
2098 PMU_CTRL_LDO_BUCK_SET_EN val;
2099 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2100 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2101 val.mod = VRF2;
2102 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2103 DclPMU_Close(handle);
2104 }
2105
2106 {
2107 DCL_HANDLE handle;
2108 PMU_CTRL_LDO_BUCK_SET_MODESET val;
2109 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2110 val.mod = VRF1;
2111 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
2112 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
2113 DclPMU_Close(handle);
2114 }
2115
2116 {
2117 DCL_HANDLE handle;
2118 PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
2119 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2120 val.sel = SRCLKEN_IN1_SEL;
2121 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
2122 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
2123 val.mod = VMIPI;
2124 DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
2125 DclPMU_Close(handle);
2126 }
2127
2128 {
2129 DCL_HANDLE handle;
2130 PMU_CTRL_LDO_BUCK_SET_EN val;
2131 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2132 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2133 val.mod = VSIM1;
2134 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2135 DclPMU_Close(handle);
2136 }
2137
2138 {
2139 DCL_HANDLE handle;
2140 PMU_CTRL_LDO_BUCK_SET_EN val;
2141 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2142 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2143 val.mod = VSIM2;
2144 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2145 DclPMU_Close(handle);
2146 }
2147
2148 {
2149 DCL_HANDLE handle;
2150 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
2151 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2152 val.mod=VSIM1;
2153 val.voltage = PMU_VOLT_01_800000_V;
2154 /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
2155 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
2156 DclPMU_Close(handle);
2157 }
2158
2159 {
2160 DCL_HANDLE handle;
2161 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
2162 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2163 val.mod=VSIM2;
2164 val.voltage = PMU_VOLT_01_800000_V;
2165 /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
2166 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
2167 DclPMU_Close(handle);
2168 }
2169}
2170#endif // End of #if defined(PMIC_UNIT_TEST)
2171
2172#endif // End of #if defined(PMIC_6356_REG_API)
2173