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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / devdrv / pmic / src / dcl_pmic6357.c
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rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2013
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*****************************************************************************
37 *
38 * Filename:
39 * ---------
40 * dcl_pmic6355_37.c
41 *
42 * Project:
43 * --------
44 * MOLY Software
45 *
46 * Description:
47 * ------------
48 * This file is for PMIC 6355
49 *
50 * Author:
51 * -------
52 * -------
53 *
54 *============================================================================
55 * HISTORY
56 * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
57 *------------------------------------------------------------------------------
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147 *------------------------------------------------------------------------------
148 * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
149 *============================================================================
150 ****************************************************************************/
151
152#if defined(FPGA_CTP)
153#include <common.h>
154#endif
155
156#include "reg_base.h"
157#include "drv_comm.h"
158#include "init.h"
159#include "dcl.h"
160#include "dcl_pmu_sw.h"
161#include "pmic_wrap.h"
162#include "kal_public_api.h"
163#include "us_timer.h"
164
165#if defined(PMIC_6357_REG_API)
166
167// Start PMIC_UNIT_TEST
168//#define PMIC_UNIT_TEST
169// ARM Section RW/RO/ZI Use Internal SRAM
170#define PMIC_INTERNAL_SRAM
171
172#if !defined(__FUE__)
173#define SAVEANDSETIRQMASK() SaveAndSetIRQMask()
174#define RESTOREIRQMASK(mask) RestoreIRQMask(mask)
175#else /*defined(__FUE__)*/
176#define SAVEANDSETIRQMASK() 0
177#define RESTOREIRQMASK(mask) {}
178#endif /*defined(__FUE__)*/
179
180#define PMIC_MAX_REG_NUM 0x3a00 // 0x0000~0x3a00
181
182//////////////////////////////////////////////////
183// Exported APIs //
184//////////////////////////////////////////////////
185
186extern DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr);
187extern DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr);
188extern void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val);
189extern void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val);
190extern DCL_BOOL dcl_pmic_init_done_query(void);
191typedef enum
192{
193 AUXADC_READ_INIT = 0,
194 AUXADC_READ_REQUEST = 1,
195 AUXADC_READ_READY = 2,
196 AUXADC_READ_BUSY = 3,
197 AUXADC_READ_DATA = 4
198}AUXADC_FSM;
199
200typedef struct
201{
202 kal_uint32 command_flag;
203 kal_uint32 reg_before_write;
204 kal_uint32 write_value;
205 kal_uint32 address_offset;
206 kal_uint32 reg_mask;
207 kal_uint32 reg_shift;
208 kal_uint32 reg_addr;
209 kal_uint32 reg_data;
210}PMIC_REG_LOG;
211
212AUXADC_FSM AUXADC_Status = AUXADC_READ_INIT;
213PMIC_REG_LOG pmic_reg_log;
214
215#if (defined(__MTK_TARGET__) && defined(PMIC_INTERNAL_SRAM))
216__attribute__ ((zero_init))
217#endif /* __MTK_TARGET__ */
218
219kal_uint8 pmic_hw_version;
220kal_uint8 pmic_sw_version;
221kal_uint16 pmic_reg[PMIC_MAX_REG_NUM];
222DCL_BOOL pmic_init_done = DCL_FALSE;
223
224kal_spinlockid dcl_pmic_access_spinlock;
225extern kal_spinlockid dcl_pmic_control_spinlock;
226
227const PMIC_FLAG_TABLE_ENTRY pmic_flags_table[] =
228{
229 {MT6357_HWCID, PMIC_HWCID_MASK, PMIC_HWCID_SHIFT, },
230 {MT6357_SWCID, PMIC_SWCID_MASK, PMIC_SWCID_SHIFT, },
231 {MT6357_TOP_CON, PMIC_RG_SRCLKEN_IN0_EN_MASK, PMIC_RG_SRCLKEN_IN0_EN_SHIFT, },
232 {MT6357_TOP_CON, PMIC_RG_SRCLKEN_IN1_EN_MASK, PMIC_RG_SRCLKEN_IN1_EN_SHIFT, },
233 {MT6357_TOP_CON, PMIC_RG_SRCLKEN_IN0_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN0_HW_MODE_SHIFT, },
234 {MT6357_TOP_CON, PMIC_RG_SRCLKEN_IN1_HW_MODE_MASK, PMIC_RG_SRCLKEN_IN1_HW_MODE_SHIFT, },
235 {MT6357_BUCK_TOP_ELR1, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_LIMIT_SEL_SHIFT, },
236 {MT6357_BUCK_TOP_ELR1, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_LIMIT_SEL_SHIFT, },
237 {MT6357_BUCK_VCORE_CON1, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SLEEP_SHIFT, },
238 {MT6357_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_MASK, PMIC_DA_VCORE_VOSEL_SHIFT, },
239 {MT6357_BUCK_VCORE_DBG0, PMIC_DA_VCORE_VOSEL_GRAY_MASK, PMIC_DA_VCORE_VOSEL_GRAY_SHIFT, },
240 {MT6357_BUCK_VCORE_ELR0, PMIC_RG_BUCK_VCORE_VOSEL_MASK, PMIC_RG_BUCK_VCORE_VOSEL_SHIFT, },
241 {MT6357_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_EN_MASK, PMIC_RG_BUCK_VMODEM_EN_SHIFT, },
242 {MT6357_BUCK_VMODEM_CON0, PMIC_RG_BUCK_VMODEM_LP_MASK, PMIC_RG_BUCK_VMODEM_LP_SHIFT, },
243 {MT6357_BUCK_VMODEM_CON1, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SLEEP_SHIFT, },
244 {MT6357_BUCK_VMODEM_ELR0, PMIC_RG_BUCK_VMODEM_VOSEL_MASK, PMIC_RG_BUCK_VMODEM_VOSEL_SHIFT, },
245 {MT6357_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_SW_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_SW_OP_EN_SHIFT, },
246 {MT6357_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_EN_SHIFT, },
247 {MT6357_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_EN_SHIFT, },
248 {MT6357_BUCK_VMODEM_OP_EN, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_EN_SHIFT, },
249 {MT6357_BUCK_VMODEM_OP_EN_SET, PMIC_RG_BUCK_VMODEM_OP_EN_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_SET_SHIFT, },
250 {MT6357_BUCK_VMODEM_OP_EN_CLR, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_EN_CLR_SHIFT, },
251 {MT6357_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW0_OP_CFG_SHIFT, },
252 {MT6357_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW1_OP_CFG_SHIFT, },
253 {MT6357_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_MASK, PMIC_RG_BUCK_VMODEM_HW2_OP_CFG_SHIFT, },
254 {MT6357_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_ON_OP_MASK, PMIC_RG_BUCK_VMODEM_ON_OP_SHIFT, },
255 {MT6357_BUCK_VMODEM_OP_CFG, PMIC_RG_BUCK_VMODEM_LP_OP_MASK, PMIC_RG_BUCK_VMODEM_LP_OP_SHIFT, },
256 {MT6357_BUCK_VMODEM_OP_CFG_SET, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_SET_SHIFT, },
257 {MT6357_BUCK_VMODEM_OP_CFG_CLR, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_MASK, PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_SHIFT, },
258 {MT6357_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_MASK, PMIC_DA_VMODEM_VOSEL_SHIFT, },
259 {MT6357_BUCK_VMODEM_DBG0, PMIC_DA_VMODEM_VOSEL_GRAY_MASK, PMIC_DA_VMODEM_VOSEL_GRAY_SHIFT, },
260 {MT6357_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_EN_MASK, PMIC_DA_VMODEM_EN_SHIFT, },
261 {MT6357_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_STB_MASK, PMIC_DA_VMODEM_STB_SHIFT, },
262 {MT6357_BUCK_VMODEM_DBG1, PMIC_DA_VMODEM_VSLEEP_SEL_MASK, PMIC_DA_VMODEM_VSLEEP_SEL_SHIFT, },
263 {MT6357_BUCK_VS1_VOTER, PMIC_RG_BUCK_VS1_VOTER_EN_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SHIFT, },
264 {MT6357_BUCK_VS1_VOTER_SET, PMIC_RG_BUCK_VS1_VOTER_EN_SET_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_SET_SHIFT, },
265 {MT6357_BUCK_VS1_VOTER_CLR, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_MASK, PMIC_RG_BUCK_VS1_VOTER_EN_CLR_SHIFT, },
266 {MT6357_BUCK_VS1_VOTER_CFG, PMIC_RG_BUCK_VS1_VOTER_VOSEL_MASK, PMIC_RG_BUCK_VS1_VOTER_VOSEL_SHIFT, },
267 {MT6357_BUCK_VPA_CON0, PMIC_RG_BUCK_VPA_EN_MASK, PMIC_RG_BUCK_VPA_EN_SHIFT, },
268 {MT6357_BUCK_VPA_CON1, PMIC_RG_BUCK_VPA_VOSEL_MASK, PMIC_RG_BUCK_VPA_VOSEL_SHIFT, },
269 {MT6357_SMPS_ANA_CON1, PMIC_RG_VCORE_SLEEP_VOLTAGE_MASK, PMIC_RG_VCORE_SLEEP_VOLTAGE_SHIFT, },
270 {MT6357_SMPS_ANA_CON1, PMIC_RG_VMODEM_SLEEP_VOLTAGE_MASK, PMIC_RG_VMODEM_SLEEP_VOLTAGE_SHIFT, },
271 {MT6357_VMODEM_ANA_CON0, PMIC_RG_VMODEM_FPWM_MASK, PMIC_RG_VMODEM_FPWM_SHIFT, },
272 {MT6357_VCORE_VPROC_ANA_CON0, PMIC_RG_VCORE_FPWM_MASK, PMIC_RG_VCORE_FPWM_SHIFT, },
273 {MT6357_VCORE_VPROC_ANA_CON0, PMIC_RG_VPROC_FPWM_MASK, PMIC_RG_VPROC_FPWM_SHIFT, },
274 {MT6357_LDO_VSRAM_CON1, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_MASK, PMIC_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT, },
275 {MT6357_VMODEM_ANA_CON0, PMIC_RG_VMODEM_FCOT_MASK, PMIC_RG_VMODEM_FCOT_SHIFT, },
276 {MT6357_VPA_ANA_CON0, PMIC_RG_VPA_MODESET_MASK, PMIC_RG_VPA_MODESET_SHIFT, },
277 {MT6357_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_EN_MASK, PMIC_RG_LDO_VSIM1_EN_SHIFT, },
278 {MT6357_LDO_VSIM1_CON0, PMIC_RG_LDO_VSIM1_LP_MASK, PMIC_RG_LDO_VSIM1_LP_SHIFT, },
279 {MT6357_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM1_SW_OP_EN_SHIFT, },
280 {MT6357_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_EN_SHIFT, },
281 {MT6357_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_EN_SHIFT, },
282 {MT6357_LDO_VSIM1_OP_EN, PMIC_RG_LDO_VSIM1_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_EN_SHIFT, },
283 {MT6357_LDO_VSIM1_OP_EN_SET, PMIC_RG_LDO_VSIM1_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM1_OP_EN_SET_SHIFT, },
284 {MT6357_LDO_VSIM1_OP_EN_CLR, PMIC_RG_LDO_VSIM1_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_EN_CLR_SHIFT, },
285 {MT6357_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW0_OP_CFG_SHIFT, },
286 {MT6357_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW1_OP_CFG_SHIFT, },
287 {MT6357_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM1_HW2_OP_CFG_SHIFT, },
288// {MT6357_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_ON_OP_MASK, PMIC_RG_LDO_VSIM1_ON_OP_SHIFT, },
289// {MT6357_LDO_VSIM1_OP_CFG, PMIC_RG_LDO_VSIM1_LP_OP_MASK, PMIC_RG_LDO_VSIM1_LP_OP_SHIFT, },
290 {MT6357_LDO_VSIM1_OP_CFG_SET, PMIC_RG_LDO_VSIM1_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_SET_SHIFT, },
291 {MT6357_LDO_VSIM1_OP_CFG_CLR, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM1_OP_CFG_CLR_SHIFT, },
292 {MT6357_LDO_VSIM1_CON2, PMIC_RG_LDO_VSIM1_OCFB_EN_MASK, PMIC_RG_LDO_VSIM1_OCFB_EN_SHIFT, },
293 {MT6357_LDO_VSIM1_CON2, PMIC_DA_VSIM1_OCFB_EN_MASK, PMIC_DA_VSIM1_OCFB_EN_SHIFT, },
294 {MT6357_VSIM1_ANA_CON0, PMIC_RG_VSIM1_VOSEL_MASK, PMIC_RG_VSIM1_VOSEL_SHIFT, },
295 {MT6357_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_EN_MASK, PMIC_RG_LDO_VSIM2_EN_SHIFT, },
296 {MT6357_LDO_VSIM2_CON0, PMIC_RG_LDO_VSIM2_LP_MASK, PMIC_RG_LDO_VSIM2_LP_SHIFT, },
297 {MT6357_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_SW_OP_EN_MASK, PMIC_RG_LDO_VSIM2_SW_OP_EN_SHIFT, },
298 {MT6357_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW0_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_EN_SHIFT, },
299 {MT6357_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW1_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_EN_SHIFT, },
300 {MT6357_LDO_VSIM2_OP_EN, PMIC_RG_LDO_VSIM2_HW2_OP_EN_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_EN_SHIFT, },
301 {MT6357_LDO_VSIM2_OP_EN_SET, PMIC_RG_LDO_VSIM2_OP_EN_SET_MASK, PMIC_RG_LDO_VSIM2_OP_EN_SET_SHIFT, },
302 {MT6357_LDO_VSIM2_OP_EN_CLR, PMIC_RG_LDO_VSIM2_OP_EN_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_EN_CLR_SHIFT, },
303 {MT6357_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW0_OP_CFG_SHIFT, },
304 {MT6357_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW1_OP_CFG_SHIFT, },
305 {MT6357_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_MASK, PMIC_RG_LDO_VSIM2_HW2_OP_CFG_SHIFT, },
306// {MT6357_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_ON_OP_MASK, PMIC_RG_LDO_VSIM2_ON_OP_SHIFT, },
307// {MT6357_LDO_VSIM2_OP_CFG, PMIC_RG_LDO_VSIM2_LP_OP_MASK, PMIC_RG_LDO_VSIM2_LP_OP_SHIFT, },
308 {MT6357_LDO_VSIM2_OP_CFG_SET, PMIC_RG_LDO_VSIM2_OP_CFG_SET_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_SET_SHIFT, },
309 {MT6357_LDO_VSIM2_OP_CFG_CLR, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_MASK, PMIC_RG_LDO_VSIM2_OP_CFG_CLR_SHIFT, },
310 {MT6357_LDO_VSIM2_CON2, PMIC_RG_LDO_VSIM2_OCFB_EN_MASK, PMIC_RG_LDO_VSIM2_OCFB_EN_SHIFT, },
311 {MT6357_LDO_VSIM2_CON2, PMIC_DA_VSIM2_OCFB_EN_MASK, PMIC_DA_VSIM2_OCFB_EN_SHIFT, },
312 {MT6357_VSIM2_ANA_CON0, PMIC_RG_VSIM2_VOSEL_MASK, PMIC_RG_VSIM2_VOSEL_SHIFT, },
313 {MT6357_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_EN_MASK, PMIC_RG_LDO_VFE28_EN_SHIFT, },
314 {MT6357_LDO_VFE28_CON0, PMIC_RG_LDO_VFE28_LP_MASK, PMIC_RG_LDO_VFE28_LP_SHIFT, },
315 {MT6357_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_SW_OP_EN_MASK, PMIC_RG_LDO_VFE28_SW_OP_EN_SHIFT, },
316 {MT6357_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW0_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW0_OP_EN_SHIFT, },
317 {MT6357_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW1_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW1_OP_EN_SHIFT, },
318 {MT6357_LDO_VFE28_OP_EN, PMIC_RG_LDO_VFE28_HW2_OP_EN_MASK, PMIC_RG_LDO_VFE28_HW2_OP_EN_SHIFT, },
319 {MT6357_LDO_VFE28_OP_EN_SET, PMIC_RG_LDO_VFE28_OP_EN_SET_MASK, PMIC_RG_LDO_VFE28_OP_EN_SET_SHIFT, },
320 {MT6357_LDO_VFE28_OP_EN_CLR, PMIC_RG_LDO_VFE28_OP_EN_CLR_MASK, PMIC_RG_LDO_VFE28_OP_EN_CLR_SHIFT, },
321 {MT6357_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW0_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW0_OP_CFG_SHIFT, },
322 {MT6357_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW1_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW1_OP_CFG_SHIFT, },
323 {MT6357_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_HW2_OP_CFG_MASK, PMIC_RG_LDO_VFE28_HW2_OP_CFG_SHIFT, },
324// {MT6357_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_ON_OP_MASK, PMIC_RG_LDO_VFE28_ON_OP_SHIFT, },
325// {MT6357_LDO_VFE28_OP_CFG, PMIC_RG_LDO_VFE28_LP_OP_MASK, PMIC_RG_LDO_VFE28_LP_OP_SHIFT, },
326 {MT6357_LDO_VFE28_OP_CFG_SET, PMIC_RG_LDO_VFE28_OP_CFG_SET_MASK, PMIC_RG_LDO_VFE28_OP_CFG_SET_SHIFT, },
327 {MT6357_LDO_VFE28_OP_CFG_CLR, PMIC_RG_LDO_VFE28_OP_CFG_CLR_MASK, PMIC_RG_LDO_VFE28_OP_CFG_CLR_SHIFT, },
328 {MT6357_LDO_VFE28_CON1, PMIC_DA_VFE28_MODE_MASK, PMIC_DA_VFE28_MODE_SHIFT, },
329 {MT6357_LDO_VFE28_CON1, PMIC_DA_VFE28_EN_MASK, PMIC_DA_VFE28_EN_SHIFT, },
330 {MT6357_LDO_VFE28_CON2, PMIC_RG_LDO_VFE28_OCFB_EN_MASK, PMIC_RG_LDO_VFE28_OCFB_EN_SHIFT, },
331 {MT6357_LDO_VFE28_CON2, PMIC_DA_VFE28_OCFB_EN_MASK, PMIC_DA_VFE28_OCFB_EN_SHIFT, },
332 {MT6357_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_EN_MASK, PMIC_RG_LDO_VRF18_EN_SHIFT, },
333 {MT6357_LDO_VRF18_CON0, PMIC_RG_LDO_VRF18_LP_MASK, PMIC_RG_LDO_VRF18_LP_SHIFT, },
334 {MT6357_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_SW_OP_EN_MASK, PMIC_RG_LDO_VRF18_SW_OP_EN_SHIFT, },
335 {MT6357_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW0_OP_EN_SHIFT, },
336 {MT6357_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW1_OP_EN_SHIFT, },
337 {MT6357_LDO_VRF18_OP_EN, PMIC_RG_LDO_VRF18_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF18_HW2_OP_EN_SHIFT, },
338 {MT6357_LDO_VRF18_OP_EN_SET, PMIC_RG_LDO_VRF18_OP_EN_SET_MASK, PMIC_RG_LDO_VRF18_OP_EN_SET_SHIFT, },
339 {MT6357_LDO_VRF18_OP_EN_CLR, PMIC_RG_LDO_VRF18_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF18_OP_EN_CLR_SHIFT, },
340 {MT6357_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW0_OP_CFG_SHIFT, },
341 {MT6357_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW1_OP_CFG_SHIFT, },
342 {MT6357_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF18_HW2_OP_CFG_SHIFT, },
343// {MT6357_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_ON_OP_MASK, PMIC_RG_LDO_VRF18_ON_OP_SHIFT, },
344// {MT6357_LDO_VRF18_OP_CFG, PMIC_RG_LDO_VRF18_LP_OP_MASK, PMIC_RG_LDO_VRF18_LP_OP_SHIFT, },
345 {MT6357_LDO_VRF18_OP_CFG_SET, PMIC_RG_LDO_VRF18_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF18_OP_CFG_SET_SHIFT, },
346 {MT6357_LDO_VRF18_OP_CFG_CLR, PMIC_RG_LDO_VRF18_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF18_OP_CFG_CLR_SHIFT, },
347 {MT6357_LDO_VRF18_CON1, PMIC_DA_VRF18_MODE_MASK, PMIC_DA_VRF18_MODE_SHIFT, },
348 {MT6357_LDO_VRF18_CON1, PMIC_DA_VRF18_EN_MASK, PMIC_DA_VRF18_EN_SHIFT, },
349 {MT6357_LDO_VRF18_CON2, PMIC_RG_LDO_VRF18_OCFB_EN_MASK, PMIC_RG_LDO_VRF18_OCFB_EN_SHIFT, },
350 {MT6357_LDO_VRF18_CON2, PMIC_DA_VRF18_OCFB_EN_MASK, PMIC_DA_VRF18_OCFB_EN_SHIFT, },
351 {MT6357_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_EN_MASK, PMIC_RG_LDO_VRF12_EN_SHIFT, },
352 {MT6357_LDO_VRF12_CON0, PMIC_RG_LDO_VRF12_LP_MASK, PMIC_RG_LDO_VRF12_LP_SHIFT, },
353 {MT6357_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_SW_OP_EN_MASK, PMIC_RG_LDO_VRF12_SW_OP_EN_SHIFT, },
354 {MT6357_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW0_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW0_OP_EN_SHIFT, },
355 {MT6357_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW1_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW1_OP_EN_SHIFT, },
356 {MT6357_LDO_VRF12_OP_EN, PMIC_RG_LDO_VRF12_HW2_OP_EN_MASK, PMIC_RG_LDO_VRF12_HW2_OP_EN_SHIFT, },
357 {MT6357_LDO_VRF12_OP_EN_SET, PMIC_RG_LDO_VRF12_OP_EN_SET_MASK, PMIC_RG_LDO_VRF12_OP_EN_SET_SHIFT, },
358 {MT6357_LDO_VRF12_OP_EN_CLR, PMIC_RG_LDO_VRF12_OP_EN_CLR_MASK, PMIC_RG_LDO_VRF12_OP_EN_CLR_SHIFT, },
359 {MT6357_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW0_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW0_OP_CFG_SHIFT, },
360 {MT6357_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW1_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW1_OP_CFG_SHIFT, },
361 {MT6357_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_HW2_OP_CFG_MASK, PMIC_RG_LDO_VRF12_HW2_OP_CFG_SHIFT, },
362// {MT6357_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_ON_OP_MASK, PMIC_RG_LDO_VRF12_ON_OP_SHIFT, },
363// {MT6357_LDO_VRF12_OP_CFG, PMIC_RG_LDO_VRF12_LP_OP_MASK, PMIC_RG_LDO_VRF12_LP_OP_SHIFT, },
364 {MT6357_LDO_VRF12_OP_CFG_SET, PMIC_RG_LDO_VRF12_OP_CFG_SET_MASK, PMIC_RG_LDO_VRF12_OP_CFG_SET_SHIFT, },
365 {MT6357_LDO_VRF12_OP_CFG_CLR, PMIC_RG_LDO_VRF12_OP_CFG_CLR_MASK, PMIC_RG_LDO_VRF12_OP_CFG_CLR_SHIFT, },
366 {MT6357_LDO_VRF12_CON1, PMIC_DA_VRF12_MODE_MASK, PMIC_DA_VRF12_MODE_SHIFT, },
367 {MT6357_LDO_VRF12_CON1, PMIC_DA_VRF12_EN_MASK, PMIC_DA_VRF12_EN_SHIFT, },
368 {MT6357_LDO_VRF12_CON2, PMIC_RG_LDO_VRF12_OCFB_EN_MASK, PMIC_RG_LDO_VRF12_OCFB_EN_SHIFT, },
369 {MT6357_LDO_VRF12_CON2, PMIC_DA_VRF12_OCFB_EN_MASK, PMIC_DA_VRF12_OCFB_EN_SHIFT, },
370 {MT6357_VXO22_ANA_CON0, PMIC_RG_VXO22_VOSEL_MASK, PMIC_RG_VXO22_VOSEL_SHIFT, },
371 {MT6357_DCXO_CW00, PMIC_XO_EXTBUF1_MODE_MASK, PMIC_XO_EXTBUF1_MODE_SHIFT, },
372 {MT6357_DCXO_CW00, PMIC_XO_EXTBUF1_EN_M_MASK, PMIC_XO_EXTBUF1_EN_M_SHIFT, },
373 {MT6357_DCXO_CW00, PMIC_XO_EXTBUF2_MODE_MASK, PMIC_XO_EXTBUF2_MODE_SHIFT, },
374 {MT6357_DCXO_CW00, PMIC_XO_EXTBUF2_EN_M_MASK, PMIC_XO_EXTBUF2_EN_M_SHIFT, },
375 {MT6357_DCXO_CW00, PMIC_XO_EXTBUF3_MODE_MASK, PMIC_XO_EXTBUF3_MODE_SHIFT, },
376 {MT6357_DCXO_CW00, PMIC_XO_EXTBUF3_EN_M_MASK, PMIC_XO_EXTBUF3_EN_M_SHIFT, },
377 {MT6357_DCXO_CW00, PMIC_XO_EXTBUF4_MODE_MASK, PMIC_XO_EXTBUF4_MODE_SHIFT, },
378 {MT6357_DCXO_CW00, PMIC_XO_EXTBUF4_EN_M_MASK, PMIC_XO_EXTBUF4_EN_M_SHIFT, },
379 {MT6357_DCXO_CW00, PMIC_XO_BB_LPM_EN_MASK, PMIC_XO_BB_LPM_EN_SHIFT, },
380 {MT6357_DCXO_CW00, PMIC_XO_ENBB_MAN_MASK, PMIC_XO_ENBB_MAN_SHIFT, },
381 {MT6357_DCXO_CW00, PMIC_XO_ENBB_EN_M_MASK, PMIC_XO_ENBB_EN_M_SHIFT, },
382 {MT6357_DCXO_CW00, PMIC_XO_CLKSEL_MAN_MASK, PMIC_XO_CLKSEL_MAN_SHIFT, },
383 {MT6357_DCXO_CW00_SET, PMIC_DCXO_CW00_SET_MASK, PMIC_DCXO_CW00_SET_SHIFT, },
384 {MT6357_DCXO_CW00_CLR, PMIC_DCXO_CW00_CLR_MASK, PMIC_DCXO_CW00_CLR_SHIFT, },
385 {MT6357_DCXO_CW02, PMIC_XO_EN32K_MAN_MASK, PMIC_XO_EN32K_MAN_SHIFT, },
386 {MT6357_DCXO_CW02, PMIC_XO_EN32K_M_MASK, PMIC_XO_EN32K_M_SHIFT, },
387 {MT6357_DCXO_CW02, PMIC_XO_XMODE_MAN_MASK, PMIC_XO_XMODE_MAN_SHIFT, },
388 {MT6357_DCXO_CW02, PMIC_XO_XMODE_M_MASK, PMIC_XO_XMODE_M_SHIFT, },
389 {MT6357_DCXO_CW02, PMIC_XO_STRUP_MODE_MASK, PMIC_XO_STRUP_MODE_SHIFT, },
390 {MT6357_DCXO_CW02, PMIC_XO_AAC_FPM_TIME_MASK, PMIC_XO_AAC_FPM_TIME_SHIFT, },
391 {MT6357_DCXO_CW02, PMIC_XO_AAC_MODE_LPM_MASK, PMIC_XO_AAC_MODE_LPM_SHIFT, },
392 {MT6357_DCXO_CW02, PMIC_XO_AAC_MODE_FPM_MASK, PMIC_XO_AAC_MODE_FPM_SHIFT, },
393 {MT6357_DCXO_CW02, PMIC_XO_EN26M_OFFSQ_EN_MASK, PMIC_XO_EN26M_OFFSQ_EN_SHIFT, },
394 {MT6357_DCXO_CW02, PMIC_XO_LDOCAL_EN_MASK, PMIC_XO_LDOCAL_EN_SHIFT, },
395 {MT6357_DCXO_CW02, PMIC_XO_CBANK_SYNC_DYN_MASK, PMIC_XO_CBANK_SYNC_DYN_SHIFT, },
396 {MT6357_DCXO_CW02, PMIC_XO_26MLP_MAN_EN_MASK, PMIC_XO_26MLP_MAN_EN_SHIFT, },
397 {MT6357_DCXO_CW02, PMIC_XO_BUFLDOK_EN_MASK, PMIC_XO_BUFLDOK_EN_SHIFT, },
398 {MT6357_DCXO_CW04, PMIC_XO_CDAC_FPM_MASK, PMIC_XO_CDAC_FPM_SHIFT, },
399 {MT6357_DCXO_CW04, PMIC_XO_CDAC_LPM_MASK, PMIC_XO_CDAC_LPM_SHIFT, },
400 {MT6357_DCXO_CW05, PMIC_XO_32KDIV_NFRAC_FPM_MASK, PMIC_XO_32KDIV_NFRAC_FPM_SHIFT, },
401 {MT6357_DCXO_CW05, PMIC_XO_COFST_FPM_MASK, PMIC_XO_COFST_FPM_SHIFT, },
402 {MT6357_DCXO_CW06, PMIC_XO_32KDIV_NFRAC_LPM_MASK, PMIC_XO_32KDIV_NFRAC_LPM_SHIFT, },
403 {MT6357_DCXO_CW06, PMIC_XO_COFST_LPM_MASK, PMIC_XO_COFST_LPM_SHIFT, },
404 {MT6357_DCXO_CW07, PMIC_XO_CORE_MAN_MASK, PMIC_XO_CORE_MAN_SHIFT, },
405 {MT6357_DCXO_CW07, PMIC_XO_CORE_EN_M_MASK, PMIC_XO_CORE_EN_M_SHIFT, },
406 {MT6357_DCXO_CW07, PMIC_XO_CORE_TURBO_EN_M_MASK, PMIC_XO_CORE_TURBO_EN_M_SHIFT, },
407 {MT6357_DCXO_CW07, PMIC_XO_CORE_AAC_EN_M_MASK, PMIC_XO_CORE_AAC_EN_M_SHIFT, },
408 {MT6357_DCXO_CW07, PMIC_XO_STARTUP_EN_M_MASK, PMIC_XO_STARTUP_EN_M_SHIFT, },
409 {MT6357_DCXO_CW07, PMIC_XO_CORE_VBFPM_EN_M_MASK, PMIC_XO_CORE_VBFPM_EN_M_SHIFT, },
410 {MT6357_DCXO_CW07, PMIC_XO_CORE_VBLPM_EN_M_MASK, PMIC_XO_CORE_VBLPM_EN_M_SHIFT, },
411 {MT6357_DCXO_CW07, PMIC_XO_LPMBIAS_EN_M_MASK, PMIC_XO_LPMBIAS_EN_M_SHIFT, },
412 {MT6357_DCXO_CW07, PMIC_XO_VTCGEN_EN_M_MASK, PMIC_XO_VTCGEN_EN_M_SHIFT, },
413 {MT6357_DCXO_CW07, PMIC_XO_IAAC_COMP_EN_M_MASK, PMIC_XO_IAAC_COMP_EN_M_SHIFT, },
414 {MT6357_DCXO_CW07, PMIC_XO_IFPM_COMP_EN_M_MASK, PMIC_XO_IFPM_COMP_EN_M_SHIFT, },
415 {MT6357_DCXO_CW07, PMIC_XO_ILPM_COMP_EN_M_MASK, PMIC_XO_ILPM_COMP_EN_M_SHIFT, },
416 {MT6357_DCXO_CW07, PMIC_XO_CORE_BYPCAS_FPM_MASK, PMIC_XO_CORE_BYPCAS_FPM_SHIFT, },
417 {MT6357_DCXO_CW07, PMIC_XO_CORE_GMX2_FPM_MASK, PMIC_XO_CORE_GMX2_FPM_SHIFT, },
418 {MT6357_DCXO_CW07, PMIC_XO_CORE_IDAC_FPM_MASK, PMIC_XO_CORE_IDAC_FPM_SHIFT, },
419 {MT6357_DCXO_CW09, PMIC_XO_CORE_BYPCAS_LPM_MASK, PMIC_XO_CORE_BYPCAS_LPM_SHIFT, },
420 {MT6357_DCXO_CW09, PMIC_XO_CORE_GMX2_LPM_MASK, PMIC_XO_CORE_GMX2_LPM_SHIFT, },
421 {MT6357_DCXO_CW09, PMIC_XO_CORE_IDAC_LPM_MASK, PMIC_XO_CORE_IDAC_LPM_SHIFT, },
422 {MT6357_DCXO_CW09, PMIC_XO_AAC_COMP_HV_LPM_MASK, PMIC_XO_AAC_COMP_HV_LPM_SHIFT, },
423 {MT6357_DCXO_CW09, PMIC_XO_AAC_VSEL_LPM_MASK, PMIC_XO_AAC_VSEL_LPM_SHIFT, },
424 {MT6357_DCXO_CW09, PMIC_XO_AAC_HV_LPM_MASK, PMIC_XO_AAC_HV_LPM_SHIFT, },
425 {MT6357_DCXO_CW09, PMIC_XO_AAC_IBIAS_LPM_MASK, PMIC_XO_AAC_IBIAS_LPM_SHIFT, },
426 {MT6357_DCXO_CW09, PMIC_XO_AAC_VOFST_LPM_MASK, PMIC_XO_AAC_VOFST_LPM_SHIFT, },
427 {MT6357_DCXO_CW09, PMIC_XO_AAC_FPM_SWEN_MASK, PMIC_XO_AAC_FPM_SWEN_SHIFT, },
428 {MT6357_DCXO_CW09, PMIC_XO_SWRST_MASK, PMIC_XO_SWRST_SHIFT, },
429 {MT6357_DCXO_CW18, PMIC_XO_STATIC_AUXOUT_SEL_MASK, PMIC_XO_STATIC_AUXOUT_SEL_SHIFT, },
430 {MT6357_DCXO_CW18, PMIC_XO_AUXOUT_SEL_MASK, PMIC_XO_AUXOUT_SEL_SHIFT, },
431 {MT6357_DCXO_CW19, PMIC_XO_STATIC_AUXOUT_MASK, PMIC_XO_STATIC_AUXOUT_SHIFT, },
432 {MT6357_AUXADC_ADC17, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_OUT_CH7_BY_MD_SHIFT, },
433 {MT6357_AUXADC_ADC17, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_MASK, PMIC_AUXADC_ADC_RDY_CH7_BY_MD_SHIFT, },
434 {MT6357_AUXADC_RQST1_SET, PMIC_AUXADC_RQST1_SET_MASK, PMIC_AUXADC_RQST1_SET_SHIFT, },
435 {MT6357_AUXADC_RQST1_CLR, PMIC_AUXADC_RQST1_CLR_MASK, PMIC_AUXADC_RQST1_CLR_SHIFT, },
436 {MT6357_VRF18_ANA_CON0, PMIC_RG_VRF18_VOCAL_MASK, PMIC_RG_VRF18_VOCAL_SHIFT, },
437 {MT6357_VRF12_ANA_CON0, PMIC_RG_VRF12_VOCAL_MASK, PMIC_RG_VRF12_VOCAL_SHIFT, },
438 {MT6357_VRF18_ELR_0, PMIC_RG_VRF18_VOTRIM_MASK, PMIC_RG_VRF18_VOTRIM_SHIFT, },
439 {MT6357_VRF12_ELR_0, PMIC_RG_VRF12_VOTRIM_MASK, PMIC_RG_VRF12_VOTRIM_SHIFT, },
440 {MT6357_BUCK_TOP_OC_CON0, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_MASK, PMIC_RG_BUCK_VPA_OC_SDN_STATUS_SHIFT, },
441};
442#if defined(DCL_PMIC_MODULE_CONTROL)
443DCL_HANDLE current_dcl_handle = 0;
444#endif
445
446//#define DCL_PMIC_PERMISSION_CONTROL
447#if defined(DCL_PMIC_PERMISSION_CONTROL)
448PMU_CTRL_MISC_SET_REGISTER_VALUE illegal_misc_set_register_value = {0};
449#endif
450
451//////////////////////////////////////////////////
452// WRITE APIs //
453//////////////////////////////////////////////////
454#if defined(DCL_PMIC_PERMISSION_CONTROL)
455DCL_BOOL dcl_pmic_check_permission(kal_uint16 offset)
456{
457 DCL_BOOL ret = DCL_FALSE;
458 kal_uint8 c = ((offset>>8) & 0xFF);
459
460 switch(c)
461 {
462 case 0x82:
463 {
464 //CLK : TOP_CLKSQ_SET (0x8226),TOP_CKPDN_CON0_CLR (0x8204),TOP_CLKSQ(0x8224)
465 if(offset == 0x8226 || offset == 0x8204 || offset == 0x8224)
466 ret=DCL_TRUE;
467 }
468 break;
469
470 case 0x90:
471 {
472 //LDO_DIG: 0x901A,0x901C, 0x9006, 0x9008
473 if(offset == 0x901A || offset == 0x901C || offset == 0x9006 || offset == 0x9008)
474 ret=DCL_TRUE;
475 }
476 break;
477
478 case 0x98:
479 {
480 //Audio Analog : 0x9800~0x9852
481 if(offset >= 0x9800 && offset <= 0x9852)
482 ret=DCL_TRUE;
483 }
484 break;
485
486 case 0x9A:
487 {
488 //Audio DRE : 0x9A00 ~0x9A0A
489 if(offset >= 0x9A00 && offset <= 0x9A0A)
490 ret=DCL_TRUE;
491 }
492 break;
493
494 case 0xE0:
495 case 0xE1:
496 {
497 //Audio digital : 0xE000 ~0xE138
498 if(offset >= 0xE000 && offset <= 0xE138)
499 ret=DCL_TRUE;
500 }
501 break;
502
503 default:
504 ret=DCL_FALSE;
505 break;
506 }
507 return ret;
508}
509#endif
510// Write Whole Bytes
511void dcl_pmic_byte_write(DCL_UINT16 addr, DCL_UINT16 val)
512{
513 DCL_UINT32 idx, type;
514
515 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
516
517 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
518 idx = pmic_access_duration_index[type];
519
520
521#if defined(DCL_PMIC_ACCESS_TIME_LOG)
522 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
523#endif
524 if(addr < PMIC_MAX_REG_NUM)
525 {
526 pmic_reg[addr] = val;
527 }
528
529 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
530
531#if defined(DCL_PMIC_ACCESS_TIME_LOG)
532 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
533 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
534 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
535#endif
536 kal_give_spinlock(dcl_pmic_access_spinlock);
537}
538
539// Write Whole Bytes
540void dcl_pmic_byte_write_nolock(DCL_UINT16 addr, DCL_UINT16 val)
541{
542 DCL_UINT32 idx, type;
543
544 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
545 type = PMIC_LOG_TYPE_HRT_DOMAIN;
546 else
547 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
548
549 idx = pmic_access_duration_index[type];
550
551#if defined(DCL_PMIC_ACCESS_TIME_LOG)
552 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
553#endif
554
555
556 if(addr < PMIC_MAX_REG_NUM)
557 {
558 pmic_reg[addr] = val;
559 }
560
561// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
562 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
563// else
564// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, addr, val, 0x00);
565
566#if defined(DCL_PMIC_ACCESS_TIME_LOG)
567 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
568 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
569 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
570#endif
571
572}
573
574// Write register field
575void dcl_pmic_field_write(PMIC6357_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
576{
577 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
578 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
579 DCL_UINT32 idx = pmic_access_duration_index[type];
580
581 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
582#if defined(DCL_PMIC_ACCESS_TIME_LOG)
583 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
584#endif
585
586 pmic_reg_log.command_flag = flag;
587 pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
588
589 pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
590 pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
591
592// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
593 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
594// else
595// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
596
597 pmic_reg_log.write_value = sel;
598 pmic_reg_log.address_offset = pTable[flag].offset;
599 pmic_reg_log.reg_mask = pTable[flag].mask;
600 pmic_reg_log.reg_shift = pTable[flag].shift;
601 pmic_reg_log.reg_addr = pTable[flag].offset;
602 pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
603
604#if defined(DCL_PMIC_ACCESS_TIME_LOG)
605 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
606 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
607#endif
608
609 kal_give_spinlock(dcl_pmic_access_spinlock);
610}
611
612// Write register field
613void dcl_pmic_field_write_nolock(PMIC6357_FLAGS_LIST_ENUM flag, DCL_UINT16 sel)
614{
615 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
616 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
617 DCL_UINT32 idx = pmic_access_duration_index[type];
618
619#if defined(DCL_PMIC_ACCESS_TIME_LOG)
620 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
621#endif
622
623 pmic_reg_log.command_flag = flag;
624 pmic_reg_log.reg_before_write = pmic_reg[pTable[flag].offset];
625
626 pmic_reg[pTable[flag].offset] &= ~(pTable[flag].mask << pTable[flag].shift);
627 pmic_reg[pTable[flag].offset] |= ((kal_uint16)sel << pTable[flag].shift);
628
629// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
630 DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
631// else
632// DrvPWRAP_WACS0(PMIC_WRAP_WRITE, pTable[flag].offset, pmic_reg[pTable[flag].offset], 0x00);
633
634 pmic_reg_log.write_value = sel;
635 pmic_reg_log.address_offset = pTable[flag].offset;
636 pmic_reg_log.reg_mask = pTable[flag].mask;
637 pmic_reg_log.reg_shift = pTable[flag].shift;
638 pmic_reg_log.reg_addr = pTable[flag].offset;
639 pmic_reg_log.reg_data = pmic_reg[pTable[flag].offset];
640
641#if defined(DCL_PMIC_ACCESS_TIME_LOG)
642 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
643 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
644#endif
645
646}
647//////////////////////////////////////////////////
648// READ APIs //
649//////////////////////////////////////////////////
650
651// Read Whole Bytes
652DCL_UINT16 dcl_pmic_byte_return(DCL_UINT16 addr)
653{
654 DCL_UINT16 reg_temp;
655 DCL_UINT32 idx, type;
656
657 kal_take_spinlock(dcl_pmic_access_spinlock, KAL_INFINITE_WAIT);
658
659 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
660 idx = pmic_access_duration_index[type];
661
662#if defined(DCL_PMIC_ACCESS_TIME_LOG)
663 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
664#endif
665
666// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
667 DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
668// else
669// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
670
671 if(addr < PMIC_MAX_REG_NUM)
672 {
673 pmic_reg[addr] = reg_temp;
674 }
675
676#if defined(DCL_PMIC_ACCESS_TIME_LOG)
677 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
678 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
679#endif
680
681 kal_give_spinlock(dcl_pmic_access_spinlock);
682
683 return reg_temp;
684}
685
686// Read Whole Bytes
687DCL_UINT16 dcl_pmic_byte_return_nolock(DCL_UINT16 addr)
688{
689 DCL_UINT16 reg_temp;
690 DCL_UINT32 idx, type;
691
692 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
693 type = PMIC_LOG_TYPE_HRT_DOMAIN;
694 else
695 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
696
697 idx = pmic_access_duration_index[type];
698
699#if defined(DCL_PMIC_ACCESS_TIME_LOG)
700 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
701#endif
702
703// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
704 DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
705// else
706// DrvPWRAP_WACS0(PMIC_WRAP_READ, (DCL_UINT32)addr, 0x00, &reg_temp);
707
708 if(addr < PMIC_MAX_REG_NUM)
709 {
710 pmic_reg[addr] = reg_temp;
711 }
712
713#if defined(DCL_PMIC_ACCESS_TIME_LOG)
714 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
715 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time, pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
716#endif
717
718 return reg_temp;
719}
720
721// Read register field
722DCL_UINT16 dcl_pmic_field_read(PMIC6357_FLAGS_LIST_ENUM flag)
723{
724 const PMIC_FLAG_TABLE_ENTRY *pTable = pmic_flags_table;
725 DCL_UINT16 reg_return = 0;
726 DCL_UINT32 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
727 DCL_UINT32 idx = pmic_access_duration_index[type];
728
729 if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
730 type = PMIC_LOG_TYPE_HRT_DOMAIN;
731 else
732 type = PMIC_LOG_TYPE_NORMAL_DOMAIN;
733
734 idx = pmic_access_duration_index[type];
735
736
737#if defined(DCL_PMIC_ACCESS_TIME_LOG)
738 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time = ust_get_current_time();
739#endif
740
741// if( DclPMU_GetHrtFlag()!= 0) //if(HRT)
742 DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
743// else
744// DrvPWRAP_WACS0(PMIC_WRAP_READ, pTable[flag].offset, 0x00, &pmic_reg[pTable[flag].offset]);
745
746 reg_return = ((pmic_reg[pTable[flag].offset] & (pTable[flag].mask << pTable[flag].shift)) >> pTable[flag].shift);
747
748#if defined(DCL_PMIC_ACCESS_TIME_LOG)
749 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time = ust_get_current_time();
750 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].duration_time = ust_us_duration(pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].start_time,
751 pmic_access_duration_log[type][PMIC_INTERFACE_DBG][idx].end_time);
752#endif
753
754 return reg_return;
755}
756
757// Exported for EM used
758void pmic_EM_reg_write(kal_uint16 reg, kal_uint16 val){
759 dcl_pmic_byte_write_nolock(reg, val);
760// dcl_pmic_byte_write(reg, val);
761}
762
763kal_uint16 pmic_EM_reg_read(kal_uint16 reg){
764 return dcl_pmic_byte_return_nolock(reg);
765}
766
767const DCL_UINT32 vpa_vosel[] =
768{
769 PMU_VOLT_00_500000_V, PMU_VOLT_INVALID, PMU_VOLT_00_600000_V, PMU_VOLT_INVALID,
770 PMU_VOLT_00_700000_V, PMU_VOLT_INVALID, PMU_VOLT_00_800000_V, PMU_VOLT_INVALID,
771 PMU_VOLT_00_900000_V, PMU_VOLT_INVALID, PMU_VOLT_01_000000_V, PMU_VOLT_INVALID,
772 PMU_VOLT_01_100000_V, PMU_VOLT_INVALID, PMU_VOLT_01_200000_V, PMU_VOLT_INVALID,
773 PMU_VOLT_01_300000_V, PMU_VOLT_INVALID, PMU_VOLT_01_400000_V, PMU_VOLT_INVALID,
774 PMU_VOLT_01_500000_V, PMU_VOLT_INVALID, PMU_VOLT_01_600000_V, PMU_VOLT_INVALID,
775 PMU_VOLT_01_700000_V, PMU_VOLT_INVALID, PMU_VOLT_01_800000_V, PMU_VOLT_INVALID,
776 PMU_VOLT_01_900000_V, PMU_VOLT_INVALID, PMU_VOLT_02_000000_V, PMU_VOLT_INVALID,
777 PMU_VOLT_02_100000_V, PMU_VOLT_INVALID, PMU_VOLT_02_200000_V, PMU_VOLT_INVALID,
778 PMU_VOLT_02_300000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
779 PMU_VOLT_02_500000_V, PMU_VOLT_INVALID, PMU_VOLT_02_600000_V, PMU_VOLT_INVALID,
780 PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_02_800000_V, PMU_VOLT_INVALID,
781 PMU_VOLT_02_900000_V, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V, PMU_VOLT_INVALID,
782 PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_03_200000_V, PMU_VOLT_INVALID,
783 PMU_VOLT_03_300000_V, PMU_VOLT_INVALID, PMU_VOLT_03_400000_V, PMU_VOLT_INVALID,
784 PMU_VOLT_03_500000_V, PMU_VOLT_INVALID, PMU_VOLT_03_600000_V, PMU_VOLT_INVALID,
785};
786
787const DCL_UINT32 vsim1_vosel[] =
788{
789 PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_01_700000_V,
790 PMU_VOLT_01_800000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
791 PMU_VOLT_02_700000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_03_000000_V,
792 PMU_VOLT_03_100000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
793};
794
795const DCL_UINT32 vxo22_vosel[] =
796{
797 PMU_VOLT_02_200000_V, PMU_VOLT_INVALID, PMU_VOLT_02_400000_V, PMU_VOLT_INVALID,
798 PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
799};
800
801const DCL_UINT32 vmodem_vosel[] =
802{
803 PMU_VOLT_00_500000_V, PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_750000_V,
804 PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
805};
806
807#if 0
808/* under construction !*/
809/* under construction !*/
810/* under construction !*/
811/* under construction !*/
812#endif
813
814const DCL_UINT32 vsram_vmd_vosel[] =
815{
816 PMU_VOLT_00_550000_V, PMU_VOLT_00_600000_V, PMU_VOLT_00_650000_V, PMU_VOLT_00_750000_V,
817 PMU_VOLT_00_800000_V, PMU_VOLT_00_850000_V, PMU_VOLT_INVALID, PMU_VOLT_INVALID,
818};
819
820PMU_PARAMETER_TABLE_ENTRY pmu_parameter_table[]=
821{
822 {ENC(LDO_BUCK_SET_VOLTAGE, VPA_SW), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
823 {ENC(LDO_BUCK_SET_VOLTAGE, VPA), vpa_vosel, NULL, GETARRNUM(vpa_vosel) },
824 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM1), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
825 {ENC(LDO_BUCK_SET_VOLTAGE, VSIM2), vsim1_vosel, NULL, GETARRNUM(vsim1_vosel) },
826 {ENC(LDO_BUCK_SET_VOLTAGE, VXO22), vxo22_vosel, NULL, GETARRNUM(vxo22_vosel) },
827 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VMODEM), vmodem_vosel, NULL, GETARRNUM(vmodem_vosel) },
828 {ENC(LDO_BUCK_SET_SLEEP_VOLTAGE, VSRAM_MD), vsram_vmd_vosel, NULL, GETARRNUM(vsram_vmd_vosel) },
829};
830
831
832extern PMU_CONTROL_HANDLER pmu_control_handler;
833
834DCL_UINT16 pmu_parameter_size = 0;
835
836DCL_STATUS PMIC_control_handler(DCL_HANDLE handle,DCL_CTRL_CMD cmd,DCL_CTRL_DATA_T *data)
837{
838 DCL_UINT16 regVal;
839 DCL_INT32 return_val = STATUS_FAIL;
840#if defined(DCL_PMIC_MODULE_CONTROL)
841 current_dcl_handle = handle;
842#endif
843 switch(cmd)
844 {
845 case LDO_BUCK_SET_EN: //Enable control in SW mode
846 {
847 PMU_CTRL_LDO_BUCK_SET_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetEn);
848
849 switch(pLdoBuckCtrl->mod)
850 {
851 case VMODEM:
852 {
853 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_EN, pLdoBuckCtrl->enable);
854 return_val = STATUS_OK;
855 }
856 break;
857
858 case VPA_SW:
859 {
860 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_EN, pLdoBuckCtrl->enable);
861 return_val = STATUS_OK;
862 }
863 break;
864
865 case VSIM1:
866 {
867 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_EN, pLdoBuckCtrl->enable);
868 return_val = STATUS_OK;
869 }
870 break;
871
872 case VSIM2:
873 {
874 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_EN, pLdoBuckCtrl->enable);
875 return_val = STATUS_OK;
876 }
877 break;
878
879 case VFE28:
880 {
881 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_EN, pLdoBuckCtrl->enable);
882 return_val = STATUS_OK;
883 }
884 break;
885
886 case VRF18:
887 {
888 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_EN, pLdoBuckCtrl->enable);
889 return_val = STATUS_OK;
890 }
891 break;
892
893 case VRF12:
894 {
895 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_EN, pLdoBuckCtrl->enable);
896 return_val = STATUS_OK;
897 }
898 break;
899
900 case VS1:
901 {
902 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_EN, pLdoBuckCtrl->enable);
903 return_val = STATUS_OK;
904 }
905 break;
906
907 default:
908 return_val = STATUS_UNSUPPORTED;
909 break;
910 }
911 }
912 break;
913
914 case LDO_BUCK_SET_LP_MODE_SET:
915 {
916 PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET *pLdoBuckCtrl =& (data->rPMULdoBuckSetLpModeSet);
917
918 switch(pLdoBuckCtrl->mod)
919 {
920 case VMODEM:
921 { // 1'b0:Normal mode, 1'b1:Low power mode
922 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_LP, pLdoBuckCtrl->enable);
923 return_val = STATUS_OK;
924 }
925 break;
926
927 case VSIM1:
928 { // 1'b0:Normal mode, 1'b1:Low power mode
929 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_LP, pLdoBuckCtrl->enable);
930 return_val = STATUS_OK;
931 }
932 break;
933
934 case VSIM2:
935 { // 1'b0:Normal mode, 1'b1:Low power mode
936 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_LP, pLdoBuckCtrl->enable);
937 return_val = STATUS_OK;
938 }
939 break;
940
941 case VFE28:
942 { // 1'b0:Normal mode, 1'b1:Low power mode
943 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_LP, pLdoBuckCtrl->enable);
944 return_val = STATUS_OK;
945 }
946 break;
947
948 case VRF18:
949 { // 1'b0:Normal mode, 1'b1:Low power mode
950 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_LP, pLdoBuckCtrl->enable);
951 return_val = STATUS_OK;
952 }
953 break;
954
955 case VRF12:
956 { // 1'b0:Normal mode, 1'b1:Low power mode
957 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_LP, pLdoBuckCtrl->enable);
958 return_val = STATUS_OK;
959 }
960 break;
961
962 default:
963 return_val = STATUS_UNSUPPORTED;
964 break;
965 }
966 }
967 break;
968
969 case LDO_BUCK_SET_OCFB_EN:
970 {
971 PMU_CTRL_LDO_BUCK_SET_OCFB_EN *pLdoBuckCtrl=&(data->rPMULdoBuckSetOcfbEn);
972
973 switch(pLdoBuckCtrl->mod)
974 {
975 case VSIM1:
976 {
977 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OCFB_EN, pLdoBuckCtrl->enable);
978 return_val = STATUS_OK;
979 }
980 break;
981
982 case VSIM2:
983 {
984 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OCFB_EN, pLdoBuckCtrl->enable);
985 return_val = STATUS_OK;
986 }
987 break;
988
989 default:
990 return_val = STATUS_UNSUPPORTED;
991 break;
992 }
993 }
994 break;
995
996 case LDO_BUCK_GET_VOSEL:
997 {
998 PMU_CTRL_LDO_BUCK_GET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckGetVosel);
999
1000 switch(pLdoBuckCtrl->mod)
1001 {
1002 case VMODEM:
1003 {
1004 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL);
1005 return_val = STATUS_OK;
1006 }
1007 break;
1008
1009 case VS1:
1010 {
1011 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL);
1012 return_val = STATUS_OK;
1013 }
1014 break;
1015
1016 default:
1017 return_val = STATUS_UNSUPPORTED;
1018 break;
1019 }
1020 }
1021 break;
1022
1023 case LDO_BUCK_SET_VOSEL:
1024 {
1025 PMU_CTRL_LDO_BUCK_SET_VOSEL *pLdoBuckCtrl = &(data->rPMULdoBuckSetVosel);
1026
1027 switch(pLdoBuckCtrl->mod)
1028 {
1029 case VMODEM:
1030 {
1031 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL, pLdoBuckCtrl->code);
1032 return_val = STATUS_OK;
1033 }
1034 break;
1035
1036 case VS1:
1037 {
1038 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VS1_VOTER_VOSEL, pLdoBuckCtrl->code);
1039 return_val = STATUS_OK;
1040 }
1041 break;
1042
1043 case VSRAM_OTHERS:
1044 {
1045 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSRAM_OTHERS_VOSEL, pLdoBuckCtrl->code);
1046 return_val = STATUS_OK;
1047 }
1048 break;
1049
1050 default:
1051 return_val = STATUS_UNSUPPORTED;
1052 break;
1053 }
1054 }
1055 break;
1056
1057 case LDO_BUCK_GET_VOSEL_SLEEP:
1058 {
1059 PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckGetVoselSleep);
1060
1061 switch(pLdoBuckCtrl->mod)
1062 {
1063 case VMODEM:
1064 {
1065 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP);
1066 return_val = STATUS_OK;
1067 }
1068 break;
1069
1070 default:
1071 return_val = STATUS_UNSUPPORTED;
1072 break;
1073 }
1074 }
1075 break;
1076
1077 case LDO_BUCK_SET_VOSEL_SLEEP:
1078 {
1079 PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoselSleep);
1080
1081 switch(pLdoBuckCtrl->mod)
1082 {
1083 case VMODEM:
1084 {
1085 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_VOSEL_SLEEP, pLdoBuckCtrl->code);
1086 return_val = STATUS_OK;
1087 }
1088 break;
1089
1090 default:
1091 return_val = STATUS_UNSUPPORTED;
1092 break;
1093 }
1094 }
1095 break;
1096
1097 case LDO_BUCK_SET_MODESET:
1098 {
1099 PMU_CTRL_LDO_BUCK_SET_MODESET *pLdoBuckCtrl = &(data->rPMULdoBuckSetModeset);
1100
1101 switch(pLdoBuckCtrl->mod)
1102 {
1103 case VPA_SW:
1104 {
1105 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_VPA_MODESET, pLdoBuckCtrl->mode);
1106 return_val = STATUS_OK;
1107 }
1108 break;
1109
1110 case VMODEM:
1111 {
1112 dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_MODESET, pLdoBuckCtrl->mode);
1113 return_val = STATUS_OK;
1114 }
1115 break;
1116
1117 default:
1118 return_val = STATUS_UNSUPPORTED;
1119 break;
1120 }
1121 }
1122 break;
1123
1124 case LDO_BUCK_SET_OP_EN:
1125 {
1126 PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
1127
1128 kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
1129 (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
1130
1131 switch(pLdoBuckCtrl->mod)
1132 {
1133 case VMODEM:
1134 {
1135 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_SET_ADDR, mode);
1136 return_val = STATUS_OK;
1137 }
1138 break;
1139
1140 case VSIM1:
1141 {
1142 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_SET_ADDR, mode);
1143 return_val = STATUS_OK;
1144 }
1145 break;
1146
1147 case VSIM2:
1148 {
1149 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_SET_ADDR, mode);
1150 return_val = STATUS_OK;
1151 }
1152 break;
1153
1154 case VFE28:
1155 {
1156 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_SET_ADDR, mode);
1157 return_val = STATUS_OK;
1158 }
1159 break;
1160
1161 case VRF18:
1162 {
1163 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_SET_ADDR, mode);
1164 return_val = STATUS_OK;
1165 }
1166 break;
1167
1168 case VRF12:
1169 {
1170 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_SET_ADDR, mode);
1171 return_val = STATUS_OK;
1172 }
1173 break;
1174
1175 default:
1176 return_val = STATUS_UNSUPPORTED;
1177 break;
1178 }
1179 }
1180 break;
1181
1182 case LDO_BUCK_CLR_OP_EN:
1183 {
1184 PMU_CTRL_LDO_BUCK_SET_OP_EN *pLdoBuckCtrl = &(data->rPMULdoBuckSetOpEn);
1185
1186 kal_uint16 mode =((pLdoBuckCtrl->sw_op_en << SW_OP_EN_SHIFT) | (pLdoBuckCtrl->hw0_op_en << HW0_OP_EN_SHIFT)|
1187 (pLdoBuckCtrl->hw1_op_en << HW1_OP_EN_SHIFT)| (pLdoBuckCtrl->hw2_op_en << HW2_OP_EN_SHIFT));
1188
1189 switch(pLdoBuckCtrl->mod)
1190 {
1191 case VMODEM:
1192 {
1193 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_EN_CLR_ADDR, mode);
1194 return_val = STATUS_OK;
1195 }
1196 break;
1197
1198 case VSIM1:
1199 {
1200 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_EN_CLR_ADDR, mode);
1201 return_val = STATUS_OK;
1202 }
1203 break;
1204
1205 case VSIM2:
1206 {
1207 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_EN_CLR_ADDR, mode);
1208 return_val = STATUS_OK;
1209 }
1210 break;
1211
1212 case VFE28:
1213 {
1214 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_EN_CLR_ADDR, mode);
1215 return_val = STATUS_OK;
1216 }
1217 break;
1218
1219 case VRF18:
1220 {
1221 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_EN_CLR_ADDR, mode);
1222 return_val = STATUS_OK;
1223 }
1224 break;
1225
1226 case VRF12:
1227 {
1228 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_EN_CLR_ADDR, mode);
1229 return_val = STATUS_OK;
1230 }
1231 break;
1232
1233 default:
1234 return_val = STATUS_UNSUPPORTED;
1235 break;
1236 }
1237 }
1238 break;
1239
1240 case LDO_BUCK_SET_HW_OP_CFG:
1241 {
1242 PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckSetHwOp);
1243
1244 kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
1245 (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
1246 (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
1247
1248 switch(pLdoBuckCtrl->mod)
1249 {
1250 case VMODEM:
1251 {
1252 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_SET_ADDR, value);
1253 return_val = STATUS_OK;
1254 }
1255 break;
1256
1257 case VSIM1:
1258 {
1259 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_SET_ADDR, value);
1260 return_val = STATUS_OK;
1261 }
1262 break;
1263
1264 case VSIM2:
1265 {
1266 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_SET_ADDR, value);
1267 return_val = STATUS_OK;
1268 }
1269 break;
1270
1271 case VFE28:
1272 {
1273 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_SET_ADDR, value);
1274 return_val = STATUS_OK;
1275 }
1276 break;
1277
1278 case VRF18:
1279 {
1280 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_SET_ADDR, value);
1281 return_val = STATUS_OK;
1282 }
1283 break;
1284
1285 case VRF12:
1286 {
1287 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_SET_ADDR, value);
1288 return_val = STATUS_OK;
1289 }
1290 break;
1291
1292 default:
1293 return_val = STATUS_UNSUPPORTED;
1294 break;
1295 }
1296 }
1297 break;
1298
1299 case LDO_BUCK_CLR_HW_OP_CFG:
1300 {
1301 PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG *pLdoBuckCtrl = &(data->rPMULdoBuckClrHwOp);
1302
1303 kal_uint16 value =((pLdoBuckCtrl->hw0_op_cfg << HW0_OP_CFG_SHIFT) |
1304 (pLdoBuckCtrl->hw1_op_cfg << HW1_OP_CFG_SHIFT) |
1305 (pLdoBuckCtrl->hw2_op_cfg << HW2_OP_CFG_SHIFT));
1306
1307 switch(pLdoBuckCtrl->mod)
1308 {
1309 case VMODEM:
1310 {
1311 pmic_EM_reg_write(PMIC_RG_BUCK_VMODEM_OP_CFG_CLR_ADDR, value);
1312 return_val = STATUS_OK;
1313 }
1314 break;
1315
1316 case VSIM1:
1317 {
1318 pmic_EM_reg_write(PMIC_RG_LDO_VSIM1_OP_CFG_CLR_ADDR, value);
1319 return_val = STATUS_OK;
1320 }
1321 break;
1322
1323 case VSIM2:
1324 {
1325 pmic_EM_reg_write(PMIC_RG_LDO_VSIM2_OP_CFG_CLR_ADDR, value);
1326 return_val = STATUS_OK;
1327 }
1328 break;
1329
1330 case VFE28:
1331 {
1332 pmic_EM_reg_write(PMIC_RG_LDO_VFE28_OP_CFG_CLR_ADDR, value);
1333 return_val = STATUS_OK;
1334 }
1335 break;
1336
1337 case VRF18:
1338 {
1339 pmic_EM_reg_write(PMIC_RG_LDO_VRF18_OP_CFG_CLR_ADDR, value);
1340 return_val = STATUS_OK;
1341 }
1342 break;
1343
1344 case VRF12:
1345 {
1346 pmic_EM_reg_write(PMIC_RG_LDO_VRF12_OP_CFG_CLR_ADDR, value);
1347 return_val = STATUS_OK;
1348 }
1349 break;
1350
1351 default:
1352 return_val = STATUS_UNSUPPORTED;
1353 break;
1354 }
1355 }
1356 break;
1357
1358 case LDO_BUCK_SET_GO_ON_OP:
1359 {
1360 PMU_CTRL_LDO_BUCK_SET_GO_ON_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoOnOp);
1361
1362 switch(pLdoBuckCtrl->mod)
1363 {
1364 case VMODEM:
1365 {
1366 if(pLdoBuckCtrl->mode == Prefer_OFF)
1367 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1368 else
1369 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1370 return_val = STATUS_OK;
1371 }
1372 break;
1373
1374 case VSIM1:
1375 {
1376 if(pLdoBuckCtrl->mode == Prefer_OFF)
1377 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1378 else
1379 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1380 return_val = STATUS_OK;
1381 }
1382 break;
1383
1384 case VSIM2:
1385 {
1386 if(pLdoBuckCtrl->mode == Prefer_OFF)
1387 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1388 else
1389 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1390 return_val = STATUS_OK;
1391 }
1392 break;
1393
1394 case VFE28:
1395 {
1396 if(pLdoBuckCtrl->mode == Prefer_OFF)
1397 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1398 else
1399 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1400 return_val = STATUS_OK;
1401 }
1402 break;
1403
1404 case VRF18:
1405 {
1406 if(pLdoBuckCtrl->mode == Prefer_OFF)
1407 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1408 else
1409 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1410 return_val = STATUS_OK;
1411 }
1412 break;
1413
1414 case VRF12:
1415 {
1416 if(pLdoBuckCtrl->mode == Prefer_OFF)
1417 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_ON_OP_SHIFT);
1418 else
1419 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_ON_OP_SHIFT);
1420 return_val = STATUS_OK;
1421 }
1422 break;
1423
1424 default:
1425 return_val = STATUS_UNSUPPORTED;
1426 break;
1427 }
1428 }
1429 break;
1430
1431 case LDO_BUCK_SET_GO_LP_OP:
1432 {
1433 PMU_CTRL_LDO_BUCK_SET_GO_LP_OP *pLdoBuckCtrl = &(data->rPMULdoBuckSetGoLpOp);
1434
1435 switch(pLdoBuckCtrl->mod)
1436 {
1437 case VMODEM:
1438 {
1439 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1440 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1441 else
1442 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VMODEM_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1443 return_val = STATUS_OK;
1444 }
1445 break;
1446
1447 case VSIM1:
1448 {
1449 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1450 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1451 else
1452 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM1_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1453 return_val = STATUS_OK;
1454 }
1455 break;
1456
1457 case VSIM2:
1458 {
1459 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1460 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1461 else
1462 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VSIM2_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1463 return_val = STATUS_OK;
1464 }
1465 break;
1466
1467 case VFE28:
1468 {
1469 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1470 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1471 else
1472 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VFE28_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1473 return_val = STATUS_OK;
1474 }
1475 break;
1476
1477 case VRF18:
1478 {
1479 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1480 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1481 else
1482 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF18_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1483 return_val = STATUS_OK;
1484 }
1485 break;
1486
1487 case VRF12:
1488 {
1489 if(pLdoBuckCtrl->mode == Prefer_NO_LP)
1490 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_SET, 1 << GO_LP_OP_SHIFT);
1491 else
1492 dcl_pmic_field_write(PMIC_ENUM_RG_LDO_VRF12_OP_CFG_CLR, 1 << GO_LP_OP_SHIFT);
1493 return_val = STATUS_OK;
1494 }
1495 break;
1496
1497 default:
1498 return_val = STATUS_UNSUPPORTED;
1499 break;
1500 }
1501 }
1502 break;
1503
1504
1505 case LDO_BUCK_SET_VOLTAGE:
1506 {
1507 PMU_CTRL_LDO_BUCK_SET_VOLTAGE *pLdoBuckCtrl = &(data->rPMULdoBuckSetVoltage);
1508 regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->voltage);
1509
1510 switch(pLdoBuckCtrl->mod)
1511 {
1512 case VSIM1:
1513 {
1514 dcl_pmic_field_write(PMIC_ENUM_RG_VSIM1_VOSEL, regVal);
1515 return_val = STATUS_OK;
1516 }
1517 break;
1518
1519 case VSIM2:
1520 {
1521 dcl_pmic_field_write(PMIC_ENUM_RG_VSIM2_VOSEL, regVal);
1522 return_val = STATUS_OK;
1523 }
1524 break;
1525
1526 case VPA_SW:
1527 {
1528 dcl_pmic_field_write_nolock(PMIC_ENUM_RG_BUCK_VPA_VOSEL, regVal);
1529 return_val = STATUS_OK;
1530 }
1531 break;
1532
1533 case VXO22:
1534 {
1535 dcl_pmic_field_write(PMIC_ENUM_RG_VXO22_VOSEL, regVal);
1536 return_val = STATUS_OK;
1537 }
1538 break;
1539
1540 default:
1541 return_val = STATUS_UNSUPPORTED;
1542 break;
1543 }
1544 }
1545 break;
1546
1547
1548 case LDO_BUCK_GET_VOLTAGE:
1549 {
1550 PMU_CTRL_LDO_BUCK_GET_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckGetVolt);
1551
1552 switch(pLdoBuckCtrl->mod)
1553 {
1554 case VMODEM:
1555 {
1556 pLdoBuckCtrl->code = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_DA_VMODEM_VOSEL);
1557 return_val = STATUS_OK;
1558 }
1559 break;
1560
1561 default:
1562 return_val = STATUS_UNSUPPORTED;
1563 break;
1564 }
1565 }
1566 break;
1567
1568 case LDO_BUCK_SET_SLEEP_VOLTAGE:
1569 {
1570 PMU_CTRL_LDO_BUCK_SET_SLEEP_VOLTAGE *pLdoBuckCtrl=&(data->rPMULdoBuckSetSleepVoltage);
1571 regVal = PMU_Parameter_to_Value(ENC(cmd, pLdoBuckCtrl->mod), pLdoBuckCtrl->sleepVoltage);
1572
1573 switch(pLdoBuckCtrl->mod)
1574 {
1575 case VCORE:
1576 {
1577 dcl_pmic_field_write(PMIC_ENUM_RG_VCORE_SLEEP_VOLTAGE, regVal);
1578 return_val = STATUS_OK;
1579 }
1580 break;
1581
1582 case VMODEM:
1583 {
1584 dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_SLEEP_VOLTAGE, regVal);
1585 return_val = STATUS_OK;
1586 }
1587 break;
1588
1589 default:
1590 return_val = STATUS_UNSUPPORTED;
1591 break;
1592 }
1593 }
1594 break;
1595
1596 /*
1597 case VPA_SET_EN:
1598 {
1599 PMU_CTRL_VPA_SET_EN *pVpaSetEn = &(data->rPMUVpaSetEn);
1600 dcl_pmic6332_field_write(MT6332_VPA_EN, pVpaSetEn->enable);
1601 return_val = STATUS_OK;
1602 }
1603 break;
1604 */
1605
1606 case VPA_GET_VOLTAGE_LIST:
1607 {
1608 PMU_CTRL_VPA_GET_VOLTAGE_LIST *pVpaCtrl = &(data->rPMUVpaGetVoltageList);
1609 pVpaCtrl->pVoltageList = vpa_vosel;
1610 pVpaCtrl->number = GETARRNUM(vpa_vosel);
1611 return_val = STATUS_OK;
1612 }
1613 break;
1614
1615 case ADC_SET_RQST:
1616 {
1617 PMU_CTRL_ADC_SET_RQST *pAdcCtrl = &(data->rPMUAdcSetRqst);
1618 if((AUXADC_Status != AUXADC_READ_INIT) && (AUXADC_Status != AUXADC_READ_DATA))
1619 {
1620 ASSERT(0);
1621 }
1622 // Enable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
1623//TBD pmic_EM_reg_write(PMIC_TOP_CLKSQ_SET_ADDR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
1624 pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR_ADDR, (pAdcCtrl->enable << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
1625 pmic_EM_reg_write(PMIC_AUXADC_RQST1_SET_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
1626 AUXADC_Status = AUXADC_READ_REQUEST;
1627 return_val = STATUS_OK;
1628 }
1629 break;
1630
1631
1632 case ADC_GET_RDY_MD:
1633 {
1634 PMU_CTRL_ADC_GET_RDY_MD *pAdcCtrl = &(data->rPMUAdcGetRdyMd);
1635 pAdcCtrl->status = (DCL_BOOL)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_RDY_CH7_BY_MD);
1636 if((AUXADC_Status != AUXADC_READ_REQUEST) && (AUXADC_Status != AUXADC_READ_BUSY))
1637 {
1638 ASSERT(0);
1639 }
1640
1641 if(pAdcCtrl->status == DCL_TRUE)
1642 {
1643 AUXADC_Status = AUXADC_READ_READY;
1644 }
1645 else
1646 {
1647 AUXADC_Status = AUXADC_READ_BUSY;
1648 }
1649
1650 return_val = STATUS_OK;
1651 }
1652 break;
1653
1654 case ADC_GET_OUT_MD:
1655 {
1656 PMU_CTRL_ADC_GET_OUT_MD *pAdcCtrl = &(data->rPMUAdcGetOutMd);
1657 if(AUXADC_Status != AUXADC_READ_READY)
1658 {
1659 ASSERT(0);
1660 }
1661 pAdcCtrl->data = (DCL_UINT32)dcl_pmic_field_read(PMIC_ENUM_AUXADC_ADC_OUT_CH7_BY_MD);
1662 AUXADC_Status = AUXADC_READ_DATA;
1663 pmic_EM_reg_write(PMIC_AUXADC_RQST1_CLR_ADDR, (0x1 << PMIC_AUXADC_RQST_CH7_BY_MD_SHIFT));
1664 // Disable CLKSQ for MD (SW mode) RG_CLKSQ_EN_AUX_MD
1665//TBD pmic_EM_reg_write(PMIC_TOP_CLKSQ_CLR_ADDR, (0x1 << PMIC_RG_CLKSQ_EN_AUX_MD_SHIFT));
1666
1667 return_val = STATUS_OK;
1668 }
1669 break;
1670
1671 case TOP_SET_SRCLKEN_IN_EN:
1672 {
1673 PMU_CTRL_TOP_SET_SRCLKEN_IN_EN *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInEn);
1674
1675 switch(pTopSrclkenCtrl->mod)
1676 {
1677 case PMIC_SRCLKEN_IN0:
1678 {
1679 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_EN, pTopSrclkenCtrl->mode);
1680 return_val = STATUS_OK;
1681 }
1682 break;
1683
1684 case PMIC_SRCLKEN_IN1:
1685 {
1686 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_EN, pTopSrclkenCtrl->mode);
1687 return_val = STATUS_OK;
1688 }
1689 break;
1690
1691 default:
1692 return_val = STATUS_UNSUPPORTED;
1693 break;
1694 }
1695 }
1696 break;
1697
1698 case TOP_SET_SRCLKEN_IN_MODE:
1699 {
1700 PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE *pTopSrclkenCtrl = &(data->rPMUTopSetSrclkenInMode);
1701
1702 switch(pTopSrclkenCtrl->mod)
1703 {
1704 case PMIC_SRCLKEN_IN0:
1705 {
1706 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN0_HW_MODE, pTopSrclkenCtrl->mode);
1707 return_val = STATUS_OK;
1708 }
1709 break;
1710
1711 case PMIC_SRCLKEN_IN1:
1712 {
1713 dcl_pmic_field_write(PMIC_ENUM_RG_SRCLKEN_IN1_HW_MODE, pTopSrclkenCtrl->mode);
1714 return_val = STATUS_OK;
1715 }
1716 break;
1717
1718 default:
1719 return_val = STATUS_UNSUPPORTED;
1720 break;
1721 }
1722 }
1723 break;
1724
1725 case LDO_BUCK_SET_FPWM:
1726 {
1727 PMU_CTRL_LDO_BUCK_SET_FPWM *pLdoBuckSetFpwm = &(data->rPMULdoBuckSetFpwm);
1728
1729 switch(pLdoBuckSetFpwm->mod)
1730 {
1731 case VCORE:
1732 {
1733 dcl_pmic_field_write(PMIC_ENUM_RG_VCORE_FPWM, pLdoBuckSetFpwm->enable);
1734 return_val = STATUS_OK;
1735 }
1736 break;
1737
1738 case VPROC:
1739 {
1740 dcl_pmic_field_write(PMIC_ENUM_RG_VPROC_FPWM, pLdoBuckSetFpwm->enable);
1741 return_val = STATUS_OK;
1742 }
1743 break;
1744
1745 case VMODEM:
1746 {
1747 dcl_pmic_field_write(PMIC_ENUM_RG_VMODEM_FPWM, pLdoBuckSetFpwm->enable);
1748 return_val = STATUS_OK;
1749 }
1750 break;
1751
1752 default:
1753 return_val = STATUS_UNSUPPORTED;
1754 break;
1755 }
1756 }
1757 break;
1758
1759 case DCXO_SET_REGISTER_VALUE:
1760 {
1761 PMU_CTRL_DCXO_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUDcxoSetRegisterValue);
1762
1763 pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
1764 return_val = STATUS_OK;
1765
1766#if 0
1767/* under construction !*/
1768/* under construction !*/
1769/* under construction !*/
1770/* under construction !*/
1771/* under construction !*/
1772/* under construction !*/
1773/* under construction !*/
1774/* under construction !*/
1775/* under construction !*/
1776#endif
1777 }
1778 break;
1779
1780 case DCXO_GET_REGISTER_VALUE:
1781 {
1782 PMU_CTRL_DCXO_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUDcxoGetRegisterValue);
1783 pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
1784 return_val = STATUS_OK;
1785 }
1786 break;
1787
1788 case MISC_SET_REGISTER_VALUE:
1789 {
1790 PMU_CTRL_MISC_SET_REGISTER_VALUE *pChrCtrl = &(data->rPMUMiscSetRegisterValue);
1791#if defined(DCL_PMIC_PERMISSION_CONTROL)
1792 if(dcl_pmic_check_permission(pChrCtrl->offset)== DCL_TRUE)
1793#endif
1794 {
1795 pmic_EM_reg_write(pChrCtrl->offset, pChrCtrl->value);
1796 return_val = STATUS_OK;
1797 }
1798#if defined(DCL_PMIC_PERMISSION_CONTROL)
1799 else
1800 {
1801 illegal_misc_set_register_value.offset = pChrCtrl->offset;
1802 illegal_misc_set_register_value.value = pChrCtrl->value;
1803 ASSERT(0);
1804 }
1805#endif
1806 }
1807 break;
1808
1809 case MISC_GET_REGISTER_VALUE:
1810 {
1811 PMU_CTRL_MISC_GET_REGISTER_VALUE *pChrCtrl=&(data->rPMUMiscGetRegisterValue);
1812 pChrCtrl->value = pmic_EM_reg_read(pChrCtrl->offset);
1813 return_val = STATUS_OK;
1814 }
1815 break;
1816
1817 case LDO_BUCK_SET_VOCAL:
1818 {
1819 PMU_CTRL_LDO_BUCK_SET_VOCAL *pLdoBuckSetVocal = &(data->rPMULdoBuckSetVocal);
1820
1821 switch(pLdoBuckSetVocal->mod)
1822 {
1823 case VRF18_VOCAL:
1824 {
1825 dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOCAL, pLdoBuckSetVocal->value);
1826 return_val = STATUS_OK;
1827 }
1828 break;
1829
1830 case VRF12_VOCAL:
1831 {
1832 dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOCAL, pLdoBuckSetVocal->value);
1833 return_val = STATUS_OK;
1834 }
1835 break;
1836
1837 default:
1838 return_val = STATUS_UNSUPPORTED;
1839 break;
1840 }
1841 }
1842 break;
1843
1844 case LDO_BUCK_GET_VOCAL:
1845 {
1846 PMU_CTRL_LDO_BUCK_GET_VOCAL *pLdoBuckGetVocal = &(data->rPMULdoBuckGetVocal);
1847
1848 switch(pLdoBuckGetVocal->mod)
1849 {
1850 case VRF18_VOCAL:
1851 {
1852 pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOCAL);
1853 return_val = STATUS_OK;
1854 }
1855 break;
1856
1857 case VRF12_VOCAL:
1858 {
1859 pLdoBuckGetVocal->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOCAL);
1860 return_val = STATUS_OK;
1861 }
1862 break;
1863
1864 default:
1865 return_val = STATUS_UNSUPPORTED;
1866 break;
1867 }
1868 }
1869 break;
1870
1871
1872 case LDO_BUCK_SET_VOTRIM:
1873 {
1874 PMU_CTRL_LDO_BUCK_SET_VOTRIM *pLdoBuckSetVotrim = &(data->rPMULdoBuckSetVotrim);
1875
1876 switch(pLdoBuckSetVotrim->mod)
1877 {
1878 case VRF18_VOTRIM:
1879 {
1880 dcl_pmic_field_write(PMIC_ENUM_RG_VRF18_VOTRIM, pLdoBuckSetVotrim->value);
1881 return_val = STATUS_OK;
1882 }
1883 break;
1884
1885 case VRF12_VOTRIM:
1886 {
1887 dcl_pmic_field_write(PMIC_ENUM_RG_VRF12_VOTRIM, pLdoBuckSetVotrim->value);
1888 return_val = STATUS_OK;
1889 }
1890 break;
1891
1892 default:
1893 return_val = STATUS_UNSUPPORTED;
1894 break;
1895 }
1896 }
1897 break;
1898
1899 case LDO_BUCK_GET_VOTRIM:
1900 {
1901 PMU_CTRL_LDO_BUCK_GET_VOTRIM *pLdoBuckGetVotrim = &(data->rPMULdoBuckGetVotrim);
1902
1903 switch(pLdoBuckGetVotrim->mod)
1904 {
1905 case VRF18_VOTRIM:
1906 {
1907 pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF18_VOTRIM);
1908 return_val = STATUS_OK;
1909 }
1910 break;
1911
1912 case VRF12_VOTRIM:
1913 {
1914 pLdoBuckGetVotrim->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_VRF12_VOTRIM);
1915 return_val = STATUS_OK;
1916 }
1917 break;
1918
1919 default:
1920 return_val = STATUS_UNSUPPORTED;
1921 break;
1922 }
1923 }
1924 break;
1925
1926 case LDO_BUCK_SET_VPA_OC_SDN_STATUS:
1927 {
1928 PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_STATUS *pLdoBuckSetVpaOcSdnStatus = &(data->rPMULdoBuckSetVpaOcSdnStatus);
1929
1930 switch(pLdoBuckSetVpaOcSdnStatus->mod)
1931 {
1932 case VPA_OC_SDN_STATUS:
1933 {
1934 dcl_pmic_field_write(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS, pLdoBuckSetVpaOcSdnStatus->value);
1935 return_val = STATUS_OK;
1936 }
1937 break;
1938
1939 default:
1940 return_val = STATUS_UNSUPPORTED;
1941 break;
1942 }
1943 }
1944 break;
1945
1946 case LDO_BUCK_GET_VPA_OC_SDN_STATUS:
1947 {
1948 PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_STATUS *pLdoBuckGetVpaOcSdnStatus = &(data->rPMULdoBuckGetVpaOcSdnStatus);
1949
1950 switch(pLdoBuckGetVpaOcSdnStatus->mod)
1951 {
1952 case VPA_OC_SDN_STATUS:
1953 {
1954 pLdoBuckGetVpaOcSdnStatus->value = (DCL_UINT16)dcl_pmic_field_read(PMIC_ENUM_RG_BUCK_VPA_OC_SDN_STATUS);
1955 return_val = STATUS_OK;
1956 }
1957 break;
1958
1959 default:
1960 return_val = STATUS_UNSUPPORTED;
1961 break;
1962 }
1963 }
1964 break;
1965
1966 default:
1967 return_val = STATUS_UNSUPPORTED;
1968 break;
1969 }
1970#if defined(DCL_PMIC_MODULE_CONTROL)
1971 current_dcl_handle = 0;
1972#endif
1973 return return_val;
1974
1975}
1976
1977extern void dcl_pmic_modem_only_init(void);
1978extern void PMIC_Read_All(void);
1979#if defined(PMIC_UNIT_TEST)
1980extern void PMIC_Read_All(void);
1981extern void PMIC_Unit_Test(void);
1982#endif
1983DCL_UINT32 DRV_Read_PMIC_Data(DCL_UINT32 pmic_addr)
1984{
1985 return dcl_pmic_byte_return(pmic_addr);
1986}
1987
1988void DRV_Write_PMIC_Data(DCL_UINT32 pmic_addr, DCL_UINT32 value)
1989{
1990 dcl_pmic_byte_write(pmic_addr, value);
1991}
1992
1993void dcl_pmic_init(void){
1994 extern void pmic_wrap_dump_init(void);
1995 pmu_control_handler = PMIC_control_handler;
1996 pmu_parameter_size = GETARRNUM(pmu_parameter_table);
1997
1998 pmic_wrap_dump_init();
1999
2000 dcl_pmic_access_spinlock = kal_create_spinlock("pmic access");
2001 dcl_pmic_control_spinlock = kal_create_spinlock("pmic control");
2002
2003#if !defined(__SMART_PHONE_MODEM__)
2004 DrvPWRAP_Init();
2005#endif
2006 pmic_hw_version = dcl_pmic_byte_return(MT6357_HWCID);
2007 if (pmic_hw_version == 0x0)
2008 ASSERT(0);
2009
2010 PMIC_Read_All();
2011
2012#if !defined(__SMART_PHONE_MODEM__)
2013
2014/*
2015 if(DrvPWRAP_CheckCIPHER() == 1)
2016 dcl_pmic6355_modem_only_init();
2017 else
2018*/
2019 dcl_pmic_modem_only_init();
2020
2021#endif
2022
2023#if defined(PMIC_UNIT_TEST)
2024 PMIC_Read_All();
2025 PMIC_Unit_Test();
2026 PMIC_Read_All();
2027#endif
2028 pmic_init_done = DCL_TRUE;
2029
2030}
2031
2032void PMIC_Read_All(void)
2033{
2034 volatile kal_uint32 i,j;
2035 j=0;
2036 for (i = 0; i < PMIC_MAX_REG_NUM; i += 2){
2037 pmic_reg[i] = dcl_pmic_byte_return(i);
2038 while(j!=0x200){j++;}
2039 j=0;
2040 }
2041}
2042#if defined(PMIC_UNIT_TEST)
2043void PMIC_Unit_Test(void)
2044{
2045 {
2046 DCL_HANDLE handle;
2047 PMU_CTRL_LDO_BUCK_SET_ON_CTRL val;
2048 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2049 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
2050 val.mod = VMIPI;
2051 DclPMU_Control(handle, LDO_BUCK_SET_ON_CTRL, (DCL_CTRL_DATA_T *)&val);
2052 DclPMU_Close(handle);
2053 }
2054
2055 {
2056 DCL_HANDLE handle;
2057 PMU_CTRL_LDO_BUCK_SET_EN val;
2058 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2059 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2060 val.mod = VMIPI;
2061 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2062 DclPMU_Close(handle);
2063 }
2064
2065 {
2066 DCL_HANDLE handle;
2067 PMU_CTRL_LDO_BUCK_SET_EN val;
2068 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2069 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2070 val.mod = VPA_SW;
2071 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2072 DclPMU_Close(handle);
2073 }
2074
2075 {
2076 DCL_HANDLE handle;
2077 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
2078 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2079 val.mod=VPA_SW;
2080 val.voltage = PMU_VOLT_01_800000_V;
2081 /* PMU_VOLT_00_500000_V, PMU_VOLT_00_600000_V,
2082 PMU_VOLT_00_700000_V, PMU_VOLT_00_800000_V,
2083 PMU_VOLT_00_900000_V, PMU_VOLT_01_000000_V,
2084 PMU_VOLT_01_100000_V, PMU_VOLT_01_200000_V,
2085 PMU_VOLT_01_300000_V, PMU_VOLT_01_400000_V,
2086 PMU_VOLT_01_500000_V, PMU_VOLT_01_600000_V,
2087 PMU_VOLT_01_700000_V, PMU_VOLT_01_800000_V,
2088 PMU_VOLT_01_900000_V, PMU_VOLT_02_000000_V,
2089 PMU_VOLT_02_100000_V, PMU_VOLT_02_200000_V,
2090 PMU_VOLT_02_300000_V, PMU_VOLT_02_400000_V,
2091 PMU_VOLT_02_500000_V, PMU_VOLT_02_600000_V,
2092 PMU_VOLT_02_700000_V, PMU_VOLT_02_800000_V,
2093 PMU_VOLT_02_900000_V, PMU_VOLT_03_000000_V,
2094 PMU_VOLT_03_100000_V, PMU_VOLT_03_200000_V,
2095 PMU_VOLT_03_300000_V, PMU_VOLT_03_400000_V,
2096 PMU_VOLT_03_500000_V, PMU_VOLT_03_600000_V, */
2097 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
2098 DclPMU_Close(handle);
2099 }
2100
2101 {
2102 DCL_HANDLE handle;
2103 PMU_CTRL_LDO_BUCK_SET_MODESET val;
2104 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2105 val.mod = VPA_SW;
2106 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
2107 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
2108 DclPMU_Close(handle);
2109 }
2110 {
2111 DCL_HANDLE handle;
2112 PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
2113 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2114 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
2115 val.mod = VRF1;
2116 DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
2117 DclPMU_Close(handle);
2118 }
2119
2120 {
2121 DCL_HANDLE handle;
2122 PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
2123 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2124 val.sel = SRCLKEN_IN1_SEL;
2125 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
2126 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
2127 val.mod = VRF1;
2128 DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
2129 DclPMU_Close(handle);
2130 }
2131
2132 {
2133 DCL_HANDLE handle;
2134 PMU_CTRL_LDO_BUCK_SET_MODESET val;
2135 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2136 val.mod = VRF1;
2137 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
2138 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
2139 DclPMU_Close(handle);
2140 }
2141
2142 {
2143 DCL_HANDLE handle;
2144 PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET val;
2145 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2146 val.regval = 0x7; // (0x0~0xF)
2147 DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_SET, (DCL_CTRL_DATA_T *)&val);
2148 DclPMU_Close(handle);
2149 }
2150
2151 {
2152 DCL_HANDLE handle;
2153 PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR val;
2154 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2155 val.regval = 0x7; // (0x0~0xF)
2156 DclPMU_Control(handle, VRF1_SET_MODESET_CKPDN_CLR, (DCL_CTRL_DATA_T *)&val);
2157 DclPMU_Close(handle);
2158 }
2159
2160 {
2161 DCL_HANDLE handle;
2162 PMU_CTRL_VRF1_GET_MODESET_CKPDN val;
2163 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2164 // val.regval will be your request value ( no need do any shift)
2165 DclPMU_Control(handle, VRF1_GET_MODESET_CKPDN, (DCL_CTRL_DATA_T *)&val);
2166 DclPMU_Close(handle);
2167 }
2168
2169 {
2170 DCL_HANDLE handle;
2171 PMU_CTRL_LDO_BUCK_SET_EN_CTRL val;
2172 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2173 val.mode = HW_CONTROL; // (SW_CONTROL_BY_REG / HW_CONTROL)
2174 val.mod = VRF2;
2175 DclPMU_Control(handle, LDO_BUCK_SET_EN_CTRL, (DCL_CTRL_DATA_T *)&val);
2176 DclPMU_Close(handle);
2177 }
2178
2179 {
2180 DCL_HANDLE handle;
2181 PMU_CTRL_LDO_BUCK_SET_EN_SEL val;
2182 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2183 val.sel = SRCLKEN_IN1_SEL;
2184 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
2185 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
2186 val.mod = VRF2;
2187 DclPMU_Control(handle, LDO_BUCK_SET_EN_SEL, (DCL_CTRL_DATA_T *)&val);
2188 DclPMU_Close(handle);
2189 }
2190
2191 {
2192 DCL_HANDLE handle;
2193 PMU_CTRL_LDO_BUCK_SET_EN val;
2194 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2195 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2196 val.mod = VRF2;
2197 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2198 DclPMU_Close(handle);
2199 }
2200
2201 {
2202 DCL_HANDLE handle;
2203 PMU_CTRL_LDO_BUCK_SET_MODESET val;
2204 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2205 val.mod = VRF1;
2206 val.mode = FORCE_PWM_MODE; // (AUTO_MODE / FORCE_PWM_MODE)
2207 DclPMU_Control(handle, LDO_BUCK_SET_MODESET, (DCL_CTRL_DATA_T *)&val);
2208 DclPMU_Close(handle);
2209 }
2210
2211 {
2212 DCL_HANDLE handle;
2213 PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL val;
2214 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2215 val.sel = SRCLKEN_IN1_SEL;
2216 /* SRCLKEN_IN1_SEL / SRCLKEN_IN2_SEL/ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL/
2217 SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL/ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL */
2218 val.mod = VMIPI;
2219 DclPMU_Control(handle, LDO_BUCK_SET_SRCLK_EN_SEL, (DCL_CTRL_DATA_T *)&val);
2220 DclPMU_Close(handle);
2221 }
2222
2223 {
2224 DCL_HANDLE handle;
2225 PMU_CTRL_LDO_BUCK_SET_EN val;
2226 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2227 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2228 val.mod = VSIM1;
2229 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2230 DclPMU_Close(handle);
2231 }
2232
2233 {
2234 DCL_HANDLE handle;
2235 PMU_CTRL_LDO_BUCK_SET_EN val;
2236 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2237 val.enable = DCL_TRUE; // (DCL_TRUE / DCL_FALSE);
2238 val.mod = VSIM2;
2239 DclPMU_Control(handle, LDO_BUCK_SET_EN, (DCL_CTRL_DATA_T *)&val);
2240 DclPMU_Close(handle);
2241 }
2242
2243 {
2244 DCL_HANDLE handle;
2245 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
2246 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2247 val.mod=VSIM1;
2248 val.voltage = PMU_VOLT_01_800000_V;
2249 /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
2250 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
2251 DclPMU_Close(handle);
2252 }
2253
2254 {
2255 DCL_HANDLE handle;
2256 PMU_CTRL_LDO_BUCK_SET_VOLTAGE val;
2257 handle = DclPMU_Open(DCL_PMU, FLAGS_NONE);
2258 val.mod=VSIM2;
2259 val.voltage = PMU_VOLT_01_800000_V;
2260 /* PMU_VOLT_01_800000_V, PMU_VOLT_03_000000_V, */
2261 DclPMU_Control(handle, LDO_BUCK_SET_VOLTAGE, (DCL_CTRL_DATA_T *)&val);
2262 DclPMU_Close(handle);
2263 }
2264}
2265#endif // End of #if defined(PMIC_UNIT_TEST)
2266
2267#endif // End of #if defined(PMIC_6357_REG_API)
2268