| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2005 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | |
| 36 | /***************************************************************************** |
| 37 | * |
| 38 | * Filename: |
| 39 | * --------- |
| 40 | * uart_hw.h |
| 41 | * |
| 42 | * Project: |
| 43 | * -------- |
| 44 | * Maui_Software |
| 45 | * |
| 46 | * Description: |
| 47 | * ------------ |
| 48 | * This file is intends for UART driver. |
| 49 | * |
| 50 | * Author: |
| 51 | * ------- |
| 52 | * ------- |
| 53 | * |
| 54 | *============================================================================ |
| 55 | * HISTORY |
| 56 | * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 57 | *------------------------------------------------------------------------------ |
| 58 | * removed! |
| 59 | * removed! |
| 60 | * removed! |
| 61 | * |
| 62 | * removed! |
| 63 | * removed! |
| 64 | * removed! |
| 65 | * |
| 66 | * removed! |
| 67 | * removed! |
| 68 | * removed! |
| 69 | * |
| 70 | * removed! |
| 71 | * removed! |
| 72 | * removed! |
| 73 | * |
| 74 | * removed! |
| 75 | * removed! |
| 76 | * removed! |
| 77 | * |
| 78 | * removed! |
| 79 | * removed! |
| 80 | * removed! |
| 81 | * |
| 82 | * removed! |
| 83 | * removed! |
| 84 | * removed! |
| 85 | * |
| 86 | * removed! |
| 87 | * removed! |
| 88 | * removed! |
| 89 | * |
| 90 | * removed! |
| 91 | * removed! |
| 92 | * removed! |
| 93 | * |
| 94 | * removed! |
| 95 | * removed! |
| 96 | * removed! |
| 97 | * |
| 98 | * removed! |
| 99 | * removed! |
| 100 | * removed! |
| 101 | * removed! |
| 102 | * removed! |
| 103 | * removed! |
| 104 | * |
| 105 | * removed! |
| 106 | * removed! |
| 107 | * removed! |
| 108 | * removed! |
| 109 | * removed! |
| 110 | * |
| 111 | * removed! |
| 112 | * removed! |
| 113 | * removed! |
| 114 | * |
| 115 | * removed! |
| 116 | * removed! |
| 117 | * removed! |
| 118 | * |
| 119 | * removed! |
| 120 | * removed! |
| 121 | * removed! |
| 122 | * |
| 123 | * removed! |
| 124 | * removed! |
| 125 | * removed! |
| 126 | * |
| 127 | * removed! |
| 128 | * removed! |
| 129 | * removed! |
| 130 | * |
| 131 | * removed! |
| 132 | * removed! |
| 133 | * removed! |
| 134 | * |
| 135 | * removed! |
| 136 | * removed! |
| 137 | * removed! |
| 138 | * |
| 139 | * removed! |
| 140 | * removed! |
| 141 | * removed! |
| 142 | * |
| 143 | * removed! |
| 144 | * removed! |
| 145 | * removed! |
| 146 | * |
| 147 | * removed! |
| 148 | * removed! |
| 149 | * removed! |
| 150 | * |
| 151 | * removed! |
| 152 | * removed! |
| 153 | * removed! |
| 154 | * |
| 155 | * removed! |
| 156 | * removed! |
| 157 | * removed! |
| 158 | * |
| 159 | * removed! |
| 160 | * removed! |
| 161 | * removed! |
| 162 | * |
| 163 | * removed! |
| 164 | * removed! |
| 165 | * removed! |
| 166 | * |
| 167 | * removed! |
| 168 | * removed! |
| 169 | * removed! |
| 170 | * |
| 171 | * removed! |
| 172 | * removed! |
| 173 | * removed! |
| 174 | * |
| 175 | * removed! |
| 176 | * removed! |
| 177 | * removed! |
| 178 | * |
| 179 | * removed! |
| 180 | * removed! |
| 181 | * removed! |
| 182 | * |
| 183 | * removed! |
| 184 | * removed! |
| 185 | * removed! |
| 186 | * |
| 187 | * removed! |
| 188 | * removed! |
| 189 | * removed! |
| 190 | * |
| 191 | * removed! |
| 192 | * removed! |
| 193 | * removed! |
| 194 | * |
| 195 | * removed! |
| 196 | * removed! |
| 197 | * removed! |
| 198 | * |
| 199 | * removed! |
| 200 | * removed! |
| 201 | * removed! |
| 202 | * |
| 203 | * removed! |
| 204 | * removed! |
| 205 | * removed! |
| 206 | * |
| 207 | * removed! |
| 208 | * removed! |
| 209 | * removed! |
| 210 | * |
| 211 | * removed! |
| 212 | * removed! |
| 213 | * removed! |
| 214 | * |
| 215 | * removed! |
| 216 | * removed! |
| 217 | * removed! |
| 218 | * |
| 219 | * removed! |
| 220 | * removed! |
| 221 | * removed! |
| 222 | * removed! |
| 223 | * removed! |
| 224 | * removed! |
| 225 | * removed! |
| 226 | * removed! |
| 227 | * removed! |
| 228 | * removed! |
| 229 | * removed! |
| 230 | * removed! |
| 231 | * removed! |
| 232 | * removed! |
| 233 | * removed! |
| 234 | * removed! |
| 235 | * removed! |
| 236 | * removed! |
| 237 | * removed! |
| 238 | * removed! |
| 239 | * removed! |
| 240 | * removed! |
| 241 | * removed! |
| 242 | * removed! |
| 243 | * removed! |
| 244 | * removed! |
| 245 | * removed! |
| 246 | * removed! |
| 247 | * removed! |
| 248 | * removed! |
| 249 | * removed! |
| 250 | * removed! |
| 251 | * removed! |
| 252 | * removed! |
| 253 | * removed! |
| 254 | * removed! |
| 255 | * removed! |
| 256 | * removed! |
| 257 | * removed! |
| 258 | * removed! |
| 259 | * removed! |
| 260 | * removed! |
| 261 | * removed! |
| 262 | * removed! |
| 263 | * removed! |
| 264 | * removed! |
| 265 | * removed! |
| 266 | * removed! |
| 267 | * removed! |
| 268 | * removed! |
| 269 | * removed! |
| 270 | * removed! |
| 271 | * removed! |
| 272 | * removed! |
| 273 | * removed! |
| 274 | * removed! |
| 275 | * removed! |
| 276 | * removed! |
| 277 | * removed! |
| 278 | * removed! |
| 279 | * removed! |
| 280 | * removed! |
| 281 | * removed! |
| 282 | * removed! |
| 283 | * removed! |
| 284 | * removed! |
| 285 | * removed! |
| 286 | * removed! |
| 287 | * removed! |
| 288 | * removed! |
| 289 | * removed! |
| 290 | * removed! |
| 291 | * removed! |
| 292 | * removed! |
| 293 | * removed! |
| 294 | * removed! |
| 295 | * removed! |
| 296 | * removed! |
| 297 | * removed! |
| 298 | * removed! |
| 299 | * removed! |
| 300 | * removed! |
| 301 | * removed! |
| 302 | * removed! |
| 303 | * removed! |
| 304 | * removed! |
| 305 | * removed! |
| 306 | * removed! |
| 307 | * removed! |
| 308 | *------------------------------------------------------------------------------ |
| 309 | * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!! |
| 310 | *============================================================================ |
| 311 | ****************************************************************************/ |
| 312 | #ifndef UART_HW_H |
| 313 | #define UART_HW_H |
| 314 | |
| 315 | #if __LTE_TBC__ |
| 316 | #include "dma_hw.h" |
| 317 | #endif |
| 318 | #include "drv_comm.h" |
| 319 | |
| 320 | #if !defined(DRV_UART_OFF) |
| 321 | |
| 322 | /*used in Task or normal function*/ |
| 323 | #define UART_RBR(_baseaddr) (_baseaddr+0x0) /* Read only */ |
| 324 | #define UART_THR(_baseaddr) (_baseaddr+0x0) /* Write only */ |
| 325 | #define UART_IER(_baseaddr) (_baseaddr+0x4) |
| 326 | #define UART_IIR(_baseaddr) (_baseaddr+0x8) /* Read only */ |
| 327 | #define UART_FCR(_baseaddr) (_baseaddr+0x8) /* Write only */ |
| 328 | #define UART_LCR(_baseaddr) (_baseaddr+0xc) |
| 329 | #define UART_MCR(_baseaddr) (_baseaddr+0x10) |
| 330 | #define UART_LSR(_baseaddr) (_baseaddr+0x14) |
| 331 | #define UART_MSR(_baseaddr) (_baseaddr+0x18) |
| 332 | #define UART_SCR(_baseaddr) (_baseaddr+0x1c) |
| 333 | #define UART_DLL(_baseaddr) (_baseaddr+0x0) |
| 334 | #define UART_DLH(_baseaddr) (_baseaddr+0x4) |
| 335 | #define UART_EFR(_baseaddr) (_baseaddr+0x8) /* Only when LCR = 0xbf */ |
| 336 | #define UART_XON1(_baseaddr) (_baseaddr+0x10) /* Only when LCR = 0xbf */ |
| 337 | #define UART_XON2(_baseaddr) (_baseaddr+0x14) /* Only when LCR = 0xbf */ |
| 338 | #define UART_XOFF1(_baseaddr) (_baseaddr+0x18) /* Only when LCR = 0xbf */ |
| 339 | #define UART_XOFF2(_baseaddr) (_baseaddr+0x1c) /* Only when LCR = 0xbf */ |
| 340 | |
| 341 | #define UART_RATE_STEP(_baseaddr) (_baseaddr+0x24) |
| 342 | #define UART_STEP_COUNT(_baseaddr) (_baseaddr+0x28) |
| 343 | #define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr+0x2c) |
| 344 | #define UART_RATE_FIX_REG(_baseaddr) (_baseaddr+0x34) |
| 345 | #define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr+0x38) |
| 346 | #define UART_GUARD(_baseaddr) (_baseaddr+0x3C) |
| 347 | #define UART_ESCAPE_DAT(_baseaddr) (_baseaddr+0x40) |
| 348 | #define UART_ESCAPE_EN(_baseaddr) (_baseaddr+0x44) |
| 349 | #define UART_SLEEP_EN(_baseaddr) (_baseaddr+0x48) |
| 350 | #define UART_DMA_EN(_baseaddr) (_baseaddr+0x4c) |
| 351 | #define UART_RXTRI(_baseaddr) (_baseaddr+0x50) |
| 352 | #define UART_DMA_ACK(_baseaddr) (_baseaddr+0xb8) |
| 353 | |
| 354 | //IER |
| 355 | #if defined(DRV_UART_FIFO_FLOW_CONTROL) |
| 356 | #define UART_IER_ERBFI 0x0001 |
| 357 | #define UART_IER_ETBEI 0x0002 |
| 358 | #define UART_IER_ELSI 0x0004 |
| 359 | #define UART_IER_EDSSI 0x0008 |
| 360 | #define UART_IER_XOFFI 0x0020 |
| 361 | #define UART_IER_RTSI 0x0040 |
| 362 | #define UART_IER_CTSI 0x0080 |
| 363 | |
| 364 | #define IER_HW_NORMALINTS 0x001d |
| 365 | #define IER_HW_ALLINTS 0x001f |
| 366 | #define IER_SW_NORMALINTS 0x003d |
| 367 | #define IER_SW_ALLINTS 0x003f |
| 368 | |
| 369 | #define UART_IER_ALLOFF 0x0010 //because of UART_IER_VFF_FC_EN not one of interrupt masks |
| 370 | #define UART_IER_VFIFO 0x0011 |
| 371 | #else //#if defined(DRV_UART_FIFO_FLOW_CONTROL) |
| 372 | #define UART_IER_ERBFI 0x0001 |
| 373 | #define UART_IER_ETBEI 0x0002 |
| 374 | #define UART_IER_ELSI 0x0004 |
| 375 | #define UART_IER_EDSSI 0x0008 |
| 376 | #define UART_IER_XOFFI 0x0020 |
| 377 | #define UART_IER_RTSI 0x0040 |
| 378 | #define UART_IER_CTSI 0x0080 |
| 379 | |
| 380 | #define IER_HW_NORMALINTS 0x000d |
| 381 | #define IER_HW_ALLINTS 0x000f |
| 382 | #define IER_SW_NORMALINTS 0x002d |
| 383 | #define IER_SW_ALLINTS 0x002f |
| 384 | |
| 385 | #define UART_IER_ALLOFF 0x0000 |
| 386 | #define UART_IER_VFIFO 0x0001 |
| 387 | #endif //#if defined(DRV_UART_FIFO_FLOW_CONTROL) |
| 388 | |
| 389 | |
| 390 | |
| 391 | #define UART_RATE_STEP_16 0x0000 /* baud = clock/UART_RATE_STEP/divisor */ |
| 392 | #define UART_RATE_STEP_8 0x0001 |
| 393 | #define UART_RATE_STEP_4 0x0002 |
| 394 | #define UART_RATE_STEP_COUNT 0x0003 /* baud = clock/UART_RATE_STEP_COUNT */ |
| 395 | #define UART_STEP_COUNT_MASK 0x00ff |
| 396 | #define UART_SAMPLE_COUNT_MASK 0x00ff |
| 397 | |
| 398 | |
| 399 | //FCR |
| 400 | #define UART_FCR_FIFOEN 0x0001 |
| 401 | #define UART_FCR_CLRR 0x0002 |
| 402 | #define UART_FCR_CLRT 0x0004 |
| 403 | #define UART_FCR_FIFOINI 0x0007 |
| 404 | #define UART_FCR_RX1Byte_Level 0x0000 |
| 405 | #define UART_FCR_RX6Byte_Level 0x0040 |
| 406 | #define UART_FCR_RX12Byte_Level 0x0080 |
| 407 | #define UART_FCR_RXTRIG_Level 0x00c0 |
| 408 | |
| 409 | #define UART_FCR_TX0Byte_Level 0x0000 |
| 410 | #define UART_FCR_TX4Byte_Level 0x0010 |
| 411 | #define UART_FCR_TX8Byte_Level 0x0020 |
| 412 | #define UART_FCR_TX14Byte_Level 0x0030 |
| 413 | |
| 414 | #define UART_FCR_Normal (UART_FCR_TX0Byte_Level | UART_FCR_RX12Byte_Level | UART_FCR_FIFOINI) |
| 415 | #define UART_FCR_RX_Normal (UART_FCR_RX12Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel |
| 416 | #define UART_FCR_TX_Normal (UART_FCR_TX0Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel |
| 417 | #define UART1_TxFIFO_DEPTH 32 |
| 418 | #define UART1_RxFIFO_DEPTH 32 |
| 419 | #define UART2_TxFIFO_DEPTH 32 |
| 420 | #define UART2_RxFIFO_DEPTH 32 |
| 421 | |
| 422 | #if defined(DRV_UART_FIFO_FLOW_CONTROL) //Use larger size of RX FIFO, because it can trigger flow CONTROL_CHANNEL_MSG |
| 423 | #define UART_VFIFO_DEPTH (UART_FCR_FIFOINI | UART_FCR_RX16Byte_Level) |
| 424 | #else |
| 425 | #define UART_VFIFO_DEPTH 7 |
| 426 | #endif |
| 427 | |
| 428 | //IIR,RO |
| 429 | #define UART_IIR_INT_INVALID 0x0001 |
| 430 | #define UART_IIR_RLS 0x0006 // Receiver Line Status |
| 431 | #define UART_IIR_RDA 0x0004 // Receive Data Available |
| 432 | #define UART_IIR_CTI 0x000C // Character Timeout Indicator |
| 433 | #define UART_IIR_THRE 0x0002 // Transmit Holding Register Empty |
| 434 | #define UART_IIR_MS 0x0000 // Check Modem Status Register |
| 435 | #define UART_IIR_SWFlowCtrl 0x0010 // Receive XOFF characters |
| 436 | #define UART_IIR_HWFlowCtrl 0x0020 // CTS or RTS Rising Edge |
| 437 | #define UART_IIR_FIFOS_ENABLED 0x00c0 |
| 438 | #define UART_IIR_NO_INTERRUPT_PENDING 0x0001 |
| 439 | #define UART_IIR_INT_MASK 0x001f |
| 440 | |
| 441 | //===============================LCR================================ |
| 442 | //WLS |
| 443 | #define UART_WLS_8 0x0003 |
| 444 | #define UART_WLS_7 0x0002 |
| 445 | #define UART_WLS_6 0x0001 |
| 446 | #define UART_WLS_5 0x0000 |
| 447 | #define UART_DATA_MASK 0x0003 |
| 448 | |
| 449 | //Parity |
| 450 | #define UART_NONE_PARITY 0x0000 |
| 451 | #define UART_ODD_PARITY 0x0008 |
| 452 | #define UART_EVEN_PARITY 0x0018 |
| 453 | #define UART_MARK_PARITY 0x0028 |
| 454 | #define UART_SPACE_PARITY 0x0038 |
| 455 | #define UART_PARITY_MASK 0x0038 |
| 456 | |
| 457 | //Stop bits |
| 458 | #define UART_1_STOP 0x0000 |
| 459 | #define UART_1_5_STOP 0x0004 // Only valid for 5 data bits |
| 460 | #define UART_2_STOP 0x0004 |
| 461 | #define UART_STOP_MASK 0x0004 |
| 462 | |
| 463 | #define UART_LCR_DLAB 0x0080 |
| 464 | #define UART_LCR_BREAK 0x0040 |
| 465 | //===============================LCR================================ |
| 466 | |
| 467 | //MCR |
| 468 | #define UART_MCR_DTR 0x0001 |
| 469 | #define UART_MCR_RTS 0x0002 |
| 470 | #define UART_MCR_LOOPB 0x0010 |
| 471 | #define UART_MCR_IRE 0x0040 //Enable IrDA modulation/demodulation |
| 472 | #define UART_MCR_XOFF 0x0080 |
| 473 | #define UART_MCR_Normal (UART_MCR_DTR | UART_MCR_RTS) |
| 474 | #define UART_MCR_DCM_EN 0x0020 |
| 475 | |
| 476 | |
| 477 | //LSR |
| 478 | #define UART_LSR_DR 0x0001 |
| 479 | #define UART_LSR_OE 0x0002 |
| 480 | #define UART_LSR_PE 0x0004 |
| 481 | #define UART_LSR_FE 0x0008 |
| 482 | #define UART_LSR_BI 0x0010 |
| 483 | #define UART_LSR_THRE 0x0020 |
| 484 | #define UART_LSR_TEMT 0x0040 |
| 485 | #define UART_LSR_FIFOERR 0x0080 |
| 486 | |
| 487 | //MSR |
| 488 | #define UART_MSR_DCTS 0x0001 |
| 489 | #define UART_MSR_DDSR 0x0002 |
| 490 | #define UART_MSR_TERI 0x0004 |
| 491 | #define UART_MSR_DDCD 0x0008 |
| 492 | #define UART_MSR_CTS 0x0010 |
| 493 | #define UART_MSR_DSR 0x0020 |
| 494 | #define UART_MSR_RI 0x0040 |
| 495 | #define UART_MSR_DCD 0x0080 |
| 496 | |
| 497 | //DLL |
| 498 | //DLM |
| 499 | //EFR |
| 500 | #define UART_EFR_AutoCTS 0x0080 |
| 501 | #define UART_EFR_AutoRTS 0x0040 |
| 502 | #define UART_EFR_Enchance 0x0010 |
| 503 | #define UART_EFR_SWCtrlMask 0x000f |
| 504 | #define UART_EFR_NoSWFlowCtrl 0x0000 |
| 505 | #define UART_EFR_ALLOFF 0x0000 |
| 506 | #define UART_EFR_AutoRTSCTS 0x00c0 |
| 507 | |
| 508 | #if defined(DRV_UART_FIFO_FLOW_CONTROL) //add 0x10 RX FIFO flow control in all values. |
| 509 | //Tx/Rx XON1/Xoff1 as flow control word |
| 510 | #define UART_EFR_SWFlowCtrlX1 0x001a |
| 511 | //Tx/Rx XON2/Xoff2 as flow control word |
| 512 | #define UART_EFR_SWFlowCtrlX2 0x0015 |
| 513 | //Tx/Rx XON1&XON2/Xoff1&Xoff2 as flow control word |
| 514 | #define UART_EFR_SWFlowCtrlXAll 0x001f |
| 515 | #else //#if defined(DRV_UART_FIFO_FLOW_CONTROL) |
| 516 | #define UART_EFR_SWFlowCtrlX1 0x000a |
| 517 | #define UART_EFR_SWFlowCtrlX2 0x0005 |
| 518 | #define UART_EFR_SWFlowCtrlXAll 0x000f |
| 519 | #endif//#if defined(DRV_UART_FIFO_FLOW_CONTROL) |
| 520 | |
| 521 | //DMA_EN |
| 522 | #define UART_TXRXDMA_ON 0x0003 |
| 523 | #define UART_TO_CNT_AUTORST 0x0004 |
| 524 | #define UART_FIFO_LSR_SEL 0x0008 |
| 525 | #define UART_TXRXDMA_OFF 0x0000 |
| 526 | |
| 527 | //DMA_ACK |
| 528 | #define UART_DMA_ACK_TX 0x0002 |
| 529 | #define UART_DMA_ACK_RX 0x0001 |
| 530 | #define UART_DMA_ACK_DIS 0x0000 |
| 531 | |
| 532 | #define UART_RXTRI_VALUE 0x16 |
| 533 | |
| 534 | #if defined(DRV_UART_VFIFO_V2) |
| 535 | |
| 536 | #ifdef DMA_POP |
| 537 | #undef DMA_POP |
| 538 | #endif |
| 539 | |
| 540 | #ifdef DMA_PUSH |
| 541 | #undef DMA_PUSH |
| 542 | #endif |
| 543 | |
| 544 | #define DMA_POP(_n) DRV_Reg8(DRV_Reg(DMA_VFF_RPT(_n))+DRV_Reg32(DMA_SRC(_n)));\ |
| 545 | if(DRV_Reg(DMA_VFF_RPT(_n)) == (DRV_Reg(DMA_VFF_SIZE(_n))-1))\ |
| 546 | DRV_WriteReg32(DMA_VFF_RPT(_n), (~DRV_Reg32(DMA_VFF_RPT(_n)))&0x10000);\ |
| 547 | else \ |
| 548 | DRV_WriteReg32(DMA_VFF_RPT(_n), DRV_Reg32(DMA_VFF_RPT(_n))+1); |
| 549 | |
| 550 | #define DMA_PUSH(_n,_data) while(DRV_Reg(DMA_W_INT_BUF_SIZE(_n))>=64);*(volatile kal_uint8*)DMA_VPORT(_n) = (kal_uint8)_data; |
| 551 | #define DMA_PUSH32(_n,_data) while(DRV_Reg(DMA_W_INT_BUF_SIZE(_n))>60);*(volatile kal_uint32*)DMA_VPORT(_n) = (kal_uint32)_data; |
| 552 | |
| 553 | #endif //#if defined(DRV_UART_VFIFO_V2) |
| 554 | |
| 555 | #if defined(DRV_UART_VFIFO_V3) |
| 556 | |
| 557 | #ifdef DMA_POP |
| 558 | #undef DMA_POP |
| 559 | #endif |
| 560 | |
| 561 | #ifdef DMA_PUSH |
| 562 | #undef DMA_PUSH |
| 563 | #endif |
| 564 | |
| 565 | #define DMA_POP(_n) DRV_Reg8(DRV_Reg(DMA_VFF_RPT(_n))+DRV_Reg32(DMA_SRC(_n)));\ |
| 566 | if(DRV_Reg(DMA_VFF_RPT(_n)) == (DRV_Reg(DMA_VFF_SIZE(_n))-1))\ |
| 567 | DRV_WriteReg32(DMA_VFF_RPT(_n), (~DRV_Reg32(DMA_VFF_RPT(_n)))&0x10000);\ |
| 568 | else \ |
| 569 | DRV_WriteReg32(DMA_VFF_RPT(_n), DRV_Reg32(DMA_VFF_RPT(_n))+1); |
| 570 | |
| 571 | #define DMA_PUSH(_n,_data) \ |
| 572 | DRV_WriteReg8(DRV_Reg(DMA_VFF_WPT(_n))+DRV_Reg32(DMA_SRC(_n)),_data);\ |
| 573 | if(DRV_Reg(DMA_VFF_WPT(_n)) == (DRV_Reg(DMA_VFF_SIZE(_n))-1))\ |
| 574 | DRV_WriteReg32(DMA_VFF_WPT(_n), (~DRV_Reg32(DMA_VFF_WPT(_n)))&0x10000);\ |
| 575 | else \ |
| 576 | DRV_WriteReg32(DMA_VFF_WPT(_n), DRV_Reg32(DMA_VFF_WPT(_n))+1); |
| 577 | |
| 578 | #endif //#if defined(DRV_UART_VFIFO_V3) |
| 579 | |
| 580 | |
| 581 | |
| 582 | #endif /*#if !defined(DRV_UART_OFF)*/ |
| 583 | #endif /*UART_HW_H*/ |
| 584 | |
| 585 | |