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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / devdrv / uart / src / dbgprint.c
blob: 599069b1d3c9219a110379a1b6601b5607ef61a1 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1/*****************************************************************************
2* Copyright Statement:
3* --------------------
4* This software is protected by Copyright and the information contained
5* herein is confidential. The software may not be copied and the information
6* contained herein may not be used or disclosed except with the written
7* permission of MediaTek Inc. (C) 2012
8*
9* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
10* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
11* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
12* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
13* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
14* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
15* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
16* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
17* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
18* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
19* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
20* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
21*
22* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
23* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
24* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
25* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
26* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
27*
28* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
29* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
30* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
31* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
32* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
33*
34*****************************************************************************/
35
36/*******************************************************************************
37 * Filename:
38 * ---------
39 * dbgprint.c
40 *
41 * Project:
42 * --------
43 * TATAKA
44 *
45 * Description:
46 * ------------
47 * This Module defines debug function for driver.
48 *
49 * Author:
50 * -------
51 * -------
52 * -------
53 * -------
54 *
55 * ==========================================================================
56 * $Log$
57 *
58 * 11 16 2020 vend_mcd_cienet018
59 * [MOLY00594178] [colgin] porting uart driver code from NR15.R3.T700.MP to NR15.R3.MD700.MP
60 * [colgin]modify build error in dbgprint.c
61 *
62 * 11 12 2020 vend_mcd_cienet018
63 * [MOLY00594178] [colgin] porting uart driver code from NR15.R3.T700.MP to NR15.R3.MD700.MP
64 * [colgin] porting uart driver code from NR15.R3.T700.MP to NR15.R3.MD700.MP
65 *
66 * 11 12 2020 vend_mcd_cienet018
67 * [MOLY00592922] [Montrose] Call for check in:add option in IDC/UART driver
68 * [Colgin] porting code from T700 to MD700 for uart drver
69 *
70 * 11 10 2020 vend_mcd_cienet018
71 * [MOLY00592922] [Montrose] call for check in: add option in UART driver
72 *
73 * 07 15 2020 yao.xue
74 * [MOLY00546509] Palmer /Petrus-p call for check in: update IDC/UART driver
75 * Palmer/Petrus-p call for check in:updateIDC/UART driver
76 *
77 * 02 15 2019 panu.peisa
78 * [MOLY00384803] [Gen97][SystemService][Change Request] KAL Refactoring Phase-in
79 *
80 * Added changes to swrd part.
81 *
82 * 04 10 2018 yuke.ren
83 * [MOLY00318981] Merge SLT Code
84 * .
85 *
86 * 11 07 2017 shenghui.shi
87 * [MOLY00288093] update UART driver to remove no needed project option
88 * update uart driver to remove no needed files
89 *
90 * 09 15 2017 da.li
91 * [MOLY00270315] [System Service][KIR] make ex robust before ex steplog work
92 * Replace INT_QueryExceptionStatus with #include <ex_public.h>.
93 *
94 * 09 08 2017 da.li
95 * [MOLY00274163] [Sylvia] Driver porting
96 * Build warning(error) fix.
97 *
98 * 09 07 2017 da.li
99 * [MOLY00274163] [Sylvia] Driver porting
100 * UART driver porting for Sylvia.
101 *
102 * 09 07 2017 yao.xue
103 * [MOLY00275927] update uart dbg_print init
104 * update dbgprint init
105 *
106 * 07 13 2017 shenghui.shi
107 * [MOLY00263518] Update UART driver test code
108 * fix build error
109 *
110 * 07 13 2017 shenghui.shi
111 * [MOLY00263518] Update UART driver test code
112 * update UART driver
113 *
114 * 04 24 2017 shenghui.shi
115 * [MOLY00243727] update UART PDN feature
116 * update UART pdn feature,to void system could not entry DCM issue.
117 *
118 * 03 06 2017 shenghui.shi
119 * [MOLY00233604] UART print driver update for baudrate
120 * update UART baudrate
121 *
122 * 02 07 2017 shenghui.shi
123 * [MOLY00228102] [Bianco Bring-up]UMOLYA uart driver update
124 * update UART dbgprint driver
125 *
126 * 09 30 2016 shenghui.shi
127 * [MOLY00171995] update uart driver for 93
128 * .
129 *
130 * 09 22 2016 yuke.ren
131 * [MOLY00204183] Fix UART HDMA usage
132 * set RX SEL for RX channel
133 *
134 * 09 20 2016 yuke.ren
135 * [MOLY00204183] Fix UART HDMA usage
136 * .
137 *
138 * 07 05 2016 shenghui.shi
139 * [MOLY00184725] UMOLYA ESL/MASE porting
140 * .
141 *
142 * 05 19 2016 shenghui.shi
143 * [MOLY00171995] update uart driver for 93
144 * .
145 *
146 * 03 15 2016 shenghui.shi
147 * [MOLY00081492] [UART] update uart driver
148 * update dbgprint driver for SMP
149 *
150 * 08 05 2015 yuke.ren
151 * [MOLY00135235] [6291+] UART Driver Porting
152 * Merging
153 *
154 * //UMOLY/DEV/MT6291PLUS.PRE_SB.W1517.DEV/mcu/common/driver/devdrv/uart/src/dbgprint.c
155 *
156 * to //UMOLY/TRUNK/UMOLY/mcu/common/driver/devdrv/uart/src/dbgprint.c
157 *
158 * 08 05 2015 yuke.ren
159 * [MOLY00135235] [6291+] UART Driver Porting
160 * .
161 *
162 * 08 04 2015 yuke.ren
163 * [MOLY00135235] [6291+] UART Driver Porting
164 * .
165 *
166 * 08 04 2015 yuke.ren
167 * [MOLY00135235] [6291+] UART Driver Porting
168 * .
169 *
170 * 05 22 2014 shenghui.shi
171 * [MOLY00065467] [TK6291] update UART driver for TK6291
172 * .
173 *
174 * 05 22 2014 shenghui.shi
175 * [MOLY00065467] [TK6291] update UART driver for TK6291
176 * update dbg_print() API
177 *
178 * 05 19 2014 shenghui.shi
179 * [MOLY00065467] [TK6291] update UART driver for TK6291
180 * Revert uart dbgprint.c to version1. to fixed dbg_print() undefined error.
181 *
182 * 12 10 2013 shenghui.shi
183 * [MOLY00049628] MT6595 UART merge to Trunk
184 * .
185 *
186 * 11 13 2013 shenghui.shi
187 * [MOLY00046360] add SLT UART logging API
188 * .
189 *
190 * 09 03 2013 shenghui.shi
191 * [MOLY00035768] fix uart build warnning
192 * .
193 *
194 * 09 03 2013 shenghui.shi
195 * [MOLY00035768] fix uart build warnning
196 * .
197 *
198 * 07 18 2013 shenghui.shi
199 * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
200 * add dbgprint for ARM7 using SUART0 port.
201 *
202 * 03 06 2013 ansel.liao
203 * [MOLY00006575] add temporary feature: can use CPU mode UART in normal build
204 * Integration change.
205 *
206 * 03 05 2013 ansel.liao
207 * [MOLY00006575] add temporary feature: can use CPU mode UART in normal build
208 * temporary feature
209 *
210 * 11 30 2012 ansel.liao
211 * [MOLY00006575] Add UART/HDMA Driver
212 * add dbg_flush and corresponding drvtest
213 *
214 * 11 23 2012 ansel.liao
215 * [MOLY00006575] Add UART/HDMA Driver
216 * Add UART/HDMA driver
217 ****************************************************************************/
218#define MAXCHARS 512
219#define MAXFRACT 10000
220#define NumFract 4
221
222#include "drv_comm.h"
223#include "stdarg.h"
224#include "dcl.h"
225
226#include "kal_public_api.h"
227#ifdef KTEST_UART_TRACES
228#include "kal_hrt_api.h"
229#endif
230#include "uart_internal.h"
231#include "uart_hw.h"
232#include "drvpdn.h"
233#include "sync_data.h"
234
235#if (defined(DRV_DEBUG) || defined(__IC_SLT__))
236
237#if defined( DRV_DEBUG)
238#define DBG_PRINT_PORT uart_port1 // Use UART1 as debug port (UART_MD)
239#define DBG_PRINT_BAUD UART_BAUD_1500000
240#else //defined(__IC_SLT__)
241#define DBG_PRINT_PORT uart_port1 // Use UART1 as debug port (UART_MD)
242#define DBG_PRINT_BAUD UART_BAUD_1500000
243#endif
244
245#ifndef KTEST_UART_TRACES
246kal_spinlockid dbg_print_lock = 0;
247#if defined(DRV_DEBUG_BUFFER_DMA_MODE)
248extern kal_spinlockid print_buf_lock;
249#endif
250#endif
251
252extern kal_uint32 UART_BaseAddr[MAX_UART_PORT_NUM];
253extern UARTStruct UARTPort[MAX_UART_PORT_NUM];
254kal_bool dbg_init_flag = KAL_FALSE;
255char print_buf[MAXCHARS];
256
257
258extern void U_SetBaudRate(UART_PORT port, UART_baudrate baudrate, module_type ownerid);
259#include <ex_public.h>
260void dbg_uart_init(void);
261void itof(char **buf, int i);
262static void itoa(char **buf, int i, int base);
263
264static void dbg_UARTPutByte(kal_uint8 data)
265{
266 volatile kal_uint16 LSR;
267 kal_uint32 uart_base = UART_BaseAddr[DBG_PRINT_PORT];
268 while(1)
269 {
270 LSR = DRV_Reg32(UART_LSR(uart_base));
271 if((LSR & UART_LSR_THRE))
272 {
273 DRV_WriteReg32(UART_THR(uart_base), data);
274 break;
275 }
276 }
277}
278void itof(char **buf, int i)
279{
280 char *s;
281#define LEN 20
282 int rem, j;
283 static char rev[LEN+1];
284
285 rev[LEN] = 0;
286 s = &rev[LEN];
287 for (j= 0 ; j < NumFract ; j++)
288 {
289 rem = i % 10;
290 *--s = rem + '0';
291 i /= 10;
292 }
293 while (*s)
294 {
295 (*buf)[0] = *s++;
296 ++(*buf);
297 }
298}
299
300static void itoa(char **buf, int i, int base)
301{
302 char *s;
303#define LEN 20
304 int rem;
305 static char rev[LEN+1];
306
307 rev[LEN] = 0;
308 if (i == 0)
309 {
310 (*buf)[0] = '0';
311 ++(*buf);
312 return;
313 }
314 s = &rev[LEN];
315 while (i)
316 {
317 rem = i % base;
318 if (rem < 10)
319 *--s = rem + '0';
320 else if (base == 16)
321 *--s = "abcdef"[rem - 10];
322 i /= base;
323 }
324 while (*s)
325 {
326 (*buf)[0] = *s++;
327 ++(*buf);
328 }
329}
330
331void drv_uart_configure_hdma(kal_uint32 uart_port)
332{
333 kal_uint32 uart_hdma_tx_channel, uart_hdma_rx_channel;
334 switch(uart_port){
335 case uart_port1:
336 uart_hdma_tx_channel = UART1_HDMA_TX_CHANNEL;
337 uart_hdma_rx_channel = UART1_HDMA_RX_CHANNEL;
338 // init TX HDMA
339 HDMA_MODE_CONFIG(uart_hdma_tx_channel, HDMA_CKSUM_EN_DEFAULT, HDMA_BASIC_MODE, HDMA_CKSUM_12B);
340 HDMA_CONFIG(UART1_HDMA_TX_CHANNEL, HDMA_BURST_SIZE_DEFAULT, HDMA_DEV_BUS_WIDTH_DEFAULT, HDMA_MEM_BUS_WIDTH_DEFAULT);
341 HDMA_BUF0_XFER_SIZE_CONFIG(UART1_HDMA_TX_CHANNEL, 0);
342
343 // init RX HDMA
344 HDMA_CONFIG_RX_SEL(UART1_HDMA_RX_CHANNEL, 0x3);
345 HDMA_MODE_CONFIG(uart_hdma_rx_channel, HDMA_CKSUM_EN_DEFAULT, HDMA_BASIC_MODE, HDMA_CKSUM_12B);
346 HDMA_CONFIG(UART1_HDMA_RX_CHANNEL, HDMA_BURST_SIZE_DEFAULT, HDMA_DEV_BUS_WIDTH_DEFAULT, HDMA_MEM_BUS_WIDTH_DEFAULT);
347 HDMA_BUF0_XFER_SIZE_CONFIG(UART1_HDMA_RX_CHANNEL, 0);
348
349 DRV_WriteReg32(UART_DMA_EN(UART_BaseAddr[uart_port]), UART_TXRXDMA_ON|UART_TO_CNT_AUTORST);
350 DRV_WriteReg32(UART_DMA_ACK(UART_BaseAddr[uart_port]),UART_DMA_ACK_DIS);
351 break;
352 case uart_port2:
353 break;
354 default:
355 ASSERT(0);
356 break;
357 }
358}
359
360extern void UART_PDN_Disable(UART_PORT port);
361
362void drv_uart_IOPAD_configure(DCL_DEV uart_port) {
363
364 // APB Module gpio
365 #define GPIO_BASE (0xC0005000)
366
367#if defined(MT6893) // for Petrus-P
368 if(uart_port== uart_port1) {
369 /* GPIO36/37 set to function6 */
370 DRV_WriteReg32((GPIO_BASE+0x348), (0xFF << 16));
371 DRV_WriteReg32((GPIO_BASE+0x344), (0x44 << 16));
372
373 DRV_WriteReg32((0xC1F20000+0x68), (0X3 << 17));
374 DRV_WriteReg32((0xC1F20000+0x84), (0X1 << 17));
375
376 } else if (uart_port== uart_port2) {
377
378 /* GPIO38/GPIO39 set to function4 */
379 DRV_WriteReg32((GPIO_BASE+0x348), (0xFF << 24));
380 DRV_WriteReg32((GPIO_BASE+0x344), (0x44 << 24));
381
382 DRV_WriteReg32((0xC1F20000+0x68), (0X3 << 19));
383 DRV_WriteReg32((0xC1F20000+0x84), (0X1 << 19));
384
385 } else if (uart_port == uart_port3) {
386 /* Do nothing */
387 /*Bianco not have MDUART2 port*/
388 }
389#elif defined(MT6833) // for PALMER
390 if(uart_port== uart_port1) {
391 /* GPIO35/36 set to function6 */
392 DRV_WriteReg32((GPIO_BASE+0x348), (0xFF << 12));
393 DRV_WriteReg32((GPIO_BASE+0x344), (0x44 << 12));
394
395 DRV_WriteReg32((0xC1E60000+0xC8), (0X3 << 6));
396 DRV_WriteReg32((0xC1E60000+0xE4), (0X1 << 6));
397
398 } else if (uart_port== uart_port2) {
399 /* GPIO37/38 set to function4 */
400 DRV_WriteReg32((GPIO_BASE+0x348), (0xFF << 20));
401 DRV_WriteReg32((GPIO_BASE+0x344), (0x44 << 20));
402
403 DRV_WriteReg32((0xC1E60000+0xC8), (0X3 << 8));
404 DRV_WriteReg32((0xC1E60000+0xE4), (0X1 << 8));
405
406 } else if (uart_port == uart_port3) {
407 /* Do nothing */
408 /*Bianco not have MDUART2 port*/
409 }
410#elif defined(MT6877) // for Montrose
411 if(uart_port== uart_port1) {
412 /* GPIO98/99 set to function4 */
413 DRV_WriteReg32((GPIO_BASE+0x3C8), (0xFF << 8));
414 DRV_WriteReg32((GPIO_BASE+0x3C4), (0x44 << 8));
415
416 DRV_WriteReg32((0xC1D30000+0x58), 1);
417 DRV_WriteReg32((0xC1D30000+0x74), 1);
418 DRV_WriteReg32((0xC1D10000+0x78), 1);
419
420 } else if (uart_port== uart_port2) {
421 /* GPIO100/101 set to function4 */
422 DRV_WriteReg32((GPIO_BASE+0x3C8), (0xFF << 16));
423 DRV_WriteReg32((GPIO_BASE+0x3C4), (0x44 << 16));
424
425 DRV_WriteReg32((0xC1D10000+0x78), 2);
426 DRV_WriteReg32((0xC1D10000+0xa4), 2);
427 DRV_WriteReg32((0xC1D30000+0x58), 2);
428
429 } else if (uart_port == uart_port3) {
430 /* Do nothing */
431 /*Bianco not have MDUART2 port*/
432 }
433#elif defined(CHIP10992) // for colgin
434 if(uart_port == uart_port1) {
435 /* GPIO183/184 set to function4 */
436 DRV_WriteReg32((GPIO_BASE+0x468), 0x70000000);
437 DRV_WriteReg32((GPIO_BASE+0x478), 0x7);
438 DRV_WriteReg32((GPIO_BASE+0x464), 0x20000000);
439 DRV_WriteReg32((GPIO_BASE+0x474), 0x2);
440
441
442 /* URXD/UTXD PULL clear PD */
443 DRV_WriteReg32((0xC1C10000+0x098), 0x8800);
444 /* URXD PULL up Select */
445 DRV_WriteReg32((0xC1C10000+0x0C4), 0x8000);
446 } else if (uart_port == uart_port2) {
447
448 } else if (uart_port == uart_port3) {
449 }
450#else
451
452#define IOCFG1_BASE (0xC1C10000)
453
454if(uart_port== uart_port1) {
455 /* GPIO184/183 set to function6 */
456 DRV_WriteReg32((GPIO_BASE+0x468), 0X70000000);
457 DRV_WriteReg32((GPIO_BASE+0x478), 0X7);
458DRV_WriteReg32((GPIO_BASE+0x464), 0X20000000);
459 DRV_WriteReg32((GPIO_BASE+0x474), 0X2);
460
461 /* URXD PULL enable */
462 DRV_WriteReg32((IOCFG1_BASE+0x098), 0X8800);
463 /* URXD PULL up Select */
464 DRV_WriteReg32((IOCFG1_BASE+0x0C4), 0X8000);
465
466} else if (uart_port== uart_port2) {
467
468 /* GPIO10/GPIO11 set to function4 */
469 DRV_WriteReg32((0xC0005000+0x318), (0xFF00));
470 DRV_WriteReg32((0xC0005000+0x314), (0x6600));
471
472 /* URXD PULL enable */
473 DRV_WriteReg32((0xC0002A00+0x054), (0x1 << 1));
474 /* URXD PULL DOWN disable*/
475 DRV_WriteReg32((0xC0002A00+0x048), (0x1 << 1));
476
477} else if (uart_port == uart_port3) {
478 /* Do nothing */
479 /*Bianco not have MDUART2 port*/
480}
481#endif
482}
483
484//we must set this init function to driver init stage to void muliti-core access init function at the same time issue.
485#ifndef KTEST_UART_TRACES
486void dbg_uart_create_spinlock(void){
487 if (dbg_print_lock == 0) {
488 dbg_print_lock = kal_create_spinlock("printf_");
489 }
490#if defined(DRV_DEBUG_BUFFER_DMA_MODE)
491 if (print_buf_lock == 0){
492 print_buf_lock = kal_create_spinlock("printf_buf");
493 }
494#endif
495}
496#endif
497
498void dbg_uart_init(void){
499
500 kal_uint32 port = DBG_PRINT_PORT;
501 kal_uint32 uart_base = UART_BaseAddr[DBG_PRINT_PORT];
502
503 if((dbg_init_flag == KAL_FALSE)||(DRV_Reg32(UART_RATE_STEP(uart_base)) != 0x3)){
504 UART_PDN_Disable(port);
505
506 drv_uart_IOPAD_configure(port);//for debug
507 if(port == uart_port1){
508 #if defined(DRV_DEBUG_DMA_MODE) || defined(DRV_DEBUG_BUFFER_DMA_MODE)
509 HDMA_DONE_INTR_UNMASK(UART1_HDMA_TX_CHANNEL);
510 drv_uart_configure_hdma(port);
511 #else
512 DRV_WriteReg32(UART_DMA_EN(uart_base), 0x0); //disable DMA
513 #endif
514 }
515
516/* #if defined(__MTK_TARGET__)
517 switch(port){
518 case uart_port1:
519 PDN_CLR(PDN_UART0);
520 #if defined(DRV_DEBUG_DMA_MODE) || defined(DRV_DEBUG_BUFFER_DMA_MODE)
521 HDMA_PDN_CLR(port+2);
522 HDMA_PDN_CLR(port+4);
523 HDMA_DONE_INTR_UNMASK(2);
524 drv_uart_configure_hdma(port);
525 #else
526 DRV_WriteReg32(UART_DMA_EN(uart_base), 0x0); //disable DMA
527 #endif
528 break;
529 case uart_port2:
530 PDN_CLR(PDN_UART1);
531 DRV_WriteReg32(UART_DMA_EN(uart_base), 0x0); //disable DMA
532 break;
533 default: break;
534 }
535 #endif
536*/
537 DRV_WriteReg(UART_IER(uart_base), UART_IER_ALLOFF);
538 DRV_WriteReg32(UART_LCR(uart_base), 0xBF);
539 DRV_WriteReg32(UART_EFR(uart_base), 0x0); //no flow control;
540 DRV_WriteReg32(UART_LCR(uart_base), 0x03); //word len = 8 bit; stop bit =1; parity = false;
541 DRV_WriteReg32(UART_FCR(uart_base), 0x05); //set fifo enable ,and clear Tx and Rx fifo.
542 U_SetBaudRate(DBG_PRINT_PORT, DBG_PRINT_BAUD, (module_type)(DBG_PRINT_PORT));
543
544 dbg_init_flag = KAL_TRUE;
545 }
546
547}
548
549
550
551#ifdef DRV_DEBUG
552extern void UART_DMA_PutBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length);
553extern kal_uint16 BMT_PutBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length);
554#if !defined(__ESL_DBG_UTIL__)
555void dbg_print(char *fmt,...)
556{
557#if (!defined(IC_MODULE_TEST))
558 va_list ap;
559 double dval;
560 int ival;
561 char *p, *sval;
562 char *bp, cval;
563 int fract;
564 unsigned short len;
565 UART_CTRL_PUT_BYTES_T BMTPutBytes;
566
567
568#ifndef KTEST_UART_TRACES
569 kal_take_spinlock(dbg_print_lock, KAL_INFINITE_WAIT);
570#else
571 kal_hrt_take_itc_lock(KAL_ITC_DBG, KAL_INFINITE_WAIT);
572#endif
573 dbg_uart_init();
574
575#if defined(DRV_DEBUG_DMA_MODE)
576 while(HDMA_BUF0_IS_ACTIVE(DBG_PRINT_PORT+2));
577#elif defined(DRV_DEBUG_BUFFER_MODE)
578 //no need do anything.
579#else
580 //no need do anything.
581#endif
582
583 bp= print_buf;
584 *bp= 0;
585
586 va_start (ap, fmt);
587 for (p= fmt; *p; p++)
588 {
589 if (*p != '%')
590 {
591 *bp++= *p;
592 continue;
593 }
594 switch (*++p) {
595 case 'd':
596 ival= va_arg(ap, int);
597 if (ival < 0){
598 *bp++= '-';
599 ival= -ival;
600 }
601 itoa (&bp, ival, 10);
602 break;
603
604 case 'o':
605 ival= va_arg(ap, int);
606 if (ival < 0){
607 *bp++= '-';
608 ival= -ival;
609 }
610 *bp++= '0';
611 itoa (&bp, ival, 8);
612 break;
613
614 case 'x':
615 ival= va_arg(ap, int);
616 if (ival < 0){
617 *bp++= '-';
618 ival= -ival;
619 }
620 *bp++= '0';
621 *bp++= 'x';
622 itoa (&bp, ival, 16);
623 break;
624
625 case 'X':
626 ival= va_arg(ap, int);
627 bp += sprintf(bp, "0x%x", ival);
628 break;
629
630 case 'c':
631 cval= va_arg(ap, int);
632 *bp++= cval;
633 break;
634
635 case 'f':
636 dval= va_arg(ap, double);
637 if (dval < 0){
638 *bp++= '-';
639 dval= -dval;
640 }
641 if (dval >= 1.0)
642 itoa (&bp, (int)dval, 10);
643 else
644 *bp++= '0';
645 *bp++= '.';
646 fract= (int)((dval- (double)(int)dval)*(double)(MAXFRACT));
647 itof(&bp, fract);
648 break;
649
650 case 's':
651 for (sval = va_arg(ap, char *) ; *sval ; sval++ )
652 *bp++= *sval;
653 break;
654 }
655 }
656 va_end (ap);
657
658 *bp= 0;
659 len = (unsigned short)(bp - print_buf);
660
661
662 BMTPutBytes.puBuffaddr = (kal_uint8 *)print_buf;
663 BMTPutBytes.u2Length = len;
664#if defined(DRV_DEBUG_DMA_MODE)
665 UART_DMA_PutBytes(DBG_PRINT_PORT, BMTPutBytes.puBuffaddr, BMTPutBytes.u2Length);
666#elif defined(DRV_DEBUG_BUFFER_MODE) || defined(DRV_DEBUG_BUFFER_DMA_MODE)
667 BMT_PutBytes(DBG_PRINT_PORT, BMTPutBytes.puBuffaddr, BMTPutBytes.u2Length);
668#else
669 int i = (int)BMTPutBytes.u2Length;
670 for(i = 0; i < len; i++)
671 {
672 dbg_UARTPutByte(print_buf[i]);
673 }
674#endif
675
676
677#ifndef KTEST_UART_TRACES
678 kal_give_spinlock(dbg_print_lock);
679#else
680#if !defined (__FPGA__)
681 { // Have some delay for UART buffer flushing
682 volatile kal_uint32 i=300000;
683 while(i--);
684 }
685#endif
686 kal_hrt_give_itc_lock(KAL_ITC_DBG);
687#endif
688
689 // Flush the data in uart buffer when exception occurs
690 if(INT_QueryExceptionStatus()){
691 UART_AssertWaitPrevDataSentOut(DBG_PRINT_PORT);
692
693 }
694#endif
695
696}
697#endif
698char print_buf2[MAXCHARS];
699void dbg_printWithTime(char *fmt,...)
700{
701#if !defined(__LTE_REMOVE_TEMPERAL__)
702
703#if (!defined(IC_MODULE_TEST))
704 int i;
705 va_list ap;
706 double dval;
707 int ival;
708 char *p, *sval;
709 char *bp, cval;
710 int fract;
711 unsigned short len;
712
713 bp= print_buf2;
714 *bp= 0;
715
716#ifndef KTEST_UART_TRACES
717 kal_take_spinlock(dbg_print_lock, KAL_INFINITE_WAIT);
718#else
719 kal_hrt_take_itc_lock(KAL_ITC_DBG, KAL_INFINITE_WAIT);
720#endif
721
722 va_start (ap, fmt);
723 for(p= fmt; *p; p++)
724 {
725 if (*p != '%')
726 {
727 *bp++= *p;
728 continue;
729 }
730 switch (*++p)
731 {
732 case 'd':
733 ival= va_arg(ap, int);
734 if (ival < 0)
735 {
736 *bp++= '-';
737 ival= -ival;
738 }
739 itoa (&bp, ival, 10);
740 break;
741
742 case 'o':
743 ival= va_arg(ap, int);
744 if (ival < 0)
745 {
746 *bp++= '-';
747 ival= -ival;
748 }
749 *bp++= '0';
750 itoa (&bp, ival, 8);
751 break;
752
753 case 'x':
754 ival= va_arg(ap, int);
755 if(ival < 0)
756 {
757 *bp++= '-';
758 ival= -ival;
759 }
760 *bp++= '0';
761 *bp++= 'x';
762 itoa (&bp, ival, 16);
763 break;
764
765 case 'X':
766 ival= va_arg(ap, int);
767 bp += sprintf(bp, "0x%x", ival);
768 break;
769
770 case 'c':
771 cval= va_arg(ap, int);
772 *bp++= cval;
773 break;
774
775 case 'f':
776 dval= va_arg(ap, double);
777 if(dval < 0)
778 {
779 *bp++= '-';
780 dval= -dval;
781 }
782 if(dval >= 1.0)
783 itoa (&bp, (int)dval, 10);
784 else
785 *bp++= '0';
786 *bp++= '.';
787 fract= (int)((dval- (double)(int)dval)*(double)(MAXFRACT));
788 itof(&bp, fract);
789 break;
790
791 case 's':
792 for(sval = va_arg(ap, char *) ; *sval ; sval++ )
793 *bp++= *sval;
794 break;
795 }
796 }
797 *bp= 0;
798 len = (unsigned short)(bp - print_buf2);
799
800
801 for(i = 0; i < len; i++)
802 {
803 dbg_UARTPutByte(print_buf2[i]);
804 }
805
806 va_end (ap);
807
808#ifndef KTEST_UART_TRACES
809 kal_give_spinlock(dbg_print_lock);
810#else
811 kal_hrt_give_itc_lock(KAL_ITC_DBG);
812#endif
813#endif
814#endif /* !defined(__LTE_REMOVE_TEMPERAL__) */
815
816}
817
818void dbg_flush(void)
819{
820#if 0
821/* under construction !*/
822/* under construction !*/
823/* under construction !*/
824/* under construction !*/
825/* under construction !*/
826/* under construction !*/
827/* under construction !*/
828/* under construction !*/
829/* under construction !*/
830/* under construction !*/
831/* under construction !*/
832/* under construction !*/
833/* under construction !*/
834/* under construction !*/
835/* under construction !*/
836/* under construction !*/
837/* under construction !*/
838/* under construction !*/
839/* under construction !*/
840/* under construction !*/
841/* under construction !*/
842/* under construction !*/
843/* under construction !*/
844/* under construction !*/
845/* under construction !*/
846/* under construction !*/
847/* under construction !*/
848/* under construction !*/
849/* under construction !*/
850/* under construction !*/
851#endif
852}
853
854
855#endif
856
857#if defined(__IC_SLT__)
858
859#if !defined(DRV_DEBUG)
860void dbg_printWithTime(char *fmt,...){}
861void dbg_print(char *fmt,...){}
862void dbg_flush(void){}
863#endif
864
865void slt_dbg_print(char *fmt,...)
866{
867
868 int i;
869 va_list ap;
870 double dval;
871 int ival;
872 char *p, *sval;
873 char *bp, cval;
874 int fract;
875 unsigned short len;
876
877 bp= print_buf;
878 *bp= 0;
879
880#ifndef KTEST_UART_TRACES
881 kal_take_spinlock(dbg_print_lock, KAL_INFINITE_WAIT);
882#else
883 kal_hrt_take_itc_lock(KAL_ITC_DBG, KAL_INFINITE_WAIT);
884#endif
885 dbg_uart_init();
886
887 va_start (ap, fmt);
888 for(p= fmt; *p; p++)
889 {
890 if (*p != '%')
891 {
892 *bp++= *p;
893 continue;
894 }
895 switch (*++p)
896 {
897 case 'd':
898 ival= va_arg(ap, int);
899 if (ival < 0)
900 {
901 *bp++= '-';
902 ival= -ival;
903 }
904 itoa (&bp, ival, 10);
905 break;
906
907 case 'o':
908 ival= va_arg(ap, int);
909 if (ival < 0)
910 {
911 *bp++= '-';
912 ival= -ival;
913 }
914 *bp++= '0';
915 itoa (&bp, ival, 8);
916 break;
917
918 case 'x':
919 ival= va_arg(ap, int);
920 if(ival < 0)
921 {
922 *bp++= '-';
923 ival= -ival;
924 }
925 *bp++= '0';
926 *bp++= 'x';
927 itoa (&bp, ival, 16);
928 break;
929
930 case 'X':
931 ival= va_arg(ap, int);
932 bp += sprintf(bp, "0x%x", ival);
933 break;
934
935 case 'c':
936 cval= va_arg(ap, int);
937 *bp++= cval;
938 break;
939
940 case 'f':
941 dval= va_arg(ap, double);
942 if(dval < 0)
943 {
944 *bp++= '-';
945 dval= -dval;
946 }
947 if(dval >= 1.0)
948 itoa (&bp, (int)dval, 10);
949 else
950 *bp++= '0';
951 *bp++= '.';
952 fract= (int)((dval- (double)(int)dval)*(double)(MAXFRACT));
953 itof(&bp, fract);
954 break;
955
956 case 's':
957 for(sval = va_arg(ap, char *) ; *sval ; sval++ )
958 *bp++= *sval;
959 break;
960 }
961 }
962 *bp= 0;
963 len = (unsigned short)(bp - print_buf);
964
965 for(i = 0; i < len; i++)
966 {
967 dbg_UARTPutByte(print_buf[i]);
968 }
969
970 va_end (ap);
971
972#ifndef KTEST_UART_TRACES
973 kal_give_spinlock(dbg_print_lock);
974#else
975 kal_hrt_give_itc_lock(KAL_ITC_DBG);
976#endif
977
978}
979#endif
980
981#else
982void dbg_printWithTime(char *fmt,...){}
983void dbg_print(char *fmt,...){}
984void dbg_flush(void){}
985void dbg_uart_init(void){}
986void slt_dbg_flush(void){};
987void slt_dbg_print(char *fmt,...){}
988
989#endif