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192.168.1.100 / T800_MD / 04730939d77d4b1fce91df3083777d88f0b04c4a / . / mcu / driver / peripheral / inc / dcl_pmu6253_sw.h
blob: ee833fdb3703a5188176f060c36314406cc0e7e3 [file] [log] [blame]
rjw6c1fd8f2022-11-30 14:33:01 +0800[diff] [blame]1
2
3
4#ifndef __DCL_PMU6253_SW_H_STRUCT__
5#define __DCL_PMU6253_SW_H_STRUCT__
6
7#include "dcl_pmic_features.h"
8
9#if defined(PMIC_6253_REG_API)
10
11/* Charger external interrupt is fixed. */
12
13#define PMU_CHR_EINT_PIN 7
14
15
16/* adc number for measuring VBAT/VISENSE/VCHARGER is fixed internally. */
17#if defined(PMIC_6253_REG_API)
18#if defined(DRV_MISC_PMU_ADC_CHANNEL_FROM_0)
19#define PMU_ADC_VBAT_CH_NUM 0
20#define PMU_ADC_VISENSE_CH_NUM 1
21#define PMU_ADC_VCHARGER_CH_NUM 2
22#else // #if defined(DRV_MISC_PMU_ADC_CHANNEL_FROM_0)
23#define PMU_ADC_VBAT_CH_NUM 3
24#define PMU_ADC_VISENSE_CH_NUM 4
25#define PMU_ADC_VCHARGER_CH_NUM 5
26#endif // #if defined(DRV_MISC_PMU_ADC_CHANNEL_FROM_0)
27#endif // #elif defined(PMIC_6253_REG_API)
28
29/* adc factor for VBAT/VISENSE/VCHARGER */
30#define PMU_ADC_FACTOR_VBAT 100
31#define PMU_ADC_FACTOR_VISENSE 100
32#define PMU_ADC_FACTOR_VCHARGER 250
33
34
35// Define to enable PMU6253 charger watch dog timer kick
36// When enable charger, PMU6253 will enable a watch dog timer
37// We need to kick the timer periodically, to ontify PMU6253 that BB is alive
38// If timeout, PMU6253 will disable charge automatically
39// #### If this is NOT enabled, we will disable the watch dog timer function at boot time
40// This should be defined when PMU driver need to perform WDT clear
41// BMT already support charge WDT, so this should be comment
42//#define PMU6253_ENABLE_DRIVER_CHARGE_WDT
43
44
45// Define to disable charge WDT of PMU6253
46// Define only for debug purpose
47//#define DEBUG_DISABLE_CHARGE_WDT
48
49
50
51// (0x800) VRF CON
52typedef enum{
53 VRF_ON_SEL_SRCLKENA=0,
54 VRF_ON_SEL_VRF_EN
55}pmu6253_vrf_on_sel_enum;
56
57typedef enum{
58 VD_SENSE_FROM_LOCAL_VOLTAGE=0,
59 VD_SENSE_FROM_REMOTE_VOLTAGE
60}pmu6253_vd_sense_enum;
61
62// (0x810) VTCXO CON
63typedef enum{
64 VTCXO_ON_SEL_SRCLKENA=0,
65 VTCXO_ON_SEL_VTCXO_EN
66}pmu6253_vtcxo_on_sel_enum;
67
68// (0x814) VA CON
69typedef enum{
70 VA_ON_SEL_ALWAYS_ON = 0,
71 VA_ON_SEL_SRCLKENA
72}pmu6253_va_on_sel_enum;
73
74// (0x818) VSIM CON
75typedef enum{
76 PMU6253_VSIM_1_8V = 0,
77 PMU6253_VSIM_3_0V
78}pmu6253_vsim_sel_enum;
79
80#if defined(__DRV_PMU53_SPEC_V1__)
81
82// (0x824) VBT CON ==> VBT move to 0x890
83typedef enum{
84 VBT_SEL_2_8V = 0,
85 VBT_SEL_3_0V
86}pmu6253_vbt_sel_enum;
87
88#else // #if defined(__DRV_PMU53_SPEC_V1__)
89
90// (0x890) VBT CON
91typedef enum{
92 VBT_SEL_1_5V = 0,
93 VBT_SEL_1_8V,
94 VBT_SEL_2_5V,
95 VBT_SEL_3_0V
96}pmu6253_vbt_sel_enum;
97
98#endif // #if defined(__DRV_PMU53_SPEC_V1__)
99
100// (0x828) VCAMD CON
101typedef enum{
102 VCAMD_SEL_1_3V = 0,
103 VCAMD_SEL_1_5V,
104 VCAMD_SEL_1_8V,
105 VCAMD_SEL_2_8V
106}pmu6253_vcamd_sel_enum;
107
108// (0x82C) VCAMA CON
109typedef enum{
110 VCAMA_SEL_1_5V = 0,
111 VCAMA_SEL_1_8V,
112 VCAMA_SEL_2_5V,
113 VCAMA_SEL_2_8V
114}pmu6253_vcama_sel_enum;
115
116// (0x834) GPIO CON
117typedef enum{
118 GPIO_DRV_8_MA=0,
119 GPIO_DRV_4_MA
120}pmu6253_gpio_drv_sel_enum;
121
122// (0x844) VCORE CON1
123typedef enum{
124 VCORE_MODESET_PWM = 0,
125 VCORE_MODESET_PFM
126}pmu6253_vcore_modeset_enum;
127
128typedef enum{
129 VCORE_ADC_IN_NEGATIVE_EDGE = 0,
130 VCORE_ADC_IN_POSITIVE_EDGE
131}pmu6253_vcore_adc_in_enum;
132
133typedef enum{
134 VCORE_26MHZ_DIVIDED_BY_32 = 0,
135 VCORE_26MHZ_DIVIDED_BY_16
136}pmu6253_vcore_fast_slow_enum;
137
138typedef enum{
139 VCORE_PWMB_3_BITS = 0,
140 VCORE_PWMB_4_BITS
141}pmu_6253_vcore_pwmb_enum;
142
143// (0x848) VCORE CON2
144typedef enum{
145 VCORE_VOLSEL_1_4V_TO_2_2V = 0,
146 VCORE_VOLSEL_0_8V_TO_1_6V
147}pmu6253_vcore_volsel_enum;
148
149// (0x84C) VCORE CON3
150typedef enum{
151 VCORE_VFBADJ_0_85V = 0,
152 VCORE_VFBADJ_0_90V,
153 VCORE_VFBADJ_0_95V,
154 VCORE_VFBADJ_1_00V,
155 VCORE_VFBADJ_1_05V,
156 VCORE_VFBADJ_1_10V,
157 VCORE_VFBADJ_1_15V,
158 VCORE_VFBADJ_1_20V,
159 VCORE_VFBADJ_1_25V,
160 VCORE_VFBADJ_1_30V,
161 VCORE_VFBADJ_1_35V,
162 VCORE_VFBADJ_1_40V,
163 VCORE_VFBADJ_1_45V,
164 VCORE_VFBADJ_1_50V,
165 VCORE_VFBADJ_1_55V,
166 VCORE_VFBADJ_1_60V
167}pmu6253_vcore_vfbadj_enum;
168
169typedef enum{
170 VCORE_DIRECT_CTRL_DVFS = 0,
171 VCORE_DIRECT_CTRL_DIRECT_FEED_THROUGH
172}pmu6253_vcore_direct_ctrl_enum;
173
174typedef enum{
175 VCORE_DCVCLKSEL_INTERNAL = 0,
176 VCORE_DCVCLKSEL_EXTERNAL
177}pmu6253_vcore_dcvclksel_enum;
178
179typedef enum{
180 VCORE_MODEEN_MANUAL_CHANGE_MODE = 0,
181 VCORE_MODEEN_MANUAL_AUTO_CHANGE_MODE,
182 VCORE_MODEEN_MANUAL_SW_CHANGE_MODE
183}pmu6253_vcore_modeen_enum;
184
185typedef enum{
186 VCORE_MODECMP_LOW_OFFSET = 0,
187 VCORE_MODECMP_AUTO_ZERO
188}pmu6253_vcore_modecmp_enum;
189
190typedef enum{
191 VCORE_MODESEL1A_NCD_MODE = 0,
192 VCORE_MODESEL1A_AVG_CURRENT_MODE
193}pmu6253_vcore_modesel1a_enum;
194
195typedef enum{
196 VCORE_CLK_SOURCE_FROM_CLKSQ = 0,
197 VCORE_CLK_SOURCE_FROM_TCXO26M_CK
198}pmu6253_vcore_clk_source_enum;
199
200// (0x860) STARTUP CON0
201typedef enum{
202 UV_SEL_2_90V = 0,
203 UV_SEL_2_75V,
204 UV_SEL_2_60V,
205 UL_SEL_FOLLOW_DDLO
206}pmu6253_uv_sel_enum;
207
208typedef enum{
209 PWRKEY_LOW = 0,
210 PWRKEY_HIGH
211}pmu6253_pwrkey_signal_enum;
212
213// (0x864) STARTUP CON1
214typedef enum{
215 THR_INIT_SETTING = 0,
216 THR_PLUS_10_DEGREE_C,
217 THR_MINUS_20_DEGREE_C,
218 THR_MINUS_10_DEGREE_C
219}pmu6253_thr_sel_num;
220
221// (0x870) CHR CON0
222typedef enum{
223 CHOFST_PLUS_0_STEP = 0,
224 CHOFST_PLUS_1_STEP = 1,
225 CHOFST_PLUS_2_STEP = 2,
226 CHOFST_MINUS_2_STEP = 6,
227 CHOFST_MINUS_1_STEP = 7
228}pmu6253_chofst_enum;
229
230typedef enum{
231 CHR_CURR_50_0MA = 0,
232 CHR_CURR_87_5MA,
233 CHR_CURR_150_0MA,
234 CHR_CURR_225_0MA,
235 CHR_CURR_300_0MA,
236 CHR_CURR_450_0MA,
237 CHR_CURR_650_0MA,
238 CHR_CURR_800_0MA
239}pmu6253_chr_current_enum;
240
241typedef enum{
242 CV_TUNE_1_200V = 0,
243 CV_TUNE_1_205V,
244 CV_TUNE_1_210V,
245 CV_TUNE_1_215V,
246 CV_TUNE_1_180V,
247 CV_TUNE_1_185V,
248 CV_TUNE_1_190V,
249 CV_TUNE_1_195V
250}pmu6253_cv_tune_enum;
251
252// (0x874) CHR CON1
253typedef enum{
254 CAL_PRECC_50_0MA = 0,
255 CAL_PRECC_87_5_MA,
256 CAL_PRECC_150_0MA,
257 CAL_PRECC_225_0MA
258}pmu6253_cal_precc_enum;
259
260typedef enum{
261 SYSTEM_PWR_SRC_DEFAULT = 0,
262 SYSTEM_PWR_SRC_REFER_PS_SET
263}pmu6253_ps_sel_enum;
264
265typedef enum{
266 SYSTEM_PWR_SRC_VBAT = 0,
267 SYSTEM_PWR_SRC_AC
268}pmu6253_ps_set_enum;
269
270typedef enum{
271 CHR_OV_5_5V = 0,
272 CHR_OV_6_0V,
273 CHR_OV_6_5V,
274 CHR_OV_7_0V
275}pmu6253_chr_ov_enum;
276
277// (0x87C) CHR CON3
278typedef enum{
279 CHR_WDT_4_SEC = 0,
280 CHR_WDT_8_SEC,
281 CHR_WDT_16_SEC,
282 CHR_WDT_32_SEC
283}pmu6253_chr_wdt_td_enum;
284
285// (0x880) DRIVER CON0
286typedef enum{
287 KPLED_WLED = 0,
288 KPLED_RLED
289}pmu6253_kpled_type_enum;
290
291
292typedef enum{
293 LED_1_SET = 1,
294 LED_4_WLED_4_RLED = 3,
295 LED_4_WLED_8_RLED = 7
296}pmu6253_kpled_sel_enum;
297
298typedef enum{
299 ISINK1_TURN_ON = 1, // Bit 0
300 ISINK2_TURN_ON = 2, // Bit 1
301 ISINK3_TURN_ON = 4, // Bit 2
302 ISINK4_TURN_ON = 8, // Bit 3
303 ISINKALL_TURN_ON = 0xF // 0xF (Bit[3..0])
304}pmu6253_isinks_chsel_enum;
305
306// (0x888) DRIVER CON2
307typedef enum{
308 ISINKS_VLED_STEP_5_MA = 0,
309 ISINKS_VLED_STEP_10_MA,
310 ISINKS_VLED_STEP_15_MA,
311 ISINKS_VLED_STEP_20_MA
312}pmu6253_isinks_vled_enum;
313
314#if defined(__DRV_PMU53_SPEC_V1__)
315
316// (0x890) DRIVER CON4
317typedef enum{
318 VIBR_SEL_1_5V = 0,
319 VIBR_SEL_1_8V,
320 VIBR_SEL_2_5V,
321 VIBR_SEL_3_0V
322}pmu6253_vibr_sel_enum;
323
324#else // #if defined(__DRV_PMU53_SPEC_V1__)
325
326// (0x824) DRIVER CON4
327typedef enum{
328 VIBR_SEL_2_8V = 0,
329 VIBR_SEL_3_0V
330}pmu6253_vibr_sel_enum;
331
332#endif // #if defined(__DRV_PMU53_SPEC_V1__)
333
334typedef enum{
335 VBOOST_SS_SPEED_NORMAL = 0,
336 VBOOST_SS_SPEED_2_OVER_3
337}pmu6253_vboost_ss_speed_enum;
338
339// (0x8B0) CLASSD CON0
340typedef enum{
341 SPK_EMODE_NO_EXTENSION = 1,
342 SPK_EMODE_LEAD_EXTENSION,
343 SPK_EMODE_LAG_EXTENSION
344}pmu6253_spk_emode_enum;
345
346typedef enum{
347 PMU6253_SPK_CLASS_D_MODE = 0,
348 PMU6253_SPK_CLASS_AB_MODE
349}pmu6253_spk_mode_enum;
350
351typedef enum{
352 SPK_AB_BIAS_3_225MA = 0,
353 SPK_AB_BIAS_6_381MA,
354 SPK_AB_BIAS_9_533MA,
355 SPK_AB_BIAS_12_684MA
356}pmu6253_spkab_obias_enum;
357
358// (0x8B8) CLASSD CON2
359typedef enum{
360 SPK_DMODE_FB_FORCED = 0,
361 SPK_DMODE_FB_AUTO,
362 SPK_DMODE_FF_FORCED,
363 SPK_DMODE_FF_AUTO
364}pmu6253_spk_dmode_enum;
365
366typedef enum{
367 SPK_PCHG_103_0NS = 0,
368 SPK_PCHG_55_67NS,
369 SPK_PCHG_39_09NS,
370 SPK_PCHG_30_47NS
371}pmu6253_spk_pchg_enum;
372
373typedef enum{
374 SPK_SPK_CCODE = 1,
375 SPK_TRIANGLE_WAVE = 2,
376 SPK_PRNG_WAVE = 3
377}pmu6253_spk_freq_ctrl_enum;
378
379typedef enum{
380 SPK_SLEW_2_OVER_4 = 0,
381 SPK_SLEW_1_OVER_4,
382 SPK_SLEW_4_OVER_4,
383 SPK_SLEW_3_OVER_4
384}pmu6253_spk_slew_enum;
385
386// (0x8D0) OC CON0
387typedef enum{
388 OC_GEAR_100_US = 0,
389 OC_GEAR_200_US,
390 OC_GEAR_400_US,
391 OC_GEAR_800_US
392}pmu6253_gear_enum;
393
394// (0x8E0) OC CON4
395typedef enum{
396 SS_DELAY_200US = 0,
397 SS_DELAY_400US,
398 SS_DELAY_600US,
399 SS_DELAY_800US
400}pmu6253_soft_start_delay;
401
402
403// (0x8E4) OC CON5
404typedef enum{
405 SPK_OC_FLAG = 0x0001,
406 VIBR_OC_FLAG = 0x0002,
407 VBOOST_OC_FLAG = 0x0004,
408 VSIM_OC_FLAG = 0x0008,
409 VBT_OC_FLAG = 0x0010,
410 VUSB_OC_FLAG = 0x0020,
411 VCAMD_OC_FLAG = 0x0040,
412 VCAMA_OC_FLAG = 0x0080,
413 VTCXO_OC_FLAG = 0x0800,
414 VRF_OC_FLAG = 0x1000,
415 VIO_OC_FLAG = 0x2000,
416 VM_OC_FLAG = 0x4000,
417 VA_OC_FLAG = 0x8000
418}pmu6253_oc_bit_enum;
419
420
421// =====================================================================================
422// (0x800) VRF CON
423extern void dcl_pmu6253_vrf_enable(kal_bool enable);
424extern void dcl_pmu6253_vrf_cal(kal_uint8 val);
425extern void dcl_pmu6253_vrf_on_sel(pmu6253_vrf_on_sel_enum sel);
426extern void dcl_pmu6253_vrf_ocfb_enable(kal_bool enable);
427extern kal_bool dcl_pmu6253_vrf_status(void);
428
429// (0x804) VIO CON
430extern void dcl_pmu6253_vio_cal(kal_uint8 val);
431extern void dcl_pmu6253_vio_vd_sense(pmu6253_vd_sense_enum sel);
432extern void dcl_pmu6253_vio_ocfb_enable(kal_bool enable);
433extern kal_bool dcl_pmu6253_vio_status(void);
434
435// (0x808) VM CON
436extern void dcl_pmu6253_vm_cal(kal_uint8 val);
437extern void dcl_pmu6253_vm_vd_sense(pmu6253_vd_sense_enum sel);
438extern void dcl_pmu6253_vm_ocfb_enable(kal_bool enable);
439extern kal_bool dcl_pmu6253_vm_status(void);
440
441// (0x80C) VRTC CON
442extern void dcl_pmu6253_vrtc_cal(kal_uint8 val);
443extern kal_bool dcl_pmu6253_vrtc_status(void);
444
445// (0x810) VTCXO CON
446extern void dcl_pmu6253_vtcxo_enable(kal_bool enable);
447extern void dcl_pmu6253_vtcxo_cal(kal_uint8 val);
448extern void dcl_pmu6253_vtcxo_on_sel(pmu6253_vtcxo_on_sel_enum sel);
449extern void dcl_pmu6253_vtcxo_srclken(kal_bool enable);
450extern void dcl_pmu6253_vtcxo_ocfb_enable(kal_bool enable);
451extern kal_bool dcl_pmu6253_vtcxo_status(void);
452
453// (0x814) VA CON
454extern void dcl_pmu6253_va_cal(kal_uint8 val);
455extern void dcl_pmu6253_va_vd_sense(pmu6253_vd_sense_enum sel);
456extern void dcl_pmu6253_va_on_sel(pmu6253_va_on_sel_enum sel);
457extern void dcl_pmu6253_va_ocfb_enable(kal_bool enable);
458extern kal_bool dcl_pmu6253_va_status(void);
459
460// (0x818) VSIM CON
461extern void dcl_pmu6253_vsim_enable(kal_bool enable);
462extern void dcl_pmu6253_vsim_cal(kal_uint8 val);
463extern void dcl_pmu6253_vsim_datal(kal_bool pull_low);
464extern void dcl_pmu6253_vsim_sel(pmu6253_vsim_sel_enum sel);
465extern void dcl_pmu6253_vsim_pwr_saving(kal_bool enable);
466extern void dcl_pmu6253_vsim_ocfb_enable(kal_bool enable);
467extern kal_bool dcl_pmu6253_vsim_status(void);
468
469// (0x81C) VSIM2 CON
470extern void dcl_pmu6253_vsim2_enable(kal_bool enable);
471extern void dcl_pmu6253_vsim2_cal(kal_uint8 val);
472extern void dcl_pmu6253_vsim2_datal(kal_bool pull_low);
473extern void dcl_pmu6253_vsim2_sel(pmu6253_vsim_sel_enum sel);
474extern kal_bool dcl_pmu6253_vsim2_status(void);
475
476// (0x820) VUSB CON
477extern void dcl_pmu6253_vusb_enable(kal_bool enable);
478extern void dcl_pmu6253_vusb_cal(kal_uint8 val);
479extern void dcl_pmu6253_vusb_ocfb_enable(kal_bool enable);
480extern kal_bool dcl_pmu6253_vusb_status(void);
481
482// (0x824) VBT CON
483extern void dcl_pmu6253_vbt_enable(kal_bool enable);
484extern void dcl_pmu6253_vbt_cal(kal_uint8 val);
485extern void dcl_pmu6253_vbt_sel(pmu6253_vbt_sel_enum sel);
486extern void dcl_pmu6253_vbt_ocfb_enable(kal_bool enable);
487extern kal_bool dcl_pmu6253_vbt_status(void);
488
489// (0x828) VCAMD CON
490extern void dcl_pmu6253_vcamd_enable(kal_bool enable);
491extern void dcl_pmu6253_vcamd_cal(kal_uint8 val);
492extern void dcl_pmu6253_vcamd_sel(pmu6253_vcamd_sel_enum sel);
493extern void dcl_pmu6253_vcamd_ocfb_enable(kal_bool enable);
494extern kal_bool dcl_pmu6253_vcamd_status(void);
495
496// (0x82C) VCAMA CON
497extern void dcl_pmu6253_vcama_enable(kal_bool enable);
498extern void dcl_pmu6253_vcama_cal(kal_uint8 val);
499extern void dcl_pmu6253_vcama_sel(pmu6253_vcama_sel_enum sel);
500extern void dcl_pmu6253_vcama_ocfb_enable(kal_bool enable);
501extern kal_bool dcl_pmu6253_vcama_status(void);
502
503// (0x834) GPIO CON
504extern void dcl_pmu6253_gpio_drv(pmu6253_gpio_drv_sel_enum sel);
505extern void dcl_pmu6253_mtv_enable(kal_bool enable);
506
507// (0x840) VCORE CON
508extern void dcl_pmu6253_vcore_en_force(kal_bool enable);
509extern void dcl_pmu6253_vcore_cal(kal_uint8 val);
510extern void dcl_pmu6253_vcore_vd_sense(pmu6253_vd_sense_enum sel);
511extern kal_bool dcl_pmu6253_vcore_status(void);
512
513// (0x844) VCORE CON1
514extern void dcl_pmu6253_vcore_modeset(pmu6253_vcore_modeset_enum mode);
515extern void dcl_pmu6253_vcore_adc_in_edge(pmu6253_vcore_adc_in_enum edge);
516extern void dcl_pmu6253_vcore_fast_slow(pmu6253_vcore_fast_slow_enum sel);
517extern void dcl_pmu6253_vcore_pwmb(pmu_6253_vcore_pwmb_enum sel);
518extern void dcl_pmu6253_vcore_acc_out_init(kal_uint8 val);
519
520// (0x848) VCORE CON2
521extern void dcl_pmu6253_vcore_volsel(pmu6253_vcore_volsel_enum sel);
522extern void dcl_pmu6253_vcore_fben(kal_bool enable);
523
524// (0x84C) VCORE CON3
525extern void dcl_pmu6253_vcore_vfbadj(pmu6253_vcore_vfbadj_enum sel);
526extern void dcl_pmu6253_vcore_direct_ctrl_en(pmu6253_vcore_direct_ctrl_enum sel);
527extern void dcl_pmu6253_vcore_dcvclksel(pmu6253_vcore_dcvclksel_enum sel);
528extern void dcl_pmu6253_vcore_modeen(pmu6253_vcore_modeen_enum sel);
529extern void dcl_pmu6253_vcore_modecmp(pmu6253_vcore_modecmp_enum sel);
530extern void dcl_pmu6253_vcore_modesel1A(pmu6253_vcore_modesel1a_enum sel);
531
532// (0x854) VCORE CON5
533extern void dcl_pmu6253_vcore_vfbadj_slp(pmu6253_vcore_vfbadj_enum sel);
534extern void dcl_pmu6253_vcore_clk_source_sel(pmu6253_vcore_clk_source_enum sel);
535
536// (0x860) STARTUP CON0
537extern void dcl_pmu6253_uv_sel(pmu6253_uv_sel_enum sel);
538extern void dcl_pmu6253_pwrkey_vcore(pmu6253_pwrkey_signal_enum sel);
539extern void dcl_pmu6253_pwrkey_deb(pmu6253_pwrkey_signal_enum sel);
540
541// (0x864) STARTUP CON1
542extern void dcl_pmu6253_thr_sel(pmu6253_thr_sel_num sel);
543
544// (0x870) CHR CON0
545extern void dcl_pmu6253_chr_enable(kal_bool enable);
546extern void dcl_pmu6253_chofst(pmu6253_chofst_enum sel);
547extern void dcl_pmu6253_chr_current(pmu6253_chr_current_enum sel);
548extern pmu6253_chr_current_enum pmu6253_chr_get_current(void);
549extern void dcl_pmu6253_chr_force_enable(kal_bool enable);
550extern void dcl_pmu6253_cv_rt(kal_uint8 val);
551extern void dcl_pmu6253_cv_tune(pmu6253_cv_tune_enum sel);
552
553// (0x874) CHR CON1
554extern void dcl_pmu6253_cal_precc(pmu6253_cal_precc_enum sel);
555extern void dcl_pmu6253_ps_sel(pmu6253_ps_sel_enum sel);
556extern void dcl_pmu6253_ps_set(pmu6253_ps_set_enum sel);
557extern void dcl_pmu6253_chr_ov_sel(pmu6253_chr_ov_enum sel);
558
559// (0x878) CHR CON2
560extern kal_bool dcl_pmu6253_chrdet(void);
561extern kal_bool dcl_pmu6253_ovp(void);
562extern kal_bool dcl_pmu6253_bat_on(void);
563extern kal_bool dcl_pmu6253_bad_bat(void);
564extern kal_bool dcl_pmu6253_cv_mode(void);
565
566// (0x87C) CHR CON3
567extern void dcl_pmu6253_chr_wdt_td(pmu6253_chr_wdt_td_enum sel);
568extern void dcl_pmu6253_chr_wdt_enable(kal_bool enable);
569
570// (0x8F0) CHR CON4
571extern void dcl_pmu6253_chr_wdt_intr_enable(kal_bool enable);
572extern kal_bool dcl_pmu6253_chr_wdt_status(void);
573extern void dcl_pmu6253_chr_wdt_clear(void);
574
575// (0x8F4) CHR CON5
576//extern void dcl_pmu6253_chr_wdt_cnt(kal_uint32 val32);
577
578// (0x880) DRIVER CON0
579extern void dcl_pmu6253_isinks_enable(kal_bool enable);
580extern void dcl_pmu6253_isinks_force_off(kal_bool off);
581extern void dcl_pmu6253_kpled_type(pmu6253_kpled_type_enum sel);
582extern void dcl_pmu6253_kpled_enable(kal_bool enable);
583extern void dcl_pmu6253_kpled_force_off(kal_bool off);
584extern void dcl_pmu6253_kpled_sel(pmu6253_kpled_sel_enum sel);
585extern kal_bool dcl_pmu6253_isink1_status(void);
586extern kal_bool dcl_pmu6253_isink2_status(void);
587extern kal_bool dcl_pmu6253_isink3_status(void);
588extern kal_bool dcl_pmu6253_isink4_status(void);
589extern kal_bool dcl_pmu6253_kpled_status(void);
590
591// (0x884) DRIVER CON1
592extern void dcl_pmu6253_isinks_dimm(kal_uint8 sel);
593extern void dcl_pmu6253_isinks_chsel(pmu6253_isinks_chsel_enum sel);
594
595// (0x888) DRIVER CON2
596extern void dcl_pmu6253_sinks_irset_cal(kal_uint8 val);
597extern void dcl_pmu6253_isinks_vled_step(pmu6253_isinks_vled_enum sel);
598
599// (0x88C) DRIVER CON3
600extern void dcl_pmu6253_bl_enable(kal_bool enable);
601extern void dcl_pmu6253_vboost_enable(kal_bool enable);
602extern void dcl_pmu6253_bl_vgen_forceon(kal_bool on);
603extern void dcl_pmu6253_bl_mode(kal_uint8 val);
604extern void dcl_pmu6253_dimm_duty(kal_uint8 val);
605
606// (0x890) DRIVER CON4
607extern void dcl_pmu6253_vibr_enable(kal_bool enable);
608extern void dcl_pmu6253_vibr_sel(pmu6253_vibr_sel_enum sel);
609extern void dcl_pmu6253_vibr_cal(kal_uint8 val);
610extern void dcl_pmu6253_vibr_ocfb_enable(kal_bool enable);
611extern kal_bool dcl_pmu6253_vibr_status(void);
612
613// (0x8A0) BOOST CON0
614extern void dcl_pmu6253_vboost_sync_enable(kal_bool enable);
615extern void dcl_pmu6253_vboost_ss_speed(pmu6253_vboost_ss_speed_enum sel);
616extern void dcl_pmu6253_vboost_tune(kal_uint8 val);
617extern void dcl_pmu6253_vboost_cal(kal_uint8 val);
618extern kal_bool dcl_pmu6253_vboost_trk_status(void);
619extern kal_bool dcl_pmu6253_vboost_status(void);
620
621// (0x8A4) BOOST CON1
622extern void dcl_pmu6253_isns_cal(kal_uint8 val);
623
624// (0x8A8) BOOST CON2
625extern void dcl_pmu6253_vboost_forceon_clk(kal_bool forceon);
626extern void dcl_pmu6253_vboost_disclk(kal_bool forceoff);
627
628// (0x8B0) CLASSD CON0
629extern void dcl_pmu6253_spk_enable(kal_bool enable);
630extern void dcl_pmu6253_spk_reset(kal_bool reset);
631extern void dcl_pmu6253_spk_emode(pmu6253_spk_emode_enum sel);
632extern void dcl_pmu6253_spk_mode(pmu6253_spk_mode_enum sel);
633extern void dcl_pmu6253_spkab_float(kal_bool enable);
634extern void dcl_pmu6253_spkab_sended(kal_bool enable);
635extern void dcl_pmu6253_spkab_oc_enable(kal_bool enable);
636extern void dcl_pmu6253_spkab_depop_enable(kal_bool enable);
637extern void dcl_pmu6253_spkab_obias(pmu6253_spkab_obias_enum sel);
638
639// (0x8B4) CLASSD CON1
640extern void dcl_pmu6253_spk_dtin(kal_uint8 val);
641extern void dcl_pmu6253_spk_dtip(kal_uint8 val);
642extern void dcl_pmu6253_spk_dtcn(kal_uint8 val);
643extern void dcl_pmu6253_spk_dtcp(kal_uint8 val);
644
645// (0x8B8) CLASSD CON2
646extern void dcl_pmu6253_spk_dmode(pmu6253_spk_dmode_enum sel);
647extern void dcl_pmu6253_spk_pchg(pmu6253_spk_pchg_enum sel);
648extern void dcl_pmu6253_spk_dtcal(kal_bool enable);
649extern void dcl_pmu6253_spk_pmode_enable(kal_bool enable);
650extern void dcl_pmu6253_spk_cmode(pmu6253_spk_freq_ctrl_enum sel);
651extern void dcl_pmu6253_spk_ccode(kal_uint8 val);
652
653// (0x8BC) CLASSD CON3
654extern void dcl_pmu6253_spk_enable_view_clk(kal_bool enable);
655extern void dcl_pmu6253_spk_enable_view_vref(kal_bool enable);
656extern void dcl_pmu6253_spk_slew(pmu6253_spk_slew_enum sel);
657extern void dcl_pmu6253_spk_oc_enable(kal_bool enable);
658extern void dcl_pmu6253_spk_oscisel_half(kal_bool half);
659extern void dcl_pmu6253_spk_vol(kal_uint8 val);
660extern kal_uint8 pmu6253_spk_get_vol(void);
661
662// (0x8C8) TEST CON2
663extern void dcl_pmu6253_adc_vol_divided_by_2(kal_bool enable);
664extern void dcl_pmu6253_adc_meas_on(kal_bool enable);
665
666// (0x8D0) OC CON0
667extern void dcl_pmu6253_vrf_oc_gear(pmu6253_gear_enum sel);
668extern void dcl_pmu6253_vrf_oc_auto_off(kal_bool enable);
669extern void dcl_pmu6253_vrf_oc_int_enable(kal_bool enable);
670extern void dcl_pmu6253_vio_oc_gear(pmu6253_gear_enum sel);
671extern void dcl_pmu6253_vio_oc_auto_off(kal_bool enable);
672extern void dcl_pmu6253_vio_oc_int_enable(kal_bool enable);
673extern void dcl_pmu6253_vm_oc_gear(pmu6253_gear_enum sel);
674extern void dcl_pmu6253_vm_oc_auto_off(kal_bool enable);
675extern void dcl_pmu6253_vm_oc_int_enable(kal_bool enable);
676extern void dcl_pmu6253_va_oc_gear(pmu6253_gear_enum sel);
677extern void dcl_pmu6253_va_oc_auto_off(kal_bool enable);
678extern void dcl_pmu6253_va_oc_int_enable(kal_bool enable);
679
680// (0x8D4) OC CON1
681extern void dcl_pmu6253_vtcxo_oc_gear(pmu6253_gear_enum sel);
682extern void dcl_pmu6253_vtcxo_oc_auto_off(kal_bool enable);
683extern void dcl_pmu6253_vtcxo_oc_int_enable(kal_bool enable);
684
685// (0x8D8) OC CON2
686extern void dcl_pmu6253_vbt_oc_gear(pmu6253_gear_enum sel);
687extern void dcl_pmu6253_vbt_oc_auto_off(kal_bool enable);
688extern void dcl_pmu6253_vbt_oc_int_enable(kal_bool enable);
689extern void dcl_pmu6253_vusb_oc_gear(pmu6253_gear_enum sel);
690extern void dcl_pmu6253_vusb_oc_auto_off(kal_bool enable);
691extern void dcl_pmu6253_vusb_oc_int_enable(kal_bool enable);
692extern void dcl_pmu6253_vcamd_oc_gear(pmu6253_gear_enum sel);
693extern void dcl_pmu6253_vcamd_oc_auto_off(kal_bool enable);
694extern void dcl_pmu6253_vcamd_oc_int_enable(kal_bool enable);
695extern void dcl_pmu6253_vcama_oc_gear(pmu6253_gear_enum sel);
696extern void dcl_pmu6253_vcama_oc_auto_off(kal_bool enable);
697extern void dcl_pmu6253_vcama_oc_int_enable(kal_bool enable);
698
699// (0x8DC) OC CON3
700extern void dcl_pmu6253_spk_oc_gear(pmu6253_gear_enum sel);
701extern void dcl_pmu6253_spk_oc_auto_off(kal_bool enable);
702extern void dcl_pmu6253_spk_oc_int_enable(kal_bool enable);
703extern void dcl_pmu6253_vibr_oc_gear(pmu6253_gear_enum sel);
704extern void dcl_pmu6253_vibr_oc_auto_off(kal_bool enable);
705extern void dcl_pmu6253_vibr_oc_int_enable(kal_bool enable);
706extern void dcl_pmu6253_vboost_oc_gear(pmu6253_gear_enum sel);
707extern void dcl_pmu6253_vboost_oc_auto_off(kal_bool enable);
708extern void dcl_pmu6253_vboost_oc_int_enable(kal_bool enable);
709extern void dcl_pmu6253_vsim_oc_gear(pmu6253_gear_enum sel);
710extern void dcl_pmu6253_vsim_oc_auto_off(kal_bool enable);
711extern void dcl_pmu6253_vsim_oc_int_enable(kal_bool enable);
712
713// (0x8E0) OC CON4
714extern void dcl_pmu6253_vibr_stbtd(pmu6253_soft_start_delay sel);
715extern void dcl_pmu6253_vsim_stbtd(pmu6253_soft_start_delay sel);
716extern void dcl_pmu6253_vbt_stbtd(pmu6253_soft_start_delay sel);
717extern void dcl_pmu6253_vusb_stbtd(pmu6253_soft_start_delay sel);
718extern void dcl_pmu6253_vcamd_stbtd(pmu6253_soft_start_delay sel);
719extern void dcl_pmu6253_vcama_stbtd(pmu6253_soft_start_delay sel);
720
721// (0x8E4) OC CON5
722extern kal_bool dcl_pmu6253_oc_flag(pmu6253_oc_bit_enum sel);
723extern void dcl_pmu6253_clear_oc_flag(pmu6253_oc_bit_enum sel);
724extern void dcl_pmu6253_clear_all_oc_flag(void);
725
726
727// ====== Other exported APIs =============
728extern pmu6253_chr_current_enum pmu6253_ret_chr_current(void);
729extern pmu6253_chr_current_enum pmu6253_ret_usb_current(void);
730extern void dcl_pmu6253_init(void);
731
732
733
734/*
735typedef enum
736{
737 PMU_FAKE_LDO_BUCK_MAX
738}PMU_FAKE_LDO_BUCK_LIST_ENUM;
739
740typedef enum
741{
742 VRF,
743 VIO,
744 VM,
745 VRTC,
746 VTCXO,
747 VA,
748 VSIM,
749 VSIM2,
750 VUSB,
751 VBT,
752 VCAMA,
753 VCAMD,
754 VCORE,
755 VIBR,
756 PMU_LDO_BUCK_MAX,
757 VRF18,
758 VFM,
759 VMC
760}PMU_LDO_BUCK_LIST_ENUM;
761
762typedef enum
763{
764 VPA1,
765 PMU_VPA_MAX
766}PMU_VPA_LIST_ENUM;
767
768typedef enum
769{
770 CHR,
771 PMU_CHR_MAX
772}PMU_CHR_LIST_ENUM;
773
774typedef enum
775{
776 SPK,
777 SPKL,
778 SPKR,
779 PMU_SPK_MAX
780}PMU_SPK_LIST_ENUM;
781
782typedef enum
783{
784 PMU_ISINK_MAX
785}PMU_ISINK_LIST_ENUM;
786
787typedef enum
788{
789 PMU_BOOST_MAX
790}PMU_BOOST_LIST_ENUM;
791*/
792
793
794#endif // #ifdef PMIC_6253_REG_API
795#endif // #ifndef __DCL_PMU6253_SW_H_STRUCT__
796
797
798